1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
21 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
27 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
28 InstrItinClass arg_ri> {
29 InstrItinClass rr = arg_rr;
30 InstrItinClass rm = arg_rm;
31 InstrItinClass ri = arg_ri;
36 def SSE_ALU_F32S : OpndItins<
37 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
40 def SSE_ALU_F64S : OpndItins<
41 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
44 def SSE_ALU_ITINS_S : SizeItins<
45 SSE_ALU_F32S, SSE_ALU_F64S
48 def SSE_MUL_F32S : OpndItins<
49 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
52 def SSE_MUL_F64S : OpndItins<
53 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
56 def SSE_MUL_ITINS_S : SizeItins<
57 SSE_MUL_F32S, SSE_MUL_F64S
60 def SSE_DIV_F32S : OpndItins<
61 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
64 def SSE_DIV_F64S : OpndItins<
65 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
68 def SSE_DIV_ITINS_S : SizeItins<
69 SSE_DIV_F32S, SSE_DIV_F64S
73 def SSE_ALU_F32P : OpndItins<
74 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
77 def SSE_ALU_F64P : OpndItins<
78 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
81 def SSE_ALU_ITINS_P : SizeItins<
82 SSE_ALU_F32P, SSE_ALU_F64P
85 def SSE_MUL_F32P : OpndItins<
86 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
89 def SSE_MUL_F64P : OpndItins<
90 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
93 def SSE_MUL_ITINS_P : SizeItins<
94 SSE_MUL_F32P, SSE_MUL_F64P
97 def SSE_DIV_F32P : OpndItins<
98 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
101 def SSE_DIV_F64P : OpndItins<
102 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
105 def SSE_DIV_ITINS_P : SizeItins<
106 SSE_DIV_F32P, SSE_DIV_F64P
109 def SSE_BIT_ITINS_P : OpndItins<
110 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
113 def SSE_INTALU_ITINS_P : OpndItins<
114 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
117 def SSE_INTALUQ_ITINS_P : OpndItins<
118 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
121 def SSE_INTMUL_ITINS_P : OpndItins<
122 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
125 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
126 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
129 def SSE_MOVA_ITINS : OpndItins<
130 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
133 def SSE_MOVU_ITINS : OpndItins<
134 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
137 //===----------------------------------------------------------------------===//
138 // SSE 1 & 2 Instructions Classes
139 //===----------------------------------------------------------------------===//
141 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
142 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
143 RegisterClass RC, X86MemOperand x86memop,
146 let isCommutable = 1 in {
147 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
149 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
150 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
151 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>;
153 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
155 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
156 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
157 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>;
160 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
161 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
162 string asm, string SSEVer, string FPSizeStr,
163 Operand memopr, ComplexPattern mem_cpat,
166 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
168 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
169 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
170 [(set RC:$dst, (!cast<Intrinsic>(
171 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
172 RC:$src1, RC:$src2))], itins.rr>;
173 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
175 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
176 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
177 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
178 SSEVer, "_", OpcodeStr, FPSizeStr))
179 RC:$src1, mem_cpat:$src2))], itins.rm>;
182 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
183 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
184 RegisterClass RC, ValueType vt,
185 X86MemOperand x86memop, PatFrag mem_frag,
186 Domain d, OpndItins itins, bit Is2Addr = 1> {
187 let isCommutable = 1 in
188 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
190 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
191 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
192 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>;
194 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
196 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
197 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
198 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
202 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
203 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
204 string OpcodeStr, X86MemOperand x86memop,
205 list<dag> pat_rr, list<dag> pat_rm,
207 let isCommutable = 1, hasSideEffects = 0 in
208 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
210 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
211 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
212 pat_rr, IIC_DEFAULT, d>;
213 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
215 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
216 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
217 pat_rm, IIC_DEFAULT, d>;
220 //===----------------------------------------------------------------------===//
221 // Non-instruction patterns
222 //===----------------------------------------------------------------------===//
224 // A vector extract of the first f32/f64 position is a subregister copy
225 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
226 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
227 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
228 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
230 // A 128-bit subvector extract from the first 256-bit vector position
231 // is a subregister copy that needs no instruction.
232 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
233 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
234 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
235 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
237 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
238 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
239 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
240 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
242 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
243 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
244 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
245 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
247 // A 128-bit subvector insert to the first 256-bit vector position
248 // is a subregister copy that needs no instruction.
249 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
250 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
251 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
252 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
253 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
254 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
255 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
256 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
257 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
258 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
259 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
260 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
261 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
264 // Implicitly promote a 32-bit scalar to a vector.
265 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
266 (COPY_TO_REGCLASS FR32:$src, VR128)>;
267 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
268 (COPY_TO_REGCLASS FR32:$src, VR128)>;
269 // Implicitly promote a 64-bit scalar to a vector.
270 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
271 (COPY_TO_REGCLASS FR64:$src, VR128)>;
272 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
273 (COPY_TO_REGCLASS FR64:$src, VR128)>;
275 // Bitcasts between 128-bit vector types. Return the original type since
276 // no instruction is needed for the conversion
277 let Predicates = [HasSSE2] in {
278 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
279 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
280 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
281 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
282 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
283 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
284 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
285 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
286 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
287 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
288 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
289 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
290 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
291 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
292 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
293 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
294 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
295 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
296 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
297 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
298 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
299 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
300 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
301 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
302 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
303 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
304 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
305 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
306 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
307 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
310 // Bitcasts between 256-bit vector types. Return the original type since
311 // no instruction is needed for the conversion
312 let Predicates = [HasAVX] in {
313 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
314 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
315 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
316 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
317 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
318 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
319 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
320 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
321 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
322 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
323 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
324 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
325 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
326 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
327 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
328 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
329 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
330 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
331 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
332 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
333 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
334 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
335 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
336 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
337 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
338 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
339 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
340 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
341 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
342 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
345 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
346 // This is expanded by ExpandPostRAPseudos.
347 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
349 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
350 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
351 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
352 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
355 //===----------------------------------------------------------------------===//
356 // AVX & SSE - Zero/One Vectors
357 //===----------------------------------------------------------------------===//
359 // Alias instruction that maps zero vector to pxor / xorp* for sse.
360 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
361 // swizzled by ExecutionDepsFix to pxor.
362 // We set canFoldAsLoad because this can be converted to a constant-pool
363 // load of an all-zeros value if folding it would be beneficial.
364 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
366 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
367 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
370 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
371 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
372 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
373 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
374 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
377 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
378 // and doesn't need it because on sandy bridge the register is set to zero
379 // at the rename stage without using any execution unit, so SET0PSY
380 // and SET0PDY can be used for vector int instructions without penalty
381 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
382 isPseudo = 1, Predicates = [HasAVX] in {
383 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
384 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
387 let Predicates = [HasAVX] in
388 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
390 let Predicates = [HasAVX2] in {
391 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
392 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
393 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
394 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
397 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
398 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
399 let Predicates = [HasAVX1Only] in {
400 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
401 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
402 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
404 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
405 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
406 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
408 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
409 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
410 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
412 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
413 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
414 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
417 // We set canFoldAsLoad because this can be converted to a constant-pool
418 // load of an all-ones value if folding it would be beneficial.
419 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
421 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
422 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
423 let Predicates = [HasAVX2] in
424 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
425 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
429 //===----------------------------------------------------------------------===//
430 // SSE 1 & 2 - Move FP Scalar Instructions
432 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
433 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
434 // is used instead. Register-to-register movss/movsd is not modeled as an
435 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
436 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
437 //===----------------------------------------------------------------------===//
439 class sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt, string asm> :
440 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
441 [(set VR128:$dst, (vt (OpNode VR128:$src1,
442 (scalar_to_vector RC:$src2))))],
445 // Loading from memory automatically zeroing upper bits.
446 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
447 PatFrag mem_pat, string OpcodeStr> :
448 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
449 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
450 [(set RC:$dst, (mem_pat addr:$src))],
454 def VMOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
455 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
457 def VMOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
458 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
461 // For the disassembler
462 let isCodeGenOnly = 1, hasSideEffects = 0 in {
463 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
464 (ins VR128:$src1, FR32:$src2),
465 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
468 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
469 (ins VR128:$src1, FR64:$src2),
470 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
475 let canFoldAsLoad = 1, isReMaterializable = 1 in {
476 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
478 let AddedComplexity = 20 in
479 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
483 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
484 "movss\t{$src, $dst|$dst, $src}",
485 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
487 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
488 "movsd\t{$src, $dst|$dst, $src}",
489 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
493 let Constraints = "$src1 = $dst" in {
494 def MOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
495 "movss\t{$src2, $dst|$dst, $src2}">, XS;
496 def MOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
497 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
499 // For the disassembler
500 let isCodeGenOnly = 1, hasSideEffects = 0 in {
501 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
502 (ins VR128:$src1, FR32:$src2),
503 "movss\t{$src2, $dst|$dst, $src2}", [],
504 IIC_SSE_MOV_S_RR>, XS;
505 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
506 (ins VR128:$src1, FR64:$src2),
507 "movsd\t{$src2, $dst|$dst, $src2}", [],
508 IIC_SSE_MOV_S_RR>, XD;
512 let canFoldAsLoad = 1, isReMaterializable = 1 in {
513 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
515 let AddedComplexity = 20 in
516 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
519 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
520 "movss\t{$src, $dst|$dst, $src}",
521 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
522 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
523 "movsd\t{$src, $dst|$dst, $src}",
524 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
527 let Predicates = [HasAVX] in {
528 let AddedComplexity = 15 in {
529 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
530 // MOVS{S,D} to the lower bits.
531 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
532 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
533 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
534 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
535 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
536 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
537 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
538 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
540 // Move low f32 and clear high bits.
541 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
542 (SUBREG_TO_REG (i32 0),
543 (VMOVSSrr (v4f32 (V_SET0)),
544 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
545 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
546 (SUBREG_TO_REG (i32 0),
547 (VMOVSSrr (v4i32 (V_SET0)),
548 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
551 let AddedComplexity = 20 in {
552 // MOVSSrm zeros the high parts of the register; represent this
553 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
554 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
555 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
556 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
557 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
558 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
559 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
561 // MOVSDrm zeros the high parts of the register; represent this
562 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
563 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
564 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
565 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
566 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
567 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
568 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
569 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
570 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
571 def : Pat<(v2f64 (X86vzload addr:$src)),
572 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
574 // Represent the same patterns above but in the form they appear for
576 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
577 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
578 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
579 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
580 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
581 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
582 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
583 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
584 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
586 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
587 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
588 (SUBREG_TO_REG (i32 0),
589 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
591 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
592 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
593 (SUBREG_TO_REG (i64 0),
594 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
596 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
597 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
598 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
600 // Move low f64 and clear high bits.
601 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
602 (SUBREG_TO_REG (i32 0),
603 (VMOVSDrr (v2f64 (V_SET0)),
604 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
606 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
607 (SUBREG_TO_REG (i32 0),
608 (VMOVSDrr (v2i64 (V_SET0)),
609 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
611 // Extract and store.
612 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
614 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
615 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
617 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
619 // Shuffle with VMOVSS
620 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
621 (VMOVSSrr (v4i32 VR128:$src1),
622 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
623 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
624 (VMOVSSrr (v4f32 VR128:$src1),
625 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
628 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
629 (SUBREG_TO_REG (i32 0),
630 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
631 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
633 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
634 (SUBREG_TO_REG (i32 0),
635 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
636 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
639 // Shuffle with VMOVSD
640 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
641 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
642 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
643 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
644 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
645 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
646 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
647 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
650 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
651 (SUBREG_TO_REG (i32 0),
652 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
653 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
655 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
656 (SUBREG_TO_REG (i32 0),
657 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
658 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
662 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
663 // is during lowering, where it's not possible to recognize the fold cause
664 // it has two uses through a bitcast. One use disappears at isel time and the
665 // fold opportunity reappears.
666 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
667 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
668 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
669 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
670 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
671 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
672 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
673 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
676 let Predicates = [UseSSE1] in {
677 let AddedComplexity = 15 in {
678 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
679 // MOVSS to the lower bits.
680 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
681 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
682 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
683 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
684 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
685 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
688 let AddedComplexity = 20 in {
689 // MOVSSrm already zeros the high parts of the register.
690 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
691 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
692 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
693 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
694 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
695 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
698 // Extract and store.
699 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
701 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
703 // Shuffle with MOVSS
704 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
705 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
706 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
707 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
710 let Predicates = [UseSSE2] in {
711 let AddedComplexity = 15 in {
712 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
713 // MOVSD to the lower bits.
714 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
715 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
718 let AddedComplexity = 20 in {
719 // MOVSDrm already zeros the high parts of the register.
720 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
721 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
722 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
723 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
724 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
725 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
726 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
727 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
728 def : Pat<(v2f64 (X86vzload addr:$src)),
729 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
732 // Extract and store.
733 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
735 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
737 // Shuffle with MOVSD
738 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
739 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
740 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
741 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
742 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
743 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
744 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
745 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
747 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
748 // is during lowering, where it's not possible to recognize the fold cause
749 // it has two uses through a bitcast. One use disappears at isel time and the
750 // fold opportunity reappears.
751 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
752 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
753 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
754 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
755 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
756 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
757 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
758 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
761 //===----------------------------------------------------------------------===//
762 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
763 //===----------------------------------------------------------------------===//
765 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
766 X86MemOperand x86memop, PatFrag ld_frag,
767 string asm, Domain d,
769 bit IsReMaterializable = 1> {
770 let neverHasSideEffects = 1 in
771 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
772 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>;
773 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
774 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
775 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
776 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>;
779 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
780 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
782 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
783 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
785 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
786 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
788 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
789 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
792 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
793 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
795 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
796 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
797 TB, OpSize, VEX, VEX_L;
798 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
799 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
801 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
802 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
803 TB, OpSize, VEX, VEX_L;
804 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
805 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
807 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
808 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
810 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
811 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
813 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
814 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
817 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
818 "movaps\t{$src, $dst|$dst, $src}",
819 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
820 IIC_SSE_MOVA_P_MR>, VEX;
821 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
822 "movapd\t{$src, $dst|$dst, $src}",
823 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
824 IIC_SSE_MOVA_P_MR>, VEX;
825 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
826 "movups\t{$src, $dst|$dst, $src}",
827 [(store (v4f32 VR128:$src), addr:$dst)],
828 IIC_SSE_MOVU_P_MR>, VEX;
829 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
830 "movupd\t{$src, $dst|$dst, $src}",
831 [(store (v2f64 VR128:$src), addr:$dst)],
832 IIC_SSE_MOVU_P_MR>, VEX;
833 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
834 "movaps\t{$src, $dst|$dst, $src}",
835 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
836 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
837 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
838 "movapd\t{$src, $dst|$dst, $src}",
839 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
840 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
841 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
842 "movups\t{$src, $dst|$dst, $src}",
843 [(store (v8f32 VR256:$src), addr:$dst)],
844 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
845 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
846 "movupd\t{$src, $dst|$dst, $src}",
847 [(store (v4f64 VR256:$src), addr:$dst)],
848 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
851 let isCodeGenOnly = 1, hasSideEffects = 0 in {
852 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
854 "movaps\t{$src, $dst|$dst, $src}", [],
855 IIC_SSE_MOVA_P_RR>, VEX;
856 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
858 "movapd\t{$src, $dst|$dst, $src}", [],
859 IIC_SSE_MOVA_P_RR>, VEX;
860 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
862 "movups\t{$src, $dst|$dst, $src}", [],
863 IIC_SSE_MOVU_P_RR>, VEX;
864 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
866 "movupd\t{$src, $dst|$dst, $src}", [],
867 IIC_SSE_MOVU_P_RR>, VEX;
868 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
870 "movaps\t{$src, $dst|$dst, $src}", [],
871 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
872 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
874 "movapd\t{$src, $dst|$dst, $src}", [],
875 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
876 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
878 "movups\t{$src, $dst|$dst, $src}", [],
879 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
880 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
882 "movupd\t{$src, $dst|$dst, $src}", [],
883 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
886 let Predicates = [HasAVX] in {
887 def : Pat<(v8i32 (X86vzmovl
888 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
889 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
890 def : Pat<(v4i64 (X86vzmovl
891 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
892 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
893 def : Pat<(v8f32 (X86vzmovl
894 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
895 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
896 def : Pat<(v4f64 (X86vzmovl
897 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
898 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
902 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
903 (VMOVUPSYmr addr:$dst, VR256:$src)>;
904 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
905 (VMOVUPDYmr addr:$dst, VR256:$src)>;
907 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
908 "movaps\t{$src, $dst|$dst, $src}",
909 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
911 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
912 "movapd\t{$src, $dst|$dst, $src}",
913 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
915 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
916 "movups\t{$src, $dst|$dst, $src}",
917 [(store (v4f32 VR128:$src), addr:$dst)],
919 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
920 "movupd\t{$src, $dst|$dst, $src}",
921 [(store (v2f64 VR128:$src), addr:$dst)],
925 let isCodeGenOnly = 1, hasSideEffects = 0 in {
926 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
927 "movaps\t{$src, $dst|$dst, $src}", [],
929 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
930 "movapd\t{$src, $dst|$dst, $src}", [],
932 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
933 "movups\t{$src, $dst|$dst, $src}", [],
935 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
936 "movupd\t{$src, $dst|$dst, $src}", [],
940 let Predicates = [HasAVX] in {
941 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
942 (VMOVUPSmr addr:$dst, VR128:$src)>;
943 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
944 (VMOVUPDmr addr:$dst, VR128:$src)>;
947 let Predicates = [UseSSE1] in
948 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
949 (MOVUPSmr addr:$dst, VR128:$src)>;
950 let Predicates = [UseSSE2] in
951 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
952 (MOVUPDmr addr:$dst, VR128:$src)>;
954 // Use vmovaps/vmovups for AVX integer load/store.
955 let Predicates = [HasAVX] in {
956 // 128-bit load/store
957 def : Pat<(alignedloadv2i64 addr:$src),
958 (VMOVAPSrm addr:$src)>;
959 def : Pat<(loadv2i64 addr:$src),
960 (VMOVUPSrm addr:$src)>;
962 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
963 (VMOVAPSmr addr:$dst, VR128:$src)>;
964 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
965 (VMOVAPSmr addr:$dst, VR128:$src)>;
966 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
967 (VMOVAPSmr addr:$dst, VR128:$src)>;
968 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
969 (VMOVAPSmr addr:$dst, VR128:$src)>;
970 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
971 (VMOVUPSmr addr:$dst, VR128:$src)>;
972 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
973 (VMOVUPSmr addr:$dst, VR128:$src)>;
974 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
975 (VMOVUPSmr addr:$dst, VR128:$src)>;
976 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
977 (VMOVUPSmr addr:$dst, VR128:$src)>;
979 // 256-bit load/store
980 def : Pat<(alignedloadv4i64 addr:$src),
981 (VMOVAPSYrm addr:$src)>;
982 def : Pat<(loadv4i64 addr:$src),
983 (VMOVUPSYrm addr:$src)>;
984 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
985 (VMOVAPSYmr addr:$dst, VR256:$src)>;
986 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
987 (VMOVAPSYmr addr:$dst, VR256:$src)>;
988 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
989 (VMOVAPSYmr addr:$dst, VR256:$src)>;
990 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
991 (VMOVAPSYmr addr:$dst, VR256:$src)>;
992 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
993 (VMOVUPSYmr addr:$dst, VR256:$src)>;
994 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
995 (VMOVUPSYmr addr:$dst, VR256:$src)>;
996 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
997 (VMOVUPSYmr addr:$dst, VR256:$src)>;
998 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
999 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1001 // Special patterns for storing subvector extracts of lower 128-bits
1002 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1003 def : Pat<(alignedstore (v2f64 (extract_subvector
1004 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1005 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1006 def : Pat<(alignedstore (v4f32 (extract_subvector
1007 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1008 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1009 def : Pat<(alignedstore (v2i64 (extract_subvector
1010 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1011 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1012 def : Pat<(alignedstore (v4i32 (extract_subvector
1013 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1014 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1015 def : Pat<(alignedstore (v8i16 (extract_subvector
1016 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1017 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1018 def : Pat<(alignedstore (v16i8 (extract_subvector
1019 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1020 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1022 def : Pat<(store (v2f64 (extract_subvector
1023 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1024 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1025 def : Pat<(store (v4f32 (extract_subvector
1026 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1027 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1028 def : Pat<(store (v2i64 (extract_subvector
1029 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1030 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1031 def : Pat<(store (v4i32 (extract_subvector
1032 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1033 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1034 def : Pat<(store (v8i16 (extract_subvector
1035 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1036 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1037 def : Pat<(store (v16i8 (extract_subvector
1038 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1039 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1042 // Use movaps / movups for SSE integer load / store (one byte shorter).
1043 // The instructions selected below are then converted to MOVDQA/MOVDQU
1044 // during the SSE domain pass.
1045 let Predicates = [UseSSE1] in {
1046 def : Pat<(alignedloadv2i64 addr:$src),
1047 (MOVAPSrm addr:$src)>;
1048 def : Pat<(loadv2i64 addr:$src),
1049 (MOVUPSrm addr:$src)>;
1051 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1052 (MOVAPSmr addr:$dst, VR128:$src)>;
1053 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1054 (MOVAPSmr addr:$dst, VR128:$src)>;
1055 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1056 (MOVAPSmr addr:$dst, VR128:$src)>;
1057 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1058 (MOVAPSmr addr:$dst, VR128:$src)>;
1059 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1060 (MOVUPSmr addr:$dst, VR128:$src)>;
1061 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1062 (MOVUPSmr addr:$dst, VR128:$src)>;
1063 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1064 (MOVUPSmr addr:$dst, VR128:$src)>;
1065 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1066 (MOVUPSmr addr:$dst, VR128:$src)>;
1069 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1070 // bits are disregarded. FIXME: Set encoding to pseudo!
1071 let neverHasSideEffects = 1 in {
1072 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1073 "movaps\t{$src, $dst|$dst, $src}", [],
1074 IIC_SSE_MOVA_P_RR>, VEX;
1075 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1076 "movapd\t{$src, $dst|$dst, $src}", [],
1077 IIC_SSE_MOVA_P_RR>, VEX;
1078 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1079 "movaps\t{$src, $dst|$dst, $src}", [],
1081 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1082 "movapd\t{$src, $dst|$dst, $src}", [],
1086 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1087 // bits are disregarded. FIXME: Set encoding to pseudo!
1088 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1089 let isCodeGenOnly = 1 in {
1090 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1091 "movaps\t{$src, $dst|$dst, $src}",
1092 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1093 IIC_SSE_MOVA_P_RM>, VEX;
1094 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1095 "movapd\t{$src, $dst|$dst, $src}",
1096 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1097 IIC_SSE_MOVA_P_RM>, VEX;
1099 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1100 "movaps\t{$src, $dst|$dst, $src}",
1101 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1103 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1104 "movapd\t{$src, $dst|$dst, $src}",
1105 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1109 //===----------------------------------------------------------------------===//
1110 // SSE 1 & 2 - Move Low packed FP Instructions
1111 //===----------------------------------------------------------------------===//
1113 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
1114 SDNode psnode, SDNode pdnode, string base_opc,
1115 string asm_opr, InstrItinClass itin> {
1116 def PSrm : PI<opc, MRMSrcMem,
1117 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1118 !strconcat(base_opc, "s", asm_opr),
1121 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1122 itin, SSEPackedSingle>, TB;
1124 def PDrm : PI<opc, MRMSrcMem,
1125 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
1126 !strconcat(base_opc, "d", asm_opr),
1127 [(set RC:$dst, (v2f64 (pdnode RC:$src1,
1128 (scalar_to_vector (loadf64 addr:$src2)))))],
1129 itin, SSEPackedDouble>, TB, OpSize;
1132 let AddedComplexity = 20 in {
1133 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1134 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1135 IIC_SSE_MOV_LH>, VEX_4V;
1137 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1138 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1139 "\t{$src2, $dst|$dst, $src2}",
1143 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1144 "movlps\t{$src, $dst|$dst, $src}",
1145 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1146 (iPTR 0))), addr:$dst)],
1147 IIC_SSE_MOV_LH>, VEX;
1148 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1149 "movlpd\t{$src, $dst|$dst, $src}",
1150 [(store (f64 (vector_extract (v2f64 VR128:$src),
1151 (iPTR 0))), addr:$dst)],
1152 IIC_SSE_MOV_LH>, VEX;
1153 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1154 "movlps\t{$src, $dst|$dst, $src}",
1155 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1156 (iPTR 0))), addr:$dst)],
1158 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1159 "movlpd\t{$src, $dst|$dst, $src}",
1160 [(store (f64 (vector_extract (v2f64 VR128:$src),
1161 (iPTR 0))), addr:$dst)],
1164 let Predicates = [HasAVX] in {
1165 // Shuffle with VMOVLPS
1166 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1167 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1168 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1169 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1171 // Shuffle with VMOVLPD
1172 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1173 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1174 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1175 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1178 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1180 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1181 def : Pat<(store (v4i32 (X86Movlps
1182 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1183 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1184 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1186 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1187 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1189 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1192 let Predicates = [UseSSE1] in {
1193 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1194 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1195 (iPTR 0))), addr:$src1),
1196 (MOVLPSmr addr:$src1, VR128:$src2)>;
1198 // Shuffle with MOVLPS
1199 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1200 (MOVLPSrm VR128:$src1, addr:$src2)>;
1201 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1202 (MOVLPSrm VR128:$src1, addr:$src2)>;
1203 def : Pat<(X86Movlps VR128:$src1,
1204 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1205 (MOVLPSrm VR128:$src1, addr:$src2)>;
1208 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1210 (MOVLPSmr addr:$src1, VR128:$src2)>;
1211 def : Pat<(store (v4i32 (X86Movlps
1212 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1214 (MOVLPSmr addr:$src1, VR128:$src2)>;
1217 let Predicates = [UseSSE2] in {
1218 // Shuffle with MOVLPD
1219 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1220 (MOVLPDrm VR128:$src1, addr:$src2)>;
1221 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1222 (MOVLPDrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1227 (MOVLPDmr addr:$src1, VR128:$src2)>;
1228 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1230 (MOVLPDmr addr:$src1, VR128:$src2)>;
1233 //===----------------------------------------------------------------------===//
1234 // SSE 1 & 2 - Move Hi packed FP Instructions
1235 //===----------------------------------------------------------------------===//
1237 let AddedComplexity = 20 in {
1238 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1239 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1240 IIC_SSE_MOV_LH>, VEX_4V;
1242 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1243 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1244 "\t{$src2, $dst|$dst, $src2}",
1248 // v2f64 extract element 1 is always custom lowered to unpack high to low
1249 // and extract element 0 so the non-store version isn't too horrible.
1250 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1251 "movhps\t{$src, $dst|$dst, $src}",
1252 [(store (f64 (vector_extract
1253 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1254 (bc_v2f64 (v4f32 VR128:$src))),
1255 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1256 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1257 "movhpd\t{$src, $dst|$dst, $src}",
1258 [(store (f64 (vector_extract
1259 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1260 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1261 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1262 "movhps\t{$src, $dst|$dst, $src}",
1263 [(store (f64 (vector_extract
1264 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1265 (bc_v2f64 (v4f32 VR128:$src))),
1266 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1267 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1268 "movhpd\t{$src, $dst|$dst, $src}",
1269 [(store (f64 (vector_extract
1270 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1271 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1273 let Predicates = [HasAVX] in {
1275 def : Pat<(X86Movlhps VR128:$src1,
1276 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1277 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1278 def : Pat<(X86Movlhps VR128:$src1,
1279 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1280 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1282 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1283 // is during lowering, where it's not possible to recognize the load fold
1284 // cause it has two uses through a bitcast. One use disappears at isel time
1285 // and the fold opportunity reappears.
1286 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1287 (scalar_to_vector (loadf64 addr:$src2)))),
1288 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1291 let Predicates = [UseSSE1] in {
1293 def : Pat<(X86Movlhps VR128:$src1,
1294 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1295 (MOVHPSrm VR128:$src1, addr:$src2)>;
1296 def : Pat<(X86Movlhps VR128:$src1,
1297 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1298 (MOVHPSrm VR128:$src1, addr:$src2)>;
1301 let Predicates = [UseSSE2] in {
1302 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1303 // is during lowering, where it's not possible to recognize the load fold
1304 // cause it has two uses through a bitcast. One use disappears at isel time
1305 // and the fold opportunity reappears.
1306 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1307 (scalar_to_vector (loadf64 addr:$src2)))),
1308 (MOVHPDrm VR128:$src1, addr:$src2)>;
1311 //===----------------------------------------------------------------------===//
1312 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1313 //===----------------------------------------------------------------------===//
1315 let AddedComplexity = 20 in {
1316 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1317 (ins VR128:$src1, VR128:$src2),
1318 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1320 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1323 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1324 (ins VR128:$src1, VR128:$src2),
1325 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1327 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1331 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1332 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1333 (ins VR128:$src1, VR128:$src2),
1334 "movlhps\t{$src2, $dst|$dst, $src2}",
1336 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1338 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1339 (ins VR128:$src1, VR128:$src2),
1340 "movhlps\t{$src2, $dst|$dst, $src2}",
1342 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1346 let Predicates = [HasAVX] in {
1348 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1349 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1350 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1351 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1354 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1355 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1358 let Predicates = [UseSSE1] in {
1360 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1361 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1362 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1363 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1366 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1367 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1370 //===----------------------------------------------------------------------===//
1371 // SSE 1 & 2 - Conversion Instructions
1372 //===----------------------------------------------------------------------===//
1374 def SSE_CVT_PD : OpndItins<
1375 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1378 def SSE_CVT_PS : OpndItins<
1379 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1382 def SSE_CVT_Scalar : OpndItins<
1383 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1386 def SSE_CVT_SS2SI_32 : OpndItins<
1387 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1390 def SSE_CVT_SS2SI_64 : OpndItins<
1391 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1394 def SSE_CVT_SD2SI : OpndItins<
1395 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1398 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1399 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1400 string asm, OpndItins itins> {
1401 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1402 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1404 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1405 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1409 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1410 X86MemOperand x86memop, string asm, Domain d,
1412 let neverHasSideEffects = 1 in {
1413 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1416 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1421 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1422 X86MemOperand x86memop, string asm> {
1423 let neverHasSideEffects = 1 in {
1424 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1425 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1427 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1428 (ins DstRC:$src1, x86memop:$src),
1429 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1430 } // neverHasSideEffects = 1
1433 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1434 "cvttss2si\t{$src, $dst|$dst, $src}",
1437 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1438 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1440 XS, VEX, VEX_W, VEX_LIG;
1441 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1442 "cvttsd2si\t{$src, $dst|$dst, $src}",
1445 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1446 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1448 XD, VEX, VEX_W, VEX_LIG;
1450 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1451 // register, but the same isn't true when only using memory operands,
1452 // provide other assembly "l" and "q" forms to address this explicitly
1453 // where appropriate to do so.
1454 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">,
1455 XS, VEX_4V, VEX_LIG;
1456 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1457 XS, VEX_4V, VEX_W, VEX_LIG;
1458 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">,
1459 XD, VEX_4V, VEX_LIG;
1460 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1461 XD, VEX_4V, VEX_W, VEX_LIG;
1463 def : InstAlias<"vcvtsi2sd{l}\t{$src, $src1, $dst|$dst, $src1, $src}",
1464 (VCVTSI2SDrr FR64:$dst, FR64:$src1, GR32:$src)>;
1465 def : InstAlias<"vcvtsi2sd{l}\t{$src, $src1, $dst|$dst, $src1, $src}",
1466 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1468 let Predicates = [HasAVX] in {
1469 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1470 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1471 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1472 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1473 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1474 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1475 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1476 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1478 def : Pat<(f32 (sint_to_fp GR32:$src)),
1479 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1480 def : Pat<(f32 (sint_to_fp GR64:$src)),
1481 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1482 def : Pat<(f64 (sint_to_fp GR32:$src)),
1483 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1484 def : Pat<(f64 (sint_to_fp GR64:$src)),
1485 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1488 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1489 "cvttss2si\t{$src, $dst|$dst, $src}",
1490 SSE_CVT_SS2SI_32>, XS;
1491 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1492 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1493 SSE_CVT_SS2SI_64>, XS, REX_W;
1494 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1495 "cvttsd2si\t{$src, $dst|$dst, $src}",
1497 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1498 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1499 SSE_CVT_SD2SI>, XD, REX_W;
1500 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1501 "cvtsi2ss\t{$src, $dst|$dst, $src}",
1502 SSE_CVT_Scalar>, XS;
1503 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1504 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1505 SSE_CVT_Scalar>, XS, REX_W;
1506 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1507 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1508 SSE_CVT_Scalar>, XD;
1509 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1510 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1511 SSE_CVT_Scalar>, XD, REX_W;
1513 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1514 // and/or XMM operand(s).
1516 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1517 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1518 string asm, OpndItins itins> {
1519 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1520 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1521 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>;
1522 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1523 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1524 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>;
1527 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1528 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1529 PatFrag ld_frag, string asm, OpndItins itins,
1531 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1533 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1534 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1535 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1537 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1538 (ins DstRC:$src1, x86memop:$src2),
1540 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1541 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1542 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1546 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1547 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si{l}",
1548 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1549 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1550 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si{q}",
1551 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1553 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1554 sdmem, sse_load_f64, "cvtsd2si{l}", SSE_CVT_SD2SI>, XD;
1555 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1556 sdmem, sse_load_f64, "cvtsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1559 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1560 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss",
1561 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1562 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1563 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1564 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1566 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1567 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd",
1568 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1569 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1570 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1571 SSE_CVT_Scalar, 0>, XD,
1574 let Constraints = "$src1 = $dst" in {
1575 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1576 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1577 "cvtsi2ss", SSE_CVT_Scalar>, XS;
1578 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1579 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1580 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1581 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1582 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1583 "cvtsi2sd", SSE_CVT_Scalar>, XD;
1584 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1585 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1586 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1591 // Aliases for intrinsics
1592 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1593 ssmem, sse_load_f32, "cvttss2si",
1594 SSE_CVT_SS2SI_32>, XS, VEX;
1595 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1596 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1597 "cvttss2si{q}", SSE_CVT_SS2SI_64>,
1599 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1600 sdmem, sse_load_f64, "cvttsd2si",
1601 SSE_CVT_SD2SI>, XD, VEX;
1602 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1603 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1604 "cvttsd2si{q}", SSE_CVT_SD2SI>,
1606 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1607 ssmem, sse_load_f32, "cvttss2si",
1608 SSE_CVT_SS2SI_32>, XS;
1609 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1610 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1611 "cvttss2si{q}", SSE_CVT_SS2SI_64>, XS, REX_W;
1612 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1613 sdmem, sse_load_f64, "cvttsd2si",
1615 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1616 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1617 "cvttsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1619 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1620 ssmem, sse_load_f32, "cvtss2si{l}",
1621 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1622 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1623 ssmem, sse_load_f32, "cvtss2si{q}",
1624 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1626 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1627 ssmem, sse_load_f32, "cvtss2si{l}",
1628 SSE_CVT_SS2SI_32>, XS;
1629 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1630 ssmem, sse_load_f32, "cvtss2si{q}",
1631 SSE_CVT_SS2SI_64>, XS, REX_W;
1633 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1634 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1635 SSEPackedSingle, SSE_CVT_PS>,
1636 TB, VEX, Requires<[HasAVX]>;
1637 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1638 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1639 SSEPackedSingle, SSE_CVT_PS>,
1640 TB, VEX, VEX_L, Requires<[HasAVX]>;
1642 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1643 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1644 SSEPackedSingle, SSE_CVT_PS>,
1645 TB, Requires<[UseSSE2]>;
1649 // Convert scalar double to scalar single
1650 let neverHasSideEffects = 1 in {
1651 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1652 (ins FR64:$src1, FR64:$src2),
1653 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1654 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG;
1656 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1657 (ins FR64:$src1, f64mem:$src2),
1658 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1659 [], IIC_SSE_CVT_Scalar_RM>,
1660 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1663 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1666 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1667 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1668 [(set FR32:$dst, (fround FR64:$src))],
1669 IIC_SSE_CVT_Scalar_RR>;
1670 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1671 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1672 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1673 IIC_SSE_CVT_Scalar_RM>,
1675 Requires<[UseSSE2, OptForSize]>;
1677 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1678 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1679 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1681 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1682 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>;
1683 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1684 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1685 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1686 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1687 VR128:$src1, sse_load_f64:$src2))],
1688 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>;
1690 let Constraints = "$src1 = $dst" in {
1691 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1692 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1693 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1695 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1696 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>;
1697 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1698 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1699 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1700 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1701 VR128:$src1, sse_load_f64:$src2))],
1702 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>;
1705 // Convert scalar single to scalar double
1706 // SSE2 instructions with XS prefix
1707 let neverHasSideEffects = 1 in {
1708 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1709 (ins FR32:$src1, FR32:$src2),
1710 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1711 [], IIC_SSE_CVT_Scalar_RR>,
1712 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1714 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1715 (ins FR32:$src1, f32mem:$src2),
1716 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1717 [], IIC_SSE_CVT_Scalar_RM>,
1718 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1721 def : Pat<(f64 (fextend FR32:$src)),
1722 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[HasAVX]>;
1723 def : Pat<(fextend (loadf32 addr:$src)),
1724 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX]>;
1726 def : Pat<(extloadf32 addr:$src),
1727 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1728 Requires<[HasAVX, OptForSize]>;
1729 def : Pat<(extloadf32 addr:$src),
1730 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1731 Requires<[HasAVX, OptForSpeed]>;
1733 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1734 "cvtss2sd\t{$src, $dst|$dst, $src}",
1735 [(set FR64:$dst, (fextend FR32:$src))],
1736 IIC_SSE_CVT_Scalar_RR>, XS,
1737 Requires<[UseSSE2]>;
1738 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1739 "cvtss2sd\t{$src, $dst|$dst, $src}",
1740 [(set FR64:$dst, (extloadf32 addr:$src))],
1741 IIC_SSE_CVT_Scalar_RM>, XS,
1742 Requires<[UseSSE2, OptForSize]>;
1744 // extload f32 -> f64. This matches load+fextend because we have a hack in
1745 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1747 // Since these loads aren't folded into the fextend, we have to match it
1749 def : Pat<(fextend (loadf32 addr:$src)),
1750 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1751 def : Pat<(extloadf32 addr:$src),
1752 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1754 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1755 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1756 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1758 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1759 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[HasAVX]>;
1760 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1761 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1762 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1764 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1765 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[HasAVX]>;
1766 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1767 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1768 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1769 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1771 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1772 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>;
1773 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1774 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1775 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1777 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1778 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>;
1781 // Convert packed single/double fp to doubleword
1782 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1783 "cvtps2dq\t{$src, $dst|$dst, $src}",
1784 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1785 IIC_SSE_CVT_PS_RR>, VEX;
1786 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1787 "cvtps2dq\t{$src, $dst|$dst, $src}",
1789 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1790 IIC_SSE_CVT_PS_RM>, VEX;
1791 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1792 "cvtps2dq\t{$src, $dst|$dst, $src}",
1794 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1795 IIC_SSE_CVT_PS_RR>, VEX, VEX_L;
1796 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1797 "cvtps2dq\t{$src, $dst|$dst, $src}",
1799 (int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)))],
1800 IIC_SSE_CVT_PS_RM>, VEX, VEX_L;
1801 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1802 "cvtps2dq\t{$src, $dst|$dst, $src}",
1803 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1805 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1806 "cvtps2dq\t{$src, $dst|$dst, $src}",
1808 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1812 // Convert Packed Double FP to Packed DW Integers
1813 let Predicates = [HasAVX] in {
1814 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1815 // register, but the same isn't true when using memory operands instead.
1816 // Provide other assembly rr and rm forms to address this explicitly.
1817 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1818 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1819 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1823 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1824 (VCVTPD2DQrr VR128:$dst, VR128:$src)>;
1825 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1826 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1828 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))]>, VEX;
1831 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1832 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1834 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L;
1835 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1836 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1838 (int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)))]>,
1840 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
1841 (VCVTPD2DQYrr VR128:$dst, VR256:$src)>;
1844 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1845 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1847 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
1849 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1850 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1851 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1854 // Convert with truncation packed single/double fp to doubleword
1855 // SSE2 packed instructions with XS prefix
1856 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1857 "cvttps2dq\t{$src, $dst|$dst, $src}",
1859 (int_x86_sse2_cvttps2dq VR128:$src))],
1860 IIC_SSE_CVT_PS_RR>, VEX;
1861 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1862 "cvttps2dq\t{$src, $dst|$dst, $src}",
1863 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1864 (memopv4f32 addr:$src)))],
1865 IIC_SSE_CVT_PS_RM>, VEX;
1866 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1867 "cvttps2dq\t{$src, $dst|$dst, $src}",
1869 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
1870 IIC_SSE_CVT_PS_RR>, VEX, VEX_L;
1871 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1872 "cvttps2dq\t{$src, $dst|$dst, $src}",
1873 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
1874 (memopv8f32 addr:$src)))],
1875 IIC_SSE_CVT_PS_RM>, VEX, VEX_L;
1877 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1878 "cvttps2dq\t{$src, $dst|$dst, $src}",
1879 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
1881 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1882 "cvttps2dq\t{$src, $dst|$dst, $src}",
1884 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
1887 let Predicates = [HasAVX] in {
1888 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1889 (VCVTDQ2PSrr VR128:$src)>;
1890 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1891 (VCVTDQ2PSrm addr:$src)>;
1893 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1894 (VCVTDQ2PSrr VR128:$src)>;
1895 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
1896 (VCVTDQ2PSrm addr:$src)>;
1898 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1899 (VCVTTPS2DQrr VR128:$src)>;
1900 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1901 (VCVTTPS2DQrm addr:$src)>;
1903 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1904 (VCVTDQ2PSYrr VR256:$src)>;
1905 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
1906 (VCVTDQ2PSYrm addr:$src)>;
1908 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1909 (VCVTTPS2DQYrr VR256:$src)>;
1910 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
1911 (VCVTTPS2DQYrm addr:$src)>;
1914 let Predicates = [UseSSE2] in {
1915 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1916 (CVTDQ2PSrr VR128:$src)>;
1917 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1918 (CVTDQ2PSrm addr:$src)>;
1920 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1921 (CVTDQ2PSrr VR128:$src)>;
1922 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
1923 (CVTDQ2PSrm addr:$src)>;
1925 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1926 (CVTTPS2DQrr VR128:$src)>;
1927 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1928 (CVTTPS2DQrm addr:$src)>;
1931 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1932 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1934 (int_x86_sse2_cvttpd2dq VR128:$src))],
1935 IIC_SSE_CVT_PD_RR>, VEX;
1937 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1938 // register, but the same isn't true when using memory operands instead.
1939 // Provide other assembly rr and rm forms to address this explicitly.
1942 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
1943 (VCVTTPD2DQrr VR128:$dst, VR128:$src)>;
1944 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1945 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
1946 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1947 (memopv2f64 addr:$src)))],
1948 IIC_SSE_CVT_PD_RM>, VEX;
1951 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1952 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
1954 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
1955 IIC_SSE_CVT_PD_RR>, VEX, VEX_L;
1956 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1957 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
1959 (int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)))],
1960 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
1961 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
1962 (VCVTTPD2DQYrr VR128:$dst, VR256:$src)>;
1964 let Predicates = [HasAVX] in {
1965 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
1966 (VCVTTPD2DQYrr VR256:$src)>;
1967 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
1968 (VCVTTPD2DQYrm addr:$src)>;
1969 } // Predicates = [HasAVX]
1971 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1972 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1973 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
1975 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1976 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1977 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1978 (memopv2f64 addr:$src)))],
1981 // Convert packed single to packed double
1982 let Predicates = [HasAVX] in {
1983 // SSE2 instructions without OpSize prefix
1984 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1985 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1986 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
1987 IIC_SSE_CVT_PD_RR>, TB, VEX;
1988 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1989 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1990 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
1991 IIC_SSE_CVT_PD_RM>, TB, VEX;
1992 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1993 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1995 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
1996 IIC_SSE_CVT_PD_RR>, TB, VEX, VEX_L;
1997 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1998 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2000 (int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)))],
2001 IIC_SSE_CVT_PD_RM>, TB, VEX, VEX_L;
2004 let Predicates = [UseSSE2] in {
2005 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2006 "cvtps2pd\t{$src, $dst|$dst, $src}",
2007 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2008 IIC_SSE_CVT_PD_RR>, TB;
2009 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2010 "cvtps2pd\t{$src, $dst|$dst, $src}",
2011 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2012 IIC_SSE_CVT_PD_RM>, TB;
2015 // Convert Packed DW Integers to Packed Double FP
2016 let Predicates = [HasAVX] in {
2017 let neverHasSideEffects = 1, mayLoad = 1 in
2018 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2019 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2021 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2022 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2024 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX;
2025 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2026 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2028 (int_x86_avx_cvtdq2_pd_256
2029 (bitconvert (memopv2i64 addr:$src))))]>, VEX, VEX_L;
2030 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2031 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2033 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L;
2036 let neverHasSideEffects = 1, mayLoad = 1 in
2037 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2038 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2040 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2041 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2042 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2045 // AVX 256-bit register conversion intrinsics
2046 let Predicates = [HasAVX] in {
2047 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2048 (VCVTDQ2PDYrr VR128:$src)>;
2049 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2050 (VCVTDQ2PDYrm addr:$src)>;
2051 } // Predicates = [HasAVX]
2053 // Convert packed double to packed single
2054 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2055 // register, but the same isn't true when using memory operands instead.
2056 // Provide other assembly rr and rm forms to address this explicitly.
2057 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2058 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2059 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2060 IIC_SSE_CVT_PD_RR>, VEX;
2063 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2064 (VCVTPD2PSrr VR128:$dst, VR128:$src)>;
2065 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2066 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2068 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2069 IIC_SSE_CVT_PD_RM>, VEX;
2072 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2073 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2075 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2076 IIC_SSE_CVT_PD_RR>, VEX, VEX_L;
2077 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2078 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2080 (int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)))],
2081 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
2082 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2083 (VCVTPD2PSYrr VR128:$dst, VR256:$src)>;
2085 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2086 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2087 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2089 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2090 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2092 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2096 // AVX 256-bit register conversion intrinsics
2097 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2098 // whenever possible to avoid declaring two versions of each one.
2099 let Predicates = [HasAVX] in {
2100 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2101 (VCVTDQ2PSYrr VR256:$src)>;
2102 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2103 (VCVTDQ2PSYrm addr:$src)>;
2105 // Match fround and fextend for 128/256-bit conversions
2106 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2107 (VCVTPD2PSrr VR128:$src)>;
2108 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2109 (VCVTPD2PSXrm addr:$src)>;
2110 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2111 (VCVTPD2PSYrr VR256:$src)>;
2112 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2113 (VCVTPD2PSYrm addr:$src)>;
2115 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2116 (VCVTPS2PDrr VR128:$src)>;
2117 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2118 (VCVTPS2PDYrr VR128:$src)>;
2119 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2120 (VCVTPS2PDYrm addr:$src)>;
2123 let Predicates = [UseSSE2] in {
2124 // Match fround and fextend for 128 conversions
2125 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2126 (CVTPD2PSrr VR128:$src)>;
2127 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2128 (CVTPD2PSrm addr:$src)>;
2130 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2131 (CVTPS2PDrr VR128:$src)>;
2134 //===----------------------------------------------------------------------===//
2135 // SSE 1 & 2 - Compare Instructions
2136 //===----------------------------------------------------------------------===//
2138 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2139 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2140 Operand CC, SDNode OpNode, ValueType VT,
2141 PatFrag ld_frag, string asm, string asm_alt,
2143 def rr : SIi8<0xC2, MRMSrcReg,
2144 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2145 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2147 def rm : SIi8<0xC2, MRMSrcMem,
2148 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2149 [(set RC:$dst, (OpNode (VT RC:$src1),
2150 (ld_frag addr:$src2), imm:$cc))],
2153 // Accept explicit immediate argument form instead of comparison code.
2154 let neverHasSideEffects = 1 in {
2155 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2156 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2157 IIC_SSE_ALU_F32S_RR>;
2159 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2160 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2161 IIC_SSE_ALU_F32S_RM>;
2165 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2166 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2167 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2169 XS, VEX_4V, VEX_LIG;
2170 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2171 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2172 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2173 SSE_ALU_F32S>, // same latency as 32 bit compare
2174 XD, VEX_4V, VEX_LIG;
2176 let Constraints = "$src1 = $dst" in {
2177 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2178 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2179 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2181 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2182 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2183 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2184 SSE_ALU_F32S>, // same latency as 32 bit compare
2188 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2189 Intrinsic Int, string asm, OpndItins itins> {
2190 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2191 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2192 [(set VR128:$dst, (Int VR128:$src1,
2193 VR128:$src, imm:$cc))],
2195 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2196 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2197 [(set VR128:$dst, (Int VR128:$src1,
2198 (load addr:$src), imm:$cc))],
2202 // Aliases to match intrinsics which expect XMM operand(s).
2203 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2204 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2207 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2208 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2209 SSE_ALU_F32S>, // same latency as f32
2211 let Constraints = "$src1 = $dst" in {
2212 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2213 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2215 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2216 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2217 SSE_ALU_F32S>, // same latency as f32
2222 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2223 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2224 ValueType vt, X86MemOperand x86memop,
2225 PatFrag ld_frag, string OpcodeStr, Domain d> {
2226 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2227 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2228 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2229 IIC_SSE_COMIS_RR, d>;
2230 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2231 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2232 [(set EFLAGS, (OpNode (vt RC:$src1),
2233 (ld_frag addr:$src2)))],
2234 IIC_SSE_COMIS_RM, d>;
2237 let Defs = [EFLAGS] in {
2238 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2239 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2240 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2241 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2243 let Pattern = []<dag> in {
2244 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2245 "comiss", SSEPackedSingle>, TB, VEX,
2247 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2248 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2252 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2253 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2254 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2255 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2257 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2258 load, "comiss", SSEPackedSingle>, TB, VEX;
2259 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2260 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2261 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2262 "ucomiss", SSEPackedSingle>, TB;
2263 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2264 "ucomisd", SSEPackedDouble>, TB, OpSize;
2266 let Pattern = []<dag> in {
2267 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2268 "comiss", SSEPackedSingle>, TB;
2269 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2270 "comisd", SSEPackedDouble>, TB, OpSize;
2273 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2274 load, "ucomiss", SSEPackedSingle>, TB;
2275 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2276 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2278 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2279 "comiss", SSEPackedSingle>, TB;
2280 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2281 "comisd", SSEPackedDouble>, TB, OpSize;
2282 } // Defs = [EFLAGS]
2284 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2285 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2286 Operand CC, Intrinsic Int, string asm,
2287 string asm_alt, Domain d> {
2288 def rri : PIi8<0xC2, MRMSrcReg,
2289 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2290 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2291 IIC_SSE_CMPP_RR, d>;
2292 def rmi : PIi8<0xC2, MRMSrcMem,
2293 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2294 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2295 IIC_SSE_CMPP_RM, d>;
2297 // Accept explicit immediate argument form instead of comparison code.
2298 let neverHasSideEffects = 1 in {
2299 def rri_alt : PIi8<0xC2, MRMSrcReg,
2300 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2301 asm_alt, [], IIC_SSE_CMPP_RR, d>;
2302 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2303 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2304 asm_alt, [], IIC_SSE_CMPP_RM, d>;
2308 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2309 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2310 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2311 SSEPackedSingle>, TB, VEX_4V;
2312 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2313 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2314 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2315 SSEPackedDouble>, TB, OpSize, VEX_4V;
2316 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2317 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2318 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2319 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2320 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2321 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2322 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2323 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2324 let Constraints = "$src1 = $dst" in {
2325 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2326 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2327 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2328 SSEPackedSingle>, TB;
2329 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2330 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2331 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2332 SSEPackedDouble>, TB, OpSize;
2335 let Predicates = [HasAVX] in {
2336 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2337 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2338 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2339 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2340 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2341 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2342 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2343 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2345 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2346 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2347 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2348 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2349 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2350 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2351 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2352 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2355 let Predicates = [UseSSE1] in {
2356 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2357 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2358 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2359 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2362 let Predicates = [UseSSE2] in {
2363 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2364 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2365 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2366 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2369 //===----------------------------------------------------------------------===//
2370 // SSE 1 & 2 - Shuffle Instructions
2371 //===----------------------------------------------------------------------===//
2373 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2374 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2375 ValueType vt, string asm, PatFrag mem_frag,
2376 Domain d, bit IsConvertibleToThreeAddress = 0> {
2377 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2378 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2379 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2380 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2381 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2382 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2383 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2384 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2385 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2388 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2389 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2390 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2391 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2392 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2393 memopv8f32, SSEPackedSingle>, TB, VEX_4V, VEX_L;
2394 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2395 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2396 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2397 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2398 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2399 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2401 let Constraints = "$src1 = $dst" in {
2402 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2403 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2404 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2406 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2407 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2408 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2412 let Predicates = [HasAVX] in {
2413 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2414 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2415 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2416 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2417 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2419 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2420 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2421 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2422 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2423 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2426 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2427 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2428 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2429 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2430 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2432 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2433 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2434 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2435 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2436 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2439 let Predicates = [UseSSE1] in {
2440 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2441 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2442 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2443 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2444 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2447 let Predicates = [UseSSE2] in {
2448 // Generic SHUFPD patterns
2449 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2450 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2451 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2452 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2453 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2456 //===----------------------------------------------------------------------===//
2457 // SSE 1 & 2 - Unpack Instructions
2458 //===----------------------------------------------------------------------===//
2460 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2461 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2462 PatFrag mem_frag, RegisterClass RC,
2463 X86MemOperand x86memop, string asm,
2465 def rr : PI<opc, MRMSrcReg,
2466 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2468 (vt (OpNode RC:$src1, RC:$src2)))],
2470 def rm : PI<opc, MRMSrcMem,
2471 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2473 (vt (OpNode RC:$src1,
2474 (mem_frag addr:$src2))))],
2478 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2479 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2480 SSEPackedSingle>, TB, VEX_4V;
2481 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2482 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2483 SSEPackedDouble>, TB, OpSize, VEX_4V;
2484 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2485 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2486 SSEPackedSingle>, TB, VEX_4V;
2487 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2488 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2489 SSEPackedDouble>, TB, OpSize, VEX_4V;
2491 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2492 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2493 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2494 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2495 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2496 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2497 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2498 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2499 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2500 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2501 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2502 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2504 let Constraints = "$src1 = $dst" in {
2505 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2506 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2507 SSEPackedSingle>, TB;
2508 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2509 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2510 SSEPackedDouble>, TB, OpSize;
2511 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2512 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2513 SSEPackedSingle>, TB;
2514 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2515 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2516 SSEPackedDouble>, TB, OpSize;
2517 } // Constraints = "$src1 = $dst"
2519 let Predicates = [HasAVX1Only] in {
2520 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2521 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2522 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2523 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2524 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2525 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2526 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2527 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2529 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
2530 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2531 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2532 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2533 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
2534 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2535 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2536 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2539 let Predicates = [HasAVX] in {
2540 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2541 // problem is during lowering, where it's not possible to recognize the load
2542 // fold cause it has two uses through a bitcast. One use disappears at isel
2543 // time and the fold opportunity reappears.
2544 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2545 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2548 let Predicates = [UseSSE2] in {
2549 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2550 // problem is during lowering, where it's not possible to recognize the load
2551 // fold cause it has two uses through a bitcast. One use disappears at isel
2552 // time and the fold opportunity reappears.
2553 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2554 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2557 //===----------------------------------------------------------------------===//
2558 // SSE 1 & 2 - Extract Floating-Point Sign mask
2559 //===----------------------------------------------------------------------===//
2561 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2562 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2564 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2565 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2566 [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>;
2567 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2568 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2569 IIC_SSE_MOVMSK, d>, REX_W;
2572 let Predicates = [HasAVX] in {
2573 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2574 "movmskps", SSEPackedSingle>, TB, VEX;
2575 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2576 "movmskpd", SSEPackedDouble>, TB,
2578 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2579 "movmskps", SSEPackedSingle>, TB,
2581 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2582 "movmskpd", SSEPackedDouble>, TB,
2585 def : Pat<(i32 (X86fgetsign FR32:$src)),
2586 (VMOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2587 def : Pat<(i64 (X86fgetsign FR32:$src)),
2588 (VMOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2589 def : Pat<(i32 (X86fgetsign FR64:$src)),
2590 (VMOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2591 def : Pat<(i64 (X86fgetsign FR64:$src)),
2592 (VMOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2595 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2596 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2597 SSEPackedSingle>, TB, VEX;
2598 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2599 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2600 SSEPackedDouble>, TB,
2602 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2603 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2604 SSEPackedSingle>, TB, VEX, VEX_L;
2605 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2606 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2607 SSEPackedDouble>, TB,
2611 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2612 SSEPackedSingle>, TB;
2613 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2614 SSEPackedDouble>, TB, OpSize;
2616 def : Pat<(i32 (X86fgetsign FR32:$src)),
2617 (MOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2618 Requires<[UseSSE1]>;
2619 def : Pat<(i64 (X86fgetsign FR32:$src)),
2620 (MOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2621 Requires<[UseSSE1]>;
2622 def : Pat<(i32 (X86fgetsign FR64:$src)),
2623 (MOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2624 Requires<[UseSSE2]>;
2625 def : Pat<(i64 (X86fgetsign FR64:$src)),
2626 (MOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2627 Requires<[UseSSE2]>;
2629 //===---------------------------------------------------------------------===//
2630 // SSE2 - Packed Integer Logical Instructions
2631 //===---------------------------------------------------------------------===//
2633 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2635 /// PDI_binop_rm - Simple SSE2 binary operator.
2636 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2637 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2638 X86MemOperand x86memop, OpndItins itins,
2639 bit IsCommutable, bit Is2Addr> {
2640 let isCommutable = IsCommutable in
2641 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2642 (ins RC:$src1, RC:$src2),
2644 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2645 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2646 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>;
2647 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2648 (ins RC:$src1, x86memop:$src2),
2650 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2651 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2652 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2653 (bitconvert (memop_frag addr:$src2)))))],
2656 } // ExeDomain = SSEPackedInt
2658 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2659 ValueType OpVT128, ValueType OpVT256,
2660 OpndItins itins, bit IsCommutable = 0> {
2661 let Predicates = [HasAVX] in
2662 defm V#NAME# : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2663 VR128, memopv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2665 let Constraints = "$src1 = $dst" in
2666 defm #NAME# : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2667 memopv2i64, i128mem, itins, IsCommutable, 1>;
2669 let Predicates = [HasAVX2] in
2670 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2671 OpVT256, VR256, memopv4i64, i256mem, itins,
2672 IsCommutable, 0>, VEX_4V, VEX_L;
2675 // These are ordered here for pattern ordering requirements with the fp versions
2677 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2678 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2679 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2680 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2681 SSE_BIT_ITINS_P, 0>;
2683 //===----------------------------------------------------------------------===//
2684 // SSE 1 & 2 - Logical Instructions
2685 //===----------------------------------------------------------------------===//
2687 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2689 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2690 SDNode OpNode, OpndItins itins> {
2691 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2692 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2695 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2696 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2699 let Constraints = "$src1 = $dst" in {
2700 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2701 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2704 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2705 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2710 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2711 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2713 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2715 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2718 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2719 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef,
2722 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2724 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2726 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2727 !strconcat(OpcodeStr, "ps"), f256mem,
2728 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2729 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2730 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V, VEX_L;
2732 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2733 !strconcat(OpcodeStr, "pd"), f256mem,
2734 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2735 (bc_v4i64 (v4f64 VR256:$src2))))],
2736 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2737 (memopv4i64 addr:$src2)))], 0>,
2738 TB, OpSize, VEX_4V, VEX_L;
2740 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2741 // are all promoted to v2i64, and the patterns are covered by the int
2742 // version. This is needed in SSE only, because v2i64 isn't supported on
2743 // SSE1, but only on SSE2.
2744 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2745 !strconcat(OpcodeStr, "ps"), f128mem, [],
2746 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2747 (memopv2i64 addr:$src2)))], 0>, TB, VEX_4V;
2749 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2750 !strconcat(OpcodeStr, "pd"), f128mem,
2751 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2752 (bc_v2i64 (v2f64 VR128:$src2))))],
2753 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2754 (memopv2i64 addr:$src2)))], 0>,
2757 let Constraints = "$src1 = $dst" in {
2758 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2759 !strconcat(OpcodeStr, "ps"), f128mem,
2760 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2761 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2762 (memopv2i64 addr:$src2)))]>, TB;
2764 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2765 !strconcat(OpcodeStr, "pd"), f128mem,
2766 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2767 (bc_v2i64 (v2f64 VR128:$src2))))],
2768 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2769 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2773 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2774 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2775 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2776 let isCommutable = 0 in
2777 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2779 //===----------------------------------------------------------------------===//
2780 // SSE 1 & 2 - Arithmetic Instructions
2781 //===----------------------------------------------------------------------===//
2783 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2786 /// In addition, we also have a special variant of the scalar form here to
2787 /// represent the associated intrinsic operation. This form is unlike the
2788 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2789 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2791 /// These three forms can each be reg+reg or reg+mem.
2794 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2796 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2799 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2800 OpNode, FR32, f32mem,
2801 itins.s, Is2Addr>, XS;
2802 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2803 OpNode, FR64, f64mem,
2804 itins.d, Is2Addr>, XD;
2807 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
2808 SDNode OpNode, SizeItins itins> {
2809 let Predicates = [HasAVX] in {
2810 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2811 VR128, v4f32, f128mem, memopv4f32,
2812 SSEPackedSingle, itins.s, 0>, TB, VEX_4V;
2813 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2814 VR128, v2f64, f128mem, memopv2f64,
2815 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V;
2817 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
2818 OpNode, VR256, v8f32, f256mem, memopv8f32,
2819 SSEPackedSingle, itins.s, 0>, TB, VEX_4V, VEX_L;
2820 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
2821 OpNode, VR256, v4f64, f256mem, memopv4f64,
2822 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V, VEX_L;
2825 let Constraints = "$src1 = $dst" in {
2826 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2827 v4f32, f128mem, memopv4f32, SSEPackedSingle,
2829 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2830 v2f64, f128mem, memopv2f64, SSEPackedDouble,
2831 itins.d, 1>, TB, OpSize;
2835 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2838 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2839 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2840 itins.s, Is2Addr>, XS;
2841 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2842 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2843 itins.d, Is2Addr>, XD;
2846 // Binary Arithmetic instructions
2847 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>;
2848 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>;
2849 let isCommutable = 0 in {
2850 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>;
2851 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>;
2852 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>;
2853 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>;
2856 let isCodeGenOnly = 1 in {
2857 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>;
2858 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>;
2861 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S, 0>,
2862 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S, 0>,
2864 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S, 0>,
2865 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S, 0>,
2868 let isCommutable = 0 in {
2869 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S, 0>,
2870 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S, 0>,
2872 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S, 0>,
2873 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S, 0>,
2875 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S, 0>,
2876 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S, 0>,
2878 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S, 0>,
2879 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S, 0>,
2883 let Constraints = "$src1 = $dst" in {
2884 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
2885 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
2886 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
2887 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
2889 let isCommutable = 0 in {
2890 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
2891 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
2892 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
2893 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
2894 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
2895 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
2896 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
2897 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
2901 let isCodeGenOnly = 1 in {
2902 defm VMAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S, 0>,
2904 defm VMINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S, 0>,
2906 let Constraints = "$src1 = $dst" in {
2907 defm MAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
2908 defm MINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
2913 /// In addition, we also have a special variant of the scalar form here to
2914 /// represent the associated intrinsic operation. This form is unlike the
2915 /// plain scalar form, in that it takes an entire vector (instead of a
2916 /// scalar) and leaves the top elements undefined.
2918 /// And, we have a special variant form for a full-vector intrinsic form.
2920 def SSE_SQRTP : OpndItins<
2921 IIC_SSE_SQRTP_RR, IIC_SSE_SQRTP_RM
2924 def SSE_SQRTS : OpndItins<
2925 IIC_SSE_SQRTS_RR, IIC_SSE_SQRTS_RM
2928 def SSE_RCPP : OpndItins<
2929 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
2932 def SSE_RCPS : OpndItins<
2933 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
2936 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2937 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2938 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
2939 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2940 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2941 [(set FR32:$dst, (OpNode FR32:$src))]>;
2942 // For scalar unary operations, fold a load into the operation
2943 // only in OptForSize mode. It eliminates an instruction, but it also
2944 // eliminates a whole-register clobber (the load), so it introduces a
2945 // partial register update condition.
2946 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
2947 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2948 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
2949 Requires<[UseSSE1, OptForSize]>;
2950 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2951 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2952 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>;
2953 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
2954 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2955 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>;
2958 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
2959 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2960 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
2961 !strconcat(OpcodeStr,
2962 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2963 let mayLoad = 1 in {
2964 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
2965 !strconcat(OpcodeStr,
2966 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2967 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
2968 (ins VR128:$src1, ssmem:$src2),
2969 !strconcat(OpcodeStr,
2970 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2974 /// sse1_fp_unop_p - SSE1 unops in packed form.
2975 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2977 let Predicates = [HasAVX] in {
2978 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2979 !strconcat(!strconcat("v", OpcodeStr),
2980 "ps\t{$src, $dst|$dst, $src}"),
2981 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
2983 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2984 !strconcat(!strconcat("v", OpcodeStr),
2985 "ps\t{$src, $dst|$dst, $src}"),
2986 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))],
2988 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2989 !strconcat(!strconcat("v", OpcodeStr),
2990 "ps\t{$src, $dst|$dst, $src}"),
2991 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
2992 itins.rr>, VEX, VEX_L;
2993 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2994 !strconcat(!strconcat("v", OpcodeStr),
2995 "ps\t{$src, $dst|$dst, $src}"),
2996 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))],
2997 itins.rm>, VEX, VEX_L;
3000 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3001 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3002 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>;
3003 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3004 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3005 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>;
3008 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3009 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3010 Intrinsic V4F32Int, Intrinsic V8F32Int,
3012 let Predicates = [HasAVX] in {
3013 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3014 !strconcat(!strconcat("v", OpcodeStr),
3015 "ps\t{$src, $dst|$dst, $src}"),
3016 [(set VR128:$dst, (V4F32Int VR128:$src))],
3018 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3019 !strconcat(!strconcat("v", OpcodeStr),
3020 "ps\t{$src, $dst|$dst, $src}"),
3021 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3023 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3024 !strconcat(!strconcat("v", OpcodeStr),
3025 "ps\t{$src, $dst|$dst, $src}"),
3026 [(set VR256:$dst, (V8F32Int VR256:$src))],
3027 itins.rr>, VEX, VEX_L;
3028 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3030 !strconcat(!strconcat("v", OpcodeStr),
3031 "ps\t{$src, $dst|$dst, $src}"),
3032 [(set VR256:$dst, (V8F32Int (memopv8f32 addr:$src)))],
3033 itins.rm>, VEX, VEX_L;
3036 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3037 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3038 [(set VR128:$dst, (V4F32Int VR128:$src))],
3040 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3041 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3042 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3046 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3047 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3048 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3049 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3050 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3051 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>;
3052 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3053 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3054 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3055 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3056 Requires<[UseSSE2, OptForSize]>;
3057 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3058 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3059 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>;
3060 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3061 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3062 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>;
3065 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
3066 let hasSideEffects = 0 in
3067 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3068 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
3069 !strconcat(OpcodeStr,
3070 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3071 let mayLoad = 1 in {
3072 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
3073 !strconcat(OpcodeStr,
3074 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3075 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3076 (ins VR128:$src1, sdmem:$src2),
3077 !strconcat(OpcodeStr,
3078 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3082 /// sse2_fp_unop_p_new - SSE2 unops in vector forms.
3083 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3084 SDNode OpNode, OpndItins itins> {
3085 let Predicates = [HasAVX] in {
3086 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3087 !strconcat(!strconcat("v", OpcodeStr),
3088 "pd\t{$src, $dst|$dst, $src}"),
3089 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3091 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3092 !strconcat(!strconcat("v", OpcodeStr),
3093 "pd\t{$src, $dst|$dst, $src}"),
3094 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))],
3096 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3097 !strconcat(!strconcat("v", OpcodeStr),
3098 "pd\t{$src, $dst|$dst, $src}"),
3099 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3100 itins.rr>, VEX, VEX_L;
3101 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3102 !strconcat(!strconcat("v", OpcodeStr),
3103 "pd\t{$src, $dst|$dst, $src}"),
3104 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))],
3105 itins.rm>, VEX, VEX_L;
3108 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3109 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3110 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>;
3111 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3112 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3113 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>;
3116 defm SQRT : sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTP>,
3117 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTP>;
3118 defm RSQRT : sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTP>,
3119 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3120 int_x86_avx_rsqrt_ps_256, SSE_SQRTP>;
3121 defm RCP : sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3122 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3123 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3125 let Predicates = [HasAVX] in {
3127 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
3128 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
3130 // Reciprocal approximations. Note that these typically require refinement
3131 // in order to obtain suitable precision.
3132 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
3133 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
3136 def : Pat<(f32 (fsqrt FR32:$src)),
3137 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3138 def : Pat<(f32 (fsqrt (load addr:$src))),
3139 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3140 Requires<[HasAVX, OptForSize]>;
3141 def : Pat<(f64 (fsqrt FR64:$src)),
3142 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3143 def : Pat<(f64 (fsqrt (load addr:$src))),
3144 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3145 Requires<[HasAVX, OptForSize]>;
3147 def : Pat<(f32 (X86frsqrt FR32:$src)),
3148 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3149 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3150 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3151 Requires<[HasAVX, OptForSize]>;
3153 def : Pat<(f32 (X86frcp FR32:$src)),
3154 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3155 def : Pat<(f32 (X86frcp (load addr:$src))),
3156 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3157 Requires<[HasAVX, OptForSize]>;
3159 let Predicates = [HasAVX] in {
3160 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3161 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3162 (COPY_TO_REGCLASS VR128:$src, FR32)),
3164 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3165 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3167 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3168 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3169 (COPY_TO_REGCLASS VR128:$src, FR64)),
3171 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3172 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3174 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3175 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3176 (COPY_TO_REGCLASS VR128:$src, FR32)),
3178 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3179 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3181 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3182 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3183 (COPY_TO_REGCLASS VR128:$src, FR32)),
3185 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3186 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3190 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3192 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3195 /// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.
3196 multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,
3198 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3199 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3200 [(set FR32:$dst, (OpNode FR32:$src))]>;
3201 // For scalar unary operations, fold a load into the operation
3202 // only in OptForSize mode. It eliminates an instruction, but it also
3203 // eliminates a whole-register clobber (the load), so it introduces a
3204 // partial register update condition.
3205 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3206 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3207 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3208 Requires<[UseSSE1, OptForSize]>;
3209 let Constraints = "$src1 = $dst" in {
3210 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3211 (ins VR128:$src1, VR128:$src2),
3212 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3214 let mayLoad = 1, hasSideEffects = 0 in
3215 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3216 (ins VR128:$src1, ssmem:$src2),
3217 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3222 // Reciprocal approximations. Note that these typically require refinement
3223 // in order to obtain suitable precision.
3224 defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_SQRTS>;
3225 let Predicates = [UseSSE1] in {
3226 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3227 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3230 defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>;
3231 let Predicates = [UseSSE1] in {
3232 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3233 (RCPSSr_Int VR128:$src, VR128:$src)>;
3236 // There is no f64 version of the reciprocal approximation instructions.
3238 //===----------------------------------------------------------------------===//
3239 // SSE 1 & 2 - Non-temporal stores
3240 //===----------------------------------------------------------------------===//
3242 let AddedComplexity = 400 in { // Prefer non-temporal versions
3243 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3244 (ins f128mem:$dst, VR128:$src),
3245 "movntps\t{$src, $dst|$dst, $src}",
3246 [(alignednontemporalstore (v4f32 VR128:$src),
3248 IIC_SSE_MOVNT>, VEX;
3249 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3250 (ins f128mem:$dst, VR128:$src),
3251 "movntpd\t{$src, $dst|$dst, $src}",
3252 [(alignednontemporalstore (v2f64 VR128:$src),
3254 IIC_SSE_MOVNT>, VEX;
3256 let ExeDomain = SSEPackedInt in
3257 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3258 (ins f128mem:$dst, VR128:$src),
3259 "movntdq\t{$src, $dst|$dst, $src}",
3260 [(alignednontemporalstore (v2i64 VR128:$src),
3262 IIC_SSE_MOVNT>, VEX;
3264 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3265 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3267 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3268 (ins f256mem:$dst, VR256:$src),
3269 "movntps\t{$src, $dst|$dst, $src}",
3270 [(alignednontemporalstore (v8f32 VR256:$src),
3272 IIC_SSE_MOVNT>, VEX, VEX_L;
3273 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3274 (ins f256mem:$dst, VR256:$src),
3275 "movntpd\t{$src, $dst|$dst, $src}",
3276 [(alignednontemporalstore (v4f64 VR256:$src),
3278 IIC_SSE_MOVNT>, VEX, VEX_L;
3279 let ExeDomain = SSEPackedInt in
3280 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3281 (ins f256mem:$dst, VR256:$src),
3282 "movntdq\t{$src, $dst|$dst, $src}",
3283 [(alignednontemporalstore (v4i64 VR256:$src),
3285 IIC_SSE_MOVNT>, VEX, VEX_L;
3288 let AddedComplexity = 400 in { // Prefer non-temporal versions
3289 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3290 "movntps\t{$src, $dst|$dst, $src}",
3291 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3293 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3294 "movntpd\t{$src, $dst|$dst, $src}",
3295 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3298 let ExeDomain = SSEPackedInt in
3299 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3300 "movntdq\t{$src, $dst|$dst, $src}",
3301 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3304 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3305 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[UseSSE2]>;
3307 // There is no AVX form for instructions below this point
3308 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3309 "movnti{l}\t{$src, $dst|$dst, $src}",
3310 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3312 TB, Requires<[HasSSE2]>;
3313 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3314 "movnti{q}\t{$src, $dst|$dst, $src}",
3315 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3317 TB, Requires<[HasSSE2]>;
3320 //===----------------------------------------------------------------------===//
3321 // SSE 1 & 2 - Prefetch and memory fence
3322 //===----------------------------------------------------------------------===//
3324 // Prefetch intrinsic.
3325 let Predicates = [HasSSE1] in {
3326 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3327 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3328 IIC_SSE_PREFETCH>, TB;
3329 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3330 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3331 IIC_SSE_PREFETCH>, TB;
3332 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3333 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3334 IIC_SSE_PREFETCH>, TB;
3335 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3336 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3337 IIC_SSE_PREFETCH>, TB;
3341 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3342 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3343 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3345 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3346 // was introduced with SSE2, it's backward compatible.
3347 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
3349 // Load, store, and memory fence
3350 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3351 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3352 TB, Requires<[HasSSE1]>;
3353 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3354 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3355 TB, Requires<[HasSSE2]>;
3356 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3357 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3358 TB, Requires<[HasSSE2]>;
3360 def : Pat<(X86SFence), (SFENCE)>;
3361 def : Pat<(X86LFence), (LFENCE)>;
3362 def : Pat<(X86MFence), (MFENCE)>;
3364 //===----------------------------------------------------------------------===//
3365 // SSE 1 & 2 - Load/Store XCSR register
3366 //===----------------------------------------------------------------------===//
3368 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3369 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3370 IIC_SSE_LDMXCSR>, VEX;
3371 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3372 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3373 IIC_SSE_STMXCSR>, VEX;
3375 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3376 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3378 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3379 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3382 //===---------------------------------------------------------------------===//
3383 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3384 //===---------------------------------------------------------------------===//
3386 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3388 let neverHasSideEffects = 1 in {
3389 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3390 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3392 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3393 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3395 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3396 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3398 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3399 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3404 let isCodeGenOnly = 1, hasSideEffects = 0 in {
3405 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3406 "movdqa\t{$src, $dst|$dst, $src}", [],
3409 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3410 "movdqa\t{$src, $dst|$dst, $src}", [],
3411 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3412 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3413 "movdqu\t{$src, $dst|$dst, $src}", [],
3416 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3417 "movdqu\t{$src, $dst|$dst, $src}", [],
3418 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3421 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3422 neverHasSideEffects = 1 in {
3423 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3424 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3426 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3427 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3429 let Predicates = [HasAVX] in {
3430 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3431 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3433 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3434 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3439 let mayStore = 1, neverHasSideEffects = 1 in {
3440 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3441 (ins i128mem:$dst, VR128:$src),
3442 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3444 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3445 (ins i256mem:$dst, VR256:$src),
3446 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3448 let Predicates = [HasAVX] in {
3449 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3450 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3452 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3453 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3458 let neverHasSideEffects = 1 in
3459 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3460 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3462 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3463 "movdqu\t{$src, $dst|$dst, $src}",
3464 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3467 let isCodeGenOnly = 1, hasSideEffects = 0 in {
3468 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3469 "movdqa\t{$src, $dst|$dst, $src}", [],
3472 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3473 "movdqu\t{$src, $dst|$dst, $src}",
3474 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3477 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3478 neverHasSideEffects = 1 in {
3479 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3480 "movdqa\t{$src, $dst|$dst, $src}",
3481 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3483 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3484 "movdqu\t{$src, $dst|$dst, $src}",
3485 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3487 XS, Requires<[UseSSE2]>;
3490 let mayStore = 1 in {
3491 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3492 "movdqa\t{$src, $dst|$dst, $src}",
3493 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3495 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3496 "movdqu\t{$src, $dst|$dst, $src}",
3497 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3499 XS, Requires<[UseSSE2]>;
3502 } // ExeDomain = SSEPackedInt
3504 let Predicates = [HasAVX] in {
3505 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3506 (VMOVDQUmr addr:$dst, VR128:$src)>;
3507 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3508 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3510 let Predicates = [UseSSE2] in
3511 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3512 (MOVDQUmr addr:$dst, VR128:$src)>;
3514 //===---------------------------------------------------------------------===//
3515 // SSE2 - Packed Integer Arithmetic Instructions
3516 //===---------------------------------------------------------------------===//
3518 def SSE_PMADD : OpndItins<
3519 IIC_SSE_PMADD, IIC_SSE_PMADD
3522 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3524 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3525 RegisterClass RC, PatFrag memop_frag,
3526 X86MemOperand x86memop,
3528 bit IsCommutable = 0,
3530 let isCommutable = IsCommutable in
3531 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3532 (ins RC:$src1, RC:$src2),
3534 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3535 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3536 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>;
3537 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3538 (ins RC:$src1, x86memop:$src2),
3540 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3541 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3542 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3546 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3547 Intrinsic IntId256, OpndItins itins,
3548 bit IsCommutable = 0> {
3549 let Predicates = [HasAVX] in
3550 defm V#NAME# : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3551 VR128, memopv2i64, i128mem, itins,
3552 IsCommutable, 0>, VEX_4V;
3554 let Constraints = "$src1 = $dst" in
3555 defm #NAME# : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3556 i128mem, itins, IsCommutable, 1>;
3558 let Predicates = [HasAVX2] in
3559 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3560 VR256, memopv4i64, i256mem, itins,
3561 IsCommutable, 0>, VEX_4V, VEX_L;
3564 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3565 string OpcodeStr, SDNode OpNode,
3566 SDNode OpNode2, RegisterClass RC,
3567 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3568 ShiftOpndItins itins,
3570 // src2 is always 128-bit
3571 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3572 (ins RC:$src1, VR128:$src2),
3574 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3575 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3576 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3578 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3579 (ins RC:$src1, i128mem:$src2),
3581 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3582 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3583 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3584 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>;
3585 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3586 (ins RC:$src1, i32i8imm:$src2),
3588 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3589 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3590 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))], itins.ri>;
3593 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
3594 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3595 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3596 PatFrag memop_frag, X86MemOperand x86memop,
3598 bit IsCommutable = 0, bit Is2Addr = 1> {
3599 let isCommutable = IsCommutable in
3600 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3601 (ins RC:$src1, RC:$src2),
3603 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3604 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3605 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>;
3606 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3607 (ins RC:$src1, x86memop:$src2),
3609 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3610 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3611 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3612 (bitconvert (memop_frag addr:$src2)))))]>;
3614 } // ExeDomain = SSEPackedInt
3616 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
3617 SSE_INTALU_ITINS_P, 1>;
3618 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
3619 SSE_INTALU_ITINS_P, 1>;
3620 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
3621 SSE_INTALU_ITINS_P, 1>;
3622 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
3623 SSE_INTALUQ_ITINS_P, 1>;
3624 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
3625 SSE_INTMUL_ITINS_P, 1>;
3626 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
3627 SSE_INTALU_ITINS_P, 0>;
3628 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
3629 SSE_INTALU_ITINS_P, 0>;
3630 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
3631 SSE_INTALU_ITINS_P, 0>;
3632 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
3633 SSE_INTALUQ_ITINS_P, 0>;
3634 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
3635 SSE_INTALU_ITINS_P, 0>;
3636 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
3637 SSE_INTALU_ITINS_P, 0>;
3638 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
3639 SSE_INTALU_ITINS_P, 1>;
3640 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
3641 SSE_INTALU_ITINS_P, 1>;
3642 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
3643 SSE_INTALU_ITINS_P, 1>;
3644 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
3645 SSE_INTALU_ITINS_P, 1>;
3648 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
3649 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
3650 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3651 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
3652 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3653 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
3654 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3655 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
3656 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3657 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
3658 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3659 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
3660 defm PMULHUW : PDI_binop_all_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3661 int_x86_avx2_pmulhu_w, SSE_INTMUL_ITINS_P, 1>;
3662 defm PMULHW : PDI_binop_all_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3663 int_x86_avx2_pmulh_w, SSE_INTMUL_ITINS_P, 1>;
3664 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3665 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
3666 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3667 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
3668 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3669 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
3670 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3671 int_x86_avx2_psad_bw, SSE_INTALU_ITINS_P, 1>;
3673 let Predicates = [HasAVX] in
3674 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3675 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3677 let Predicates = [HasAVX2] in
3678 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3679 VR256, memopv4i64, i256mem,
3680 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3681 let Constraints = "$src1 = $dst" in
3682 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3683 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3685 //===---------------------------------------------------------------------===//
3686 // SSE2 - Packed Integer Logical Instructions
3687 //===---------------------------------------------------------------------===//
3689 let Predicates = [HasAVX] in {
3690 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3691 VR128, v8i16, v8i16, bc_v8i16,
3692 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3693 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3694 VR128, v4i32, v4i32, bc_v4i32,
3695 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3696 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3697 VR128, v2i64, v2i64, bc_v2i64,
3698 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3700 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3701 VR128, v8i16, v8i16, bc_v8i16,
3702 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3703 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3704 VR128, v4i32, v4i32, bc_v4i32,
3705 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3706 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3707 VR128, v2i64, v2i64, bc_v2i64,
3708 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3710 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3711 VR128, v8i16, v8i16, bc_v8i16,
3712 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3713 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3714 VR128, v4i32, v4i32, bc_v4i32,
3715 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3717 let ExeDomain = SSEPackedInt in {
3718 // 128-bit logical shifts.
3719 def VPSLLDQri : PDIi8<0x73, MRM7r,
3720 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3721 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3723 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3725 def VPSRLDQri : PDIi8<0x73, MRM3r,
3726 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3727 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3729 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3731 // PSRADQri doesn't exist in SSE[1-3].
3733 } // Predicates = [HasAVX]
3735 let Predicates = [HasAVX2] in {
3736 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3737 VR256, v16i16, v8i16, bc_v8i16,
3738 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3739 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3740 VR256, v8i32, v4i32, bc_v4i32,
3741 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3742 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3743 VR256, v4i64, v2i64, bc_v2i64,
3744 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3746 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3747 VR256, v16i16, v8i16, bc_v8i16,
3748 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3749 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3750 VR256, v8i32, v4i32, bc_v4i32,
3751 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3752 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3753 VR256, v4i64, v2i64, bc_v2i64,
3754 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3756 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3757 VR256, v16i16, v8i16, bc_v8i16,
3758 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3759 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3760 VR256, v8i32, v4i32, bc_v4i32,
3761 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3763 let ExeDomain = SSEPackedInt in {
3764 // 256-bit logical shifts.
3765 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3766 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3767 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3769 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
3771 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3772 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3773 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3775 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
3777 // PSRADQYri doesn't exist in SSE[1-3].
3779 } // Predicates = [HasAVX2]
3781 let Constraints = "$src1 = $dst" in {
3782 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
3783 VR128, v8i16, v8i16, bc_v8i16,
3784 SSE_INTSHIFT_ITINS_P>;
3785 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
3786 VR128, v4i32, v4i32, bc_v4i32,
3787 SSE_INTSHIFT_ITINS_P>;
3788 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
3789 VR128, v2i64, v2i64, bc_v2i64,
3790 SSE_INTSHIFT_ITINS_P>;
3792 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
3793 VR128, v8i16, v8i16, bc_v8i16,
3794 SSE_INTSHIFT_ITINS_P>;
3795 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
3796 VR128, v4i32, v4i32, bc_v4i32,
3797 SSE_INTSHIFT_ITINS_P>;
3798 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
3799 VR128, v2i64, v2i64, bc_v2i64,
3800 SSE_INTSHIFT_ITINS_P>;
3802 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
3803 VR128, v8i16, v8i16, bc_v8i16,
3804 SSE_INTSHIFT_ITINS_P>;
3805 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
3806 VR128, v4i32, v4i32, bc_v4i32,
3807 SSE_INTSHIFT_ITINS_P>;
3809 let ExeDomain = SSEPackedInt in {
3810 // 128-bit logical shifts.
3811 def PSLLDQri : PDIi8<0x73, MRM7r,
3812 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3813 "pslldq\t{$src2, $dst|$dst, $src2}",
3815 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>;
3816 def PSRLDQri : PDIi8<0x73, MRM3r,
3817 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3818 "psrldq\t{$src2, $dst|$dst, $src2}",
3820 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>;
3821 // PSRADQri doesn't exist in SSE[1-3].
3823 } // Constraints = "$src1 = $dst"
3825 let Predicates = [HasAVX] in {
3826 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3827 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3828 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3829 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3830 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3831 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3833 // Shift up / down and insert zero's.
3834 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
3835 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3836 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
3837 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3840 let Predicates = [HasAVX2] in {
3841 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
3842 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
3843 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
3844 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
3847 let Predicates = [UseSSE2] in {
3848 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3849 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3850 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3851 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3852 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3853 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3855 // Shift up / down and insert zero's.
3856 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
3857 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3858 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
3859 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3862 //===---------------------------------------------------------------------===//
3863 // SSE2 - Packed Integer Comparison Instructions
3864 //===---------------------------------------------------------------------===//
3866 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
3867 SSE_INTALU_ITINS_P, 1>;
3868 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
3869 SSE_INTALU_ITINS_P, 1>;
3870 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
3871 SSE_INTALU_ITINS_P, 1>;
3872 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
3873 SSE_INTALU_ITINS_P, 0>;
3874 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
3875 SSE_INTALU_ITINS_P, 0>;
3876 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
3877 SSE_INTALU_ITINS_P, 0>;
3879 //===---------------------------------------------------------------------===//
3880 // SSE2 - Packed Integer Pack Instructions
3881 //===---------------------------------------------------------------------===//
3883 defm PACKSSWB : PDI_binop_all_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
3884 int_x86_avx2_packsswb, SSE_INTALU_ITINS_P, 0>;
3885 defm PACKSSDW : PDI_binop_all_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
3886 int_x86_avx2_packssdw, SSE_INTALU_ITINS_P, 0>;
3887 defm PACKUSWB : PDI_binop_all_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
3888 int_x86_avx2_packuswb, SSE_INTALU_ITINS_P, 0>;
3890 //===---------------------------------------------------------------------===//
3891 // SSE2 - Packed Integer Shuffle Instructions
3892 //===---------------------------------------------------------------------===//
3894 let ExeDomain = SSEPackedInt in {
3895 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, SDNode OpNode> {
3896 def ri : Ii8<0x70, MRMSrcReg,
3897 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
3898 !strconcat(OpcodeStr,
3899 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3900 [(set VR128:$dst, (vt (OpNode VR128:$src1, (i8 imm:$src2))))],
3902 def mi : Ii8<0x70, MRMSrcMem,
3903 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
3904 !strconcat(OpcodeStr,
3905 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3907 (vt (OpNode (bitconvert (memopv2i64 addr:$src1)),
3912 multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, SDNode OpNode> {
3913 def Yri : Ii8<0x70, MRMSrcReg,
3914 (outs VR256:$dst), (ins VR256:$src1, i8imm:$src2),
3915 !strconcat(OpcodeStr,
3916 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3917 [(set VR256:$dst, (vt (OpNode VR256:$src1, (i8 imm:$src2))))]>;
3918 def Ymi : Ii8<0x70, MRMSrcMem,
3919 (outs VR256:$dst), (ins i256mem:$src1, i8imm:$src2),
3920 !strconcat(OpcodeStr,
3921 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3923 (vt (OpNode (bitconvert (memopv4i64 addr:$src1)),
3924 (i8 imm:$src2))))]>;
3926 } // ExeDomain = SSEPackedInt
3928 let Predicates = [HasAVX] in {
3929 let AddedComplexity = 5 in
3930 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, X86PShufd>, TB, OpSize, VEX;
3932 // SSE2 with ImmT == Imm8 and XS prefix.
3933 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, X86PShufhw>, XS, VEX;
3935 // SSE2 with ImmT == Imm8 and XD prefix.
3936 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, X86PShuflw>, XD, VEX;
3938 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
3939 (VPSHUFDmi addr:$src1, imm:$imm)>;
3940 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3941 (VPSHUFDri VR128:$src1, imm:$imm)>;
3944 let Predicates = [HasAVX2] in {
3945 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, X86PShufd>,
3946 TB, OpSize, VEX,VEX_L;
3947 defm VPSHUFHW : sse2_pshuffle_y<"vpshufhw", v16i16, X86PShufhw>,
3949 defm VPSHUFLW : sse2_pshuffle_y<"vpshuflw", v16i16, X86PShuflw>,
3953 let Predicates = [UseSSE2] in {
3954 let AddedComplexity = 5 in
3955 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, X86PShufd>, TB, OpSize;
3957 // SSE2 with ImmT == Imm8 and XS prefix.
3958 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, X86PShufhw>, XS;
3960 // SSE2 with ImmT == Imm8 and XD prefix.
3961 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, X86PShuflw>, XD;
3963 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
3964 (PSHUFDmi addr:$src1, imm:$imm)>;
3965 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3966 (PSHUFDri VR128:$src1, imm:$imm)>;
3969 //===---------------------------------------------------------------------===//
3970 // SSE2 - Packed Integer Unpack Instructions
3971 //===---------------------------------------------------------------------===//
3973 let ExeDomain = SSEPackedInt in {
3974 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
3975 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
3976 def rr : PDI<opc, MRMSrcReg,
3977 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3979 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3980 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3981 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
3983 def rm : PDI<opc, MRMSrcMem,
3984 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3986 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3987 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3988 [(set VR128:$dst, (OpNode VR128:$src1,
3989 (bc_frag (memopv2i64
3994 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
3995 SDNode OpNode, PatFrag bc_frag> {
3996 def Yrr : PDI<opc, MRMSrcReg,
3997 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
3998 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3999 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
4000 def Yrm : PDI<opc, MRMSrcMem,
4001 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4002 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4003 [(set VR256:$dst, (OpNode VR256:$src1,
4004 (bc_frag (memopv4i64 addr:$src2))))]>;
4007 let Predicates = [HasAVX] in {
4008 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4009 bc_v16i8, 0>, VEX_4V;
4010 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4011 bc_v8i16, 0>, VEX_4V;
4012 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4013 bc_v4i32, 0>, VEX_4V;
4014 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4015 bc_v2i64, 0>, VEX_4V;
4017 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4018 bc_v16i8, 0>, VEX_4V;
4019 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4020 bc_v8i16, 0>, VEX_4V;
4021 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4022 bc_v4i32, 0>, VEX_4V;
4023 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4024 bc_v2i64, 0>, VEX_4V;
4027 let Predicates = [HasAVX2] in {
4028 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4029 bc_v32i8>, VEX_4V, VEX_L;
4030 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4031 bc_v16i16>, VEX_4V, VEX_L;
4032 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4033 bc_v8i32>, VEX_4V, VEX_L;
4034 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4035 bc_v4i64>, VEX_4V, VEX_L;
4037 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4038 bc_v32i8>, VEX_4V, VEX_L;
4039 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4040 bc_v16i16>, VEX_4V, VEX_L;
4041 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4042 bc_v8i32>, VEX_4V, VEX_L;
4043 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4044 bc_v4i64>, VEX_4V, VEX_L;
4047 let Constraints = "$src1 = $dst" in {
4048 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4050 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4052 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4054 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4057 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4059 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4061 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4063 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4066 } // ExeDomain = SSEPackedInt
4068 //===---------------------------------------------------------------------===//
4069 // SSE2 - Packed Integer Extract and Insert
4070 //===---------------------------------------------------------------------===//
4072 let ExeDomain = SSEPackedInt in {
4073 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4074 def rri : Ii8<0xC4, MRMSrcReg,
4075 (outs VR128:$dst), (ins VR128:$src1,
4076 GR32:$src2, i32i8imm:$src3),
4078 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4079 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4081 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>;
4082 def rmi : Ii8<0xC4, MRMSrcMem,
4083 (outs VR128:$dst), (ins VR128:$src1,
4084 i16mem:$src2, i32i8imm:$src3),
4086 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4087 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4089 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4090 imm:$src3))], IIC_SSE_PINSRW>;
4094 let Predicates = [HasAVX] in
4095 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4096 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4097 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4098 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4099 imm:$src2))]>, TB, OpSize, VEX;
4100 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4101 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4102 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4103 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4104 imm:$src2))], IIC_SSE_PEXTRW>;
4107 let Predicates = [HasAVX] in {
4108 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4109 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4110 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4111 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4112 []>, TB, OpSize, VEX_4V;
4115 let Constraints = "$src1 = $dst" in
4116 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[UseSSE2]>;
4118 } // ExeDomain = SSEPackedInt
4120 //===---------------------------------------------------------------------===//
4121 // SSE2 - Packed Mask Creation
4122 //===---------------------------------------------------------------------===//
4124 let ExeDomain = SSEPackedInt in {
4126 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4127 "pmovmskb\t{$src, $dst|$dst, $src}",
4128 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4129 IIC_SSE_MOVMSK>, VEX;
4130 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4131 "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;
4133 let Predicates = [HasAVX2] in {
4134 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4135 "pmovmskb\t{$src, $dst|$dst, $src}",
4136 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX, VEX_L;
4137 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4138 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4141 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4142 "pmovmskb\t{$src, $dst|$dst, $src}",
4143 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4146 } // ExeDomain = SSEPackedInt
4148 //===---------------------------------------------------------------------===//
4149 // SSE2 - Conditional Store
4150 //===---------------------------------------------------------------------===//
4152 let ExeDomain = SSEPackedInt in {
4155 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4156 (ins VR128:$src, VR128:$mask),
4157 "maskmovdqu\t{$mask, $src|$src, $mask}",
4158 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4159 IIC_SSE_MASKMOV>, VEX;
4161 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4162 (ins VR128:$src, VR128:$mask),
4163 "maskmovdqu\t{$mask, $src|$src, $mask}",
4164 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4165 IIC_SSE_MASKMOV>, VEX;
4168 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4169 "maskmovdqu\t{$mask, $src|$src, $mask}",
4170 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4173 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4174 "maskmovdqu\t{$mask, $src|$src, $mask}",
4175 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4178 } // ExeDomain = SSEPackedInt
4180 //===---------------------------------------------------------------------===//
4181 // SSE2 - Move Doubleword
4182 //===---------------------------------------------------------------------===//
4184 //===---------------------------------------------------------------------===//
4185 // Move Int Doubleword to Packed Double Int
4187 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4188 "movd\t{$src, $dst|$dst, $src}",
4190 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4192 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4193 "movd\t{$src, $dst|$dst, $src}",
4195 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4198 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4199 "mov{d|q}\t{$src, $dst|$dst, $src}",
4201 (v2i64 (scalar_to_vector GR64:$src)))],
4202 IIC_SSE_MOVDQ>, VEX;
4203 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4204 "mov{d|q}\t{$src, $dst|$dst, $src}",
4205 [(set FR64:$dst, (bitconvert GR64:$src))],
4206 IIC_SSE_MOVDQ>, VEX;
4208 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4209 "movd\t{$src, $dst|$dst, $src}",
4211 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>;
4212 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4213 "movd\t{$src, $dst|$dst, $src}",
4215 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4217 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4218 "mov{d|q}\t{$src, $dst|$dst, $src}",
4220 (v2i64 (scalar_to_vector GR64:$src)))],
4222 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4223 "mov{d|q}\t{$src, $dst|$dst, $src}",
4224 [(set FR64:$dst, (bitconvert GR64:$src))],
4227 //===---------------------------------------------------------------------===//
4228 // Move Int Doubleword to Single Scalar
4230 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4231 "movd\t{$src, $dst|$dst, $src}",
4232 [(set FR32:$dst, (bitconvert GR32:$src))],
4233 IIC_SSE_MOVDQ>, VEX;
4235 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4236 "movd\t{$src, $dst|$dst, $src}",
4237 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4240 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4241 "movd\t{$src, $dst|$dst, $src}",
4242 [(set FR32:$dst, (bitconvert GR32:$src))],
4245 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4246 "movd\t{$src, $dst|$dst, $src}",
4247 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4250 //===---------------------------------------------------------------------===//
4251 // Move Packed Doubleword Int to Packed Double Int
4253 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4254 "movd\t{$src, $dst|$dst, $src}",
4255 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4256 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX;
4257 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4258 (ins i32mem:$dst, VR128:$src),
4259 "movd\t{$src, $dst|$dst, $src}",
4260 [(store (i32 (vector_extract (v4i32 VR128:$src),
4261 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4263 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4264 "movd\t{$src, $dst|$dst, $src}",
4265 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4266 (iPTR 0)))], IIC_SSE_MOVD_ToGP>;
4267 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4268 "movd\t{$src, $dst|$dst, $src}",
4269 [(store (i32 (vector_extract (v4i32 VR128:$src),
4270 (iPTR 0))), addr:$dst)],
4273 //===---------------------------------------------------------------------===//
4274 // Move Packed Doubleword Int first element to Doubleword Int
4276 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4277 "vmov{d|q}\t{$src, $dst|$dst, $src}",
4278 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4281 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4283 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4284 "mov{d|q}\t{$src, $dst|$dst, $src}",
4285 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4289 //===---------------------------------------------------------------------===//
4290 // Bitcast FR64 <-> GR64
4292 let Predicates = [HasAVX] in
4293 def VMOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4294 "vmovq\t{$src, $dst|$dst, $src}",
4295 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4297 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4298 "mov{d|q}\t{$src, $dst|$dst, $src}",
4299 [(set GR64:$dst, (bitconvert FR64:$src))],
4300 IIC_SSE_MOVDQ>, VEX;
4301 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4302 "movq\t{$src, $dst|$dst, $src}",
4303 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4304 IIC_SSE_MOVDQ>, VEX;
4306 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4307 "movq\t{$src, $dst|$dst, $src}",
4308 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4310 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4311 "mov{d|q}\t{$src, $dst|$dst, $src}",
4312 [(set GR64:$dst, (bitconvert FR64:$src))],
4314 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4315 "movq\t{$src, $dst|$dst, $src}",
4316 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4319 //===---------------------------------------------------------------------===//
4320 // Move Scalar Single to Double Int
4322 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4323 "movd\t{$src, $dst|$dst, $src}",
4324 [(set GR32:$dst, (bitconvert FR32:$src))],
4325 IIC_SSE_MOVD_ToGP>, VEX;
4326 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4327 "movd\t{$src, $dst|$dst, $src}",
4328 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4329 IIC_SSE_MOVDQ>, VEX;
4330 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4331 "movd\t{$src, $dst|$dst, $src}",
4332 [(set GR32:$dst, (bitconvert FR32:$src))],
4334 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4335 "movd\t{$src, $dst|$dst, $src}",
4336 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4339 //===---------------------------------------------------------------------===//
4340 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4342 let AddedComplexity = 15 in {
4343 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4344 "movd\t{$src, $dst|$dst, $src}",
4345 [(set VR128:$dst, (v4i32 (X86vzmovl
4346 (v4i32 (scalar_to_vector GR32:$src)))))],
4347 IIC_SSE_MOVDQ>, VEX;
4348 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4349 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4350 [(set VR128:$dst, (v2i64 (X86vzmovl
4351 (v2i64 (scalar_to_vector GR64:$src)))))],
4355 let AddedComplexity = 15 in {
4356 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4357 "movd\t{$src, $dst|$dst, $src}",
4358 [(set VR128:$dst, (v4i32 (X86vzmovl
4359 (v4i32 (scalar_to_vector GR32:$src)))))],
4361 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4362 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4363 [(set VR128:$dst, (v2i64 (X86vzmovl
4364 (v2i64 (scalar_to_vector GR64:$src)))))],
4368 let AddedComplexity = 20 in {
4369 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4370 "movd\t{$src, $dst|$dst, $src}",
4372 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4373 (loadi32 addr:$src))))))],
4374 IIC_SSE_MOVDQ>, VEX;
4375 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4376 "movd\t{$src, $dst|$dst, $src}",
4378 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4379 (loadi32 addr:$src))))))],
4383 let Predicates = [HasAVX] in {
4384 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4385 let AddedComplexity = 20 in {
4386 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4387 (VMOVZDI2PDIrm addr:$src)>;
4388 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4389 (VMOVZDI2PDIrm addr:$src)>;
4391 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4392 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4393 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4394 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4395 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4396 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4397 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4400 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4401 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4402 (MOVZDI2PDIrm addr:$src)>;
4403 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4404 (MOVZDI2PDIrm addr:$src)>;
4407 // These are the correct encodings of the instructions so that we know how to
4408 // read correct assembly, even though we continue to emit the wrong ones for
4409 // compatibility with Darwin's buggy assembler.
4410 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4411 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4412 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4413 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4414 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4415 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4416 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4417 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4418 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4419 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4420 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4421 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4423 //===---------------------------------------------------------------------===//
4424 // SSE2 - Move Quadword
4425 //===---------------------------------------------------------------------===//
4427 //===---------------------------------------------------------------------===//
4428 // Move Quadword Int to Packed Quadword Int
4430 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4431 "vmovq\t{$src, $dst|$dst, $src}",
4433 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4434 VEX, Requires<[HasAVX]>;
4435 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4436 "movq\t{$src, $dst|$dst, $src}",
4438 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4440 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4442 //===---------------------------------------------------------------------===//
4443 // Move Packed Quadword Int to Quadword Int
4445 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4446 "movq\t{$src, $dst|$dst, $src}",
4447 [(store (i64 (vector_extract (v2i64 VR128:$src),
4448 (iPTR 0))), addr:$dst)],
4449 IIC_SSE_MOVDQ>, VEX;
4450 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4451 "movq\t{$src, $dst|$dst, $src}",
4452 [(store (i64 (vector_extract (v2i64 VR128:$src),
4453 (iPTR 0))), addr:$dst)],
4456 //===---------------------------------------------------------------------===//
4457 // Store / copy lower 64-bits of a XMM register.
4459 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4460 "movq\t{$src, $dst|$dst, $src}",
4461 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4462 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4463 "movq\t{$src, $dst|$dst, $src}",
4464 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4467 let AddedComplexity = 20 in
4468 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4469 "vmovq\t{$src, $dst|$dst, $src}",
4471 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4472 (loadi64 addr:$src))))))],
4474 XS, VEX, Requires<[HasAVX]>;
4476 let AddedComplexity = 20 in
4477 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4478 "movq\t{$src, $dst|$dst, $src}",
4480 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4481 (loadi64 addr:$src))))))],
4483 XS, Requires<[UseSSE2]>;
4485 let Predicates = [HasAVX], AddedComplexity = 20 in {
4486 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4487 (VMOVZQI2PQIrm addr:$src)>;
4488 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4489 (VMOVZQI2PQIrm addr:$src)>;
4490 def : Pat<(v2i64 (X86vzload addr:$src)),
4491 (VMOVZQI2PQIrm addr:$src)>;
4494 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4495 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4496 (MOVZQI2PQIrm addr:$src)>;
4497 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4498 (MOVZQI2PQIrm addr:$src)>;
4499 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4502 let Predicates = [HasAVX] in {
4503 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4504 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4505 def : Pat<(v4i64 (X86vzload addr:$src)),
4506 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4509 //===---------------------------------------------------------------------===//
4510 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4511 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4513 let AddedComplexity = 15 in
4514 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4515 "vmovq\t{$src, $dst|$dst, $src}",
4516 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4518 XS, VEX, Requires<[HasAVX]>;
4519 let AddedComplexity = 15 in
4520 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4521 "movq\t{$src, $dst|$dst, $src}",
4522 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4524 XS, Requires<[UseSSE2]>;
4526 let AddedComplexity = 20 in
4527 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4528 "vmovq\t{$src, $dst|$dst, $src}",
4529 [(set VR128:$dst, (v2i64 (X86vzmovl
4530 (loadv2i64 addr:$src))))],
4532 XS, VEX, Requires<[HasAVX]>;
4533 let AddedComplexity = 20 in {
4534 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4535 "movq\t{$src, $dst|$dst, $src}",
4536 [(set VR128:$dst, (v2i64 (X86vzmovl
4537 (loadv2i64 addr:$src))))],
4539 XS, Requires<[UseSSE2]>;
4542 let AddedComplexity = 20 in {
4543 let Predicates = [HasAVX] in {
4544 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4545 (VMOVZPQILo2PQIrm addr:$src)>;
4546 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4547 (VMOVZPQILo2PQIrr VR128:$src)>;
4549 let Predicates = [UseSSE2] in {
4550 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4551 (MOVZPQILo2PQIrm addr:$src)>;
4552 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4553 (MOVZPQILo2PQIrr VR128:$src)>;
4557 // Instructions to match in the assembler
4558 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4559 "movq\t{$src, $dst|$dst, $src}", [],
4560 IIC_SSE_MOVDQ>, VEX, VEX_W;
4561 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4562 "movq\t{$src, $dst|$dst, $src}", [],
4563 IIC_SSE_MOVDQ>, VEX, VEX_W;
4564 // Recognize "movd" with GR64 destination, but encode as a "movq"
4565 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4566 "movd\t{$src, $dst|$dst, $src}", [],
4567 IIC_SSE_MOVDQ>, VEX, VEX_W;
4569 // Instructions for the disassembler
4570 // xr = XMM register
4573 let Predicates = [HasAVX] in
4574 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4575 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4576 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4577 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, XS;
4579 //===---------------------------------------------------------------------===//
4580 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4581 //===---------------------------------------------------------------------===//
4582 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4583 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4584 X86MemOperand x86memop> {
4585 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4586 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4587 [(set RC:$dst, (vt (OpNode RC:$src)))],
4589 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4590 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4591 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4595 let Predicates = [HasAVX] in {
4596 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4597 v4f32, VR128, memopv4f32, f128mem>, VEX;
4598 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4599 v4f32, VR128, memopv4f32, f128mem>, VEX;
4600 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4601 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4602 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4603 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4605 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4606 memopv4f32, f128mem>;
4607 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4608 memopv4f32, f128mem>;
4610 let Predicates = [HasAVX] in {
4611 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4612 (VMOVSHDUPrr VR128:$src)>;
4613 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4614 (VMOVSHDUPrm addr:$src)>;
4615 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4616 (VMOVSLDUPrr VR128:$src)>;
4617 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4618 (VMOVSLDUPrm addr:$src)>;
4619 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4620 (VMOVSHDUPYrr VR256:$src)>;
4621 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4622 (VMOVSHDUPYrm addr:$src)>;
4623 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4624 (VMOVSLDUPYrr VR256:$src)>;
4625 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4626 (VMOVSLDUPYrm addr:$src)>;
4629 let Predicates = [UseSSE3] in {
4630 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4631 (MOVSHDUPrr VR128:$src)>;
4632 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4633 (MOVSHDUPrm addr:$src)>;
4634 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4635 (MOVSLDUPrr VR128:$src)>;
4636 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4637 (MOVSLDUPrm addr:$src)>;
4640 //===---------------------------------------------------------------------===//
4641 // SSE3 - Replicate Double FP - MOVDDUP
4642 //===---------------------------------------------------------------------===//
4644 multiclass sse3_replicate_dfp<string OpcodeStr> {
4645 let neverHasSideEffects = 1 in
4646 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4647 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4648 [], IIC_SSE_MOV_LH>;
4649 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4650 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4653 (scalar_to_vector (loadf64 addr:$src)))))],
4657 // FIXME: Merge with above classe when there're patterns for the ymm version
4658 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4659 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4660 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4661 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>;
4662 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4663 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4666 (scalar_to_vector (loadf64 addr:$src)))))]>;
4669 let Predicates = [HasAVX] in {
4670 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4671 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
4674 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4676 let Predicates = [HasAVX] in {
4677 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4678 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4679 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4680 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4681 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4682 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4683 def : Pat<(X86Movddup (bc_v2f64
4684 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4685 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4688 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4689 (VMOVDDUPYrm addr:$src)>;
4690 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4691 (VMOVDDUPYrm addr:$src)>;
4692 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4693 (VMOVDDUPYrm addr:$src)>;
4694 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4695 (VMOVDDUPYrr VR256:$src)>;
4698 let Predicates = [UseSSE3] in {
4699 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4700 (MOVDDUPrm addr:$src)>;
4701 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4702 (MOVDDUPrm addr:$src)>;
4703 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4704 (MOVDDUPrm addr:$src)>;
4705 def : Pat<(X86Movddup (bc_v2f64
4706 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4707 (MOVDDUPrm addr:$src)>;
4710 //===---------------------------------------------------------------------===//
4711 // SSE3 - Move Unaligned Integer
4712 //===---------------------------------------------------------------------===//
4714 let Predicates = [HasAVX] in {
4715 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4716 "vlddqu\t{$src, $dst|$dst, $src}",
4717 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4718 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4719 "vlddqu\t{$src, $dst|$dst, $src}",
4720 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
4723 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4724 "lddqu\t{$src, $dst|$dst, $src}",
4725 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
4728 //===---------------------------------------------------------------------===//
4729 // SSE3 - Arithmetic
4730 //===---------------------------------------------------------------------===//
4732 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4733 X86MemOperand x86memop, OpndItins itins,
4735 def rr : I<0xD0, MRMSrcReg,
4736 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4738 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4739 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4740 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>;
4741 def rm : I<0xD0, MRMSrcMem,
4742 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4744 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4745 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4746 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>;
4749 let Predicates = [HasAVX] in {
4750 let ExeDomain = SSEPackedSingle in {
4751 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4752 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
4753 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4754 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V, VEX_L;
4756 let ExeDomain = SSEPackedDouble in {
4757 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4758 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
4759 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
4760 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V, VEX_L;
4763 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
4764 let ExeDomain = SSEPackedSingle in
4765 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
4766 f128mem, SSE_ALU_F32P>, TB, XD;
4767 let ExeDomain = SSEPackedDouble in
4768 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
4769 f128mem, SSE_ALU_F64P>, TB, OpSize;
4772 //===---------------------------------------------------------------------===//
4773 // SSE3 Instructions
4774 //===---------------------------------------------------------------------===//
4777 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4778 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4779 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4781 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4782 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4783 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
4785 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4787 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4788 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4789 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
4790 IIC_SSE_HADDSUB_RM>;
4792 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4793 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4794 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4796 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4797 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4798 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
4800 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4802 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4803 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4804 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
4805 IIC_SSE_HADDSUB_RM>;
4808 let Predicates = [HasAVX] in {
4809 let ExeDomain = SSEPackedSingle in {
4810 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
4811 X86fhadd, 0>, VEX_4V;
4812 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
4813 X86fhsub, 0>, VEX_4V;
4814 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
4815 X86fhadd, 0>, VEX_4V, VEX_L;
4816 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
4817 X86fhsub, 0>, VEX_4V, VEX_L;
4819 let ExeDomain = SSEPackedDouble in {
4820 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
4821 X86fhadd, 0>, VEX_4V;
4822 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
4823 X86fhsub, 0>, VEX_4V;
4824 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
4825 X86fhadd, 0>, VEX_4V, VEX_L;
4826 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
4827 X86fhsub, 0>, VEX_4V, VEX_L;
4831 let Constraints = "$src1 = $dst" in {
4832 let ExeDomain = SSEPackedSingle in {
4833 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
4834 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
4836 let ExeDomain = SSEPackedDouble in {
4837 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
4838 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
4842 //===---------------------------------------------------------------------===//
4843 // SSSE3 - Packed Absolute Instructions
4844 //===---------------------------------------------------------------------===//
4847 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
4848 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
4849 Intrinsic IntId128> {
4850 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4852 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4853 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
4856 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4858 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4861 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
4865 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
4866 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
4867 Intrinsic IntId256> {
4868 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
4870 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4871 [(set VR256:$dst, (IntId256 VR256:$src))]>,
4874 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
4876 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4879 (bitconvert (memopv4i64 addr:$src))))]>, OpSize;
4882 let Predicates = [HasAVX] in {
4883 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
4884 int_x86_ssse3_pabs_b_128>, VEX;
4885 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
4886 int_x86_ssse3_pabs_w_128>, VEX;
4887 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
4888 int_x86_ssse3_pabs_d_128>, VEX;
4891 let Predicates = [HasAVX2] in {
4892 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
4893 int_x86_avx2_pabs_b>, VEX, VEX_L;
4894 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
4895 int_x86_avx2_pabs_w>, VEX, VEX_L;
4896 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
4897 int_x86_avx2_pabs_d>, VEX, VEX_L;
4900 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
4901 int_x86_ssse3_pabs_b_128>;
4902 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
4903 int_x86_ssse3_pabs_w_128>;
4904 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
4905 int_x86_ssse3_pabs_d_128>;
4907 //===---------------------------------------------------------------------===//
4908 // SSSE3 - Packed Binary Operator Instructions
4909 //===---------------------------------------------------------------------===//
4911 def SSE_PHADDSUBD : OpndItins<
4912 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
4914 def SSE_PHADDSUBSW : OpndItins<
4915 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
4917 def SSE_PHADDSUBW : OpndItins<
4918 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
4920 def SSE_PSHUFB : OpndItins<
4921 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
4923 def SSE_PSIGN : OpndItins<
4924 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
4926 def SSE_PMULHRSW : OpndItins<
4927 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
4930 /// SS3I_binop_rm - Simple SSSE3 bin op
4931 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4932 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
4933 X86MemOperand x86memop, OpndItins itins,
4935 let isCommutable = 1 in
4936 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
4937 (ins RC:$src1, RC:$src2),
4939 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4940 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4941 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
4943 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
4944 (ins RC:$src1, x86memop:$src2),
4946 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4947 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4949 (OpVT (OpNode RC:$src1,
4950 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize;
4953 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
4954 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
4955 Intrinsic IntId128, OpndItins itins,
4957 let isCommutable = 1 in
4958 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4959 (ins VR128:$src1, VR128:$src2),
4961 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4962 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4963 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4965 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4966 (ins VR128:$src1, i128mem:$src2),
4968 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4969 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4971 (IntId128 VR128:$src1,
4972 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
4975 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
4976 Intrinsic IntId256> {
4977 let isCommutable = 1 in
4978 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
4979 (ins VR256:$src1, VR256:$src2),
4980 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4981 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
4983 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
4984 (ins VR256:$src1, i256mem:$src2),
4985 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4987 (IntId256 VR256:$src1,
4988 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
4991 let ImmT = NoImm, Predicates = [HasAVX] in {
4992 let isCommutable = 0 in {
4993 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
4994 memopv2i64, i128mem,
4995 SSE_PHADDSUBW, 0>, VEX_4V;
4996 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
4997 memopv2i64, i128mem,
4998 SSE_PHADDSUBD, 0>, VEX_4V;
4999 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5000 memopv2i64, i128mem,
5001 SSE_PHADDSUBW, 0>, VEX_4V;
5002 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5003 memopv2i64, i128mem,
5004 SSE_PHADDSUBD, 0>, VEX_4V;
5005 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5006 memopv2i64, i128mem,
5007 SSE_PSIGN, 0>, VEX_4V;
5008 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5009 memopv2i64, i128mem,
5010 SSE_PSIGN, 0>, VEX_4V;
5011 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5012 memopv2i64, i128mem,
5013 SSE_PSIGN, 0>, VEX_4V;
5014 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5015 memopv2i64, i128mem,
5016 SSE_PSHUFB, 0>, VEX_4V;
5017 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5018 int_x86_ssse3_phadd_sw_128,
5019 SSE_PHADDSUBSW, 0>, VEX_4V;
5020 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5021 int_x86_ssse3_phsub_sw_128,
5022 SSE_PHADDSUBSW, 0>, VEX_4V;
5023 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5024 int_x86_ssse3_pmadd_ub_sw_128,
5025 SSE_PMADD, 0>, VEX_4V;
5027 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5028 int_x86_ssse3_pmul_hr_sw_128,
5029 SSE_PMULHRSW, 0>, VEX_4V;
5032 let ImmT = NoImm, Predicates = [HasAVX2] in {
5033 let isCommutable = 0 in {
5034 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5035 memopv4i64, i256mem,
5036 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5037 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5038 memopv4i64, i256mem,
5039 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5040 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5041 memopv4i64, i256mem,
5042 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5043 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5044 memopv4i64, i256mem,
5045 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5046 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5047 memopv4i64, i256mem,
5048 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5049 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5050 memopv4i64, i256mem,
5051 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5052 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5053 memopv4i64, i256mem,
5054 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5055 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5056 memopv4i64, i256mem,
5057 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5058 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5059 int_x86_avx2_phadd_sw>, VEX_4V, VEX_L;
5060 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5061 int_x86_avx2_phsub_sw>, VEX_4V, VEX_L;
5062 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5063 int_x86_avx2_pmadd_ub_sw>, VEX_4V, VEX_L;
5065 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5066 int_x86_avx2_pmul_hr_sw>, VEX_4V, VEX_L;
5069 // None of these have i8 immediate fields.
5070 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5071 let isCommutable = 0 in {
5072 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5073 memopv2i64, i128mem, SSE_PHADDSUBW>;
5074 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5075 memopv2i64, i128mem, SSE_PHADDSUBD>;
5076 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5077 memopv2i64, i128mem, SSE_PHADDSUBW>;
5078 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5079 memopv2i64, i128mem, SSE_PHADDSUBD>;
5080 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5081 memopv2i64, i128mem, SSE_PSIGN>;
5082 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5083 memopv2i64, i128mem, SSE_PSIGN>;
5084 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5085 memopv2i64, i128mem, SSE_PSIGN>;
5086 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5087 memopv2i64, i128mem, SSE_PSHUFB>;
5088 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5089 int_x86_ssse3_phadd_sw_128,
5091 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5092 int_x86_ssse3_phsub_sw_128,
5094 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5095 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5097 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5098 int_x86_ssse3_pmul_hr_sw_128,
5102 //===---------------------------------------------------------------------===//
5103 // SSSE3 - Packed Align Instruction Patterns
5104 //===---------------------------------------------------------------------===//
5106 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
5107 let neverHasSideEffects = 1 in {
5108 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5109 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5111 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5113 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5114 [], IIC_SSE_PALIGNR>, OpSize;
5116 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5117 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5119 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5121 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5122 [], IIC_SSE_PALIGNR>, OpSize;
5126 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
5127 let neverHasSideEffects = 1 in {
5128 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5129 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5131 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5134 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5135 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5137 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5142 let Predicates = [HasAVX] in
5143 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5144 let Predicates = [HasAVX2] in
5145 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V, VEX_L;
5146 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5147 defm PALIGN : ssse3_palign<"palignr">;
5149 let Predicates = [HasAVX2] in {
5150 def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5151 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5152 def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5153 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5154 def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5155 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5156 def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5157 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5160 let Predicates = [HasAVX] in {
5161 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5162 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5163 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5164 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5165 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5166 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5167 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5168 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5171 let Predicates = [UseSSSE3] in {
5172 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5173 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5174 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5175 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5176 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5177 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5178 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5179 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5182 //===---------------------------------------------------------------------===//
5183 // SSSE3 - Thread synchronization
5184 //===---------------------------------------------------------------------===//
5186 let usesCustomInserter = 1 in {
5187 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5188 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5189 Requires<[HasSSE3]>;
5192 let Uses = [EAX, ECX, EDX] in
5193 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5194 TB, Requires<[HasSSE3]>;
5195 let Uses = [ECX, EAX] in
5196 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5197 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5198 TB, Requires<[HasSSE3]>;
5200 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5201 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5203 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5204 Requires<[In32BitMode]>;
5205 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5206 Requires<[In64BitMode]>;
5208 //===----------------------------------------------------------------------===//
5209 // SSE4.1 - Packed Move with Sign/Zero Extend
5210 //===----------------------------------------------------------------------===//
5212 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5213 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5214 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5215 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5217 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5218 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5220 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5224 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5226 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5227 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5228 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5230 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5231 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5232 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5235 let Predicates = [HasAVX] in {
5236 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5238 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5240 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5242 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5244 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5246 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5250 let Predicates = [HasAVX2] in {
5251 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5252 int_x86_avx2_pmovsxbw>, VEX, VEX_L;
5253 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5254 int_x86_avx2_pmovsxwd>, VEX, VEX_L;
5255 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5256 int_x86_avx2_pmovsxdq>, VEX, VEX_L;
5257 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5258 int_x86_avx2_pmovzxbw>, VEX, VEX_L;
5259 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5260 int_x86_avx2_pmovzxwd>, VEX, VEX_L;
5261 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5262 int_x86_avx2_pmovzxdq>, VEX, VEX_L;
5265 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5266 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5267 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5268 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5269 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5270 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5272 let Predicates = [HasAVX] in {
5273 // Common patterns involving scalar load.
5274 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5275 (VPMOVSXBWrm addr:$src)>;
5276 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5277 (VPMOVSXBWrm addr:$src)>;
5278 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5279 (VPMOVSXBWrm addr:$src)>;
5281 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5282 (VPMOVSXWDrm addr:$src)>;
5283 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5284 (VPMOVSXWDrm addr:$src)>;
5285 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5286 (VPMOVSXWDrm addr:$src)>;
5288 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5289 (VPMOVSXDQrm addr:$src)>;
5290 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5291 (VPMOVSXDQrm addr:$src)>;
5292 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5293 (VPMOVSXDQrm addr:$src)>;
5295 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5296 (VPMOVZXBWrm addr:$src)>;
5297 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5298 (VPMOVZXBWrm addr:$src)>;
5299 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5300 (VPMOVZXBWrm addr:$src)>;
5302 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5303 (VPMOVZXWDrm addr:$src)>;
5304 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5305 (VPMOVZXWDrm addr:$src)>;
5306 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5307 (VPMOVZXWDrm addr:$src)>;
5309 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5310 (VPMOVZXDQrm addr:$src)>;
5311 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5312 (VPMOVZXDQrm addr:$src)>;
5313 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5314 (VPMOVZXDQrm addr:$src)>;
5317 let Predicates = [UseSSE41] in {
5318 // Common patterns involving scalar load.
5319 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5320 (PMOVSXBWrm addr:$src)>;
5321 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5322 (PMOVSXBWrm addr:$src)>;
5323 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5324 (PMOVSXBWrm addr:$src)>;
5326 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5327 (PMOVSXWDrm addr:$src)>;
5328 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5329 (PMOVSXWDrm addr:$src)>;
5330 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5331 (PMOVSXWDrm addr:$src)>;
5333 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5334 (PMOVSXDQrm addr:$src)>;
5335 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5336 (PMOVSXDQrm addr:$src)>;
5337 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5338 (PMOVSXDQrm addr:$src)>;
5340 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5341 (PMOVZXBWrm addr:$src)>;
5342 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5343 (PMOVZXBWrm addr:$src)>;
5344 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5345 (PMOVZXBWrm addr:$src)>;
5347 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5348 (PMOVZXWDrm addr:$src)>;
5349 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5350 (PMOVZXWDrm addr:$src)>;
5351 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5352 (PMOVZXWDrm addr:$src)>;
5354 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5355 (PMOVZXDQrm addr:$src)>;
5356 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5357 (PMOVZXDQrm addr:$src)>;
5358 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5359 (PMOVZXDQrm addr:$src)>;
5362 let Predicates = [HasAVX2] in {
5363 let AddedComplexity = 15 in {
5364 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5365 (VPMOVZXDQYrr VR128:$src)>;
5366 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5367 (VPMOVZXWDYrr VR128:$src)>;
5370 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5371 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5374 let Predicates = [HasAVX] in {
5375 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5376 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5379 let Predicates = [UseSSE41] in {
5380 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5381 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5385 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5386 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5387 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5388 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5390 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5391 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5393 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5397 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5399 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5400 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5401 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5403 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5404 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5406 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5410 let Predicates = [HasAVX] in {
5411 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5413 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5415 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5417 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5421 let Predicates = [HasAVX2] in {
5422 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5423 int_x86_avx2_pmovsxbd>, VEX, VEX_L;
5424 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5425 int_x86_avx2_pmovsxwq>, VEX, VEX_L;
5426 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5427 int_x86_avx2_pmovzxbd>, VEX, VEX_L;
5428 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5429 int_x86_avx2_pmovzxwq>, VEX, VEX_L;
5432 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5433 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5434 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5435 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5437 let Predicates = [HasAVX] in {
5438 // Common patterns involving scalar load
5439 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5440 (VPMOVSXBDrm addr:$src)>;
5441 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5442 (VPMOVSXWQrm addr:$src)>;
5444 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5445 (VPMOVZXBDrm addr:$src)>;
5446 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5447 (VPMOVZXWQrm addr:$src)>;
5450 let Predicates = [UseSSE41] in {
5451 // Common patterns involving scalar load
5452 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5453 (PMOVSXBDrm addr:$src)>;
5454 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5455 (PMOVSXWQrm addr:$src)>;
5457 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5458 (PMOVZXBDrm addr:$src)>;
5459 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5460 (PMOVZXWQrm addr:$src)>;
5463 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5464 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5465 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5466 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5468 // Expecting a i16 load any extended to i32 value.
5469 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5470 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5471 [(set VR128:$dst, (IntId (bitconvert
5472 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5476 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5478 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5479 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5480 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5482 // Expecting a i16 load any extended to i32 value.
5483 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5484 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5485 [(set VR256:$dst, (IntId (bitconvert
5486 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5490 let Predicates = [HasAVX] in {
5491 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5493 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5496 let Predicates = [HasAVX2] in {
5497 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5498 int_x86_avx2_pmovsxbq>, VEX, VEX_L;
5499 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5500 int_x86_avx2_pmovzxbq>, VEX, VEX_L;
5502 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5503 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5505 let Predicates = [HasAVX2] in {
5506 def : Pat<(v8i32 (X86vsmovl (v8i16 (bitconvert (v2i64 (load addr:$src)))))),
5507 (VPMOVSXWDYrm addr:$src)>;
5508 def : Pat<(v4i64 (X86vsmovl (v4i32 (bitconvert (v2i64 (load addr:$src)))))),
5509 (VPMOVSXDQYrm addr:$src)>;
5511 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2i64
5512 (scalar_to_vector (loadi64 addr:$src))))))),
5513 (VPMOVSXBDYrm addr:$src)>;
5514 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2f64
5515 (scalar_to_vector (loadf64 addr:$src))))))),
5516 (VPMOVSXBDYrm addr:$src)>;
5518 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2i64
5519 (scalar_to_vector (loadi64 addr:$src))))))),
5520 (VPMOVSXWQYrm addr:$src)>;
5521 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2f64
5522 (scalar_to_vector (loadf64 addr:$src))))))),
5523 (VPMOVSXWQYrm addr:$src)>;
5525 def : Pat<(v4i64 (X86vsext (v16i8 (bitconvert (v4i32
5526 (scalar_to_vector (loadi32 addr:$src))))))),
5527 (VPMOVSXBQYrm addr:$src)>;
5530 let Predicates = [HasAVX] in {
5531 // Common patterns involving scalar load
5532 def : Pat<(int_x86_sse41_pmovsxbq
5533 (bitconvert (v4i32 (X86vzmovl
5534 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5535 (VPMOVSXBQrm addr:$src)>;
5537 def : Pat<(int_x86_sse41_pmovzxbq
5538 (bitconvert (v4i32 (X86vzmovl
5539 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5540 (VPMOVZXBQrm addr:$src)>;
5543 let Predicates = [UseSSE41] in {
5544 // Common patterns involving scalar load
5545 def : Pat<(int_x86_sse41_pmovsxbq
5546 (bitconvert (v4i32 (X86vzmovl
5547 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5548 (PMOVSXBQrm addr:$src)>;
5550 def : Pat<(int_x86_sse41_pmovzxbq
5551 (bitconvert (v4i32 (X86vzmovl
5552 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5553 (PMOVZXBQrm addr:$src)>;
5555 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
5556 (scalar_to_vector (loadi64 addr:$src))))))),
5557 (PMOVSXWDrm addr:$src)>;
5558 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
5559 (scalar_to_vector (loadf64 addr:$src))))))),
5560 (PMOVSXWDrm addr:$src)>;
5561 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
5562 (scalar_to_vector (loadi32 addr:$src))))))),
5563 (PMOVSXBDrm addr:$src)>;
5564 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
5565 (scalar_to_vector (loadi32 addr:$src))))))),
5566 (PMOVSXWQrm addr:$src)>;
5567 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
5568 (scalar_to_vector (extloadi32i16 addr:$src))))))),
5569 (PMOVSXBQrm addr:$src)>;
5570 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
5571 (scalar_to_vector (loadi64 addr:$src))))))),
5572 (PMOVSXDQrm addr:$src)>;
5573 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
5574 (scalar_to_vector (loadf64 addr:$src))))))),
5575 (PMOVSXDQrm addr:$src)>;
5576 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
5577 (scalar_to_vector (loadi64 addr:$src))))))),
5578 (PMOVSXBWrm addr:$src)>;
5579 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
5580 (scalar_to_vector (loadf64 addr:$src))))))),
5581 (PMOVSXBWrm addr:$src)>;
5584 let Predicates = [HasAVX2] in {
5585 def : Pat<(v16i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWYrr VR128:$src)>;
5586 def : Pat<(v8i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDYrr VR128:$src)>;
5587 def : Pat<(v4i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQYrr VR128:$src)>;
5589 def : Pat<(v8i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDYrr VR128:$src)>;
5590 def : Pat<(v4i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQYrr VR128:$src)>;
5592 def : Pat<(v4i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQYrr VR128:$src)>;
5594 def : Pat<(v16i16 (X86vzext (v32i8 VR256:$src))),
5595 (VPMOVZXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5596 def : Pat<(v8i32 (X86vzext (v32i8 VR256:$src))),
5597 (VPMOVZXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5598 def : Pat<(v4i64 (X86vzext (v32i8 VR256:$src))),
5599 (VPMOVZXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5601 def : Pat<(v8i32 (X86vzext (v16i16 VR256:$src))),
5602 (VPMOVZXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5603 def : Pat<(v4i64 (X86vzext (v16i16 VR256:$src))),
5604 (VPMOVZXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5606 def : Pat<(v4i64 (X86vzext (v8i32 VR256:$src))),
5607 (VPMOVZXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5610 let Predicates = [HasAVX] in {
5611 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWrr VR128:$src)>;
5612 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDrr VR128:$src)>;
5613 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQrr VR128:$src)>;
5615 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDrr VR128:$src)>;
5616 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQrr VR128:$src)>;
5618 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQrr VR128:$src)>;
5620 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5621 (VPMOVZXBWrm addr:$src)>;
5622 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5623 (VPMOVZXBWrm addr:$src)>;
5624 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5625 (VPMOVZXBDrm addr:$src)>;
5626 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
5627 (VPMOVZXBQrm addr:$src)>;
5629 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5630 (VPMOVZXWDrm addr:$src)>;
5631 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5632 (VPMOVZXWDrm addr:$src)>;
5633 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5634 (VPMOVZXWQrm addr:$src)>;
5636 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5637 (VPMOVZXDQrm addr:$src)>;
5638 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5639 (VPMOVZXDQrm addr:$src)>;
5640 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
5641 (VPMOVZXDQrm addr:$src)>;
5643 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
5644 (scalar_to_vector (loadi64 addr:$src))))))),
5645 (VPMOVSXWDrm addr:$src)>;
5646 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
5647 (scalar_to_vector (loadi64 addr:$src))))))),
5648 (VPMOVSXDQrm addr:$src)>;
5649 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
5650 (scalar_to_vector (loadf64 addr:$src))))))),
5651 (VPMOVSXWDrm addr:$src)>;
5652 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
5653 (scalar_to_vector (loadf64 addr:$src))))))),
5654 (VPMOVSXDQrm addr:$src)>;
5655 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
5656 (scalar_to_vector (loadi64 addr:$src))))))),
5657 (VPMOVSXBWrm addr:$src)>;
5658 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
5659 (scalar_to_vector (loadf64 addr:$src))))))),
5660 (VPMOVSXBWrm addr:$src)>;
5662 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
5663 (scalar_to_vector (loadi32 addr:$src))))))),
5664 (VPMOVSXBDrm addr:$src)>;
5665 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
5666 (scalar_to_vector (loadi32 addr:$src))))))),
5667 (VPMOVSXWQrm addr:$src)>;
5668 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
5669 (scalar_to_vector (extloadi32i16 addr:$src))))))),
5670 (VPMOVSXBQrm addr:$src)>;
5673 let Predicates = [UseSSE41] in {
5674 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (PMOVZXBWrr VR128:$src)>;
5675 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (PMOVZXBDrr VR128:$src)>;
5676 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (PMOVZXBQrr VR128:$src)>;
5678 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (PMOVZXWDrr VR128:$src)>;
5679 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (PMOVZXWQrr VR128:$src)>;
5681 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (PMOVZXDQrr VR128:$src)>;
5683 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5684 (PMOVZXBWrm addr:$src)>;
5685 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5686 (PMOVZXBWrm addr:$src)>;
5687 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5688 (PMOVZXBDrm addr:$src)>;
5689 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
5690 (PMOVZXBQrm addr:$src)>;
5692 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5693 (PMOVZXWDrm addr:$src)>;
5694 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5695 (PMOVZXWDrm addr:$src)>;
5696 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5697 (PMOVZXWQrm addr:$src)>;
5699 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5700 (PMOVZXDQrm addr:$src)>;
5701 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5702 (PMOVZXDQrm addr:$src)>;
5703 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
5704 (PMOVZXDQrm addr:$src)>;
5707 //===----------------------------------------------------------------------===//
5708 // SSE4.1 - Extract Instructions
5709 //===----------------------------------------------------------------------===//
5711 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5712 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5713 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5714 (ins VR128:$src1, i32i8imm:$src2),
5715 !strconcat(OpcodeStr,
5716 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5717 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5719 let neverHasSideEffects = 1, mayStore = 1 in
5720 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5721 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5722 !strconcat(OpcodeStr,
5723 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5726 // There's an AssertZext in the way of writing the store pattern
5727 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5730 let Predicates = [HasAVX] in {
5731 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5732 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5733 (ins VR128:$src1, i32i8imm:$src2),
5734 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5737 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5740 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5741 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5742 let neverHasSideEffects = 1, mayStore = 1 in
5743 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5744 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5745 !strconcat(OpcodeStr,
5746 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5749 // There's an AssertZext in the way of writing the store pattern
5750 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5753 let Predicates = [HasAVX] in
5754 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5756 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5759 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5760 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5761 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5762 (ins VR128:$src1, i32i8imm:$src2),
5763 !strconcat(OpcodeStr,
5764 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5766 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5767 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5768 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5769 !strconcat(OpcodeStr,
5770 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5771 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5772 addr:$dst)]>, OpSize;
5775 let Predicates = [HasAVX] in
5776 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5778 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5780 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5781 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5782 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5783 (ins VR128:$src1, i32i8imm:$src2),
5784 !strconcat(OpcodeStr,
5785 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5787 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5788 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5789 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5790 !strconcat(OpcodeStr,
5791 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5792 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5793 addr:$dst)]>, OpSize, REX_W;
5796 let Predicates = [HasAVX] in
5797 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5799 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5801 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5803 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5804 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5805 (ins VR128:$src1, i32i8imm:$src2),
5806 !strconcat(OpcodeStr,
5807 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5809 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5811 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5812 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5813 !strconcat(OpcodeStr,
5814 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5815 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5816 addr:$dst)]>, OpSize;
5819 let ExeDomain = SSEPackedSingle in {
5820 let Predicates = [HasAVX] in {
5821 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5822 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5823 (ins VR128:$src1, i32i8imm:$src2),
5824 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
5827 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
5830 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
5831 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5834 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5836 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5839 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5840 Requires<[UseSSE41]>;
5842 //===----------------------------------------------------------------------===//
5843 // SSE4.1 - Insert Instructions
5844 //===----------------------------------------------------------------------===//
5846 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5847 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5848 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5850 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5852 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5854 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5855 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5856 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
5858 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5860 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5862 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
5863 imm:$src3))]>, OpSize;
5866 let Predicates = [HasAVX] in
5867 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
5868 let Constraints = "$src1 = $dst" in
5869 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
5871 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
5872 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5873 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5875 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5877 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5879 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
5881 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5882 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
5884 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5886 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5888 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
5889 imm:$src3)))]>, OpSize;
5892 let Predicates = [HasAVX] in
5893 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
5894 let Constraints = "$src1 = $dst" in
5895 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
5897 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
5898 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5899 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
5901 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5903 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5905 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
5907 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5908 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
5910 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5912 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5914 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
5915 imm:$src3)))]>, OpSize;
5918 let Predicates = [HasAVX] in
5919 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
5920 let Constraints = "$src1 = $dst" in
5921 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
5923 // insertps has a few different modes, there's the first two here below which
5924 // are optimized inserts that won't zero arbitrary elements in the destination
5925 // vector. The next one matches the intrinsic and could zero arbitrary elements
5926 // in the target vector.
5927 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
5928 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5929 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
5931 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5933 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5935 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
5937 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5938 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
5940 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5942 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5944 (X86insrtps VR128:$src1,
5945 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
5946 imm:$src3))]>, OpSize;
5949 let ExeDomain = SSEPackedSingle in {
5950 let Predicates = [HasAVX] in
5951 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
5952 let Constraints = "$src1 = $dst" in
5953 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
5956 //===----------------------------------------------------------------------===//
5957 // SSE4.1 - Round Instructions
5958 //===----------------------------------------------------------------------===//
5960 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
5961 X86MemOperand x86memop, RegisterClass RC,
5962 PatFrag mem_frag32, PatFrag mem_frag64,
5963 Intrinsic V4F32Int, Intrinsic V2F64Int> {
5964 let ExeDomain = SSEPackedSingle in {
5965 // Intrinsic operation, reg.
5966 // Vector intrinsic operation, reg
5967 def PSr : SS4AIi8<opcps, MRMSrcReg,
5968 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5969 !strconcat(OpcodeStr,
5970 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5971 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
5974 // Vector intrinsic operation, mem
5975 def PSm : SS4AIi8<opcps, MRMSrcMem,
5976 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5977 !strconcat(OpcodeStr,
5978 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5980 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
5982 } // ExeDomain = SSEPackedSingle
5984 let ExeDomain = SSEPackedDouble in {
5985 // Vector intrinsic operation, reg
5986 def PDr : SS4AIi8<opcpd, MRMSrcReg,
5987 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5988 !strconcat(OpcodeStr,
5989 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5990 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
5993 // Vector intrinsic operation, mem
5994 def PDm : SS4AIi8<opcpd, MRMSrcMem,
5995 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5996 !strconcat(OpcodeStr,
5997 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5999 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
6001 } // ExeDomain = SSEPackedDouble
6004 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6007 Intrinsic F64Int, bit Is2Addr = 1> {
6008 let ExeDomain = GenericDomain in {
6010 let hasSideEffects = 0 in
6011 def SSr : SS4AIi8<opcss, MRMSrcReg,
6012 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6014 !strconcat(OpcodeStr,
6015 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6016 !strconcat(OpcodeStr,
6017 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6020 // Intrinsic operation, reg.
6021 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6022 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6024 !strconcat(OpcodeStr,
6025 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6026 !strconcat(OpcodeStr,
6027 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6028 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6031 // Intrinsic operation, mem.
6032 def SSm : SS4AIi8<opcss, MRMSrcMem,
6033 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6035 !strconcat(OpcodeStr,
6036 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6037 !strconcat(OpcodeStr,
6038 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6040 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6044 let hasSideEffects = 0 in
6045 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6046 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6048 !strconcat(OpcodeStr,
6049 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6050 !strconcat(OpcodeStr,
6051 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6054 // Intrinsic operation, reg.
6055 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6056 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6058 !strconcat(OpcodeStr,
6059 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6060 !strconcat(OpcodeStr,
6061 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6062 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6065 // Intrinsic operation, mem.
6066 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6067 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6069 !strconcat(OpcodeStr,
6070 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6071 !strconcat(OpcodeStr,
6072 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6074 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6076 } // ExeDomain = GenericDomain
6079 // FP round - roundss, roundps, roundsd, roundpd
6080 let Predicates = [HasAVX] in {
6082 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6083 memopv4f32, memopv2f64,
6084 int_x86_sse41_round_ps,
6085 int_x86_sse41_round_pd>, VEX;
6086 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6087 memopv8f32, memopv4f64,
6088 int_x86_avx_round_ps_256,
6089 int_x86_avx_round_pd_256>, VEX, VEX_L;
6090 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6091 int_x86_sse41_round_ss,
6092 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6094 def : Pat<(ffloor FR32:$src),
6095 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6096 def : Pat<(f64 (ffloor FR64:$src)),
6097 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6098 def : Pat<(f32 (fnearbyint FR32:$src)),
6099 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6100 def : Pat<(f64 (fnearbyint FR64:$src)),
6101 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6102 def : Pat<(f32 (fceil FR32:$src)),
6103 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6104 def : Pat<(f64 (fceil FR64:$src)),
6105 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6106 def : Pat<(f32 (frint FR32:$src)),
6107 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6108 def : Pat<(f64 (frint FR64:$src)),
6109 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6110 def : Pat<(f32 (ftrunc FR32:$src)),
6111 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6112 def : Pat<(f64 (ftrunc FR64:$src)),
6113 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6115 def : Pat<(v4f32 (ffloor VR128:$src)),
6116 (VROUNDPSr VR128:$src, (i32 0x1))>;
6117 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6118 (VROUNDPSr VR128:$src, (i32 0xC))>;
6119 def : Pat<(v4f32 (fceil VR128:$src)),
6120 (VROUNDPSr VR128:$src, (i32 0x2))>;
6121 def : Pat<(v4f32 (frint VR128:$src)),
6122 (VROUNDPSr VR128:$src, (i32 0x4))>;
6123 def : Pat<(v4f32 (ftrunc VR128:$src)),
6124 (VROUNDPSr VR128:$src, (i32 0x3))>;
6126 def : Pat<(v2f64 (ffloor VR128:$src)),
6127 (VROUNDPDr VR128:$src, (i32 0x1))>;
6128 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6129 (VROUNDPDr VR128:$src, (i32 0xC))>;
6130 def : Pat<(v2f64 (fceil VR128:$src)),
6131 (VROUNDPDr VR128:$src, (i32 0x2))>;
6132 def : Pat<(v2f64 (frint VR128:$src)),
6133 (VROUNDPDr VR128:$src, (i32 0x4))>;
6134 def : Pat<(v2f64 (ftrunc VR128:$src)),
6135 (VROUNDPDr VR128:$src, (i32 0x3))>;
6137 def : Pat<(v8f32 (ffloor VR256:$src)),
6138 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6139 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6140 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6141 def : Pat<(v8f32 (fceil VR256:$src)),
6142 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6143 def : Pat<(v8f32 (frint VR256:$src)),
6144 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6145 def : Pat<(v8f32 (ftrunc VR256:$src)),
6146 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6148 def : Pat<(v4f64 (ffloor VR256:$src)),
6149 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6150 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6151 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6152 def : Pat<(v4f64 (fceil VR256:$src)),
6153 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6154 def : Pat<(v4f64 (frint VR256:$src)),
6155 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6156 def : Pat<(v4f64 (ftrunc VR256:$src)),
6157 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6160 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6161 memopv4f32, memopv2f64,
6162 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6163 let Constraints = "$src1 = $dst" in
6164 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6165 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6167 let Predicates = [UseSSE41] in {
6168 def : Pat<(ffloor FR32:$src),
6169 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6170 def : Pat<(f64 (ffloor FR64:$src)),
6171 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6172 def : Pat<(f32 (fnearbyint FR32:$src)),
6173 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6174 def : Pat<(f64 (fnearbyint FR64:$src)),
6175 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6176 def : Pat<(f32 (fceil FR32:$src)),
6177 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6178 def : Pat<(f64 (fceil FR64:$src)),
6179 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6180 def : Pat<(f32 (frint FR32:$src)),
6181 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6182 def : Pat<(f64 (frint FR64:$src)),
6183 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6184 def : Pat<(f32 (ftrunc FR32:$src)),
6185 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6186 def : Pat<(f64 (ftrunc FR64:$src)),
6187 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6189 def : Pat<(v4f32 (ffloor VR128:$src)),
6190 (ROUNDPSr VR128:$src, (i32 0x1))>;
6191 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6192 (ROUNDPSr VR128:$src, (i32 0xC))>;
6193 def : Pat<(v4f32 (fceil VR128:$src)),
6194 (ROUNDPSr VR128:$src, (i32 0x2))>;
6195 def : Pat<(v4f32 (frint VR128:$src)),
6196 (ROUNDPSr VR128:$src, (i32 0x4))>;
6197 def : Pat<(v4f32 (ftrunc VR128:$src)),
6198 (ROUNDPSr VR128:$src, (i32 0x3))>;
6200 def : Pat<(v2f64 (ffloor VR128:$src)),
6201 (ROUNDPDr VR128:$src, (i32 0x1))>;
6202 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6203 (ROUNDPDr VR128:$src, (i32 0xC))>;
6204 def : Pat<(v2f64 (fceil VR128:$src)),
6205 (ROUNDPDr VR128:$src, (i32 0x2))>;
6206 def : Pat<(v2f64 (frint VR128:$src)),
6207 (ROUNDPDr VR128:$src, (i32 0x4))>;
6208 def : Pat<(v2f64 (ftrunc VR128:$src)),
6209 (ROUNDPDr VR128:$src, (i32 0x3))>;
6212 //===----------------------------------------------------------------------===//
6213 // SSE4.1 - Packed Bit Test
6214 //===----------------------------------------------------------------------===//
6216 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6217 // the intel intrinsic that corresponds to this.
6218 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6219 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6220 "vptest\t{$src2, $src1|$src1, $src2}",
6221 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6223 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6224 "vptest\t{$src2, $src1|$src1, $src2}",
6225 [(set EFLAGS,(X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6228 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6229 "vptest\t{$src2, $src1|$src1, $src2}",
6230 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6232 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6233 "vptest\t{$src2, $src1|$src1, $src2}",
6234 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6238 let Defs = [EFLAGS] in {
6239 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6240 "ptest\t{$src2, $src1|$src1, $src2}",
6241 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6243 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6244 "ptest\t{$src2, $src1|$src1, $src2}",
6245 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6249 // The bit test instructions below are AVX only
6250 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6251 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6252 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6253 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6254 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6255 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6256 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6257 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6261 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6262 let ExeDomain = SSEPackedSingle in {
6263 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6264 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>,
6267 let ExeDomain = SSEPackedDouble in {
6268 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6269 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>,
6274 //===----------------------------------------------------------------------===//
6275 // SSE4.1 - Misc Instructions
6276 //===----------------------------------------------------------------------===//
6278 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6279 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6280 "popcnt{w}\t{$src, $dst|$dst, $src}",
6281 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6283 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6284 "popcnt{w}\t{$src, $dst|$dst, $src}",
6285 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6286 (implicit EFLAGS)]>, OpSize, XS;
6288 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6289 "popcnt{l}\t{$src, $dst|$dst, $src}",
6290 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6292 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6293 "popcnt{l}\t{$src, $dst|$dst, $src}",
6294 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6295 (implicit EFLAGS)]>, XS;
6297 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6298 "popcnt{q}\t{$src, $dst|$dst, $src}",
6299 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6301 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6302 "popcnt{q}\t{$src, $dst|$dst, $src}",
6303 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6304 (implicit EFLAGS)]>, XS;
6309 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6310 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6311 Intrinsic IntId128> {
6312 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6314 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6315 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6316 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6318 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6321 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6324 let Predicates = [HasAVX] in
6325 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6326 int_x86_sse41_phminposuw>, VEX;
6327 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6328 int_x86_sse41_phminposuw>;
6330 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6331 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6332 Intrinsic IntId128, bit Is2Addr = 1> {
6333 let isCommutable = 1 in
6334 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6335 (ins VR128:$src1, VR128:$src2),
6337 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6338 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6339 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6340 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6341 (ins VR128:$src1, i128mem:$src2),
6343 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6344 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6346 (IntId128 VR128:$src1,
6347 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6350 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
6351 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6352 Intrinsic IntId256> {
6353 let isCommutable = 1 in
6354 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6355 (ins VR256:$src1, VR256:$src2),
6356 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6357 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6358 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6359 (ins VR256:$src1, i256mem:$src2),
6360 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6362 (IntId256 VR256:$src1,
6363 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6367 /// SS48I_binop_rm - Simple SSE41 binary operator.
6368 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6369 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6370 X86MemOperand x86memop, bit Is2Addr = 1> {
6371 let isCommutable = 1 in
6372 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6373 (ins RC:$src1, RC:$src2),
6375 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6376 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6377 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6378 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6379 (ins RC:$src1, x86memop:$src2),
6381 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6382 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6384 (OpVT (OpNode RC:$src1,
6385 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6388 let Predicates = [HasAVX] in {
6389 let isCommutable = 0 in
6390 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6392 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
6393 memopv2i64, i128mem, 0>, VEX_4V;
6394 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
6395 memopv2i64, i128mem, 0>, VEX_4V;
6396 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
6397 memopv2i64, i128mem, 0>, VEX_4V;
6398 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
6399 memopv2i64, i128mem, 0>, VEX_4V;
6400 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
6401 memopv2i64, i128mem, 0>, VEX_4V;
6402 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
6403 memopv2i64, i128mem, 0>, VEX_4V;
6404 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
6405 memopv2i64, i128mem, 0>, VEX_4V;
6406 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
6407 memopv2i64, i128mem, 0>, VEX_4V;
6408 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6412 let Predicates = [HasAVX2] in {
6413 let isCommutable = 0 in
6414 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6415 int_x86_avx2_packusdw>, VEX_4V, VEX_L;
6416 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
6417 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6418 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
6419 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6420 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
6421 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6422 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
6423 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6424 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
6425 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6426 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
6427 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6428 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
6429 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6430 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
6431 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6432 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6433 int_x86_avx2_pmul_dq>, VEX_4V, VEX_L;
6436 let Constraints = "$src1 = $dst" in {
6437 let isCommutable = 0 in
6438 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6439 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
6440 memopv2i64, i128mem>;
6441 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
6442 memopv2i64, i128mem>;
6443 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
6444 memopv2i64, i128mem>;
6445 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
6446 memopv2i64, i128mem>;
6447 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
6448 memopv2i64, i128mem>;
6449 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
6450 memopv2i64, i128mem>;
6451 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
6452 memopv2i64, i128mem>;
6453 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
6454 memopv2i64, i128mem>;
6455 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6458 let Predicates = [HasAVX] in {
6459 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6460 memopv2i64, i128mem, 0>, VEX_4V;
6461 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6462 memopv2i64, i128mem, 0>, VEX_4V;
6464 let Predicates = [HasAVX2] in {
6465 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6466 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6467 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6468 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6471 let Constraints = "$src1 = $dst" in {
6472 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6473 memopv2i64, i128mem>;
6474 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6475 memopv2i64, i128mem>;
6478 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6479 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6480 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6481 X86MemOperand x86memop, bit Is2Addr = 1> {
6482 let isCommutable = 1 in
6483 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6484 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6486 !strconcat(OpcodeStr,
6487 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6488 !strconcat(OpcodeStr,
6489 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6490 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6492 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6493 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6495 !strconcat(OpcodeStr,
6496 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6497 !strconcat(OpcodeStr,
6498 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6501 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6505 let Predicates = [HasAVX] in {
6506 let isCommutable = 0 in {
6507 let ExeDomain = SSEPackedSingle in {
6508 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6509 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6510 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6511 int_x86_avx_blend_ps_256, VR256, memopv8f32,
6512 f256mem, 0>, VEX_4V, VEX_L;
6514 let ExeDomain = SSEPackedDouble in {
6515 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6516 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6517 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6518 int_x86_avx_blend_pd_256,VR256, memopv4f64,
6519 f256mem, 0>, VEX_4V, VEX_L;
6521 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6522 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6523 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6524 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6526 let ExeDomain = SSEPackedSingle in
6527 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6528 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6529 let ExeDomain = SSEPackedDouble in
6530 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6531 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6532 let ExeDomain = SSEPackedSingle in
6533 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6534 VR256, memopv8f32, i256mem, 0>, VEX_4V, VEX_L;
6537 let Predicates = [HasAVX2] in {
6538 let isCommutable = 0 in {
6539 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6540 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6541 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6542 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6546 let Constraints = "$src1 = $dst" in {
6547 let isCommutable = 0 in {
6548 let ExeDomain = SSEPackedSingle in
6549 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6550 VR128, memopv4f32, f128mem>;
6551 let ExeDomain = SSEPackedDouble in
6552 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6553 VR128, memopv2f64, f128mem>;
6554 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6555 VR128, memopv2i64, i128mem>;
6556 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6557 VR128, memopv2i64, i128mem>;
6559 let ExeDomain = SSEPackedSingle in
6560 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6561 VR128, memopv4f32, f128mem>;
6562 let ExeDomain = SSEPackedDouble in
6563 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6564 VR128, memopv2f64, f128mem>;
6567 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6568 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6569 RegisterClass RC, X86MemOperand x86memop,
6570 PatFrag mem_frag, Intrinsic IntId> {
6571 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6572 (ins RC:$src1, RC:$src2, RC:$src3),
6573 !strconcat(OpcodeStr,
6574 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6575 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6576 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6578 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6579 (ins RC:$src1, x86memop:$src2, RC:$src3),
6580 !strconcat(OpcodeStr,
6581 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6583 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6585 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6588 let Predicates = [HasAVX] in {
6589 let ExeDomain = SSEPackedDouble in {
6590 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
6591 memopv2f64, int_x86_sse41_blendvpd>;
6592 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
6593 memopv4f64, int_x86_avx_blendv_pd_256>, VEX_L;
6594 } // ExeDomain = SSEPackedDouble
6595 let ExeDomain = SSEPackedSingle in {
6596 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
6597 memopv4f32, int_x86_sse41_blendvps>;
6598 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
6599 memopv8f32, int_x86_avx_blendv_ps_256>, VEX_L;
6600 } // ExeDomain = SSEPackedSingle
6601 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6602 memopv2i64, int_x86_sse41_pblendvb>;
6605 let Predicates = [HasAVX2] in {
6606 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6607 memopv4i64, int_x86_avx2_pblendvb>, VEX_L;
6610 let Predicates = [HasAVX] in {
6611 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6612 (v16i8 VR128:$src2))),
6613 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6614 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6615 (v4i32 VR128:$src2))),
6616 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6617 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6618 (v4f32 VR128:$src2))),
6619 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6620 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6621 (v2i64 VR128:$src2))),
6622 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6623 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6624 (v2f64 VR128:$src2))),
6625 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6626 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6627 (v8i32 VR256:$src2))),
6628 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6629 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6630 (v8f32 VR256:$src2))),
6631 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6632 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6633 (v4i64 VR256:$src2))),
6634 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6635 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6636 (v4f64 VR256:$src2))),
6637 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6639 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6641 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6642 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6644 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6646 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6648 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
6649 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6651 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
6652 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6654 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
6657 let Predicates = [HasAVX2] in {
6658 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6659 (v32i8 VR256:$src2))),
6660 (VPBLENDVBYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
6661 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6663 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6666 /// SS41I_ternary_int - SSE 4.1 ternary operator
6667 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6668 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6669 X86MemOperand x86memop, Intrinsic IntId> {
6670 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6671 (ins VR128:$src1, VR128:$src2),
6672 !strconcat(OpcodeStr,
6673 "\t{$src2, $dst|$dst, $src2}"),
6674 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6677 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6678 (ins VR128:$src1, x86memop:$src2),
6679 !strconcat(OpcodeStr,
6680 "\t{$src2, $dst|$dst, $src2}"),
6683 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
6687 let ExeDomain = SSEPackedDouble in
6688 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
6689 int_x86_sse41_blendvpd>;
6690 let ExeDomain = SSEPackedSingle in
6691 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
6692 int_x86_sse41_blendvps>;
6693 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
6694 int_x86_sse41_pblendvb>;
6696 // Aliases with the implicit xmm0 argument
6697 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6698 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
6699 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6700 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
6701 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6702 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
6703 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6704 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
6705 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6706 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
6707 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6708 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
6710 let Predicates = [UseSSE41] in {
6711 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6712 (v16i8 VR128:$src2))),
6713 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6714 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6715 (v4i32 VR128:$src2))),
6716 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6717 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6718 (v4f32 VR128:$src2))),
6719 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6720 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6721 (v2i64 VR128:$src2))),
6722 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6723 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6724 (v2f64 VR128:$src2))),
6725 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6727 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6729 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
6730 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6732 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
6733 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6735 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
6739 let Predicates = [HasAVX] in
6740 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6741 "vmovntdqa\t{$src, $dst|$dst, $src}",
6742 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6744 let Predicates = [HasAVX2] in
6745 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
6746 "vmovntdqa\t{$src, $dst|$dst, $src}",
6747 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
6749 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6750 "movntdqa\t{$src, $dst|$dst, $src}",
6751 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6754 //===----------------------------------------------------------------------===//
6755 // SSE4.2 - Compare Instructions
6756 //===----------------------------------------------------------------------===//
6758 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
6759 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6760 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6761 X86MemOperand x86memop, bit Is2Addr = 1> {
6762 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
6763 (ins RC:$src1, RC:$src2),
6765 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6766 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6767 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6769 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
6770 (ins RC:$src1, x86memop:$src2),
6772 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6773 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6775 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
6778 let Predicates = [HasAVX] in
6779 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
6780 memopv2i64, i128mem, 0>, VEX_4V;
6782 let Predicates = [HasAVX2] in
6783 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
6784 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6786 let Constraints = "$src1 = $dst" in
6787 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
6788 memopv2i64, i128mem>;
6790 //===----------------------------------------------------------------------===//
6791 // SSE4.2 - String/text Processing Instructions
6792 //===----------------------------------------------------------------------===//
6794 // Packed Compare Implicit Length Strings, Return Mask
6795 multiclass pseudo_pcmpistrm<string asm> {
6796 def REG : PseudoI<(outs VR128:$dst),
6797 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6798 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6800 def MEM : PseudoI<(outs VR128:$dst),
6801 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6802 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
6803 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
6806 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6807 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6808 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
6811 multiclass pcmpistrm_SS42AI<string asm> {
6812 def rr : SS42AI<0x62, MRMSrcReg, (outs),
6813 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6814 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6817 def rm :SS42AI<0x62, MRMSrcMem, (outs),
6818 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6819 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6823 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
6824 let Predicates = [HasAVX] in
6825 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
6826 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
6829 // Packed Compare Explicit Length Strings, Return Mask
6830 multiclass pseudo_pcmpestrm<string asm> {
6831 def REG : PseudoI<(outs VR128:$dst),
6832 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6833 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6834 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6835 def MEM : PseudoI<(outs VR128:$dst),
6836 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6837 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
6838 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
6841 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6842 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6843 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
6846 multiclass SS42AI_pcmpestrm<string asm> {
6847 def rr : SS42AI<0x60, MRMSrcReg, (outs),
6848 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6849 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6852 def rm : SS42AI<0x60, MRMSrcMem, (outs),
6853 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6854 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6858 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6859 let Predicates = [HasAVX] in
6860 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
6861 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
6864 // Packed Compare Implicit Length Strings, Return Index
6865 multiclass pseudo_pcmpistri<string asm> {
6866 def REG : PseudoI<(outs GR32:$dst),
6867 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6868 [(set GR32:$dst, EFLAGS,
6869 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
6870 def MEM : PseudoI<(outs GR32:$dst),
6871 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6872 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
6873 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
6876 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6877 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
6878 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
6881 multiclass SS42AI_pcmpistri<string asm> {
6882 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6883 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6884 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6887 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6888 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6889 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6893 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
6894 let Predicates = [HasAVX] in
6895 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
6896 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
6899 // Packed Compare Explicit Length Strings, Return Index
6900 multiclass pseudo_pcmpestri<string asm> {
6901 def REG : PseudoI<(outs GR32:$dst),
6902 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6903 [(set GR32:$dst, EFLAGS,
6904 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6905 def MEM : PseudoI<(outs GR32:$dst),
6906 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6907 [(set GR32:$dst, EFLAGS,
6908 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
6912 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6913 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
6914 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
6917 multiclass SS42AI_pcmpestri<string asm> {
6918 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6919 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6920 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6923 def rm : SS42AI<0x61, MRMSrcMem, (outs),
6924 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6925 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6929 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6930 let Predicates = [HasAVX] in
6931 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
6932 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
6935 //===----------------------------------------------------------------------===//
6936 // SSE4.2 - CRC Instructions
6937 //===----------------------------------------------------------------------===//
6939 // No CRC instructions have AVX equivalents
6941 // crc intrinsic instruction
6942 // This set of instructions are only rm, the only difference is the size
6944 let Constraints = "$src1 = $dst" in {
6945 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
6946 (ins GR32:$src1, i8mem:$src2),
6947 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6949 (int_x86_sse42_crc32_32_8 GR32:$src1,
6950 (load addr:$src2)))]>;
6951 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
6952 (ins GR32:$src1, GR8:$src2),
6953 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6955 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
6956 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6957 (ins GR32:$src1, i16mem:$src2),
6958 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6960 (int_x86_sse42_crc32_32_16 GR32:$src1,
6961 (load addr:$src2)))]>,
6963 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6964 (ins GR32:$src1, GR16:$src2),
6965 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6967 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
6969 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6970 (ins GR32:$src1, i32mem:$src2),
6971 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6973 (int_x86_sse42_crc32_32_32 GR32:$src1,
6974 (load addr:$src2)))]>;
6975 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6976 (ins GR32:$src1, GR32:$src2),
6977 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6979 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
6980 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
6981 (ins GR64:$src1, i8mem:$src2),
6982 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6984 (int_x86_sse42_crc32_64_8 GR64:$src1,
6985 (load addr:$src2)))]>,
6987 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
6988 (ins GR64:$src1, GR8:$src2),
6989 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6991 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
6993 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
6994 (ins GR64:$src1, i64mem:$src2),
6995 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6997 (int_x86_sse42_crc32_64_64 GR64:$src1,
6998 (load addr:$src2)))]>,
7000 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
7001 (ins GR64:$src1, GR64:$src2),
7002 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7004 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
7008 //===----------------------------------------------------------------------===//
7009 // AES-NI Instructions
7010 //===----------------------------------------------------------------------===//
7012 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7013 Intrinsic IntId128, bit Is2Addr = 1> {
7014 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7015 (ins VR128:$src1, VR128:$src2),
7017 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7018 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7019 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7021 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7022 (ins VR128:$src1, i128mem:$src2),
7024 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7025 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7027 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7030 // Perform One Round of an AES Encryption/Decryption Flow
7031 let Predicates = [HasAVX, HasAES] in {
7032 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7033 int_x86_aesni_aesenc, 0>, VEX_4V;
7034 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7035 int_x86_aesni_aesenclast, 0>, VEX_4V;
7036 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7037 int_x86_aesni_aesdec, 0>, VEX_4V;
7038 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7039 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7042 let Constraints = "$src1 = $dst" in {
7043 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7044 int_x86_aesni_aesenc>;
7045 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7046 int_x86_aesni_aesenclast>;
7047 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7048 int_x86_aesni_aesdec>;
7049 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7050 int_x86_aesni_aesdeclast>;
7053 // Perform the AES InvMixColumn Transformation
7054 let Predicates = [HasAVX, HasAES] in {
7055 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7057 "vaesimc\t{$src1, $dst|$dst, $src1}",
7059 (int_x86_aesni_aesimc VR128:$src1))]>,
7061 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7062 (ins i128mem:$src1),
7063 "vaesimc\t{$src1, $dst|$dst, $src1}",
7064 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7067 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7069 "aesimc\t{$src1, $dst|$dst, $src1}",
7071 (int_x86_aesni_aesimc VR128:$src1))]>,
7073 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7074 (ins i128mem:$src1),
7075 "aesimc\t{$src1, $dst|$dst, $src1}",
7076 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7079 // AES Round Key Generation Assist
7080 let Predicates = [HasAVX, HasAES] in {
7081 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7082 (ins VR128:$src1, i8imm:$src2),
7083 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7085 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7087 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7088 (ins i128mem:$src1, i8imm:$src2),
7089 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7091 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7094 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7095 (ins VR128:$src1, i8imm:$src2),
7096 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7098 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7100 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7101 (ins i128mem:$src1, i8imm:$src2),
7102 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7104 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7107 //===----------------------------------------------------------------------===//
7108 // PCLMUL Instructions
7109 //===----------------------------------------------------------------------===//
7111 // AVX carry-less Multiplication instructions
7112 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7113 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7114 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7116 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7118 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7119 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7120 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7121 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7122 (memopv2i64 addr:$src2), imm:$src3))]>;
7124 // Carry-less Multiplication instructions
7125 let Constraints = "$src1 = $dst" in {
7126 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7127 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7128 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7130 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7132 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7133 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7134 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7135 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7136 (memopv2i64 addr:$src2), imm:$src3))]>;
7137 } // Constraints = "$src1 = $dst"
7140 multiclass pclmul_alias<string asm, int immop> {
7141 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7142 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7144 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7145 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7147 def : InstAlias<!strconcat("vpclmul", asm,
7148 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7149 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7151 def : InstAlias<!strconcat("vpclmul", asm,
7152 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7153 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7155 defm : pclmul_alias<"hqhq", 0x11>;
7156 defm : pclmul_alias<"hqlq", 0x01>;
7157 defm : pclmul_alias<"lqhq", 0x10>;
7158 defm : pclmul_alias<"lqlq", 0x00>;
7160 //===----------------------------------------------------------------------===//
7161 // SSE4A Instructions
7162 //===----------------------------------------------------------------------===//
7164 let Predicates = [HasSSE4A] in {
7166 let Constraints = "$src = $dst" in {
7167 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7168 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7169 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7170 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7171 imm:$idx))]>, TB, OpSize;
7172 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7173 (ins VR128:$src, VR128:$mask),
7174 "extrq\t{$mask, $src|$src, $mask}",
7175 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7176 VR128:$mask))]>, TB, OpSize;
7178 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7179 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7180 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7181 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7182 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7183 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7184 (ins VR128:$src, VR128:$mask),
7185 "insertq\t{$mask, $src|$src, $mask}",
7186 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7187 VR128:$mask))]>, XD;
7190 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7191 "movntss\t{$src, $dst|$dst, $src}",
7192 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7194 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7195 "movntsd\t{$src, $dst|$dst, $src}",
7196 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7199 //===----------------------------------------------------------------------===//
7201 //===----------------------------------------------------------------------===//
7203 //===----------------------------------------------------------------------===//
7204 // VBROADCAST - Load from memory and broadcast to all elements of the
7205 // destination operand
7207 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7208 X86MemOperand x86memop, Intrinsic Int> :
7209 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7210 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7211 [(set RC:$dst, (Int addr:$src))]>, VEX;
7213 // AVX2 adds register forms
7214 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7216 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7217 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7218 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7220 let ExeDomain = SSEPackedSingle in {
7221 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7222 int_x86_avx_vbroadcast_ss>;
7223 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7224 int_x86_avx_vbroadcast_ss_256>, VEX_L;
7226 let ExeDomain = SSEPackedDouble in
7227 def VBROADCASTSDYrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7228 int_x86_avx_vbroadcast_sd_256>, VEX_L;
7229 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7230 int_x86_avx_vbroadcastf128_pd_256>, VEX_L;
7232 let ExeDomain = SSEPackedSingle in {
7233 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7234 int_x86_avx2_vbroadcast_ss_ps>;
7235 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7236 int_x86_avx2_vbroadcast_ss_ps_256>, VEX_L;
7238 let ExeDomain = SSEPackedDouble in
7239 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7240 int_x86_avx2_vbroadcast_sd_pd_256>, VEX_L;
7242 let Predicates = [HasAVX2] in
7243 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7244 int_x86_avx2_vbroadcasti128>, VEX_L;
7246 let Predicates = [HasAVX] in
7247 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7248 (VBROADCASTF128 addr:$src)>;
7251 //===----------------------------------------------------------------------===//
7252 // VINSERTF128 - Insert packed floating-point values
7254 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7255 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7256 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7257 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7260 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7261 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7262 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7266 let Predicates = [HasAVX] in {
7267 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7269 (VINSERTF128rr VR256:$src1, VR128:$src2,
7270 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7271 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7273 (VINSERTF128rr VR256:$src1, VR128:$src2,
7274 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7276 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (memopv4f32 addr:$src2),
7278 (VINSERTF128rm VR256:$src1, addr:$src2,
7279 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7280 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (memopv2f64 addr:$src2),
7282 (VINSERTF128rm VR256:$src1, addr:$src2,
7283 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7286 let Predicates = [HasAVX1Only] in {
7287 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7289 (VINSERTF128rr VR256:$src1, VR128:$src2,
7290 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7291 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7293 (VINSERTF128rr VR256:$src1, VR128:$src2,
7294 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7295 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7297 (VINSERTF128rr VR256:$src1, VR128:$src2,
7298 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7299 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7301 (VINSERTF128rr VR256:$src1, VR128:$src2,
7302 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7304 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
7306 (VINSERTF128rm VR256:$src1, addr:$src2,
7307 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7308 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1),
7309 (bc_v4i32 (memopv2i64 addr:$src2)),
7311 (VINSERTF128rm VR256:$src1, addr:$src2,
7312 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7313 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1),
7314 (bc_v16i8 (memopv2i64 addr:$src2)),
7316 (VINSERTF128rm VR256:$src1, addr:$src2,
7317 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7318 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1),
7319 (bc_v8i16 (memopv2i64 addr:$src2)),
7321 (VINSERTF128rm VR256:$src1, addr:$src2,
7322 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7325 //===----------------------------------------------------------------------===//
7326 // VEXTRACTF128 - Extract packed floating-point values
7328 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7329 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7330 (ins VR256:$src1, i8imm:$src2),
7331 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7334 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7335 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7336 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7341 let Predicates = [HasAVX] in {
7342 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7343 (v4f32 (VEXTRACTF128rr
7344 (v8f32 VR256:$src1),
7345 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7346 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7347 (v2f64 (VEXTRACTF128rr
7348 (v4f64 VR256:$src1),
7349 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7351 def : Pat<(alignedstore (v4f32 (vextractf128_extract:$ext (v8f32 VR256:$src1),
7352 (iPTR imm))), addr:$dst),
7353 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7354 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7355 def : Pat<(alignedstore (v2f64 (vextractf128_extract:$ext (v4f64 VR256:$src1),
7356 (iPTR imm))), addr:$dst),
7357 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7358 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7361 let Predicates = [HasAVX1Only] in {
7362 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7363 (v2i64 (VEXTRACTF128rr
7364 (v4i64 VR256:$src1),
7365 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7366 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7367 (v4i32 (VEXTRACTF128rr
7368 (v8i32 VR256:$src1),
7369 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7370 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7371 (v8i16 (VEXTRACTF128rr
7372 (v16i16 VR256:$src1),
7373 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7374 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7375 (v16i8 (VEXTRACTF128rr
7376 (v32i8 VR256:$src1),
7377 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7379 def : Pat<(alignedstore (v2i64 (vextractf128_extract:$ext (v4i64 VR256:$src1),
7380 (iPTR imm))), addr:$dst),
7381 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7382 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7383 def : Pat<(alignedstore (v4i32 (vextractf128_extract:$ext (v8i32 VR256:$src1),
7384 (iPTR imm))), addr:$dst),
7385 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7386 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7387 def : Pat<(alignedstore (v8i16 (vextractf128_extract:$ext (v16i16 VR256:$src1),
7388 (iPTR imm))), addr:$dst),
7389 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7390 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7391 def : Pat<(alignedstore (v16i8 (vextractf128_extract:$ext (v32i8 VR256:$src1),
7392 (iPTR imm))), addr:$dst),
7393 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7394 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7397 //===----------------------------------------------------------------------===//
7398 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7400 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7401 Intrinsic IntLd, Intrinsic IntLd256,
7402 Intrinsic IntSt, Intrinsic IntSt256> {
7403 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7404 (ins VR128:$src1, f128mem:$src2),
7405 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7406 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7408 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7409 (ins VR256:$src1, f256mem:$src2),
7410 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7411 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7413 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7414 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7415 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7416 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7417 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7418 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7419 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7420 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
7423 let ExeDomain = SSEPackedSingle in
7424 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7425 int_x86_avx_maskload_ps,
7426 int_x86_avx_maskload_ps_256,
7427 int_x86_avx_maskstore_ps,
7428 int_x86_avx_maskstore_ps_256>;
7429 let ExeDomain = SSEPackedDouble in
7430 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7431 int_x86_avx_maskload_pd,
7432 int_x86_avx_maskload_pd_256,
7433 int_x86_avx_maskstore_pd,
7434 int_x86_avx_maskstore_pd_256>;
7436 //===----------------------------------------------------------------------===//
7437 // VPERMIL - Permute Single and Double Floating-Point Values
7439 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7440 RegisterClass RC, X86MemOperand x86memop_f,
7441 X86MemOperand x86memop_i, PatFrag i_frag,
7442 Intrinsic IntVar, ValueType vt> {
7443 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7444 (ins RC:$src1, RC:$src2),
7445 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7446 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7447 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7448 (ins RC:$src1, x86memop_i:$src2),
7449 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7450 [(set RC:$dst, (IntVar RC:$src1,
7451 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7453 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7454 (ins RC:$src1, i8imm:$src2),
7455 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7456 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7457 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7458 (ins x86memop_f:$src1, i8imm:$src2),
7459 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7461 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7464 let ExeDomain = SSEPackedSingle in {
7465 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7466 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7467 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7468 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
7470 let ExeDomain = SSEPackedDouble in {
7471 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7472 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7473 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7474 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
7477 let Predicates = [HasAVX] in {
7478 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7479 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7480 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7481 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7482 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7484 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7485 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7486 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7488 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7489 (VPERMILPDri VR128:$src1, imm:$imm)>;
7490 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7491 (VPERMILPDmi addr:$src1, imm:$imm)>;
7494 //===----------------------------------------------------------------------===//
7495 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7497 let ExeDomain = SSEPackedSingle in {
7498 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7499 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7500 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7501 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7502 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
7503 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7504 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7505 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7506 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7507 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
7510 let Predicates = [HasAVX] in {
7511 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7512 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7513 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7514 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7515 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7518 let Predicates = [HasAVX1Only] in {
7519 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7520 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7521 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7522 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7523 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7524 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7525 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7526 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7528 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7529 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7530 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7531 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7532 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7533 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7534 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7535 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7536 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7537 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7538 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7539 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7542 //===----------------------------------------------------------------------===//
7543 // VZERO - Zero YMM registers
7545 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7546 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7547 // Zero All YMM registers
7548 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7549 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7551 // Zero Upper bits of YMM registers
7552 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7553 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7556 //===----------------------------------------------------------------------===//
7557 // Half precision conversion instructions
7558 //===----------------------------------------------------------------------===//
7559 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7560 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7561 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7562 [(set RC:$dst, (Int VR128:$src))]>,
7564 let neverHasSideEffects = 1, mayLoad = 1 in
7565 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7566 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7569 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7570 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7571 (ins RC:$src1, i32i8imm:$src2),
7572 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7573 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7575 let neverHasSideEffects = 1, mayStore = 1 in
7576 def mr : Ii8<0x1D, MRMDestMem, (outs),
7577 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
7578 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7582 let Predicates = [HasAVX, HasF16C] in {
7583 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7584 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
7585 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7586 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
7589 //===----------------------------------------------------------------------===//
7590 // AVX2 Instructions
7591 //===----------------------------------------------------------------------===//
7593 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7594 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7595 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7596 X86MemOperand x86memop> {
7597 let isCommutable = 1 in
7598 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7599 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7600 !strconcat(OpcodeStr,
7601 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7602 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7604 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7605 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7606 !strconcat(OpcodeStr,
7607 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7610 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7614 let isCommutable = 0 in {
7615 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7616 VR128, memopv2i64, i128mem>;
7617 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7618 VR256, memopv4i64, i256mem>, VEX_L;
7621 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
7623 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7624 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
7626 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7628 //===----------------------------------------------------------------------===//
7629 // VPBROADCAST - Load from memory and broadcast to all elements of the
7630 // destination operand
7632 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7633 X86MemOperand x86memop, PatFrag ld_frag,
7634 Intrinsic Int128, Intrinsic Int256> {
7635 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7636 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7637 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7638 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7639 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7641 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7642 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7643 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7644 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX, VEX_L;
7645 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7646 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7648 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
7652 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7653 int_x86_avx2_pbroadcastb_128,
7654 int_x86_avx2_pbroadcastb_256>;
7655 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7656 int_x86_avx2_pbroadcastw_128,
7657 int_x86_avx2_pbroadcastw_256>;
7658 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7659 int_x86_avx2_pbroadcastd_128,
7660 int_x86_avx2_pbroadcastd_256>;
7661 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7662 int_x86_avx2_pbroadcastq_128,
7663 int_x86_avx2_pbroadcastq_256>;
7665 let Predicates = [HasAVX2] in {
7666 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7667 (VPBROADCASTBrm addr:$src)>;
7668 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7669 (VPBROADCASTBYrm addr:$src)>;
7670 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7671 (VPBROADCASTWrm addr:$src)>;
7672 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7673 (VPBROADCASTWYrm addr:$src)>;
7674 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7675 (VPBROADCASTDrm addr:$src)>;
7676 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7677 (VPBROADCASTDYrm addr:$src)>;
7678 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
7679 (VPBROADCASTQrm addr:$src)>;
7680 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7681 (VPBROADCASTQYrm addr:$src)>;
7683 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
7684 (VPBROADCASTBrr VR128:$src)>;
7685 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
7686 (VPBROADCASTBYrr VR128:$src)>;
7687 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
7688 (VPBROADCASTWrr VR128:$src)>;
7689 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
7690 (VPBROADCASTWYrr VR128:$src)>;
7691 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
7692 (VPBROADCASTDrr VR128:$src)>;
7693 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
7694 (VPBROADCASTDYrr VR128:$src)>;
7695 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
7696 (VPBROADCASTQrr VR128:$src)>;
7697 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
7698 (VPBROADCASTQYrr VR128:$src)>;
7699 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
7700 (VBROADCASTSSrr VR128:$src)>;
7701 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
7702 (VBROADCASTSSYrr VR128:$src)>;
7703 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
7704 (VPBROADCASTQrr VR128:$src)>;
7705 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
7706 (VBROADCASTSDYrr VR128:$src)>;
7708 // Provide fallback in case the load node that is used in the patterns above
7709 // is used by additional users, which prevents the pattern selection.
7710 let AddedComplexity = 20 in {
7711 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7712 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
7713 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7714 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
7715 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7716 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
7718 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7719 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
7720 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7721 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
7722 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7723 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
7727 // AVX1 broadcast patterns
7728 let Predicates = [HasAVX1Only] in {
7729 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7730 (VBROADCASTSSYrm addr:$src)>;
7731 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7732 (VBROADCASTSDYrm addr:$src)>;
7733 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7734 (VBROADCASTSSrm addr:$src)>;
7737 let Predicates = [HasAVX] in {
7738 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
7739 (VBROADCASTSSYrm addr:$src)>;
7740 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
7741 (VBROADCASTSDYrm addr:$src)>;
7742 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
7743 (VBROADCASTSSrm addr:$src)>;
7745 // Provide fallback in case the load node that is used in the patterns above
7746 // is used by additional users, which prevents the pattern selection.
7747 let AddedComplexity = 20 in {
7748 // 128bit broadcasts:
7749 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7750 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
7751 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7752 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
7753 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
7754 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
7755 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7756 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
7757 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
7758 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
7760 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7761 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
7762 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7763 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
7764 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
7765 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
7766 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7767 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
7768 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
7769 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
7773 //===----------------------------------------------------------------------===//
7774 // VPERM - Permute instructions
7777 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7779 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7780 (ins VR256:$src1, VR256:$src2),
7781 !strconcat(OpcodeStr,
7782 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7784 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
7786 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7787 (ins VR256:$src1, i256mem:$src2),
7788 !strconcat(OpcodeStr,
7789 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7791 (OpVT (X86VPermv VR256:$src1,
7792 (bitconvert (mem_frag addr:$src2)))))]>,
7796 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, v8i32>;
7797 let ExeDomain = SSEPackedSingle in
7798 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, v8f32>;
7800 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7802 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7803 (ins VR256:$src1, i8imm:$src2),
7804 !strconcat(OpcodeStr,
7805 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7807 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
7809 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
7810 (ins i256mem:$src1, i8imm:$src2),
7811 !strconcat(OpcodeStr,
7812 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7814 (OpVT (X86VPermi (mem_frag addr:$src1),
7815 (i8 imm:$src2))))]>, VEX, VEX_L;
7818 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, v4i64>, VEX_W;
7819 let ExeDomain = SSEPackedDouble in
7820 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, v4f64>, VEX_W;
7822 //===----------------------------------------------------------------------===//
7823 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
7825 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7826 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7827 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7828 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7829 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
7830 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
7831 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7832 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7833 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
7834 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
7836 let Predicates = [HasAVX2] in {
7837 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7838 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7839 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7840 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7841 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7842 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7844 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
7846 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7847 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7848 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7849 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7850 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
7852 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7856 //===----------------------------------------------------------------------===//
7857 // VINSERTI128 - Insert packed integer values
7859 let neverHasSideEffects = 1 in {
7860 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7861 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7862 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7865 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
7866 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
7867 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7871 let Predicates = [HasAVX2] in {
7872 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7874 (VINSERTI128rr VR256:$src1, VR128:$src2,
7875 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7876 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7878 (VINSERTI128rr VR256:$src1, VR128:$src2,
7879 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7880 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7882 (VINSERTI128rr VR256:$src1, VR128:$src2,
7883 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7884 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7886 (VINSERTI128rr VR256:$src1, VR128:$src2,
7887 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7889 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
7891 (VINSERTI128rm VR256:$src1, addr:$src2,
7892 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7893 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1),
7894 (bc_v4i32 (memopv2i64 addr:$src2)),
7896 (VINSERTI128rm VR256:$src1, addr:$src2,
7897 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7898 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1),
7899 (bc_v16i8 (memopv2i64 addr:$src2)),
7901 (VINSERTI128rm VR256:$src1, addr:$src2,
7902 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7903 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1),
7904 (bc_v8i16 (memopv2i64 addr:$src2)),
7906 (VINSERTI128rm VR256:$src1, addr:$src2,
7907 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7910 //===----------------------------------------------------------------------===//
7911 // VEXTRACTI128 - Extract packed integer values
7913 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
7914 (ins VR256:$src1, i8imm:$src2),
7915 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7917 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
7919 let neverHasSideEffects = 1, mayStore = 1 in
7920 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
7921 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
7922 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7925 let Predicates = [HasAVX2] in {
7926 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7927 (v2i64 (VEXTRACTI128rr
7928 (v4i64 VR256:$src1),
7929 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7930 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7931 (v4i32 (VEXTRACTI128rr
7932 (v8i32 VR256:$src1),
7933 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7934 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7935 (v8i16 (VEXTRACTI128rr
7936 (v16i16 VR256:$src1),
7937 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7938 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7939 (v16i8 (VEXTRACTI128rr
7940 (v32i8 VR256:$src1),
7941 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7943 def : Pat<(alignedstore (v2i64 (vextractf128_extract:$ext (v4i64 VR256:$src1),
7944 (iPTR imm))), addr:$dst),
7945 (VEXTRACTI128mr addr:$dst, VR256:$src1,
7946 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7947 def : Pat<(alignedstore (v4i32 (vextractf128_extract:$ext (v8i32 VR256:$src1),
7948 (iPTR imm))), addr:$dst),
7949 (VEXTRACTI128mr addr:$dst, VR256:$src1,
7950 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7951 def : Pat<(alignedstore (v8i16 (vextractf128_extract:$ext (v16i16 VR256:$src1),
7952 (iPTR imm))), addr:$dst),
7953 (VEXTRACTI128mr addr:$dst, VR256:$src1,
7954 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7955 def : Pat<(alignedstore (v16i8 (vextractf128_extract:$ext (v32i8 VR256:$src1),
7956 (iPTR imm))), addr:$dst),
7957 (VEXTRACTI128mr addr:$dst, VR256:$src1,
7958 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7961 //===----------------------------------------------------------------------===//
7962 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
7964 multiclass avx2_pmovmask<string OpcodeStr,
7965 Intrinsic IntLd128, Intrinsic IntLd256,
7966 Intrinsic IntSt128, Intrinsic IntSt256> {
7967 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
7968 (ins VR128:$src1, i128mem:$src2),
7969 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7970 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
7971 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
7972 (ins VR256:$src1, i256mem:$src2),
7973 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7974 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7976 def mr : AVX28I<0x8e, MRMDestMem, (outs),
7977 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
7978 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7979 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7980 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
7981 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
7982 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7983 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
7986 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
7987 int_x86_avx2_maskload_d,
7988 int_x86_avx2_maskload_d_256,
7989 int_x86_avx2_maskstore_d,
7990 int_x86_avx2_maskstore_d_256>;
7991 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
7992 int_x86_avx2_maskload_q,
7993 int_x86_avx2_maskload_q_256,
7994 int_x86_avx2_maskstore_q,
7995 int_x86_avx2_maskstore_q_256>, VEX_W;
7998 //===----------------------------------------------------------------------===//
7999 // Variable Bit Shifts
8001 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8002 ValueType vt128, ValueType vt256> {
8003 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8004 (ins VR128:$src1, VR128:$src2),
8005 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8007 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8009 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8010 (ins VR128:$src1, i128mem:$src2),
8011 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8013 (vt128 (OpNode VR128:$src1,
8014 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
8016 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8017 (ins VR256:$src1, VR256:$src2),
8018 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8020 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8022 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8023 (ins VR256:$src1, i256mem:$src2),
8024 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8026 (vt256 (OpNode VR256:$src1,
8027 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
8031 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8032 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8033 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8034 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8035 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8037 //===----------------------------------------------------------------------===//
8038 // VGATHER - GATHER Operations
8039 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8040 X86MemOperand memop128, X86MemOperand memop256> {
8041 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8042 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8043 !strconcat(OpcodeStr,
8044 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8046 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8047 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8048 !strconcat(OpcodeStr,
8049 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8050 []>, VEX_4VOp3, VEX_L;
8053 let mayLoad = 1, Constraints = "$src1 = $dst, $mask = $mask_wb" in {
8054 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8055 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8056 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8057 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;
8058 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8059 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8060 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8061 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;