1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pshufb : SDNode<"X86ISD::PSHUFB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
42 def X86pextrb : SDNode<"X86ISD::PEXTRB",
43 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
44 def X86pextrw : SDNode<"X86ISD::PEXTRW",
45 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
46 def X86pinsrb : SDNode<"X86ISD::PINSRB",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86pinsrw : SDNode<"X86ISD::PINSRW",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
52 def X86insrtps : SDNode<"X86ISD::INSERTPS",
53 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
54 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
55 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
56 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
57 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
58 [SDNPHasChain, SDNPMayLoad]>;
59 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
60 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
61 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
62 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
63 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
65 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
66 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
67 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
68 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
69 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
70 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
72 def SDTX86CmpPTest : SDTypeProfile<0, 2, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4f32>]>;
73 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
75 //===----------------------------------------------------------------------===//
76 // SSE Complex Patterns
77 //===----------------------------------------------------------------------===//
79 // These are 'extloads' from a scalar to the low element of a vector, zeroing
80 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
82 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
83 [SDNPHasChain, SDNPMayLoad]>;
84 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
85 [SDNPHasChain, SDNPMayLoad]>;
87 def ssmem : Operand<v4f32> {
88 let PrintMethod = "printf32mem";
89 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
90 let ParserMatchClass = X86MemAsmOperand;
92 def sdmem : Operand<v2f64> {
93 let PrintMethod = "printf64mem";
94 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
95 let ParserMatchClass = X86MemAsmOperand;
98 //===----------------------------------------------------------------------===//
99 // SSE pattern fragments
100 //===----------------------------------------------------------------------===//
102 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
103 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
104 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
105 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
107 // Like 'store', but always requires vector alignment.
108 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
109 (store node:$val, node:$ptr), [{
110 return cast<StoreSDNode>(N)->getAlignment() >= 16;
113 // Like 'load', but always requires vector alignment.
114 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
115 return cast<LoadSDNode>(N)->getAlignment() >= 16;
118 def alignedloadfsf32 : PatFrag<(ops node:$ptr), (f32 (alignedload node:$ptr))>;
119 def alignedloadfsf64 : PatFrag<(ops node:$ptr), (f64 (alignedload node:$ptr))>;
120 def alignedloadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (alignedload node:$ptr))>;
121 def alignedloadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (alignedload node:$ptr))>;
122 def alignedloadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (alignedload node:$ptr))>;
123 def alignedloadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (alignedload node:$ptr))>;
125 // Like 'load', but uses special alignment checks suitable for use in
126 // memory operands in most SSE instructions, which are required to
127 // be naturally aligned on some targets but not on others.
128 // FIXME: Actually implement support for targets that don't require the
129 // alignment. This probably wants a subtarget predicate.
130 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
131 return cast<LoadSDNode>(N)->getAlignment() >= 16;
134 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
135 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
136 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
137 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
138 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
139 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
140 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
142 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
144 // FIXME: 8 byte alignment for mmx reads is not required
145 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
146 return cast<LoadSDNode>(N)->getAlignment() >= 8;
149 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
150 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
151 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
152 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
154 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
155 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
156 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
157 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
158 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
159 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
161 def vzmovl_v2i64 : PatFrag<(ops node:$src),
162 (bitconvert (v2i64 (X86vzmovl
163 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
164 def vzmovl_v4i32 : PatFrag<(ops node:$src),
165 (bitconvert (v4i32 (X86vzmovl
166 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
168 def vzload_v2i64 : PatFrag<(ops node:$src),
169 (bitconvert (v2i64 (X86vzload node:$src)))>;
172 def fp32imm0 : PatLeaf<(f32 fpimm), [{
173 return N->isExactlyValue(+0.0);
176 def PSxLDQ_imm : SDNodeXForm<imm, [{
177 // Transformation function: imm >> 3
178 return getI32Imm(N->getZExtValue() >> 3);
181 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
183 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
184 return getI8Imm(X86::getShuffleSHUFImmediate(N));
187 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
189 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
190 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
193 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
195 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
196 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
199 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
200 (vector_shuffle node:$lhs, node:$rhs), [{
201 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
202 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
205 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
206 (vector_shuffle node:$lhs, node:$rhs), [{
207 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
210 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
211 (vector_shuffle node:$lhs, node:$rhs), [{
212 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
215 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
216 (vector_shuffle node:$lhs, node:$rhs), [{
217 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
220 def movhp : PatFrag<(ops node:$lhs, node:$rhs),
221 (vector_shuffle node:$lhs, node:$rhs), [{
222 return X86::isMOVHPMask(cast<ShuffleVectorSDNode>(N));
225 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
226 (vector_shuffle node:$lhs, node:$rhs), [{
227 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
230 def movl : PatFrag<(ops node:$lhs, node:$rhs),
231 (vector_shuffle node:$lhs, node:$rhs), [{
232 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
235 def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
236 (vector_shuffle node:$lhs, node:$rhs), [{
237 return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
240 def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
241 (vector_shuffle node:$lhs, node:$rhs), [{
242 return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
245 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
246 (vector_shuffle node:$lhs, node:$rhs), [{
247 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
250 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
251 (vector_shuffle node:$lhs, node:$rhs), [{
252 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
255 def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
256 (vector_shuffle node:$lhs, node:$rhs), [{
257 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
260 def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
261 (vector_shuffle node:$lhs, node:$rhs), [{
262 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
265 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
266 (vector_shuffle node:$lhs, node:$rhs), [{
267 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
268 }], SHUFFLE_get_shuf_imm>;
270 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
271 (vector_shuffle node:$lhs, node:$rhs), [{
272 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
273 }], SHUFFLE_get_shuf_imm>;
275 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
276 (vector_shuffle node:$lhs, node:$rhs), [{
277 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
278 }], SHUFFLE_get_pshufhw_imm>;
280 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
281 (vector_shuffle node:$lhs, node:$rhs), [{
282 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
283 }], SHUFFLE_get_pshuflw_imm>;
285 //===----------------------------------------------------------------------===//
286 // SSE scalar FP Instructions
287 //===----------------------------------------------------------------------===//
289 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
290 // scheduler into a branch sequence.
291 // These are expanded by the scheduler.
292 let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
293 def CMOV_FR32 : I<0, Pseudo,
294 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
295 "#CMOV_FR32 PSEUDO!",
296 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
298 def CMOV_FR64 : I<0, Pseudo,
299 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
300 "#CMOV_FR64 PSEUDO!",
301 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
303 def CMOV_V4F32 : I<0, Pseudo,
304 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
305 "#CMOV_V4F32 PSEUDO!",
307 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
309 def CMOV_V2F64 : I<0, Pseudo,
310 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
311 "#CMOV_V2F64 PSEUDO!",
313 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
315 def CMOV_V2I64 : I<0, Pseudo,
316 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
317 "#CMOV_V2I64 PSEUDO!",
319 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
323 //===----------------------------------------------------------------------===//
325 //===----------------------------------------------------------------------===//
328 let neverHasSideEffects = 1 in
329 def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
330 "movss\t{$src, $dst|$dst, $src}", []>;
331 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
332 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
333 "movss\t{$src, $dst|$dst, $src}",
334 [(set FR32:$dst, (loadf32 addr:$src))]>;
335 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
336 "movss\t{$src, $dst|$dst, $src}",
337 [(store FR32:$src, addr:$dst)]>;
339 // Conversion instructions
340 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
341 "cvttss2si\t{$src, $dst|$dst, $src}",
342 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
343 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
344 "cvttss2si\t{$src, $dst|$dst, $src}",
345 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
346 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
347 "cvtsi2ss\t{$src, $dst|$dst, $src}",
348 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
349 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
350 "cvtsi2ss\t{$src, $dst|$dst, $src}",
351 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
353 // Match intrinsics which expect XMM operand(s).
354 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
355 "cvtss2si\t{$src, $dst|$dst, $src}",
356 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
357 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
358 "cvtss2si\t{$src, $dst|$dst, $src}",
359 [(set GR32:$dst, (int_x86_sse_cvtss2si
360 (load addr:$src)))]>;
362 // Match intrinisics which expect MM and XMM operand(s).
363 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
364 "cvtps2pi\t{$src, $dst|$dst, $src}",
365 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
366 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
367 "cvtps2pi\t{$src, $dst|$dst, $src}",
368 [(set VR64:$dst, (int_x86_sse_cvtps2pi
369 (load addr:$src)))]>;
370 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
371 "cvttps2pi\t{$src, $dst|$dst, $src}",
372 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
373 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
374 "cvttps2pi\t{$src, $dst|$dst, $src}",
375 [(set VR64:$dst, (int_x86_sse_cvttps2pi
376 (load addr:$src)))]>;
377 let Constraints = "$src1 = $dst" in {
378 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
379 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
380 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
381 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
383 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
384 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
385 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
386 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
387 (load addr:$src2)))]>;
390 // Aliases for intrinsics
391 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
392 "cvttss2si\t{$src, $dst|$dst, $src}",
394 (int_x86_sse_cvttss2si VR128:$src))]>;
395 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
396 "cvttss2si\t{$src, $dst|$dst, $src}",
398 (int_x86_sse_cvttss2si(load addr:$src)))]>;
400 let Constraints = "$src1 = $dst" in {
401 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
402 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
403 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
404 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
406 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
407 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
408 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
409 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
410 (loadi32 addr:$src2)))]>;
413 // Comparison instructions
414 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
415 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
416 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
417 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
419 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
420 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
421 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
424 let Defs = [EFLAGS] in {
425 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
426 "ucomiss\t{$src2, $src1|$src1, $src2}",
427 [(X86cmp FR32:$src1, FR32:$src2), (implicit EFLAGS)]>;
428 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
429 "ucomiss\t{$src2, $src1|$src1, $src2}",
430 [(X86cmp FR32:$src1, (loadf32 addr:$src2)),
434 // Aliases to match intrinsics which expect XMM operand(s).
435 let Constraints = "$src1 = $dst" in {
436 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
437 (outs VR128:$dst), (ins VR128:$src1, VR128:$src,
439 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
440 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
441 VR128:$src, imm:$cc))]>;
442 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
443 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src,
445 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
446 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
447 (load addr:$src), imm:$cc))]>;
450 let Defs = [EFLAGS] in {
451 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
452 "ucomiss\t{$src2, $src1|$src1, $src2}",
453 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2),
455 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
456 "ucomiss\t{$src2, $src1|$src1, $src2}",
457 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2)),
460 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
461 "comiss\t{$src2, $src1|$src1, $src2}",
462 [(X86comi (v4f32 VR128:$src1), VR128:$src2),
464 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
465 "comiss\t{$src2, $src1|$src1, $src2}",
466 [(X86comi (v4f32 VR128:$src1), (load addr:$src2)),
470 // Aliases of packed SSE1 instructions for scalar use. These all have names
471 // that start with 'Fs'.
473 // Alias instructions that map fld0 to pxor for sse.
474 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
475 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
476 "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
477 Requires<[HasSSE1]>, TB, OpSize;
479 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
481 let neverHasSideEffects = 1 in
482 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
483 "movaps\t{$src, $dst|$dst, $src}", []>;
485 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
487 let canFoldAsLoad = 1 in
488 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
489 "movaps\t{$src, $dst|$dst, $src}",
490 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
492 // Alias bitwise logical operations using SSE logical ops on packed FP values.
493 let Constraints = "$src1 = $dst" in {
494 let isCommutable = 1 in {
495 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst),
496 (ins FR32:$src1, FR32:$src2),
497 "andps\t{$src2, $dst|$dst, $src2}",
498 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
499 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst),
500 (ins FR32:$src1, FR32:$src2),
501 "orps\t{$src2, $dst|$dst, $src2}",
502 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
503 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst),
504 (ins FR32:$src1, FR32:$src2),
505 "xorps\t{$src2, $dst|$dst, $src2}",
506 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
509 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst),
510 (ins FR32:$src1, f128mem:$src2),
511 "andps\t{$src2, $dst|$dst, $src2}",
512 [(set FR32:$dst, (X86fand FR32:$src1,
513 (memopfsf32 addr:$src2)))]>;
514 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst),
515 (ins FR32:$src1, f128mem:$src2),
516 "orps\t{$src2, $dst|$dst, $src2}",
517 [(set FR32:$dst, (X86for FR32:$src1,
518 (memopfsf32 addr:$src2)))]>;
519 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst),
520 (ins FR32:$src1, f128mem:$src2),
521 "xorps\t{$src2, $dst|$dst, $src2}",
522 [(set FR32:$dst, (X86fxor FR32:$src1,
523 (memopfsf32 addr:$src2)))]>;
525 let neverHasSideEffects = 1 in {
526 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
527 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
528 "andnps\t{$src2, $dst|$dst, $src2}", []>;
530 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
531 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
532 "andnps\t{$src2, $dst|$dst, $src2}", []>;
536 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
538 /// In addition, we also have a special variant of the scalar form here to
539 /// represent the associated intrinsic operation. This form is unlike the
540 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
541 /// and leaves the top elements unmodified (therefore these cannot be commuted).
543 /// These three forms can each be reg+reg or reg+mem, so there are a total of
544 /// six "instructions".
546 let Constraints = "$src1 = $dst" in {
547 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
548 SDNode OpNode, Intrinsic F32Int,
549 bit Commutable = 0> {
550 // Scalar operation, reg+reg.
551 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
552 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
553 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
554 let isCommutable = Commutable;
557 // Scalar operation, reg+mem.
558 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
559 (ins FR32:$src1, f32mem:$src2),
560 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
561 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
563 // Vector operation, reg+reg.
564 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
565 (ins VR128:$src1, VR128:$src2),
566 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
567 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
568 let isCommutable = Commutable;
571 // Vector operation, reg+mem.
572 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
573 (ins VR128:$src1, f128mem:$src2),
574 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
575 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
577 // Intrinsic operation, reg+reg.
578 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
579 (ins VR128:$src1, VR128:$src2),
580 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
581 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]>;
583 // Intrinsic operation, reg+mem.
584 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
585 (ins VR128:$src1, ssmem:$src2),
586 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
587 [(set VR128:$dst, (F32Int VR128:$src1,
588 sse_load_f32:$src2))]>;
592 // Arithmetic instructions
593 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
594 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
595 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
596 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
598 /// sse1_fp_binop_rm - Other SSE1 binops
600 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
601 /// instructions for a full-vector intrinsic form. Operations that map
602 /// onto C operators don't use this form since they just use the plain
603 /// vector form instead of having a separate vector intrinsic form.
605 /// This provides a total of eight "instructions".
607 let Constraints = "$src1 = $dst" in {
608 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
612 bit Commutable = 0> {
614 // Scalar operation, reg+reg.
615 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
616 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
617 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
618 let isCommutable = Commutable;
621 // Scalar operation, reg+mem.
622 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
623 (ins FR32:$src1, f32mem:$src2),
624 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
625 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
627 // Vector operation, reg+reg.
628 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
629 (ins VR128:$src1, VR128:$src2),
630 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
631 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
632 let isCommutable = Commutable;
635 // Vector operation, reg+mem.
636 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
637 (ins VR128:$src1, f128mem:$src2),
638 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
639 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
641 // Intrinsic operation, reg+reg.
642 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
643 (ins VR128:$src1, VR128:$src2),
644 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
645 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
646 let isCommutable = Commutable;
649 // Intrinsic operation, reg+mem.
650 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
651 (ins VR128:$src1, ssmem:$src2),
652 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
653 [(set VR128:$dst, (F32Int VR128:$src1,
654 sse_load_f32:$src2))]>;
656 // Vector intrinsic operation, reg+reg.
657 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
658 (ins VR128:$src1, VR128:$src2),
659 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
660 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
661 let isCommutable = Commutable;
664 // Vector intrinsic operation, reg+mem.
665 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
666 (ins VR128:$src1, f128mem:$src2),
667 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
668 [(set VR128:$dst, (V4F32Int VR128:$src1, (memopv4f32 addr:$src2)))]>;
672 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
673 int_x86_sse_max_ss, int_x86_sse_max_ps>;
674 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
675 int_x86_sse_min_ss, int_x86_sse_min_ps>;
677 //===----------------------------------------------------------------------===//
678 // SSE packed FP Instructions
681 let neverHasSideEffects = 1 in
682 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
683 "movaps\t{$src, $dst|$dst, $src}", []>;
684 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
685 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
686 "movaps\t{$src, $dst|$dst, $src}",
687 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
689 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
690 "movaps\t{$src, $dst|$dst, $src}",
691 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
693 let neverHasSideEffects = 1 in
694 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
695 "movups\t{$src, $dst|$dst, $src}", []>;
696 let canFoldAsLoad = 1 in
697 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
698 "movups\t{$src, $dst|$dst, $src}",
699 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
700 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
701 "movups\t{$src, $dst|$dst, $src}",
702 [(store (v4f32 VR128:$src), addr:$dst)]>;
704 // Intrinsic forms of MOVUPS load and store
705 let canFoldAsLoad = 1 in
706 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
707 "movups\t{$src, $dst|$dst, $src}",
708 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
709 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
710 "movups\t{$src, $dst|$dst, $src}",
711 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
713 let Constraints = "$src1 = $dst" in {
714 let AddedComplexity = 20 in {
715 def MOVLPSrm : PSI<0x12, MRMSrcMem,
716 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
717 "movlps\t{$src2, $dst|$dst, $src2}",
720 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
721 def MOVHPSrm : PSI<0x16, MRMSrcMem,
722 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
723 "movhps\t{$src2, $dst|$dst, $src2}",
726 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
728 } // Constraints = "$src1 = $dst"
731 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
732 "movlps\t{$src, $dst|$dst, $src}",
733 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
734 (iPTR 0))), addr:$dst)]>;
736 // v2f64 extract element 1 is always custom lowered to unpack high to low
737 // and extract element 0 so the non-store version isn't too horrible.
738 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
739 "movhps\t{$src, $dst|$dst, $src}",
740 [(store (f64 (vector_extract
741 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
742 (undef)), (iPTR 0))), addr:$dst)]>;
744 let Constraints = "$src1 = $dst" in {
745 let AddedComplexity = 20 in {
746 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
747 (ins VR128:$src1, VR128:$src2),
748 "movlhps\t{$src2, $dst|$dst, $src2}",
750 (v4f32 (movhp VR128:$src1, VR128:$src2)))]>;
752 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
753 (ins VR128:$src1, VR128:$src2),
754 "movhlps\t{$src2, $dst|$dst, $src2}",
756 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
758 } // Constraints = "$src1 = $dst"
760 let AddedComplexity = 20 in {
761 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
762 (MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
763 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
764 (MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
771 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
773 /// In addition, we also have a special variant of the scalar form here to
774 /// represent the associated intrinsic operation. This form is unlike the
775 /// plain scalar form, in that it takes an entire vector (instead of a
776 /// scalar) and leaves the top elements undefined.
778 /// And, we have a special variant form for a full-vector intrinsic form.
780 /// These four forms can each have a reg or a mem operand, so there are a
781 /// total of eight "instructions".
783 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
787 bit Commutable = 0> {
788 // Scalar operation, reg.
789 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
790 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
791 [(set FR32:$dst, (OpNode FR32:$src))]> {
792 let isCommutable = Commutable;
795 // Scalar operation, mem.
796 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
797 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
798 [(set FR32:$dst, (OpNode (load addr:$src)))]>;
800 // Vector operation, reg.
801 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
802 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
803 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
804 let isCommutable = Commutable;
807 // Vector operation, mem.
808 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
809 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
810 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
812 // Intrinsic operation, reg.
813 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
814 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
815 [(set VR128:$dst, (F32Int VR128:$src))]> {
816 let isCommutable = Commutable;
819 // Intrinsic operation, mem.
820 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
821 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
822 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
824 // Vector intrinsic operation, reg
825 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
826 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
827 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
828 let isCommutable = Commutable;
831 // Vector intrinsic operation, mem
832 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
833 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
834 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
838 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
839 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
841 // Reciprocal approximations. Note that these typically require refinement
842 // in order to obtain suitable precision.
843 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
844 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
845 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
846 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
849 let Constraints = "$src1 = $dst" in {
850 let isCommutable = 1 in {
851 def ANDPSrr : PSI<0x54, MRMSrcReg,
852 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
853 "andps\t{$src2, $dst|$dst, $src2}",
854 [(set VR128:$dst, (v2i64
855 (and VR128:$src1, VR128:$src2)))]>;
856 def ORPSrr : PSI<0x56, MRMSrcReg,
857 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
858 "orps\t{$src2, $dst|$dst, $src2}",
859 [(set VR128:$dst, (v2i64
860 (or VR128:$src1, VR128:$src2)))]>;
861 def XORPSrr : PSI<0x57, MRMSrcReg,
862 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
863 "xorps\t{$src2, $dst|$dst, $src2}",
864 [(set VR128:$dst, (v2i64
865 (xor VR128:$src1, VR128:$src2)))]>;
868 def ANDPSrm : PSI<0x54, MRMSrcMem,
869 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
870 "andps\t{$src2, $dst|$dst, $src2}",
871 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
872 (memopv2i64 addr:$src2)))]>;
873 def ORPSrm : PSI<0x56, MRMSrcMem,
874 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
875 "orps\t{$src2, $dst|$dst, $src2}",
876 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
877 (memopv2i64 addr:$src2)))]>;
878 def XORPSrm : PSI<0x57, MRMSrcMem,
879 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
880 "xorps\t{$src2, $dst|$dst, $src2}",
881 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
882 (memopv2i64 addr:$src2)))]>;
883 def ANDNPSrr : PSI<0x55, MRMSrcReg,
884 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
885 "andnps\t{$src2, $dst|$dst, $src2}",
887 (v2i64 (and (xor VR128:$src1,
888 (bc_v2i64 (v4i32 immAllOnesV))),
890 def ANDNPSrm : PSI<0x55, MRMSrcMem,
891 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
892 "andnps\t{$src2, $dst|$dst, $src2}",
894 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
895 (bc_v2i64 (v4i32 immAllOnesV))),
896 (memopv2i64 addr:$src2))))]>;
899 let Constraints = "$src1 = $dst" in {
900 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
901 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
902 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
903 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
904 VR128:$src, imm:$cc))]>;
905 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
906 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
907 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
908 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
909 (memop addr:$src), imm:$cc))]>;
911 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
912 (CMPPSrri VR128:$src1, VR128:$src2, imm:$cc)>;
913 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
914 (CMPPSrmi VR128:$src1, addr:$src2, imm:$cc)>;
916 // Shuffle and unpack instructions
917 let Constraints = "$src1 = $dst" in {
918 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
919 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
920 (outs VR128:$dst), (ins VR128:$src1,
921 VR128:$src2, i8imm:$src3),
922 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
924 (v4f32 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
925 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
926 (outs VR128:$dst), (ins VR128:$src1,
927 f128mem:$src2, i8imm:$src3),
928 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
931 VR128:$src1, (memopv4f32 addr:$src2))))]>;
933 let AddedComplexity = 10 in {
934 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
935 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
936 "unpckhps\t{$src2, $dst|$dst, $src2}",
938 (v4f32 (unpckh VR128:$src1, VR128:$src2)))]>;
939 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
940 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
941 "unpckhps\t{$src2, $dst|$dst, $src2}",
943 (v4f32 (unpckh VR128:$src1,
944 (memopv4f32 addr:$src2))))]>;
946 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
947 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
948 "unpcklps\t{$src2, $dst|$dst, $src2}",
950 (v4f32 (unpckl VR128:$src1, VR128:$src2)))]>;
951 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
952 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
953 "unpcklps\t{$src2, $dst|$dst, $src2}",
955 (unpckl VR128:$src1, (memopv4f32 addr:$src2)))]>;
957 } // Constraints = "$src1 = $dst"
960 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
961 "movmskps\t{$src, $dst|$dst, $src}",
962 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
963 def MOVMSKPDrr : PDI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
964 "movmskpd\t{$src, $dst|$dst, $src}",
965 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
967 // Prefetch intrinsic.
968 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
969 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
970 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
971 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
972 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
973 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
974 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
975 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
977 // Non-temporal stores
978 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
979 "movntps\t{$src, $dst|$dst, $src}",
980 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
982 // Load, store, and memory fence
983 def SFENCE : PSI<0xAE, MRM7r, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
986 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
987 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
988 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
989 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
991 // Alias instructions that map zero vector to pxor / xorp* for sse.
992 // We set canFoldAsLoad because this can be converted to a constant-pool
993 // load of an all-zeros value if folding it would be beneficial.
994 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1 in
995 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
997 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
999 let Predicates = [HasSSE1] in {
1000 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
1001 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
1002 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
1003 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
1004 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
1007 // FR32 to 128-bit vector conversion.
1008 let isAsCheapAsAMove = 1 in
1009 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
1010 "movss\t{$src, $dst|$dst, $src}",
1012 (v4f32 (scalar_to_vector FR32:$src)))]>;
1013 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1014 "movss\t{$src, $dst|$dst, $src}",
1016 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
1018 // FIXME: may not be able to eliminate this movss with coalescing the src and
1019 // dest register classes are different. We really want to write this pattern
1021 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1022 // (f32 FR32:$src)>;
1023 let isAsCheapAsAMove = 1 in
1024 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src),
1025 "movss\t{$src, $dst|$dst, $src}",
1026 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
1028 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
1029 "movss\t{$src, $dst|$dst, $src}",
1030 [(store (f32 (vector_extract (v4f32 VR128:$src),
1031 (iPTR 0))), addr:$dst)]>;
1034 // Move to lower bits of a VR128, leaving upper bits alone.
1035 // Three operand (but two address) aliases.
1036 let Constraints = "$src1 = $dst" in {
1037 let neverHasSideEffects = 1 in
1038 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
1039 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
1040 "movss\t{$src2, $dst|$dst, $src2}", []>;
1042 let AddedComplexity = 15 in
1043 def MOVLPSrr : SSI<0x10, MRMSrcReg,
1044 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1045 "movss\t{$src2, $dst|$dst, $src2}",
1047 (v4f32 (movl VR128:$src1, VR128:$src2)))]>;
1050 // Move to lower bits of a VR128 and zeroing upper bits.
1051 // Loading from memory automatically zeroing upper bits.
1052 let AddedComplexity = 20 in
1053 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1054 "movss\t{$src, $dst|$dst, $src}",
1055 [(set VR128:$dst, (v4f32 (X86vzmovl (v4f32 (scalar_to_vector
1056 (loadf32 addr:$src))))))]>;
1058 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1059 (MOVZSS2PSrm addr:$src)>;
1061 //===---------------------------------------------------------------------===//
1062 // SSE2 Instructions
1063 //===---------------------------------------------------------------------===//
1065 // Move Instructions
1066 let neverHasSideEffects = 1 in
1067 def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1068 "movsd\t{$src, $dst|$dst, $src}", []>;
1069 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1070 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1071 "movsd\t{$src, $dst|$dst, $src}",
1072 [(set FR64:$dst, (loadf64 addr:$src))]>;
1073 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1074 "movsd\t{$src, $dst|$dst, $src}",
1075 [(store FR64:$src, addr:$dst)]>;
1077 // Conversion instructions
1078 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1079 "cvttsd2si\t{$src, $dst|$dst, $src}",
1080 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1081 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1082 "cvttsd2si\t{$src, $dst|$dst, $src}",
1083 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1084 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1085 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1086 [(set FR32:$dst, (fround FR64:$src))]>;
1087 def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1088 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1089 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
1090 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1091 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1092 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1093 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1094 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1095 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1097 // SSE2 instructions with XS prefix
1098 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1099 "cvtss2sd\t{$src, $dst|$dst, $src}",
1100 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1101 Requires<[HasSSE2]>;
1102 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1103 "cvtss2sd\t{$src, $dst|$dst, $src}",
1104 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1105 Requires<[HasSSE2]>;
1107 // Match intrinsics which expect XMM operand(s).
1108 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1109 "cvtsd2si\t{$src, $dst|$dst, $src}",
1110 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1111 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1112 "cvtsd2si\t{$src, $dst|$dst, $src}",
1113 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1114 (load addr:$src)))]>;
1116 // Match intrinisics which expect MM and XMM operand(s).
1117 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1118 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1119 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1120 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1121 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1122 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1123 (memop addr:$src)))]>;
1124 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1125 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1126 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1127 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1128 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1129 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1130 (memop addr:$src)))]>;
1131 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1132 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1133 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1134 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1135 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1136 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1137 (load addr:$src)))]>;
1139 // Aliases for intrinsics
1140 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1141 "cvttsd2si\t{$src, $dst|$dst, $src}",
1143 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1144 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1145 "cvttsd2si\t{$src, $dst|$dst, $src}",
1146 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1147 (load addr:$src)))]>;
1149 // Comparison instructions
1150 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1151 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1152 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1153 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1155 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1156 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1157 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1160 let Defs = [EFLAGS] in {
1161 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1162 "ucomisd\t{$src2, $src1|$src1, $src2}",
1163 [(X86cmp FR64:$src1, FR64:$src2), (implicit EFLAGS)]>;
1164 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1165 "ucomisd\t{$src2, $src1|$src1, $src2}",
1166 [(X86cmp FR64:$src1, (loadf64 addr:$src2)),
1167 (implicit EFLAGS)]>;
1168 } // Defs = [EFLAGS]
1170 // Aliases to match intrinsics which expect XMM operand(s).
1171 let Constraints = "$src1 = $dst" in {
1172 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1173 (outs VR128:$dst), (ins VR128:$src1, VR128:$src,
1175 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1176 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1177 VR128:$src, imm:$cc))]>;
1178 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1179 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src,
1181 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1182 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1183 (load addr:$src), imm:$cc))]>;
1186 let Defs = [EFLAGS] in {
1187 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1188 "ucomisd\t{$src2, $src1|$src1, $src2}",
1189 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1190 (implicit EFLAGS)]>;
1191 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1192 "ucomisd\t{$src2, $src1|$src1, $src2}",
1193 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2)),
1194 (implicit EFLAGS)]>;
1196 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1197 "comisd\t{$src2, $src1|$src1, $src2}",
1198 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1199 (implicit EFLAGS)]>;
1200 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1201 "comisd\t{$src2, $src1|$src1, $src2}",
1202 [(X86comi (v2f64 VR128:$src1), (load addr:$src2)),
1203 (implicit EFLAGS)]>;
1204 } // Defs = [EFLAGS]
1206 // Aliases of packed SSE2 instructions for scalar use. These all have names
1207 // that start with 'Fs'.
1209 // Alias instructions that map fld0 to pxor for sse.
1210 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1211 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
1212 "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
1213 Requires<[HasSSE2]>, TB, OpSize;
1215 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1217 let neverHasSideEffects = 1 in
1218 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1219 "movapd\t{$src, $dst|$dst, $src}", []>;
1221 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1223 let canFoldAsLoad = 1 in
1224 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1225 "movapd\t{$src, $dst|$dst, $src}",
1226 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1228 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1229 let Constraints = "$src1 = $dst" in {
1230 let isCommutable = 1 in {
1231 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst),
1232 (ins FR64:$src1, FR64:$src2),
1233 "andpd\t{$src2, $dst|$dst, $src2}",
1234 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1235 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst),
1236 (ins FR64:$src1, FR64:$src2),
1237 "orpd\t{$src2, $dst|$dst, $src2}",
1238 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1239 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst),
1240 (ins FR64:$src1, FR64:$src2),
1241 "xorpd\t{$src2, $dst|$dst, $src2}",
1242 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1245 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst),
1246 (ins FR64:$src1, f128mem:$src2),
1247 "andpd\t{$src2, $dst|$dst, $src2}",
1248 [(set FR64:$dst, (X86fand FR64:$src1,
1249 (memopfsf64 addr:$src2)))]>;
1250 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst),
1251 (ins FR64:$src1, f128mem:$src2),
1252 "orpd\t{$src2, $dst|$dst, $src2}",
1253 [(set FR64:$dst, (X86for FR64:$src1,
1254 (memopfsf64 addr:$src2)))]>;
1255 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst),
1256 (ins FR64:$src1, f128mem:$src2),
1257 "xorpd\t{$src2, $dst|$dst, $src2}",
1258 [(set FR64:$dst, (X86fxor FR64:$src1,
1259 (memopfsf64 addr:$src2)))]>;
1261 let neverHasSideEffects = 1 in {
1262 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1263 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1264 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1266 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1267 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1268 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1272 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1274 /// In addition, we also have a special variant of the scalar form here to
1275 /// represent the associated intrinsic operation. This form is unlike the
1276 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1277 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1279 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1280 /// six "instructions".
1282 let Constraints = "$src1 = $dst" in {
1283 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1284 SDNode OpNode, Intrinsic F64Int,
1285 bit Commutable = 0> {
1286 // Scalar operation, reg+reg.
1287 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1288 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1289 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1290 let isCommutable = Commutable;
1293 // Scalar operation, reg+mem.
1294 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1295 (ins FR64:$src1, f64mem:$src2),
1296 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1297 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1299 // Vector operation, reg+reg.
1300 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1301 (ins VR128:$src1, VR128:$src2),
1302 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1303 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1304 let isCommutable = Commutable;
1307 // Vector operation, reg+mem.
1308 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1309 (ins VR128:$src1, f128mem:$src2),
1310 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1311 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1313 // Intrinsic operation, reg+reg.
1314 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1315 (ins VR128:$src1, VR128:$src2),
1316 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1317 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]>;
1319 // Intrinsic operation, reg+mem.
1320 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1321 (ins VR128:$src1, sdmem:$src2),
1322 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1323 [(set VR128:$dst, (F64Int VR128:$src1,
1324 sse_load_f64:$src2))]>;
1328 // Arithmetic instructions
1329 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1330 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1331 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1332 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1334 /// sse2_fp_binop_rm - Other SSE2 binops
1336 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1337 /// instructions for a full-vector intrinsic form. Operations that map
1338 /// onto C operators don't use this form since they just use the plain
1339 /// vector form instead of having a separate vector intrinsic form.
1341 /// This provides a total of eight "instructions".
1343 let Constraints = "$src1 = $dst" in {
1344 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1348 bit Commutable = 0> {
1350 // Scalar operation, reg+reg.
1351 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1352 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1353 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1354 let isCommutable = Commutable;
1357 // Scalar operation, reg+mem.
1358 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1359 (ins FR64:$src1, f64mem:$src2),
1360 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1361 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1363 // Vector operation, reg+reg.
1364 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1365 (ins VR128:$src1, VR128:$src2),
1366 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1367 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1368 let isCommutable = Commutable;
1371 // Vector operation, reg+mem.
1372 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1373 (ins VR128:$src1, f128mem:$src2),
1374 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1375 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1377 // Intrinsic operation, reg+reg.
1378 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1379 (ins VR128:$src1, VR128:$src2),
1380 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1381 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1382 let isCommutable = Commutable;
1385 // Intrinsic operation, reg+mem.
1386 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1387 (ins VR128:$src1, sdmem:$src2),
1388 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1389 [(set VR128:$dst, (F64Int VR128:$src1,
1390 sse_load_f64:$src2))]>;
1392 // Vector intrinsic operation, reg+reg.
1393 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1394 (ins VR128:$src1, VR128:$src2),
1395 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1396 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1397 let isCommutable = Commutable;
1400 // Vector intrinsic operation, reg+mem.
1401 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1402 (ins VR128:$src1, f128mem:$src2),
1403 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1404 [(set VR128:$dst, (V2F64Int VR128:$src1,
1405 (memopv2f64 addr:$src2)))]>;
1409 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1410 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1411 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1412 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1414 //===---------------------------------------------------------------------===//
1415 // SSE packed FP Instructions
1417 // Move Instructions
1418 let neverHasSideEffects = 1 in
1419 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1420 "movapd\t{$src, $dst|$dst, $src}", []>;
1421 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1422 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1423 "movapd\t{$src, $dst|$dst, $src}",
1424 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1426 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1427 "movapd\t{$src, $dst|$dst, $src}",
1428 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1430 let neverHasSideEffects = 1 in
1431 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1432 "movupd\t{$src, $dst|$dst, $src}", []>;
1433 let canFoldAsLoad = 1 in
1434 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1435 "movupd\t{$src, $dst|$dst, $src}",
1436 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1437 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1438 "movupd\t{$src, $dst|$dst, $src}",
1439 [(store (v2f64 VR128:$src), addr:$dst)]>;
1441 // Intrinsic forms of MOVUPD load and store
1442 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1443 "movupd\t{$src, $dst|$dst, $src}",
1444 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1445 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1446 "movupd\t{$src, $dst|$dst, $src}",
1447 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1449 let Constraints = "$src1 = $dst" in {
1450 let AddedComplexity = 20 in {
1451 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1452 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1453 "movlpd\t{$src2, $dst|$dst, $src2}",
1455 (v2f64 (movlp VR128:$src1,
1456 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1457 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1458 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1459 "movhpd\t{$src2, $dst|$dst, $src2}",
1461 (v2f64 (movhp VR128:$src1,
1462 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1463 } // AddedComplexity
1464 } // Constraints = "$src1 = $dst"
1466 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1467 "movlpd\t{$src, $dst|$dst, $src}",
1468 [(store (f64 (vector_extract (v2f64 VR128:$src),
1469 (iPTR 0))), addr:$dst)]>;
1471 // v2f64 extract element 1 is always custom lowered to unpack high to low
1472 // and extract element 0 so the non-store version isn't too horrible.
1473 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1474 "movhpd\t{$src, $dst|$dst, $src}",
1475 [(store (f64 (vector_extract
1476 (v2f64 (unpckh VR128:$src, (undef))),
1477 (iPTR 0))), addr:$dst)]>;
1479 // SSE2 instructions without OpSize prefix
1480 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1481 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1482 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1483 TB, Requires<[HasSSE2]>;
1484 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1485 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1486 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1487 (bitconvert (memopv2i64 addr:$src))))]>,
1488 TB, Requires<[HasSSE2]>;
1490 // SSE2 instructions with XS prefix
1491 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1492 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1493 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1494 XS, Requires<[HasSSE2]>;
1495 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1496 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1497 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1498 (bitconvert (memopv2i64 addr:$src))))]>,
1499 XS, Requires<[HasSSE2]>;
1501 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1502 "cvtps2dq\t{$src, $dst|$dst, $src}",
1503 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1504 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1505 "cvtps2dq\t{$src, $dst|$dst, $src}",
1506 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1507 (memop addr:$src)))]>;
1508 // SSE2 packed instructions with XS prefix
1509 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1510 "cvttps2dq\t{$src, $dst|$dst, $src}",
1511 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
1512 XS, Requires<[HasSSE2]>;
1513 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1514 "cvttps2dq\t{$src, $dst|$dst, $src}",
1515 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1516 (memop addr:$src)))]>,
1517 XS, Requires<[HasSSE2]>;
1519 // SSE2 packed instructions with XD prefix
1520 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1521 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1522 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1523 XD, Requires<[HasSSE2]>;
1524 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1525 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1526 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1527 (memop addr:$src)))]>,
1528 XD, Requires<[HasSSE2]>;
1530 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1531 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1532 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1533 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1534 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1535 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1536 (memop addr:$src)))]>;
1538 // SSE2 instructions without OpSize prefix
1539 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1540 "cvtps2pd\t{$src, $dst|$dst, $src}",
1541 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1542 TB, Requires<[HasSSE2]>;
1543 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1544 "cvtps2pd\t{$src, $dst|$dst, $src}",
1545 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1546 (load addr:$src)))]>,
1547 TB, Requires<[HasSSE2]>;
1549 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1550 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1551 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1552 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1553 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1554 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1555 (memop addr:$src)))]>;
1557 // Match intrinsics which expect XMM operand(s).
1558 // Aliases for intrinsics
1559 let Constraints = "$src1 = $dst" in {
1560 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1561 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1562 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1563 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1565 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1566 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1567 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1568 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1569 (loadi32 addr:$src2)))]>;
1570 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1571 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1572 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1573 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1575 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1576 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1577 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1578 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1579 (load addr:$src2)))]>;
1580 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1581 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1582 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1583 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1584 VR128:$src2))]>, XS,
1585 Requires<[HasSSE2]>;
1586 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1587 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1588 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1589 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1590 (load addr:$src2)))]>, XS,
1591 Requires<[HasSSE2]>;
1596 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1598 /// In addition, we also have a special variant of the scalar form here to
1599 /// represent the associated intrinsic operation. This form is unlike the
1600 /// plain scalar form, in that it takes an entire vector (instead of a
1601 /// scalar) and leaves the top elements undefined.
1603 /// And, we have a special variant form for a full-vector intrinsic form.
1605 /// These four forms can each have a reg or a mem operand, so there are a
1606 /// total of eight "instructions".
1608 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1612 bit Commutable = 0> {
1613 // Scalar operation, reg.
1614 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1615 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1616 [(set FR64:$dst, (OpNode FR64:$src))]> {
1617 let isCommutable = Commutable;
1620 // Scalar operation, mem.
1621 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1622 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1623 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1625 // Vector operation, reg.
1626 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1627 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1628 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1629 let isCommutable = Commutable;
1632 // Vector operation, mem.
1633 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1634 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1635 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1637 // Intrinsic operation, reg.
1638 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1639 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1640 [(set VR128:$dst, (F64Int VR128:$src))]> {
1641 let isCommutable = Commutable;
1644 // Intrinsic operation, mem.
1645 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1646 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1647 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1649 // Vector intrinsic operation, reg
1650 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1651 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1652 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1653 let isCommutable = Commutable;
1656 // Vector intrinsic operation, mem
1657 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1658 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1659 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1663 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1664 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1666 // There is no f64 version of the reciprocal approximation instructions.
1669 let Constraints = "$src1 = $dst" in {
1670 let isCommutable = 1 in {
1671 def ANDPDrr : PDI<0x54, MRMSrcReg,
1672 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1673 "andpd\t{$src2, $dst|$dst, $src2}",
1675 (and (bc_v2i64 (v2f64 VR128:$src1)),
1676 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1677 def ORPDrr : PDI<0x56, MRMSrcReg,
1678 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1679 "orpd\t{$src2, $dst|$dst, $src2}",
1681 (or (bc_v2i64 (v2f64 VR128:$src1)),
1682 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1683 def XORPDrr : PDI<0x57, MRMSrcReg,
1684 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1685 "xorpd\t{$src2, $dst|$dst, $src2}",
1687 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1688 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1691 def ANDPDrm : PDI<0x54, MRMSrcMem,
1692 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1693 "andpd\t{$src2, $dst|$dst, $src2}",
1695 (and (bc_v2i64 (v2f64 VR128:$src1)),
1696 (memopv2i64 addr:$src2)))]>;
1697 def ORPDrm : PDI<0x56, MRMSrcMem,
1698 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1699 "orpd\t{$src2, $dst|$dst, $src2}",
1701 (or (bc_v2i64 (v2f64 VR128:$src1)),
1702 (memopv2i64 addr:$src2)))]>;
1703 def XORPDrm : PDI<0x57, MRMSrcMem,
1704 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1705 "xorpd\t{$src2, $dst|$dst, $src2}",
1707 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1708 (memopv2i64 addr:$src2)))]>;
1709 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1710 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1711 "andnpd\t{$src2, $dst|$dst, $src2}",
1713 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1714 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1715 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1716 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1717 "andnpd\t{$src2, $dst|$dst, $src2}",
1719 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1720 (memopv2i64 addr:$src2)))]>;
1723 let Constraints = "$src1 = $dst" in {
1724 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1725 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1726 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1727 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1728 VR128:$src, imm:$cc))]>;
1729 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1730 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1731 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1732 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1733 (memop addr:$src), imm:$cc))]>;
1735 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1736 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1737 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1738 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1740 // Shuffle and unpack instructions
1741 let Constraints = "$src1 = $dst" in {
1742 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1743 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1744 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1746 (v2f64 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1747 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1748 (outs VR128:$dst), (ins VR128:$src1,
1749 f128mem:$src2, i8imm:$src3),
1750 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1753 VR128:$src1, (memopv2f64 addr:$src2))))]>;
1755 let AddedComplexity = 10 in {
1756 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1757 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1758 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1760 (v2f64 (unpckh VR128:$src1, VR128:$src2)))]>;
1761 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1762 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1763 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1765 (v2f64 (unpckh VR128:$src1,
1766 (memopv2f64 addr:$src2))))]>;
1768 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1769 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1770 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1772 (v2f64 (unpckl VR128:$src1, VR128:$src2)))]>;
1773 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1774 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1775 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1777 (unpckl VR128:$src1, (memopv2f64 addr:$src2)))]>;
1778 } // AddedComplexity
1779 } // Constraints = "$src1 = $dst"
1782 //===---------------------------------------------------------------------===//
1783 // SSE integer instructions
1785 // Move Instructions
1786 let neverHasSideEffects = 1 in
1787 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1788 "movdqa\t{$src, $dst|$dst, $src}", []>;
1789 let canFoldAsLoad = 1, mayLoad = 1 in
1790 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1791 "movdqa\t{$src, $dst|$dst, $src}",
1792 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1794 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1795 "movdqa\t{$src, $dst|$dst, $src}",
1796 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1797 let canFoldAsLoad = 1, mayLoad = 1 in
1798 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1799 "movdqu\t{$src, $dst|$dst, $src}",
1800 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1801 XS, Requires<[HasSSE2]>;
1803 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1804 "movdqu\t{$src, $dst|$dst, $src}",
1805 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1806 XS, Requires<[HasSSE2]>;
1808 // Intrinsic forms of MOVDQU load and store
1809 let canFoldAsLoad = 1 in
1810 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1811 "movdqu\t{$src, $dst|$dst, $src}",
1812 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1813 XS, Requires<[HasSSE2]>;
1814 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1815 "movdqu\t{$src, $dst|$dst, $src}",
1816 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1817 XS, Requires<[HasSSE2]>;
1819 let Constraints = "$src1 = $dst" in {
1821 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1822 bit Commutable = 0> {
1823 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1824 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1825 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1826 let isCommutable = Commutable;
1828 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1829 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1830 [(set VR128:$dst, (IntId VR128:$src1,
1831 (bitconvert (memopv2i64 addr:$src2))))]>;
1834 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1836 Intrinsic IntId, Intrinsic IntId2> {
1837 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1,
1839 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1840 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1841 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1,
1843 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1844 [(set VR128:$dst, (IntId VR128:$src1,
1845 (bitconvert (memopv2i64 addr:$src2))))]>;
1846 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst), (ins VR128:$src1,
1848 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1849 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
1852 /// PDI_binop_rm - Simple SSE2 binary operator.
1853 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1854 ValueType OpVT, bit Commutable = 0> {
1855 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1,
1857 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1858 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1859 let isCommutable = Commutable;
1861 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1,
1863 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1864 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1865 (bitconvert (memopv2i64 addr:$src2)))))]>;
1868 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1870 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1871 /// to collapse (bitconvert VT to VT) into its operand.
1873 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1874 bit Commutable = 0> {
1875 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1876 (ins VR128:$src1, VR128:$src2),
1877 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1878 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1879 let isCommutable = Commutable;
1881 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1882 (ins VR128:$src1, i128mem:$src2),
1883 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1884 [(set VR128:$dst, (OpNode VR128:$src1,
1885 (memopv2i64 addr:$src2)))]>;
1888 } // Constraints = "$src1 = $dst"
1890 // 128-bit Integer Arithmetic
1892 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1893 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1894 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1895 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1897 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1898 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1899 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1900 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1902 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1903 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1904 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1905 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1907 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1908 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1909 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1910 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1912 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1914 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1915 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1916 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1918 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1920 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1921 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1924 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1925 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1926 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1927 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1928 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
1931 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
1932 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
1933 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
1934 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
1935 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
1936 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
1938 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
1939 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
1940 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
1941 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
1942 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
1943 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
1945 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
1946 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
1947 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
1948 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
1950 // 128-bit logical shifts.
1951 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1952 def PSLLDQri : PDIi8<0x73, MRM7r,
1953 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1954 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
1955 def PSRLDQri : PDIi8<0x73, MRM3r,
1956 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1957 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
1958 // PSRADQri doesn't exist in SSE[1-3].
1961 let Predicates = [HasSSE2] in {
1962 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1963 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1964 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1965 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1966 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
1967 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
1968 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
1969 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
1970 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
1971 (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1973 // Shift up / down and insert zero's.
1974 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
1975 (v2i64 (PSLLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1976 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
1977 (v2i64 (PSRLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1981 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1982 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1983 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1985 let Constraints = "$src1 = $dst" in {
1986 def PANDNrr : PDI<0xDF, MRMSrcReg,
1987 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1988 "pandn\t{$src2, $dst|$dst, $src2}",
1989 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1992 def PANDNrm : PDI<0xDF, MRMSrcMem,
1993 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1994 "pandn\t{$src2, $dst|$dst, $src2}",
1995 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1996 (memopv2i64 addr:$src2))))]>;
1999 // SSE2 Integer comparison
2000 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
2001 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
2002 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
2003 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2004 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2005 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2007 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2008 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2009 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2010 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2011 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2012 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2013 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2014 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2015 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2016 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2017 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2018 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2020 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2021 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2022 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2023 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2024 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2025 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2026 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2027 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2028 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2029 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2030 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2031 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2034 // Pack instructions
2035 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2036 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2037 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2039 // Shuffle and unpack instructions
2040 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2041 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2042 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2043 [(set VR128:$dst, (v4i32 (pshufd:$src2
2044 VR128:$src1, (undef))))]>;
2045 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2046 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2047 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2048 [(set VR128:$dst, (v4i32 (pshufd:$src2
2049 (bc_v4i32(memopv2i64 addr:$src1)),
2052 // SSE2 with ImmT == Imm8 and XS prefix.
2053 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2054 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2055 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2056 [(set VR128:$dst, (v8i16 (pshufhw:$src2 VR128:$src1,
2058 XS, Requires<[HasSSE2]>;
2059 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2060 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2061 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2062 [(set VR128:$dst, (v8i16 (pshufhw:$src2
2063 (bc_v8i16 (memopv2i64 addr:$src1)),
2065 XS, Requires<[HasSSE2]>;
2067 // SSE2 with ImmT == Imm8 and XD prefix.
2068 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2069 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2070 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2071 [(set VR128:$dst, (v8i16 (pshuflw:$src2 VR128:$src1,
2073 XD, Requires<[HasSSE2]>;
2074 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2075 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2076 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2077 [(set VR128:$dst, (v8i16 (pshuflw:$src2
2078 (bc_v8i16 (memopv2i64 addr:$src1)),
2080 XD, Requires<[HasSSE2]>;
2083 let Constraints = "$src1 = $dst" in {
2084 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
2085 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2086 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2088 (v16i8 (unpckl VR128:$src1, VR128:$src2)))]>;
2089 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
2090 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2091 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2093 (unpckl VR128:$src1,
2094 (bc_v16i8 (memopv2i64 addr:$src2))))]>;
2095 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
2096 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2097 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2099 (v8i16 (unpckl VR128:$src1, VR128:$src2)))]>;
2100 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
2101 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2102 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2104 (unpckl VR128:$src1,
2105 (bc_v8i16 (memopv2i64 addr:$src2))))]>;
2106 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2107 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2108 "punpckldq\t{$src2, $dst|$dst, $src2}",
2110 (v4i32 (unpckl VR128:$src1, VR128:$src2)))]>;
2111 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2112 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2113 "punpckldq\t{$src2, $dst|$dst, $src2}",
2115 (unpckl VR128:$src1,
2116 (bc_v4i32 (memopv2i64 addr:$src2))))]>;
2117 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2118 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2119 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2121 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2122 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2123 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2124 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2126 (v2i64 (unpckl VR128:$src1,
2127 (memopv2i64 addr:$src2))))]>;
2129 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2130 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2131 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2133 (v16i8 (unpckh VR128:$src1, VR128:$src2)))]>;
2134 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2135 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2136 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2138 (unpckh VR128:$src1,
2139 (bc_v16i8 (memopv2i64 addr:$src2))))]>;
2140 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2141 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2142 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2144 (v8i16 (unpckh VR128:$src1, VR128:$src2)))]>;
2145 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2146 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2147 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2149 (unpckh VR128:$src1,
2150 (bc_v8i16 (memopv2i64 addr:$src2))))]>;
2151 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2152 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2153 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2155 (v4i32 (unpckh VR128:$src1, VR128:$src2)))]>;
2156 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2157 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2158 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2160 (unpckh VR128:$src1,
2161 (bc_v4i32 (memopv2i64 addr:$src2))))]>;
2162 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2163 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2164 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2166 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2167 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2168 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2169 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2171 (v2i64 (unpckh VR128:$src1,
2172 (memopv2i64 addr:$src2))))]>;
2176 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2177 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2178 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2179 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2181 let Constraints = "$src1 = $dst" in {
2182 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2183 (outs VR128:$dst), (ins VR128:$src1,
2184 GR32:$src2, i32i8imm:$src3),
2185 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2187 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2188 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2189 (outs VR128:$dst), (ins VR128:$src1,
2190 i16mem:$src2, i32i8imm:$src3),
2191 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2193 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2198 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2199 "pmovmskb\t{$src, $dst|$dst, $src}",
2200 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2202 // Conditional store
2204 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2205 "maskmovdqu\t{$mask, $src|$src, $mask}",
2206 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2209 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2210 "maskmovdqu\t{$mask, $src|$src, $mask}",
2211 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2213 // Non-temporal stores
2214 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2215 "movntpd\t{$src, $dst|$dst, $src}",
2216 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2217 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2218 "movntdq\t{$src, $dst|$dst, $src}",
2219 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2220 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2221 "movnti\t{$src, $dst|$dst, $src}",
2222 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2223 TB, Requires<[HasSSE2]>;
2226 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2227 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2228 TB, Requires<[HasSSE2]>;
2230 // Load, store, and memory fence
2231 def LFENCE : I<0xAE, MRM5r, (outs), (ins),
2232 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2233 def MFENCE : I<0xAE, MRM6r, (outs), (ins),
2234 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2236 //TODO: custom lower this so as to never even generate the noop
2237 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2239 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2240 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2241 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2244 // Alias instructions that map zero vector to pxor / xorp* for sse.
2245 // We set canFoldAsLoad because this can be converted to a constant-pool
2246 // load of an all-ones value if folding it would be beneficial.
2247 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1 in
2248 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
2249 "pcmpeqd\t$dst, $dst",
2250 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2252 // FR64 to 128-bit vector conversion.
2253 let isAsCheapAsAMove = 1 in
2254 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src),
2255 "movsd\t{$src, $dst|$dst, $src}",
2257 (v2f64 (scalar_to_vector FR64:$src)))]>;
2258 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2259 "movsd\t{$src, $dst|$dst, $src}",
2261 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2263 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2264 "movd\t{$src, $dst|$dst, $src}",
2266 (v4i32 (scalar_to_vector GR32:$src)))]>;
2267 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2268 "movd\t{$src, $dst|$dst, $src}",
2270 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2272 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2273 "movd\t{$src, $dst|$dst, $src}",
2274 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2276 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2277 "movd\t{$src, $dst|$dst, $src}",
2278 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2280 // SSE2 instructions with XS prefix
2281 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2282 "movq\t{$src, $dst|$dst, $src}",
2284 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2285 Requires<[HasSSE2]>;
2286 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2287 "movq\t{$src, $dst|$dst, $src}",
2288 [(store (i64 (vector_extract (v2i64 VR128:$src),
2289 (iPTR 0))), addr:$dst)]>;
2291 // FIXME: may not be able to eliminate this movss with coalescing the src and
2292 // dest register classes are different. We really want to write this pattern
2294 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2295 // (f32 FR32:$src)>;
2296 let isAsCheapAsAMove = 1 in
2297 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src),
2298 "movsd\t{$src, $dst|$dst, $src}",
2299 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2301 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
2302 "movsd\t{$src, $dst|$dst, $src}",
2303 [(store (f64 (vector_extract (v2f64 VR128:$src),
2304 (iPTR 0))), addr:$dst)]>;
2305 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2306 "movd\t{$src, $dst|$dst, $src}",
2307 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2309 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2310 "movd\t{$src, $dst|$dst, $src}",
2311 [(store (i32 (vector_extract (v4i32 VR128:$src),
2312 (iPTR 0))), addr:$dst)]>;
2314 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2315 "movd\t{$src, $dst|$dst, $src}",
2316 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2317 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2318 "movd\t{$src, $dst|$dst, $src}",
2319 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2322 // Move to lower bits of a VR128, leaving upper bits alone.
2323 // Three operand (but two address) aliases.
2324 let Constraints = "$src1 = $dst" in {
2325 let neverHasSideEffects = 1 in
2326 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
2327 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
2328 "movsd\t{$src2, $dst|$dst, $src2}", []>;
2330 let AddedComplexity = 15 in
2331 def MOVLPDrr : SDI<0x10, MRMSrcReg,
2332 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2333 "movsd\t{$src2, $dst|$dst, $src2}",
2335 (v2f64 (movl VR128:$src1, VR128:$src2)))]>;
2338 // Store / copy lower 64-bits of a XMM register.
2339 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2340 "movq\t{$src, $dst|$dst, $src}",
2341 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2343 // Move to lower bits of a VR128 and zeroing upper bits.
2344 // Loading from memory automatically zeroing upper bits.
2345 let AddedComplexity = 20 in {
2346 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2347 "movsd\t{$src, $dst|$dst, $src}",
2349 (v2f64 (X86vzmovl (v2f64 (scalar_to_vector
2350 (loadf64 addr:$src))))))]>;
2352 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2353 (MOVZSD2PDrm addr:$src)>;
2354 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2355 (MOVZSD2PDrm addr:$src)>;
2356 def : Pat<(v2f64 (X86vzload addr:$src)), (MOVZSD2PDrm addr:$src)>;
2359 // movd / movq to XMM register zero-extends
2360 let AddedComplexity = 15 in {
2361 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2362 "movd\t{$src, $dst|$dst, $src}",
2363 [(set VR128:$dst, (v4i32 (X86vzmovl
2364 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2365 // This is X86-64 only.
2366 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2367 "mov{d|q}\t{$src, $dst|$dst, $src}",
2368 [(set VR128:$dst, (v2i64 (X86vzmovl
2369 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2372 let AddedComplexity = 20 in {
2373 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2374 "movd\t{$src, $dst|$dst, $src}",
2376 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2377 (loadi32 addr:$src))))))]>;
2379 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2380 (MOVZDI2PDIrm addr:$src)>;
2381 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2382 (MOVZDI2PDIrm addr:$src)>;
2383 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2384 (MOVZDI2PDIrm addr:$src)>;
2386 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2387 "movq\t{$src, $dst|$dst, $src}",
2389 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2390 (loadi64 addr:$src))))))]>, XS,
2391 Requires<[HasSSE2]>;
2393 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2394 (MOVZQI2PQIrm addr:$src)>;
2395 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2396 (MOVZQI2PQIrm addr:$src)>;
2397 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2400 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2401 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2402 let AddedComplexity = 15 in
2403 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2404 "movq\t{$src, $dst|$dst, $src}",
2405 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2406 XS, Requires<[HasSSE2]>;
2408 let AddedComplexity = 20 in {
2409 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2410 "movq\t{$src, $dst|$dst, $src}",
2411 [(set VR128:$dst, (v2i64 (X86vzmovl
2412 (loadv2i64 addr:$src))))]>,
2413 XS, Requires<[HasSSE2]>;
2415 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2416 (MOVZPQILo2PQIrm addr:$src)>;
2419 //===---------------------------------------------------------------------===//
2420 // SSE3 Instructions
2421 //===---------------------------------------------------------------------===//
2423 // Move Instructions
2424 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2425 "movshdup\t{$src, $dst|$dst, $src}",
2426 [(set VR128:$dst, (v4f32 (movshdup
2427 VR128:$src, (undef))))]>;
2428 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2429 "movshdup\t{$src, $dst|$dst, $src}",
2430 [(set VR128:$dst, (movshdup
2431 (memopv4f32 addr:$src), (undef)))]>;
2433 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2434 "movsldup\t{$src, $dst|$dst, $src}",
2435 [(set VR128:$dst, (v4f32 (movsldup
2436 VR128:$src, (undef))))]>;
2437 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2438 "movsldup\t{$src, $dst|$dst, $src}",
2439 [(set VR128:$dst, (movsldup
2440 (memopv4f32 addr:$src), (undef)))]>;
2442 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2443 "movddup\t{$src, $dst|$dst, $src}",
2444 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
2445 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2446 "movddup\t{$src, $dst|$dst, $src}",
2448 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
2451 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
2453 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2455 let AddedComplexity = 5 in {
2456 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
2457 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2458 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
2459 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2460 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
2461 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2462 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
2463 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2467 let Constraints = "$src1 = $dst" in {
2468 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2469 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2470 "addsubps\t{$src2, $dst|$dst, $src2}",
2471 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2473 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2474 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2475 "addsubps\t{$src2, $dst|$dst, $src2}",
2476 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2477 (memop addr:$src2)))]>;
2478 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2479 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2480 "addsubpd\t{$src2, $dst|$dst, $src2}",
2481 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2483 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2484 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2485 "addsubpd\t{$src2, $dst|$dst, $src2}",
2486 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2487 (memop addr:$src2)))]>;
2490 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2491 "lddqu\t{$src, $dst|$dst, $src}",
2492 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2495 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2496 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2497 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2498 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2499 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2500 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2501 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2502 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2503 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2504 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2505 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2506 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2507 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2508 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2509 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2510 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2512 let Constraints = "$src1 = $dst" in {
2513 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2514 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2515 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2516 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2517 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2518 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2519 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2520 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2523 // Thread synchronization
2524 def MONITOR : I<0x01, MRM1r, (outs), (ins), "monitor",
2525 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2526 def MWAIT : I<0x01, MRM1r, (outs), (ins), "mwait",
2527 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2529 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2530 let AddedComplexity = 15 in
2531 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
2532 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2533 let AddedComplexity = 20 in
2534 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2535 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2537 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2538 let AddedComplexity = 15 in
2539 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
2540 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2541 let AddedComplexity = 20 in
2542 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2543 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2545 //===---------------------------------------------------------------------===//
2546 // SSSE3 Instructions
2547 //===---------------------------------------------------------------------===//
2549 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2550 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2551 Intrinsic IntId64, Intrinsic IntId128> {
2552 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2553 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2554 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2556 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2557 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2559 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2561 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2563 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2564 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2567 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2569 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2572 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2575 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2576 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2577 Intrinsic IntId64, Intrinsic IntId128> {
2578 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2580 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2581 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2583 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2585 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2588 (bitconvert (memopv4i16 addr:$src))))]>;
2590 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2592 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2593 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2596 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2598 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2601 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2604 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2605 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2606 Intrinsic IntId64, Intrinsic IntId128> {
2607 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2609 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2610 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2612 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2614 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2617 (bitconvert (memopv2i32 addr:$src))))]>;
2619 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2621 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2622 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2625 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2627 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2630 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2633 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2634 int_x86_ssse3_pabs_b,
2635 int_x86_ssse3_pabs_b_128>;
2636 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2637 int_x86_ssse3_pabs_w,
2638 int_x86_ssse3_pabs_w_128>;
2639 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2640 int_x86_ssse3_pabs_d,
2641 int_x86_ssse3_pabs_d_128>;
2643 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2644 let Constraints = "$src1 = $dst" in {
2645 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2646 Intrinsic IntId64, Intrinsic IntId128,
2647 bit Commutable = 0> {
2648 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2649 (ins VR64:$src1, VR64:$src2),
2650 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2651 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2652 let isCommutable = Commutable;
2654 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2655 (ins VR64:$src1, i64mem:$src2),
2656 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2658 (IntId64 VR64:$src1,
2659 (bitconvert (memopv8i8 addr:$src2))))]>;
2661 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2662 (ins VR128:$src1, VR128:$src2),
2663 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2664 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2666 let isCommutable = Commutable;
2668 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2669 (ins VR128:$src1, i128mem:$src2),
2670 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2672 (IntId128 VR128:$src1,
2673 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2677 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2678 let Constraints = "$src1 = $dst" in {
2679 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2680 Intrinsic IntId64, Intrinsic IntId128,
2681 bit Commutable = 0> {
2682 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2683 (ins VR64:$src1, VR64:$src2),
2684 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2685 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2686 let isCommutable = Commutable;
2688 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2689 (ins VR64:$src1, i64mem:$src2),
2690 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2692 (IntId64 VR64:$src1,
2693 (bitconvert (memopv4i16 addr:$src2))))]>;
2695 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2696 (ins VR128:$src1, VR128:$src2),
2697 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2698 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2700 let isCommutable = Commutable;
2702 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2703 (ins VR128:$src1, i128mem:$src2),
2704 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2706 (IntId128 VR128:$src1,
2707 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2711 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2712 let Constraints = "$src1 = $dst" in {
2713 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2714 Intrinsic IntId64, Intrinsic IntId128,
2715 bit Commutable = 0> {
2716 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2717 (ins VR64:$src1, VR64:$src2),
2718 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2719 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2720 let isCommutable = Commutable;
2722 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2723 (ins VR64:$src1, i64mem:$src2),
2724 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2726 (IntId64 VR64:$src1,
2727 (bitconvert (memopv2i32 addr:$src2))))]>;
2729 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2730 (ins VR128:$src1, VR128:$src2),
2731 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2732 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2734 let isCommutable = Commutable;
2736 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2737 (ins VR128:$src1, i128mem:$src2),
2738 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2740 (IntId128 VR128:$src1,
2741 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2745 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2746 int_x86_ssse3_phadd_w,
2747 int_x86_ssse3_phadd_w_128>;
2748 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2749 int_x86_ssse3_phadd_d,
2750 int_x86_ssse3_phadd_d_128>;
2751 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2752 int_x86_ssse3_phadd_sw,
2753 int_x86_ssse3_phadd_sw_128>;
2754 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2755 int_x86_ssse3_phsub_w,
2756 int_x86_ssse3_phsub_w_128>;
2757 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2758 int_x86_ssse3_phsub_d,
2759 int_x86_ssse3_phsub_d_128>;
2760 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2761 int_x86_ssse3_phsub_sw,
2762 int_x86_ssse3_phsub_sw_128>;
2763 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2764 int_x86_ssse3_pmadd_ub_sw,
2765 int_x86_ssse3_pmadd_ub_sw_128>;
2766 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2767 int_x86_ssse3_pmul_hr_sw,
2768 int_x86_ssse3_pmul_hr_sw_128, 1>;
2769 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2770 int_x86_ssse3_pshuf_b,
2771 int_x86_ssse3_pshuf_b_128>;
2772 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2773 int_x86_ssse3_psign_b,
2774 int_x86_ssse3_psign_b_128>;
2775 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2776 int_x86_ssse3_psign_w,
2777 int_x86_ssse3_psign_w_128>;
2778 defm PSIGND : SS3I_binop_rm_int_32<0x0A, "psignd",
2779 int_x86_ssse3_psign_d,
2780 int_x86_ssse3_psign_d_128>;
2782 let Constraints = "$src1 = $dst" in {
2783 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2784 (ins VR64:$src1, VR64:$src2, i16imm:$src3),
2785 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2787 (int_x86_ssse3_palign_r
2788 VR64:$src1, VR64:$src2,
2790 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2791 (ins VR64:$src1, i64mem:$src2, i16imm:$src3),
2792 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2794 (int_x86_ssse3_palign_r
2796 (bitconvert (memopv2i32 addr:$src2)),
2799 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2800 (ins VR128:$src1, VR128:$src2, i32imm:$src3),
2801 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2803 (int_x86_ssse3_palign_r_128
2804 VR128:$src1, VR128:$src2,
2805 imm:$src3))]>, OpSize;
2806 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2807 (ins VR128:$src1, i128mem:$src2, i32imm:$src3),
2808 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2810 (int_x86_ssse3_palign_r_128
2812 (bitconvert (memopv4i32 addr:$src2)),
2813 imm:$src3))]>, OpSize;
2816 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
2817 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
2818 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
2819 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
2821 //===---------------------------------------------------------------------===//
2822 // Non-Instruction Patterns
2823 //===---------------------------------------------------------------------===//
2825 // extload f32 -> f64. This matches load+fextend because we have a hack in
2826 // the isel (PreprocessForFPConvert) that can introduce loads after dag
2828 // Since these loads aren't folded into the fextend, we have to match it
2830 let Predicates = [HasSSE2] in
2831 def : Pat<(fextend (loadf32 addr:$src)),
2832 (CVTSS2SDrm addr:$src)>;
2835 let Predicates = [HasSSE2] in {
2836 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2837 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2838 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2839 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2840 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2841 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2842 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2843 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2844 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2845 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2846 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2847 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2848 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2849 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2850 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2851 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2852 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2853 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2854 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2855 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2856 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2857 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2858 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2859 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2860 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2861 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2862 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2863 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2864 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2865 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2868 // Move scalar to XMM zero-extended
2869 // movd to XMM register zero-extends
2870 let AddedComplexity = 15 in {
2871 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2872 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
2873 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2874 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
2875 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE1]>;
2876 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
2877 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>;
2878 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
2879 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>;
2882 // Splat v2f64 / v2i64
2883 let AddedComplexity = 10 in {
2884 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2885 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2886 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
2887 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2888 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
2889 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2890 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
2891 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2894 // Special unary SHUFPSrri case.
2895 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2896 (SHUFPSrri VR128:$src1, VR128:$src1,
2897 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2898 Requires<[HasSSE1]>;
2899 let AddedComplexity = 5 in
2900 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
2901 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2902 Requires<[HasSSE2]>;
2903 // Special unary SHUFPDrri case.
2904 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2905 (SHUFPDrri VR128:$src1, VR128:$src1,
2906 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2907 Requires<[HasSSE2]>;
2908 // Special unary SHUFPDrri case.
2909 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2910 (SHUFPDrri VR128:$src1, VR128:$src1,
2911 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2912 Requires<[HasSSE2]>;
2913 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2914 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
2915 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2916 Requires<[HasSSE2]>;
2918 // Special binary v4i32 shuffle cases with SHUFPS.
2919 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2920 (SHUFPSrri VR128:$src1, VR128:$src2,
2921 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2922 Requires<[HasSSE2]>;
2923 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
2924 (SHUFPSrmi VR128:$src1, addr:$src2,
2925 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2926 Requires<[HasSSE2]>;
2927 // Special binary v2i64 shuffle cases using SHUFPDrri.
2928 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2929 (SHUFPDrri VR128:$src1, VR128:$src2,
2930 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2931 Requires<[HasSSE2]>;
2933 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2934 let AddedComplexity = 15 in {
2935 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
2936 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2937 Requires<[OptForSpeed, HasSSE2]>;
2938 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
2939 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2940 Requires<[OptForSpeed, HasSSE2]>;
2942 let AddedComplexity = 10 in {
2943 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
2944 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2945 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
2946 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2947 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
2948 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2949 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
2950 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2953 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2954 let AddedComplexity = 15 in {
2955 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
2956 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2957 Requires<[OptForSpeed, HasSSE2]>;
2958 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
2959 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2960 Requires<[OptForSpeed, HasSSE2]>;
2962 let AddedComplexity = 10 in {
2963 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
2964 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2965 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
2966 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2967 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
2968 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2969 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
2970 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2973 let AddedComplexity = 20 in {
2974 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2975 def : Pat<(v4i32 (movhp VR128:$src1, VR128:$src2)),
2976 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2978 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2979 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
2980 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
2982 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
2983 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
2984 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2985 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
2986 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2989 let AddedComplexity = 20 in {
2990 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2991 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
2992 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
2993 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2994 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
2995 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2996 def : Pat<(v4f32 (movhp VR128:$src1, (load addr:$src2))),
2997 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2998 def : Pat<(v2f64 (movhp VR128:$src1, (load addr:$src2))),
2999 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3001 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3002 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3003 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3004 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3005 def : Pat<(v4i32 (movhp VR128:$src1, (load addr:$src2))),
3006 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
3007 def : Pat<(v2i64 (movhp VR128:$src1, (load addr:$src2))),
3008 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3011 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3012 // (store (vector_shuffle (load addr), v2, <0, 1, 4, 5>), addr) using MOVHPS
3013 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3014 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3015 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3016 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3017 def : Pat<(store (v4f32 (movhp (load addr:$src1), VR128:$src2)), addr:$src1),
3018 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3019 def : Pat<(store (v2f64 (movhp (load addr:$src1), VR128:$src2)), addr:$src1),
3020 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3022 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3024 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3025 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3026 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3027 def : Pat<(store (v4i32 (movhp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3029 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3030 def : Pat<(store (v2i64 (movhp (load addr:$src1), VR128:$src2)), addr:$src1),
3031 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3034 let AddedComplexity = 15 in {
3035 // Setting the lowest element in the vector.
3036 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3037 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3038 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3039 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3041 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
3042 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3043 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3044 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3045 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3048 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3049 // fall back to this for SSE1)
3050 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3051 (SHUFPSrri VR128:$src2, VR128:$src1,
3052 (SHUFFLE_get_shuf_imm VR128:$src3))>, Requires<[HasSSE1]>;
3054 // Set lowest element and zero upper elements.
3055 let AddedComplexity = 15 in
3056 def : Pat<(v2f64 (movl immAllZerosV_bc, VR128:$src)),
3057 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3058 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3059 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3061 // Some special case pandn patterns.
3062 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3064 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3065 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3067 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3068 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3070 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3072 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3073 (memop addr:$src2))),
3074 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3075 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3076 (memop addr:$src2))),
3077 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3078 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3079 (memop addr:$src2))),
3080 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3082 // vector -> vector casts
3083 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3084 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3085 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3086 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3087 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3088 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3089 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3090 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3092 // Use movaps / movups for SSE integer load / store (one byte shorter).
3093 def : Pat<(alignedloadv4i32 addr:$src),
3094 (MOVAPSrm addr:$src)>, Requires<[HasSSE1]>;
3095 def : Pat<(loadv4i32 addr:$src),
3096 (MOVUPSrm addr:$src)>, Requires<[HasSSE1]>;
3097 def : Pat<(alignedloadv2i64 addr:$src),
3098 (MOVAPSrm addr:$src)>, Requires<[HasSSE2]>;
3099 def : Pat<(loadv2i64 addr:$src),
3100 (MOVUPSrm addr:$src)>, Requires<[HasSSE2]>;
3102 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3103 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3104 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3105 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3106 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3107 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3108 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3109 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3110 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3111 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3112 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3113 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3114 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3115 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3116 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3117 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3119 //===----------------------------------------------------------------------===//
3120 // SSE4.1 Instructions
3121 //===----------------------------------------------------------------------===//
3123 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3126 Intrinsic V2F64Int> {
3127 // Intrinsic operation, reg.
3128 // Vector intrinsic operation, reg
3129 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3130 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3131 !strconcat(OpcodeStr,
3132 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3133 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3136 // Vector intrinsic operation, mem
3137 def PSm_Int : SS4AIi8<opcps, MRMSrcMem,
3138 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3139 !strconcat(OpcodeStr,
3140 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3142 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3145 // Vector intrinsic operation, reg
3146 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3147 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3148 !strconcat(OpcodeStr,
3149 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3150 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3153 // Vector intrinsic operation, mem
3154 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3155 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3156 !strconcat(OpcodeStr,
3157 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3159 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3163 let Constraints = "$src1 = $dst" in {
3164 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3168 // Intrinsic operation, reg.
3169 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3171 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3172 !strconcat(OpcodeStr,
3173 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3175 (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3178 // Intrinsic operation, mem.
3179 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3181 (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3182 !strconcat(OpcodeStr,
3183 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3185 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
3188 // Intrinsic operation, reg.
3189 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3191 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3192 !strconcat(OpcodeStr,
3193 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3195 (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3198 // Intrinsic operation, mem.
3199 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3201 (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
3202 !strconcat(OpcodeStr,
3203 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3205 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
3210 // FP round - roundss, roundps, roundsd, roundpd
3211 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
3212 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
3213 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
3214 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
3216 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3217 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3218 Intrinsic IntId128> {
3219 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3221 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3222 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3223 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3225 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3228 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3231 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3232 int_x86_sse41_phminposuw>;
3234 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3235 let Constraints = "$src1 = $dst" in {
3236 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3237 Intrinsic IntId128, bit Commutable = 0> {
3238 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3239 (ins VR128:$src1, VR128:$src2),
3240 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3241 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3243 let isCommutable = Commutable;
3245 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3246 (ins VR128:$src1, i128mem:$src2),
3247 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3249 (IntId128 VR128:$src1,
3250 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3254 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3255 int_x86_sse41_pcmpeqq, 1>;
3256 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3257 int_x86_sse41_packusdw, 0>;
3258 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3259 int_x86_sse41_pminsb, 1>;
3260 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3261 int_x86_sse41_pminsd, 1>;
3262 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3263 int_x86_sse41_pminud, 1>;
3264 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3265 int_x86_sse41_pminuw, 1>;
3266 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3267 int_x86_sse41_pmaxsb, 1>;
3268 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3269 int_x86_sse41_pmaxsd, 1>;
3270 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3271 int_x86_sse41_pmaxud, 1>;
3272 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3273 int_x86_sse41_pmaxuw, 1>;
3275 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
3277 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3278 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3279 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3280 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3282 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3283 let Constraints = "$src1 = $dst" in {
3284 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3285 SDNode OpNode, Intrinsic IntId128,
3286 bit Commutable = 0> {
3287 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3288 (ins VR128:$src1, VR128:$src2),
3289 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3290 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3291 VR128:$src2))]>, OpSize {
3292 let isCommutable = Commutable;
3294 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3295 (ins VR128:$src1, VR128:$src2),
3296 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3297 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3299 let isCommutable = Commutable;
3301 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3302 (ins VR128:$src1, i128mem:$src2),
3303 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3305 (OpNode VR128:$src1, (memop addr:$src2)))]>, OpSize;
3306 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3307 (ins VR128:$src1, i128mem:$src2),
3308 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3310 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3314 defm PMULLD : SS41I_binop_patint<0x40, "pmulld", v4i32, mul,
3315 int_x86_sse41_pmulld, 1>;
3317 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3318 let Constraints = "$src1 = $dst" in {
3319 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3320 Intrinsic IntId128, bit Commutable = 0> {
3321 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3322 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3323 !strconcat(OpcodeStr,
3324 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3326 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3328 let isCommutable = Commutable;
3330 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3331 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3332 !strconcat(OpcodeStr,
3333 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3335 (IntId128 VR128:$src1,
3336 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3341 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3342 int_x86_sse41_blendps, 0>;
3343 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3344 int_x86_sse41_blendpd, 0>;
3345 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3346 int_x86_sse41_pblendw, 0>;
3347 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3348 int_x86_sse41_dpps, 1>;
3349 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3350 int_x86_sse41_dppd, 1>;
3351 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3352 int_x86_sse41_mpsadbw, 1>;
3355 /// SS41I_ternary_int - SSE 4.1 ternary operator
3356 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3357 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3358 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3359 (ins VR128:$src1, VR128:$src2),
3360 !strconcat(OpcodeStr,
3361 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3362 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3365 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3366 (ins VR128:$src1, i128mem:$src2),
3367 !strconcat(OpcodeStr,
3368 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3371 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3375 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3376 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3377 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3380 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3381 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3382 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3383 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3385 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3386 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3388 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3392 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3393 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3394 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3395 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3396 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3397 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3399 // Common patterns involving scalar load.
3400 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3401 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3402 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3403 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3405 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3406 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3407 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3408 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3410 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3411 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3412 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3413 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3415 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3416 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3417 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3418 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3420 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3421 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3422 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3423 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3425 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3426 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3427 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3428 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3431 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3432 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3433 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3434 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3436 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3437 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3439 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3443 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3444 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3445 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3446 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3448 // Common patterns involving scalar load
3449 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3450 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3451 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3452 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3454 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3455 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3456 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3457 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3460 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3461 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3462 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3463 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3465 // Expecting a i16 load any extended to i32 value.
3466 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3467 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3468 [(set VR128:$dst, (IntId (bitconvert
3469 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3473 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3474 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
3476 // Common patterns involving scalar load
3477 def : Pat<(int_x86_sse41_pmovsxbq
3478 (bitconvert (v4i32 (X86vzmovl
3479 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3480 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3482 def : Pat<(int_x86_sse41_pmovzxbq
3483 (bitconvert (v4i32 (X86vzmovl
3484 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3485 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3488 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3489 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3490 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3491 (ins VR128:$src1, i32i8imm:$src2),
3492 !strconcat(OpcodeStr,
3493 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3494 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3496 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3497 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3498 !strconcat(OpcodeStr,
3499 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3502 // There's an AssertZext in the way of writing the store pattern
3503 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3506 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3509 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3510 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3511 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3512 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3513 !strconcat(OpcodeStr,
3514 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3517 // There's an AssertZext in the way of writing the store pattern
3518 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3521 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3524 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3525 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3526 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3527 (ins VR128:$src1, i32i8imm:$src2),
3528 !strconcat(OpcodeStr,
3529 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3531 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3532 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3533 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3534 !strconcat(OpcodeStr,
3535 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3536 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3537 addr:$dst)]>, OpSize;
3540 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3543 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3545 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3546 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3547 (ins VR128:$src1, i32i8imm:$src2),
3548 !strconcat(OpcodeStr,
3549 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3551 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3553 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3554 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3555 !strconcat(OpcodeStr,
3556 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3557 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3558 addr:$dst)]>, OpSize;
3561 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3563 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3564 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3567 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3568 Requires<[HasSSE41]>;
3570 let Constraints = "$src1 = $dst" in {
3571 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3572 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3573 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3574 !strconcat(OpcodeStr,
3575 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3577 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3578 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3579 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3580 !strconcat(OpcodeStr,
3581 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3583 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3584 imm:$src3))]>, OpSize;
3588 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3590 let Constraints = "$src1 = $dst" in {
3591 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3592 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3593 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3594 !strconcat(OpcodeStr,
3595 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3597 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3599 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3600 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3601 !strconcat(OpcodeStr,
3602 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3604 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3605 imm:$src3)))]>, OpSize;
3609 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3611 // insertps has a few different modes, there's the first two here below which
3612 // are optimized inserts that won't zero arbitrary elements in the destination
3613 // vector. The next one matches the intrinsic and could zero arbitrary elements
3614 // in the target vector.
3615 let Constraints = "$src1 = $dst" in {
3616 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3617 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3618 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3619 !strconcat(OpcodeStr,
3620 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3622 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
3624 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3625 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3626 !strconcat(OpcodeStr,
3627 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3629 (X86insrtps VR128:$src1,
3630 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
3631 imm:$src3))]>, OpSize;
3635 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3637 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
3638 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
3640 // ptest instruction we'll lower to this in X86ISelLowering primarily from
3641 // the intel intrinsic that corresponds to this.
3642 let Defs = [EFLAGS] in {
3643 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3644 "ptest \t{$src2, $src1|$src1, $src2}",
3645 [(X86ptest VR128:$src1, VR128:$src2),
3646 (implicit EFLAGS)]>, OpSize;
3647 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3648 "ptest \t{$src2, $src1|$src1, $src2}",
3649 [(X86ptest VR128:$src1, (load addr:$src2)),
3650 (implicit EFLAGS)]>, OpSize;
3653 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3654 "movntdqa\t{$src, $dst|$dst, $src}",
3655 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
3657 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3658 let Constraints = "$src1 = $dst" in {
3659 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3660 Intrinsic IntId128, bit Commutable = 0> {
3661 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3662 (ins VR128:$src1, VR128:$src2),
3663 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3664 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3666 let isCommutable = Commutable;
3668 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3669 (ins VR128:$src1, i128mem:$src2),
3670 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3672 (IntId128 VR128:$src1,
3673 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3677 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3679 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3680 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3681 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3682 (PCMPGTQrm VR128:$src1, addr:$src2)>;
3684 // crc intrinsic instruction
3685 // This set of instructions are only rm, the only difference is the size
3687 let Constraints = "$src1 = $dst" in {
3688 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
3689 (ins GR32:$src1, i8mem:$src2),
3690 "crc32 \t{$src2, $src1|$src1, $src2}",
3692 (int_x86_sse42_crc32_8 GR32:$src1,
3693 (load addr:$src2)))]>, OpSize;
3694 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
3695 (ins GR32:$src1, GR8:$src2),
3696 "crc32 \t{$src2, $src1|$src1, $src2}",
3698 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>,
3700 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3701 (ins GR32:$src1, i16mem:$src2),
3702 "crc32 \t{$src2, $src1|$src1, $src2}",
3704 (int_x86_sse42_crc32_16 GR32:$src1,
3705 (load addr:$src2)))]>,
3707 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3708 (ins GR32:$src1, GR16:$src2),
3709 "crc32 \t{$src2, $src1|$src1, $src2}",
3711 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
3713 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3714 (ins GR32:$src1, i32mem:$src2),
3715 "crc32 \t{$src2, $src1|$src1, $src2}",
3717 (int_x86_sse42_crc32_32 GR32:$src1,
3718 (load addr:$src2)))]>, OpSize;
3719 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3720 (ins GR32:$src1, GR32:$src2),
3721 "crc32 \t{$src2, $src1|$src1, $src2}",
3723 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>,
3725 def CRC64m64 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
3726 (ins GR64:$src1, i64mem:$src2),
3727 "crc32 \t{$src2, $src1|$src1, $src2}",
3729 (int_x86_sse42_crc32_64 GR64:$src1,
3730 (load addr:$src2)))]>,
3732 def CRC64r64 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
3733 (ins GR64:$src1, GR64:$src2),
3734 "crc32 \t{$src2, $src1|$src1, $src2}",
3736 (int_x86_sse42_crc32_64 GR64:$src1, GR64:$src2))]>,
3739 // TODO: These correspond to int_x86_sse42_crc32_8 but with a 64-bit src
3740 // and dest, figure it out.
3741 //def CRC64m8 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
3742 // (ins GR32:$src1, i8mem:$src2),
3743 // "crc32 \t{$src2, $src1|$src1, $src2}",
3745 // (int_x86_sse42_crc32_8 GR64:$src1,
3746 // (load addr:$src2)))]>,
3748 //def CRC64r8 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
3749 // (ins GR64:$src1, GR8:$src2),
3750 // "crc32 \t{$src2, $src1|$src1, $src2}",
3752 // (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>,