1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 let isCommutable = 1 in
85 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
90 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
97 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
98 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
99 string asm, string SSEVer, string FPSizeStr,
100 X86MemOperand x86memop, PatFrag mem_frag,
101 Domain d, bit Is2Addr = 1> {
102 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
104 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
105 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
106 [(set RC:$dst, (!cast<Intrinsic>(
107 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
108 RC:$src1, RC:$src2))], d>;
109 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
111 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
113 [(set RC:$dst, (!cast<Intrinsic>(
114 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
115 RC:$src1, (mem_frag addr:$src2)))], d>;
118 //===----------------------------------------------------------------------===//
119 // SSE 1 & 2 - Move Instructions
120 //===----------------------------------------------------------------------===//
122 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
123 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
124 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
126 // Loading from memory automatically zeroing upper bits.
127 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
128 PatFrag mem_pat, string OpcodeStr> :
129 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
130 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
131 [(set RC:$dst, (mem_pat addr:$src))]>;
133 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
134 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
135 // is used instead. Register-to-register movss/movsd is not modeled as an
136 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
137 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
138 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
139 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
140 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
141 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
143 let canFoldAsLoad = 1, isReMaterializable = 1 in {
144 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
146 let AddedComplexity = 20 in
147 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
150 let Constraints = "$src1 = $dst" in {
151 def MOVSSrr : sse12_move_rr<FR32, v4f32,
152 "movss\t{$src2, $dst|$dst, $src2}">, XS;
153 def MOVSDrr : sse12_move_rr<FR64, v2f64,
154 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
157 let canFoldAsLoad = 1, isReMaterializable = 1 in {
158 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
160 let AddedComplexity = 20 in
161 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
164 let AddedComplexity = 15 in {
165 // Extract the low 32-bit value from one vector and insert it into another.
166 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
167 (MOVSSrr (v4f32 VR128:$src1),
168 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
169 // Extract the low 64-bit value from one vector and insert it into another.
170 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
171 (MOVSDrr (v2f64 VR128:$src1),
172 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
175 // Implicitly promote a 32-bit scalar to a vector.
176 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
177 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
178 // Implicitly promote a 64-bit scalar to a vector.
179 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
180 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
181 // Implicitly promote a 32-bit scalar to a vector.
182 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
183 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
184 // Implicitly promote a 64-bit scalar to a vector.
185 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
186 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
188 let AddedComplexity = 20 in {
189 let Predicates = [HasSSE1] in {
190 // MOVSSrm zeros the high parts of the register; represent this
191 // with SUBREG_TO_REG.
192 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
193 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
194 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
195 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
196 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
197 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
199 let Predicates = [HasSSE2] in {
200 // MOVSDrm zeros the high parts of the register; represent this
201 // with SUBREG_TO_REG.
202 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
203 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
204 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
205 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
206 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
207 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
208 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
209 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
210 def : Pat<(v2f64 (X86vzload addr:$src)),
211 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
215 let AddedComplexity = 20, Predicates = [HasAVX] in {
216 // MOVSSrm zeros the high parts of the register; represent this
217 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
218 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
219 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
220 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
221 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
222 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
223 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
224 // MOVSDrm zeros the high parts of the register; represent this
225 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
226 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
227 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
228 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
229 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
230 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
231 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
232 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
233 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
234 def : Pat<(v2f64 (X86vzload addr:$src)),
235 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
236 // Represent the same patterns above but in the form they appear for
238 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
239 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
240 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
241 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
242 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
243 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
246 // Store scalar value to memory.
247 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
248 "movss\t{$src, $dst|$dst, $src}",
249 [(store FR32:$src, addr:$dst)]>;
250 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
251 "movsd\t{$src, $dst|$dst, $src}",
252 [(store FR64:$src, addr:$dst)]>;
254 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
255 "movss\t{$src, $dst|$dst, $src}",
256 [(store FR32:$src, addr:$dst)]>, XS, VEX;
257 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
258 "movsd\t{$src, $dst|$dst, $src}",
259 [(store FR64:$src, addr:$dst)]>, XD, VEX;
261 // Extract and store.
262 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
265 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
266 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
269 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
271 // Move Aligned/Unaligned floating point values
272 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
273 X86MemOperand x86memop, PatFrag ld_frag,
274 string asm, Domain d,
275 bit IsReMaterializable = 1> {
276 let neverHasSideEffects = 1 in
277 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
278 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
279 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
280 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
281 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
282 [(set RC:$dst, (ld_frag addr:$src))], d>;
285 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
286 "movaps", SSEPackedSingle>, VEX;
287 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
288 "movapd", SSEPackedDouble>, OpSize, VEX;
289 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
290 "movups", SSEPackedSingle>, VEX;
291 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
292 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
294 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
295 "movaps", SSEPackedSingle>, VEX;
296 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
297 "movapd", SSEPackedDouble>, OpSize, VEX;
298 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
299 "movups", SSEPackedSingle>, VEX;
300 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
301 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
302 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
303 "movaps", SSEPackedSingle>, TB;
304 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
305 "movapd", SSEPackedDouble>, TB, OpSize;
306 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
307 "movups", SSEPackedSingle>, TB;
308 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
309 "movupd", SSEPackedDouble, 0>, TB, OpSize;
311 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
312 "movaps\t{$src, $dst|$dst, $src}",
313 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
314 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
315 "movapd\t{$src, $dst|$dst, $src}",
316 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
317 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
318 "movups\t{$src, $dst|$dst, $src}",
319 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
320 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
321 "movupd\t{$src, $dst|$dst, $src}",
322 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
323 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
324 "movaps\t{$src, $dst|$dst, $src}",
325 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
326 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
327 "movapd\t{$src, $dst|$dst, $src}",
328 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
329 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
330 "movups\t{$src, $dst|$dst, $src}",
331 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
332 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
333 "movupd\t{$src, $dst|$dst, $src}",
334 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
336 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
337 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
338 (VMOVUPSYmr addr:$dst, VR256:$src)>;
340 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
341 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
342 (VMOVUPDYmr addr:$dst, VR256:$src)>;
344 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
345 "movaps\t{$src, $dst|$dst, $src}",
346 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
347 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
348 "movapd\t{$src, $dst|$dst, $src}",
349 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
350 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
351 "movups\t{$src, $dst|$dst, $src}",
352 [(store (v4f32 VR128:$src), addr:$dst)]>;
353 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
354 "movupd\t{$src, $dst|$dst, $src}",
355 [(store (v2f64 VR128:$src), addr:$dst)]>;
357 // Intrinsic forms of MOVUPS/D load and store
358 def VMOVUPSmr_Int : VPSI<0x11, MRMDestMem, (outs),
359 (ins f128mem:$dst, VR128:$src),
360 "movups\t{$src, $dst|$dst, $src}",
361 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX;
362 def VMOVUPDmr_Int : VPDI<0x11, MRMDestMem, (outs),
363 (ins f128mem:$dst, VR128:$src),
364 "movupd\t{$src, $dst|$dst, $src}",
365 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX;
367 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
368 "movups\t{$src, $dst|$dst, $src}",
369 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
370 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
371 "movupd\t{$src, $dst|$dst, $src}",
372 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
374 // Move Low/High packed floating point values
375 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
376 PatFrag mov_frag, string base_opc,
378 def PSrm : PI<opc, MRMSrcMem,
379 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
380 !strconcat(base_opc, "s", asm_opr),
383 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
384 SSEPackedSingle>, TB;
386 def PDrm : PI<opc, MRMSrcMem,
387 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
388 !strconcat(base_opc, "d", asm_opr),
389 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
390 (scalar_to_vector (loadf64 addr:$src2)))))],
391 SSEPackedDouble>, TB, OpSize;
394 let AddedComplexity = 20 in {
395 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
396 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
397 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
398 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
400 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
401 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
402 "\t{$src2, $dst|$dst, $src2}">;
403 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
404 "\t{$src2, $dst|$dst, $src2}">;
407 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
408 "movlps\t{$src, $dst|$dst, $src}",
409 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
410 (iPTR 0))), addr:$dst)]>, VEX;
411 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
412 "movlpd\t{$src, $dst|$dst, $src}",
413 [(store (f64 (vector_extract (v2f64 VR128:$src),
414 (iPTR 0))), addr:$dst)]>, VEX;
415 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
416 "movlps\t{$src, $dst|$dst, $src}",
417 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
418 (iPTR 0))), addr:$dst)]>;
419 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
420 "movlpd\t{$src, $dst|$dst, $src}",
421 [(store (f64 (vector_extract (v2f64 VR128:$src),
422 (iPTR 0))), addr:$dst)]>;
424 // v2f64 extract element 1 is always custom lowered to unpack high to low
425 // and extract element 0 so the non-store version isn't too horrible.
426 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
427 "movhps\t{$src, $dst|$dst, $src}",
428 [(store (f64 (vector_extract
429 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
430 (undef)), (iPTR 0))), addr:$dst)]>,
432 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
433 "movhpd\t{$src, $dst|$dst, $src}",
434 [(store (f64 (vector_extract
435 (v2f64 (unpckh VR128:$src, (undef))),
436 (iPTR 0))), addr:$dst)]>,
438 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
439 "movhps\t{$src, $dst|$dst, $src}",
440 [(store (f64 (vector_extract
441 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
442 (undef)), (iPTR 0))), addr:$dst)]>;
443 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
444 "movhpd\t{$src, $dst|$dst, $src}",
445 [(store (f64 (vector_extract
446 (v2f64 (unpckh VR128:$src, (undef))),
447 (iPTR 0))), addr:$dst)]>;
449 let AddedComplexity = 20 in {
450 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
451 (ins VR128:$src1, VR128:$src2),
452 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
454 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
456 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
457 (ins VR128:$src1, VR128:$src2),
458 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
460 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
463 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
464 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
465 (ins VR128:$src1, VR128:$src2),
466 "movlhps\t{$src2, $dst|$dst, $src2}",
468 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
469 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
470 (ins VR128:$src1, VR128:$src2),
471 "movhlps\t{$src2, $dst|$dst, $src2}",
473 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
476 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
477 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
478 let AddedComplexity = 20 in {
479 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
480 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
481 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
482 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
485 //===----------------------------------------------------------------------===//
486 // SSE 1 & 2 - Conversion Instructions
487 //===----------------------------------------------------------------------===//
489 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
490 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
492 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
493 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
494 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
495 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
498 multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
499 X86MemOperand x86memop, string asm> {
500 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
502 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
506 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
507 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
508 string asm, Domain d> {
509 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
510 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
511 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
512 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
515 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
516 X86MemOperand x86memop, string asm> {
517 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
518 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
519 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
520 (ins DstRC:$src1, x86memop:$src),
521 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
524 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
525 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
526 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
527 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
529 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
530 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
531 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
532 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
535 // The assembler can recognize rr 64-bit instructions by seeing a rxx
536 // register, but the same isn't true when only using memory operands,
537 // provide other assembly "l" and "q" forms to address this explicitly
538 // where appropriate to do so.
539 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
541 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
543 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
545 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
547 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
550 let Predicates = [HasAVX] in {
551 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
552 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
553 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
554 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
555 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
556 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
557 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
558 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
560 def : Pat<(f32 (sint_to_fp GR32:$src)),
561 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
562 def : Pat<(f32 (sint_to_fp GR64:$src)),
563 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
564 def : Pat<(f64 (sint_to_fp GR32:$src)),
565 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
566 def : Pat<(f64 (sint_to_fp GR64:$src)),
567 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
570 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
571 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
572 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
573 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
574 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
575 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
576 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
577 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
578 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
579 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
580 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
581 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
582 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
583 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
584 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
585 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
587 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
588 // and/or XMM operand(s).
590 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
591 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
593 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
594 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
595 [(set DstRC:$dst, (Int SrcRC:$src))]>;
596 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
597 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
598 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
601 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
602 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
603 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
604 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
606 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
607 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
608 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
609 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
610 (ins DstRC:$src1, x86memop:$src2),
612 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
613 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
614 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
617 defm Int_VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
618 f32mem, load, "cvtss2si">, XS, VEX;
619 defm Int_VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
620 int_x86_sse_cvtss2si64, f32mem, load, "cvtss2si">,
622 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
623 f128mem, load, "cvtsd2si">, XD, VEX;
624 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
625 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
628 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
629 // Get rid of this hack or rename the intrinsics, there are several
630 // intructions that only match with the intrinsic form, why create duplicates
631 // to let them be recognized by the assembler?
632 defm VCVTSD2SI_alt : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
633 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
634 defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
635 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
636 defm Int_CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
637 f32mem, load, "cvtss2si">, XS;
638 defm Int_CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
639 f32mem, load, "cvtss2si{q}">, XS, REX_W;
640 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
641 f128mem, load, "cvtsd2si{l}">, XD;
642 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
643 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
646 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
647 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
648 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
649 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
651 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
652 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
653 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
654 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
657 let Constraints = "$src1 = $dst" in {
658 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
659 int_x86_sse_cvtsi2ss, i32mem, loadi32,
661 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
662 int_x86_sse_cvtsi642ss, i64mem, loadi64,
663 "cvtsi2ss{q}">, XS, REX_W;
664 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
665 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
667 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
668 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
669 "cvtsi2sd">, XD, REX_W;
674 // Aliases for intrinsics
675 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
676 f32mem, load, "cvttss2si">, XS, VEX;
677 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
678 int_x86_sse_cvttss2si64, f32mem, load,
679 "cvttss2si">, XS, VEX, VEX_W;
680 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
681 f128mem, load, "cvttsd2si">, XD, VEX;
682 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
683 int_x86_sse2_cvttsd2si64, f128mem, load,
684 "cvttsd2si">, XD, VEX, VEX_W;
685 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
686 f32mem, load, "cvttss2si">, XS;
687 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
688 int_x86_sse_cvttss2si64, f32mem, load,
689 "cvttss2si{q}">, XS, REX_W;
690 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
691 f128mem, load, "cvttsd2si">, XD;
692 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
693 int_x86_sse2_cvttsd2si64, f128mem, load,
694 "cvttsd2si{q}">, XD, REX_W;
696 let Pattern = []<dag> in {
697 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
698 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
699 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
700 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
702 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
703 "cvtdq2ps\t{$src, $dst|$dst, $src}",
704 SSEPackedSingle>, TB, VEX;
705 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
706 "cvtdq2ps\t{$src, $dst|$dst, $src}",
707 SSEPackedSingle>, TB, VEX;
709 let Pattern = []<dag> in {
710 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
711 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
712 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
713 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
714 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
715 "cvtdq2ps\t{$src, $dst|$dst, $src}",
716 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
721 // Convert scalar double to scalar single
722 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
723 (ins FR64:$src1, FR64:$src2),
724 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
726 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
727 (ins FR64:$src1, f64mem:$src2),
728 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
729 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
730 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
733 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
734 "cvtsd2ss\t{$src, $dst|$dst, $src}",
735 [(set FR32:$dst, (fround FR64:$src))]>;
736 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
737 "cvtsd2ss\t{$src, $dst|$dst, $src}",
738 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
739 Requires<[HasSSE2, OptForSize]>;
741 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
742 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
744 let Constraints = "$src1 = $dst" in
745 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
746 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
748 // Convert scalar single to scalar double
749 // SSE2 instructions with XS prefix
750 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
751 (ins FR32:$src1, FR32:$src2),
752 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
753 []>, XS, Requires<[HasAVX]>, VEX_4V;
754 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
755 (ins FR32:$src1, f32mem:$src2),
756 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
757 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
759 let Predicates = [HasAVX] in {
760 def : Pat<(f64 (fextend FR32:$src)),
761 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
762 def : Pat<(fextend (loadf32 addr:$src)),
763 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
764 def : Pat<(extloadf32 addr:$src),
765 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
768 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
769 "cvtss2sd\t{$src, $dst|$dst, $src}",
770 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
772 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
773 "cvtss2sd\t{$src, $dst|$dst, $src}",
774 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
775 Requires<[HasSSE2, OptForSize]>;
777 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
778 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
779 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
780 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
781 VR128:$src2))]>, XS, VEX_4V,
783 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
784 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
785 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
786 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
787 (load addr:$src2)))]>, XS, VEX_4V,
789 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
790 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
791 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
792 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
793 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
796 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
797 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
798 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
799 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
800 (load addr:$src2)))]>, XS,
804 def : Pat<(extloadf32 addr:$src),
805 (CVTSS2SDrr (MOVSSrm addr:$src))>,
806 Requires<[HasSSE2, OptForSpeed]>;
808 // Convert doubleword to packed single/double fp
809 // SSE2 instructions without OpSize prefix
810 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
811 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
812 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
813 TB, VEX, Requires<[HasAVX]>;
814 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
815 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
816 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
817 (bitconvert (memopv2i64 addr:$src))))]>,
818 TB, VEX, Requires<[HasAVX]>;
819 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
820 "cvtdq2ps\t{$src, $dst|$dst, $src}",
821 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
822 TB, Requires<[HasSSE2]>;
823 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
824 "cvtdq2ps\t{$src, $dst|$dst, $src}",
825 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
826 (bitconvert (memopv2i64 addr:$src))))]>,
827 TB, Requires<[HasSSE2]>;
829 // FIXME: why the non-intrinsic version is described as SSE3?
830 // SSE2 instructions with XS prefix
831 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
832 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
833 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
834 XS, VEX, Requires<[HasAVX]>;
835 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
836 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
837 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
838 (bitconvert (memopv2i64 addr:$src))))]>,
839 XS, VEX, Requires<[HasAVX]>;
840 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
841 "cvtdq2pd\t{$src, $dst|$dst, $src}",
842 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
843 XS, Requires<[HasSSE2]>;
844 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
845 "cvtdq2pd\t{$src, $dst|$dst, $src}",
846 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
847 (bitconvert (memopv2i64 addr:$src))))]>,
848 XS, Requires<[HasSSE2]>;
851 // Convert packed single/double fp to doubleword
852 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
853 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
854 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
855 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
856 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
857 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
858 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
859 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
860 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
861 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
862 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
863 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
865 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
866 "cvtps2dq\t{$src, $dst|$dst, $src}",
867 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
869 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
871 "cvtps2dq\t{$src, $dst|$dst, $src}",
872 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
873 (memop addr:$src)))]>, VEX;
874 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
875 "cvtps2dq\t{$src, $dst|$dst, $src}",
876 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
877 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
878 "cvtps2dq\t{$src, $dst|$dst, $src}",
879 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
880 (memop addr:$src)))]>;
882 // SSE2 packed instructions with XD prefix
883 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
884 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
885 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
886 XD, VEX, Requires<[HasAVX]>;
887 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
888 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
889 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
890 (memop addr:$src)))]>,
891 XD, VEX, Requires<[HasAVX]>;
892 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
893 "cvtpd2dq\t{$src, $dst|$dst, $src}",
894 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
895 XD, Requires<[HasSSE2]>;
896 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
897 "cvtpd2dq\t{$src, $dst|$dst, $src}",
898 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
899 (memop addr:$src)))]>,
900 XD, Requires<[HasSSE2]>;
903 // Convert with truncation packed single/double fp to doubleword
904 // SSE2 packed instructions with XS prefix
905 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
906 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
907 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
908 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
909 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
910 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
911 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
912 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
913 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
914 "cvttps2dq\t{$src, $dst|$dst, $src}",
916 (int_x86_sse2_cvttps2dq VR128:$src))]>;
917 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
918 "cvttps2dq\t{$src, $dst|$dst, $src}",
920 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
922 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
923 "vcvttps2dq\t{$src, $dst|$dst, $src}",
925 (int_x86_sse2_cvttps2dq VR128:$src))]>,
926 XS, VEX, Requires<[HasAVX]>;
927 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
928 "vcvttps2dq\t{$src, $dst|$dst, $src}",
929 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
930 (memop addr:$src)))]>,
931 XS, VEX, Requires<[HasAVX]>;
933 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
934 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
935 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
936 (CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
938 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
939 (Int_VCVTDQ2PSrr VR128:$src)>, Requires<[HasAVX]>;
940 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
941 (VCVTTPS2DQrr VR128:$src)>, Requires<[HasAVX]>;
942 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
943 (VCVTDQ2PSYrr VR256:$src)>, Requires<[HasAVX]>;
944 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
945 (VCVTTPS2DQYrr VR256:$src)>, Requires<[HasAVX]>;
947 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
949 "cvttpd2dq\t{$src, $dst|$dst, $src}",
950 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
952 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
954 "cvttpd2dq\t{$src, $dst|$dst, $src}",
955 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
956 (memop addr:$src)))]>, VEX;
957 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
958 "cvttpd2dq\t{$src, $dst|$dst, $src}",
959 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
960 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
961 "cvttpd2dq\t{$src, $dst|$dst, $src}",
962 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
963 (memop addr:$src)))]>;
965 // The assembler can recognize rr 256-bit instructions by seeing a ymm
966 // register, but the same isn't true when using memory operands instead.
967 // Provide other assembly rr and rm forms to address this explicitly.
968 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
969 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
970 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
971 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
974 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
975 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
976 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
977 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
980 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
981 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
982 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
983 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
985 // Convert packed single to packed double
986 let Predicates = [HasAVX] in {
987 // SSE2 instructions without OpSize prefix
988 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
989 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
990 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
991 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
992 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
993 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
994 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
995 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
997 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
998 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
999 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1000 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1002 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1003 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1004 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1005 VEX, Requires<[HasAVX]>;
1006 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1007 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1008 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1009 (load addr:$src)))]>,
1010 VEX, Requires<[HasAVX]>;
1011 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1012 "cvtps2pd\t{$src, $dst|$dst, $src}",
1013 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1014 TB, Requires<[HasSSE2]>;
1015 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1016 "cvtps2pd\t{$src, $dst|$dst, $src}",
1017 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1018 (load addr:$src)))]>,
1019 TB, Requires<[HasSSE2]>;
1021 // Convert packed double to packed single
1022 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1023 // register, but the same isn't true when using memory operands instead.
1024 // Provide other assembly rr and rm forms to address this explicitly.
1025 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1026 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1027 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1028 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1031 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1032 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1033 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1034 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1037 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1038 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1039 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1040 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1041 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1042 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1043 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1044 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1047 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1048 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1049 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1050 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1052 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1053 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1054 (memop addr:$src)))]>;
1055 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1056 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1057 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1058 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1059 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1060 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1061 (memop addr:$src)))]>;
1063 // AVX 256-bit register conversion intrinsics
1064 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1065 // whenever possible to avoid declaring two versions of each one.
1066 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1067 (VCVTDQ2PSYrr VR256:$src)>;
1068 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
1069 (VCVTDQ2PSYrm addr:$src)>;
1071 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1072 (VCVTPD2PSYrr VR256:$src)>;
1073 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1074 (VCVTPD2PSYrm addr:$src)>;
1076 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1077 (VCVTPS2DQYrr VR256:$src)>;
1078 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1079 (VCVTPS2DQYrm addr:$src)>;
1081 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1082 (VCVTPS2PDYrr VR128:$src)>;
1083 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1084 (VCVTPS2PDYrm addr:$src)>;
1086 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1087 (VCVTTPD2DQYrr VR256:$src)>;
1088 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1089 (VCVTTPD2DQYrm addr:$src)>;
1091 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1092 (VCVTTPS2DQYrr VR256:$src)>;
1093 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1094 (VCVTTPS2DQYrm addr:$src)>;
1096 // Match fround for 128/256-bit conversions
1097 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
1098 (VCVTPD2PSYrr VR256:$src)>;
1099 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
1100 (VCVTPD2PSYrm addr:$src)>;
1102 //===----------------------------------------------------------------------===//
1103 // SSE 1 & 2 - Compare Instructions
1104 //===----------------------------------------------------------------------===//
1106 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1107 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1108 string asm, string asm_alt> {
1109 let isAsmParserOnly = 1 in {
1110 def rr : SIi8<0xC2, MRMSrcReg,
1111 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1114 def rm : SIi8<0xC2, MRMSrcMem,
1115 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1119 // Accept explicit immediate argument form instead of comparison code.
1120 def rr_alt : SIi8<0xC2, MRMSrcReg,
1121 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1124 def rm_alt : SIi8<0xC2, MRMSrcMem,
1125 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1129 let neverHasSideEffects = 1 in {
1130 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1131 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1132 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1134 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1135 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1136 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1140 let Constraints = "$src1 = $dst" in {
1141 def CMPSSrr : SIi8<0xC2, MRMSrcReg,
1142 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc),
1143 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1144 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2, imm:$cc))]>, XS;
1145 def CMPSSrm : SIi8<0xC2, MRMSrcMem,
1146 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc),
1147 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1148 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), (loadf32 addr:$src2), imm:$cc))]>, XS;
1149 def CMPSDrr : SIi8<0xC2, MRMSrcReg,
1150 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc),
1151 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1152 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2, imm:$cc))]>, XD;
1153 def CMPSDrm : SIi8<0xC2, MRMSrcMem,
1154 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc),
1155 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1156 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2), imm:$cc))]>, XD;
1158 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1159 def CMPSSrr_alt : SIi8<0xC2, MRMSrcReg,
1160 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
1161 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1162 def CMPSSrm_alt : SIi8<0xC2, MRMSrcMem,
1163 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
1164 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1165 def CMPSDrr_alt : SIi8<0xC2, MRMSrcReg,
1166 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
1167 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1168 def CMPSDrm_alt : SIi8<0xC2, MRMSrcMem,
1169 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
1170 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1173 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
1174 Intrinsic Int, string asm> {
1175 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1176 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1177 [(set VR128:$dst, (Int VR128:$src1,
1178 VR128:$src, imm:$cc))]>;
1179 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1180 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
1181 [(set VR128:$dst, (Int VR128:$src1,
1182 (load addr:$src), imm:$cc))]>;
1185 // Aliases to match intrinsics which expect XMM operand(s).
1186 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1187 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1189 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1190 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1192 let Constraints = "$src1 = $dst" in {
1193 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1194 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1195 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1196 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1200 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1201 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
1202 ValueType vt, X86MemOperand x86memop,
1203 PatFrag ld_frag, string OpcodeStr, Domain d> {
1204 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1205 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1206 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
1207 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
1208 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1209 [(set EFLAGS, (OpNode (vt RC:$src1),
1210 (ld_frag addr:$src2)))], d>;
1213 let Defs = [EFLAGS] in {
1214 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1215 "ucomiss", SSEPackedSingle>, VEX;
1216 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1217 "ucomisd", SSEPackedDouble>, OpSize, VEX;
1218 let Pattern = []<dag> in {
1219 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1220 "comiss", SSEPackedSingle>, VEX;
1221 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1222 "comisd", SSEPackedDouble>, OpSize, VEX;
1225 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1226 load, "ucomiss", SSEPackedSingle>, VEX;
1227 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1228 load, "ucomisd", SSEPackedDouble>, OpSize, VEX;
1230 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
1231 load, "comiss", SSEPackedSingle>, VEX;
1232 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
1233 load, "comisd", SSEPackedDouble>, OpSize, VEX;
1234 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1235 "ucomiss", SSEPackedSingle>, TB;
1236 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1237 "ucomisd", SSEPackedDouble>, TB, OpSize;
1239 let Pattern = []<dag> in {
1240 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1241 "comiss", SSEPackedSingle>, TB;
1242 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1243 "comisd", SSEPackedDouble>, TB, OpSize;
1246 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1247 load, "ucomiss", SSEPackedSingle>, TB;
1248 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1249 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
1251 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
1252 "comiss", SSEPackedSingle>, TB;
1253 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
1254 "comisd", SSEPackedDouble>, TB, OpSize;
1255 } // Defs = [EFLAGS]
1257 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
1258 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
1259 Intrinsic Int, string asm, string asm_alt,
1261 let isAsmParserOnly = 1 in {
1262 def rri : PIi8<0xC2, MRMSrcReg,
1263 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1264 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1265 def rmi : PIi8<0xC2, MRMSrcMem,
1266 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1267 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1270 // Accept explicit immediate argument form instead of comparison code.
1271 def rri_alt : PIi8<0xC2, MRMSrcReg,
1272 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1274 def rmi_alt : PIi8<0xC2, MRMSrcMem,
1275 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1279 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1280 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1281 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1282 SSEPackedSingle>, VEX_4V;
1283 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1284 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1285 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1286 SSEPackedDouble>, OpSize, VEX_4V;
1287 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
1288 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1289 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1290 SSEPackedSingle>, VEX_4V;
1291 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
1292 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1293 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1294 SSEPackedDouble>, OpSize, VEX_4V;
1295 let Constraints = "$src1 = $dst" in {
1296 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1297 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1298 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1299 SSEPackedSingle>, TB;
1300 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1301 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1302 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1303 SSEPackedDouble>, TB, OpSize;
1306 let Predicates = [HasSSE1] in {
1307 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1308 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1309 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1310 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1313 let Predicates = [HasSSE2] in {
1314 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1315 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1316 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1317 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1320 let Predicates = [HasAVX] in {
1321 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1322 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1323 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1324 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1325 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1326 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1327 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1328 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1330 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
1331 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
1332 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
1333 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
1334 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
1335 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
1336 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
1337 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
1340 //===----------------------------------------------------------------------===//
1341 // SSE 1 & 2 - Shuffle Instructions
1342 //===----------------------------------------------------------------------===//
1344 /// sse12_shuffle - sse 1 & 2 shuffle instructions
1345 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
1346 ValueType vt, string asm, PatFrag mem_frag,
1347 Domain d, bit IsConvertibleToThreeAddress = 0> {
1348 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
1349 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
1350 [(set RC:$dst, (vt (shufp:$src3
1351 RC:$src1, (mem_frag addr:$src2))))], d>;
1352 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
1353 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
1354 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
1356 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
1359 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1360 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1361 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
1362 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
1363 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1364 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
1365 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1366 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1367 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1368 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
1369 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1370 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1372 let Constraints = "$src1 = $dst" in {
1373 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1374 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1375 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
1377 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1378 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1379 memopv2f64, SSEPackedDouble>, TB, OpSize;
1382 //===----------------------------------------------------------------------===//
1383 // SSE 1 & 2 - Unpack Instructions
1384 //===----------------------------------------------------------------------===//
1386 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
1387 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
1388 PatFrag mem_frag, RegisterClass RC,
1389 X86MemOperand x86memop, string asm,
1391 def rr : PI<opc, MRMSrcReg,
1392 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1394 (vt (OpNode RC:$src1, RC:$src2)))], d>;
1395 def rm : PI<opc, MRMSrcMem,
1396 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1398 (vt (OpNode RC:$src1,
1399 (mem_frag addr:$src2))))], d>;
1402 let AddedComplexity = 10 in {
1403 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1404 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1405 SSEPackedSingle>, VEX_4V;
1406 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1407 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1408 SSEPackedDouble>, OpSize, VEX_4V;
1409 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1410 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1411 SSEPackedSingle>, VEX_4V;
1412 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1413 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1414 SSEPackedDouble>, OpSize, VEX_4V;
1416 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
1417 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1418 SSEPackedSingle>, VEX_4V;
1419 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
1420 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1421 SSEPackedDouble>, OpSize, VEX_4V;
1422 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
1423 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1424 SSEPackedSingle>, VEX_4V;
1425 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
1426 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1427 SSEPackedDouble>, OpSize, VEX_4V;
1429 let Constraints = "$src1 = $dst" in {
1430 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1431 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1432 SSEPackedSingle>, TB;
1433 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1434 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1435 SSEPackedDouble>, TB, OpSize;
1436 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1437 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1438 SSEPackedSingle>, TB;
1439 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1440 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1441 SSEPackedDouble>, TB, OpSize;
1442 } // Constraints = "$src1 = $dst"
1443 } // AddedComplexity
1445 //===----------------------------------------------------------------------===//
1446 // SSE 1 & 2 - Extract Floating-Point Sign mask
1447 //===----------------------------------------------------------------------===//
1449 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
1450 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
1452 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
1453 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1454 [(set GR32:$dst, (Int RC:$src))], d>;
1455 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
1456 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
1460 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
1461 "movmskps", SSEPackedSingle>, VEX;
1462 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
1463 "movmskpd", SSEPackedDouble>, OpSize,
1465 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
1466 "movmskps", SSEPackedSingle>, VEX;
1467 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
1468 "movmskpd", SSEPackedDouble>, OpSize,
1470 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
1471 SSEPackedSingle>, TB;
1472 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
1473 SSEPackedDouble>, TB, OpSize;
1476 def MOVMSKPDrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1477 "movmskpd\t{$src, $dst|$dst, $src}",
1478 [(set GR32:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB, OpSize;
1479 def MOVMSKPDrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1480 "movmskpd\t{$src, $dst|$dst, $src}",
1481 [(set GR64:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB, OpSize;
1482 def MOVMSKPSrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
1483 "movmskps\t{$src, $dst|$dst, $src}",
1484 [(set GR32:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
1485 def MOVMSKPSrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1486 "movmskps\t{$src, $dst|$dst, $src}",
1487 [(set GR64:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
1490 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1491 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1492 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1493 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1495 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1496 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1497 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1498 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1501 //===----------------------------------------------------------------------===//
1502 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
1503 //===----------------------------------------------------------------------===//
1505 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
1506 // names that start with 'Fs'.
1508 // Alias instructions that map fld0 to pxor for sse.
1509 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1510 canFoldAsLoad = 1 in {
1511 // FIXME: Set encoding to pseudo!
1512 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1513 [(set FR32:$dst, fp32imm0)]>,
1514 Requires<[HasSSE1]>, TB, OpSize;
1515 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1516 [(set FR64:$dst, fpimm0)]>,
1517 Requires<[HasSSE2]>, TB, OpSize;
1518 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1519 [(set FR32:$dst, fp32imm0)]>,
1520 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1521 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1522 [(set FR64:$dst, fpimm0)]>,
1523 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1526 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1527 // bits are disregarded.
1528 let neverHasSideEffects = 1 in {
1529 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1530 "movaps\t{$src, $dst|$dst, $src}", []>;
1531 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1532 "movapd\t{$src, $dst|$dst, $src}", []>;
1535 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1536 // bits are disregarded.
1537 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1538 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1539 "movaps\t{$src, $dst|$dst, $src}",
1540 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
1541 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1542 "movapd\t{$src, $dst|$dst, $src}",
1543 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1546 //===----------------------------------------------------------------------===//
1547 // SSE 1 & 2 - Logical Instructions
1548 //===----------------------------------------------------------------------===//
1550 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
1552 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
1554 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
1555 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, VEX_4V;
1557 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
1558 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, OpSize, VEX_4V;
1560 let Constraints = "$src1 = $dst" in {
1561 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
1562 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
1564 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
1565 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
1569 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1570 let mayLoad = 0 in {
1571 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
1572 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
1573 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
1576 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
1577 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
1579 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
1581 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
1583 let Pattern = []<dag> in {
1584 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1585 !strconcat(OpcodeStr, "ps"), f128mem,
1586 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
1587 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1588 (memopv2i64 addr:$src2)))], 0>, VEX_4V;
1590 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1591 !strconcat(OpcodeStr, "pd"), f128mem,
1592 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1593 (bc_v2i64 (v2f64 VR128:$src2))))],
1594 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1595 (memopv2i64 addr:$src2)))], 0>,
1598 let Constraints = "$src1 = $dst" in {
1599 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1600 !strconcat(OpcodeStr, "ps"), f128mem,
1601 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
1602 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1603 (memopv2i64 addr:$src2)))]>, TB;
1605 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1606 !strconcat(OpcodeStr, "pd"), f128mem,
1607 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1608 (bc_v2i64 (v2f64 VR128:$src2))))],
1609 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1610 (memopv2i64 addr:$src2)))]>, TB, OpSize;
1614 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
1616 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
1618 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
1619 !strconcat(OpcodeStr, "ps"), f256mem,
1620 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
1621 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
1622 (memopv4i64 addr:$src2)))], 0>, VEX_4V;
1624 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
1625 !strconcat(OpcodeStr, "pd"), f256mem,
1626 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
1627 (bc_v4i64 (v4f64 VR256:$src2))))],
1628 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
1629 (memopv4i64 addr:$src2)))], 0>,
1633 // AVX 256-bit packed logical ops forms
1634 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
1635 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
1636 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
1637 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
1639 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
1640 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
1641 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
1642 let isCommutable = 0 in
1643 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
1645 //===----------------------------------------------------------------------===//
1646 // SSE 1 & 2 - Arithmetic Instructions
1647 //===----------------------------------------------------------------------===//
1649 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
1652 /// In addition, we also have a special variant of the scalar form here to
1653 /// represent the associated intrinsic operation. This form is unlike the
1654 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1655 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1657 /// These three forms can each be reg+reg or reg+mem.
1660 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
1662 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1664 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
1665 OpNode, FR32, f32mem, Is2Addr>, XS;
1666 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
1667 OpNode, FR64, f64mem, Is2Addr>, XD;
1670 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
1672 let mayLoad = 0 in {
1673 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
1674 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
1675 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
1676 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
1680 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
1682 let mayLoad = 0 in {
1683 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
1684 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
1685 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
1686 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
1690 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
1692 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1693 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
1694 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1695 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
1698 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
1700 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1701 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
1702 SSEPackedSingle, Is2Addr>, TB;
1704 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1705 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
1706 SSEPackedDouble, Is2Addr>, TB, OpSize;
1709 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
1710 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1711 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
1712 SSEPackedSingle, 0>, TB;
1714 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1715 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
1716 SSEPackedDouble, 0>, TB, OpSize;
1719 // Binary Arithmetic instructions
1720 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
1721 basic_sse12_fp_binop_s_int<0x58, "add", 0>,
1722 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
1723 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
1724 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
1725 basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
1726 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
1727 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
1729 let isCommutable = 0 in {
1730 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
1731 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
1732 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
1733 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
1734 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
1735 basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
1736 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
1737 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
1738 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
1739 basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
1740 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
1741 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
1742 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
1743 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
1744 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
1745 basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
1746 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
1747 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
1748 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
1749 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
1752 let Constraints = "$src1 = $dst" in {
1753 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
1754 basic_sse12_fp_binop_p<0x58, "add", fadd>,
1755 basic_sse12_fp_binop_s_int<0x58, "add">;
1756 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
1757 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
1758 basic_sse12_fp_binop_s_int<0x59, "mul">;
1760 let isCommutable = 0 in {
1761 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
1762 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
1763 basic_sse12_fp_binop_s_int<0x5C, "sub">;
1764 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
1765 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
1766 basic_sse12_fp_binop_s_int<0x5E, "div">;
1767 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
1768 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
1769 basic_sse12_fp_binop_s_int<0x5F, "max">,
1770 basic_sse12_fp_binop_p_int<0x5F, "max">;
1771 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
1772 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
1773 basic_sse12_fp_binop_s_int<0x5D, "min">,
1774 basic_sse12_fp_binop_p_int<0x5D, "min">;
1779 /// In addition, we also have a special variant of the scalar form here to
1780 /// represent the associated intrinsic operation. This form is unlike the
1781 /// plain scalar form, in that it takes an entire vector (instead of a
1782 /// scalar) and leaves the top elements undefined.
1784 /// And, we have a special variant form for a full-vector intrinsic form.
1786 /// sse1_fp_unop_s - SSE1 unops in scalar form.
1787 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
1788 SDNode OpNode, Intrinsic F32Int> {
1789 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1790 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1791 [(set FR32:$dst, (OpNode FR32:$src))]>;
1792 // For scalar unary operations, fold a load into the operation
1793 // only in OptForSize mode. It eliminates an instruction, but it also
1794 // eliminates a whole-register clobber (the load), so it introduces a
1795 // partial register update condition.
1796 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1797 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1798 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1799 Requires<[HasSSE1, OptForSize]>;
1800 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1801 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1802 [(set VR128:$dst, (F32Int VR128:$src))]>;
1803 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1804 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1805 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1808 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
1809 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1810 SDNode OpNode, Intrinsic F32Int> {
1811 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
1812 !strconcat(OpcodeStr,
1813 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1814 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
1815 !strconcat(OpcodeStr,
1816 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1817 []>, XS, Requires<[HasAVX, OptForSize]>;
1818 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1819 !strconcat(OpcodeStr,
1820 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1821 [(set VR128:$dst, (F32Int VR128:$src))]>;
1822 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1823 !strconcat(OpcodeStr,
1824 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1825 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1828 /// sse1_fp_unop_p - SSE1 unops in packed form.
1829 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1830 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1831 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1832 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
1833 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1834 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1835 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1838 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
1839 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1840 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1841 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1842 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
1843 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1844 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1845 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
1848 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
1849 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1850 Intrinsic V4F32Int> {
1851 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1852 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1853 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
1854 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1855 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1856 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1859 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
1860 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1861 Intrinsic V4F32Int> {
1862 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1863 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1864 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
1865 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1866 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1867 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
1870 /// sse2_fp_unop_s - SSE2 unops in scalar form.
1871 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
1872 SDNode OpNode, Intrinsic F64Int> {
1873 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1874 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1875 [(set FR64:$dst, (OpNode FR64:$src))]>;
1876 // See the comments in sse1_fp_unop_s for why this is OptForSize.
1877 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1878 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1879 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
1880 Requires<[HasSSE2, OptForSize]>;
1881 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1882 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1883 [(set VR128:$dst, (F64Int VR128:$src))]>;
1884 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1885 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1886 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1889 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
1890 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1891 SDNode OpNode, Intrinsic F64Int> {
1892 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1893 !strconcat(OpcodeStr,
1894 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1895 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1896 (ins FR64:$src1, f64mem:$src2),
1897 !strconcat(OpcodeStr,
1898 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1899 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1900 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1901 [(set VR128:$dst, (F64Int VR128:$src))]>;
1902 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1903 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1904 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1907 /// sse2_fp_unop_p - SSE2 unops in vector forms.
1908 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
1910 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1911 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1912 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
1913 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1914 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1915 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1918 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
1919 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1920 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1921 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1922 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
1923 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1924 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1925 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
1928 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
1929 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1930 Intrinsic V2F64Int> {
1931 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1932 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1933 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
1934 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1935 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1936 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1939 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
1940 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1941 Intrinsic V2F64Int> {
1942 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1943 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1944 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
1945 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1946 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1947 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
1950 let Predicates = [HasAVX] in {
1952 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ss>,
1953 sse2_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1956 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
1957 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
1958 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1959 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1960 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
1961 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
1962 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
1963 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
1966 // Reciprocal approximations. Note that these typically require refinement
1967 // in order to obtain suitable precision.
1968 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt", X86frsqrt,
1969 int_x86_sse_rsqrt_ss>, VEX_4V;
1970 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
1971 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
1972 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
1973 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
1975 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ss>,
1977 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
1978 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
1979 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
1980 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
1983 def : Pat<(f32 (fsqrt FR32:$src)),
1984 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
1985 def : Pat<(f64 (fsqrt FR64:$src)),
1986 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
1987 def : Pat<(f64 (fsqrt (load addr:$src))),
1988 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
1989 Requires<[HasAVX, OptForSize]>;
1990 def : Pat<(f32 (fsqrt (load addr:$src))),
1991 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
1992 Requires<[HasAVX, OptForSize]>;
1995 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
1996 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
1997 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
1998 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1999 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
2000 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
2002 // Reciprocal approximations. Note that these typically require refinement
2003 // in order to obtain suitable precision.
2004 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
2005 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
2006 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
2007 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
2008 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
2009 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
2011 // There is no f64 version of the reciprocal approximation instructions.
2013 //===----------------------------------------------------------------------===//
2014 // SSE 1 & 2 - Non-temporal stores
2015 //===----------------------------------------------------------------------===//
2017 let AddedComplexity = 400 in { // Prefer non-temporal versions
2018 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
2019 (ins f128mem:$dst, VR128:$src),
2020 "movntps\t{$src, $dst|$dst, $src}",
2021 [(alignednontemporalstore (v4f32 VR128:$src),
2023 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
2024 (ins f128mem:$dst, VR128:$src),
2025 "movntpd\t{$src, $dst|$dst, $src}",
2026 [(alignednontemporalstore (v2f64 VR128:$src),
2028 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
2029 (ins f128mem:$dst, VR128:$src),
2030 "movntdq\t{$src, $dst|$dst, $src}",
2031 [(alignednontemporalstore (v2f64 VR128:$src),
2034 let ExeDomain = SSEPackedInt in
2035 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
2036 (ins f128mem:$dst, VR128:$src),
2037 "movntdq\t{$src, $dst|$dst, $src}",
2038 [(alignednontemporalstore (v4f32 VR128:$src),
2041 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
2042 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
2044 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
2045 (ins f256mem:$dst, VR256:$src),
2046 "movntps\t{$src, $dst|$dst, $src}",
2047 [(alignednontemporalstore (v8f32 VR256:$src),
2049 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
2050 (ins f256mem:$dst, VR256:$src),
2051 "movntpd\t{$src, $dst|$dst, $src}",
2052 [(alignednontemporalstore (v4f64 VR256:$src),
2054 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
2055 (ins f256mem:$dst, VR256:$src),
2056 "movntdq\t{$src, $dst|$dst, $src}",
2057 [(alignednontemporalstore (v4f64 VR256:$src),
2059 let ExeDomain = SSEPackedInt in
2060 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
2061 (ins f256mem:$dst, VR256:$src),
2062 "movntdq\t{$src, $dst|$dst, $src}",
2063 [(alignednontemporalstore (v8f32 VR256:$src),
2067 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
2068 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
2069 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
2070 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
2071 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
2072 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
2074 let AddedComplexity = 400 in { // Prefer non-temporal versions
2075 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2076 "movntps\t{$src, $dst|$dst, $src}",
2077 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2078 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2079 "movntpd\t{$src, $dst|$dst, $src}",
2080 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2082 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2083 "movntdq\t{$src, $dst|$dst, $src}",
2084 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
2086 let ExeDomain = SSEPackedInt in
2087 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2088 "movntdq\t{$src, $dst|$dst, $src}",
2089 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2091 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
2092 (MOVNTDQmr addr:$dst, VR128:$src)>;
2094 // There is no AVX form for instructions below this point
2095 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2096 "movnti{l}\t{$src, $dst|$dst, $src}",
2097 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
2098 TB, Requires<[HasSSE2]>;
2099 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2100 "movnti{q}\t{$src, $dst|$dst, $src}",
2101 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
2102 TB, Requires<[HasSSE2]>;
2105 //===----------------------------------------------------------------------===//
2106 // SSE 1 & 2 - Misc Instructions (No AVX form)
2107 //===----------------------------------------------------------------------===//
2109 // Prefetch intrinsic.
2110 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
2111 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
2112 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
2113 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
2114 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
2115 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
2116 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
2117 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
2119 // Load, store, and memory fence
2120 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
2121 TB, Requires<[HasSSE1]>;
2122 def : Pat<(X86SFence), (SFENCE)>;
2124 // Alias instructions that map zero vector to pxor / xorp* for sse.
2125 // We set canFoldAsLoad because this can be converted to a constant-pool
2126 // load of an all-zeros value if folding it would be beneficial.
2127 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
2128 // JIT implementation, it does not expand the instructions below like
2129 // X86MCInstLower does.
2130 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2131 isCodeGenOnly = 1 in {
2132 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2133 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2134 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2135 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
2136 let ExeDomain = SSEPackedInt in
2137 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2138 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2141 // The same as done above but for AVX. The 128-bit versions are the
2142 // same, but re-encoded. The 256-bit does not support PI version, and
2143 // doesn't need it because on sandy bridge the register is set to zero
2144 // at the rename stage without using any execution unit, so SET0PSY
2145 // and SET0PDY can be used for vector int instructions without penalty
2146 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
2147 // JIT implementatioan, it does not expand the instructions below like
2148 // X86MCInstLower does.
2149 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2150 isCodeGenOnly = 1, Predicates = [HasAVX] in {
2151 def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2152 [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V;
2153 def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2154 [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V;
2155 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2156 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
2157 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2158 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
2159 let ExeDomain = SSEPackedInt in
2160 def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2161 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2164 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
2165 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
2166 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
2168 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2169 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
2171 // AVX has no support for 256-bit integer instructions, but since the 128-bit
2172 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
2173 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
2174 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
2175 (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
2177 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
2178 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
2179 (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
2181 //===----------------------------------------------------------------------===//
2182 // SSE 1 & 2 - Load/Store XCSR register
2183 //===----------------------------------------------------------------------===//
2185 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2186 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
2187 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2188 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
2190 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2191 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
2192 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2193 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
2195 //===---------------------------------------------------------------------===//
2196 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
2197 //===---------------------------------------------------------------------===//
2199 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2201 let neverHasSideEffects = 1 in {
2202 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2203 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2204 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2205 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2207 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2208 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2209 def VMOVDQUYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2210 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2212 let canFoldAsLoad = 1, mayLoad = 1 in {
2213 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2214 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2215 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2216 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2217 let Predicates = [HasAVX] in {
2218 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2219 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2220 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2221 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2225 let mayStore = 1 in {
2226 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
2227 (ins i128mem:$dst, VR128:$src),
2228 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2229 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
2230 (ins i256mem:$dst, VR256:$src),
2231 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2232 let Predicates = [HasAVX] in {
2233 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2234 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2235 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
2236 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2240 let neverHasSideEffects = 1 in
2241 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2242 "movdqa\t{$src, $dst|$dst, $src}", []>;
2244 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2245 "movdqu\t{$src, $dst|$dst, $src}",
2246 []>, XS, Requires<[HasSSE2]>;
2248 let canFoldAsLoad = 1, mayLoad = 1 in {
2249 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2250 "movdqa\t{$src, $dst|$dst, $src}",
2251 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
2252 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2253 "movdqu\t{$src, $dst|$dst, $src}",
2254 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2255 XS, Requires<[HasSSE2]>;
2258 let mayStore = 1 in {
2259 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2260 "movdqa\t{$src, $dst|$dst, $src}",
2261 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
2262 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2263 "movdqu\t{$src, $dst|$dst, $src}",
2264 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2265 XS, Requires<[HasSSE2]>;
2268 // Intrinsic forms of MOVDQU load and store
2269 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2270 "vmovdqu\t{$src, $dst|$dst, $src}",
2271 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2272 XS, VEX, Requires<[HasAVX]>;
2274 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2275 "movdqu\t{$src, $dst|$dst, $src}",
2276 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2277 XS, Requires<[HasSSE2]>;
2279 } // ExeDomain = SSEPackedInt
2281 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
2282 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
2283 (VMOVDQUYmr addr:$dst, VR256:$src)>;
2285 //===---------------------------------------------------------------------===//
2286 // SSE2 - Packed Integer Arithmetic Instructions
2287 //===---------------------------------------------------------------------===//
2289 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2291 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2292 bit IsCommutable = 0, bit Is2Addr = 1> {
2293 let isCommutable = IsCommutable in
2294 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2295 (ins VR128:$src1, VR128:$src2),
2297 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2298 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2299 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2300 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2301 (ins VR128:$src1, i128mem:$src2),
2303 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2304 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2305 [(set VR128:$dst, (IntId VR128:$src1,
2306 (bitconvert (memopv2i64 addr:$src2))))]>;
2309 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2310 string OpcodeStr, Intrinsic IntId,
2311 Intrinsic IntId2, bit Is2Addr = 1> {
2312 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2313 (ins VR128:$src1, VR128:$src2),
2315 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2316 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2317 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2318 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2319 (ins VR128:$src1, i128mem:$src2),
2321 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2322 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2323 [(set VR128:$dst, (IntId VR128:$src1,
2324 (bitconvert (memopv2i64 addr:$src2))))]>;
2325 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2326 (ins VR128:$src1, i32i8imm:$src2),
2328 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2329 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2330 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2333 /// PDI_binop_rm - Simple SSE2 binary operator.
2334 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2335 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
2336 let isCommutable = IsCommutable in
2337 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2338 (ins VR128:$src1, VR128:$src2),
2340 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2341 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2342 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2343 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2344 (ins VR128:$src1, i128mem:$src2),
2346 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2347 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2348 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2349 (bitconvert (memopv2i64 addr:$src2)))))]>;
2352 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2354 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2355 /// to collapse (bitconvert VT to VT) into its operand.
2357 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2358 bit IsCommutable = 0, bit Is2Addr = 1> {
2359 let isCommutable = IsCommutable in
2360 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2361 (ins VR128:$src1, VR128:$src2),
2363 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2364 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2365 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
2366 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2367 (ins VR128:$src1, i128mem:$src2),
2369 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2370 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2371 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
2374 } // ExeDomain = SSEPackedInt
2376 // 128-bit Integer Arithmetic
2378 let Predicates = [HasAVX] in {
2379 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
2380 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
2381 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
2382 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
2383 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
2384 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
2385 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
2386 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
2387 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
2390 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
2392 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
2394 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
2396 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
2398 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
2400 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
2402 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
2404 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
2406 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
2408 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
2410 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
2412 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
2414 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
2416 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
2418 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
2420 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
2422 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
2424 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
2426 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
2430 let Constraints = "$src1 = $dst" in {
2431 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2432 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2433 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2434 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2435 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2436 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2437 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2438 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2439 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2442 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2443 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2444 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2445 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2446 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2447 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2448 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2449 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2450 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2451 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
2452 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2453 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2454 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2455 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2456 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2457 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2458 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2459 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2460 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2462 } // Constraints = "$src1 = $dst"
2464 //===---------------------------------------------------------------------===//
2465 // SSE2 - Packed Integer Logical Instructions
2466 //===---------------------------------------------------------------------===//
2468 let Predicates = [HasAVX] in {
2469 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
2470 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
2472 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
2473 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
2475 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
2476 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
2479 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
2480 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
2482 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
2483 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
2485 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
2486 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
2489 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
2490 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
2492 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
2493 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
2496 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
2497 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
2498 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
2500 let ExeDomain = SSEPackedInt in {
2501 let neverHasSideEffects = 1 in {
2502 // 128-bit logical shifts.
2503 def VPSLLDQri : PDIi8<0x73, MRM7r,
2504 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2505 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2507 def VPSRLDQri : PDIi8<0x73, MRM3r,
2508 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2509 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2511 // PSRADQri doesn't exist in SSE[1-3].
2513 def VPANDNrr : PDI<0xDF, MRMSrcReg,
2514 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2515 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2516 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2517 VR128:$src2)))]>, VEX_4V;
2519 def VPANDNrm : PDI<0xDF, MRMSrcMem,
2520 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2521 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2522 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2523 (memopv2i64 addr:$src2))))]>,
2528 let Constraints = "$src1 = $dst" in {
2529 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2530 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2531 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2532 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2533 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2534 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2536 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2537 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2538 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2539 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2540 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2541 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2543 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2544 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2545 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2546 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2548 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2549 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
2550 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2552 let ExeDomain = SSEPackedInt in {
2553 let neverHasSideEffects = 1 in {
2554 // 128-bit logical shifts.
2555 def PSLLDQri : PDIi8<0x73, MRM7r,
2556 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2557 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2558 def PSRLDQri : PDIi8<0x73, MRM3r,
2559 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2560 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2561 // PSRADQri doesn't exist in SSE[1-3].
2563 def PANDNrr : PDI<0xDF, MRMSrcReg,
2564 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2565 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2567 def PANDNrm : PDI<0xDF, MRMSrcMem,
2568 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2569 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2571 } // Constraints = "$src1 = $dst"
2573 let Predicates = [HasAVX] in {
2574 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2575 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2576 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2577 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2578 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2579 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
2580 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2581 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
2582 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2583 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2585 // Shift up / down and insert zero's.
2586 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2587 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2588 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2589 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2592 let Predicates = [HasSSE2] in {
2593 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2594 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2595 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2596 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2597 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2598 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2599 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2600 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2601 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2602 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2604 // Shift up / down and insert zero's.
2605 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2606 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2607 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2608 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2611 //===---------------------------------------------------------------------===//
2612 // SSE2 - Packed Integer Comparison Instructions
2613 //===---------------------------------------------------------------------===//
2615 let Predicates = [HasAVX] in {
2616 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
2618 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
2620 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
2622 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
2624 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
2626 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
2630 let Constraints = "$src1 = $dst" in {
2631 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
2632 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
2633 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
2634 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2635 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2636 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2637 } // Constraints = "$src1 = $dst"
2639 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2640 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2641 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2642 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2643 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2644 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2645 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2646 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2647 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2648 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2649 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2650 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2652 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2653 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2654 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2655 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2656 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2657 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2658 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2659 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2660 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2661 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2662 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2663 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2665 //===---------------------------------------------------------------------===//
2666 // SSE2 - Packed Integer Pack Instructions
2667 //===---------------------------------------------------------------------===//
2669 let Predicates = [HasAVX] in {
2670 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
2672 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
2674 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
2678 let Constraints = "$src1 = $dst" in {
2679 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2680 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2681 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2682 } // Constraints = "$src1 = $dst"
2684 //===---------------------------------------------------------------------===//
2685 // SSE2 - Packed Integer Shuffle Instructions
2686 //===---------------------------------------------------------------------===//
2688 let ExeDomain = SSEPackedInt in {
2689 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
2691 def ri : Ii8<0x70, MRMSrcReg,
2692 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2693 !strconcat(OpcodeStr,
2694 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2695 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
2697 def mi : Ii8<0x70, MRMSrcMem,
2698 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2699 !strconcat(OpcodeStr,
2700 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2701 [(set VR128:$dst, (vt (pshuf_frag:$src2
2702 (bc_frag (memopv2i64 addr:$src1)),
2705 } // ExeDomain = SSEPackedInt
2707 let Predicates = [HasAVX] in {
2708 let AddedComplexity = 5 in
2709 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize,
2712 // SSE2 with ImmT == Imm8 and XS prefix.
2713 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
2716 // SSE2 with ImmT == Imm8 and XD prefix.
2717 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
2721 let Predicates = [HasSSE2] in {
2722 let AddedComplexity = 5 in
2723 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
2725 // SSE2 with ImmT == Imm8 and XS prefix.
2726 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
2728 // SSE2 with ImmT == Imm8 and XD prefix.
2729 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
2732 //===---------------------------------------------------------------------===//
2733 // SSE2 - Packed Integer Unpack Instructions
2734 //===---------------------------------------------------------------------===//
2736 let ExeDomain = SSEPackedInt in {
2737 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2738 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
2739 def rr : PDI<opc, MRMSrcReg,
2740 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2742 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2743 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2744 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))]>;
2745 def rm : PDI<opc, MRMSrcMem,
2746 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2748 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2749 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2750 [(set VR128:$dst, (OpNode VR128:$src1,
2751 (bc_frag (memopv2i64
2755 let Predicates = [HasAVX] in {
2756 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Punpcklbw,
2757 bc_v16i8, 0>, VEX_4V;
2758 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Punpcklwd,
2759 bc_v8i16, 0>, VEX_4V;
2760 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Punpckldq,
2761 bc_v4i32, 0>, VEX_4V;
2763 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2764 /// knew to collapse (bitconvert VT to VT) into its operand.
2765 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2766 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2767 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2768 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
2769 VR128:$src2)))]>, VEX_4V;
2770 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2771 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2772 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2773 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
2774 (memopv2i64 addr:$src2))))]>, VEX_4V;
2776 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Punpckhbw,
2777 bc_v16i8, 0>, VEX_4V;
2778 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Punpckhwd,
2779 bc_v8i16, 0>, VEX_4V;
2780 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Punpckhdq,
2781 bc_v4i32, 0>, VEX_4V;
2783 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2784 /// knew to collapse (bitconvert VT to VT) into its operand.
2785 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2786 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2787 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2788 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
2789 VR128:$src2)))]>, VEX_4V;
2790 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2791 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2792 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2793 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
2794 (memopv2i64 addr:$src2))))]>, VEX_4V;
2797 let Constraints = "$src1 = $dst" in {
2798 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Punpcklbw, bc_v16i8>;
2799 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Punpcklwd, bc_v8i16>;
2800 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Punpckldq, bc_v4i32>;
2802 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2803 /// knew to collapse (bitconvert VT to VT) into its operand.
2804 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2805 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2806 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2808 (v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)))]>;
2809 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2810 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2811 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2813 (v2i64 (X86Punpcklqdq VR128:$src1,
2814 (memopv2i64 addr:$src2))))]>;
2816 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Punpckhbw, bc_v16i8>;
2817 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Punpckhwd, bc_v8i16>;
2818 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Punpckhdq, bc_v4i32>;
2820 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2821 /// knew to collapse (bitconvert VT to VT) into its operand.
2822 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2823 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2824 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2826 (v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)))]>;
2827 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2828 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2829 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2831 (v2i64 (X86Punpckhqdq VR128:$src1,
2832 (memopv2i64 addr:$src2))))]>;
2835 } // ExeDomain = SSEPackedInt
2837 //===---------------------------------------------------------------------===//
2838 // SSE2 - Packed Integer Extract and Insert
2839 //===---------------------------------------------------------------------===//
2841 let ExeDomain = SSEPackedInt in {
2842 multiclass sse2_pinsrw<bit Is2Addr = 1> {
2843 def rri : Ii8<0xC4, MRMSrcReg,
2844 (outs VR128:$dst), (ins VR128:$src1,
2845 GR32:$src2, i32i8imm:$src3),
2847 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2848 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2850 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2851 def rmi : Ii8<0xC4, MRMSrcMem,
2852 (outs VR128:$dst), (ins VR128:$src1,
2853 i16mem:$src2, i32i8imm:$src3),
2855 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2856 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2858 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2863 let Predicates = [HasAVX] in
2864 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
2865 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2866 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2867 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2868 imm:$src2))]>, OpSize, VEX;
2869 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2870 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2871 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2872 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2876 let Predicates = [HasAVX] in {
2877 defm VPINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
2878 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
2879 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2880 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2881 []>, OpSize, VEX_4V;
2884 let Constraints = "$src1 = $dst" in
2885 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
2887 } // ExeDomain = SSEPackedInt
2889 //===---------------------------------------------------------------------===//
2890 // SSE2 - Packed Mask Creation
2891 //===---------------------------------------------------------------------===//
2893 let ExeDomain = SSEPackedInt in {
2895 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2896 "pmovmskb\t{$src, $dst|$dst, $src}",
2897 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
2898 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2899 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
2900 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2901 "pmovmskb\t{$src, $dst|$dst, $src}",
2902 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2904 } // ExeDomain = SSEPackedInt
2906 //===---------------------------------------------------------------------===//
2907 // SSE2 - Conditional Store
2908 //===---------------------------------------------------------------------===//
2910 let ExeDomain = SSEPackedInt in {
2913 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
2914 (ins VR128:$src, VR128:$mask),
2915 "maskmovdqu\t{$mask, $src|$src, $mask}",
2916 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
2918 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
2919 (ins VR128:$src, VR128:$mask),
2920 "maskmovdqu\t{$mask, $src|$src, $mask}",
2921 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
2924 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2925 "maskmovdqu\t{$mask, $src|$src, $mask}",
2926 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2928 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2929 "maskmovdqu\t{$mask, $src|$src, $mask}",
2930 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2932 } // ExeDomain = SSEPackedInt
2934 //===---------------------------------------------------------------------===//
2935 // SSE2 - Move Doubleword
2936 //===---------------------------------------------------------------------===//
2938 //===---------------------------------------------------------------------===//
2939 // Move Int Doubleword to Packed Double Int
2941 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2942 "movd\t{$src, $dst|$dst, $src}",
2944 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
2945 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2946 "movd\t{$src, $dst|$dst, $src}",
2948 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
2950 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2951 "mov{d|q}\t{$src, $dst|$dst, $src}",
2953 (v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
2954 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2955 "mov{d|q}\t{$src, $dst|$dst, $src}",
2956 [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
2958 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2959 "movd\t{$src, $dst|$dst, $src}",
2961 (v4i32 (scalar_to_vector GR32:$src)))]>;
2962 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2963 "movd\t{$src, $dst|$dst, $src}",
2965 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2966 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2967 "mov{d|q}\t{$src, $dst|$dst, $src}",
2969 (v2i64 (scalar_to_vector GR64:$src)))]>;
2970 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2971 "mov{d|q}\t{$src, $dst|$dst, $src}",
2972 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2974 //===---------------------------------------------------------------------===//
2975 // Move Int Doubleword to Single Scalar
2977 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2978 "movd\t{$src, $dst|$dst, $src}",
2979 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
2981 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2982 "movd\t{$src, $dst|$dst, $src}",
2983 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
2985 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2986 "movd\t{$src, $dst|$dst, $src}",
2987 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2989 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2990 "movd\t{$src, $dst|$dst, $src}",
2991 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2993 //===---------------------------------------------------------------------===//
2994 // Move Packed Doubleword Int to Packed Double Int
2996 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2997 "movd\t{$src, $dst|$dst, $src}",
2998 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
3000 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
3001 (ins i32mem:$dst, VR128:$src),
3002 "movd\t{$src, $dst|$dst, $src}",
3003 [(store (i32 (vector_extract (v4i32 VR128:$src),
3004 (iPTR 0))), addr:$dst)]>, VEX;
3005 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
3006 "movd\t{$src, $dst|$dst, $src}",
3007 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
3009 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
3010 "movd\t{$src, $dst|$dst, $src}",
3011 [(store (i32 (vector_extract (v4i32 VR128:$src),
3012 (iPTR 0))), addr:$dst)]>;
3014 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3015 "mov{d|q}\t{$src, $dst|$dst, $src}",
3016 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
3018 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
3019 "movq\t{$src, $dst|$dst, $src}",
3020 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
3022 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
3023 "mov{d|q}\t{$src, $dst|$dst, $src}",
3024 [(set GR64:$dst, (bitconvert FR64:$src))]>;
3025 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
3026 "movq\t{$src, $dst|$dst, $src}",
3027 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
3029 //===---------------------------------------------------------------------===//
3030 // Move Scalar Single to Double Int
3032 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
3033 "movd\t{$src, $dst|$dst, $src}",
3034 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
3035 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
3036 "movd\t{$src, $dst|$dst, $src}",
3037 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
3038 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
3039 "movd\t{$src, $dst|$dst, $src}",
3040 [(set GR32:$dst, (bitconvert FR32:$src))]>;
3041 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
3042 "movd\t{$src, $dst|$dst, $src}",
3043 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
3045 //===---------------------------------------------------------------------===//
3046 // Patterns and instructions to describe movd/movq to XMM register zero-extends
3048 let AddedComplexity = 15 in {
3049 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3050 "movd\t{$src, $dst|$dst, $src}",
3051 [(set VR128:$dst, (v4i32 (X86vzmovl
3052 (v4i32 (scalar_to_vector GR32:$src)))))]>,
3054 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3055 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3056 [(set VR128:$dst, (v2i64 (X86vzmovl
3057 (v2i64 (scalar_to_vector GR64:$src)))))]>,
3060 let AddedComplexity = 15 in {
3061 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3062 "movd\t{$src, $dst|$dst, $src}",
3063 [(set VR128:$dst, (v4i32 (X86vzmovl
3064 (v4i32 (scalar_to_vector GR32:$src)))))]>;
3065 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3066 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3067 [(set VR128:$dst, (v2i64 (X86vzmovl
3068 (v2i64 (scalar_to_vector GR64:$src)))))]>;
3071 let AddedComplexity = 20 in {
3072 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3073 "movd\t{$src, $dst|$dst, $src}",
3075 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3076 (loadi32 addr:$src))))))]>,
3078 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3079 "movd\t{$src, $dst|$dst, $src}",
3081 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3082 (loadi32 addr:$src))))))]>;
3084 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
3085 (MOVZDI2PDIrm addr:$src)>;
3086 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3087 (MOVZDI2PDIrm addr:$src)>;
3088 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3089 (MOVZDI2PDIrm addr:$src)>;
3092 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3093 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3094 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3095 (v4i32 (scalar_to_vector GR32:$src)), (i32 0)))),
3096 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
3097 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3098 (v2i64 (scalar_to_vector GR64:$src)), (i32 0)))),
3099 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
3101 // These are the correct encodings of the instructions so that we know how to
3102 // read correct assembly, even though we continue to emit the wrong ones for
3103 // compatibility with Darwin's buggy assembler.
3104 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3105 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
3106 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3107 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
3108 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3109 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
3110 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3111 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
3112 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3113 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
3114 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3115 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
3117 //===---------------------------------------------------------------------===//
3118 // SSE2 - Move Quadword
3119 //===---------------------------------------------------------------------===//
3121 //===---------------------------------------------------------------------===//
3122 // Move Quadword Int to Packed Quadword Int
3124 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3125 "vmovq\t{$src, $dst|$dst, $src}",
3127 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3128 VEX, Requires<[HasAVX]>;
3129 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3130 "movq\t{$src, $dst|$dst, $src}",
3132 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3133 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
3135 //===---------------------------------------------------------------------===//
3136 // Move Packed Quadword Int to Quadword Int
3138 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3139 "movq\t{$src, $dst|$dst, $src}",
3140 [(store (i64 (vector_extract (v2i64 VR128:$src),
3141 (iPTR 0))), addr:$dst)]>, VEX;
3142 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3143 "movq\t{$src, $dst|$dst, $src}",
3144 [(store (i64 (vector_extract (v2i64 VR128:$src),
3145 (iPTR 0))), addr:$dst)]>;
3147 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
3148 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
3150 //===---------------------------------------------------------------------===//
3151 // Store / copy lower 64-bits of a XMM register.
3153 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3154 "movq\t{$src, $dst|$dst, $src}",
3155 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
3156 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3157 "movq\t{$src, $dst|$dst, $src}",
3158 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
3160 let AddedComplexity = 20 in
3161 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3162 "vmovq\t{$src, $dst|$dst, $src}",
3164 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3165 (loadi64 addr:$src))))))]>,
3166 XS, VEX, Requires<[HasAVX]>;
3168 let AddedComplexity = 20 in {
3169 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3170 "movq\t{$src, $dst|$dst, $src}",
3172 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3173 (loadi64 addr:$src))))))]>,
3174 XS, Requires<[HasSSE2]>;
3176 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3177 (MOVZQI2PQIrm addr:$src)>;
3178 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
3179 (MOVZQI2PQIrm addr:$src)>;
3180 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
3183 //===---------------------------------------------------------------------===//
3184 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
3185 // IA32 document. movq xmm1, xmm2 does clear the high bits.
3187 let AddedComplexity = 15 in
3188 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3189 "vmovq\t{$src, $dst|$dst, $src}",
3190 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3191 XS, VEX, Requires<[HasAVX]>;
3192 let AddedComplexity = 15 in
3193 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3194 "movq\t{$src, $dst|$dst, $src}",
3195 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3196 XS, Requires<[HasSSE2]>;
3198 let AddedComplexity = 20 in
3199 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3200 "vmovq\t{$src, $dst|$dst, $src}",
3201 [(set VR128:$dst, (v2i64 (X86vzmovl
3202 (loadv2i64 addr:$src))))]>,
3203 XS, VEX, Requires<[HasAVX]>;
3204 let AddedComplexity = 20 in {
3205 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3206 "movq\t{$src, $dst|$dst, $src}",
3207 [(set VR128:$dst, (v2i64 (X86vzmovl
3208 (loadv2i64 addr:$src))))]>,
3209 XS, Requires<[HasSSE2]>;
3211 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
3212 (MOVZPQILo2PQIrm addr:$src)>;
3215 // Instructions to match in the assembler
3216 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3217 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3218 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3219 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3220 // Recognize "movd" with GR64 destination, but encode as a "movq"
3221 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3222 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3224 // Instructions for the disassembler
3225 // xr = XMM register
3228 let Predicates = [HasAVX] in
3229 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3230 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
3231 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3232 "movq\t{$src, $dst|$dst, $src}", []>, XS;
3234 //===---------------------------------------------------------------------===//
3235 // SSE2 - Misc Instructions
3236 //===---------------------------------------------------------------------===//
3239 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3240 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3241 TB, Requires<[HasSSE2]>;
3243 // Load, store, and memory fence
3244 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3245 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3246 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3247 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3248 def : Pat<(X86LFence), (LFENCE)>;
3249 def : Pat<(X86MFence), (MFENCE)>;
3252 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3253 // was introduced with SSE2, it's backward compatible.
3254 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3256 // Alias instructions that map zero vector to pxor / xorp* for sse.
3257 // We set canFoldAsLoad because this can be converted to a constant-pool
3258 // load of an all-ones value if folding it would be beneficial.
3259 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
3260 // JIT implementation, it does not expand the instructions below like
3261 // X86MCInstLower does.
3262 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3263 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
3264 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3265 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
3266 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3267 isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in
3268 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3269 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
3271 //===---------------------------------------------------------------------===//
3272 // SSE3 - Conversion Instructions
3273 //===---------------------------------------------------------------------===//
3275 // Convert Packed Double FP to Packed DW Integers
3276 let Predicates = [HasAVX] in {
3277 // The assembler can recognize rr 256-bit instructions by seeing a ymm
3278 // register, but the same isn't true when using memory operands instead.
3279 // Provide other assembly rr and rm forms to address this explicitly.
3280 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3281 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3282 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3283 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3286 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3287 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3288 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3289 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3292 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3293 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
3294 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
3295 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
3298 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3299 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3300 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3301 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3303 // Convert Packed DW Integers to Packed Double FP
3304 let Predicates = [HasAVX] in {
3305 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3306 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3307 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3308 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3309 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
3310 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3311 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
3312 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3315 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3316 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3317 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3318 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3320 // AVX 256-bit register conversion intrinsics
3321 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
3322 (VCVTDQ2PDYrr VR128:$src)>;
3323 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
3324 (VCVTDQ2PDYrm addr:$src)>;
3326 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
3327 (VCVTPD2DQYrr VR256:$src)>;
3328 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
3329 (VCVTPD2DQYrm addr:$src)>;
3331 //===---------------------------------------------------------------------===//
3332 // SSE3 - Move Instructions
3333 //===---------------------------------------------------------------------===//
3335 //===---------------------------------------------------------------------===//
3336 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3338 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3339 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3340 X86MemOperand x86memop> {
3341 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3342 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3343 [(set RC:$dst, (vt (OpNode RC:$src)))]>;
3344 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3345 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3346 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>;
3349 let Predicates = [HasAVX] in {
3350 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3351 v4f32, VR128, memopv4f32, f128mem>, VEX;
3352 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3353 v4f32, VR128, memopv4f32, f128mem>, VEX;
3354 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3355 v8f32, VR256, memopv8f32, f256mem>, VEX;
3356 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3357 v8f32, VR256, memopv8f32, f256mem>, VEX;
3359 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
3360 memopv4f32, f128mem>;
3361 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
3362 memopv4f32, f128mem>;
3364 let Predicates = [HasSSE3] in {
3365 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
3366 (MOVSHDUPrr VR128:$src)>;
3367 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
3368 (MOVSHDUPrm addr:$src)>;
3369 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
3370 (MOVSLDUPrr VR128:$src)>;
3371 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
3372 (MOVSLDUPrm addr:$src)>;
3375 let Predicates = [HasAVX] in {
3376 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
3377 (VMOVSHDUPrr VR128:$src)>;
3378 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
3379 (VMOVSHDUPrm addr:$src)>;
3380 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
3381 (VMOVSLDUPrr VR128:$src)>;
3382 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
3383 (VMOVSLDUPrm addr:$src)>;
3384 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
3385 (VMOVSHDUPYrr VR256:$src)>;
3386 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
3387 (VMOVSHDUPYrm addr:$src)>;
3388 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
3389 (VMOVSLDUPYrr VR256:$src)>;
3390 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
3391 (VMOVSLDUPYrm addr:$src)>;
3394 //===---------------------------------------------------------------------===//
3395 // Replicate Double FP - MOVDDUP
3397 multiclass sse3_replicate_dfp<string OpcodeStr> {
3398 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3399 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3400 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
3401 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
3402 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3404 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
3408 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
3409 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3410 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3412 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3413 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3417 let Predicates = [HasAVX] in {
3418 // FIXME: Merge above classes when we have patterns for the ymm version
3419 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
3420 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
3422 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
3424 // Move Unaligned Integer
3425 let Predicates = [HasAVX] in {
3426 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3427 "vlddqu\t{$src, $dst|$dst, $src}",
3428 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
3429 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3430 "vlddqu\t{$src, $dst|$dst, $src}",
3431 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
3433 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3434 "lddqu\t{$src, $dst|$dst, $src}",
3435 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
3437 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
3439 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3441 // Several Move patterns
3442 let AddedComplexity = 5 in {
3443 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
3444 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3445 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
3446 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3447 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
3448 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3449 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
3450 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3453 //===---------------------------------------------------------------------===//
3454 // SSE3 - Arithmetic
3455 //===---------------------------------------------------------------------===//
3457 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
3458 X86MemOperand x86memop, bit Is2Addr = 1> {
3459 def rr : I<0xD0, MRMSrcReg,
3460 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3462 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3463 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3464 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
3465 def rm : I<0xD0, MRMSrcMem,
3466 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3468 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3469 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3470 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
3473 let Predicates = [HasAVX],
3474 ExeDomain = SSEPackedDouble in {
3475 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
3476 f128mem, 0>, TB, XD, VEX_4V;
3477 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
3478 f128mem, 0>, TB, OpSize, VEX_4V;
3479 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
3480 f256mem, 0>, TB, XD, VEX_4V;
3481 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
3482 f256mem, 0>, TB, OpSize, VEX_4V;
3484 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
3485 ExeDomain = SSEPackedDouble in {
3486 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
3488 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
3489 f128mem>, TB, OpSize;
3492 //===---------------------------------------------------------------------===//
3493 // SSE3 Instructions
3494 //===---------------------------------------------------------------------===//
3497 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3498 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3499 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3501 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3502 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3503 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3505 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3507 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3508 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3509 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3511 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3512 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3513 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3515 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3516 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3517 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3519 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3521 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3522 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3523 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3526 let Predicates = [HasAVX] in {
3527 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
3528 int_x86_sse3_hadd_ps, 0>, VEX_4V;
3529 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
3530 int_x86_sse3_hadd_pd, 0>, VEX_4V;
3531 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
3532 int_x86_sse3_hsub_ps, 0>, VEX_4V;
3533 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
3534 int_x86_sse3_hsub_pd, 0>, VEX_4V;
3535 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
3536 int_x86_avx_hadd_ps_256, 0>, VEX_4V;
3537 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
3538 int_x86_avx_hadd_pd_256, 0>, VEX_4V;
3539 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
3540 int_x86_avx_hsub_ps_256, 0>, VEX_4V;
3541 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
3542 int_x86_avx_hsub_pd_256, 0>, VEX_4V;
3545 let Constraints = "$src1 = $dst" in {
3546 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
3547 int_x86_sse3_hadd_ps>;
3548 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
3549 int_x86_sse3_hadd_pd>;
3550 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
3551 int_x86_sse3_hsub_ps>;
3552 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
3553 int_x86_sse3_hsub_pd>;
3556 //===---------------------------------------------------------------------===//
3557 // SSSE3 - Packed Absolute Instructions
3558 //===---------------------------------------------------------------------===//
3561 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
3562 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
3563 PatFrag mem_frag128, Intrinsic IntId128> {
3564 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3566 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3567 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3570 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3572 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3575 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
3578 let Predicates = [HasAVX] in {
3579 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
3580 int_x86_ssse3_pabs_b_128>, VEX;
3581 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
3582 int_x86_ssse3_pabs_w_128>, VEX;
3583 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
3584 int_x86_ssse3_pabs_d_128>, VEX;
3587 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
3588 int_x86_ssse3_pabs_b_128>;
3589 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
3590 int_x86_ssse3_pabs_w_128>;
3591 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
3592 int_x86_ssse3_pabs_d_128>;
3594 //===---------------------------------------------------------------------===//
3595 // SSSE3 - Packed Binary Operator Instructions
3596 //===---------------------------------------------------------------------===//
3598 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
3599 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
3600 PatFrag mem_frag128, Intrinsic IntId128,
3602 let isCommutable = 1 in
3603 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3604 (ins VR128:$src1, VR128:$src2),
3606 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3607 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3608 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3610 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3611 (ins VR128:$src1, i128mem:$src2),
3613 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3614 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3616 (IntId128 VR128:$src1,
3617 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3620 let Predicates = [HasAVX] in {
3621 let isCommutable = 0 in {
3622 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
3623 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
3624 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
3625 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
3626 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
3627 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
3628 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
3629 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
3630 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
3631 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
3632 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
3633 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
3634 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
3635 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
3636 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
3637 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
3638 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
3639 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
3640 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
3641 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
3642 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
3643 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
3645 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
3646 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
3649 // None of these have i8 immediate fields.
3650 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
3651 let isCommutable = 0 in {
3652 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
3653 int_x86_ssse3_phadd_w_128>;
3654 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
3655 int_x86_ssse3_phadd_d_128>;
3656 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
3657 int_x86_ssse3_phadd_sw_128>;
3658 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
3659 int_x86_ssse3_phsub_w_128>;
3660 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
3661 int_x86_ssse3_phsub_d_128>;
3662 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
3663 int_x86_ssse3_phsub_sw_128>;
3664 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
3665 int_x86_ssse3_pmadd_ub_sw_128>;
3666 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
3667 int_x86_ssse3_pshuf_b_128>;
3668 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
3669 int_x86_ssse3_psign_b_128>;
3670 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
3671 int_x86_ssse3_psign_w_128>;
3672 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
3673 int_x86_ssse3_psign_d_128>;
3675 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
3676 int_x86_ssse3_pmul_hr_sw_128>;
3679 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
3680 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
3681 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
3682 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
3684 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
3685 (PSIGNBrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3686 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
3687 (PSIGNWrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3688 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
3689 (PSIGNDrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3691 //===---------------------------------------------------------------------===//
3692 // SSSE3 - Packed Align Instruction Patterns
3693 //===---------------------------------------------------------------------===//
3695 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
3696 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
3697 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3699 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3701 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3703 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
3704 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3706 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3708 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3712 let Predicates = [HasAVX] in
3713 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
3714 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
3715 defm PALIGN : ssse3_palign<"palignr">;
3717 let Predicates = [HasSSSE3] in {
3718 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3719 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3720 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3721 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3722 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3723 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3724 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3725 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3728 let Predicates = [HasAVX] in {
3729 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3730 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3731 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3732 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3733 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3734 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3735 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3736 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3739 //===---------------------------------------------------------------------===//
3740 // SSSE3 Misc Instructions
3741 //===---------------------------------------------------------------------===//
3743 // Thread synchronization
3744 let usesCustomInserter = 1 in {
3745 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
3746 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
3747 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
3748 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
3751 let Uses = [EAX, ECX, EDX] in
3752 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
3753 Requires<[HasSSE3]>;
3754 let Uses = [ECX, EAX] in
3755 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
3756 Requires<[HasSSE3]>;
3758 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
3759 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
3761 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
3762 Requires<[In32BitMode]>;
3763 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
3764 Requires<[In64BitMode]>;
3766 //===---------------------------------------------------------------------===//
3767 // Non-Instruction Patterns
3768 //===---------------------------------------------------------------------===//
3770 // extload f32 -> f64. This matches load+fextend because we have a hack in
3771 // the isel (PreprocessForFPConvert) that can introduce loads after dag
3773 // Since these loads aren't folded into the fextend, we have to match it
3775 let Predicates = [HasSSE2] in
3776 def : Pat<(fextend (loadf32 addr:$src)),
3777 (CVTSS2SDrm addr:$src)>;
3779 // Bitcasts between 128-bit vector types. Return the original type since
3780 // no instruction is needed for the conversion
3781 let Predicates = [HasXMMInt] in {
3782 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
3783 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
3784 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
3785 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
3786 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
3787 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
3788 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
3789 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3790 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3791 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3792 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3793 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3794 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3795 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3796 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3797 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3798 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3799 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3800 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3801 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3802 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3803 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3804 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3805 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3806 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3807 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3808 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3809 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3810 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3811 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3814 // Bitcasts between 256-bit vector types. Return the original type since
3815 // no instruction is needed for the conversion
3816 let Predicates = [HasAVX] in {
3817 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
3818 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
3819 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
3820 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
3821 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
3822 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
3823 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
3824 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
3825 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
3826 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
3827 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
3828 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
3829 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
3830 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
3831 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
3832 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
3833 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
3834 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
3835 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
3836 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
3837 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
3838 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
3839 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
3840 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
3841 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
3842 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
3843 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
3844 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
3845 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
3846 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
3849 // Move scalar to XMM zero-extended
3850 // movd to XMM register zero-extends
3851 let AddedComplexity = 15 in {
3852 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3853 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3854 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
3855 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3856 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
3857 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3858 (MOVSSrr (v4f32 (V_SET0PS)),
3859 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
3860 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3861 (MOVSSrr (v4i32 (V_SET0PI)),
3862 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
3865 // Splat v2f64 / v2i64
3866 let AddedComplexity = 10 in {
3867 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3868 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3869 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3870 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3873 // Special unary SHUFPSrri case.
3874 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3875 (SHUFPSrri VR128:$src1, VR128:$src1,
3876 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3877 let AddedComplexity = 5 in
3878 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3879 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3880 Requires<[HasSSE2]>;
3881 // Special unary SHUFPDrri case.
3882 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3883 (SHUFPDrri VR128:$src1, VR128:$src1,
3884 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3885 Requires<[HasSSE2]>;
3886 // Special unary SHUFPDrri case.
3887 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3888 (SHUFPDrri VR128:$src1, VR128:$src1,
3889 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3890 Requires<[HasSSE2]>;
3891 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3892 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3893 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3894 Requires<[HasSSE2]>;
3896 // Special binary v4i32 shuffle cases with SHUFPS.
3897 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3898 (SHUFPSrri VR128:$src1, VR128:$src2,
3899 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3900 Requires<[HasSSE2]>;
3901 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3902 (SHUFPSrmi VR128:$src1, addr:$src2,
3903 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3904 Requires<[HasSSE2]>;
3905 // Special binary v2i64 shuffle cases using SHUFPDrri.
3906 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3907 (SHUFPDrri VR128:$src1, VR128:$src2,
3908 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3909 Requires<[HasSSE2]>;
3911 let AddedComplexity = 20 in {
3912 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3913 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3914 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3916 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3917 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3918 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3920 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3921 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3922 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3923 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3924 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3927 let AddedComplexity = 20 in {
3928 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3929 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3930 (MOVLPSrm VR128:$src1, addr:$src2)>;
3931 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3932 (MOVLPDrm VR128:$src1, addr:$src2)>;
3933 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3934 (MOVLPSrm VR128:$src1, addr:$src2)>;
3935 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3936 (MOVLPDrm VR128:$src1, addr:$src2)>;
3939 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3940 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3941 (MOVLPSmr addr:$src1, VR128:$src2)>;
3942 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3943 (MOVLPDmr addr:$src1, VR128:$src2)>;
3944 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3946 (MOVLPSmr addr:$src1, VR128:$src2)>;
3947 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3948 (MOVLPDmr addr:$src1, VR128:$src2)>;
3950 let AddedComplexity = 15 in {
3951 // Setting the lowest element in the vector.
3952 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3953 (MOVSSrr (v4i32 VR128:$src1),
3954 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3955 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3956 (MOVSDrr (v2i64 VR128:$src1),
3957 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
3959 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3960 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3961 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3962 Requires<[HasSSE2]>;
3963 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3964 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3965 Requires<[HasSSE2]>;
3968 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3969 // fall back to this for SSE1)
3970 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3971 (SHUFPSrri VR128:$src2, VR128:$src1,
3972 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3974 // Set lowest element and zero upper elements.
3975 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3976 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3978 // Use movaps / movups for SSE integer load / store (one byte shorter).
3979 // The instructions selected below are then converted to MOVDQA/MOVDQU
3980 // during the SSE domain pass.
3981 let Predicates = [HasSSE1] in {
3982 def : Pat<(alignedloadv4i32 addr:$src),
3983 (MOVAPSrm addr:$src)>;
3984 def : Pat<(loadv4i32 addr:$src),
3985 (MOVUPSrm addr:$src)>;
3986 def : Pat<(alignedloadv2i64 addr:$src),
3987 (MOVAPSrm addr:$src)>;
3988 def : Pat<(loadv2i64 addr:$src),
3989 (MOVUPSrm addr:$src)>;
3991 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3992 (MOVAPSmr addr:$dst, VR128:$src)>;
3993 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3994 (MOVAPSmr addr:$dst, VR128:$src)>;
3995 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3996 (MOVAPSmr addr:$dst, VR128:$src)>;
3997 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3998 (MOVAPSmr addr:$dst, VR128:$src)>;
3999 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
4000 (MOVUPSmr addr:$dst, VR128:$src)>;
4001 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
4002 (MOVUPSmr addr:$dst, VR128:$src)>;
4003 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
4004 (MOVUPSmr addr:$dst, VR128:$src)>;
4005 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
4006 (MOVUPSmr addr:$dst, VR128:$src)>;
4009 // Use vmovaps/vmovups for AVX integer load/store.
4010 let Predicates = [HasAVX] in {
4011 // 128-bit load/store
4012 def : Pat<(alignedloadv4i32 addr:$src),
4013 (VMOVAPSrm addr:$src)>;
4014 def : Pat<(loadv4i32 addr:$src),
4015 (VMOVUPSrm addr:$src)>;
4016 def : Pat<(alignedloadv2i64 addr:$src),
4017 (VMOVAPSrm addr:$src)>;
4018 def : Pat<(loadv2i64 addr:$src),
4019 (VMOVUPSrm addr:$src)>;
4021 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
4022 (VMOVAPSmr addr:$dst, VR128:$src)>;
4023 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
4024 (VMOVAPSmr addr:$dst, VR128:$src)>;
4025 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
4026 (VMOVAPSmr addr:$dst, VR128:$src)>;
4027 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
4028 (VMOVAPSmr addr:$dst, VR128:$src)>;
4029 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
4030 (VMOVUPSmr addr:$dst, VR128:$src)>;
4031 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
4032 (VMOVUPSmr addr:$dst, VR128:$src)>;
4033 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
4034 (VMOVUPSmr addr:$dst, VR128:$src)>;
4035 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
4036 (VMOVUPSmr addr:$dst, VR128:$src)>;
4038 // 256-bit load/store
4039 def : Pat<(alignedloadv4i64 addr:$src),
4040 (VMOVAPSYrm addr:$src)>;
4041 def : Pat<(loadv4i64 addr:$src),
4042 (VMOVUPSYrm addr:$src)>;
4043 def : Pat<(alignedloadv8i32 addr:$src),
4044 (VMOVAPSYrm addr:$src)>;
4045 def : Pat<(loadv8i32 addr:$src),
4046 (VMOVUPSYrm addr:$src)>;
4047 def : Pat<(alignedstore (v4i64 VR256:$src), addr:$dst),
4048 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4049 def : Pat<(alignedstore (v8i32 VR256:$src), addr:$dst),
4050 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4051 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
4052 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4053 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
4054 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4057 //===----------------------------------------------------------------------===//
4058 // SSE4.1 - Packed Move with Sign/Zero Extend
4059 //===----------------------------------------------------------------------===//
4061 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4062 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4063 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4064 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4066 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4067 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4069 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
4073 let Predicates = [HasAVX] in {
4074 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
4076 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
4078 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
4080 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
4082 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
4084 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
4088 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
4089 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
4090 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
4091 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
4092 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
4093 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
4095 // Common patterns involving scalar load.
4096 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
4097 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4098 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
4099 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4101 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
4102 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4103 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
4104 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4106 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
4107 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4108 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
4109 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4111 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
4112 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4113 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
4114 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4116 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
4117 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4118 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
4119 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4121 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
4122 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4123 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
4124 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4127 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4128 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4129 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4130 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4132 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4133 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4135 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
4139 let Predicates = [HasAVX] in {
4140 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
4142 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
4144 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
4146 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
4150 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
4151 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
4152 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
4153 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
4155 // Common patterns involving scalar load
4156 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
4157 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
4158 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
4159 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
4161 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
4162 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
4163 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
4164 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
4167 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4168 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4169 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4170 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4172 // Expecting a i16 load any extended to i32 value.
4173 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
4174 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4175 [(set VR128:$dst, (IntId (bitconvert
4176 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
4180 let Predicates = [HasAVX] in {
4181 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
4183 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
4186 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
4187 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
4189 // Common patterns involving scalar load
4190 def : Pat<(int_x86_sse41_pmovsxbq
4191 (bitconvert (v4i32 (X86vzmovl
4192 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4193 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
4195 def : Pat<(int_x86_sse41_pmovzxbq
4196 (bitconvert (v4i32 (X86vzmovl
4197 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4198 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
4200 //===----------------------------------------------------------------------===//
4201 // SSE4.1 - Extract Instructions
4202 //===----------------------------------------------------------------------===//
4204 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
4205 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
4206 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4207 (ins VR128:$src1, i32i8imm:$src2),
4208 !strconcat(OpcodeStr,
4209 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4210 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
4212 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4213 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
4214 !strconcat(OpcodeStr,
4215 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4218 // There's an AssertZext in the way of writing the store pattern
4219 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4222 let Predicates = [HasAVX] in {
4223 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
4224 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
4225 (ins VR128:$src1, i32i8imm:$src2),
4226 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
4229 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
4232 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
4233 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
4234 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4235 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
4236 !strconcat(OpcodeStr,
4237 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4240 // There's an AssertZext in the way of writing the store pattern
4241 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4244 let Predicates = [HasAVX] in
4245 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
4247 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
4250 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4251 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
4252 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4253 (ins VR128:$src1, i32i8imm:$src2),
4254 !strconcat(OpcodeStr,
4255 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4257 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
4258 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4259 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
4260 !strconcat(OpcodeStr,
4261 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4262 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
4263 addr:$dst)]>, OpSize;
4266 let Predicates = [HasAVX] in
4267 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
4269 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
4271 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4272 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
4273 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
4274 (ins VR128:$src1, i32i8imm:$src2),
4275 !strconcat(OpcodeStr,
4276 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4278 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
4279 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4280 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
4281 !strconcat(OpcodeStr,
4282 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4283 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
4284 addr:$dst)]>, OpSize, REX_W;
4287 let Predicates = [HasAVX] in
4288 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
4290 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
4292 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
4294 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
4295 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4296 (ins VR128:$src1, i32i8imm:$src2),
4297 !strconcat(OpcodeStr,
4298 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4300 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
4302 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4303 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
4304 !strconcat(OpcodeStr,
4305 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4306 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
4307 addr:$dst)]>, OpSize;
4310 let Predicates = [HasAVX] in {
4311 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
4312 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
4313 (ins VR128:$src1, i32i8imm:$src2),
4314 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
4317 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
4319 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
4320 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
4323 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
4324 Requires<[HasSSE41]>;
4326 //===----------------------------------------------------------------------===//
4327 // SSE4.1 - Insert Instructions
4328 //===----------------------------------------------------------------------===//
4330 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
4331 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4332 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4334 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4336 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4338 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
4339 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4340 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
4342 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4344 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4346 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
4347 imm:$src3))]>, OpSize;
4350 let Predicates = [HasAVX] in
4351 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
4352 let Constraints = "$src1 = $dst" in
4353 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
4355 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
4356 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4357 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4359 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4361 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4363 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
4365 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4366 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
4368 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4370 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4372 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
4373 imm:$src3)))]>, OpSize;
4376 let Predicates = [HasAVX] in
4377 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
4378 let Constraints = "$src1 = $dst" in
4379 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
4381 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
4382 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4383 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4385 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4387 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4389 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
4391 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4392 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
4394 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4396 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4398 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
4399 imm:$src3)))]>, OpSize;
4402 let Predicates = [HasAVX] in
4403 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
4404 let Constraints = "$src1 = $dst" in
4405 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
4407 // insertps has a few different modes, there's the first two here below which
4408 // are optimized inserts that won't zero arbitrary elements in the destination
4409 // vector. The next one matches the intrinsic and could zero arbitrary elements
4410 // in the target vector.
4411 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
4412 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4413 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
4415 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4417 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4419 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
4421 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4422 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
4424 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4426 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4428 (X86insrtps VR128:$src1,
4429 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
4430 imm:$src3))]>, OpSize;
4433 let Constraints = "$src1 = $dst" in
4434 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
4435 let Predicates = [HasAVX] in
4436 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
4438 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4439 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4441 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4442 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4443 Requires<[HasSSE41]>;
4445 //===----------------------------------------------------------------------===//
4446 // SSE4.1 - Round Instructions
4447 //===----------------------------------------------------------------------===//
4449 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4450 X86MemOperand x86memop, RegisterClass RC,
4451 PatFrag mem_frag32, PatFrag mem_frag64,
4452 Intrinsic V4F32Int, Intrinsic V2F64Int> {
4453 // Intrinsic operation, reg.
4454 // Vector intrinsic operation, reg
4455 def PSr : SS4AIi8<opcps, MRMSrcReg,
4456 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4457 !strconcat(OpcodeStr,
4458 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4459 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
4462 // Vector intrinsic operation, mem
4463 def PSm : Ii8<opcps, MRMSrcMem,
4464 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4465 !strconcat(OpcodeStr,
4466 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4468 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4470 Requires<[HasSSE41]>;
4472 // Vector intrinsic operation, reg
4473 def PDr : SS4AIi8<opcpd, MRMSrcReg,
4474 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4475 !strconcat(OpcodeStr,
4476 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4477 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
4480 // Vector intrinsic operation, mem
4481 def PDm : SS4AIi8<opcpd, MRMSrcMem,
4482 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4483 !strconcat(OpcodeStr,
4484 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4486 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4490 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
4491 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
4492 // Intrinsic operation, reg.
4493 // Vector intrinsic operation, reg
4494 def PSr_AVX : SS4AIi8<opcps, MRMSrcReg,
4495 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4496 !strconcat(OpcodeStr,
4497 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4500 // Vector intrinsic operation, mem
4501 def PSm_AVX : Ii8<opcps, MRMSrcMem,
4502 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4503 !strconcat(OpcodeStr,
4504 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4505 []>, TA, OpSize, Requires<[HasSSE41]>;
4507 // Vector intrinsic operation, reg
4508 def PDr_AVX : SS4AIi8<opcpd, MRMSrcReg,
4509 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4510 !strconcat(OpcodeStr,
4511 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4514 // Vector intrinsic operation, mem
4515 def PDm_AVX : SS4AIi8<opcpd, MRMSrcMem,
4516 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4517 !strconcat(OpcodeStr,
4518 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4522 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4525 Intrinsic F64Int, bit Is2Addr = 1> {
4526 // Intrinsic operation, reg.
4527 def SSr : SS4AIi8<opcss, MRMSrcReg,
4528 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4530 !strconcat(OpcodeStr,
4531 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4532 !strconcat(OpcodeStr,
4533 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4534 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4537 // Intrinsic operation, mem.
4538 def SSm : SS4AIi8<opcss, MRMSrcMem,
4539 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4541 !strconcat(OpcodeStr,
4542 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4543 !strconcat(OpcodeStr,
4544 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4546 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
4549 // Intrinsic operation, reg.
4550 def SDr : SS4AIi8<opcsd, MRMSrcReg,
4551 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4553 !strconcat(OpcodeStr,
4554 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4555 !strconcat(OpcodeStr,
4556 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4557 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4560 // Intrinsic operation, mem.
4561 def SDm : SS4AIi8<opcsd, MRMSrcMem,
4562 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4564 !strconcat(OpcodeStr,
4565 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4566 !strconcat(OpcodeStr,
4567 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4569 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
4573 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
4575 // Intrinsic operation, reg.
4576 def SSr_AVX : SS4AIi8<opcss, MRMSrcReg,
4577 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4578 !strconcat(OpcodeStr,
4579 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4582 // Intrinsic operation, mem.
4583 def SSm_AVX : SS4AIi8<opcss, MRMSrcMem,
4584 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4585 !strconcat(OpcodeStr,
4586 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4589 // Intrinsic operation, reg.
4590 def SDr_AVX : SS4AIi8<opcsd, MRMSrcReg,
4591 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4592 !strconcat(OpcodeStr,
4593 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4596 // Intrinsic operation, mem.
4597 def SDm_AVX : SS4AIi8<opcsd, MRMSrcMem,
4598 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4599 !strconcat(OpcodeStr,
4600 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4604 // FP round - roundss, roundps, roundsd, roundpd
4605 let Predicates = [HasAVX] in {
4607 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
4608 memopv4f32, memopv2f64,
4609 int_x86_sse41_round_ps,
4610 int_x86_sse41_round_pd>, VEX;
4611 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
4612 memopv8f32, memopv4f64,
4613 int_x86_avx_round_ps_256,
4614 int_x86_avx_round_pd_256>, VEX;
4615 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
4616 int_x86_sse41_round_ss,
4617 int_x86_sse41_round_sd, 0>, VEX_4V;
4619 // Instructions for the assembler
4620 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
4622 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
4624 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
4627 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
4628 memopv4f32, memopv2f64,
4629 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
4630 let Constraints = "$src1 = $dst" in
4631 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
4632 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
4634 //===----------------------------------------------------------------------===//
4635 // SSE4.1 - Packed Bit Test
4636 //===----------------------------------------------------------------------===//
4638 // ptest instruction we'll lower to this in X86ISelLowering primarily from
4639 // the intel intrinsic that corresponds to this.
4640 let Defs = [EFLAGS], Predicates = [HasAVX] in {
4641 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4642 "vptest\t{$src2, $src1|$src1, $src2}",
4643 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4645 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4646 "vptest\t{$src2, $src1|$src1, $src2}",
4647 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4650 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
4651 "vptest\t{$src2, $src1|$src1, $src2}",
4652 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
4654 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
4655 "vptest\t{$src2, $src1|$src1, $src2}",
4656 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
4660 let Defs = [EFLAGS] in {
4661 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4662 "ptest \t{$src2, $src1|$src1, $src2}",
4663 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4665 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4666 "ptest \t{$src2, $src1|$src1, $src2}",
4667 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4671 // The bit test instructions below are AVX only
4672 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
4673 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
4674 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
4675 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4676 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
4677 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
4678 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4679 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
4683 let Defs = [EFLAGS], Predicates = [HasAVX] in {
4684 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
4685 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
4686 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
4687 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
4690 //===----------------------------------------------------------------------===//
4691 // SSE4.1 - Misc Instructions
4692 //===----------------------------------------------------------------------===//
4694 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4695 "popcnt{w}\t{$src, $dst|$dst, $src}",
4696 [(set GR16:$dst, (ctpop GR16:$src))]>, OpSize, XS;
4697 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4698 "popcnt{w}\t{$src, $dst|$dst, $src}",
4699 [(set GR16:$dst, (ctpop (loadi16 addr:$src)))]>, OpSize, XS;
4701 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4702 "popcnt{l}\t{$src, $dst|$dst, $src}",
4703 [(set GR32:$dst, (ctpop GR32:$src))]>, XS;
4704 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4705 "popcnt{l}\t{$src, $dst|$dst, $src}",
4706 [(set GR32:$dst, (ctpop (loadi32 addr:$src)))]>, XS;
4708 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4709 "popcnt{q}\t{$src, $dst|$dst, $src}",
4710 [(set GR64:$dst, (ctpop GR64:$src))]>, XS;
4711 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4712 "popcnt{q}\t{$src, $dst|$dst, $src}",
4713 [(set GR64:$dst, (ctpop (loadi64 addr:$src)))]>, XS;
4717 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
4718 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
4719 Intrinsic IntId128> {
4720 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4722 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4723 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
4724 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4726 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4729 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
4732 let Predicates = [HasAVX] in
4733 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
4734 int_x86_sse41_phminposuw>, VEX;
4735 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
4736 int_x86_sse41_phminposuw>;
4738 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
4739 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
4740 Intrinsic IntId128, bit Is2Addr = 1> {
4741 let isCommutable = 1 in
4742 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4743 (ins VR128:$src1, VR128:$src2),
4745 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4746 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4747 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
4748 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4749 (ins VR128:$src1, i128mem:$src2),
4751 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4752 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4754 (IntId128 VR128:$src1,
4755 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4758 let Predicates = [HasAVX] in {
4759 let isCommutable = 0 in
4760 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
4762 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
4764 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
4766 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
4768 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
4770 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
4772 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
4774 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
4776 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
4778 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
4780 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
4784 let Constraints = "$src1 = $dst" in {
4785 let isCommutable = 0 in
4786 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
4787 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
4788 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
4789 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
4790 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
4791 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
4792 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
4793 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
4794 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
4795 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
4796 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
4799 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
4800 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
4801 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
4802 (PCMPEQQrm VR128:$src1, addr:$src2)>;
4804 /// SS48I_binop_rm - Simple SSE41 binary operator.
4805 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4806 ValueType OpVT, bit Is2Addr = 1> {
4807 let isCommutable = 1 in
4808 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4809 (ins VR128:$src1, VR128:$src2),
4811 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4812 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4813 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
4815 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4816 (ins VR128:$src1, i128mem:$src2),
4818 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4819 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4820 [(set VR128:$dst, (OpNode VR128:$src1,
4821 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
4825 let Predicates = [HasAVX] in
4826 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
4827 let Constraints = "$src1 = $dst" in
4828 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
4830 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
4831 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
4832 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
4833 X86MemOperand x86memop, bit Is2Addr = 1> {
4834 let isCommutable = 1 in
4835 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
4836 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
4838 !strconcat(OpcodeStr,
4839 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4840 !strconcat(OpcodeStr,
4841 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4842 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
4844 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
4845 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
4847 !strconcat(OpcodeStr,
4848 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4849 !strconcat(OpcodeStr,
4850 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4853 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
4857 let Predicates = [HasAVX] in {
4858 let isCommutable = 0 in {
4859 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
4860 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4861 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
4862 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4863 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
4864 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4865 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
4866 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4867 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
4868 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4869 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
4870 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4872 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
4873 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4874 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
4875 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4876 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
4877 VR256, memopv32i8, i256mem, 0>, VEX_4V;
4880 let Constraints = "$src1 = $dst" in {
4881 let isCommutable = 0 in {
4882 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
4883 VR128, memopv16i8, i128mem>;
4884 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
4885 VR128, memopv16i8, i128mem>;
4886 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
4887 VR128, memopv16i8, i128mem>;
4888 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
4889 VR128, memopv16i8, i128mem>;
4891 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
4892 VR128, memopv16i8, i128mem>;
4893 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
4894 VR128, memopv16i8, i128mem>;
4897 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
4898 let Predicates = [HasAVX] in {
4899 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
4900 RegisterClass RC, X86MemOperand x86memop,
4901 PatFrag mem_frag, Intrinsic IntId> {
4902 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
4903 (ins RC:$src1, RC:$src2, RC:$src3),
4904 !strconcat(OpcodeStr,
4905 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4906 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
4907 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4909 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
4910 (ins RC:$src1, x86memop:$src2, RC:$src3),
4911 !strconcat(OpcodeStr,
4912 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4914 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
4916 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4920 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
4921 memopv16i8, int_x86_sse41_blendvpd>;
4922 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
4923 memopv16i8, int_x86_sse41_blendvps>;
4924 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
4925 memopv16i8, int_x86_sse41_pblendvb>;
4926 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
4927 memopv32i8, int_x86_avx_blendv_pd_256>;
4928 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
4929 memopv32i8, int_x86_avx_blendv_ps_256>;
4931 /// SS41I_ternary_int - SSE 4.1 ternary operator
4932 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
4933 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4934 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4935 (ins VR128:$src1, VR128:$src2),
4936 !strconcat(OpcodeStr,
4937 "\t{$src2, $dst|$dst, $src2}"),
4938 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
4941 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4942 (ins VR128:$src1, i128mem:$src2),
4943 !strconcat(OpcodeStr,
4944 "\t{$src2, $dst|$dst, $src2}"),
4947 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
4951 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
4952 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
4953 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
4955 def : Pat<(X86pblendv VR128:$src1, VR128:$src2, XMM0),
4956 (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
4958 let Predicates = [HasAVX] in
4959 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4960 "vmovntdqa\t{$src, $dst|$dst, $src}",
4961 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4963 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4964 "movntdqa\t{$src, $dst|$dst, $src}",
4965 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4968 //===----------------------------------------------------------------------===//
4969 // SSE4.2 - Compare Instructions
4970 //===----------------------------------------------------------------------===//
4972 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
4973 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
4974 Intrinsic IntId128, bit Is2Addr = 1> {
4975 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
4976 (ins VR128:$src1, VR128:$src2),
4978 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4979 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4980 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4982 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
4983 (ins VR128:$src1, i128mem:$src2),
4985 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4986 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4988 (IntId128 VR128:$src1,
4989 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4992 let Predicates = [HasAVX] in
4993 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
4995 let Constraints = "$src1 = $dst" in
4996 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
4998 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
4999 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
5000 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
5001 (PCMPGTQrm VR128:$src1, addr:$src2)>;
5003 //===----------------------------------------------------------------------===//
5004 // SSE4.2 - String/text Processing Instructions
5005 //===----------------------------------------------------------------------===//
5007 // Packed Compare Implicit Length Strings, Return Mask
5008 multiclass pseudo_pcmpistrm<string asm> {
5009 def REG : PseudoI<(outs VR128:$dst),
5010 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5011 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
5013 def MEM : PseudoI<(outs VR128:$dst),
5014 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5015 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
5016 VR128:$src1, (load addr:$src2), imm:$src3))]>;
5019 let Defs = [EFLAGS], usesCustomInserter = 1 in {
5020 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
5021 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
5024 let Defs = [XMM0, EFLAGS], Predicates = [HasAVX] in {
5025 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
5026 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5027 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
5028 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
5029 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5030 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
5033 let Defs = [XMM0, EFLAGS] in {
5034 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
5035 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5036 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
5037 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
5038 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5039 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
5042 // Packed Compare Explicit Length Strings, Return Mask
5043 multiclass pseudo_pcmpestrm<string asm> {
5044 def REG : PseudoI<(outs VR128:$dst),
5045 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5046 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
5047 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
5048 def MEM : PseudoI<(outs VR128:$dst),
5049 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5050 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
5051 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
5054 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
5055 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
5056 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
5059 let Predicates = [HasAVX],
5060 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
5061 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
5062 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5063 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
5064 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
5065 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5066 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
5069 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
5070 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
5071 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5072 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
5073 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
5074 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5075 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
5078 // Packed Compare Implicit Length Strings, Return Index
5079 let Defs = [ECX, EFLAGS] in {
5080 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
5081 def rr : SS42AI<0x63, MRMSrcReg, (outs),
5082 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5083 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5084 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
5085 (implicit EFLAGS)]>, OpSize;
5086 def rm : SS42AI<0x63, MRMSrcMem, (outs),
5087 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5088 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5089 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
5090 (implicit EFLAGS)]>, OpSize;
5094 let Predicates = [HasAVX] in {
5095 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
5097 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
5099 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
5101 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
5103 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
5105 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
5109 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
5110 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
5111 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
5112 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
5113 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
5114 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
5116 // Packed Compare Explicit Length Strings, Return Index
5117 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
5118 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
5119 def rr : SS42AI<0x61, MRMSrcReg, (outs),
5120 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5121 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5122 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
5123 (implicit EFLAGS)]>, OpSize;
5124 def rm : SS42AI<0x61, MRMSrcMem, (outs),
5125 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5126 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5128 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
5129 (implicit EFLAGS)]>, OpSize;
5133 let Predicates = [HasAVX] in {
5134 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
5136 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
5138 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
5140 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
5142 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
5144 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
5148 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
5149 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
5150 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
5151 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
5152 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
5153 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
5155 //===----------------------------------------------------------------------===//
5156 // SSE4.2 - CRC Instructions
5157 //===----------------------------------------------------------------------===//
5159 // No CRC instructions have AVX equivalents
5161 // crc intrinsic instruction
5162 // This set of instructions are only rm, the only difference is the size
5164 let Constraints = "$src1 = $dst" in {
5165 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
5166 (ins GR32:$src1, i8mem:$src2),
5167 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5169 (int_x86_sse42_crc32_32_8 GR32:$src1,
5170 (load addr:$src2)))]>;
5171 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
5172 (ins GR32:$src1, GR8:$src2),
5173 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5175 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
5176 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5177 (ins GR32:$src1, i16mem:$src2),
5178 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5180 (int_x86_sse42_crc32_32_16 GR32:$src1,
5181 (load addr:$src2)))]>,
5183 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5184 (ins GR32:$src1, GR16:$src2),
5185 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5187 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
5189 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5190 (ins GR32:$src1, i32mem:$src2),
5191 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5193 (int_x86_sse42_crc32_32_32 GR32:$src1,
5194 (load addr:$src2)))]>;
5195 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5196 (ins GR32:$src1, GR32:$src2),
5197 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5199 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
5200 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
5201 (ins GR64:$src1, i8mem:$src2),
5202 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5204 (int_x86_sse42_crc32_64_8 GR64:$src1,
5205 (load addr:$src2)))]>,
5207 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
5208 (ins GR64:$src1, GR8:$src2),
5209 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5211 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
5213 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
5214 (ins GR64:$src1, i64mem:$src2),
5215 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5217 (int_x86_sse42_crc32_64_64 GR64:$src1,
5218 (load addr:$src2)))]>,
5220 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
5221 (ins GR64:$src1, GR64:$src2),
5222 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5224 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
5228 //===----------------------------------------------------------------------===//
5229 // AES-NI Instructions
5230 //===----------------------------------------------------------------------===//
5232 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
5233 Intrinsic IntId128, bit Is2Addr = 1> {
5234 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
5235 (ins VR128:$src1, VR128:$src2),
5237 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5238 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5239 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5241 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
5242 (ins VR128:$src1, i128mem:$src2),
5244 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5245 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5247 (IntId128 VR128:$src1,
5248 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5251 // Perform One Round of an AES Encryption/Decryption Flow
5252 let Predicates = [HasAVX, HasAES] in {
5253 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
5254 int_x86_aesni_aesenc, 0>, VEX_4V;
5255 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
5256 int_x86_aesni_aesenclast, 0>, VEX_4V;
5257 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
5258 int_x86_aesni_aesdec, 0>, VEX_4V;
5259 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
5260 int_x86_aesni_aesdeclast, 0>, VEX_4V;
5263 let Constraints = "$src1 = $dst" in {
5264 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
5265 int_x86_aesni_aesenc>;
5266 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
5267 int_x86_aesni_aesenclast>;
5268 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
5269 int_x86_aesni_aesdec>;
5270 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
5271 int_x86_aesni_aesdeclast>;
5274 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
5275 (AESENCrr VR128:$src1, VR128:$src2)>;
5276 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
5277 (AESENCrm VR128:$src1, addr:$src2)>;
5278 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
5279 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
5280 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
5281 (AESENCLASTrm VR128:$src1, addr:$src2)>;
5282 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
5283 (AESDECrr VR128:$src1, VR128:$src2)>;
5284 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
5285 (AESDECrm VR128:$src1, addr:$src2)>;
5286 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
5287 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
5288 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
5289 (AESDECLASTrm VR128:$src1, addr:$src2)>;
5291 // Perform the AES InvMixColumn Transformation
5292 let Predicates = [HasAVX, HasAES] in {
5293 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5295 "vaesimc\t{$src1, $dst|$dst, $src1}",
5297 (int_x86_aesni_aesimc VR128:$src1))]>,
5299 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5300 (ins i128mem:$src1),
5301 "vaesimc\t{$src1, $dst|$dst, $src1}",
5303 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5306 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5308 "aesimc\t{$src1, $dst|$dst, $src1}",
5310 (int_x86_aesni_aesimc VR128:$src1))]>,
5312 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5313 (ins i128mem:$src1),
5314 "aesimc\t{$src1, $dst|$dst, $src1}",
5316 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5319 // AES Round Key Generation Assist
5320 let Predicates = [HasAVX, HasAES] in {
5321 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5322 (ins VR128:$src1, i8imm:$src2),
5323 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5325 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5327 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5328 (ins i128mem:$src1, i8imm:$src2),
5329 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5331 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5335 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5336 (ins VR128:$src1, i8imm:$src2),
5337 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5339 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5341 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5342 (ins i128mem:$src1, i8imm:$src2),
5343 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5345 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5349 //===----------------------------------------------------------------------===//
5350 // CLMUL Instructions
5351 //===----------------------------------------------------------------------===//
5353 // Carry-less Multiplication instructions
5354 let Constraints = "$src1 = $dst" in {
5355 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5356 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5357 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5360 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5361 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5362 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5366 // AVX carry-less Multiplication instructions
5367 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5368 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5369 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5372 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5373 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5374 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5378 multiclass pclmul_alias<string asm, int immop> {
5379 def : InstAlias<!strconcat("pclmul", asm,
5380 "dq {$src, $dst|$dst, $src}"),
5381 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
5383 def : InstAlias<!strconcat("pclmul", asm,
5384 "dq {$src, $dst|$dst, $src}"),
5385 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
5387 def : InstAlias<!strconcat("vpclmul", asm,
5388 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
5389 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
5391 def : InstAlias<!strconcat("vpclmul", asm,
5392 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
5393 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
5395 defm : pclmul_alias<"hqhq", 0x11>;
5396 defm : pclmul_alias<"hqlq", 0x01>;
5397 defm : pclmul_alias<"lqhq", 0x10>;
5398 defm : pclmul_alias<"lqlq", 0x00>;
5400 //===----------------------------------------------------------------------===//
5402 //===----------------------------------------------------------------------===//
5404 //===----------------------------------------------------------------------===//
5405 // VBROADCAST - Load from memory and broadcast to all elements of the
5406 // destination operand
5408 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
5409 X86MemOperand x86memop, Intrinsic Int> :
5410 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5411 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5412 [(set RC:$dst, (Int addr:$src))]>, VEX;
5414 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
5415 int_x86_avx_vbroadcastss>;
5416 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
5417 int_x86_avx_vbroadcastss_256>;
5418 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
5419 int_x86_avx_vbroadcast_sd_256>;
5420 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
5421 int_x86_avx_vbroadcastf128_pd_256>;
5423 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
5424 (VBROADCASTF128 addr:$src)>;
5426 //===----------------------------------------------------------------------===//
5427 // VINSERTF128 - Insert packed floating-point values
5429 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
5430 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
5431 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5433 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
5434 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
5435 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5438 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
5439 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5440 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
5441 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5442 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
5443 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5445 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
5447 (VINSERTF128rr VR256:$src1, VR128:$src2,
5448 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5449 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
5451 (VINSERTF128rr VR256:$src1, VR128:$src2,
5452 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5453 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
5455 (VINSERTF128rr VR256:$src1, VR128:$src2,
5456 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5457 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
5459 (VINSERTF128rr VR256:$src1, VR128:$src2,
5460 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5461 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
5463 (VINSERTF128rr VR256:$src1, VR128:$src2,
5464 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5465 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
5467 (VINSERTF128rr VR256:$src1, VR128:$src2,
5468 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5470 // Special COPY patterns
5471 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
5472 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5473 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
5474 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5475 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
5476 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5477 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
5478 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5479 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
5480 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5481 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
5482 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5484 //===----------------------------------------------------------------------===//
5485 // VEXTRACTF128 - Extract packed floating-point values
5487 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
5488 (ins VR256:$src1, i8imm:$src2),
5489 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5491 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
5492 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
5493 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5496 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
5497 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5498 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
5499 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5500 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
5501 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5503 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5504 (v4f32 (VEXTRACTF128rr
5505 (v8f32 VR256:$src1),
5506 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5507 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5508 (v2f64 (VEXTRACTF128rr
5509 (v4f64 VR256:$src1),
5510 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5511 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5512 (v4i32 (VEXTRACTF128rr
5513 (v8i32 VR256:$src1),
5514 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5515 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5516 (v2i64 (VEXTRACTF128rr
5517 (v4i64 VR256:$src1),
5518 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5519 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5520 (v8i16 (VEXTRACTF128rr
5521 (v16i16 VR256:$src1),
5522 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5523 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5524 (v16i8 (VEXTRACTF128rr
5525 (v32i8 VR256:$src1),
5526 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5528 // Special COPY patterns
5529 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
5530 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
5531 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
5532 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
5534 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
5535 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
5536 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
5537 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
5540 //===----------------------------------------------------------------------===//
5541 // VMASKMOV - Conditional SIMD Packed Loads and Stores
5543 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
5544 Intrinsic IntLd, Intrinsic IntLd256,
5545 Intrinsic IntSt, Intrinsic IntSt256,
5546 PatFrag pf128, PatFrag pf256> {
5547 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
5548 (ins VR128:$src1, f128mem:$src2),
5549 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5550 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
5552 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
5553 (ins VR256:$src1, f256mem:$src2),
5554 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5555 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
5557 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
5558 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
5559 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5560 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
5561 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
5562 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
5563 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5564 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
5567 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
5568 int_x86_avx_maskload_ps,
5569 int_x86_avx_maskload_ps_256,
5570 int_x86_avx_maskstore_ps,
5571 int_x86_avx_maskstore_ps_256,
5572 memopv4f32, memopv8f32>;
5573 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
5574 int_x86_avx_maskload_pd,
5575 int_x86_avx_maskload_pd_256,
5576 int_x86_avx_maskstore_pd,
5577 int_x86_avx_maskstore_pd_256,
5578 memopv2f64, memopv4f64>;
5580 //===----------------------------------------------------------------------===//
5581 // VPERM - Permute Floating-Point Values
5583 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
5584 RegisterClass RC, X86MemOperand x86memop_f,
5585 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
5586 Intrinsic IntVar, Intrinsic IntImm> {
5587 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
5588 (ins RC:$src1, RC:$src2),
5589 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5590 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
5591 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
5592 (ins RC:$src1, x86memop_i:$src2),
5593 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5594 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
5596 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
5597 (ins RC:$src1, i8imm:$src2),
5598 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5599 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
5600 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
5601 (ins x86memop_f:$src1, i8imm:$src2),
5602 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5603 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
5606 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
5607 memopv4f32, memopv4i32,
5608 int_x86_avx_vpermilvar_ps,
5609 int_x86_avx_vpermil_ps>;
5610 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
5611 memopv8f32, memopv8i32,
5612 int_x86_avx_vpermilvar_ps_256,
5613 int_x86_avx_vpermil_ps_256>;
5614 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
5615 memopv2f64, memopv2i64,
5616 int_x86_avx_vpermilvar_pd,
5617 int_x86_avx_vpermil_pd>;
5618 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
5619 memopv4f64, memopv4i64,
5620 int_x86_avx_vpermilvar_pd_256,
5621 int_x86_avx_vpermil_pd_256>;
5623 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
5624 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5625 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5627 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
5628 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
5629 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5632 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
5633 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5634 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
5635 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5636 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
5637 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5639 def : Pat<(int_x86_avx_vperm2f128_ps_256
5640 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
5641 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5642 def : Pat<(int_x86_avx_vperm2f128_pd_256
5643 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
5644 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5645 def : Pat<(int_x86_avx_vperm2f128_si_256
5646 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
5647 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5649 // Shuffle with VPERMIL instructions
5650 def : Pat<(v8f32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
5651 (VPERMILPSYri VR256:$src1, imm:$imm)>;
5652 def : Pat<(v4f64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
5653 (VPERMILPDYri VR256:$src1, imm:$imm)>;
5654 def : Pat<(v8i32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
5655 (VPERMILPSYri VR256:$src1, imm:$imm)>;
5656 def : Pat<(v4i64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
5657 (VPERMILPDYri VR256:$src1, imm:$imm)>;
5659 //===----------------------------------------------------------------------===//
5660 // VZERO - Zero YMM registers
5662 // Zero All YMM registers
5663 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
5664 [(int_x86_avx_vzeroall)]>, VEX, VEX_L, Requires<[HasAVX]>;
5666 // Zero Upper bits of YMM registers
5667 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
5668 [(int_x86_avx_vzeroupper)]>, VEX, Requires<[HasAVX]>;
5670 //===----------------------------------------------------------------------===//
5671 // SSE Shuffle pattern fragments
5672 //===----------------------------------------------------------------------===//
5674 // This is part of a "work in progress" refactoring. The idea is that all
5675 // vector shuffles are going to be translated into target specific nodes and
5676 // directly matched by the patterns below (which can be changed along the way)
5677 // The AVX version of some but not all of them are described here, and more
5678 // should come in a near future.
5680 // Shuffle with PSHUFD instruction folding loads. The first two patterns match
5681 // SSE2 loads, which are always promoted to v2i64. The last one should match
5682 // the SSE1 case, where the only legal load is v4f32, but there is no PSHUFD
5683 // in SSE2, how does it ever worked? Anyway, the pattern will remain here until
5684 // we investigate further.
5685 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5687 (VPSHUFDmi addr:$src1, imm:$imm)>, Requires<[HasAVX]>;
5688 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5690 (PSHUFDmi addr:$src1, imm:$imm)>;
5691 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
5693 (PSHUFDmi addr:$src1, imm:$imm)>; // FIXME: has this ever worked?
5695 // Shuffle with PSHUFD instruction.
5696 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5697 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5698 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5699 (PSHUFDri VR128:$src1, imm:$imm)>;
5701 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5702 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5703 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5704 (PSHUFDri VR128:$src1, imm:$imm)>;
5706 // Shuffle with SHUFPD instruction.
5707 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5708 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5709 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5710 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5711 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5712 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
5714 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5715 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5716 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5717 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5719 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5720 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5721 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5722 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5724 // Shuffle with SHUFPS instruction.
5725 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5726 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5727 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5728 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5729 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5730 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5732 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5733 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5734 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5735 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5737 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5738 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5739 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5740 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5741 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5742 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5744 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5745 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5746 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5747 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5749 // Shuffle with MOVHLPS instruction
5750 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
5751 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5752 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
5753 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5755 // Shuffle with MOVDDUP instruction
5756 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5757 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5758 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5759 (MOVDDUPrm addr:$src)>;
5761 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5762 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5763 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5764 (MOVDDUPrm addr:$src)>;
5766 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5767 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5768 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5769 (MOVDDUPrm addr:$src)>;
5771 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5772 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5773 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5774 (MOVDDUPrm addr:$src)>;
5776 def : Pat<(X86Movddup (bc_v2f64
5777 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5778 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5779 def : Pat<(X86Movddup (bc_v2f64
5780 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5781 (MOVDDUPrm addr:$src)>;
5784 // Shuffle with UNPCKLPS
5785 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
5786 (VUNPCKLPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5787 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
5788 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5789 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
5790 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
5792 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
5793 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5794 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
5795 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5796 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
5797 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
5799 // Shuffle with UNPCKHPS
5800 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
5801 (VUNPCKHPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5802 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
5803 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
5805 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
5806 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5807 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
5808 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
5810 // Shuffle with VUNPCKHPSY
5811 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, (memopv8f32 addr:$src2))),
5812 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5813 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
5814 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5816 // Shuffle with UNPCKLPD
5817 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
5818 (VUNPCKLPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5819 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
5820 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5821 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
5822 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
5824 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
5825 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5826 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
5827 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5828 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
5829 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
5831 // Shuffle with UNPCKHPD
5832 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
5833 (VUNPCKHPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5834 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
5835 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
5837 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
5838 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5839 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
5840 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
5842 // Shuffle with VUNPCKHPDY
5843 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, (memopv4f64 addr:$src2))),
5844 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5845 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
5846 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5848 // Shuffle with MOVLHPS
5849 def : Pat<(X86Movlhps VR128:$src1,
5850 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
5851 (MOVHPSrm VR128:$src1, addr:$src2)>;
5852 def : Pat<(X86Movlhps VR128:$src1,
5853 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
5854 (MOVHPSrm VR128:$src1, addr:$src2)>;
5855 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
5856 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
5857 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
5858 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
5859 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
5860 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
5862 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the problem
5863 // is during lowering, where it's not possible to recognize the load fold cause
5864 // it has two uses through a bitcast. One use disappears at isel time and the
5865 // fold opportunity reappears.
5866 def : Pat<(v2f64 (X86Movddup VR128:$src)),
5867 (UNPCKLPDrr VR128:$src, VR128:$src)>;
5869 // Shuffle with MOVLHPD
5870 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
5871 (scalar_to_vector (loadf64 addr:$src2)))),
5872 (MOVHPDrm VR128:$src1, addr:$src2)>;
5874 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
5875 // is during lowering, where it's not possible to recognize the load fold cause
5876 // it has two uses through a bitcast. One use disappears at isel time and the
5877 // fold opportunity reappears.
5878 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
5879 (scalar_to_vector (loadf64 addr:$src2)))),
5880 (MOVHPDrm VR128:$src1, addr:$src2)>;
5882 // Shuffle with MOVSS
5883 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
5884 (MOVSSrr VR128:$src1, FR32:$src2)>;
5885 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
5886 (MOVSSrr (v4i32 VR128:$src1),
5887 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
5888 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
5889 (MOVSSrr (v4f32 VR128:$src1),
5890 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
5891 // FIXME: Instead of a X86Movss there should be a X86Movlps here, the problem
5892 // is during lowering, where it's not possible to recognize the load fold cause
5893 // it has two uses through a bitcast. One use disappears at isel time and the
5894 // fold opportunity reappears.
5895 def : Pat<(X86Movss VR128:$src1,
5896 (bc_v4i32 (v2i64 (load addr:$src2)))),
5897 (MOVLPSrm VR128:$src1, addr:$src2)>;
5899 // Shuffle with MOVSD
5900 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
5901 (MOVSDrr VR128:$src1, FR64:$src2)>;
5902 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
5903 (MOVSDrr (v2i64 VR128:$src1),
5904 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
5905 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
5906 (MOVSDrr (v2f64 VR128:$src1),
5907 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
5908 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
5909 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
5910 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
5911 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
5913 // Shuffle with PSHUFHW
5914 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
5915 (PSHUFHWri VR128:$src, imm:$imm)>;
5916 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
5917 (PSHUFHWmi addr:$src, imm:$imm)>;
5919 // Shuffle with PSHUFLW
5920 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
5921 (PSHUFLWri VR128:$src, imm:$imm)>;
5922 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
5923 (PSHUFLWmi addr:$src, imm:$imm)>;
5925 // Shuffle with MOVLPS
5926 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
5927 (MOVLPSrm VR128:$src1, addr:$src2)>;
5928 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
5929 (MOVLPSrm VR128:$src1, addr:$src2)>;
5930 def : Pat<(X86Movlps VR128:$src1,
5931 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
5932 (MOVLPSrm VR128:$src1, addr:$src2)>;
5933 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
5934 // is during lowering, where it's not possible to recognize the load fold cause
5935 // it has two uses through a bitcast. One use disappears at isel time and the
5936 // fold opportunity reappears.
5937 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
5938 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
5940 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
5941 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
5943 // Shuffle with MOVLPD
5944 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
5945 (MOVLPDrm VR128:$src1, addr:$src2)>;
5946 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
5947 (MOVLPDrm VR128:$src1, addr:$src2)>;
5948 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
5949 (scalar_to_vector (loadf64 addr:$src2)))),
5950 (MOVLPDrm VR128:$src1, addr:$src2)>;
5952 // Extra patterns to match stores with MOVHPS/PD and MOVLPS/PD
5953 def : Pat<(store (f64 (vector_extract
5954 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))),addr:$dst),
5955 (MOVHPSmr addr:$dst, VR128:$src)>;
5956 def : Pat<(store (f64 (vector_extract
5957 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
5958 (MOVHPDmr addr:$dst, VR128:$src)>;
5960 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),addr:$src1),
5961 (MOVLPSmr addr:$src1, VR128:$src2)>;
5962 def : Pat<(store (v4i32 (X86Movlps
5963 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
5964 (MOVLPSmr addr:$src1, VR128:$src2)>;
5966 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
5967 (MOVLPDmr addr:$src1, VR128:$src2)>;
5968 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
5969 (MOVLPDmr addr:$src1, VR128:$src2)>;