1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 let isCommutable = 1 in
85 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
90 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
97 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
98 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
99 string asm, string SSEVer, string FPSizeStr,
100 X86MemOperand x86memop, PatFrag mem_frag,
101 Domain d, bit Is2Addr = 1> {
102 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
104 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
105 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
106 [(set RC:$dst, (!cast<Intrinsic>(
107 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
108 RC:$src1, RC:$src2))], d>;
109 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
111 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
113 [(set RC:$dst, (!cast<Intrinsic>(
114 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
115 RC:$src1, (mem_frag addr:$src2)))], d>;
118 //===----------------------------------------------------------------------===//
119 // Non-instruction patterns
120 //===----------------------------------------------------------------------===//
122 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
123 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
125 // Implicitly promote a 32-bit scalar to a vector.
126 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
127 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
128 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
129 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
130 // Implicitly promote a 64-bit scalar to a vector.
131 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
132 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
133 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
134 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
136 // Bitcasts between 128-bit vector types. Return the original type since
137 // no instruction is needed for the conversion
138 let Predicates = [HasXMMInt] in {
139 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
140 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
141 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
142 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
143 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
144 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
145 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
146 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
147 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
148 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
149 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
150 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
151 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
152 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
153 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
154 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
155 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
156 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
157 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
158 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
159 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
160 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
161 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
162 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
163 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
164 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
165 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
166 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
167 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
168 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
171 // Bitcasts between 256-bit vector types. Return the original type since
172 // no instruction is needed for the conversion
173 let Predicates = [HasAVX] in {
174 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
175 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
176 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
177 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
178 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
179 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
180 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
181 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
182 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
183 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
184 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
185 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
186 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
187 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
188 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
189 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
190 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
191 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
192 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
193 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
194 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
195 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
196 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
197 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
198 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
199 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
200 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
201 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
202 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
203 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
206 //===----------------------------------------------------------------------===//
207 // AVX & SSE - Zero/One Vectors
208 //===----------------------------------------------------------------------===//
210 // Alias instructions that map zero vector to pxor / xorp* for sse.
211 // We set canFoldAsLoad because this can be converted to a constant-pool
212 // load of an all-zeros value if folding it would be beneficial.
213 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
214 // JIT implementation, it does not expand the instructions below like
215 // X86MCInstLower does.
216 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
217 isCodeGenOnly = 1 in {
218 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
219 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
220 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
221 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
222 let ExeDomain = SSEPackedInt in
223 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
224 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
227 // The same as done above but for AVX. The 128-bit versions are the
228 // same, but re-encoded. The 256-bit does not support PI version, and
229 // doesn't need it because on sandy bridge the register is set to zero
230 // at the rename stage without using any execution unit, so SET0PSY
231 // and SET0PDY can be used for vector int instructions without penalty
232 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
233 // JIT implementatioan, it does not expand the instructions below like
234 // X86MCInstLower does.
235 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
236 isCodeGenOnly = 1, Predicates = [HasAVX] in {
237 def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
238 [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V;
239 def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
240 [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V;
241 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
242 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
243 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
244 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
245 let ExeDomain = SSEPackedInt in
246 def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
247 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
250 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
251 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
252 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
254 // AVX has no support for 256-bit integer instructions, but since the 128-bit
255 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
256 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
257 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
258 (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
260 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
261 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
262 (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
264 //===----------------------------------------------------------------------===//
265 // SSE 1 & 2 - Move Instructions
266 //===----------------------------------------------------------------------===//
268 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
269 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
270 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
272 // Loading from memory automatically zeroing upper bits.
273 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
274 PatFrag mem_pat, string OpcodeStr> :
275 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
276 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
277 [(set RC:$dst, (mem_pat addr:$src))]>;
279 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
280 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
281 // is used instead. Register-to-register movss/movsd is not modeled as an
282 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
283 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
284 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
285 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
286 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
287 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
289 let canFoldAsLoad = 1, isReMaterializable = 1 in {
290 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
292 let AddedComplexity = 20 in
293 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
296 let Constraints = "$src1 = $dst" in {
297 def MOVSSrr : sse12_move_rr<FR32, v4f32,
298 "movss\t{$src2, $dst|$dst, $src2}">, XS;
299 def MOVSDrr : sse12_move_rr<FR64, v2f64,
300 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
303 let canFoldAsLoad = 1, isReMaterializable = 1 in {
304 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
306 let AddedComplexity = 20 in
307 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
310 let AddedComplexity = 15 in {
311 // Extract the low 32-bit value from one vector and insert it into another.
312 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
313 (MOVSSrr (v4f32 VR128:$src1),
314 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
315 // Extract the low 64-bit value from one vector and insert it into another.
316 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
317 (MOVSDrr (v2f64 VR128:$src1),
318 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
321 let AddedComplexity = 20 in {
322 let Predicates = [HasSSE1] in {
323 // MOVSSrm zeros the high parts of the register; represent this
324 // with SUBREG_TO_REG.
325 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
326 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
327 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
328 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
329 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
330 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
332 let Predicates = [HasSSE2] in {
333 // MOVSDrm zeros the high parts of the register; represent this
334 // with SUBREG_TO_REG.
335 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
336 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
337 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
338 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
339 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
340 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
341 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
342 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
343 def : Pat<(v2f64 (X86vzload addr:$src)),
344 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
348 let AddedComplexity = 20, Predicates = [HasAVX] in {
349 // MOVSSrm zeros the high parts of the register; represent this
350 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
351 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
352 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
353 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
354 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
355 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
356 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
357 // MOVSDrm zeros the high parts of the register; represent this
358 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
359 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
360 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
361 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
362 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
363 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
364 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
365 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
366 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
367 def : Pat<(v2f64 (X86vzload addr:$src)),
368 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
369 // Represent the same patterns above but in the form they appear for
371 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
372 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
373 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
374 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
375 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
376 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
379 // Store scalar value to memory.
380 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
381 "movss\t{$src, $dst|$dst, $src}",
382 [(store FR32:$src, addr:$dst)]>;
383 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
384 "movsd\t{$src, $dst|$dst, $src}",
385 [(store FR64:$src, addr:$dst)]>;
387 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
388 "movss\t{$src, $dst|$dst, $src}",
389 [(store FR32:$src, addr:$dst)]>, XS, VEX;
390 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
391 "movsd\t{$src, $dst|$dst, $src}",
392 [(store FR64:$src, addr:$dst)]>, XD, VEX;
394 // Extract and store.
395 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
398 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
399 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
402 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
404 // Move Aligned/Unaligned floating point values
405 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
406 X86MemOperand x86memop, PatFrag ld_frag,
407 string asm, Domain d,
408 bit IsReMaterializable = 1> {
409 let neverHasSideEffects = 1 in
410 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
411 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
412 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
413 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
414 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
415 [(set RC:$dst, (ld_frag addr:$src))], d>;
418 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
419 "movaps", SSEPackedSingle>, VEX;
420 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
421 "movapd", SSEPackedDouble>, OpSize, VEX;
422 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
423 "movups", SSEPackedSingle>, VEX;
424 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
425 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
427 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
428 "movaps", SSEPackedSingle>, VEX;
429 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
430 "movapd", SSEPackedDouble>, OpSize, VEX;
431 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
432 "movups", SSEPackedSingle>, VEX;
433 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
434 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
435 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
436 "movaps", SSEPackedSingle>, TB;
437 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
438 "movapd", SSEPackedDouble>, TB, OpSize;
439 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
440 "movups", SSEPackedSingle>, TB;
441 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
442 "movupd", SSEPackedDouble, 0>, TB, OpSize;
444 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
445 "movaps\t{$src, $dst|$dst, $src}",
446 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
447 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
448 "movapd\t{$src, $dst|$dst, $src}",
449 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
450 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
451 "movups\t{$src, $dst|$dst, $src}",
452 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
453 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
454 "movupd\t{$src, $dst|$dst, $src}",
455 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
456 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
457 "movaps\t{$src, $dst|$dst, $src}",
458 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
459 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
460 "movapd\t{$src, $dst|$dst, $src}",
461 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
462 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
463 "movups\t{$src, $dst|$dst, $src}",
464 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
465 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
466 "movupd\t{$src, $dst|$dst, $src}",
467 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
469 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
470 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
471 (VMOVUPSYmr addr:$dst, VR256:$src)>;
473 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
474 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
475 (VMOVUPDYmr addr:$dst, VR256:$src)>;
477 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
478 "movaps\t{$src, $dst|$dst, $src}",
479 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
480 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
481 "movapd\t{$src, $dst|$dst, $src}",
482 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
483 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
484 "movups\t{$src, $dst|$dst, $src}",
485 [(store (v4f32 VR128:$src), addr:$dst)]>;
486 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
487 "movupd\t{$src, $dst|$dst, $src}",
488 [(store (v2f64 VR128:$src), addr:$dst)]>;
490 // Intrinsic forms of MOVUPS/D load and store
491 def VMOVUPSmr_Int : VPSI<0x11, MRMDestMem, (outs),
492 (ins f128mem:$dst, VR128:$src),
493 "movups\t{$src, $dst|$dst, $src}",
494 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX;
495 def VMOVUPDmr_Int : VPDI<0x11, MRMDestMem, (outs),
496 (ins f128mem:$dst, VR128:$src),
497 "movupd\t{$src, $dst|$dst, $src}",
498 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX;
500 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
501 "movups\t{$src, $dst|$dst, $src}",
502 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
503 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
504 "movupd\t{$src, $dst|$dst, $src}",
505 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
507 // Move Low/High packed floating point values
508 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
509 PatFrag mov_frag, string base_opc,
511 def PSrm : PI<opc, MRMSrcMem,
512 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
513 !strconcat(base_opc, "s", asm_opr),
516 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
517 SSEPackedSingle>, TB;
519 def PDrm : PI<opc, MRMSrcMem,
520 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
521 !strconcat(base_opc, "d", asm_opr),
522 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
523 (scalar_to_vector (loadf64 addr:$src2)))))],
524 SSEPackedDouble>, TB, OpSize;
527 let AddedComplexity = 20 in {
528 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
529 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
530 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
531 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
533 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
534 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
535 "\t{$src2, $dst|$dst, $src2}">;
536 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
537 "\t{$src2, $dst|$dst, $src2}">;
540 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
541 "movlps\t{$src, $dst|$dst, $src}",
542 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
543 (iPTR 0))), addr:$dst)]>, VEX;
544 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
545 "movlpd\t{$src, $dst|$dst, $src}",
546 [(store (f64 (vector_extract (v2f64 VR128:$src),
547 (iPTR 0))), addr:$dst)]>, VEX;
548 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
549 "movlps\t{$src, $dst|$dst, $src}",
550 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
551 (iPTR 0))), addr:$dst)]>;
552 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
553 "movlpd\t{$src, $dst|$dst, $src}",
554 [(store (f64 (vector_extract (v2f64 VR128:$src),
555 (iPTR 0))), addr:$dst)]>;
557 // v2f64 extract element 1 is always custom lowered to unpack high to low
558 // and extract element 0 so the non-store version isn't too horrible.
559 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
560 "movhps\t{$src, $dst|$dst, $src}",
561 [(store (f64 (vector_extract
562 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
563 (undef)), (iPTR 0))), addr:$dst)]>,
565 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
566 "movhpd\t{$src, $dst|$dst, $src}",
567 [(store (f64 (vector_extract
568 (v2f64 (unpckh VR128:$src, (undef))),
569 (iPTR 0))), addr:$dst)]>,
571 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
572 "movhps\t{$src, $dst|$dst, $src}",
573 [(store (f64 (vector_extract
574 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
575 (undef)), (iPTR 0))), addr:$dst)]>;
576 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
577 "movhpd\t{$src, $dst|$dst, $src}",
578 [(store (f64 (vector_extract
579 (v2f64 (unpckh VR128:$src, (undef))),
580 (iPTR 0))), addr:$dst)]>;
582 let AddedComplexity = 20 in {
583 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
584 (ins VR128:$src1, VR128:$src2),
585 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
587 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
589 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
590 (ins VR128:$src1, VR128:$src2),
591 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
593 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
596 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
597 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
598 (ins VR128:$src1, VR128:$src2),
599 "movlhps\t{$src2, $dst|$dst, $src2}",
601 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
602 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
603 (ins VR128:$src1, VR128:$src2),
604 "movhlps\t{$src2, $dst|$dst, $src2}",
606 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
609 let Predicates = [HasAVX] in {
611 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
612 (VMOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
613 def : Pat<(X86Movlhps VR128:$src1,
614 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
615 (VMOVHPSrm VR128:$src1, addr:$src2)>;
616 def : Pat<(X86Movlhps VR128:$src1,
617 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
618 (VMOVHPSrm VR128:$src1, addr:$src2)>;
621 let AddedComplexity = 20 in {
622 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
623 (VMOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
624 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
625 (VMOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
627 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
628 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
629 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
631 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
632 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
633 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
634 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
635 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
636 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
639 let AddedComplexity = 20 in {
640 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
641 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
642 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
644 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
645 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
646 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
647 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
648 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
651 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
652 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
653 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
654 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
657 let Predicates = [HasSSE1] in {
659 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
660 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
661 def : Pat<(X86Movlhps VR128:$src1,
662 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
663 (MOVHPSrm VR128:$src1, addr:$src2)>;
664 def : Pat<(X86Movlhps VR128:$src1,
665 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
666 (MOVHPSrm VR128:$src1, addr:$src2)>;
669 let AddedComplexity = 20 in {
670 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
671 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
672 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
673 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
675 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
676 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
677 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
679 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
680 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
681 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
682 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
683 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
684 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
687 let AddedComplexity = 20 in {
688 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
689 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
690 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
692 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
693 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
694 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
695 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
696 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
699 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
700 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
701 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
702 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
705 //===----------------------------------------------------------------------===//
706 // SSE 1 & 2 - Conversion Instructions
707 //===----------------------------------------------------------------------===//
709 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
710 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
712 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
713 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
714 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
715 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
718 multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
719 X86MemOperand x86memop, string asm> {
720 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
722 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
726 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
727 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
728 string asm, Domain d> {
729 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
730 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
731 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
732 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
735 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
736 X86MemOperand x86memop, string asm> {
737 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
738 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
739 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
740 (ins DstRC:$src1, x86memop:$src),
741 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
744 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
745 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
746 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
747 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
749 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
750 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
751 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
752 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
755 // The assembler can recognize rr 64-bit instructions by seeing a rxx
756 // register, but the same isn't true when only using memory operands,
757 // provide other assembly "l" and "q" forms to address this explicitly
758 // where appropriate to do so.
759 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
761 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
763 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
765 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
767 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
770 let Predicates = [HasAVX] in {
771 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
772 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
773 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
774 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
775 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
776 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
777 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
778 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
780 def : Pat<(f32 (sint_to_fp GR32:$src)),
781 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
782 def : Pat<(f32 (sint_to_fp GR64:$src)),
783 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
784 def : Pat<(f64 (sint_to_fp GR32:$src)),
785 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
786 def : Pat<(f64 (sint_to_fp GR64:$src)),
787 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
790 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
791 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
792 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
793 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
794 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
795 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
796 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
797 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
798 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
799 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
800 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
801 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
802 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
803 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
804 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
805 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
807 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
808 // and/or XMM operand(s).
810 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
811 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
813 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
814 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
815 [(set DstRC:$dst, (Int SrcRC:$src))]>;
816 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
817 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
818 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
821 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
822 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
823 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
824 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
826 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
827 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
828 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
829 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
830 (ins DstRC:$src1, x86memop:$src2),
832 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
833 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
834 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
837 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
838 f128mem, load, "cvtsd2si">, XD, VEX;
839 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
840 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
843 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
844 // Get rid of this hack or rename the intrinsics, there are several
845 // intructions that only match with the intrinsic form, why create duplicates
846 // to let them be recognized by the assembler?
847 defm VCVTSD2SI_alt : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
848 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
849 defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
850 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
851 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
852 f128mem, load, "cvtsd2si{l}">, XD;
853 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
854 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
857 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
858 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
859 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
860 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
862 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
863 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
864 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
865 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
868 let Constraints = "$src1 = $dst" in {
869 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
870 int_x86_sse_cvtsi2ss, i32mem, loadi32,
872 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
873 int_x86_sse_cvtsi642ss, i64mem, loadi64,
874 "cvtsi2ss{q}">, XS, REX_W;
875 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
876 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
878 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
879 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
880 "cvtsi2sd">, XD, REX_W;
885 // Aliases for intrinsics
886 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
887 f32mem, load, "cvttss2si">, XS, VEX;
888 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
889 int_x86_sse_cvttss2si64, f32mem, load,
890 "cvttss2si">, XS, VEX, VEX_W;
891 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
892 f128mem, load, "cvttsd2si">, XD, VEX;
893 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
894 int_x86_sse2_cvttsd2si64, f128mem, load,
895 "cvttsd2si">, XD, VEX, VEX_W;
896 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
897 f32mem, load, "cvttss2si">, XS;
898 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
899 int_x86_sse_cvttss2si64, f32mem, load,
900 "cvttss2si{q}">, XS, REX_W;
901 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
902 f128mem, load, "cvttsd2si">, XD;
903 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
904 int_x86_sse2_cvttsd2si64, f128mem, load,
905 "cvttsd2si{q}">, XD, REX_W;
907 let Pattern = []<dag> in {
908 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
909 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
910 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
911 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
913 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
914 "cvtdq2ps\t{$src, $dst|$dst, $src}",
915 SSEPackedSingle>, TB, VEX;
916 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
917 "cvtdq2ps\t{$src, $dst|$dst, $src}",
918 SSEPackedSingle>, TB, VEX;
921 let Pattern = []<dag> in {
922 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
923 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
924 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
925 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
926 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
927 "cvtdq2ps\t{$src, $dst|$dst, $src}",
928 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
931 let Predicates = [HasSSE1] in {
932 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
933 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
934 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
935 (CVTSS2SIrm addr:$src)>;
936 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
937 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
938 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
939 (CVTSS2SI64rm addr:$src)>;
942 let Predicates = [HasAVX] in {
943 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
944 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
945 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
946 (VCVTSS2SIrm addr:$src)>;
947 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
948 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
949 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
950 (VCVTSS2SI64rm addr:$src)>;
955 // Convert scalar double to scalar single
956 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
957 (ins FR64:$src1, FR64:$src2),
958 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
960 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
961 (ins FR64:$src1, f64mem:$src2),
962 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
963 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
964 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
967 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
968 "cvtsd2ss\t{$src, $dst|$dst, $src}",
969 [(set FR32:$dst, (fround FR64:$src))]>;
970 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
971 "cvtsd2ss\t{$src, $dst|$dst, $src}",
972 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
973 Requires<[HasSSE2, OptForSize]>;
975 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
976 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
978 let Constraints = "$src1 = $dst" in
979 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
980 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
982 // Convert scalar single to scalar double
983 // SSE2 instructions with XS prefix
984 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
985 (ins FR32:$src1, FR32:$src2),
986 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
987 []>, XS, Requires<[HasAVX]>, VEX_4V;
988 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
989 (ins FR32:$src1, f32mem:$src2),
990 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
991 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
993 let Predicates = [HasAVX] in {
994 def : Pat<(f64 (fextend FR32:$src)),
995 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
996 def : Pat<(fextend (loadf32 addr:$src)),
997 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
998 def : Pat<(extloadf32 addr:$src),
999 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1002 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1003 "cvtss2sd\t{$src, $dst|$dst, $src}",
1004 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1005 Requires<[HasSSE2]>;
1006 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1007 "cvtss2sd\t{$src, $dst|$dst, $src}",
1008 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1009 Requires<[HasSSE2, OptForSize]>;
1011 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1012 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1013 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1014 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1015 VR128:$src2))]>, XS, VEX_4V,
1017 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1018 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1019 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1020 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1021 (load addr:$src2)))]>, XS, VEX_4V,
1023 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1024 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1025 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1026 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1027 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1028 VR128:$src2))]>, XS,
1029 Requires<[HasSSE2]>;
1030 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1031 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1032 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1033 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1034 (load addr:$src2)))]>, XS,
1035 Requires<[HasSSE2]>;
1038 def : Pat<(extloadf32 addr:$src),
1039 (CVTSS2SDrr (MOVSSrm addr:$src))>,
1040 Requires<[HasSSE2, OptForSpeed]>;
1042 // Convert doubleword to packed single/double fp
1043 // SSE2 instructions without OpSize prefix
1044 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1045 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1046 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1047 TB, VEX, Requires<[HasAVX]>;
1048 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1049 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1050 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1051 (bitconvert (memopv2i64 addr:$src))))]>,
1052 TB, VEX, Requires<[HasAVX]>;
1053 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1054 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1055 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1056 TB, Requires<[HasSSE2]>;
1057 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1058 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1059 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1060 (bitconvert (memopv2i64 addr:$src))))]>,
1061 TB, Requires<[HasSSE2]>;
1063 // FIXME: why the non-intrinsic version is described as SSE3?
1064 // SSE2 instructions with XS prefix
1065 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1066 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1067 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1068 XS, VEX, Requires<[HasAVX]>;
1069 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1070 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1071 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1072 (bitconvert (memopv2i64 addr:$src))))]>,
1073 XS, VEX, Requires<[HasAVX]>;
1074 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1075 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1076 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1077 XS, Requires<[HasSSE2]>;
1078 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1079 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1080 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1081 (bitconvert (memopv2i64 addr:$src))))]>,
1082 XS, Requires<[HasSSE2]>;
1085 // Convert packed single/double fp to doubleword
1086 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1087 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1088 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1089 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1090 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1091 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1092 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1093 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1094 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1095 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1096 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1097 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1099 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1100 "cvtps2dq\t{$src, $dst|$dst, $src}",
1101 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
1103 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1105 "cvtps2dq\t{$src, $dst|$dst, $src}",
1106 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1107 (memop addr:$src)))]>, VEX;
1108 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1109 "cvtps2dq\t{$src, $dst|$dst, $src}",
1110 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1111 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1112 "cvtps2dq\t{$src, $dst|$dst, $src}",
1113 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1114 (memop addr:$src)))]>;
1116 // SSE2 packed instructions with XD prefix
1117 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1118 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1119 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1120 XD, VEX, Requires<[HasAVX]>;
1121 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1122 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1123 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1124 (memop addr:$src)))]>,
1125 XD, VEX, Requires<[HasAVX]>;
1126 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1127 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1128 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1129 XD, Requires<[HasSSE2]>;
1130 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1131 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1132 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1133 (memop addr:$src)))]>,
1134 XD, Requires<[HasSSE2]>;
1137 // Convert with truncation packed single/double fp to doubleword
1138 // SSE2 packed instructions with XS prefix
1139 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1140 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1141 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1142 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1143 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1144 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1145 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1146 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1147 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1148 "cvttps2dq\t{$src, $dst|$dst, $src}",
1150 (int_x86_sse2_cvttps2dq VR128:$src))]>;
1151 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1152 "cvttps2dq\t{$src, $dst|$dst, $src}",
1154 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
1156 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1157 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1159 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1160 XS, VEX, Requires<[HasAVX]>;
1161 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1162 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1163 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1164 (memop addr:$src)))]>,
1165 XS, VEX, Requires<[HasAVX]>;
1167 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1168 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
1169 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1170 (CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
1172 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1173 (Int_VCVTDQ2PSrr VR128:$src)>, Requires<[HasAVX]>;
1174 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1175 (VCVTTPS2DQrr VR128:$src)>, Requires<[HasAVX]>;
1176 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1177 (VCVTDQ2PSYrr VR256:$src)>, Requires<[HasAVX]>;
1178 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1179 (VCVTTPS2DQYrr VR256:$src)>, Requires<[HasAVX]>;
1181 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
1183 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1184 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
1186 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
1188 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1189 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1190 (memop addr:$src)))]>, VEX;
1191 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1192 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1193 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1194 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1195 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1196 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1197 (memop addr:$src)))]>;
1199 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1200 // register, but the same isn't true when using memory operands instead.
1201 // Provide other assembly rr and rm forms to address this explicitly.
1202 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1203 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1204 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1205 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1208 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1209 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1210 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1211 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1214 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1215 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
1216 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1217 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1219 // Convert packed single to packed double
1220 let Predicates = [HasAVX] in {
1221 // SSE2 instructions without OpSize prefix
1222 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1223 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1224 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1225 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1226 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1227 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1228 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1229 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1231 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1232 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1233 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1234 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1236 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1237 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1238 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1239 VEX, Requires<[HasAVX]>;
1240 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1241 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1242 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1243 (load addr:$src)))]>,
1244 VEX, Requires<[HasAVX]>;
1245 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1246 "cvtps2pd\t{$src, $dst|$dst, $src}",
1247 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1248 TB, Requires<[HasSSE2]>;
1249 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1250 "cvtps2pd\t{$src, $dst|$dst, $src}",
1251 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1252 (load addr:$src)))]>,
1253 TB, Requires<[HasSSE2]>;
1255 // Convert packed double to packed single
1256 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1257 // register, but the same isn't true when using memory operands instead.
1258 // Provide other assembly rr and rm forms to address this explicitly.
1259 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1260 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1261 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1262 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1265 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1266 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1267 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1268 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1271 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1272 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1273 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1274 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1275 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1276 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1277 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1278 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1281 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1282 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1283 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1284 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1286 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1287 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1288 (memop addr:$src)))]>;
1289 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1290 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1291 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1292 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1293 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1294 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1295 (memop addr:$src)))]>;
1297 // AVX 256-bit register conversion intrinsics
1298 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1299 // whenever possible to avoid declaring two versions of each one.
1300 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1301 (VCVTDQ2PSYrr VR256:$src)>;
1302 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
1303 (VCVTDQ2PSYrm addr:$src)>;
1305 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1306 (VCVTPD2PSYrr VR256:$src)>;
1307 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1308 (VCVTPD2PSYrm addr:$src)>;
1310 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1311 (VCVTPS2DQYrr VR256:$src)>;
1312 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1313 (VCVTPS2DQYrm addr:$src)>;
1315 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1316 (VCVTPS2PDYrr VR128:$src)>;
1317 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1318 (VCVTPS2PDYrm addr:$src)>;
1320 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1321 (VCVTTPD2DQYrr VR256:$src)>;
1322 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1323 (VCVTTPD2DQYrm addr:$src)>;
1325 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1326 (VCVTTPS2DQYrr VR256:$src)>;
1327 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1328 (VCVTTPS2DQYrm addr:$src)>;
1330 // Match fround and fextend for 128/256-bit conversions
1331 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
1332 (VCVTPD2PSYrr VR256:$src)>;
1333 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
1334 (VCVTPD2PSYrm addr:$src)>;
1336 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
1337 (VCVTPS2PDYrr VR128:$src)>;
1338 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
1339 (VCVTPS2PDYrm addr:$src)>;
1341 //===----------------------------------------------------------------------===//
1342 // SSE 1 & 2 - Compare Instructions
1343 //===----------------------------------------------------------------------===//
1345 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1346 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1347 string asm, string asm_alt> {
1348 let isAsmParserOnly = 1 in {
1349 def rr : SIi8<0xC2, MRMSrcReg,
1350 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1353 def rm : SIi8<0xC2, MRMSrcMem,
1354 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1358 // Accept explicit immediate argument form instead of comparison code.
1359 def rr_alt : SIi8<0xC2, MRMSrcReg,
1360 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1363 def rm_alt : SIi8<0xC2, MRMSrcMem,
1364 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1368 let neverHasSideEffects = 1 in {
1369 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1370 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1371 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1373 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1374 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1375 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1379 let Constraints = "$src1 = $dst" in {
1380 def CMPSSrr : SIi8<0xC2, MRMSrcReg,
1381 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc),
1382 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1383 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2, imm:$cc))]>, XS;
1384 def CMPSSrm : SIi8<0xC2, MRMSrcMem,
1385 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc),
1386 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1387 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), (loadf32 addr:$src2), imm:$cc))]>, XS;
1388 def CMPSDrr : SIi8<0xC2, MRMSrcReg,
1389 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc),
1390 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1391 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2, imm:$cc))]>, XD;
1392 def CMPSDrm : SIi8<0xC2, MRMSrcMem,
1393 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc),
1394 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1395 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2), imm:$cc))]>, XD;
1397 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1398 def CMPSSrr_alt : SIi8<0xC2, MRMSrcReg,
1399 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
1400 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1401 def CMPSSrm_alt : SIi8<0xC2, MRMSrcMem,
1402 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
1403 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1404 def CMPSDrr_alt : SIi8<0xC2, MRMSrcReg,
1405 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
1406 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1407 def CMPSDrm_alt : SIi8<0xC2, MRMSrcMem,
1408 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
1409 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1412 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
1413 Intrinsic Int, string asm> {
1414 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1415 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1416 [(set VR128:$dst, (Int VR128:$src1,
1417 VR128:$src, imm:$cc))]>;
1418 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1419 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
1420 [(set VR128:$dst, (Int VR128:$src1,
1421 (load addr:$src), imm:$cc))]>;
1424 // Aliases to match intrinsics which expect XMM operand(s).
1425 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1426 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1428 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1429 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1431 let Constraints = "$src1 = $dst" in {
1432 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1433 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1434 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1435 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1439 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1440 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
1441 ValueType vt, X86MemOperand x86memop,
1442 PatFrag ld_frag, string OpcodeStr, Domain d> {
1443 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1444 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1445 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
1446 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
1447 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1448 [(set EFLAGS, (OpNode (vt RC:$src1),
1449 (ld_frag addr:$src2)))], d>;
1452 let Defs = [EFLAGS] in {
1453 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1454 "ucomiss", SSEPackedSingle>, VEX;
1455 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1456 "ucomisd", SSEPackedDouble>, OpSize, VEX;
1457 let Pattern = []<dag> in {
1458 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1459 "comiss", SSEPackedSingle>, VEX;
1460 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1461 "comisd", SSEPackedDouble>, OpSize, VEX;
1464 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1465 load, "ucomiss", SSEPackedSingle>, VEX;
1466 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1467 load, "ucomisd", SSEPackedDouble>, OpSize, VEX;
1469 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
1470 load, "comiss", SSEPackedSingle>, VEX;
1471 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
1472 load, "comisd", SSEPackedDouble>, OpSize, VEX;
1473 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1474 "ucomiss", SSEPackedSingle>, TB;
1475 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1476 "ucomisd", SSEPackedDouble>, TB, OpSize;
1478 let Pattern = []<dag> in {
1479 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1480 "comiss", SSEPackedSingle>, TB;
1481 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1482 "comisd", SSEPackedDouble>, TB, OpSize;
1485 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1486 load, "ucomiss", SSEPackedSingle>, TB;
1487 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1488 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
1490 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
1491 "comiss", SSEPackedSingle>, TB;
1492 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
1493 "comisd", SSEPackedDouble>, TB, OpSize;
1494 } // Defs = [EFLAGS]
1496 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
1497 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
1498 Intrinsic Int, string asm, string asm_alt,
1500 let isAsmParserOnly = 1 in {
1501 def rri : PIi8<0xC2, MRMSrcReg,
1502 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1503 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1504 def rmi : PIi8<0xC2, MRMSrcMem,
1505 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1506 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1509 // Accept explicit immediate argument form instead of comparison code.
1510 def rri_alt : PIi8<0xC2, MRMSrcReg,
1511 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1513 def rmi_alt : PIi8<0xC2, MRMSrcMem,
1514 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1518 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1519 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1520 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1521 SSEPackedSingle>, VEX_4V;
1522 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1523 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1524 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1525 SSEPackedDouble>, OpSize, VEX_4V;
1526 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
1527 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1528 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1529 SSEPackedSingle>, VEX_4V;
1530 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
1531 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1532 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1533 SSEPackedDouble>, OpSize, VEX_4V;
1534 let Constraints = "$src1 = $dst" in {
1535 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1536 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1537 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1538 SSEPackedSingle>, TB;
1539 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1540 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1541 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1542 SSEPackedDouble>, TB, OpSize;
1545 let Predicates = [HasSSE1] in {
1546 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1547 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1548 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1549 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1552 let Predicates = [HasSSE2] in {
1553 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1554 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1555 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1556 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1559 let Predicates = [HasAVX] in {
1560 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1561 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1562 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1563 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1564 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1565 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1566 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1567 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1569 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
1570 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
1571 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
1572 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
1573 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
1574 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
1575 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
1576 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
1579 //===----------------------------------------------------------------------===//
1580 // SSE 1 & 2 - Shuffle Instructions
1581 //===----------------------------------------------------------------------===//
1583 /// sse12_shuffle - sse 1 & 2 shuffle instructions
1584 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
1585 ValueType vt, string asm, PatFrag mem_frag,
1586 Domain d, bit IsConvertibleToThreeAddress = 0> {
1587 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
1588 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
1589 [(set RC:$dst, (vt (shufp:$src3
1590 RC:$src1, (mem_frag addr:$src2))))], d>;
1591 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
1592 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
1593 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
1595 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
1598 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1599 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1600 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
1601 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
1602 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1603 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
1604 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1605 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1606 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1607 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
1608 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1609 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1611 let Constraints = "$src1 = $dst" in {
1612 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1613 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1614 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
1616 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1617 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1618 memopv2f64, SSEPackedDouble>, TB, OpSize;
1621 let Predicates = [HasSSE1] in {
1622 def : Pat<(v4f32 (X86Shufps VR128:$src1,
1623 (memopv4f32 addr:$src2), (i8 imm:$imm))),
1624 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
1625 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1626 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
1627 def : Pat<(v4i32 (X86Shufps VR128:$src1,
1628 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
1629 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
1630 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1631 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
1632 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
1633 // fall back to this for SSE1)
1634 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
1635 (SHUFPSrri VR128:$src2, VR128:$src1,
1636 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1637 // Special unary SHUFPSrri case.
1638 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
1639 (SHUFPSrri VR128:$src1, VR128:$src1,
1640 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1643 let Predicates = [HasSSE2] in {
1644 // Special binary v4i32 shuffle cases with SHUFPS.
1645 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
1646 (SHUFPSrri VR128:$src1, VR128:$src2,
1647 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1648 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
1649 (bc_v4i32 (memopv2i64 addr:$src2)))),
1650 (SHUFPSrmi VR128:$src1, addr:$src2,
1651 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1652 // Special unary SHUFPDrri cases.
1653 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
1654 (SHUFPDrri VR128:$src1, VR128:$src1,
1655 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1656 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
1657 (SHUFPDrri VR128:$src1, VR128:$src1,
1658 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1659 // Special binary v2i64 shuffle cases using SHUFPDrri.
1660 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
1661 (SHUFPDrri VR128:$src1, VR128:$src2,
1662 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1663 // Generic SHUFPD patterns
1664 def : Pat<(v2f64 (X86Shufps VR128:$src1,
1665 (memopv2f64 addr:$src2), (i8 imm:$imm))),
1666 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
1667 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1668 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
1669 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1670 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
1673 let Predicates = [HasAVX] in {
1674 def : Pat<(v4f32 (X86Shufps VR128:$src1,
1675 (memopv4f32 addr:$src2), (i8 imm:$imm))),
1676 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
1677 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1678 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
1679 def : Pat<(v4i32 (X86Shufps VR128:$src1,
1680 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
1681 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
1682 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1683 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
1684 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
1685 // fall back to this for SSE1)
1686 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
1687 (VSHUFPSrri VR128:$src2, VR128:$src1,
1688 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1689 // Special unary SHUFPSrri case.
1690 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
1691 (VSHUFPSrri VR128:$src1, VR128:$src1,
1692 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1693 // Special binary v4i32 shuffle cases with SHUFPS.
1694 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
1695 (VSHUFPSrri VR128:$src1, VR128:$src2,
1696 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1697 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
1698 (bc_v4i32 (memopv2i64 addr:$src2)))),
1699 (VSHUFPSrmi VR128:$src1, addr:$src2,
1700 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1701 // Special unary SHUFPDrri cases.
1702 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
1703 (VSHUFPDrri VR128:$src1, VR128:$src1,
1704 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1705 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
1706 (VSHUFPDrri VR128:$src1, VR128:$src1,
1707 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1708 // Special binary v2i64 shuffle cases using SHUFPDrri.
1709 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
1710 (VSHUFPDrri VR128:$src1, VR128:$src2,
1711 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1712 // Generic VSHUFPD patterns
1713 def : Pat<(v2f64 (X86Shufps VR128:$src1,
1714 (memopv2f64 addr:$src2), (i8 imm:$imm))),
1715 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
1716 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1717 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
1718 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1719 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
1722 //===----------------------------------------------------------------------===//
1723 // SSE 1 & 2 - Unpack Instructions
1724 //===----------------------------------------------------------------------===//
1726 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
1727 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
1728 PatFrag mem_frag, RegisterClass RC,
1729 X86MemOperand x86memop, string asm,
1731 def rr : PI<opc, MRMSrcReg,
1732 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1734 (vt (OpNode RC:$src1, RC:$src2)))], d>;
1735 def rm : PI<opc, MRMSrcMem,
1736 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1738 (vt (OpNode RC:$src1,
1739 (mem_frag addr:$src2))))], d>;
1742 let AddedComplexity = 10 in {
1743 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1744 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1745 SSEPackedSingle>, VEX_4V;
1746 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1747 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1748 SSEPackedDouble>, OpSize, VEX_4V;
1749 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1750 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1751 SSEPackedSingle>, VEX_4V;
1752 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1753 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1754 SSEPackedDouble>, OpSize, VEX_4V;
1756 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
1757 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1758 SSEPackedSingle>, VEX_4V;
1759 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
1760 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1761 SSEPackedDouble>, OpSize, VEX_4V;
1762 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
1763 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1764 SSEPackedSingle>, VEX_4V;
1765 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
1766 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1767 SSEPackedDouble>, OpSize, VEX_4V;
1769 let Constraints = "$src1 = $dst" in {
1770 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1771 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1772 SSEPackedSingle>, TB;
1773 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1774 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1775 SSEPackedDouble>, TB, OpSize;
1776 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1777 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1778 SSEPackedSingle>, TB;
1779 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1780 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1781 SSEPackedDouble>, TB, OpSize;
1782 } // Constraints = "$src1 = $dst"
1783 } // AddedComplexity
1785 let Predicates = [HasSSE1] in {
1786 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
1787 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
1788 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
1789 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
1790 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
1791 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
1792 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
1793 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
1796 let Predicates = [HasSSE2] in {
1797 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
1798 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
1799 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
1800 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
1801 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
1802 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
1803 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
1804 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
1806 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
1807 // problem is during lowering, where it's not possible to recognize the load
1808 // fold cause it has two uses through a bitcast. One use disappears at isel
1809 // time and the fold opportunity reappears.
1810 def : Pat<(v2f64 (X86Movddup VR128:$src)),
1811 (UNPCKLPDrr VR128:$src, VR128:$src)>;
1813 let AddedComplexity = 10 in
1814 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
1815 (UNPCKLPDrr VR128:$src, VR128:$src)>;
1818 let Predicates = [HasAVX] in {
1819 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
1820 (VUNPCKLPSrm VR128:$src1, addr:$src2)>;
1821 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
1822 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>;
1823 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
1824 (VUNPCKHPSrm VR128:$src1, addr:$src2)>;
1825 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
1826 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>;
1828 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
1829 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
1830 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
1831 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
1832 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
1833 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
1834 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, (memopv8i32 addr:$src2))),
1835 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
1836 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, (memopv8f32 addr:$src2))),
1837 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
1838 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
1839 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
1840 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, (memopv8i32 addr:$src2))),
1841 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
1842 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
1843 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
1845 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
1846 (VUNPCKLPDrm VR128:$src1, addr:$src2)>;
1847 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
1848 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>;
1849 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
1850 (VUNPCKHPDrm VR128:$src1, addr:$src2)>;
1851 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
1852 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>;
1854 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
1855 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
1856 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
1857 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
1858 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, (memopv4i64 addr:$src2))),
1859 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
1860 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
1861 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
1862 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, (memopv4f64 addr:$src2))),
1863 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
1864 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
1865 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
1866 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, (memopv4i64 addr:$src2))),
1867 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
1868 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
1869 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
1871 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
1872 // problem is during lowering, where it's not possible to recognize the load
1873 // fold cause it has two uses through a bitcast. One use disappears at isel
1874 // time and the fold opportunity reappears.
1875 def : Pat<(v2f64 (X86Movddup VR128:$src)),
1876 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
1877 let AddedComplexity = 10 in
1878 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
1879 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
1882 //===----------------------------------------------------------------------===//
1883 // SSE 1 & 2 - Extract Floating-Point Sign mask
1884 //===----------------------------------------------------------------------===//
1886 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
1887 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
1889 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
1890 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1891 [(set GR32:$dst, (Int RC:$src))], d>;
1892 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
1893 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
1896 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
1897 SSEPackedSingle>, TB;
1898 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
1899 SSEPackedDouble>, TB, OpSize;
1901 def : Pat<(i32 (X86fgetsign FR32:$src)),
1902 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
1903 sub_ss))>, Requires<[HasSSE1]>;
1904 def : Pat<(i64 (X86fgetsign FR32:$src)),
1905 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
1906 sub_ss))>, Requires<[HasSSE1]>;
1907 def : Pat<(i32 (X86fgetsign FR64:$src)),
1908 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
1909 sub_sd))>, Requires<[HasSSE2]>;
1910 def : Pat<(i64 (X86fgetsign FR64:$src)),
1911 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
1912 sub_sd))>, Requires<[HasSSE2]>;
1914 let Predicates = [HasAVX] in {
1915 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
1916 "movmskps", SSEPackedSingle>, TB, VEX;
1917 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
1918 "movmskpd", SSEPackedDouble>, TB, OpSize,
1920 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
1921 "movmskps", SSEPackedSingle>, TB, VEX;
1922 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
1923 "movmskpd", SSEPackedDouble>, TB, OpSize,
1926 def : Pat<(i32 (X86fgetsign FR32:$src)),
1927 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
1929 def : Pat<(i64 (X86fgetsign FR32:$src)),
1930 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
1932 def : Pat<(i32 (X86fgetsign FR64:$src)),
1933 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
1935 def : Pat<(i64 (X86fgetsign FR64:$src)),
1936 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
1940 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1941 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1942 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1943 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1945 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1946 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1947 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1948 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1952 //===----------------------------------------------------------------------===//
1953 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
1954 //===----------------------------------------------------------------------===//
1956 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
1957 // names that start with 'Fs'.
1959 // Alias instructions that map fld0 to pxor for sse.
1960 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1961 canFoldAsLoad = 1 in {
1962 // FIXME: Set encoding to pseudo!
1963 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1964 [(set FR32:$dst, fp32imm0)]>,
1965 Requires<[HasSSE1]>, TB, OpSize;
1966 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1967 [(set FR64:$dst, fpimm0)]>,
1968 Requires<[HasSSE2]>, TB, OpSize;
1969 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1970 [(set FR32:$dst, fp32imm0)]>,
1971 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1972 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1973 [(set FR64:$dst, fpimm0)]>,
1974 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1977 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1978 // bits are disregarded.
1979 let neverHasSideEffects = 1 in {
1980 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1981 "movaps\t{$src, $dst|$dst, $src}", []>;
1982 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1983 "movapd\t{$src, $dst|$dst, $src}", []>;
1986 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1987 // bits are disregarded.
1988 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1989 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1990 "movaps\t{$src, $dst|$dst, $src}",
1991 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
1992 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1993 "movapd\t{$src, $dst|$dst, $src}",
1994 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1997 //===----------------------------------------------------------------------===//
1998 // SSE 1 & 2 - Logical Instructions
1999 //===----------------------------------------------------------------------===//
2001 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2003 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2005 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2006 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, TB, VEX_4V;
2008 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2009 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, TB, OpSize, VEX_4V;
2011 let Constraints = "$src1 = $dst" in {
2012 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2013 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
2015 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2016 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
2020 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2021 let mayLoad = 0 in {
2022 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
2023 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
2024 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
2027 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2028 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
2030 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2032 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2034 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2035 // are all promoted to v2i64, and the patterns are covered by the int
2036 // version. This is needed in SSE only, because v2i64 isn't supported on
2037 // SSE1, but only on SSE2.
2038 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2039 !strconcat(OpcodeStr, "ps"), f128mem, [],
2040 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2041 (memopv2i64 addr:$src2)))], 0>, TB, VEX_4V;
2043 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2044 !strconcat(OpcodeStr, "pd"), f128mem,
2045 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2046 (bc_v2i64 (v2f64 VR128:$src2))))],
2047 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2048 (memopv2i64 addr:$src2)))], 0>,
2050 let Constraints = "$src1 = $dst" in {
2051 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2052 !strconcat(OpcodeStr, "ps"), f128mem,
2053 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2054 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2055 (memopv2i64 addr:$src2)))]>, TB;
2057 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2058 !strconcat(OpcodeStr, "pd"), f128mem,
2059 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2060 (bc_v2i64 (v2f64 VR128:$src2))))],
2061 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2062 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2066 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2068 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2070 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2071 !strconcat(OpcodeStr, "ps"), f256mem,
2072 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2073 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2074 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2076 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2077 !strconcat(OpcodeStr, "pd"), f256mem,
2078 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2079 (bc_v4i64 (v4f64 VR256:$src2))))],
2080 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2081 (memopv4i64 addr:$src2)))], 0>,
2085 // AVX 256-bit packed logical ops forms
2086 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2087 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2088 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2089 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2091 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2092 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2093 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2094 let isCommutable = 0 in
2095 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2097 //===----------------------------------------------------------------------===//
2098 // SSE 1 & 2 - Arithmetic Instructions
2099 //===----------------------------------------------------------------------===//
2101 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2104 /// In addition, we also have a special variant of the scalar form here to
2105 /// represent the associated intrinsic operation. This form is unlike the
2106 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2107 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2109 /// These three forms can each be reg+reg or reg+mem.
2112 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2114 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2116 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2117 OpNode, FR32, f32mem, Is2Addr>, XS;
2118 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2119 OpNode, FR64, f64mem, Is2Addr>, XD;
2122 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2124 let mayLoad = 0 in {
2125 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2126 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
2127 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2128 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
2132 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2134 let mayLoad = 0 in {
2135 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2136 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
2137 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2138 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
2142 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2144 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2145 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
2146 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2147 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
2150 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2152 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2153 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2154 SSEPackedSingle, Is2Addr>, TB;
2156 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2157 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2158 SSEPackedDouble, Is2Addr>, TB, OpSize;
2161 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
2162 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2163 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2164 SSEPackedSingle, 0>, TB;
2166 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2167 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2168 SSEPackedDouble, 0>, TB, OpSize;
2171 // Binary Arithmetic instructions
2172 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
2173 basic_sse12_fp_binop_s_int<0x58, "add", 0>,
2174 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
2175 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
2176 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
2177 basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
2178 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
2179 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
2181 let isCommutable = 0 in {
2182 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
2183 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
2184 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
2185 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
2186 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
2187 basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
2188 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
2189 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
2190 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
2191 basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
2192 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
2193 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
2194 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
2195 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
2196 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
2197 basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
2198 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
2199 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
2200 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
2201 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
2204 let Constraints = "$src1 = $dst" in {
2205 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
2206 basic_sse12_fp_binop_p<0x58, "add", fadd>,
2207 basic_sse12_fp_binop_s_int<0x58, "add">;
2208 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
2209 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
2210 basic_sse12_fp_binop_s_int<0x59, "mul">;
2212 let isCommutable = 0 in {
2213 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
2214 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
2215 basic_sse12_fp_binop_s_int<0x5C, "sub">;
2216 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
2217 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
2218 basic_sse12_fp_binop_s_int<0x5E, "div">;
2219 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
2220 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
2221 basic_sse12_fp_binop_s_int<0x5F, "max">,
2222 basic_sse12_fp_binop_p_int<0x5F, "max">;
2223 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
2224 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
2225 basic_sse12_fp_binop_s_int<0x5D, "min">,
2226 basic_sse12_fp_binop_p_int<0x5D, "min">;
2231 /// In addition, we also have a special variant of the scalar form here to
2232 /// represent the associated intrinsic operation. This form is unlike the
2233 /// plain scalar form, in that it takes an entire vector (instead of a
2234 /// scalar) and leaves the top elements undefined.
2236 /// And, we have a special variant form for a full-vector intrinsic form.
2238 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2239 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2240 SDNode OpNode, Intrinsic F32Int> {
2241 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2242 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2243 [(set FR32:$dst, (OpNode FR32:$src))]>;
2244 // For scalar unary operations, fold a load into the operation
2245 // only in OptForSize mode. It eliminates an instruction, but it also
2246 // eliminates a whole-register clobber (the load), so it introduces a
2247 // partial register update condition.
2248 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
2249 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2250 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
2251 Requires<[HasSSE1, OptForSize]>;
2252 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2253 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2254 [(set VR128:$dst, (F32Int VR128:$src))]>;
2255 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
2256 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2257 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
2260 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
2261 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2262 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
2263 !strconcat(OpcodeStr,
2264 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2265 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
2266 !strconcat(OpcodeStr,
2267 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2268 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
2269 (ins ssmem:$src1, VR128:$src2),
2270 !strconcat(OpcodeStr,
2271 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2274 /// sse1_fp_unop_p - SSE1 unops in packed form.
2275 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2276 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2277 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2278 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
2279 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2280 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2281 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
2284 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
2285 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2286 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2287 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2288 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
2289 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2290 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2291 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
2294 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
2295 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2296 Intrinsic V4F32Int> {
2297 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2298 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2299 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
2300 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2301 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2302 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
2305 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
2306 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2307 Intrinsic V4F32Int> {
2308 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2309 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2310 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
2311 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2312 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2313 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
2316 /// sse2_fp_unop_s - SSE2 unops in scalar form.
2317 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
2318 SDNode OpNode, Intrinsic F64Int> {
2319 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
2320 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2321 [(set FR64:$dst, (OpNode FR64:$src))]>;
2322 // See the comments in sse1_fp_unop_s for why this is OptForSize.
2323 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
2324 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2325 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
2326 Requires<[HasSSE2, OptForSize]>;
2327 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2328 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2329 [(set VR128:$dst, (F64Int VR128:$src))]>;
2330 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
2331 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2332 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
2335 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
2336 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2337 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
2338 !strconcat(OpcodeStr,
2339 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2340 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
2341 !strconcat(OpcodeStr,
2342 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2343 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
2344 (ins VR128:$src1, sdmem:$src2),
2345 !strconcat(OpcodeStr,
2346 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2349 /// sse2_fp_unop_p - SSE2 unops in vector forms.
2350 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
2352 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2353 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2354 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
2355 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2356 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2357 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
2360 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
2361 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2362 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2363 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2364 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
2365 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2366 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2367 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
2370 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
2371 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2372 Intrinsic V2F64Int> {
2373 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2374 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2375 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
2376 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2377 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2378 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
2381 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
2382 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2383 Intrinsic V2F64Int> {
2384 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2385 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2386 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
2387 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2388 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2389 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
2392 let Predicates = [HasAVX] in {
2394 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
2395 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V;
2397 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
2398 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
2399 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
2400 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
2401 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
2402 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
2403 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
2404 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
2407 // Reciprocal approximations. Note that these typically require refinement
2408 // in order to obtain suitable precision.
2409 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V;
2410 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
2411 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
2412 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
2413 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
2415 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V;
2416 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
2417 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
2418 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
2419 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
2422 def : Pat<(f32 (fsqrt FR32:$src)),
2423 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
2424 def : Pat<(f32 (fsqrt (load addr:$src))),
2425 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
2426 Requires<[HasAVX, OptForSize]>;
2427 def : Pat<(f64 (fsqrt FR64:$src)),
2428 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
2429 def : Pat<(f64 (fsqrt (load addr:$src))),
2430 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
2431 Requires<[HasAVX, OptForSize]>;
2433 def : Pat<(f32 (X86frsqrt FR32:$src)),
2434 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
2435 def : Pat<(f32 (X86frsqrt (load addr:$src))),
2436 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
2437 Requires<[HasAVX, OptForSize]>;
2439 def : Pat<(f32 (X86frcp FR32:$src)),
2440 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
2441 def : Pat<(f32 (X86frcp (load addr:$src))),
2442 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
2443 Requires<[HasAVX, OptForSize]>;
2445 let Predicates = [HasAVX] in {
2446 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
2447 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2448 (VSQRTSSr (f32 (IMPLICIT_DEF)),
2449 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
2451 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
2452 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2454 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
2455 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
2456 (VSQRTSDr (f64 (IMPLICIT_DEF)),
2457 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
2459 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
2460 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
2462 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
2463 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2464 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
2465 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
2467 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
2468 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2470 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
2471 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2472 (VRCPSSr (f32 (IMPLICIT_DEF)),
2473 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
2475 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
2476 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2480 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
2481 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
2482 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
2483 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
2484 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
2485 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
2487 // Reciprocal approximations. Note that these typically require refinement
2488 // in order to obtain suitable precision.
2489 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
2490 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
2491 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
2492 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
2493 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
2494 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
2496 // There is no f64 version of the reciprocal approximation instructions.
2498 //===----------------------------------------------------------------------===//
2499 // SSE 1 & 2 - Non-temporal stores
2500 //===----------------------------------------------------------------------===//
2502 let AddedComplexity = 400 in { // Prefer non-temporal versions
2503 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
2504 (ins f128mem:$dst, VR128:$src),
2505 "movntps\t{$src, $dst|$dst, $src}",
2506 [(alignednontemporalstore (v4f32 VR128:$src),
2508 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
2509 (ins f128mem:$dst, VR128:$src),
2510 "movntpd\t{$src, $dst|$dst, $src}",
2511 [(alignednontemporalstore (v2f64 VR128:$src),
2513 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
2514 (ins f128mem:$dst, VR128:$src),
2515 "movntdq\t{$src, $dst|$dst, $src}",
2516 [(alignednontemporalstore (v2f64 VR128:$src),
2519 let ExeDomain = SSEPackedInt in
2520 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
2521 (ins f128mem:$dst, VR128:$src),
2522 "movntdq\t{$src, $dst|$dst, $src}",
2523 [(alignednontemporalstore (v4f32 VR128:$src),
2526 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
2527 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
2529 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
2530 (ins f256mem:$dst, VR256:$src),
2531 "movntps\t{$src, $dst|$dst, $src}",
2532 [(alignednontemporalstore (v8f32 VR256:$src),
2534 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
2535 (ins f256mem:$dst, VR256:$src),
2536 "movntpd\t{$src, $dst|$dst, $src}",
2537 [(alignednontemporalstore (v4f64 VR256:$src),
2539 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
2540 (ins f256mem:$dst, VR256:$src),
2541 "movntdq\t{$src, $dst|$dst, $src}",
2542 [(alignednontemporalstore (v4f64 VR256:$src),
2544 let ExeDomain = SSEPackedInt in
2545 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
2546 (ins f256mem:$dst, VR256:$src),
2547 "movntdq\t{$src, $dst|$dst, $src}",
2548 [(alignednontemporalstore (v8f32 VR256:$src),
2552 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
2553 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
2554 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
2555 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
2556 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
2557 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
2559 let AddedComplexity = 400 in { // Prefer non-temporal versions
2560 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2561 "movntps\t{$src, $dst|$dst, $src}",
2562 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2563 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2564 "movntpd\t{$src, $dst|$dst, $src}",
2565 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2567 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2568 "movntdq\t{$src, $dst|$dst, $src}",
2569 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
2571 let ExeDomain = SSEPackedInt in
2572 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2573 "movntdq\t{$src, $dst|$dst, $src}",
2574 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2576 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
2577 (MOVNTDQmr addr:$dst, VR128:$src)>;
2579 // There is no AVX form for instructions below this point
2580 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2581 "movnti{l}\t{$src, $dst|$dst, $src}",
2582 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
2583 TB, Requires<[HasSSE2]>;
2584 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2585 "movnti{q}\t{$src, $dst|$dst, $src}",
2586 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
2587 TB, Requires<[HasSSE2]>;
2590 //===----------------------------------------------------------------------===//
2591 // SSE 1 & 2 - Prefetch and memory fence
2592 //===----------------------------------------------------------------------===//
2594 // Prefetch intrinsic.
2595 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
2596 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
2597 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
2598 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
2599 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
2600 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
2601 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
2602 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
2604 // Load, store, and memory fence
2605 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
2606 TB, Requires<[HasSSE1]>;
2607 def : Pat<(X86SFence), (SFENCE)>;
2609 //===----------------------------------------------------------------------===//
2610 // SSE 1 & 2 - Load/Store XCSR register
2611 //===----------------------------------------------------------------------===//
2613 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2614 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
2615 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2616 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
2618 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2619 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
2620 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2621 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
2623 //===---------------------------------------------------------------------===//
2624 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
2625 //===---------------------------------------------------------------------===//
2627 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2629 let neverHasSideEffects = 1 in {
2630 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2631 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2632 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2633 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2635 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2636 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2637 def VMOVDQUYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2638 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2640 let canFoldAsLoad = 1, mayLoad = 1 in {
2641 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2642 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2643 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2644 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2645 let Predicates = [HasAVX] in {
2646 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2647 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2648 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2649 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2653 let mayStore = 1 in {
2654 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
2655 (ins i128mem:$dst, VR128:$src),
2656 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2657 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
2658 (ins i256mem:$dst, VR256:$src),
2659 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2660 let Predicates = [HasAVX] in {
2661 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2662 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2663 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
2664 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2668 let neverHasSideEffects = 1 in
2669 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2670 "movdqa\t{$src, $dst|$dst, $src}", []>;
2672 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2673 "movdqu\t{$src, $dst|$dst, $src}",
2674 []>, XS, Requires<[HasSSE2]>;
2676 let canFoldAsLoad = 1, mayLoad = 1 in {
2677 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2678 "movdqa\t{$src, $dst|$dst, $src}",
2679 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
2680 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2681 "movdqu\t{$src, $dst|$dst, $src}",
2682 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2683 XS, Requires<[HasSSE2]>;
2686 let mayStore = 1 in {
2687 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2688 "movdqa\t{$src, $dst|$dst, $src}",
2689 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
2690 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2691 "movdqu\t{$src, $dst|$dst, $src}",
2692 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2693 XS, Requires<[HasSSE2]>;
2696 // Intrinsic forms of MOVDQU load and store
2697 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2698 "vmovdqu\t{$src, $dst|$dst, $src}",
2699 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2700 XS, VEX, Requires<[HasAVX]>;
2702 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2703 "movdqu\t{$src, $dst|$dst, $src}",
2704 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2705 XS, Requires<[HasSSE2]>;
2707 } // ExeDomain = SSEPackedInt
2709 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
2710 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
2711 (VMOVDQUYmr addr:$dst, VR256:$src)>;
2713 //===---------------------------------------------------------------------===//
2714 // SSE2 - Packed Integer Arithmetic Instructions
2715 //===---------------------------------------------------------------------===//
2717 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2719 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2720 bit IsCommutable = 0, bit Is2Addr = 1> {
2721 let isCommutable = IsCommutable in
2722 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2723 (ins VR128:$src1, VR128:$src2),
2725 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2726 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2727 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2728 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2729 (ins VR128:$src1, i128mem:$src2),
2731 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2732 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2733 [(set VR128:$dst, (IntId VR128:$src1,
2734 (bitconvert (memopv2i64 addr:$src2))))]>;
2737 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2738 string OpcodeStr, Intrinsic IntId,
2739 Intrinsic IntId2, bit Is2Addr = 1> {
2740 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2741 (ins VR128:$src1, VR128:$src2),
2743 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2744 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2745 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2746 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2747 (ins VR128:$src1, i128mem:$src2),
2749 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2750 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2751 [(set VR128:$dst, (IntId VR128:$src1,
2752 (bitconvert (memopv2i64 addr:$src2))))]>;
2753 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2754 (ins VR128:$src1, i32i8imm:$src2),
2756 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2757 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2758 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2761 /// PDI_binop_rm - Simple SSE2 binary operator.
2762 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2763 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
2764 let isCommutable = IsCommutable in
2765 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2766 (ins VR128:$src1, VR128:$src2),
2768 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2769 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2770 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2771 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2772 (ins VR128:$src1, i128mem:$src2),
2774 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2775 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2776 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2777 (bitconvert (memopv2i64 addr:$src2)))))]>;
2780 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2782 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2783 /// to collapse (bitconvert VT to VT) into its operand.
2785 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2786 bit IsCommutable = 0, bit Is2Addr = 1> {
2787 let isCommutable = IsCommutable in
2788 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2789 (ins VR128:$src1, VR128:$src2),
2791 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2792 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2793 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
2794 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2795 (ins VR128:$src1, i128mem:$src2),
2797 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2798 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2799 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
2802 } // ExeDomain = SSEPackedInt
2804 // 128-bit Integer Arithmetic
2806 let Predicates = [HasAVX] in {
2807 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
2808 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
2809 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
2810 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
2811 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
2812 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
2813 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
2814 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
2815 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
2818 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
2820 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
2822 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
2824 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
2826 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
2828 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
2830 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
2832 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
2834 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
2836 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
2838 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
2840 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
2842 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
2844 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
2846 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
2848 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
2850 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
2852 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
2854 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
2858 let Constraints = "$src1 = $dst" in {
2859 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2860 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2861 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2862 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2863 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2864 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2865 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2866 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2867 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2870 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2871 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2872 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2873 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2874 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2875 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2876 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2877 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2878 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2879 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
2880 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2881 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2882 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2883 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2884 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2885 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2886 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2887 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2888 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2890 } // Constraints = "$src1 = $dst"
2892 //===---------------------------------------------------------------------===//
2893 // SSE2 - Packed Integer Logical Instructions
2894 //===---------------------------------------------------------------------===//
2896 let Predicates = [HasAVX] in {
2897 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
2898 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
2900 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
2901 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
2903 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
2904 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
2907 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
2908 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
2910 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
2911 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
2913 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
2914 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
2917 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
2918 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
2920 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
2921 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
2924 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
2925 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
2926 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
2928 let ExeDomain = SSEPackedInt in {
2929 let neverHasSideEffects = 1 in {
2930 // 128-bit logical shifts.
2931 def VPSLLDQri : PDIi8<0x73, MRM7r,
2932 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2933 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2935 def VPSRLDQri : PDIi8<0x73, MRM3r,
2936 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2937 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2939 // PSRADQri doesn't exist in SSE[1-3].
2941 def VPANDNrr : PDI<0xDF, MRMSrcReg,
2942 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2943 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2945 (v2i64 (X86andnp VR128:$src1, VR128:$src2)))]>,VEX_4V;
2947 def VPANDNrm : PDI<0xDF, MRMSrcMem,
2948 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2949 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2950 [(set VR128:$dst, (X86andnp VR128:$src1,
2951 (memopv2i64 addr:$src2)))]>, VEX_4V;
2955 let Constraints = "$src1 = $dst" in {
2956 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2957 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2958 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2959 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2960 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2961 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2963 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2964 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2965 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2966 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2967 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2968 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2970 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2971 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2972 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2973 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2975 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2976 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
2977 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2979 let ExeDomain = SSEPackedInt in {
2980 let neverHasSideEffects = 1 in {
2981 // 128-bit logical shifts.
2982 def PSLLDQri : PDIi8<0x73, MRM7r,
2983 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2984 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2985 def PSRLDQri : PDIi8<0x73, MRM3r,
2986 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2987 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2988 // PSRADQri doesn't exist in SSE[1-3].
2990 def PANDNrr : PDI<0xDF, MRMSrcReg,
2991 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2992 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2994 def PANDNrm : PDI<0xDF, MRMSrcMem,
2995 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2996 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2998 } // Constraints = "$src1 = $dst"
3000 let Predicates = [HasAVX] in {
3001 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3002 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3003 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3004 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3005 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3006 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
3007 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3008 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
3009 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3010 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3012 // Shift up / down and insert zero's.
3013 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3014 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3015 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3016 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3019 let Predicates = [HasSSE2] in {
3020 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3021 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3022 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3023 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3024 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3025 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
3026 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3027 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
3028 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3029 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3031 // Shift up / down and insert zero's.
3032 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3033 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3034 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3035 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3038 //===---------------------------------------------------------------------===//
3039 // SSE2 - Packed Integer Comparison Instructions
3040 //===---------------------------------------------------------------------===//
3042 let Predicates = [HasAVX] in {
3043 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
3045 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
3047 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
3049 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
3051 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
3053 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
3056 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3057 (VPCMPEQBrr VR128:$src1, VR128:$src2)>;
3058 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
3059 (VPCMPEQBrm VR128:$src1, addr:$src2)>;
3060 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3061 (VPCMPEQWrr VR128:$src1, VR128:$src2)>;
3062 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
3063 (VPCMPEQWrm VR128:$src1, addr:$src2)>;
3064 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3065 (VPCMPEQDrr VR128:$src1, VR128:$src2)>;
3066 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
3067 (VPCMPEQDrm VR128:$src1, addr:$src2)>;
3069 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3070 (VPCMPGTBrr VR128:$src1, VR128:$src2)>;
3071 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
3072 (VPCMPGTBrm VR128:$src1, addr:$src2)>;
3073 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3074 (VPCMPGTWrr VR128:$src1, VR128:$src2)>;
3075 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
3076 (VPCMPGTWrm VR128:$src1, addr:$src2)>;
3077 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3078 (VPCMPGTDrr VR128:$src1, VR128:$src2)>;
3079 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
3080 (VPCMPGTDrm VR128:$src1, addr:$src2)>;
3083 let Constraints = "$src1 = $dst" in {
3084 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
3085 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
3086 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
3087 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
3088 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
3089 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
3090 } // Constraints = "$src1 = $dst"
3092 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3093 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
3094 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
3095 (PCMPEQBrm VR128:$src1, addr:$src2)>;
3096 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3097 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
3098 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
3099 (PCMPEQWrm VR128:$src1, addr:$src2)>;
3100 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3101 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
3102 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
3103 (PCMPEQDrm VR128:$src1, addr:$src2)>;
3105 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3106 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
3107 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
3108 (PCMPGTBrm VR128:$src1, addr:$src2)>;
3109 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3110 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
3111 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
3112 (PCMPGTWrm VR128:$src1, addr:$src2)>;
3113 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3114 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
3115 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
3116 (PCMPGTDrm VR128:$src1, addr:$src2)>;
3118 //===---------------------------------------------------------------------===//
3119 // SSE2 - Packed Integer Pack Instructions
3120 //===---------------------------------------------------------------------===//
3122 let Predicates = [HasAVX] in {
3123 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
3125 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
3127 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
3131 let Constraints = "$src1 = $dst" in {
3132 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
3133 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
3134 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
3135 } // Constraints = "$src1 = $dst"
3137 //===---------------------------------------------------------------------===//
3138 // SSE2 - Packed Integer Shuffle Instructions
3139 //===---------------------------------------------------------------------===//
3141 let ExeDomain = SSEPackedInt in {
3142 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
3144 def ri : Ii8<0x70, MRMSrcReg,
3145 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
3146 !strconcat(OpcodeStr,
3147 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3148 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
3150 def mi : Ii8<0x70, MRMSrcMem,
3151 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
3152 !strconcat(OpcodeStr,
3153 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3154 [(set VR128:$dst, (vt (pshuf_frag:$src2
3155 (bc_frag (memopv2i64 addr:$src1)),
3158 } // ExeDomain = SSEPackedInt
3160 let Predicates = [HasAVX] in {
3161 let AddedComplexity = 5 in
3162 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize,
3165 // SSE2 with ImmT == Imm8 and XS prefix.
3166 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
3169 // SSE2 with ImmT == Imm8 and XD prefix.
3170 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
3173 let AddedComplexity = 5 in
3174 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3175 (VPSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3176 // Unary v4f32 shuffle with VPSHUF* in order to fold a load.
3177 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3178 (VPSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3180 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
3182 (VPSHUFDmi addr:$src1, imm:$imm)>, Requires<[HasAVX]>;
3183 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
3185 (VPSHUFDmi addr:$src1, imm:$imm)>;
3186 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3187 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
3188 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3189 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
3190 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
3191 (VPSHUFHWri VR128:$src, imm:$imm)>;
3192 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
3194 (VPSHUFHWmi addr:$src, imm:$imm)>;
3195 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
3196 (VPSHUFLWri VR128:$src, imm:$imm)>;
3197 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
3199 (VPSHUFLWmi addr:$src, imm:$imm)>;
3202 let Predicates = [HasSSE2] in {
3203 let AddedComplexity = 5 in
3204 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
3206 // SSE2 with ImmT == Imm8 and XS prefix.
3207 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
3209 // SSE2 with ImmT == Imm8 and XD prefix.
3210 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
3212 let AddedComplexity = 5 in
3213 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3214 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3215 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3216 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3217 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3219 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
3221 (PSHUFDmi addr:$src1, imm:$imm)>;
3222 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
3224 (PSHUFDmi addr:$src1, imm:$imm)>;
3225 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3226 (PSHUFDri VR128:$src1, imm:$imm)>;
3227 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3228 (PSHUFDri VR128:$src1, imm:$imm)>;
3229 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
3230 (PSHUFHWri VR128:$src, imm:$imm)>;
3231 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
3233 (PSHUFHWmi addr:$src, imm:$imm)>;
3234 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
3235 (PSHUFLWri VR128:$src, imm:$imm)>;
3236 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
3238 (PSHUFLWmi addr:$src, imm:$imm)>;
3241 //===---------------------------------------------------------------------===//
3242 // SSE2 - Packed Integer Unpack Instructions
3243 //===---------------------------------------------------------------------===//
3245 let ExeDomain = SSEPackedInt in {
3246 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
3247 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
3248 def rr : PDI<opc, MRMSrcReg,
3249 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3251 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3252 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3253 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))]>;
3254 def rm : PDI<opc, MRMSrcMem,
3255 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3257 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3258 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3259 [(set VR128:$dst, (OpNode VR128:$src1,
3260 (bc_frag (memopv2i64
3264 let Predicates = [HasAVX] in {
3265 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Punpcklbw,
3266 bc_v16i8, 0>, VEX_4V;
3267 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Punpcklwd,
3268 bc_v8i16, 0>, VEX_4V;
3269 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Punpckldq,
3270 bc_v4i32, 0>, VEX_4V;
3272 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3273 /// knew to collapse (bitconvert VT to VT) into its operand.
3274 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
3275 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3276 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3277 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
3278 VR128:$src2)))]>, VEX_4V;
3279 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
3280 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3281 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3282 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
3283 (memopv2i64 addr:$src2))))]>, VEX_4V;
3285 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Punpckhbw,
3286 bc_v16i8, 0>, VEX_4V;
3287 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Punpckhwd,
3288 bc_v8i16, 0>, VEX_4V;
3289 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Punpckhdq,
3290 bc_v4i32, 0>, VEX_4V;
3292 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3293 /// knew to collapse (bitconvert VT to VT) into its operand.
3294 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
3295 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3296 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3297 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
3298 VR128:$src2)))]>, VEX_4V;
3299 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
3300 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3301 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3302 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
3303 (memopv2i64 addr:$src2))))]>, VEX_4V;
3306 let Constraints = "$src1 = $dst" in {
3307 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Punpcklbw, bc_v16i8>;
3308 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Punpcklwd, bc_v8i16>;
3309 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Punpckldq, bc_v4i32>;
3311 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3312 /// knew to collapse (bitconvert VT to VT) into its operand.
3313 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
3314 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3315 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
3317 (v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)))]>;
3318 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
3319 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3320 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
3322 (v2i64 (X86Punpcklqdq VR128:$src1,
3323 (memopv2i64 addr:$src2))))]>;
3325 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Punpckhbw, bc_v16i8>;
3326 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Punpckhwd, bc_v8i16>;
3327 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Punpckhdq, bc_v4i32>;
3329 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3330 /// knew to collapse (bitconvert VT to VT) into its operand.
3331 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
3332 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3333 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
3335 (v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)))]>;
3336 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
3337 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3338 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
3340 (v2i64 (X86Punpckhqdq VR128:$src1,
3341 (memopv2i64 addr:$src2))))]>;
3344 } // ExeDomain = SSEPackedInt
3346 //===---------------------------------------------------------------------===//
3347 // SSE2 - Packed Integer Extract and Insert
3348 //===---------------------------------------------------------------------===//
3350 let ExeDomain = SSEPackedInt in {
3351 multiclass sse2_pinsrw<bit Is2Addr = 1> {
3352 def rri : Ii8<0xC4, MRMSrcReg,
3353 (outs VR128:$dst), (ins VR128:$src1,
3354 GR32:$src2, i32i8imm:$src3),
3356 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3357 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3359 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
3360 def rmi : Ii8<0xC4, MRMSrcMem,
3361 (outs VR128:$dst), (ins VR128:$src1,
3362 i16mem:$src2, i32i8imm:$src3),
3364 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3365 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3367 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
3372 let Predicates = [HasAVX] in
3373 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
3374 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
3375 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3376 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
3377 imm:$src2))]>, OpSize, VEX;
3378 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
3379 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
3380 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3381 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
3385 let Predicates = [HasAVX] in {
3386 defm VPINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
3387 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
3388 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
3389 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
3390 []>, OpSize, VEX_4V;
3393 let Constraints = "$src1 = $dst" in
3394 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
3396 } // ExeDomain = SSEPackedInt
3398 //===---------------------------------------------------------------------===//
3399 // SSE2 - Packed Mask Creation
3400 //===---------------------------------------------------------------------===//
3402 let ExeDomain = SSEPackedInt in {
3404 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
3405 "pmovmskb\t{$src, $dst|$dst, $src}",
3406 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
3407 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
3408 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
3409 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
3410 "pmovmskb\t{$src, $dst|$dst, $src}",
3411 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
3413 } // ExeDomain = SSEPackedInt
3415 //===---------------------------------------------------------------------===//
3416 // SSE2 - Conditional Store
3417 //===---------------------------------------------------------------------===//
3419 let ExeDomain = SSEPackedInt in {
3422 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
3423 (ins VR128:$src, VR128:$mask),
3424 "maskmovdqu\t{$mask, $src|$src, $mask}",
3425 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
3427 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
3428 (ins VR128:$src, VR128:$mask),
3429 "maskmovdqu\t{$mask, $src|$src, $mask}",
3430 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
3433 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
3434 "maskmovdqu\t{$mask, $src|$src, $mask}",
3435 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
3437 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
3438 "maskmovdqu\t{$mask, $src|$src, $mask}",
3439 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
3441 } // ExeDomain = SSEPackedInt
3443 //===---------------------------------------------------------------------===//
3444 // SSE2 - Move Doubleword
3445 //===---------------------------------------------------------------------===//
3447 //===---------------------------------------------------------------------===//
3448 // Move Int Doubleword to Packed Double Int
3450 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3451 "movd\t{$src, $dst|$dst, $src}",
3453 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
3454 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3455 "movd\t{$src, $dst|$dst, $src}",
3457 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
3459 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3460 "mov{d|q}\t{$src, $dst|$dst, $src}",
3462 (v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
3463 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
3464 "mov{d|q}\t{$src, $dst|$dst, $src}",
3465 [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
3467 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3468 "movd\t{$src, $dst|$dst, $src}",
3470 (v4i32 (scalar_to_vector GR32:$src)))]>;
3471 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3472 "movd\t{$src, $dst|$dst, $src}",
3474 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
3475 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3476 "mov{d|q}\t{$src, $dst|$dst, $src}",
3478 (v2i64 (scalar_to_vector GR64:$src)))]>;
3479 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
3480 "mov{d|q}\t{$src, $dst|$dst, $src}",
3481 [(set FR64:$dst, (bitconvert GR64:$src))]>;
3483 //===---------------------------------------------------------------------===//
3484 // Move Int Doubleword to Single Scalar
3486 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
3487 "movd\t{$src, $dst|$dst, $src}",
3488 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
3490 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
3491 "movd\t{$src, $dst|$dst, $src}",
3492 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
3494 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
3495 "movd\t{$src, $dst|$dst, $src}",
3496 [(set FR32:$dst, (bitconvert GR32:$src))]>;
3498 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
3499 "movd\t{$src, $dst|$dst, $src}",
3500 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
3502 //===---------------------------------------------------------------------===//
3503 // Move Packed Doubleword Int to Packed Double Int
3505 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
3506 "movd\t{$src, $dst|$dst, $src}",
3507 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
3509 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
3510 (ins i32mem:$dst, VR128:$src),
3511 "movd\t{$src, $dst|$dst, $src}",
3512 [(store (i32 (vector_extract (v4i32 VR128:$src),
3513 (iPTR 0))), addr:$dst)]>, VEX;
3514 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
3515 "movd\t{$src, $dst|$dst, $src}",
3516 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
3518 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
3519 "movd\t{$src, $dst|$dst, $src}",
3520 [(store (i32 (vector_extract (v4i32 VR128:$src),
3521 (iPTR 0))), addr:$dst)]>;
3523 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3524 "mov{d|q}\t{$src, $dst|$dst, $src}",
3525 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
3527 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
3528 "movq\t{$src, $dst|$dst, $src}",
3529 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
3531 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
3532 "mov{d|q}\t{$src, $dst|$dst, $src}",
3533 [(set GR64:$dst, (bitconvert FR64:$src))]>;
3534 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
3535 "movq\t{$src, $dst|$dst, $src}",
3536 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
3538 //===---------------------------------------------------------------------===//
3539 // Move Scalar Single to Double Int
3541 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
3542 "movd\t{$src, $dst|$dst, $src}",
3543 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
3544 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
3545 "movd\t{$src, $dst|$dst, $src}",
3546 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
3547 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
3548 "movd\t{$src, $dst|$dst, $src}",
3549 [(set GR32:$dst, (bitconvert FR32:$src))]>;
3550 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
3551 "movd\t{$src, $dst|$dst, $src}",
3552 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
3554 //===---------------------------------------------------------------------===//
3555 // Patterns and instructions to describe movd/movq to XMM register zero-extends
3557 let AddedComplexity = 15 in {
3558 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3559 "movd\t{$src, $dst|$dst, $src}",
3560 [(set VR128:$dst, (v4i32 (X86vzmovl
3561 (v4i32 (scalar_to_vector GR32:$src)))))]>,
3563 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3564 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3565 [(set VR128:$dst, (v2i64 (X86vzmovl
3566 (v2i64 (scalar_to_vector GR64:$src)))))]>,
3569 let AddedComplexity = 15 in {
3570 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3571 "movd\t{$src, $dst|$dst, $src}",
3572 [(set VR128:$dst, (v4i32 (X86vzmovl
3573 (v4i32 (scalar_to_vector GR32:$src)))))]>;
3574 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3575 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3576 [(set VR128:$dst, (v2i64 (X86vzmovl
3577 (v2i64 (scalar_to_vector GR64:$src)))))]>;
3580 let AddedComplexity = 20 in {
3581 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3582 "movd\t{$src, $dst|$dst, $src}",
3584 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3585 (loadi32 addr:$src))))))]>,
3587 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3588 "movd\t{$src, $dst|$dst, $src}",
3590 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3591 (loadi32 addr:$src))))))]>;
3593 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
3594 (MOVZDI2PDIrm addr:$src)>;
3595 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3596 (MOVZDI2PDIrm addr:$src)>;
3597 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3598 (MOVZDI2PDIrm addr:$src)>;
3601 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3602 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3603 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3604 (v4i32 (scalar_to_vector GR32:$src)), (i32 0)))),
3605 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
3606 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3607 (v2i64 (scalar_to_vector GR64:$src)), (i32 0)))),
3608 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
3610 // These are the correct encodings of the instructions so that we know how to
3611 // read correct assembly, even though we continue to emit the wrong ones for
3612 // compatibility with Darwin's buggy assembler.
3613 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3614 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
3615 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3616 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
3617 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3618 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
3619 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3620 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
3621 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3622 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
3623 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3624 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
3626 //===---------------------------------------------------------------------===//
3627 // SSE2 - Move Quadword
3628 //===---------------------------------------------------------------------===//
3630 //===---------------------------------------------------------------------===//
3631 // Move Quadword Int to Packed Quadword Int
3633 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3634 "vmovq\t{$src, $dst|$dst, $src}",
3636 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3637 VEX, Requires<[HasAVX]>;
3638 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3639 "movq\t{$src, $dst|$dst, $src}",
3641 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3642 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
3644 //===---------------------------------------------------------------------===//
3645 // Move Packed Quadword Int to Quadword Int
3647 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3648 "movq\t{$src, $dst|$dst, $src}",
3649 [(store (i64 (vector_extract (v2i64 VR128:$src),
3650 (iPTR 0))), addr:$dst)]>, VEX;
3651 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3652 "movq\t{$src, $dst|$dst, $src}",
3653 [(store (i64 (vector_extract (v2i64 VR128:$src),
3654 (iPTR 0))), addr:$dst)]>;
3656 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
3657 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
3659 //===---------------------------------------------------------------------===//
3660 // Store / copy lower 64-bits of a XMM register.
3662 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3663 "movq\t{$src, $dst|$dst, $src}",
3664 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
3665 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3666 "movq\t{$src, $dst|$dst, $src}",
3667 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
3669 let AddedComplexity = 20 in
3670 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3671 "vmovq\t{$src, $dst|$dst, $src}",
3673 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3674 (loadi64 addr:$src))))))]>,
3675 XS, VEX, Requires<[HasAVX]>;
3677 let AddedComplexity = 20 in {
3678 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3679 "movq\t{$src, $dst|$dst, $src}",
3681 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3682 (loadi64 addr:$src))))))]>,
3683 XS, Requires<[HasSSE2]>;
3685 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3686 (MOVZQI2PQIrm addr:$src)>;
3687 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
3688 (MOVZQI2PQIrm addr:$src)>;
3689 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
3692 //===---------------------------------------------------------------------===//
3693 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
3694 // IA32 document. movq xmm1, xmm2 does clear the high bits.
3696 let AddedComplexity = 15 in
3697 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3698 "vmovq\t{$src, $dst|$dst, $src}",
3699 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3700 XS, VEX, Requires<[HasAVX]>;
3701 let AddedComplexity = 15 in
3702 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3703 "movq\t{$src, $dst|$dst, $src}",
3704 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3705 XS, Requires<[HasSSE2]>;
3707 let AddedComplexity = 20 in
3708 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3709 "vmovq\t{$src, $dst|$dst, $src}",
3710 [(set VR128:$dst, (v2i64 (X86vzmovl
3711 (loadv2i64 addr:$src))))]>,
3712 XS, VEX, Requires<[HasAVX]>;
3713 let AddedComplexity = 20 in {
3714 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3715 "movq\t{$src, $dst|$dst, $src}",
3716 [(set VR128:$dst, (v2i64 (X86vzmovl
3717 (loadv2i64 addr:$src))))]>,
3718 XS, Requires<[HasSSE2]>;
3720 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
3721 (MOVZPQILo2PQIrm addr:$src)>;
3724 // Instructions to match in the assembler
3725 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3726 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3727 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3728 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3729 // Recognize "movd" with GR64 destination, but encode as a "movq"
3730 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3731 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3733 // Instructions for the disassembler
3734 // xr = XMM register
3737 let Predicates = [HasAVX] in
3738 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3739 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
3740 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3741 "movq\t{$src, $dst|$dst, $src}", []>, XS;
3743 //===---------------------------------------------------------------------===//
3744 // SSE2 - Misc Instructions
3745 //===---------------------------------------------------------------------===//
3748 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3749 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3750 TB, Requires<[HasSSE2]>;
3752 // Load, store, and memory fence
3753 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3754 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3755 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3756 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3757 def : Pat<(X86LFence), (LFENCE)>;
3758 def : Pat<(X86MFence), (MFENCE)>;
3761 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3762 // was introduced with SSE2, it's backward compatible.
3763 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3765 // Alias instructions that map zero vector to pxor / xorp* for sse.
3766 // We set canFoldAsLoad because this can be converted to a constant-pool
3767 // load of an all-ones value if folding it would be beneficial.
3768 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
3769 // JIT implementation, it does not expand the instructions below like
3770 // X86MCInstLower does.
3771 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3772 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
3773 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3774 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
3775 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3776 isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in
3777 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3778 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
3780 //===---------------------------------------------------------------------===//
3781 // SSE3 - Conversion Instructions
3782 //===---------------------------------------------------------------------===//
3784 // Convert Packed Double FP to Packed DW Integers
3785 let Predicates = [HasAVX] in {
3786 // The assembler can recognize rr 256-bit instructions by seeing a ymm
3787 // register, but the same isn't true when using memory operands instead.
3788 // Provide other assembly rr and rm forms to address this explicitly.
3789 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3790 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3791 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3792 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3795 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3796 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3797 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3798 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3801 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3802 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
3803 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
3804 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
3807 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3808 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3809 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3810 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3812 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
3813 (VCVTPD2DQYrr VR256:$src)>;
3814 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
3815 (VCVTPD2DQYrm addr:$src)>;
3817 // Convert Packed DW Integers to Packed Double FP
3818 let Predicates = [HasAVX] in {
3819 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3820 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3821 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3822 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3823 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
3824 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3825 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
3826 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3829 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3830 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3831 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3832 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3834 // AVX 256-bit register conversion intrinsics
3835 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
3836 (VCVTDQ2PDYrr VR128:$src)>;
3837 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
3838 (VCVTDQ2PDYrm addr:$src)>;
3840 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
3841 (VCVTPD2DQYrr VR256:$src)>;
3842 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
3843 (VCVTPD2DQYrm addr:$src)>;
3845 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
3846 (VCVTDQ2PDYrr VR128:$src)>;
3847 def : Pat<(v4f64 (sint_to_fp (memopv4i32 addr:$src))),
3848 (VCVTDQ2PDYrm addr:$src)>;
3850 //===---------------------------------------------------------------------===//
3851 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
3852 //===---------------------------------------------------------------------===//
3853 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3854 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3855 X86MemOperand x86memop> {
3856 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3857 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3858 [(set RC:$dst, (vt (OpNode RC:$src)))]>;
3859 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3860 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3861 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>;
3864 let Predicates = [HasAVX] in {
3865 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3866 v4f32, VR128, memopv4f32, f128mem>, VEX;
3867 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3868 v4f32, VR128, memopv4f32, f128mem>, VEX;
3869 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3870 v8f32, VR256, memopv8f32, f256mem>, VEX;
3871 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3872 v8f32, VR256, memopv8f32, f256mem>, VEX;
3874 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
3875 memopv4f32, f128mem>;
3876 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
3877 memopv4f32, f128mem>;
3879 let Predicates = [HasSSE3] in {
3880 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
3881 (MOVSHDUPrr VR128:$src)>;
3882 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
3883 (MOVSHDUPrm addr:$src)>;
3884 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
3885 (MOVSLDUPrr VR128:$src)>;
3886 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
3887 (MOVSLDUPrm addr:$src)>;
3890 let Predicates = [HasAVX] in {
3891 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
3892 (VMOVSHDUPrr VR128:$src)>;
3893 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
3894 (VMOVSHDUPrm addr:$src)>;
3895 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
3896 (VMOVSLDUPrr VR128:$src)>;
3897 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
3898 (VMOVSLDUPrm addr:$src)>;
3899 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
3900 (VMOVSHDUPYrr VR256:$src)>;
3901 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
3902 (VMOVSHDUPYrm addr:$src)>;
3903 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
3904 (VMOVSLDUPYrr VR256:$src)>;
3905 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
3906 (VMOVSLDUPYrm addr:$src)>;
3909 //===---------------------------------------------------------------------===//
3910 // SSE3 - Replicate Double FP - MOVDDUP
3911 //===---------------------------------------------------------------------===//
3913 multiclass sse3_replicate_dfp<string OpcodeStr> {
3914 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3915 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3916 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
3917 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
3918 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3920 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
3924 // FIXME: Merge with above classe when there're patterns for the ymm version
3925 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
3926 let Predicates = [HasAVX] in {
3927 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3928 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3930 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3931 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3936 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
3937 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
3938 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
3940 let Predicates = [HasSSE3] in {
3941 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
3943 (MOVDDUPrm addr:$src)>;
3944 let AddedComplexity = 5 in {
3945 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
3946 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
3947 (MOVDDUPrm addr:$src)>;
3948 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
3949 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
3950 (MOVDDUPrm addr:$src)>;
3952 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
3953 (MOVDDUPrm addr:$src)>;
3954 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
3955 (MOVDDUPrm addr:$src)>;
3956 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
3957 (MOVDDUPrm addr:$src)>;
3958 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
3959 (MOVDDUPrm addr:$src)>;
3960 def : Pat<(X86Movddup (bc_v2f64
3961 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
3962 (MOVDDUPrm addr:$src)>;
3965 let Predicates = [HasAVX] in {
3966 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
3968 (VMOVDDUPrm addr:$src)>;
3969 let AddedComplexity = 5 in {
3970 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
3971 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
3972 (VMOVDDUPrm addr:$src)>;
3973 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
3974 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
3975 (VMOVDDUPrm addr:$src)>;
3977 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
3978 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
3979 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
3980 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
3981 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
3982 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
3983 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
3984 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
3985 def : Pat<(X86Movddup (bc_v2f64
3986 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
3987 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
3990 //===---------------------------------------------------------------------===//
3991 // SSE3 - Move Unaligned Integer
3992 //===---------------------------------------------------------------------===//
3994 let Predicates = [HasAVX] in {
3995 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3996 "vlddqu\t{$src, $dst|$dst, $src}",
3997 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
3998 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3999 "vlddqu\t{$src, $dst|$dst, $src}",
4000 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
4002 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4003 "lddqu\t{$src, $dst|$dst, $src}",
4004 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
4006 //===---------------------------------------------------------------------===//
4007 // SSE3 - Arithmetic
4008 //===---------------------------------------------------------------------===//
4010 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4011 X86MemOperand x86memop, bit Is2Addr = 1> {
4012 def rr : I<0xD0, MRMSrcReg,
4013 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4015 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4016 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4017 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
4018 def rm : I<0xD0, MRMSrcMem,
4019 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4021 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4022 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4023 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
4026 let Predicates = [HasAVX],
4027 ExeDomain = SSEPackedDouble in {
4028 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4029 f128mem, 0>, TB, XD, VEX_4V;
4030 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4031 f128mem, 0>, TB, OpSize, VEX_4V;
4032 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4033 f256mem, 0>, TB, XD, VEX_4V;
4034 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
4035 f256mem, 0>, TB, OpSize, VEX_4V;
4037 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
4038 ExeDomain = SSEPackedDouble in {
4039 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
4041 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
4042 f128mem>, TB, OpSize;
4045 //===---------------------------------------------------------------------===//
4046 // SSE3 Instructions
4047 //===---------------------------------------------------------------------===//
4050 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4051 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
4052 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4054 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4055 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4056 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
4058 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4060 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4061 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4062 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
4064 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4065 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
4066 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4068 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4069 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4070 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
4072 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4074 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4075 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4076 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
4079 let Predicates = [HasAVX] in {
4080 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
4081 int_x86_sse3_hadd_ps, 0>, VEX_4V;
4082 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
4083 int_x86_sse3_hadd_pd, 0>, VEX_4V;
4084 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
4085 int_x86_sse3_hsub_ps, 0>, VEX_4V;
4086 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
4087 int_x86_sse3_hsub_pd, 0>, VEX_4V;
4088 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
4089 int_x86_avx_hadd_ps_256, 0>, VEX_4V;
4090 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
4091 int_x86_avx_hadd_pd_256, 0>, VEX_4V;
4092 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
4093 int_x86_avx_hsub_ps_256, 0>, VEX_4V;
4094 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
4095 int_x86_avx_hsub_pd_256, 0>, VEX_4V;
4098 let Constraints = "$src1 = $dst" in {
4099 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
4100 int_x86_sse3_hadd_ps>;
4101 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
4102 int_x86_sse3_hadd_pd>;
4103 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
4104 int_x86_sse3_hsub_ps>;
4105 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
4106 int_x86_sse3_hsub_pd>;
4109 //===---------------------------------------------------------------------===//
4110 // SSSE3 - Packed Absolute Instructions
4111 //===---------------------------------------------------------------------===//
4114 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
4115 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
4116 PatFrag mem_frag128, Intrinsic IntId128> {
4117 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4119 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4120 [(set VR128:$dst, (IntId128 VR128:$src))]>,
4123 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4125 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4128 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
4131 let Predicates = [HasAVX] in {
4132 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
4133 int_x86_ssse3_pabs_b_128>, VEX;
4134 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
4135 int_x86_ssse3_pabs_w_128>, VEX;
4136 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
4137 int_x86_ssse3_pabs_d_128>, VEX;
4140 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
4141 int_x86_ssse3_pabs_b_128>;
4142 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
4143 int_x86_ssse3_pabs_w_128>;
4144 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
4145 int_x86_ssse3_pabs_d_128>;
4147 //===---------------------------------------------------------------------===//
4148 // SSSE3 - Packed Binary Operator Instructions
4149 //===---------------------------------------------------------------------===//
4151 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
4152 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
4153 PatFrag mem_frag128, Intrinsic IntId128,
4155 let isCommutable = 1 in
4156 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4157 (ins VR128:$src1, VR128:$src2),
4159 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4160 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4161 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4163 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4164 (ins VR128:$src1, i128mem:$src2),
4166 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4167 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4169 (IntId128 VR128:$src1,
4170 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4173 let Predicates = [HasAVX] in {
4174 let isCommutable = 0 in {
4175 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
4176 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
4177 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
4178 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
4179 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
4180 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
4181 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
4182 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
4183 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
4184 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
4185 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
4186 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
4187 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
4188 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
4189 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
4190 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
4191 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
4192 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
4193 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
4194 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
4195 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
4196 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
4198 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
4199 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
4202 // None of these have i8 immediate fields.
4203 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
4204 let isCommutable = 0 in {
4205 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
4206 int_x86_ssse3_phadd_w_128>;
4207 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
4208 int_x86_ssse3_phadd_d_128>;
4209 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
4210 int_x86_ssse3_phadd_sw_128>;
4211 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
4212 int_x86_ssse3_phsub_w_128>;
4213 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
4214 int_x86_ssse3_phsub_d_128>;
4215 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
4216 int_x86_ssse3_phsub_sw_128>;
4217 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
4218 int_x86_ssse3_pmadd_ub_sw_128>;
4219 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
4220 int_x86_ssse3_pshuf_b_128>;
4221 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
4222 int_x86_ssse3_psign_b_128>;
4223 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
4224 int_x86_ssse3_psign_w_128>;
4225 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
4226 int_x86_ssse3_psign_d_128>;
4228 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
4229 int_x86_ssse3_pmul_hr_sw_128>;
4232 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
4233 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
4234 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
4235 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
4237 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
4238 (PSIGNBrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
4239 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
4240 (PSIGNWrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
4241 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
4242 (PSIGNDrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
4244 //===---------------------------------------------------------------------===//
4245 // SSSE3 - Packed Align Instruction Patterns
4246 //===---------------------------------------------------------------------===//
4248 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
4249 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
4250 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4252 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4254 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4256 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
4257 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4259 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4261 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4265 let Predicates = [HasAVX] in
4266 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
4267 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
4268 defm PALIGN : ssse3_palign<"palignr">;
4270 let Predicates = [HasSSSE3] in {
4271 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4272 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4273 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4274 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4275 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4276 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4277 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4278 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4281 let Predicates = [HasAVX] in {
4282 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4283 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4284 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4285 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4286 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4287 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4288 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4289 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4292 //===---------------------------------------------------------------------===//
4293 // SSSE3 Misc Instructions
4294 //===---------------------------------------------------------------------===//
4296 // Thread synchronization
4297 let usesCustomInserter = 1 in {
4298 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
4299 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
4300 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
4301 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
4304 let Uses = [EAX, ECX, EDX] in
4305 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
4306 Requires<[HasSSE3]>;
4307 let Uses = [ECX, EAX] in
4308 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
4309 Requires<[HasSSE3]>;
4311 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
4312 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
4314 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
4315 Requires<[In32BitMode]>;
4316 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
4317 Requires<[In64BitMode]>;
4319 // extload f32 -> f64. This matches load+fextend because we have a hack in
4320 // the isel (PreprocessForFPConvert) that can introduce loads after dag
4322 // Since these loads aren't folded into the fextend, we have to match it
4324 let Predicates = [HasSSE2] in
4325 def : Pat<(fextend (loadf32 addr:$src)),
4326 (CVTSS2SDrm addr:$src)>;
4328 // Move scalar to XMM zero-extended
4329 // movd to XMM register zero-extends
4330 let AddedComplexity = 15 in {
4331 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
4332 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
4333 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
4334 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
4335 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
4336 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
4337 (MOVSSrr (v4f32 (V_SET0PS)),
4338 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
4339 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
4340 (MOVSSrr (v4i32 (V_SET0PI)),
4341 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
4344 // Splat v2f64 / v2i64
4345 let AddedComplexity = 10 in {
4346 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
4347 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
4350 let AddedComplexity = 20 in {
4351 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
4352 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
4353 (MOVLPSrm VR128:$src1, addr:$src2)>;
4354 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
4355 (MOVLPDrm VR128:$src1, addr:$src2)>;
4356 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
4357 (MOVLPSrm VR128:$src1, addr:$src2)>;
4358 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
4359 (MOVLPDrm VR128:$src1, addr:$src2)>;
4362 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
4363 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
4364 (MOVLPSmr addr:$src1, VR128:$src2)>;
4365 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
4366 (MOVLPDmr addr:$src1, VR128:$src2)>;
4367 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
4369 (MOVLPSmr addr:$src1, VR128:$src2)>;
4370 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
4371 (MOVLPDmr addr:$src1, VR128:$src2)>;
4373 let AddedComplexity = 15 in {
4374 // Setting the lowest element in the vector.
4375 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
4376 (MOVSSrr (v4i32 VR128:$src1),
4377 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
4378 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
4379 (MOVSDrr (v2i64 VR128:$src1),
4380 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
4382 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
4383 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
4384 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
4385 Requires<[HasSSE2]>;
4386 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
4387 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
4388 Requires<[HasSSE2]>;
4391 // Set lowest element and zero upper elements.
4392 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4393 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
4395 // Use movaps / movups for SSE integer load / store (one byte shorter).
4396 // The instructions selected below are then converted to MOVDQA/MOVDQU
4397 // during the SSE domain pass.
4398 let Predicates = [HasSSE1] in {
4399 def : Pat<(alignedloadv4i32 addr:$src),
4400 (MOVAPSrm addr:$src)>;
4401 def : Pat<(loadv4i32 addr:$src),
4402 (MOVUPSrm addr:$src)>;
4403 def : Pat<(alignedloadv2i64 addr:$src),
4404 (MOVAPSrm addr:$src)>;
4405 def : Pat<(loadv2i64 addr:$src),
4406 (MOVUPSrm addr:$src)>;
4408 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
4409 (MOVAPSmr addr:$dst, VR128:$src)>;
4410 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
4411 (MOVAPSmr addr:$dst, VR128:$src)>;
4412 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
4413 (MOVAPSmr addr:$dst, VR128:$src)>;
4414 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
4415 (MOVAPSmr addr:$dst, VR128:$src)>;
4416 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
4417 (MOVUPSmr addr:$dst, VR128:$src)>;
4418 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
4419 (MOVUPSmr addr:$dst, VR128:$src)>;
4420 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
4421 (MOVUPSmr addr:$dst, VR128:$src)>;
4422 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
4423 (MOVUPSmr addr:$dst, VR128:$src)>;
4426 // Use vmovaps/vmovups for AVX integer load/store.
4427 let Predicates = [HasAVX] in {
4428 // 128-bit load/store
4429 def : Pat<(alignedloadv4i32 addr:$src),
4430 (VMOVAPSrm addr:$src)>;
4431 def : Pat<(loadv4i32 addr:$src),
4432 (VMOVUPSrm addr:$src)>;
4433 def : Pat<(alignedloadv2i64 addr:$src),
4434 (VMOVAPSrm addr:$src)>;
4435 def : Pat<(loadv2i64 addr:$src),
4436 (VMOVUPSrm addr:$src)>;
4438 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
4439 (VMOVAPSmr addr:$dst, VR128:$src)>;
4440 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
4441 (VMOVAPSmr addr:$dst, VR128:$src)>;
4442 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
4443 (VMOVAPSmr addr:$dst, VR128:$src)>;
4444 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
4445 (VMOVAPSmr addr:$dst, VR128:$src)>;
4446 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
4447 (VMOVUPSmr addr:$dst, VR128:$src)>;
4448 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
4449 (VMOVUPSmr addr:$dst, VR128:$src)>;
4450 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
4451 (VMOVUPSmr addr:$dst, VR128:$src)>;
4452 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
4453 (VMOVUPSmr addr:$dst, VR128:$src)>;
4455 // 256-bit load/store
4456 def : Pat<(alignedloadv4i64 addr:$src),
4457 (VMOVAPSYrm addr:$src)>;
4458 def : Pat<(loadv4i64 addr:$src),
4459 (VMOVUPSYrm addr:$src)>;
4460 def : Pat<(alignedloadv8i32 addr:$src),
4461 (VMOVAPSYrm addr:$src)>;
4462 def : Pat<(loadv8i32 addr:$src),
4463 (VMOVUPSYrm addr:$src)>;
4464 def : Pat<(alignedstore (v4i64 VR256:$src), addr:$dst),
4465 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4466 def : Pat<(alignedstore (v8i32 VR256:$src), addr:$dst),
4467 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4468 def : Pat<(alignedstore (v16i16 VR256:$src), addr:$dst),
4469 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4470 def : Pat<(alignedstore (v32i8 VR256:$src), addr:$dst),
4471 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4472 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
4473 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4474 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
4475 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4476 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
4477 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4478 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
4479 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4482 //===----------------------------------------------------------------------===//
4483 // SSE4.1 - Packed Move with Sign/Zero Extend
4484 //===----------------------------------------------------------------------===//
4486 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4487 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4488 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4489 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4491 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4492 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4494 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
4498 let Predicates = [HasAVX] in {
4499 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
4501 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
4503 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
4505 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
4507 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
4509 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
4513 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
4514 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
4515 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
4516 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
4517 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
4518 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
4520 // Common patterns involving scalar load.
4521 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
4522 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4523 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
4524 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4526 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
4527 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4528 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
4529 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4531 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
4532 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4533 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
4534 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4536 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
4537 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4538 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
4539 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4541 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
4542 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4543 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
4544 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4546 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
4547 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4548 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
4549 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4552 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4553 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4554 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4555 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4557 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4558 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4560 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
4564 let Predicates = [HasAVX] in {
4565 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
4567 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
4569 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
4571 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
4575 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
4576 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
4577 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
4578 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
4580 // Common patterns involving scalar load
4581 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
4582 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
4583 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
4584 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
4586 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
4587 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
4588 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
4589 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
4592 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4593 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4595 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4597 // Expecting a i16 load any extended to i32 value.
4598 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
4599 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4600 [(set VR128:$dst, (IntId (bitconvert
4601 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
4605 let Predicates = [HasAVX] in {
4606 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
4608 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
4611 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
4612 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
4614 // Common patterns involving scalar load
4615 def : Pat<(int_x86_sse41_pmovsxbq
4616 (bitconvert (v4i32 (X86vzmovl
4617 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4618 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
4620 def : Pat<(int_x86_sse41_pmovzxbq
4621 (bitconvert (v4i32 (X86vzmovl
4622 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4623 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
4625 //===----------------------------------------------------------------------===//
4626 // SSE4.1 - Extract Instructions
4627 //===----------------------------------------------------------------------===//
4629 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
4630 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
4631 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4632 (ins VR128:$src1, i32i8imm:$src2),
4633 !strconcat(OpcodeStr,
4634 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4635 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
4637 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4638 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
4639 !strconcat(OpcodeStr,
4640 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4643 // There's an AssertZext in the way of writing the store pattern
4644 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4647 let Predicates = [HasAVX] in {
4648 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
4649 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
4650 (ins VR128:$src1, i32i8imm:$src2),
4651 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
4654 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
4657 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
4658 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
4659 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4660 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
4661 !strconcat(OpcodeStr,
4662 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4665 // There's an AssertZext in the way of writing the store pattern
4666 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4669 let Predicates = [HasAVX] in
4670 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
4672 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
4675 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4676 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
4677 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4678 (ins VR128:$src1, i32i8imm:$src2),
4679 !strconcat(OpcodeStr,
4680 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4682 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
4683 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4684 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
4685 !strconcat(OpcodeStr,
4686 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4687 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
4688 addr:$dst)]>, OpSize;
4691 let Predicates = [HasAVX] in
4692 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
4694 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
4696 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4697 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
4698 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
4699 (ins VR128:$src1, i32i8imm:$src2),
4700 !strconcat(OpcodeStr,
4701 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4703 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
4704 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4705 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
4706 !strconcat(OpcodeStr,
4707 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4708 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
4709 addr:$dst)]>, OpSize, REX_W;
4712 let Predicates = [HasAVX] in
4713 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
4715 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
4717 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
4719 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
4720 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4721 (ins VR128:$src1, i32i8imm:$src2),
4722 !strconcat(OpcodeStr,
4723 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4725 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
4727 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4728 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
4729 !strconcat(OpcodeStr,
4730 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4731 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
4732 addr:$dst)]>, OpSize;
4735 let Predicates = [HasAVX] in {
4736 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
4737 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
4738 (ins VR128:$src1, i32i8imm:$src2),
4739 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
4742 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
4744 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
4745 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
4748 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
4749 Requires<[HasSSE41]>;
4751 //===----------------------------------------------------------------------===//
4752 // SSE4.1 - Insert Instructions
4753 //===----------------------------------------------------------------------===//
4755 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
4756 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4757 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4759 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4761 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4763 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
4764 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4765 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
4767 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4769 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4771 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
4772 imm:$src3))]>, OpSize;
4775 let Predicates = [HasAVX] in
4776 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
4777 let Constraints = "$src1 = $dst" in
4778 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
4780 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
4781 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4782 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4784 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4786 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4788 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
4790 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4791 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
4793 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4795 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4797 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
4798 imm:$src3)))]>, OpSize;
4801 let Predicates = [HasAVX] in
4802 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
4803 let Constraints = "$src1 = $dst" in
4804 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
4806 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
4807 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4808 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4810 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4812 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4814 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
4816 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4817 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
4819 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4821 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4823 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
4824 imm:$src3)))]>, OpSize;
4827 let Predicates = [HasAVX] in
4828 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
4829 let Constraints = "$src1 = $dst" in
4830 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
4832 // insertps has a few different modes, there's the first two here below which
4833 // are optimized inserts that won't zero arbitrary elements in the destination
4834 // vector. The next one matches the intrinsic and could zero arbitrary elements
4835 // in the target vector.
4836 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
4837 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4838 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
4840 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4842 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4844 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
4846 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4847 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
4849 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4851 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4853 (X86insrtps VR128:$src1,
4854 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
4855 imm:$src3))]>, OpSize;
4858 let Constraints = "$src1 = $dst" in
4859 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
4860 let Predicates = [HasAVX] in
4861 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
4863 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4864 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4866 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4867 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4868 Requires<[HasSSE41]>;
4870 //===----------------------------------------------------------------------===//
4871 // SSE4.1 - Round Instructions
4872 //===----------------------------------------------------------------------===//
4874 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4875 X86MemOperand x86memop, RegisterClass RC,
4876 PatFrag mem_frag32, PatFrag mem_frag64,
4877 Intrinsic V4F32Int, Intrinsic V2F64Int> {
4878 // Intrinsic operation, reg.
4879 // Vector intrinsic operation, reg
4880 def PSr : SS4AIi8<opcps, MRMSrcReg,
4881 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4882 !strconcat(OpcodeStr,
4883 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4884 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
4887 // Vector intrinsic operation, mem
4888 def PSm : Ii8<opcps, MRMSrcMem,
4889 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4890 !strconcat(OpcodeStr,
4891 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4893 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4895 Requires<[HasSSE41]>;
4897 // Vector intrinsic operation, reg
4898 def PDr : SS4AIi8<opcpd, MRMSrcReg,
4899 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4900 !strconcat(OpcodeStr,
4901 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4902 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
4905 // Vector intrinsic operation, mem
4906 def PDm : SS4AIi8<opcpd, MRMSrcMem,
4907 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4908 !strconcat(OpcodeStr,
4909 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4911 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4915 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
4916 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
4917 // Intrinsic operation, reg.
4918 // Vector intrinsic operation, reg
4919 def PSr_AVX : SS4AIi8<opcps, MRMSrcReg,
4920 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4921 !strconcat(OpcodeStr,
4922 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4925 // Vector intrinsic operation, mem
4926 def PSm_AVX : Ii8<opcps, MRMSrcMem,
4927 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4928 !strconcat(OpcodeStr,
4929 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4930 []>, TA, OpSize, Requires<[HasSSE41]>;
4932 // Vector intrinsic operation, reg
4933 def PDr_AVX : SS4AIi8<opcpd, MRMSrcReg,
4934 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4935 !strconcat(OpcodeStr,
4936 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4939 // Vector intrinsic operation, mem
4940 def PDm_AVX : SS4AIi8<opcpd, MRMSrcMem,
4941 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4942 !strconcat(OpcodeStr,
4943 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4947 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4950 Intrinsic F64Int, bit Is2Addr = 1> {
4951 // Intrinsic operation, reg.
4952 def SSr : SS4AIi8<opcss, MRMSrcReg,
4953 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4955 !strconcat(OpcodeStr,
4956 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4957 !strconcat(OpcodeStr,
4958 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4959 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4962 // Intrinsic operation, mem.
4963 def SSm : SS4AIi8<opcss, MRMSrcMem,
4964 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4966 !strconcat(OpcodeStr,
4967 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4968 !strconcat(OpcodeStr,
4969 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4971 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
4974 // Intrinsic operation, reg.
4975 def SDr : SS4AIi8<opcsd, MRMSrcReg,
4976 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4978 !strconcat(OpcodeStr,
4979 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4980 !strconcat(OpcodeStr,
4981 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4982 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4985 // Intrinsic operation, mem.
4986 def SDm : SS4AIi8<opcsd, MRMSrcMem,
4987 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4989 !strconcat(OpcodeStr,
4990 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4991 !strconcat(OpcodeStr,
4992 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4994 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
4998 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
5000 // Intrinsic operation, reg.
5001 def SSr_AVX : SS4AIi8<opcss, MRMSrcReg,
5002 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5003 !strconcat(OpcodeStr,
5004 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5007 // Intrinsic operation, mem.
5008 def SSm_AVX : SS4AIi8<opcss, MRMSrcMem,
5009 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
5010 !strconcat(OpcodeStr,
5011 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5014 // Intrinsic operation, reg.
5015 def SDr_AVX : SS4AIi8<opcsd, MRMSrcReg,
5016 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5017 !strconcat(OpcodeStr,
5018 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5021 // Intrinsic operation, mem.
5022 def SDm_AVX : SS4AIi8<opcsd, MRMSrcMem,
5023 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
5024 !strconcat(OpcodeStr,
5025 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5029 // FP round - roundss, roundps, roundsd, roundpd
5030 let Predicates = [HasAVX] in {
5032 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
5033 memopv4f32, memopv2f64,
5034 int_x86_sse41_round_ps,
5035 int_x86_sse41_round_pd>, VEX;
5036 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
5037 memopv8f32, memopv4f64,
5038 int_x86_avx_round_ps_256,
5039 int_x86_avx_round_pd_256>, VEX;
5040 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
5041 int_x86_sse41_round_ss,
5042 int_x86_sse41_round_sd, 0>, VEX_4V;
5044 // Instructions for the assembler
5045 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
5047 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
5049 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
5052 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
5053 memopv4f32, memopv2f64,
5054 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
5055 let Constraints = "$src1 = $dst" in
5056 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
5057 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
5059 //===----------------------------------------------------------------------===//
5060 // SSE4.1 - Packed Bit Test
5061 //===----------------------------------------------------------------------===//
5063 // ptest instruction we'll lower to this in X86ISelLowering primarily from
5064 // the intel intrinsic that corresponds to this.
5065 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5066 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5067 "vptest\t{$src2, $src1|$src1, $src2}",
5068 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5070 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5071 "vptest\t{$src2, $src1|$src1, $src2}",
5072 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5075 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
5076 "vptest\t{$src2, $src1|$src1, $src2}",
5077 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
5079 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
5080 "vptest\t{$src2, $src1|$src1, $src2}",
5081 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
5085 let Defs = [EFLAGS] in {
5086 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5087 "ptest \t{$src2, $src1|$src1, $src2}",
5088 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5090 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5091 "ptest \t{$src2, $src1|$src1, $src2}",
5092 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5096 // The bit test instructions below are AVX only
5097 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
5098 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
5099 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
5100 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5101 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
5102 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
5103 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5104 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
5108 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5109 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
5110 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
5111 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
5112 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
5115 //===----------------------------------------------------------------------===//
5116 // SSE4.1 - Misc Instructions
5117 //===----------------------------------------------------------------------===//
5119 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
5120 "popcnt{w}\t{$src, $dst|$dst, $src}",
5121 [(set GR16:$dst, (ctpop GR16:$src))]>, OpSize, XS;
5122 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
5123 "popcnt{w}\t{$src, $dst|$dst, $src}",
5124 [(set GR16:$dst, (ctpop (loadi16 addr:$src)))]>, OpSize, XS;
5126 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
5127 "popcnt{l}\t{$src, $dst|$dst, $src}",
5128 [(set GR32:$dst, (ctpop GR32:$src))]>, XS;
5129 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
5130 "popcnt{l}\t{$src, $dst|$dst, $src}",
5131 [(set GR32:$dst, (ctpop (loadi32 addr:$src)))]>, XS;
5133 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
5134 "popcnt{q}\t{$src, $dst|$dst, $src}",
5135 [(set GR64:$dst, (ctpop GR64:$src))]>, XS;
5136 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
5137 "popcnt{q}\t{$src, $dst|$dst, $src}",
5138 [(set GR64:$dst, (ctpop (loadi64 addr:$src)))]>, XS;
5142 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
5143 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
5144 Intrinsic IntId128> {
5145 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5147 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5148 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
5149 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5151 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5154 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
5157 let Predicates = [HasAVX] in
5158 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
5159 int_x86_sse41_phminposuw>, VEX;
5160 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
5161 int_x86_sse41_phminposuw>;
5163 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
5164 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
5165 Intrinsic IntId128, bit Is2Addr = 1> {
5166 let isCommutable = 1 in
5167 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5168 (ins VR128:$src1, VR128:$src2),
5170 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5171 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5172 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
5173 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5174 (ins VR128:$src1, i128mem:$src2),
5176 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5177 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5179 (IntId128 VR128:$src1,
5180 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5183 let Predicates = [HasAVX] in {
5184 let isCommutable = 0 in
5185 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
5187 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
5189 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
5191 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
5193 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
5195 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
5197 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
5199 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
5201 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
5203 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
5205 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
5208 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
5209 (VPCMPEQQrr VR128:$src1, VR128:$src2)>;
5210 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
5211 (VPCMPEQQrm VR128:$src1, addr:$src2)>;
5214 let Constraints = "$src1 = $dst" in {
5215 let isCommutable = 0 in
5216 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
5217 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
5218 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
5219 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
5220 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
5221 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
5222 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
5223 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
5224 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
5225 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
5226 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
5229 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
5230 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
5231 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
5232 (PCMPEQQrm VR128:$src1, addr:$src2)>;
5234 /// SS48I_binop_rm - Simple SSE41 binary operator.
5235 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5236 ValueType OpVT, bit Is2Addr = 1> {
5237 let isCommutable = 1 in
5238 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5239 (ins VR128:$src1, VR128:$src2),
5241 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5242 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5243 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
5245 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5246 (ins VR128:$src1, i128mem:$src2),
5248 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5249 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5250 [(set VR128:$dst, (OpNode VR128:$src1,
5251 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
5255 let Predicates = [HasAVX] in
5256 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
5257 let Constraints = "$src1 = $dst" in
5258 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
5260 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
5261 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
5262 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
5263 X86MemOperand x86memop, bit Is2Addr = 1> {
5264 let isCommutable = 1 in
5265 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
5266 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
5268 !strconcat(OpcodeStr,
5269 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5270 !strconcat(OpcodeStr,
5271 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5272 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
5274 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
5275 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
5277 !strconcat(OpcodeStr,
5278 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5279 !strconcat(OpcodeStr,
5280 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5283 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
5287 let Predicates = [HasAVX] in {
5288 let isCommutable = 0 in {
5289 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
5290 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5291 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
5292 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5293 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
5294 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
5295 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
5296 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
5297 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
5298 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5299 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
5300 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5302 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
5303 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5304 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
5305 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5306 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
5307 VR256, memopv32i8, i256mem, 0>, VEX_4V;
5310 let Constraints = "$src1 = $dst" in {
5311 let isCommutable = 0 in {
5312 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
5313 VR128, memopv16i8, i128mem>;
5314 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
5315 VR128, memopv16i8, i128mem>;
5316 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
5317 VR128, memopv16i8, i128mem>;
5318 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
5319 VR128, memopv16i8, i128mem>;
5321 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
5322 VR128, memopv16i8, i128mem>;
5323 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
5324 VR128, memopv16i8, i128mem>;
5327 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
5328 let Predicates = [HasAVX] in {
5329 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
5330 RegisterClass RC, X86MemOperand x86memop,
5331 PatFrag mem_frag, Intrinsic IntId> {
5332 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
5333 (ins RC:$src1, RC:$src2, RC:$src3),
5334 !strconcat(OpcodeStr,
5335 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5336 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
5337 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
5339 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
5340 (ins RC:$src1, x86memop:$src2, RC:$src3),
5341 !strconcat(OpcodeStr,
5342 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5344 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
5346 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
5350 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
5351 memopv16i8, int_x86_sse41_blendvpd>;
5352 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
5353 memopv16i8, int_x86_sse41_blendvps>;
5354 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
5355 memopv16i8, int_x86_sse41_pblendvb>;
5356 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
5357 memopv32i8, int_x86_avx_blendv_pd_256>;
5358 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
5359 memopv32i8, int_x86_avx_blendv_ps_256>;
5361 /// SS41I_ternary_int - SSE 4.1 ternary operator
5362 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
5363 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5364 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5365 (ins VR128:$src1, VR128:$src2),
5366 !strconcat(OpcodeStr,
5367 "\t{$src2, $dst|$dst, $src2}"),
5368 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
5371 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5372 (ins VR128:$src1, i128mem:$src2),
5373 !strconcat(OpcodeStr,
5374 "\t{$src2, $dst|$dst, $src2}"),
5377 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
5381 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
5382 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
5383 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
5385 def : Pat<(X86pblendv VR128:$src1, VR128:$src2, XMM0),
5386 (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
5388 let Predicates = [HasAVX] in
5389 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5390 "vmovntdqa\t{$src, $dst|$dst, $src}",
5391 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
5393 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5394 "movntdqa\t{$src, $dst|$dst, $src}",
5395 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
5398 //===----------------------------------------------------------------------===//
5399 // SSE4.2 - Compare Instructions
5400 //===----------------------------------------------------------------------===//
5402 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
5403 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
5404 Intrinsic IntId128, bit Is2Addr = 1> {
5405 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
5406 (ins VR128:$src1, VR128:$src2),
5408 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5409 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5410 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5412 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
5413 (ins VR128:$src1, i128mem:$src2),
5415 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5416 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5418 (IntId128 VR128:$src1,
5419 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5422 let Predicates = [HasAVX] in {
5423 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
5426 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
5427 (VPCMPGTQrr VR128:$src1, VR128:$src2)>;
5428 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
5429 (VPCMPGTQrm VR128:$src1, addr:$src2)>;
5432 let Constraints = "$src1 = $dst" in
5433 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
5435 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
5436 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
5437 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
5438 (PCMPGTQrm VR128:$src1, addr:$src2)>;
5440 //===----------------------------------------------------------------------===//
5441 // SSE4.2 - String/text Processing Instructions
5442 //===----------------------------------------------------------------------===//
5444 // Packed Compare Implicit Length Strings, Return Mask
5445 multiclass pseudo_pcmpistrm<string asm> {
5446 def REG : PseudoI<(outs VR128:$dst),
5447 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5448 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
5450 def MEM : PseudoI<(outs VR128:$dst),
5451 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5452 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
5453 VR128:$src1, (load addr:$src2), imm:$src3))]>;
5456 let Defs = [EFLAGS], usesCustomInserter = 1 in {
5457 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
5458 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
5461 let Defs = [XMM0, EFLAGS], Predicates = [HasAVX] in {
5462 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
5463 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5464 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
5465 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
5466 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5467 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
5470 let Defs = [XMM0, EFLAGS] in {
5471 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
5472 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5473 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
5474 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
5475 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5476 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
5479 // Packed Compare Explicit Length Strings, Return Mask
5480 multiclass pseudo_pcmpestrm<string asm> {
5481 def REG : PseudoI<(outs VR128:$dst),
5482 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5483 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
5484 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
5485 def MEM : PseudoI<(outs VR128:$dst),
5486 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5487 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
5488 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
5491 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
5492 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
5493 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
5496 let Predicates = [HasAVX],
5497 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
5498 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
5499 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5500 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
5501 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
5502 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5503 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
5506 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
5507 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
5508 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5509 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
5510 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
5511 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5512 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
5515 // Packed Compare Implicit Length Strings, Return Index
5516 let Defs = [ECX, EFLAGS] in {
5517 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
5518 def rr : SS42AI<0x63, MRMSrcReg, (outs),
5519 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5520 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5521 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
5522 (implicit EFLAGS)]>, OpSize;
5523 def rm : SS42AI<0x63, MRMSrcMem, (outs),
5524 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5525 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5526 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
5527 (implicit EFLAGS)]>, OpSize;
5531 let Predicates = [HasAVX] in {
5532 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
5534 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
5536 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
5538 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
5540 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
5542 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
5546 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
5547 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
5548 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
5549 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
5550 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
5551 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
5553 // Packed Compare Explicit Length Strings, Return Index
5554 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
5555 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
5556 def rr : SS42AI<0x61, MRMSrcReg, (outs),
5557 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5558 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5559 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
5560 (implicit EFLAGS)]>, OpSize;
5561 def rm : SS42AI<0x61, MRMSrcMem, (outs),
5562 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5563 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5565 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
5566 (implicit EFLAGS)]>, OpSize;
5570 let Predicates = [HasAVX] in {
5571 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
5573 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
5575 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
5577 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
5579 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
5581 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
5585 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
5586 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
5587 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
5588 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
5589 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
5590 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
5592 //===----------------------------------------------------------------------===//
5593 // SSE4.2 - CRC Instructions
5594 //===----------------------------------------------------------------------===//
5596 // No CRC instructions have AVX equivalents
5598 // crc intrinsic instruction
5599 // This set of instructions are only rm, the only difference is the size
5601 let Constraints = "$src1 = $dst" in {
5602 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
5603 (ins GR32:$src1, i8mem:$src2),
5604 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5606 (int_x86_sse42_crc32_32_8 GR32:$src1,
5607 (load addr:$src2)))]>;
5608 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
5609 (ins GR32:$src1, GR8:$src2),
5610 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5612 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
5613 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5614 (ins GR32:$src1, i16mem:$src2),
5615 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5617 (int_x86_sse42_crc32_32_16 GR32:$src1,
5618 (load addr:$src2)))]>,
5620 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5621 (ins GR32:$src1, GR16:$src2),
5622 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5624 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
5626 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5627 (ins GR32:$src1, i32mem:$src2),
5628 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5630 (int_x86_sse42_crc32_32_32 GR32:$src1,
5631 (load addr:$src2)))]>;
5632 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5633 (ins GR32:$src1, GR32:$src2),
5634 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5636 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
5637 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
5638 (ins GR64:$src1, i8mem:$src2),
5639 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5641 (int_x86_sse42_crc32_64_8 GR64:$src1,
5642 (load addr:$src2)))]>,
5644 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
5645 (ins GR64:$src1, GR8:$src2),
5646 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5648 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
5650 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
5651 (ins GR64:$src1, i64mem:$src2),
5652 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5654 (int_x86_sse42_crc32_64_64 GR64:$src1,
5655 (load addr:$src2)))]>,
5657 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
5658 (ins GR64:$src1, GR64:$src2),
5659 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5661 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
5665 //===----------------------------------------------------------------------===//
5666 // AES-NI Instructions
5667 //===----------------------------------------------------------------------===//
5669 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
5670 Intrinsic IntId128, bit Is2Addr = 1> {
5671 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
5672 (ins VR128:$src1, VR128:$src2),
5674 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5675 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5676 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5678 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
5679 (ins VR128:$src1, i128mem:$src2),
5681 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5682 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5684 (IntId128 VR128:$src1,
5685 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5688 // Perform One Round of an AES Encryption/Decryption Flow
5689 let Predicates = [HasAVX, HasAES] in {
5690 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
5691 int_x86_aesni_aesenc, 0>, VEX_4V;
5692 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
5693 int_x86_aesni_aesenclast, 0>, VEX_4V;
5694 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
5695 int_x86_aesni_aesdec, 0>, VEX_4V;
5696 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
5697 int_x86_aesni_aesdeclast, 0>, VEX_4V;
5700 let Constraints = "$src1 = $dst" in {
5701 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
5702 int_x86_aesni_aesenc>;
5703 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
5704 int_x86_aesni_aesenclast>;
5705 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
5706 int_x86_aesni_aesdec>;
5707 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
5708 int_x86_aesni_aesdeclast>;
5711 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
5712 (AESENCrr VR128:$src1, VR128:$src2)>;
5713 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
5714 (AESENCrm VR128:$src1, addr:$src2)>;
5715 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
5716 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
5717 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
5718 (AESENCLASTrm VR128:$src1, addr:$src2)>;
5719 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
5720 (AESDECrr VR128:$src1, VR128:$src2)>;
5721 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
5722 (AESDECrm VR128:$src1, addr:$src2)>;
5723 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
5724 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
5725 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
5726 (AESDECLASTrm VR128:$src1, addr:$src2)>;
5728 // Perform the AES InvMixColumn Transformation
5729 let Predicates = [HasAVX, HasAES] in {
5730 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5732 "vaesimc\t{$src1, $dst|$dst, $src1}",
5734 (int_x86_aesni_aesimc VR128:$src1))]>,
5736 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5737 (ins i128mem:$src1),
5738 "vaesimc\t{$src1, $dst|$dst, $src1}",
5740 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5743 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5745 "aesimc\t{$src1, $dst|$dst, $src1}",
5747 (int_x86_aesni_aesimc VR128:$src1))]>,
5749 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5750 (ins i128mem:$src1),
5751 "aesimc\t{$src1, $dst|$dst, $src1}",
5753 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5756 // AES Round Key Generation Assist
5757 let Predicates = [HasAVX, HasAES] in {
5758 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5759 (ins VR128:$src1, i8imm:$src2),
5760 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5762 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5764 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5765 (ins i128mem:$src1, i8imm:$src2),
5766 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5768 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5772 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5773 (ins VR128:$src1, i8imm:$src2),
5774 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5776 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5778 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5779 (ins i128mem:$src1, i8imm:$src2),
5780 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5782 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5786 //===----------------------------------------------------------------------===//
5787 // CLMUL Instructions
5788 //===----------------------------------------------------------------------===//
5790 // Carry-less Multiplication instructions
5791 let Constraints = "$src1 = $dst" in {
5792 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5793 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5794 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5797 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5798 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5799 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5803 // AVX carry-less Multiplication instructions
5804 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5805 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5806 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5809 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5810 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5811 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5815 multiclass pclmul_alias<string asm, int immop> {
5816 def : InstAlias<!strconcat("pclmul", asm,
5817 "dq {$src, $dst|$dst, $src}"),
5818 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
5820 def : InstAlias<!strconcat("pclmul", asm,
5821 "dq {$src, $dst|$dst, $src}"),
5822 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
5824 def : InstAlias<!strconcat("vpclmul", asm,
5825 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
5826 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
5828 def : InstAlias<!strconcat("vpclmul", asm,
5829 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
5830 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
5832 defm : pclmul_alias<"hqhq", 0x11>;
5833 defm : pclmul_alias<"hqlq", 0x01>;
5834 defm : pclmul_alias<"lqhq", 0x10>;
5835 defm : pclmul_alias<"lqlq", 0x00>;
5837 //===----------------------------------------------------------------------===//
5839 //===----------------------------------------------------------------------===//
5841 //===----------------------------------------------------------------------===//
5842 // VBROADCAST - Load from memory and broadcast to all elements of the
5843 // destination operand
5845 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
5846 X86MemOperand x86memop, Intrinsic Int> :
5847 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5848 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5849 [(set RC:$dst, (Int addr:$src))]>, VEX;
5851 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
5852 int_x86_avx_vbroadcastss>;
5853 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
5854 int_x86_avx_vbroadcastss_256>;
5855 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
5856 int_x86_avx_vbroadcast_sd_256>;
5857 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
5858 int_x86_avx_vbroadcastf128_pd_256>;
5860 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
5861 (VBROADCASTF128 addr:$src)>;
5863 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
5864 (VBROADCASTSSY addr:$src)>;
5865 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
5866 (VBROADCASTSD addr:$src)>;
5867 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
5868 (VBROADCASTSSY addr:$src)>;
5869 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
5870 (VBROADCASTSD addr:$src)>;
5872 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
5873 (VBROADCASTSS addr:$src)>;
5874 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
5875 (VBROADCASTSS addr:$src)>;
5877 //===----------------------------------------------------------------------===//
5878 // VINSERTF128 - Insert packed floating-point values
5880 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
5881 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
5882 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5884 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
5885 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
5886 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5889 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
5890 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5891 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
5892 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5893 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
5894 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5896 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
5898 (VINSERTF128rr VR256:$src1, VR128:$src2,
5899 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5900 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
5902 (VINSERTF128rr VR256:$src1, VR128:$src2,
5903 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5904 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
5906 (VINSERTF128rr VR256:$src1, VR128:$src2,
5907 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5908 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
5910 (VINSERTF128rr VR256:$src1, VR128:$src2,
5911 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5912 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
5914 (VINSERTF128rr VR256:$src1, VR128:$src2,
5915 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5916 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
5918 (VINSERTF128rr VR256:$src1, VR128:$src2,
5919 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5921 // Special COPY patterns
5922 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
5923 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5924 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
5925 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5926 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
5927 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5928 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
5929 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5930 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
5931 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5932 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
5933 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5935 //===----------------------------------------------------------------------===//
5936 // VEXTRACTF128 - Extract packed floating-point values
5938 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
5939 (ins VR256:$src1, i8imm:$src2),
5940 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5942 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
5943 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
5944 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5947 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
5948 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5949 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
5950 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5951 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
5952 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5954 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5955 (v4f32 (VEXTRACTF128rr
5956 (v8f32 VR256:$src1),
5957 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5958 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5959 (v2f64 (VEXTRACTF128rr
5960 (v4f64 VR256:$src1),
5961 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5962 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5963 (v4i32 (VEXTRACTF128rr
5964 (v8i32 VR256:$src1),
5965 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5966 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5967 (v2i64 (VEXTRACTF128rr
5968 (v4i64 VR256:$src1),
5969 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5970 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5971 (v8i16 (VEXTRACTF128rr
5972 (v16i16 VR256:$src1),
5973 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5974 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5975 (v16i8 (VEXTRACTF128rr
5976 (v32i8 VR256:$src1),
5977 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5979 // Special COPY patterns
5980 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
5981 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
5982 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
5983 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
5985 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
5986 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
5987 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
5988 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
5990 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
5991 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
5992 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
5993 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
5996 //===----------------------------------------------------------------------===//
5997 // VMASKMOV - Conditional SIMD Packed Loads and Stores
5999 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
6000 Intrinsic IntLd, Intrinsic IntLd256,
6001 Intrinsic IntSt, Intrinsic IntSt256,
6002 PatFrag pf128, PatFrag pf256> {
6003 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
6004 (ins VR128:$src1, f128mem:$src2),
6005 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6006 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
6008 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
6009 (ins VR256:$src1, f256mem:$src2),
6010 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6011 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
6013 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
6014 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
6015 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6016 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
6017 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
6018 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
6019 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6020 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
6023 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
6024 int_x86_avx_maskload_ps,
6025 int_x86_avx_maskload_ps_256,
6026 int_x86_avx_maskstore_ps,
6027 int_x86_avx_maskstore_ps_256,
6028 memopv4f32, memopv8f32>;
6029 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
6030 int_x86_avx_maskload_pd,
6031 int_x86_avx_maskload_pd_256,
6032 int_x86_avx_maskstore_pd,
6033 int_x86_avx_maskstore_pd_256,
6034 memopv2f64, memopv4f64>;
6036 //===----------------------------------------------------------------------===//
6037 // VPERMIL - Permute Single and Double Floating-Point Values
6039 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
6040 RegisterClass RC, X86MemOperand x86memop_f,
6041 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
6042 Intrinsic IntVar, Intrinsic IntImm> {
6043 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
6044 (ins RC:$src1, RC:$src2),
6045 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6046 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
6047 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
6048 (ins RC:$src1, x86memop_i:$src2),
6049 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6050 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
6052 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
6053 (ins RC:$src1, i8imm:$src2),
6054 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6055 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
6056 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
6057 (ins x86memop_f:$src1, i8imm:$src2),
6058 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6059 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
6062 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
6063 memopv4f32, memopv4i32,
6064 int_x86_avx_vpermilvar_ps,
6065 int_x86_avx_vpermil_ps>;
6066 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
6067 memopv8f32, memopv8i32,
6068 int_x86_avx_vpermilvar_ps_256,
6069 int_x86_avx_vpermil_ps_256>;
6070 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
6071 memopv2f64, memopv2i64,
6072 int_x86_avx_vpermilvar_pd,
6073 int_x86_avx_vpermil_pd>;
6074 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
6075 memopv4f64, memopv4i64,
6076 int_x86_avx_vpermilvar_pd_256,
6077 int_x86_avx_vpermil_pd_256>;
6079 def : Pat<(v8f32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
6080 (VPERMILPSYri VR256:$src1, imm:$imm)>;
6081 def : Pat<(v4f64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
6082 (VPERMILPDYri VR256:$src1, imm:$imm)>;
6083 def : Pat<(v8i32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
6084 (VPERMILPSYri VR256:$src1, imm:$imm)>;
6085 def : Pat<(v4i64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
6086 (VPERMILPDYri VR256:$src1, imm:$imm)>;
6088 //===----------------------------------------------------------------------===//
6089 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
6091 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
6092 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
6093 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6095 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
6096 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
6097 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6100 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
6101 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6102 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
6103 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6104 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
6105 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6107 def : Pat<(int_x86_avx_vperm2f128_ps_256
6108 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
6109 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6110 def : Pat<(int_x86_avx_vperm2f128_pd_256
6111 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
6112 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6113 def : Pat<(int_x86_avx_vperm2f128_si_256
6114 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
6115 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6117 def : Pat<(v8f32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6118 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6119 def : Pat<(v8i32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6120 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6121 def : Pat<(v4i64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6122 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6123 def : Pat<(v4f64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6124 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6125 def : Pat<(v32i8 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6126 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6127 def : Pat<(v16i16 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6128 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6130 //===----------------------------------------------------------------------===//
6131 // VZERO - Zero YMM registers
6133 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
6134 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
6135 // Zero All YMM registers
6136 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
6137 [(int_x86_avx_vzeroall)]>, VEX, VEX_L, Requires<[HasAVX]>;
6141 // Zero Upper bits of YMM registers
6142 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
6143 [(int_x86_avx_vzeroupper)]>, VEX, Requires<[HasAVX]>;
6145 //===----------------------------------------------------------------------===//
6146 // SSE Shuffle pattern fragments
6147 //===----------------------------------------------------------------------===//
6149 // This is part of a "work in progress" refactoring. The idea is that all
6150 // vector shuffles are going to be translated into target specific nodes and
6151 // directly matched by the patterns below (which can be changed along the way)
6152 // The AVX version of some but not all of them are described here, and more
6153 // should come in a near future.
6155 // Shuffle with MOVLHPD
6156 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
6157 (scalar_to_vector (loadf64 addr:$src2)))),
6158 (MOVHPDrm VR128:$src1, addr:$src2)>;
6160 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
6161 // is during lowering, where it's not possible to recognize the load fold cause
6162 // it has two uses through a bitcast. One use disappears at isel time and the
6163 // fold opportunity reappears.
6164 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
6165 (scalar_to_vector (loadf64 addr:$src2)))),
6166 (MOVHPDrm VR128:$src1, addr:$src2)>;
6168 // Shuffle with MOVSS
6169 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
6170 (MOVSSrr VR128:$src1, FR32:$src2)>;
6171 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
6172 (MOVSSrr (v4i32 VR128:$src1),
6173 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
6174 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
6175 (MOVSSrr (v4f32 VR128:$src1),
6176 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
6178 // Shuffle with MOVSD
6179 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
6180 (MOVSDrr VR128:$src1, FR64:$src2)>;
6181 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
6182 (MOVSDrr (v2i64 VR128:$src1),
6183 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
6184 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
6185 (MOVSDrr (v2f64 VR128:$src1),
6186 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
6187 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
6188 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
6189 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
6190 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
6192 // Shuffle with MOVLPS
6193 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
6194 (MOVLPSrm VR128:$src1, addr:$src2)>;
6195 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
6196 (MOVLPSrm VR128:$src1, addr:$src2)>;
6197 def : Pat<(X86Movlps VR128:$src1,
6198 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
6199 (MOVLPSrm VR128:$src1, addr:$src2)>;
6200 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
6201 // is during lowering, where it's not possible to recognize the load fold cause
6202 // it has two uses through a bitcast. One use disappears at isel time and the
6203 // fold opportunity reappears.
6204 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
6205 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
6207 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
6208 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
6210 // Shuffle with MOVLPD
6211 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
6212 (MOVLPDrm VR128:$src1, addr:$src2)>;
6213 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
6214 (MOVLPDrm VR128:$src1, addr:$src2)>;
6215 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
6216 (scalar_to_vector (loadf64 addr:$src2)))),
6217 (MOVLPDrm VR128:$src1, addr:$src2)>;
6219 // Extra patterns to match stores with MOVHPS/PD and MOVLPS/PD
6220 def : Pat<(store (f64 (vector_extract
6221 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))),addr:$dst),
6222 (MOVHPSmr addr:$dst, VR128:$src)>;
6223 def : Pat<(store (f64 (vector_extract
6224 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
6225 (MOVHPDmr addr:$dst, VR128:$src)>;
6227 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),addr:$src1),
6228 (MOVLPSmr addr:$src1, VR128:$src2)>;
6229 def : Pat<(store (v4i32 (X86Movlps
6230 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
6231 (MOVLPSmr addr:$src1, VR128:$src2)>;
6233 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
6234 (MOVLPDmr addr:$src1, VR128:$src2)>;
6235 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
6236 (MOVLPDmr addr:$src1, VR128:$src2)>;