1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
21 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
27 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
28 InstrItinClass arg_ri> {
29 InstrItinClass rr = arg_rr;
30 InstrItinClass rm = arg_rm;
31 InstrItinClass ri = arg_ri;
36 def SSE_ALU_F32S : OpndItins<
37 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
40 def SSE_ALU_F64S : OpndItins<
41 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
44 def SSE_ALU_ITINS_S : SizeItins<
45 SSE_ALU_F32S, SSE_ALU_F64S
48 def SSE_MUL_F32S : OpndItins<
49 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
52 def SSE_MUL_F64S : OpndItins<
53 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
56 def SSE_MUL_ITINS_S : SizeItins<
57 SSE_MUL_F32S, SSE_MUL_F64S
60 def SSE_DIV_F32S : OpndItins<
61 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
64 def SSE_DIV_F64S : OpndItins<
65 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
68 def SSE_DIV_ITINS_S : SizeItins<
69 SSE_DIV_F32S, SSE_DIV_F64S
73 def SSE_ALU_F32P : OpndItins<
74 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
77 def SSE_ALU_F64P : OpndItins<
78 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
81 def SSE_ALU_ITINS_P : SizeItins<
82 SSE_ALU_F32P, SSE_ALU_F64P
85 def SSE_MUL_F32P : OpndItins<
86 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
89 def SSE_MUL_F64P : OpndItins<
90 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
93 def SSE_MUL_ITINS_P : SizeItins<
94 SSE_MUL_F32P, SSE_MUL_F64P
97 def SSE_DIV_F32P : OpndItins<
98 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
101 def SSE_DIV_F64P : OpndItins<
102 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
105 def SSE_DIV_ITINS_P : SizeItins<
106 SSE_DIV_F32P, SSE_DIV_F64P
109 def SSE_BIT_ITINS_P : OpndItins<
110 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
113 def SSE_INTALU_ITINS_P : OpndItins<
114 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
117 def SSE_INTALUQ_ITINS_P : OpndItins<
118 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
121 def SSE_INTMUL_ITINS_P : OpndItins<
122 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
125 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
126 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
129 def SSE_MOVA_ITINS : OpndItins<
130 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
133 def SSE_MOVU_ITINS : OpndItins<
134 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
137 //===----------------------------------------------------------------------===//
138 // SSE 1 & 2 Instructions Classes
139 //===----------------------------------------------------------------------===//
141 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
142 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
143 RegisterClass RC, X86MemOperand x86memop,
146 let isCommutable = 1 in {
147 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
149 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
150 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
151 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>;
153 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
155 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
156 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
157 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>;
160 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
161 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
162 string asm, string SSEVer, string FPSizeStr,
163 Operand memopr, ComplexPattern mem_cpat,
166 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
168 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
169 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
170 [(set RC:$dst, (!cast<Intrinsic>(
171 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
172 RC:$src1, RC:$src2))], itins.rr>;
173 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
175 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
176 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
177 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
178 SSEVer, "_", OpcodeStr, FPSizeStr))
179 RC:$src1, mem_cpat:$src2))], itins.rm>;
182 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
183 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
184 RegisterClass RC, ValueType vt,
185 X86MemOperand x86memop, PatFrag mem_frag,
186 Domain d, OpndItins itins, bit Is2Addr = 1> {
187 let isCommutable = 1 in
188 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
190 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
191 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
192 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>;
194 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
196 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
197 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
198 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
202 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
203 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
204 string OpcodeStr, X86MemOperand x86memop,
205 list<dag> pat_rr, list<dag> pat_rm,
207 bit rr_hasSideEffects = 0> {
208 let isCommutable = 1, neverHasSideEffects = rr_hasSideEffects in
209 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
211 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
212 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
213 pat_rr, IIC_DEFAULT, d>;
214 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
216 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
217 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
218 pat_rm, IIC_DEFAULT, d>;
221 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
222 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
223 string asm, string SSEVer, string FPSizeStr,
224 X86MemOperand x86memop, PatFrag mem_frag,
225 Domain d, OpndItins itins, bit Is2Addr = 1> {
226 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
228 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
229 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
230 [(set RC:$dst, (!cast<Intrinsic>(
231 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
232 RC:$src1, RC:$src2))], IIC_DEFAULT, d>;
233 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
235 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
236 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
237 [(set RC:$dst, (!cast<Intrinsic>(
238 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
239 RC:$src1, (mem_frag addr:$src2)))], IIC_DEFAULT, d>;
242 //===----------------------------------------------------------------------===//
243 // Non-instruction patterns
244 //===----------------------------------------------------------------------===//
246 // A vector extract of the first f32/f64 position is a subregister copy
247 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
248 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
249 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
250 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
252 // A 128-bit subvector extract from the first 256-bit vector position
253 // is a subregister copy that needs no instruction.
254 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
255 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
256 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
257 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
259 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
260 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
261 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
262 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
264 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
265 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
266 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
267 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
269 // A 128-bit subvector insert to the first 256-bit vector position
270 // is a subregister copy that needs no instruction.
271 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
272 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
273 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
274 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
275 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
276 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
277 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
278 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
279 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
280 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
281 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
282 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
284 // Implicitly promote a 32-bit scalar to a vector.
285 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
286 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
287 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
288 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
289 // Implicitly promote a 64-bit scalar to a vector.
290 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
291 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
292 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
293 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
295 // Bitcasts between 128-bit vector types. Return the original type since
296 // no instruction is needed for the conversion
297 let Predicates = [HasSSE2] in {
298 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
299 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
300 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
301 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
302 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
303 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
304 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
305 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
306 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
307 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
308 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
309 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
310 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
311 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
312 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
313 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
314 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
315 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
316 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
317 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
318 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
319 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
320 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
321 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
322 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
323 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
324 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
325 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
326 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
327 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
330 // Bitcasts between 256-bit vector types. Return the original type since
331 // no instruction is needed for the conversion
332 let Predicates = [HasAVX] in {
333 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
334 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
335 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
336 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
337 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
338 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
339 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
340 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
341 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
342 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
343 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
344 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
345 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
346 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
347 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
348 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
349 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
350 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
351 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
352 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
353 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
354 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
355 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
356 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
357 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
358 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
359 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
360 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
361 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
362 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
365 // Alias instructions that map fld0 to pxor for sse.
366 // This is expanded by ExpandPostRAPseudos.
367 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
369 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
370 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
371 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
372 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
375 //===----------------------------------------------------------------------===//
376 // AVX & SSE - Zero/One Vectors
377 //===----------------------------------------------------------------------===//
379 // Alias instruction that maps zero vector to pxor / xorp* for sse.
380 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
381 // swizzled by ExecutionDepsFix to pxor.
382 // We set canFoldAsLoad because this can be converted to a constant-pool
383 // load of an all-zeros value if folding it would be beneficial.
384 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
385 isPseudo = 1, neverHasSideEffects = 1 in {
386 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "", []>;
389 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
390 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
391 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
392 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
393 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
394 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
397 // The same as done above but for AVX. The 256-bit ISA does not support PI,
398 // and doesn't need it because on sandy bridge the register is set to zero
399 // at the rename stage without using any execution unit, so SET0PSY
400 // and SET0PDY can be used for vector int instructions without penalty
401 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
402 // JIT implementatioan, it does not expand the instructions below like
403 // X86MCInstLower does.
404 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
405 isCodeGenOnly = 1 in {
406 let Predicates = [HasAVX] in {
407 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
408 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
409 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
410 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
412 let Predicates = [HasAVX2], neverHasSideEffects = 1 in
413 def AVX2_SET0 : PDI<0xef, MRMInitReg, (outs VR256:$dst), (ins), "",
417 let Predicates = [HasAVX2], AddedComplexity = 5 in {
418 def : Pat<(v4i64 immAllZerosV), (AVX2_SET0)>;
419 def : Pat<(v8i32 immAllZerosV), (AVX2_SET0)>;
420 def : Pat<(v16i16 immAllZerosV), (AVX2_SET0)>;
421 def : Pat<(v32i8 immAllZerosV), (AVX2_SET0)>;
424 // AVX has no support for 256-bit integer instructions, but since the 128-bit
425 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
426 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
427 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
428 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
430 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
431 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
432 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
434 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
435 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
436 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
438 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
439 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
440 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
442 // We set canFoldAsLoad because this can be converted to a constant-pool
443 // load of an all-ones value if folding it would be beneficial.
444 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
445 // JIT implementation, it does not expand the instructions below like
446 // X86MCInstLower does.
447 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
448 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in {
449 let Predicates = [HasAVX] in
450 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
451 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
452 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
453 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
454 let Predicates = [HasAVX2] in
455 def AVX2_SETALLONES : PDI<0x76, MRMInitReg, (outs VR256:$dst), (ins), "",
456 [(set VR256:$dst, (v8i32 immAllOnesV))]>, VEX_4V;
460 //===----------------------------------------------------------------------===//
461 // SSE 1 & 2 - Move FP Scalar Instructions
463 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
464 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
465 // is used instead. Register-to-register movss/movsd is not modeled as an
466 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
467 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
468 //===----------------------------------------------------------------------===//
470 class sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt, string asm> :
471 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
472 [(set VR128:$dst, (vt (OpNode VR128:$src1,
473 (scalar_to_vector RC:$src2))))],
476 // Loading from memory automatically zeroing upper bits.
477 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
478 PatFrag mem_pat, string OpcodeStr> :
479 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
480 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
481 [(set RC:$dst, (mem_pat addr:$src))],
485 def VMOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
486 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
488 def VMOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
489 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
492 // For the disassembler
493 let isCodeGenOnly = 1 in {
494 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
495 (ins VR128:$src1, FR32:$src2),
496 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
499 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
500 (ins VR128:$src1, FR64:$src2),
501 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
506 let canFoldAsLoad = 1, isReMaterializable = 1 in {
507 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
509 let AddedComplexity = 20 in
510 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
514 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
515 "movss\t{$src, $dst|$dst, $src}",
516 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
518 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
519 "movsd\t{$src, $dst|$dst, $src}",
520 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
524 let Constraints = "$src1 = $dst" in {
525 def MOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
526 "movss\t{$src2, $dst|$dst, $src2}">, XS;
527 def MOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
528 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
530 // For the disassembler
531 let isCodeGenOnly = 1 in {
532 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
533 (ins VR128:$src1, FR32:$src2),
534 "movss\t{$src2, $dst|$dst, $src2}", [],
535 IIC_SSE_MOV_S_RR>, XS;
536 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
537 (ins VR128:$src1, FR64:$src2),
538 "movsd\t{$src2, $dst|$dst, $src2}", [],
539 IIC_SSE_MOV_S_RR>, XD;
543 let canFoldAsLoad = 1, isReMaterializable = 1 in {
544 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
546 let AddedComplexity = 20 in
547 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
550 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
551 "movss\t{$src, $dst|$dst, $src}",
552 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
553 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
554 "movsd\t{$src, $dst|$dst, $src}",
555 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
558 let Predicates = [HasAVX] in {
559 let AddedComplexity = 15 in {
560 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
561 // MOVS{S,D} to the lower bits.
562 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
563 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
564 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
565 (VMOVSSrr (v4f32 (V_SET0)),
566 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
567 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
568 (VMOVSSrr (v4i32 (V_SET0)),
569 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
570 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
571 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
573 // Move low f32 and clear high bits.
574 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
575 (SUBREG_TO_REG (i32 0),
576 (VMOVSSrr (v4f32 (V_SET0)),
577 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_ss)), sub_xmm)>;
578 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
579 (SUBREG_TO_REG (i32 0),
580 (VMOVSSrr (v4i32 (V_SET0)),
581 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_ss)), sub_xmm)>;
584 let AddedComplexity = 20 in {
585 // MOVSSrm zeros the high parts of the register; represent this
586 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
587 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
588 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
589 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
590 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
591 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
592 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
594 // MOVSDrm zeros the high parts of the register; represent this
595 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
596 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
597 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
598 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
599 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
600 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
601 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
602 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
603 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
604 def : Pat<(v2f64 (X86vzload addr:$src)),
605 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
607 // Represent the same patterns above but in the form they appear for
609 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
610 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (i32 0)))),
611 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
612 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
613 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
614 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
615 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
616 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
617 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
619 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
620 (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
621 (SUBREG_TO_REG (i32 0),
622 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
624 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
625 (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
626 (SUBREG_TO_REG (i64 0),
627 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
629 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
630 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (i32 0)))),
631 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
633 // Move low f64 and clear high bits.
634 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
635 (SUBREG_TO_REG (i32 0),
636 (VMOVSDrr (v2f64 (V_SET0)),
637 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_sd)), sub_xmm)>;
639 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
640 (SUBREG_TO_REG (i32 0),
641 (VMOVSDrr (v2i64 (V_SET0)),
642 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_sd)), sub_xmm)>;
644 // Extract and store.
645 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
648 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
649 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
652 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
654 // Shuffle with VMOVSS
655 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
656 (VMOVSSrr (v4i32 VR128:$src1),
657 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
658 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
659 (VMOVSSrr (v4f32 VR128:$src1),
660 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
663 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
664 (SUBREG_TO_REG (i32 0),
665 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_ss),
666 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_ss)), sub_xmm)>;
667 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
668 (SUBREG_TO_REG (i32 0),
669 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_ss),
670 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_ss)), sub_xmm)>;
672 // Shuffle with VMOVSD
673 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
674 (VMOVSDrr (v2i64 VR128:$src1),
675 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
676 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
677 (VMOVSDrr (v2f64 VR128:$src1),
678 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
679 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
680 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
682 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
683 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
687 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
688 (SUBREG_TO_REG (i32 0),
689 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_sd),
690 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_sd)), sub_xmm)>;
691 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
692 (SUBREG_TO_REG (i32 0),
693 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_sd),
694 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_sd)), sub_xmm)>;
697 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
698 // is during lowering, where it's not possible to recognize the fold cause
699 // it has two uses through a bitcast. One use disappears at isel time and the
700 // fold opportunity reappears.
701 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
702 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),
704 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
705 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),
707 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
708 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
710 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
711 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
715 let Predicates = [HasSSE1] in {
716 let AddedComplexity = 15 in {
717 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
718 // MOVSS to the lower bits.
719 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
720 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
721 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
722 (MOVSSrr (v4f32 (V_SET0)),
723 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
724 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
725 (MOVSSrr (v4i32 (V_SET0)),
726 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
729 let AddedComplexity = 20 in {
730 // MOVSSrm zeros the high parts of the register; represent this
731 // with SUBREG_TO_REG.
732 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
733 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
734 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
735 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
736 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
737 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
740 // Extract and store.
741 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
744 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
746 // Shuffle with MOVSS
747 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
748 (MOVSSrr (v4i32 VR128:$src1),
749 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
750 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
751 (MOVSSrr (v4f32 VR128:$src1),
752 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
755 let Predicates = [HasSSE2] in {
756 let AddedComplexity = 15 in {
757 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
758 // MOVSD to the lower bits.
759 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
760 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
763 let AddedComplexity = 20 in {
764 // MOVSDrm zeros the high parts of the register; represent this
765 // with SUBREG_TO_REG.
766 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
767 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
768 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
769 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
770 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
771 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
772 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
773 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
774 def : Pat<(v2f64 (X86vzload addr:$src)),
775 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
778 // Extract and store.
779 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
782 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
784 // Shuffle with MOVSD
785 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
786 (MOVSDrr (v2i64 VR128:$src1),
787 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
788 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
789 (MOVSDrr (v2f64 VR128:$src1),
790 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
791 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
792 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
793 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
794 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
796 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
797 // is during lowering, where it's not possible to recognize the fold cause
798 // it has two uses through a bitcast. One use disappears at isel time and the
799 // fold opportunity reappears.
800 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
801 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),sub_sd))>;
802 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
803 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),sub_sd))>;
804 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
805 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
806 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
807 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
810 //===----------------------------------------------------------------------===//
811 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
812 //===----------------------------------------------------------------------===//
814 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
815 X86MemOperand x86memop, PatFrag ld_frag,
816 string asm, Domain d,
818 bit IsReMaterializable = 1> {
819 let neverHasSideEffects = 1 in
820 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
821 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>;
822 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
823 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
824 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
825 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>;
828 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
829 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
831 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
832 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
834 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
835 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
837 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
838 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
841 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
842 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
844 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
845 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
847 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
848 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
850 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
851 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
853 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
854 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
856 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
857 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
859 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
860 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
862 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
863 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
866 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
867 "movaps\t{$src, $dst|$dst, $src}",
868 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
869 IIC_SSE_MOVA_P_MR>, VEX;
870 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
871 "movapd\t{$src, $dst|$dst, $src}",
872 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
873 IIC_SSE_MOVA_P_MR>, VEX;
874 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
875 "movups\t{$src, $dst|$dst, $src}",
876 [(store (v4f32 VR128:$src), addr:$dst)],
877 IIC_SSE_MOVU_P_MR>, VEX;
878 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
879 "movupd\t{$src, $dst|$dst, $src}",
880 [(store (v2f64 VR128:$src), addr:$dst)],
881 IIC_SSE_MOVU_P_MR>, VEX;
882 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
883 "movaps\t{$src, $dst|$dst, $src}",
884 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
885 IIC_SSE_MOVA_P_MR>, VEX;
886 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
887 "movapd\t{$src, $dst|$dst, $src}",
888 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
889 IIC_SSE_MOVA_P_MR>, VEX;
890 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
891 "movups\t{$src, $dst|$dst, $src}",
892 [(store (v8f32 VR256:$src), addr:$dst)],
893 IIC_SSE_MOVU_P_MR>, VEX;
894 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
895 "movupd\t{$src, $dst|$dst, $src}",
896 [(store (v4f64 VR256:$src), addr:$dst)],
897 IIC_SSE_MOVU_P_MR>, VEX;
900 let isCodeGenOnly = 1 in {
901 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
903 "movaps\t{$src, $dst|$dst, $src}", [],
904 IIC_SSE_MOVA_P_RR>, VEX;
905 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
907 "movapd\t{$src, $dst|$dst, $src}", [],
908 IIC_SSE_MOVA_P_RR>, VEX;
909 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
911 "movups\t{$src, $dst|$dst, $src}", [],
912 IIC_SSE_MOVU_P_RR>, VEX;
913 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
915 "movupd\t{$src, $dst|$dst, $src}", [],
916 IIC_SSE_MOVU_P_RR>, VEX;
917 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
919 "movaps\t{$src, $dst|$dst, $src}", [],
920 IIC_SSE_MOVA_P_RR>, VEX;
921 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
923 "movapd\t{$src, $dst|$dst, $src}", [],
924 IIC_SSE_MOVA_P_RR>, VEX;
925 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
927 "movups\t{$src, $dst|$dst, $src}", [],
928 IIC_SSE_MOVU_P_RR>, VEX;
929 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
931 "movupd\t{$src, $dst|$dst, $src}", [],
932 IIC_SSE_MOVU_P_RR>, VEX;
935 let Predicates = [HasAVX] in {
936 def : Pat<(v8i32 (X86vzmovl
937 (insert_subvector undef, (v4i32 VR128:$src), (i32 0)))),
938 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
939 def : Pat<(v4i64 (X86vzmovl
940 (insert_subvector undef, (v2i64 VR128:$src), (i32 0)))),
941 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
942 def : Pat<(v8f32 (X86vzmovl
943 (insert_subvector undef, (v4f32 VR128:$src), (i32 0)))),
944 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
945 def : Pat<(v4f64 (X86vzmovl
946 (insert_subvector undef, (v2f64 VR128:$src), (i32 0)))),
947 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
951 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
952 (VMOVUPSYmr addr:$dst, VR256:$src)>;
953 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
954 (VMOVUPDYmr addr:$dst, VR256:$src)>;
956 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
957 "movaps\t{$src, $dst|$dst, $src}",
958 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
960 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
961 "movapd\t{$src, $dst|$dst, $src}",
962 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
964 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
965 "movups\t{$src, $dst|$dst, $src}",
966 [(store (v4f32 VR128:$src), addr:$dst)],
968 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
969 "movupd\t{$src, $dst|$dst, $src}",
970 [(store (v2f64 VR128:$src), addr:$dst)],
974 let isCodeGenOnly = 1 in {
975 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
976 "movaps\t{$src, $dst|$dst, $src}", [],
978 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
979 "movapd\t{$src, $dst|$dst, $src}", [],
981 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
982 "movups\t{$src, $dst|$dst, $src}", [],
984 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
985 "movupd\t{$src, $dst|$dst, $src}", [],
989 let Predicates = [HasAVX] in {
990 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
991 (VMOVUPSmr addr:$dst, VR128:$src)>;
992 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
993 (VMOVUPDmr addr:$dst, VR128:$src)>;
996 let Predicates = [HasSSE1] in
997 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
998 (MOVUPSmr addr:$dst, VR128:$src)>;
999 let Predicates = [HasSSE2] in
1000 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1001 (MOVUPDmr addr:$dst, VR128:$src)>;
1003 // Use vmovaps/vmovups for AVX integer load/store.
1004 let Predicates = [HasAVX] in {
1005 // 128-bit load/store
1006 def : Pat<(alignedloadv2i64 addr:$src),
1007 (VMOVAPSrm addr:$src)>;
1008 def : Pat<(loadv2i64 addr:$src),
1009 (VMOVUPSrm addr:$src)>;
1011 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1012 (VMOVAPSmr addr:$dst, VR128:$src)>;
1013 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1014 (VMOVAPSmr addr:$dst, VR128:$src)>;
1015 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1016 (VMOVAPSmr addr:$dst, VR128:$src)>;
1017 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1018 (VMOVAPSmr addr:$dst, VR128:$src)>;
1019 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1020 (VMOVUPSmr addr:$dst, VR128:$src)>;
1021 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1022 (VMOVUPSmr addr:$dst, VR128:$src)>;
1023 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1024 (VMOVUPSmr addr:$dst, VR128:$src)>;
1025 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1026 (VMOVUPSmr addr:$dst, VR128:$src)>;
1028 // 256-bit load/store
1029 def : Pat<(alignedloadv4i64 addr:$src),
1030 (VMOVAPSYrm addr:$src)>;
1031 def : Pat<(loadv4i64 addr:$src),
1032 (VMOVUPSYrm addr:$src)>;
1033 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1034 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1035 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1036 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1037 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1038 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1039 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1040 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1041 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1042 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1043 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1044 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1045 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1046 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1047 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1048 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1051 // Use movaps / movups for SSE integer load / store (one byte shorter).
1052 // The instructions selected below are then converted to MOVDQA/MOVDQU
1053 // during the SSE domain pass.
1054 let Predicates = [HasSSE1] in {
1055 def : Pat<(alignedloadv2i64 addr:$src),
1056 (MOVAPSrm addr:$src)>;
1057 def : Pat<(loadv2i64 addr:$src),
1058 (MOVUPSrm addr:$src)>;
1060 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1061 (MOVAPSmr addr:$dst, VR128:$src)>;
1062 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1063 (MOVAPSmr addr:$dst, VR128:$src)>;
1064 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1065 (MOVAPSmr addr:$dst, VR128:$src)>;
1066 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1067 (MOVAPSmr addr:$dst, VR128:$src)>;
1068 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1069 (MOVUPSmr addr:$dst, VR128:$src)>;
1070 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1071 (MOVUPSmr addr:$dst, VR128:$src)>;
1072 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1073 (MOVUPSmr addr:$dst, VR128:$src)>;
1074 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1075 (MOVUPSmr addr:$dst, VR128:$src)>;
1078 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1079 // bits are disregarded. FIXME: Set encoding to pseudo!
1080 let neverHasSideEffects = 1 in {
1081 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1082 "movaps\t{$src, $dst|$dst, $src}", [],
1083 IIC_SSE_MOVA_P_RR>, VEX;
1084 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1085 "movapd\t{$src, $dst|$dst, $src}", [],
1086 IIC_SSE_MOVA_P_RR>, VEX;
1087 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1088 "movaps\t{$src, $dst|$dst, $src}", [],
1090 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1091 "movapd\t{$src, $dst|$dst, $src}", [],
1095 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1096 // bits are disregarded. FIXME: Set encoding to pseudo!
1097 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1098 let isCodeGenOnly = 1 in {
1099 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1100 "movaps\t{$src, $dst|$dst, $src}",
1101 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1102 IIC_SSE_MOVA_P_RM>, VEX;
1103 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1104 "movapd\t{$src, $dst|$dst, $src}",
1105 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1106 IIC_SSE_MOVA_P_RM>, VEX;
1108 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1109 "movaps\t{$src, $dst|$dst, $src}",
1110 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1112 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1113 "movapd\t{$src, $dst|$dst, $src}",
1114 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1118 //===----------------------------------------------------------------------===//
1119 // SSE 1 & 2 - Move Low packed FP Instructions
1120 //===----------------------------------------------------------------------===//
1122 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
1123 SDNode psnode, SDNode pdnode, string base_opc,
1124 string asm_opr, InstrItinClass itin> {
1125 def PSrm : PI<opc, MRMSrcMem,
1126 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1127 !strconcat(base_opc, "s", asm_opr),
1130 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1131 itin, SSEPackedSingle>, TB;
1133 def PDrm : PI<opc, MRMSrcMem,
1134 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
1135 !strconcat(base_opc, "d", asm_opr),
1136 [(set RC:$dst, (v2f64 (pdnode RC:$src1,
1137 (scalar_to_vector (loadf64 addr:$src2)))))],
1138 itin, SSEPackedDouble>, TB, OpSize;
1141 let AddedComplexity = 20 in {
1142 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1143 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1144 IIC_SSE_MOV_LH>, VEX_4V;
1146 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1147 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1148 "\t{$src2, $dst|$dst, $src2}",
1152 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1153 "movlps\t{$src, $dst|$dst, $src}",
1154 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1155 (iPTR 0))), addr:$dst)],
1156 IIC_SSE_MOV_LH>, VEX;
1157 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1158 "movlpd\t{$src, $dst|$dst, $src}",
1159 [(store (f64 (vector_extract (v2f64 VR128:$src),
1160 (iPTR 0))), addr:$dst)],
1161 IIC_SSE_MOV_LH>, VEX;
1162 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1163 "movlps\t{$src, $dst|$dst, $src}",
1164 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1165 (iPTR 0))), addr:$dst)],
1167 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1168 "movlpd\t{$src, $dst|$dst, $src}",
1169 [(store (f64 (vector_extract (v2f64 VR128:$src),
1170 (iPTR 0))), addr:$dst)],
1173 let Predicates = [HasAVX] in {
1174 // Shuffle with VMOVLPS
1175 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1176 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1177 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1178 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1180 // Shuffle with VMOVLPD
1181 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1182 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1183 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1184 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1187 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1189 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1190 def : Pat<(store (v4i32 (X86Movlps
1191 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1192 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1193 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1195 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1196 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1198 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1201 let Predicates = [HasSSE1] in {
1202 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1203 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1204 (iPTR 0))), addr:$src1),
1205 (MOVLPSmr addr:$src1, VR128:$src2)>;
1207 // Shuffle with MOVLPS
1208 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1209 (MOVLPSrm VR128:$src1, addr:$src2)>;
1210 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1211 (MOVLPSrm VR128:$src1, addr:$src2)>;
1212 def : Pat<(X86Movlps VR128:$src1,
1213 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1214 (MOVLPSrm VR128:$src1, addr:$src2)>;
1217 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1219 (MOVLPSmr addr:$src1, VR128:$src2)>;
1220 def : Pat<(store (v4i32 (X86Movlps
1221 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1223 (MOVLPSmr addr:$src1, VR128:$src2)>;
1226 let Predicates = [HasSSE2] in {
1227 // Shuffle with MOVLPD
1228 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1229 (MOVLPDrm VR128:$src1, addr:$src2)>;
1230 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1231 (MOVLPDrm VR128:$src1, addr:$src2)>;
1234 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1236 (MOVLPDmr addr:$src1, VR128:$src2)>;
1237 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1239 (MOVLPDmr addr:$src1, VR128:$src2)>;
1242 //===----------------------------------------------------------------------===//
1243 // SSE 1 & 2 - Move Hi packed FP Instructions
1244 //===----------------------------------------------------------------------===//
1246 let AddedComplexity = 20 in {
1247 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1248 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1249 IIC_SSE_MOV_LH>, VEX_4V;
1251 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1252 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1253 "\t{$src2, $dst|$dst, $src2}",
1257 // v2f64 extract element 1 is always custom lowered to unpack high to low
1258 // and extract element 0 so the non-store version isn't too horrible.
1259 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1260 "movhps\t{$src, $dst|$dst, $src}",
1261 [(store (f64 (vector_extract
1262 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1263 (bc_v2f64 (v4f32 VR128:$src))),
1264 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1265 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1266 "movhpd\t{$src, $dst|$dst, $src}",
1267 [(store (f64 (vector_extract
1268 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1269 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1270 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1271 "movhps\t{$src, $dst|$dst, $src}",
1272 [(store (f64 (vector_extract
1273 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1274 (bc_v2f64 (v4f32 VR128:$src))),
1275 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1276 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1277 "movhpd\t{$src, $dst|$dst, $src}",
1278 [(store (f64 (vector_extract
1279 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1280 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1282 let Predicates = [HasAVX] in {
1284 def : Pat<(X86Movlhps VR128:$src1,
1285 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1286 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1287 def : Pat<(X86Movlhps VR128:$src1,
1288 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1289 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1291 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1292 // is during lowering, where it's not possible to recognize the load fold
1293 // cause it has two uses through a bitcast. One use disappears at isel time
1294 // and the fold opportunity reappears.
1295 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1296 (scalar_to_vector (loadf64 addr:$src2)))),
1297 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1300 let Predicates = [HasSSE1] in {
1302 def : Pat<(X86Movlhps VR128:$src1,
1303 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1304 (MOVHPSrm VR128:$src1, addr:$src2)>;
1305 def : Pat<(X86Movlhps VR128:$src1,
1306 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1307 (MOVHPSrm VR128:$src1, addr:$src2)>;
1310 let Predicates = [HasSSE2] in {
1311 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1312 // is during lowering, where it's not possible to recognize the load fold
1313 // cause it has two uses through a bitcast. One use disappears at isel time
1314 // and the fold opportunity reappears.
1315 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1316 (scalar_to_vector (loadf64 addr:$src2)))),
1317 (MOVHPDrm VR128:$src1, addr:$src2)>;
1320 //===----------------------------------------------------------------------===//
1321 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1322 //===----------------------------------------------------------------------===//
1324 let AddedComplexity = 20 in {
1325 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1326 (ins VR128:$src1, VR128:$src2),
1327 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1329 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1332 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1333 (ins VR128:$src1, VR128:$src2),
1334 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1336 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1340 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1341 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1342 (ins VR128:$src1, VR128:$src2),
1343 "movlhps\t{$src2, $dst|$dst, $src2}",
1345 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1347 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1348 (ins VR128:$src1, VR128:$src2),
1349 "movhlps\t{$src2, $dst|$dst, $src2}",
1351 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1355 let Predicates = [HasAVX] in {
1357 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1358 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1359 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1360 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1363 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1364 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1367 let Predicates = [HasSSE1] in {
1369 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1370 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1371 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1372 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1375 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1376 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1379 //===----------------------------------------------------------------------===//
1380 // SSE 1 & 2 - Conversion Instructions
1381 //===----------------------------------------------------------------------===//
1383 def SSE_CVT_PD : OpndItins<
1384 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1387 def SSE_CVT_PS : OpndItins<
1388 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1391 def SSE_CVT_Scalar : OpndItins<
1392 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1395 def SSE_CVT_SS2SI_32 : OpndItins<
1396 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1399 def SSE_CVT_SS2SI_64 : OpndItins<
1400 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1403 def SSE_CVT_SD2SI : OpndItins<
1404 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1407 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1408 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1409 string asm, OpndItins itins> {
1410 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1411 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1413 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1414 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1418 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1419 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1420 string asm, Domain d, OpndItins itins> {
1421 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1422 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1424 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1425 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1429 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1430 X86MemOperand x86memop, string asm> {
1431 let neverHasSideEffects = 1 in {
1432 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1433 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1435 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1436 (ins DstRC:$src1, x86memop:$src),
1437 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1438 } // neverHasSideEffects = 1
1441 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1442 "cvttss2si\t{$src, $dst|$dst, $src}",
1445 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1446 "cvttss2si\t{$src, $dst|$dst, $src}",
1448 XS, VEX, VEX_W, VEX_LIG;
1449 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1450 "cvttsd2si\t{$src, $dst|$dst, $src}",
1453 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1454 "cvttsd2si\t{$src, $dst|$dst, $src}",
1456 XD, VEX, VEX_W, VEX_LIG;
1458 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1459 // register, but the same isn't true when only using memory operands,
1460 // provide other assembly "l" and "q" forms to address this explicitly
1461 // where appropriate to do so.
1462 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">,
1463 XS, VEX_4V, VEX_LIG;
1464 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1465 XS, VEX_4V, VEX_W, VEX_LIG;
1466 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">,
1467 XD, VEX_4V, VEX_LIG;
1468 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1469 XD, VEX_4V, VEX_LIG;
1470 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1471 XD, VEX_4V, VEX_W, VEX_LIG;
1473 let Predicates = [HasAVX], AddedComplexity = 1 in {
1474 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1475 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1476 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1477 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1478 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1479 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1480 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1481 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1483 def : Pat<(f32 (sint_to_fp GR32:$src)),
1484 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1485 def : Pat<(f32 (sint_to_fp GR64:$src)),
1486 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1487 def : Pat<(f64 (sint_to_fp GR32:$src)),
1488 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1489 def : Pat<(f64 (sint_to_fp GR64:$src)),
1490 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1493 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1494 "cvttss2si\t{$src, $dst|$dst, $src}",
1495 SSE_CVT_SS2SI_32>, XS;
1496 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1497 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1498 SSE_CVT_SS2SI_64>, XS, REX_W;
1499 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1500 "cvttsd2si\t{$src, $dst|$dst, $src}",
1502 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1503 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1504 SSE_CVT_SD2SI>, XD, REX_W;
1505 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1506 "cvtsi2ss\t{$src, $dst|$dst, $src}",
1507 SSE_CVT_Scalar>, XS;
1508 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1509 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1510 SSE_CVT_Scalar>, XS, REX_W;
1511 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1512 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1513 SSE_CVT_Scalar>, XD;
1514 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1515 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1516 SSE_CVT_Scalar>, XD, REX_W;
1518 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1519 // and/or XMM operand(s).
1521 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1522 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
1523 string asm, OpndItins itins> {
1524 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1525 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1526 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>;
1527 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
1528 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1529 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], itins.rm>;
1532 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1533 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1534 PatFrag ld_frag, string asm, OpndItins itins,
1536 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1538 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1539 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1540 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1542 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1543 (ins DstRC:$src1, x86memop:$src2),
1545 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1546 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1547 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1551 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1552 f128mem, load, "cvtsd2si", SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1553 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1554 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si",
1555 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1557 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1558 f128mem, load, "cvtsd2si{l}", SSE_CVT_SD2SI>, XD;
1559 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1560 f128mem, load, "cvtsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1563 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1564 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss",
1565 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1566 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1567 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss",
1568 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1570 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1571 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd",
1572 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1573 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1574 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd",
1575 SSE_CVT_Scalar, 0>, XD,
1578 let Constraints = "$src1 = $dst" in {
1579 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1580 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1581 "cvtsi2ss", SSE_CVT_Scalar>, XS;
1582 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1583 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1584 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1585 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1586 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1587 "cvtsi2sd", SSE_CVT_Scalar>, XD;
1588 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1589 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1590 "cvtsi2sd", SSE_CVT_Scalar>, XD, REX_W;
1595 // Aliases for intrinsics
1596 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1597 f32mem, load, "cvttss2si",
1598 SSE_CVT_SS2SI_32>, XS, VEX;
1599 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1600 int_x86_sse_cvttss2si64, f32mem, load,
1601 "cvttss2si", SSE_CVT_SS2SI_64>,
1603 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1604 f128mem, load, "cvttsd2si", SSE_CVT_SD2SI>,
1606 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1607 int_x86_sse2_cvttsd2si64, f128mem, load,
1608 "cvttsd2si", SSE_CVT_SD2SI>,
1610 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1611 f32mem, load, "cvttss2si",
1612 SSE_CVT_SS2SI_32>, XS;
1613 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1614 int_x86_sse_cvttss2si64, f32mem, load,
1615 "cvttss2si{q}", SSE_CVT_SS2SI_64>,
1617 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1618 f128mem, load, "cvttsd2si", SSE_CVT_SD2SI>,
1620 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1621 int_x86_sse2_cvttsd2si64, f128mem, load,
1622 "cvttsd2si{q}", SSE_CVT_SD2SI>,
1625 let Pattern = []<dag> in {
1626 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
1627 "cvtss2si{l}\t{$src, $dst|$dst, $src}",
1628 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1629 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
1630 "cvtss2si\t{$src, $dst|$dst, $src}",
1631 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1632 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
1633 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1634 SSEPackedSingle, SSE_CVT_PS>, TB, VEX;
1635 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
1636 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1637 SSEPackedSingle, SSE_CVT_PS>, TB, VEX;
1640 let Pattern = []<dag> in {
1641 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
1642 "cvtss2si{l}\t{$src, $dst|$dst, $src}",
1643 SSE_CVT_SS2SI_32>, XS;
1644 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
1645 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1646 SSE_CVT_SS2SI_64>, XS, REX_W;
1647 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
1648 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1649 SSEPackedSingle, SSE_CVT_PS>,
1650 TB; /* PD SSE3 form is avaiable */
1653 let Predicates = [HasAVX] in {
1654 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1655 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1656 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1657 (VCVTSS2SIrm addr:$src)>;
1658 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1659 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1660 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1661 (VCVTSS2SI64rm addr:$src)>;
1664 let Predicates = [HasSSE1] in {
1665 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1666 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1667 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1668 (CVTSS2SIrm addr:$src)>;
1669 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1670 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1671 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1672 (CVTSS2SI64rm addr:$src)>;
1677 // Convert scalar double to scalar single
1678 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1679 (ins FR64:$src1, FR64:$src2),
1680 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1681 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG;
1683 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1684 (ins FR64:$src1, f64mem:$src2),
1685 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1686 [], IIC_SSE_CVT_Scalar_RM>,
1687 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1689 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1692 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1693 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1694 [(set FR32:$dst, (fround FR64:$src))],
1695 IIC_SSE_CVT_Scalar_RR>;
1696 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1697 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1698 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1699 IIC_SSE_CVT_Scalar_RM>,
1701 Requires<[HasSSE2, OptForSize]>;
1703 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1704 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss",
1707 let Constraints = "$src1 = $dst" in
1708 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1709 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss",
1710 SSE_CVT_Scalar>, XS;
1712 // Convert scalar single to scalar double
1713 // SSE2 instructions with XS prefix
1714 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1715 (ins FR32:$src1, FR32:$src2),
1716 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1717 [], IIC_SSE_CVT_Scalar_RR>,
1718 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1720 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1721 (ins FR32:$src1, f32mem:$src2),
1722 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1723 [], IIC_SSE_CVT_Scalar_RM>,
1724 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1726 let Predicates = [HasAVX] in {
1727 def : Pat<(f64 (fextend FR32:$src)),
1728 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
1729 def : Pat<(fextend (loadf32 addr:$src)),
1730 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1731 def : Pat<(extloadf32 addr:$src),
1732 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1735 def : Pat<(extloadf32 addr:$src),
1736 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (MOVSSrm addr:$src))>,
1737 Requires<[HasAVX, OptForSpeed]>;
1739 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1740 "cvtss2sd\t{$src, $dst|$dst, $src}",
1741 [(set FR64:$dst, (fextend FR32:$src))],
1742 IIC_SSE_CVT_Scalar_RR>, XS,
1743 Requires<[HasSSE2]>;
1744 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1745 "cvtss2sd\t{$src, $dst|$dst, $src}",
1746 [(set FR64:$dst, (extloadf32 addr:$src))],
1747 IIC_SSE_CVT_Scalar_RM>, XS,
1748 Requires<[HasSSE2, OptForSize]>;
1750 // extload f32 -> f64. This matches load+fextend because we have a hack in
1751 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1753 // Since these loads aren't folded into the fextend, we have to match it
1755 def : Pat<(fextend (loadf32 addr:$src)),
1756 (CVTSS2SDrm addr:$src)>, Requires<[HasSSE2]>;
1757 def : Pat<(extloadf32 addr:$src),
1758 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1760 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1761 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1762 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1763 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1765 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V,
1767 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1768 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1769 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1770 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1771 (load addr:$src2)))],
1772 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V,
1774 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1775 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1776 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1777 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1778 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1780 IIC_SSE_CVT_Scalar_RR>, XS,
1781 Requires<[HasSSE2]>;
1782 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1783 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1784 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1785 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1786 (load addr:$src2)))],
1787 IIC_SSE_CVT_Scalar_RM>, XS,
1788 Requires<[HasSSE2]>;
1791 // Convert doubleword to packed single/double fp
1792 // SSE2 instructions without OpSize prefix
1793 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1794 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1795 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))],
1797 TB, VEX, Requires<[HasAVX]>;
1798 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1799 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1800 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1801 (bitconvert (memopv2i64 addr:$src))))],
1803 TB, VEX, Requires<[HasAVX]>;
1804 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1805 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1806 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))],
1808 TB, Requires<[HasSSE2]>;
1809 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1810 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1811 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1812 (bitconvert (memopv2i64 addr:$src))))],
1814 TB, Requires<[HasSSE2]>;
1816 // SSE2 instructions with XS prefix
1817 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1818 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1819 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
1821 XS, VEX, Requires<[HasAVX]>;
1822 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1823 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1824 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1825 (bitconvert (memopv2i64 addr:$src))))],
1827 XS, VEX, Requires<[HasAVX]>;
1828 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1829 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1830 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
1832 XS, Requires<[HasSSE2]>;
1833 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1834 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1835 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1836 (bitconvert (memopv2i64 addr:$src))))],
1838 XS, Requires<[HasSSE2]>;
1841 // Convert packed single/double fp to doubleword
1842 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1843 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1844 IIC_SSE_CVT_PS_RR>, VEX;
1845 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1846 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1847 IIC_SSE_CVT_PS_RM>, VEX;
1848 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1849 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1850 IIC_SSE_CVT_PS_RR>, VEX;
1851 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1852 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1853 IIC_SSE_CVT_PS_RM>, VEX;
1854 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1855 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1857 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1858 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1861 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1862 "cvtps2dq\t{$src, $dst|$dst, $src}",
1863 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1866 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1868 "cvtps2dq\t{$src, $dst|$dst, $src}",
1869 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1870 (memop addr:$src)))],
1871 IIC_SSE_CVT_PS_RM>, VEX;
1872 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1873 "cvtps2dq\t{$src, $dst|$dst, $src}",
1874 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1876 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1877 "cvtps2dq\t{$src, $dst|$dst, $src}",
1878 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1879 (memop addr:$src)))],
1882 // SSE2 packed instructions with XD prefix
1883 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1884 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1885 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1887 XD, VEX, Requires<[HasAVX]>;
1888 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1889 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1890 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1891 (memop addr:$src)))],
1893 XD, VEX, Requires<[HasAVX]>;
1894 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1895 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1896 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1898 XD, Requires<[HasSSE2]>;
1899 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1900 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1901 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1902 (memop addr:$src)))],
1904 XD, Requires<[HasSSE2]>;
1907 // Convert with truncation packed single/double fp to doubleword
1908 // SSE2 packed instructions with XS prefix
1909 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1910 "cvttps2dq\t{$src, $dst|$dst, $src}",
1912 (int_x86_sse2_cvttps2dq VR128:$src))],
1913 IIC_SSE_CVT_PS_RR>, VEX;
1914 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1915 "cvttps2dq\t{$src, $dst|$dst, $src}",
1916 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1917 (memop addr:$src)))],
1918 IIC_SSE_CVT_PS_RM>, VEX;
1919 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1920 "cvttps2dq\t{$src, $dst|$dst, $src}",
1922 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
1923 IIC_SSE_CVT_PS_RR>, VEX;
1924 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1925 "cvttps2dq\t{$src, $dst|$dst, $src}",
1926 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
1927 (memopv8f32 addr:$src)))],
1928 IIC_SSE_CVT_PS_RM>, VEX;
1930 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1931 "cvttps2dq\t{$src, $dst|$dst, $src}",
1933 (int_x86_sse2_cvttps2dq VR128:$src))],
1935 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1936 "cvttps2dq\t{$src, $dst|$dst, $src}",
1938 (int_x86_sse2_cvttps2dq (memop addr:$src)))],
1941 let Predicates = [HasAVX] in {
1942 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1943 (Int_VCVTDQ2PSrr VR128:$src)>;
1944 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1945 (Int_VCVTDQ2PSrm addr:$src)>;
1947 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1948 (VCVTTPS2DQrr VR128:$src)>;
1949 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1950 (VCVTTPS2DQrm addr:$src)>;
1952 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1953 (VCVTDQ2PSYrr VR256:$src)>;
1954 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
1955 (VCVTDQ2PSYrm addr:$src)>;
1957 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1958 (VCVTTPS2DQYrr VR256:$src)>;
1959 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
1960 (VCVTTPS2DQYrm addr:$src)>;
1963 let Predicates = [HasSSE2] in {
1964 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1965 (Int_CVTDQ2PSrr VR128:$src)>;
1966 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1967 (Int_CVTDQ2PSrm addr:$src)>;
1969 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1970 (CVTTPS2DQrr VR128:$src)>;
1971 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1972 (CVTTPS2DQrm addr:$src)>;
1975 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1976 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1978 (int_x86_sse2_cvttpd2dq VR128:$src))],
1979 IIC_SSE_CVT_PD_RR>, VEX;
1980 let isCodeGenOnly = 1 in
1981 def VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1982 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1983 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1984 (memop addr:$src)))],
1985 IIC_SSE_CVT_PD_RM>, VEX;
1986 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1987 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1988 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
1990 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1991 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1992 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1993 (memop addr:$src)))],
1996 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1997 // register, but the same isn't true when using memory operands instead.
1998 // Provide other assembly rr and rm forms to address this explicitly.
1999 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2000 "cvttpd2dq\t{$src, $dst|$dst, $src}", [],
2001 IIC_SSE_CVT_PD_RR>, VEX;
2004 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2005 "cvttpd2dqx\t{$src, $dst|$dst, $src}", [],
2006 IIC_SSE_CVT_PD_RR>, VEX;
2007 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2008 "cvttpd2dqx\t{$src, $dst|$dst, $src}", [],
2009 IIC_SSE_CVT_PD_RM>, VEX;
2012 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2013 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}", [],
2014 IIC_SSE_CVT_PD_RR>, VEX;
2015 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2016 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}", [],
2017 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
2019 // Convert packed single to packed double
2020 let Predicates = [HasAVX] in {
2021 // SSE2 instructions without OpSize prefix
2022 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2023 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2024 IIC_SSE_CVT_PD_RR>, TB, VEX;
2025 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2026 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2027 IIC_SSE_CVT_PD_RM>, TB, VEX;
2028 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2029 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2030 IIC_SSE_CVT_PD_RR>, TB, VEX;
2031 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2032 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2033 IIC_SSE_CVT_PD_RM>, TB, VEX;
2035 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2036 "cvtps2pd\t{$src, $dst|$dst, $src}", [],
2037 IIC_SSE_CVT_PD_RR>, TB;
2038 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2039 "cvtps2pd\t{$src, $dst|$dst, $src}", [],
2040 IIC_SSE_CVT_PD_RM>, TB;
2042 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2043 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2044 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2046 TB, VEX, Requires<[HasAVX]>;
2047 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2048 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2049 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
2050 (load addr:$src)))],
2052 TB, VEX, Requires<[HasAVX]>;
2053 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2054 "cvtps2pd\t{$src, $dst|$dst, $src}",
2055 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2057 TB, Requires<[HasSSE2]>;
2058 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2059 "cvtps2pd\t{$src, $dst|$dst, $src}",
2060 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
2061 (load addr:$src)))],
2063 TB, Requires<[HasSSE2]>;
2065 // Convert packed double to packed single
2066 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2067 // register, but the same isn't true when using memory operands instead.
2068 // Provide other assembly rr and rm forms to address this explicitly.
2069 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2070 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2071 IIC_SSE_CVT_PD_RR>, VEX;
2072 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2073 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2074 IIC_SSE_CVT_PD_RR>, VEX;
2077 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2078 "cvtpd2psx\t{$src, $dst|$dst, $src}", [],
2079 IIC_SSE_CVT_PD_RR>, VEX;
2080 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2081 "cvtpd2psx\t{$src, $dst|$dst, $src}", [],
2082 IIC_SSE_CVT_PD_RM>, VEX;
2085 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2086 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}", [],
2087 IIC_SSE_CVT_PD_RR>, VEX;
2088 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2089 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}", [],
2090 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
2091 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2092 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2094 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2095 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2099 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2100 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2101 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2103 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
2105 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2106 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
2107 (memop addr:$src)))],
2109 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2110 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2111 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2113 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2114 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2115 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
2116 (memop addr:$src)))],
2119 // AVX 256-bit register conversion intrinsics
2120 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2121 // whenever possible to avoid declaring two versions of each one.
2122 let Predicates = [HasAVX] in {
2123 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2124 (VCVTDQ2PSYrr VR256:$src)>;
2125 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2126 (VCVTDQ2PSYrm addr:$src)>;
2128 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
2129 (VCVTPD2PSYrr VR256:$src)>;
2130 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
2131 (VCVTPD2PSYrm addr:$src)>;
2133 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
2134 (VCVTPS2DQYrr VR256:$src)>;
2135 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
2136 (VCVTPS2DQYrm addr:$src)>;
2138 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
2139 (VCVTPS2PDYrr VR128:$src)>;
2140 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
2141 (VCVTPS2PDYrm addr:$src)>;
2143 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
2144 (VCVTTPD2DQYrr VR256:$src)>;
2145 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
2146 (VCVTTPD2DQYrm addr:$src)>;
2148 // Match fround and fextend for 128/256-bit conversions
2149 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2150 (VCVTPD2PSYrr VR256:$src)>;
2151 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2152 (VCVTPD2PSYrm addr:$src)>;
2154 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2155 (VCVTPS2PDYrr VR128:$src)>;
2156 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
2157 (VCVTPS2PDYrm addr:$src)>;
2160 //===----------------------------------------------------------------------===//
2161 // SSE 1 & 2 - Compare Instructions
2162 //===----------------------------------------------------------------------===//
2164 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2165 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2166 Operand CC, SDNode OpNode, ValueType VT,
2167 PatFrag ld_frag, string asm, string asm_alt,
2169 def rr : SIi8<0xC2, MRMSrcReg,
2170 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2171 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2173 def rm : SIi8<0xC2, MRMSrcMem,
2174 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2175 [(set RC:$dst, (OpNode (VT RC:$src1),
2176 (ld_frag addr:$src2), imm:$cc))],
2179 // Accept explicit immediate argument form instead of comparison code.
2180 let neverHasSideEffects = 1 in {
2181 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2182 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2183 IIC_SSE_ALU_F32S_RR>;
2185 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2186 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2187 IIC_SSE_ALU_F32S_RM>;
2191 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2192 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2193 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2195 XS, VEX_4V, VEX_LIG;
2196 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2197 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2198 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2199 SSE_ALU_F32S>, // same latency as 32 bit compare
2200 XD, VEX_4V, VEX_LIG;
2202 let Constraints = "$src1 = $dst" in {
2203 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2204 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2205 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2207 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2208 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2209 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2210 SSE_ALU_F32S>, // same latency as 32 bit compare
2214 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2215 Intrinsic Int, string asm, OpndItins itins> {
2216 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2217 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2218 [(set VR128:$dst, (Int VR128:$src1,
2219 VR128:$src, imm:$cc))],
2221 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2222 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2223 [(set VR128:$dst, (Int VR128:$src1,
2224 (load addr:$src), imm:$cc))],
2228 // Aliases to match intrinsics which expect XMM operand(s).
2229 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2230 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2233 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2234 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2235 SSE_ALU_F32S>, // same latency as f32
2237 let Constraints = "$src1 = $dst" in {
2238 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2239 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2241 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2242 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2243 SSE_ALU_F32S>, // same latency as f32
2248 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2249 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2250 ValueType vt, X86MemOperand x86memop,
2251 PatFrag ld_frag, string OpcodeStr, Domain d> {
2252 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2253 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2254 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2255 IIC_SSE_COMIS_RR, d>;
2256 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2257 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2258 [(set EFLAGS, (OpNode (vt RC:$src1),
2259 (ld_frag addr:$src2)))],
2260 IIC_SSE_COMIS_RM, d>;
2263 let Defs = [EFLAGS] in {
2264 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2265 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2266 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2267 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2269 let Pattern = []<dag> in {
2270 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2271 "comiss", SSEPackedSingle>, TB, VEX,
2273 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2274 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2278 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2279 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2280 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2281 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2283 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2284 load, "comiss", SSEPackedSingle>, TB, VEX;
2285 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2286 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2287 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2288 "ucomiss", SSEPackedSingle>, TB;
2289 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2290 "ucomisd", SSEPackedDouble>, TB, OpSize;
2292 let Pattern = []<dag> in {
2293 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2294 "comiss", SSEPackedSingle>, TB;
2295 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2296 "comisd", SSEPackedDouble>, TB, OpSize;
2299 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2300 load, "ucomiss", SSEPackedSingle>, TB;
2301 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2302 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2304 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2305 "comiss", SSEPackedSingle>, TB;
2306 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2307 "comisd", SSEPackedDouble>, TB, OpSize;
2308 } // Defs = [EFLAGS]
2310 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2311 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2312 Operand CC, Intrinsic Int, string asm,
2313 string asm_alt, Domain d> {
2314 def rri : PIi8<0xC2, MRMSrcReg,
2315 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2316 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2317 IIC_SSE_CMPP_RR, d>;
2318 def rmi : PIi8<0xC2, MRMSrcMem,
2319 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2320 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2321 IIC_SSE_CMPP_RM, d>;
2323 // Accept explicit immediate argument form instead of comparison code.
2324 let neverHasSideEffects = 1 in {
2325 def rri_alt : PIi8<0xC2, MRMSrcReg,
2326 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2327 asm_alt, [], IIC_SSE_CMPP_RR, d>;
2328 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2329 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2330 asm_alt, [], IIC_SSE_CMPP_RM, d>;
2334 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2335 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2336 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2337 SSEPackedSingle>, TB, VEX_4V;
2338 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2339 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2340 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2341 SSEPackedDouble>, TB, OpSize, VEX_4V;
2342 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2343 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2344 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2345 SSEPackedSingle>, TB, VEX_4V;
2346 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2347 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2348 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2349 SSEPackedDouble>, TB, OpSize, VEX_4V;
2350 let Constraints = "$src1 = $dst" in {
2351 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2352 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2353 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2354 SSEPackedSingle>, TB;
2355 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2356 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2357 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2358 SSEPackedDouble>, TB, OpSize;
2361 let Predicates = [HasAVX] in {
2362 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2363 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2364 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2365 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2366 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2367 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2368 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2369 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2371 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2372 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2373 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2374 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2375 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2376 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2377 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2378 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2381 let Predicates = [HasSSE1] in {
2382 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2383 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2384 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2385 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2388 let Predicates = [HasSSE2] in {
2389 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2390 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2391 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2392 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2395 //===----------------------------------------------------------------------===//
2396 // SSE 1 & 2 - Shuffle Instructions
2397 //===----------------------------------------------------------------------===//
2399 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2400 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2401 ValueType vt, string asm, PatFrag mem_frag,
2402 Domain d, bit IsConvertibleToThreeAddress = 0> {
2403 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2404 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2405 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2406 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2407 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2408 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2409 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2410 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2411 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2414 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2415 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2416 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2417 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2418 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2419 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2420 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2421 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2422 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2423 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2424 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2425 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2427 let Constraints = "$src1 = $dst" in {
2428 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2429 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2430 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2432 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2433 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2434 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2438 let Predicates = [HasAVX] in {
2439 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2440 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2441 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2442 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2443 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2445 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2446 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2447 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2448 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2449 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2452 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2453 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2454 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2455 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2456 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2458 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2459 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2460 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2461 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2462 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2465 let Predicates = [HasSSE1] in {
2466 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2467 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2468 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2469 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2470 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2473 let Predicates = [HasSSE2] in {
2474 // Generic SHUFPD patterns
2475 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2476 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2477 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2478 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2479 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2482 //===----------------------------------------------------------------------===//
2483 // SSE 1 & 2 - Unpack Instructions
2484 //===----------------------------------------------------------------------===//
2486 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2487 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2488 PatFrag mem_frag, RegisterClass RC,
2489 X86MemOperand x86memop, string asm,
2491 def rr : PI<opc, MRMSrcReg,
2492 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2494 (vt (OpNode RC:$src1, RC:$src2)))],
2496 def rm : PI<opc, MRMSrcMem,
2497 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2499 (vt (OpNode RC:$src1,
2500 (mem_frag addr:$src2))))],
2504 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2505 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2506 SSEPackedSingle>, TB, VEX_4V;
2507 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2508 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2509 SSEPackedDouble>, TB, OpSize, VEX_4V;
2510 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2511 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2512 SSEPackedSingle>, TB, VEX_4V;
2513 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2514 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2515 SSEPackedDouble>, TB, OpSize, VEX_4V;
2517 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2518 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2519 SSEPackedSingle>, TB, VEX_4V;
2520 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2521 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2522 SSEPackedDouble>, TB, OpSize, VEX_4V;
2523 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2524 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2525 SSEPackedSingle>, TB, VEX_4V;
2526 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2527 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2528 SSEPackedDouble>, TB, OpSize, VEX_4V;
2530 let Constraints = "$src1 = $dst" in {
2531 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2532 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2533 SSEPackedSingle>, TB;
2534 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2535 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2536 SSEPackedDouble>, TB, OpSize;
2537 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2538 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2539 SSEPackedSingle>, TB;
2540 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2541 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2542 SSEPackedDouble>, TB, OpSize;
2543 } // Constraints = "$src1 = $dst"
2545 let Predicates = [HasAVX], AddedComplexity = 1 in {
2546 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2547 // problem is during lowering, where it's not possible to recognize the load
2548 // fold cause it has two uses through a bitcast. One use disappears at isel
2549 // time and the fold opportunity reappears.
2550 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2551 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2554 let Predicates = [HasSSE2] in {
2555 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2556 // problem is during lowering, where it's not possible to recognize the load
2557 // fold cause it has two uses through a bitcast. One use disappears at isel
2558 // time and the fold opportunity reappears.
2559 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2560 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2563 //===----------------------------------------------------------------------===//
2564 // SSE 1 & 2 - Extract Floating-Point Sign mask
2565 //===----------------------------------------------------------------------===//
2567 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2568 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2570 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2571 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2572 [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>;
2573 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2574 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2575 IIC_SSE_MOVMSK, d>, REX_W;
2578 let Predicates = [HasAVX] in {
2579 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2580 "movmskps", SSEPackedSingle>, TB, VEX;
2581 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2582 "movmskpd", SSEPackedDouble>, TB,
2584 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2585 "movmskps", SSEPackedSingle>, TB, VEX;
2586 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2587 "movmskpd", SSEPackedDouble>, TB,
2590 def : Pat<(i32 (X86fgetsign FR32:$src)),
2591 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2593 def : Pat<(i64 (X86fgetsign FR32:$src)),
2594 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2596 def : Pat<(i32 (X86fgetsign FR64:$src)),
2597 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2599 def : Pat<(i64 (X86fgetsign FR64:$src)),
2600 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2604 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2605 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2606 SSEPackedSingle>, TB, VEX;
2607 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2608 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2609 SSEPackedDouble>, TB,
2611 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2612 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2613 SSEPackedSingle>, TB, VEX;
2614 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2615 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2616 SSEPackedDouble>, TB,
2620 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2621 SSEPackedSingle>, TB;
2622 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2623 SSEPackedDouble>, TB, OpSize;
2625 def : Pat<(i32 (X86fgetsign FR32:$src)),
2626 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2627 sub_ss))>, Requires<[HasSSE1]>;
2628 def : Pat<(i64 (X86fgetsign FR32:$src)),
2629 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2630 sub_ss))>, Requires<[HasSSE1]>;
2631 def : Pat<(i32 (X86fgetsign FR64:$src)),
2632 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2633 sub_sd))>, Requires<[HasSSE2]>;
2634 def : Pat<(i64 (X86fgetsign FR64:$src)),
2635 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2636 sub_sd))>, Requires<[HasSSE2]>;
2638 //===---------------------------------------------------------------------===//
2639 // SSE2 - Packed Integer Logical Instructions
2640 //===---------------------------------------------------------------------===//
2642 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2644 /// PDI_binop_rm - Simple SSE2 binary operator.
2645 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2646 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2647 X86MemOperand x86memop,
2649 bit IsCommutable = 0,
2651 let isCommutable = IsCommutable in
2652 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2653 (ins RC:$src1, RC:$src2),
2655 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2656 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2657 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>;
2658 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2659 (ins RC:$src1, x86memop:$src2),
2661 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2662 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2663 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2664 (bitconvert (memop_frag addr:$src2)))))],
2667 } // ExeDomain = SSEPackedInt
2669 // These are ordered here for pattern ordering requirements with the fp versions
2671 let Predicates = [HasAVX] in {
2672 defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
2673 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2674 defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
2675 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2676 defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
2677 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2678 defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
2679 i128mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2682 let Constraints = "$src1 = $dst" in {
2683 defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
2684 i128mem, SSE_BIT_ITINS_P, 1>;
2685 defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
2686 i128mem, SSE_BIT_ITINS_P, 1>;
2687 defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
2688 i128mem, SSE_BIT_ITINS_P, 1>;
2689 defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
2690 i128mem, SSE_BIT_ITINS_P, 0>;
2691 } // Constraints = "$src1 = $dst"
2693 let Predicates = [HasAVX2] in {
2694 defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
2695 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2696 defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
2697 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2698 defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
2699 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2700 defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
2701 i256mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2704 //===----------------------------------------------------------------------===//
2705 // SSE 1 & 2 - Logical Instructions
2706 //===----------------------------------------------------------------------===//
2708 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2710 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2711 SDNode OpNode, OpndItins itins> {
2712 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2713 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2716 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2717 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2720 let Constraints = "$src1 = $dst" in {
2721 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2722 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2725 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2726 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2731 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2732 let mayLoad = 0 in {
2733 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2735 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2737 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2741 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2742 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef,
2745 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2747 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2749 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2750 // are all promoted to v2i64, and the patterns are covered by the int
2751 // version. This is needed in SSE only, because v2i64 isn't supported on
2752 // SSE1, but only on SSE2.
2753 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2754 !strconcat(OpcodeStr, "ps"), f128mem, [],
2755 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2756 (memopv2i64 addr:$src2)))], 0, 1>, TB, VEX_4V;
2758 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2759 !strconcat(OpcodeStr, "pd"), f128mem,
2760 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2761 (bc_v2i64 (v2f64 VR128:$src2))))],
2762 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2763 (memopv2i64 addr:$src2)))], 0>,
2765 let Constraints = "$src1 = $dst" in {
2766 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2767 !strconcat(OpcodeStr, "ps"), f128mem,
2768 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2769 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2770 (memopv2i64 addr:$src2)))]>, TB;
2772 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2773 !strconcat(OpcodeStr, "pd"), f128mem,
2774 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2775 (bc_v2i64 (v2f64 VR128:$src2))))],
2776 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2777 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2781 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2783 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2785 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2786 !strconcat(OpcodeStr, "ps"), f256mem,
2787 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2788 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2789 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2791 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2792 !strconcat(OpcodeStr, "pd"), f256mem,
2793 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2794 (bc_v4i64 (v4f64 VR256:$src2))))],
2795 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2796 (memopv4i64 addr:$src2)))], 0>,
2800 // AVX 256-bit packed logical ops forms
2801 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2802 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2803 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2804 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2806 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2807 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2808 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2809 let isCommutable = 0 in
2810 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2812 //===----------------------------------------------------------------------===//
2813 // SSE 1 & 2 - Arithmetic Instructions
2814 //===----------------------------------------------------------------------===//
2816 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2819 /// In addition, we also have a special variant of the scalar form here to
2820 /// represent the associated intrinsic operation. This form is unlike the
2821 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2822 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2824 /// These three forms can each be reg+reg or reg+mem.
2827 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2829 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2832 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2833 OpNode, FR32, f32mem,
2834 itins.s, Is2Addr>, XS;
2835 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2836 OpNode, FR64, f64mem,
2837 itins.d, Is2Addr>, XD;
2840 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2843 let mayLoad = 0 in {
2844 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2845 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins.s, Is2Addr>,
2847 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2848 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins.d, Is2Addr>,
2853 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2856 let mayLoad = 0 in {
2857 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2858 v8f32, f256mem, memopv8f32, SSEPackedSingle, itins.s, 0>,
2860 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2861 v4f64, f256mem, memopv4f64, SSEPackedDouble, itins.d, 0>,
2866 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2869 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2870 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2871 itins.s, Is2Addr>, XS;
2872 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2873 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2874 itins.d, Is2Addr>, XD;
2877 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2880 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2881 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2882 SSEPackedSingle, itins.s, Is2Addr>,
2885 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2886 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2887 SSEPackedDouble, itins.d, Is2Addr>,
2891 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr,
2893 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2894 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2895 SSEPackedSingle, itins.s, 0>, TB;
2897 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2898 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2899 SSEPackedDouble, itins.d, 0>, TB, OpSize;
2902 // Binary Arithmetic instructions
2903 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S, 0>,
2904 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S, 0>,
2906 defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P, 0>,
2907 basic_sse12_fp_binop_p_y<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2909 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S, 0>,
2910 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S, 0>,
2912 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P, 0>,
2913 basic_sse12_fp_binop_p_y<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2916 let isCommutable = 0 in {
2917 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S, 0>,
2918 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S, 0>,
2920 defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P, 0>,
2921 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub, SSE_ALU_ITINS_P>, VEX_4V;
2922 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S, 0>,
2923 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S, 0>,
2925 defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_ALU_ITINS_P, 0>,
2926 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2928 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S, 0>,
2929 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S, 0>,
2931 defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P, 0>,
2932 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P, 0>,
2933 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2934 basic_sse12_fp_binop_p_y_int<0x5F, "max", SSE_ALU_ITINS_P>,
2936 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S, 0>,
2937 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S, 0>,
2939 defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P, 0>,
2940 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P, 0>,
2941 basic_sse12_fp_binop_p_y_int<0x5D, "min", SSE_ALU_ITINS_P>,
2942 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2946 let Constraints = "$src1 = $dst" in {
2947 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
2948 basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2949 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
2950 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
2951 basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2952 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
2954 let isCommutable = 0 in {
2955 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
2956 basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
2957 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
2958 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
2959 basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2960 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
2961 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
2962 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2963 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>,
2964 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P>;
2965 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
2966 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2967 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>,
2968 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P>;
2973 /// In addition, we also have a special variant of the scalar form here to
2974 /// represent the associated intrinsic operation. This form is unlike the
2975 /// plain scalar form, in that it takes an entire vector (instead of a
2976 /// scalar) and leaves the top elements undefined.
2978 /// And, we have a special variant form for a full-vector intrinsic form.
2980 def SSE_SQRTP : OpndItins<
2981 IIC_SSE_SQRTP_RR, IIC_SSE_SQRTP_RM
2984 def SSE_SQRTS : OpndItins<
2985 IIC_SSE_SQRTS_RR, IIC_SSE_SQRTS_RM
2988 def SSE_RCPP : OpndItins<
2989 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
2992 def SSE_RCPS : OpndItins<
2993 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
2996 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2997 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2998 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
2999 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3000 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3001 [(set FR32:$dst, (OpNode FR32:$src))]>;
3002 // For scalar unary operations, fold a load into the operation
3003 // only in OptForSize mode. It eliminates an instruction, but it also
3004 // eliminates a whole-register clobber (the load), so it introduces a
3005 // partial register update condition.
3006 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3007 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3008 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3009 Requires<[HasSSE1, OptForSize]>;
3010 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3011 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3012 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>;
3013 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3014 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3015 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>;
3018 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
3019 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3020 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
3021 !strconcat(OpcodeStr,
3022 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3024 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
3025 !strconcat(OpcodeStr,
3026 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3027 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3028 (ins VR128:$src1, ssmem:$src2),
3029 !strconcat(OpcodeStr,
3030 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3033 /// sse1_fp_unop_p - SSE1 unops in packed form.
3034 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3036 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3037 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3038 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>;
3039 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3040 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3041 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>;
3044 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
3045 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3047 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3048 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3049 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3051 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3052 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3053 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))],
3057 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3058 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3059 Intrinsic V4F32Int, OpndItins itins> {
3060 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3061 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3062 [(set VR128:$dst, (V4F32Int VR128:$src))],
3064 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3065 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3066 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3070 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
3071 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3072 Intrinsic V4F32Int, OpndItins itins> {
3073 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3074 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3075 [(set VR256:$dst, (V4F32Int VR256:$src))],
3077 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3078 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3079 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))],
3083 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3084 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3085 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3086 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3087 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3088 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>;
3089 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3090 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3091 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3092 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3093 Requires<[HasSSE2, OptForSize]>;
3094 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3095 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3096 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>;
3097 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3098 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3099 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>;
3102 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
3103 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3104 let neverHasSideEffects = 1 in {
3105 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
3106 !strconcat(OpcodeStr,
3107 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3109 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
3110 !strconcat(OpcodeStr,
3111 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3113 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3114 (ins VR128:$src1, sdmem:$src2),
3115 !strconcat(OpcodeStr,
3116 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3119 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3120 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3121 SDNode OpNode, OpndItins itins> {
3122 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3123 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3124 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>;
3125 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3126 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3127 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>;
3130 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
3131 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3133 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3134 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3135 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3137 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3138 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3139 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))],
3143 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
3144 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3145 Intrinsic V2F64Int, OpndItins itins> {
3146 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3147 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3148 [(set VR128:$dst, (V2F64Int VR128:$src))],
3150 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3151 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3152 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))],
3156 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
3157 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3158 Intrinsic V2F64Int, OpndItins itins> {
3159 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3160 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3161 [(set VR256:$dst, (V2F64Int VR256:$src))],
3163 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3164 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3165 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))],
3169 let Predicates = [HasAVX] in {
3171 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
3172 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
3174 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3175 sse2_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3176 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3177 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3178 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps,
3180 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd,
3182 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256,
3184 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256,
3188 // Reciprocal approximations. Note that these typically require refinement
3189 // in order to obtain suitable precision.
3190 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
3191 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3192 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3193 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256,
3195 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps,
3198 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
3199 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp, SSE_RCPP>,
3200 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp, SSE_RCPP>,
3201 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256,
3203 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps,
3207 let AddedComplexity = 1 in {
3208 def : Pat<(f32 (fsqrt FR32:$src)),
3209 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3210 def : Pat<(f32 (fsqrt (load addr:$src))),
3211 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3212 Requires<[HasAVX, OptForSize]>;
3213 def : Pat<(f64 (fsqrt FR64:$src)),
3214 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3215 def : Pat<(f64 (fsqrt (load addr:$src))),
3216 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3217 Requires<[HasAVX, OptForSize]>;
3219 def : Pat<(f32 (X86frsqrt FR32:$src)),
3220 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3221 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3222 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3223 Requires<[HasAVX, OptForSize]>;
3225 def : Pat<(f32 (X86frcp FR32:$src)),
3226 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3227 def : Pat<(f32 (X86frcp (load addr:$src))),
3228 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3229 Requires<[HasAVX, OptForSize]>;
3232 let Predicates = [HasAVX], AddedComplexity = 1 in {
3233 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3234 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3235 (VSQRTSSr (f32 (IMPLICIT_DEF)),
3236 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3238 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3239 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3241 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3242 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
3243 (VSQRTSDr (f64 (IMPLICIT_DEF)),
3244 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
3246 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3247 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3249 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3250 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3251 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3252 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3254 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3255 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3257 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3258 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3259 (VRCPSSr (f32 (IMPLICIT_DEF)),
3260 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3262 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3263 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3267 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3269 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3270 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps, SSE_SQRTS>,
3271 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3273 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3274 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd, SSE_SQRTS>;
3276 // Reciprocal approximations. Note that these typically require refinement
3277 // in order to obtain suitable precision.
3278 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss,
3280 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTS>,
3281 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3283 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss,
3285 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPS>,
3286 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps, SSE_RCPS>;
3288 // There is no f64 version of the reciprocal approximation instructions.
3290 //===----------------------------------------------------------------------===//
3291 // SSE 1 & 2 - Non-temporal stores
3292 //===----------------------------------------------------------------------===//
3294 let AddedComplexity = 400 in { // Prefer non-temporal versions
3295 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3296 (ins f128mem:$dst, VR128:$src),
3297 "movntps\t{$src, $dst|$dst, $src}",
3298 [(alignednontemporalstore (v4f32 VR128:$src),
3300 IIC_SSE_MOVNT>, VEX;
3301 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3302 (ins f128mem:$dst, VR128:$src),
3303 "movntpd\t{$src, $dst|$dst, $src}",
3304 [(alignednontemporalstore (v2f64 VR128:$src),
3306 IIC_SSE_MOVNT>, VEX;
3308 let ExeDomain = SSEPackedInt in
3309 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3310 (ins f128mem:$dst, VR128:$src),
3311 "movntdq\t{$src, $dst|$dst, $src}",
3312 [(alignednontemporalstore (v2i64 VR128:$src),
3314 IIC_SSE_MOVNT>, VEX;
3316 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3317 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3319 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3320 (ins f256mem:$dst, VR256:$src),
3321 "movntps\t{$src, $dst|$dst, $src}",
3322 [(alignednontemporalstore (v8f32 VR256:$src),
3324 IIC_SSE_MOVNT>, VEX;
3325 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3326 (ins f256mem:$dst, VR256:$src),
3327 "movntpd\t{$src, $dst|$dst, $src}",
3328 [(alignednontemporalstore (v4f64 VR256:$src),
3330 IIC_SSE_MOVNT>, VEX;
3331 let ExeDomain = SSEPackedInt in
3332 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3333 (ins f256mem:$dst, VR256:$src),
3334 "movntdq\t{$src, $dst|$dst, $src}",
3335 [(alignednontemporalstore (v4i64 VR256:$src),
3337 IIC_SSE_MOVNT>, VEX;
3340 let AddedComplexity = 400 in { // Prefer non-temporal versions
3341 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3342 "movntps\t{$src, $dst|$dst, $src}",
3343 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3345 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3346 "movntpd\t{$src, $dst|$dst, $src}",
3347 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3350 let ExeDomain = SSEPackedInt in
3351 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3352 "movntdq\t{$src, $dst|$dst, $src}",
3353 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3356 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3357 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3359 // There is no AVX form for instructions below this point
3360 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3361 "movnti{l}\t{$src, $dst|$dst, $src}",
3362 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3364 TB, Requires<[HasSSE2]>;
3365 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3366 "movnti{q}\t{$src, $dst|$dst, $src}",
3367 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3369 TB, Requires<[HasSSE2]>;
3372 //===----------------------------------------------------------------------===//
3373 // SSE 1 & 2 - Prefetch and memory fence
3374 //===----------------------------------------------------------------------===//
3376 // Prefetch intrinsic.
3377 let Predicates = [HasSSE1] in {
3378 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3379 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3380 IIC_SSE_PREFETCH>, TB;
3381 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3382 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3383 IIC_SSE_PREFETCH>, TB;
3384 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3385 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3386 IIC_SSE_PREFETCH>, TB;
3387 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3388 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3389 IIC_SSE_PREFETCH>, TB;
3393 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3394 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3395 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3397 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3398 // was introduced with SSE2, it's backward compatible.
3399 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
3401 // Load, store, and memory fence
3402 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3403 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3404 TB, Requires<[HasSSE1]>;
3405 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3406 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3407 TB, Requires<[HasSSE2]>;
3408 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3409 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3410 TB, Requires<[HasSSE2]>;
3412 def : Pat<(X86SFence), (SFENCE)>;
3413 def : Pat<(X86LFence), (LFENCE)>;
3414 def : Pat<(X86MFence), (MFENCE)>;
3416 //===----------------------------------------------------------------------===//
3417 // SSE 1 & 2 - Load/Store XCSR register
3418 //===----------------------------------------------------------------------===//
3420 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3421 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3422 IIC_SSE_LDMXCSR>, VEX;
3423 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3424 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3425 IIC_SSE_STMXCSR>, VEX;
3427 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3428 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3430 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3431 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3434 //===---------------------------------------------------------------------===//
3435 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3436 //===---------------------------------------------------------------------===//
3438 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3440 let neverHasSideEffects = 1 in {
3441 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3442 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3444 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3445 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3448 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3449 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3451 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3452 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3456 let isCodeGenOnly = 1 in {
3457 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3458 "movdqa\t{$src, $dst|$dst, $src}", [],
3461 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3462 "movdqa\t{$src, $dst|$dst, $src}", [],
3465 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3466 "movdqu\t{$src, $dst|$dst, $src}", [],
3469 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3470 "movdqu\t{$src, $dst|$dst, $src}", [],
3475 let canFoldAsLoad = 1, mayLoad = 1 in {
3476 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3477 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3479 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3480 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3482 let Predicates = [HasAVX] in {
3483 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3484 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3486 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3487 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3492 let mayStore = 1 in {
3493 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3494 (ins i128mem:$dst, VR128:$src),
3495 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3497 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3498 (ins i256mem:$dst, VR256:$src),
3499 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3501 let Predicates = [HasAVX] in {
3502 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3503 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3505 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3506 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3511 let neverHasSideEffects = 1 in
3512 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3513 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3515 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3516 "movdqu\t{$src, $dst|$dst, $src}",
3517 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[HasSSE2]>;
3520 let isCodeGenOnly = 1 in {
3521 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3522 "movdqa\t{$src, $dst|$dst, $src}", [],
3525 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3526 "movdqu\t{$src, $dst|$dst, $src}",
3527 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[HasSSE2]>;
3530 let canFoldAsLoad = 1, mayLoad = 1 in {
3531 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3532 "movdqa\t{$src, $dst|$dst, $src}",
3533 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3535 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3536 "movdqu\t{$src, $dst|$dst, $src}",
3537 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3539 XS, Requires<[HasSSE2]>;
3542 let mayStore = 1 in {
3543 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3544 "movdqa\t{$src, $dst|$dst, $src}",
3545 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3547 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3548 "movdqu\t{$src, $dst|$dst, $src}",
3549 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3551 XS, Requires<[HasSSE2]>;
3554 // Intrinsic forms of MOVDQU load and store
3555 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3556 "vmovdqu\t{$src, $dst|$dst, $src}",
3557 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3559 XS, VEX, Requires<[HasAVX]>;
3561 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3562 "movdqu\t{$src, $dst|$dst, $src}",
3563 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3565 XS, Requires<[HasSSE2]>;
3567 } // ExeDomain = SSEPackedInt
3569 let Predicates = [HasAVX] in {
3570 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3571 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3574 //===---------------------------------------------------------------------===//
3575 // SSE2 - Packed Integer Arithmetic Instructions
3576 //===---------------------------------------------------------------------===//
3578 def SSE_PMADD : OpndItins<
3579 IIC_SSE_PMADD, IIC_SSE_PMADD
3582 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3584 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3585 RegisterClass RC, PatFrag memop_frag,
3586 X86MemOperand x86memop,
3588 bit IsCommutable = 0,
3590 let isCommutable = IsCommutable in
3591 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3592 (ins RC:$src1, RC:$src2),
3594 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3595 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3596 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>;
3597 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3598 (ins RC:$src1, x86memop:$src2),
3600 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3601 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3602 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3606 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3607 string OpcodeStr, SDNode OpNode,
3608 SDNode OpNode2, RegisterClass RC,
3609 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3610 ShiftOpndItins itins,
3612 // src2 is always 128-bit
3613 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3614 (ins RC:$src1, VR128:$src2),
3616 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3617 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3618 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3620 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3621 (ins RC:$src1, i128mem:$src2),
3623 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3624 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3625 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3626 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>;
3627 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3628 (ins RC:$src1, i32i8imm:$src2),
3630 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3631 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3632 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))], itins.ri>;
3635 /// PDI_binop_rm - Simple SSE2 binary operator with different src and dst types
3636 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3637 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3638 PatFrag memop_frag, X86MemOperand x86memop,
3640 bit IsCommutable = 0, bit Is2Addr = 1> {
3641 let isCommutable = IsCommutable in
3642 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3643 (ins RC:$src1, RC:$src2),
3645 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3646 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3647 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>;
3648 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3649 (ins RC:$src1, x86memop:$src2),
3651 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3652 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3653 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3654 (bitconvert (memop_frag addr:$src2)))))]>;
3656 } // ExeDomain = SSEPackedInt
3658 // 128-bit Integer Arithmetic
3660 let Predicates = [HasAVX] in {
3661 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, VR128, memopv2i64,
3662 i128mem, SSE_INTALU_ITINS_P, 1, 0 /*3addr*/>,
3664 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
3665 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3666 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
3667 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3668 defm VPADDQ : PDI_binop_rm<0xD4, "vpaddq", add, v2i64, VR128, memopv2i64,
3669 i128mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3670 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
3671 i128mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3672 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
3673 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3674 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
3675 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3676 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
3677 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3678 defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
3679 i128mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3680 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3681 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3685 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
3686 VR128, memopv2i64, i128mem,
3687 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3688 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w,
3689 VR128, memopv2i64, i128mem,
3690 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3691 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b,
3692 VR128, memopv2i64, i128mem,
3693 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3694 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w,
3695 VR128, memopv2i64, i128mem,
3696 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3697 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b,
3698 VR128, memopv2i64, i128mem,
3699 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3700 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w,
3701 VR128, memopv2i64, i128mem,
3702 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3703 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b,
3704 VR128, memopv2i64, i128mem,
3705 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3706 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w,
3707 VR128, memopv2i64, i128mem,
3708 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3709 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
3710 VR128, memopv2i64, i128mem,
3711 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3712 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
3713 VR128, memopv2i64, i128mem,
3714 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3715 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
3716 VR128, memopv2i64, i128mem,
3717 SSE_PMADD, 1, 0>, VEX_4V;
3718 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
3719 VR128, memopv2i64, i128mem,
3720 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3721 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w,
3722 VR128, memopv2i64, i128mem,
3723 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3724 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b,
3725 VR128, memopv2i64, i128mem,
3726 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3727 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w,
3728 VR128, memopv2i64, i128mem,
3729 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3730 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b,
3731 VR128, memopv2i64, i128mem,
3732 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3733 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w,
3734 VR128, memopv2i64, i128mem,
3735 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3736 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
3737 VR128, memopv2i64, i128mem,
3738 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3741 let Predicates = [HasAVX2] in {
3742 defm VPADDBY : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
3743 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3744 defm VPADDWY : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
3745 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3746 defm VPADDDY : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
3747 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3748 defm VPADDQY : PDI_binop_rm<0xD4, "vpaddq", add, v4i64, VR256, memopv4i64,
3749 i256mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3750 defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
3751 i256mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3752 defm VPSUBBY : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
3753 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3754 defm VPSUBWY : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
3755 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3756 defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
3757 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3758 defm VPSUBQY : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
3759 i256mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3760 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3761 VR256, memopv4i64, i256mem,
3762 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3765 defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
3766 VR256, memopv4i64, i256mem,
3767 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3768 defm VPSUBSWY : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_avx2_psubs_w,
3769 VR256, memopv4i64, i256mem,
3770 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3771 defm VPSUBUSBY : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_avx2_psubus_b,
3772 VR256, memopv4i64, i256mem,
3773 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3774 defm VPSUBUSWY : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_avx2_psubus_w,
3775 VR256, memopv4i64, i256mem,
3776 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3777 defm VPADDSBY : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_avx2_padds_b,
3778 VR256, memopv4i64, i256mem,
3779 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3780 defm VPADDSWY : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_avx2_padds_w,
3781 VR256, memopv4i64, i256mem,
3782 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3783 defm VPADDUSBY : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_avx2_paddus_b,
3784 VR256, memopv4i64, i256mem,
3785 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3786 defm VPADDUSWY : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_avx2_paddus_w,
3787 VR256, memopv4i64, i256mem,
3788 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3789 defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
3790 VR256, memopv4i64, i256mem,
3791 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3792 defm VPMULHWY : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
3793 VR256, memopv4i64, i256mem,
3794 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3795 defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
3796 VR256, memopv4i64, i256mem,
3797 SSE_PMADD, 1, 0>, VEX_4V;
3798 defm VPAVGBY : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
3799 VR256, memopv4i64, i256mem,
3800 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3801 defm VPAVGWY : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_avx2_pavg_w,
3802 VR256, memopv4i64, i256mem,
3803 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3804 defm VPMINUBY : PDI_binop_rm_int<0xDA, "vpminub", int_x86_avx2_pminu_b,
3805 VR256, memopv4i64, i256mem,
3806 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3807 defm VPMINSWY : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_avx2_pmins_w,
3808 VR256, memopv4i64, i256mem,
3809 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3810 defm VPMAXUBY : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_avx2_pmaxu_b,
3811 VR256, memopv4i64, i256mem,
3812 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3813 defm VPMAXSWY : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_avx2_pmaxs_w,
3814 VR256, memopv4i64, i256mem,
3815 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3816 defm VPSADBWY : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
3817 VR256, memopv4i64, i256mem,
3818 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3821 let Constraints = "$src1 = $dst" in {
3822 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, VR128, memopv2i64,
3823 i128mem, SSE_INTALU_ITINS_P, 1>;
3824 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
3825 i128mem, SSE_INTALU_ITINS_P, 1>;
3826 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
3827 i128mem, SSE_INTALU_ITINS_P, 1>;
3828 defm PADDQ : PDI_binop_rm<0xD4, "paddq", add, v2i64, VR128, memopv2i64,
3829 i128mem, SSE_INTALUQ_ITINS_P, 1>;
3830 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
3831 i128mem, SSE_INTMUL_ITINS_P, 1>;
3832 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
3833 i128mem, SSE_INTALU_ITINS_P>;
3834 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
3835 i128mem, SSE_INTALU_ITINS_P>;
3836 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
3837 i128mem, SSE_INTALU_ITINS_P>;
3838 defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
3839 i128mem, SSE_INTALUQ_ITINS_P>;
3840 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3841 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3844 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
3845 VR128, memopv2i64, i128mem,
3846 SSE_INTALU_ITINS_P>;
3847 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3848 VR128, memopv2i64, i128mem,
3849 SSE_INTALU_ITINS_P>;
3850 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b,
3851 VR128, memopv2i64, i128mem,
3852 SSE_INTALU_ITINS_P>;
3853 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w,
3854 VR128, memopv2i64, i128mem,
3855 SSE_INTALU_ITINS_P>;
3856 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3857 VR128, memopv2i64, i128mem,
3858 SSE_INTALU_ITINS_P, 1>;
3859 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3860 VR128, memopv2i64, i128mem,
3861 SSE_INTALU_ITINS_P, 1>;
3862 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3863 VR128, memopv2i64, i128mem,
3864 SSE_INTALU_ITINS_P, 1>;
3865 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3866 VR128, memopv2i64, i128mem,
3867 SSE_INTALU_ITINS_P, 1>;
3868 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3869 VR128, memopv2i64, i128mem,
3870 SSE_INTMUL_ITINS_P, 1>;
3871 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3872 VR128, memopv2i64, i128mem,
3873 SSE_INTMUL_ITINS_P, 1>;
3874 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3875 VR128, memopv2i64, i128mem,
3877 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3878 VR128, memopv2i64, i128mem,
3879 SSE_INTALU_ITINS_P, 1>;
3880 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3881 VR128, memopv2i64, i128mem,
3882 SSE_INTALU_ITINS_P, 1>;
3883 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b,
3884 VR128, memopv2i64, i128mem,
3885 SSE_INTALU_ITINS_P, 1>;
3886 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w,
3887 VR128, memopv2i64, i128mem,
3888 SSE_INTALU_ITINS_P, 1>;
3889 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b,
3890 VR128, memopv2i64, i128mem,
3891 SSE_INTALU_ITINS_P, 1>;
3892 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w,
3893 VR128, memopv2i64, i128mem,
3894 SSE_INTALU_ITINS_P, 1>;
3895 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3896 VR128, memopv2i64, i128mem,
3897 SSE_INTALU_ITINS_P, 1>;
3899 } // Constraints = "$src1 = $dst"
3901 //===---------------------------------------------------------------------===//
3902 // SSE2 - Packed Integer Logical Instructions
3903 //===---------------------------------------------------------------------===//
3905 let Predicates = [HasAVX] in {
3906 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3907 VR128, v8i16, v8i16, bc_v8i16,
3908 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3909 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3910 VR128, v4i32, v4i32, bc_v4i32,
3911 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3912 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3913 VR128, v2i64, v2i64, bc_v2i64,
3914 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3916 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3917 VR128, v8i16, v8i16, bc_v8i16,
3918 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3919 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3920 VR128, v4i32, v4i32, bc_v4i32,
3921 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3922 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3923 VR128, v2i64, v2i64, bc_v2i64,
3924 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3926 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3927 VR128, v8i16, v8i16, bc_v8i16,
3928 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3929 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3930 VR128, v4i32, v4i32, bc_v4i32,
3931 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3933 let ExeDomain = SSEPackedInt in {
3934 // 128-bit logical shifts.
3935 def VPSLLDQri : PDIi8<0x73, MRM7r,
3936 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3937 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3939 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3941 def VPSRLDQri : PDIi8<0x73, MRM3r,
3942 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3943 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3945 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3947 // PSRADQri doesn't exist in SSE[1-3].
3949 } // Predicates = [HasAVX]
3951 let Predicates = [HasAVX2] in {
3952 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3953 VR256, v16i16, v8i16, bc_v8i16,
3954 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3955 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3956 VR256, v8i32, v4i32, bc_v4i32,
3957 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3958 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3959 VR256, v4i64, v2i64, bc_v2i64,
3960 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3962 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3963 VR256, v16i16, v8i16, bc_v8i16,
3964 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3965 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3966 VR256, v8i32, v4i32, bc_v4i32,
3967 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3968 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3969 VR256, v4i64, v2i64, bc_v2i64,
3970 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3972 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3973 VR256, v16i16, v8i16, bc_v8i16,
3974 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3975 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3976 VR256, v8i32, v4i32, bc_v4i32,
3977 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3979 let ExeDomain = SSEPackedInt in {
3980 // 256-bit logical shifts.
3981 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3982 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3983 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3985 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
3987 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3988 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3989 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3991 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
3993 // PSRADQYri doesn't exist in SSE[1-3].
3995 } // Predicates = [HasAVX2]
3997 let Constraints = "$src1 = $dst" in {
3998 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
3999 VR128, v8i16, v8i16, bc_v8i16,
4000 SSE_INTSHIFT_ITINS_P>;
4001 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4002 VR128, v4i32, v4i32, bc_v4i32,
4003 SSE_INTSHIFT_ITINS_P>;
4004 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4005 VR128, v2i64, v2i64, bc_v2i64,
4006 SSE_INTSHIFT_ITINS_P>;
4008 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4009 VR128, v8i16, v8i16, bc_v8i16,
4010 SSE_INTSHIFT_ITINS_P>;
4011 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4012 VR128, v4i32, v4i32, bc_v4i32,
4013 SSE_INTSHIFT_ITINS_P>;
4014 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4015 VR128, v2i64, v2i64, bc_v2i64,
4016 SSE_INTSHIFT_ITINS_P>;
4018 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4019 VR128, v8i16, v8i16, bc_v8i16,
4020 SSE_INTSHIFT_ITINS_P>;
4021 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4022 VR128, v4i32, v4i32, bc_v4i32,
4023 SSE_INTSHIFT_ITINS_P>;
4025 let ExeDomain = SSEPackedInt in {
4026 // 128-bit logical shifts.
4027 def PSLLDQri : PDIi8<0x73, MRM7r,
4028 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4029 "pslldq\t{$src2, $dst|$dst, $src2}",
4031 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>;
4032 def PSRLDQri : PDIi8<0x73, MRM3r,
4033 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4034 "psrldq\t{$src2, $dst|$dst, $src2}",
4036 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>;
4037 // PSRADQri doesn't exist in SSE[1-3].
4039 } // Constraints = "$src1 = $dst"
4041 let Predicates = [HasAVX] in {
4042 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4043 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4044 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4045 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4046 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4047 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4049 // Shift up / down and insert zero's.
4050 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4051 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4052 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4053 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4056 let Predicates = [HasAVX2] in {
4057 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4058 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4059 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4060 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4063 let Predicates = [HasSSE2] in {
4064 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4065 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4066 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4067 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4068 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4069 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4071 // Shift up / down and insert zero's.
4072 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4073 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4074 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4075 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4078 //===---------------------------------------------------------------------===//
4079 // SSE2 - Packed Integer Comparison Instructions
4080 //===---------------------------------------------------------------------===//
4082 let Predicates = [HasAVX] in {
4083 defm VPCMPEQB : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v16i8,
4084 VR128, memopv2i64, i128mem,
4085 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4086 defm VPCMPEQW : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v8i16,
4087 VR128, memopv2i64, i128mem,
4088 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4089 defm VPCMPEQD : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v4i32,
4090 VR128, memopv2i64, i128mem,
4091 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4092 defm VPCMPGTB : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v16i8,
4093 VR128, memopv2i64, i128mem,
4094 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4095 defm VPCMPGTW : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v8i16,
4096 VR128, memopv2i64, i128mem,
4097 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4098 defm VPCMPGTD : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v4i32,
4099 VR128, memopv2i64, i128mem,
4100 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4103 let Predicates = [HasAVX2] in {
4104 defm VPCMPEQBY : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v32i8,
4105 VR256, memopv4i64, i256mem,
4106 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4107 defm VPCMPEQWY : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v16i16,
4108 VR256, memopv4i64, i256mem,
4109 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4110 defm VPCMPEQDY : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v8i32,
4111 VR256, memopv4i64, i256mem,
4112 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4113 defm VPCMPGTBY : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v32i8,
4114 VR256, memopv4i64, i256mem,
4115 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4116 defm VPCMPGTWY : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v16i16,
4117 VR256, memopv4i64, i256mem,
4118 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4119 defm VPCMPGTDY : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v8i32,
4120 VR256, memopv4i64, i256mem,
4121 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4124 let Constraints = "$src1 = $dst" in {
4125 defm PCMPEQB : PDI_binop_rm<0x74, "pcmpeqb", X86pcmpeq, v16i8,
4126 VR128, memopv2i64, i128mem,
4127 SSE_INTALU_ITINS_P, 1>;
4128 defm PCMPEQW : PDI_binop_rm<0x75, "pcmpeqw", X86pcmpeq, v8i16,
4129 VR128, memopv2i64, i128mem,
4130 SSE_INTALU_ITINS_P, 1>;
4131 defm PCMPEQD : PDI_binop_rm<0x76, "pcmpeqd", X86pcmpeq, v4i32,
4132 VR128, memopv2i64, i128mem,
4133 SSE_INTALU_ITINS_P, 1>;
4134 defm PCMPGTB : PDI_binop_rm<0x64, "pcmpgtb", X86pcmpgt, v16i8,
4135 VR128, memopv2i64, i128mem,
4136 SSE_INTALU_ITINS_P>;
4137 defm PCMPGTW : PDI_binop_rm<0x65, "pcmpgtw", X86pcmpgt, v8i16,
4138 VR128, memopv2i64, i128mem,
4139 SSE_INTALU_ITINS_P>;
4140 defm PCMPGTD : PDI_binop_rm<0x66, "pcmpgtd", X86pcmpgt, v4i32,
4141 VR128, memopv2i64, i128mem,
4142 SSE_INTALU_ITINS_P>;
4143 } // Constraints = "$src1 = $dst"
4145 //===---------------------------------------------------------------------===//
4146 // SSE2 - Packed Integer Pack Instructions
4147 //===---------------------------------------------------------------------===//
4149 let Predicates = [HasAVX] in {
4150 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
4151 VR128, memopv2i64, i128mem,
4152 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4153 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
4154 VR128, memopv2i64, i128mem,
4155 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4156 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
4157 VR128, memopv2i64, i128mem,
4158 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4161 let Predicates = [HasAVX2] in {
4162 defm VPACKSSWBY : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_avx2_packsswb,
4163 VR256, memopv4i64, i256mem,
4164 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4165 defm VPACKSSDWY : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_avx2_packssdw,
4166 VR256, memopv4i64, i256mem,
4167 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4168 defm VPACKUSWBY : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_avx2_packuswb,
4169 VR256, memopv4i64, i256mem,
4170 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4173 let Constraints = "$src1 = $dst" in {
4174 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4175 VR128, memopv2i64, i128mem,
4176 SSE_INTALU_ITINS_P>;
4177 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4178 VR128, memopv2i64, i128mem,
4179 SSE_INTALU_ITINS_P>;
4180 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4181 VR128, memopv2i64, i128mem,
4182 SSE_INTALU_ITINS_P>;
4183 } // Constraints = "$src1 = $dst"
4185 //===---------------------------------------------------------------------===//
4186 // SSE2 - Packed Integer Shuffle Instructions
4187 //===---------------------------------------------------------------------===//
4189 let ExeDomain = SSEPackedInt in {
4190 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, SDNode OpNode> {
4191 def ri : Ii8<0x70, MRMSrcReg,
4192 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4193 !strconcat(OpcodeStr,
4194 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4195 [(set VR128:$dst, (vt (OpNode VR128:$src1, (i8 imm:$src2))))],
4197 def mi : Ii8<0x70, MRMSrcMem,
4198 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4199 !strconcat(OpcodeStr,
4200 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4202 (vt (OpNode (bitconvert (memopv2i64 addr:$src1)),
4207 multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, SDNode OpNode> {
4208 def Yri : Ii8<0x70, MRMSrcReg,
4209 (outs VR256:$dst), (ins VR256:$src1, i8imm:$src2),
4210 !strconcat(OpcodeStr,
4211 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4212 [(set VR256:$dst, (vt (OpNode VR256:$src1, (i8 imm:$src2))))]>;
4213 def Ymi : Ii8<0x70, MRMSrcMem,
4214 (outs VR256:$dst), (ins i256mem:$src1, i8imm:$src2),
4215 !strconcat(OpcodeStr,
4216 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4218 (vt (OpNode (bitconvert (memopv4i64 addr:$src1)),
4219 (i8 imm:$src2))))]>;
4221 } // ExeDomain = SSEPackedInt
4223 let Predicates = [HasAVX] in {
4224 let AddedComplexity = 5 in
4225 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, X86PShufd>, TB, OpSize, VEX;
4227 // SSE2 with ImmT == Imm8 and XS prefix.
4228 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, X86PShufhw>, XS, VEX;
4230 // SSE2 with ImmT == Imm8 and XD prefix.
4231 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, X86PShuflw>, XD, VEX;
4233 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4234 (VPSHUFDmi addr:$src1, imm:$imm)>;
4235 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4236 (VPSHUFDri VR128:$src1, imm:$imm)>;
4239 let Predicates = [HasAVX2] in {
4240 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, X86PShufd>, TB, OpSize, VEX;
4241 defm VPSHUFHW : sse2_pshuffle_y<"vpshufhw", v16i16, X86PShufhw>, XS, VEX;
4242 defm VPSHUFLW : sse2_pshuffle_y<"vpshuflw", v16i16, X86PShuflw>, XD, VEX;
4245 let Predicates = [HasSSE2] in {
4246 let AddedComplexity = 5 in
4247 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, X86PShufd>, TB, OpSize;
4249 // SSE2 with ImmT == Imm8 and XS prefix.
4250 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, X86PShufhw>, XS;
4252 // SSE2 with ImmT == Imm8 and XD prefix.
4253 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, X86PShuflw>, XD;
4255 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4256 (PSHUFDmi addr:$src1, imm:$imm)>;
4257 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4258 (PSHUFDri VR128:$src1, imm:$imm)>;
4261 //===---------------------------------------------------------------------===//
4262 // SSE2 - Packed Integer Unpack Instructions
4263 //===---------------------------------------------------------------------===//
4265 let ExeDomain = SSEPackedInt in {
4266 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4267 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4268 def rr : PDI<opc, MRMSrcReg,
4269 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4271 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4272 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4273 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4275 def rm : PDI<opc, MRMSrcMem,
4276 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4278 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4279 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4280 [(set VR128:$dst, (OpNode VR128:$src1,
4281 (bc_frag (memopv2i64
4286 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4287 SDNode OpNode, PatFrag bc_frag> {
4288 def Yrr : PDI<opc, MRMSrcReg,
4289 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4290 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4291 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
4292 def Yrm : PDI<opc, MRMSrcMem,
4293 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4294 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4295 [(set VR256:$dst, (OpNode VR256:$src1,
4296 (bc_frag (memopv4i64 addr:$src2))))]>;
4299 let Predicates = [HasAVX] in {
4300 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4301 bc_v16i8, 0>, VEX_4V;
4302 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4303 bc_v8i16, 0>, VEX_4V;
4304 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4305 bc_v4i32, 0>, VEX_4V;
4306 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4307 bc_v2i64, 0>, VEX_4V;
4309 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4310 bc_v16i8, 0>, VEX_4V;
4311 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4312 bc_v8i16, 0>, VEX_4V;
4313 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4314 bc_v4i32, 0>, VEX_4V;
4315 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4316 bc_v2i64, 0>, VEX_4V;
4319 let Predicates = [HasAVX2] in {
4320 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4322 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4324 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4326 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4329 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4331 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4333 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4335 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4339 let Constraints = "$src1 = $dst" in {
4340 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4342 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4344 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4346 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4349 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4351 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4353 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4355 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4358 } // ExeDomain = SSEPackedInt
4360 // Patterns for using AVX1 instructions with integer vectors
4361 // Here to give AVX2 priority
4362 let Predicates = [HasAVX] in {
4363 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4364 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
4365 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
4366 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
4367 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4368 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
4369 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
4370 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
4372 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
4373 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
4374 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
4375 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
4376 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
4377 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
4378 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
4379 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
4382 //===---------------------------------------------------------------------===//
4383 // SSE2 - Packed Integer Extract and Insert
4384 //===---------------------------------------------------------------------===//
4386 let ExeDomain = SSEPackedInt in {
4387 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4388 def rri : Ii8<0xC4, MRMSrcReg,
4389 (outs VR128:$dst), (ins VR128:$src1,
4390 GR32:$src2, i32i8imm:$src3),
4392 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4393 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4395 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>;
4396 def rmi : Ii8<0xC4, MRMSrcMem,
4397 (outs VR128:$dst), (ins VR128:$src1,
4398 i16mem:$src2, i32i8imm:$src3),
4400 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4401 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4403 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4404 imm:$src3))], IIC_SSE_PINSRW>;
4408 let Predicates = [HasAVX] in
4409 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4410 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4411 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4412 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4413 imm:$src2))]>, TB, OpSize, VEX;
4414 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4415 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4416 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4417 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4418 imm:$src2))], IIC_SSE_PEXTRW>;
4421 let Predicates = [HasAVX] in {
4422 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4423 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4424 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4425 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4426 []>, TB, OpSize, VEX_4V;
4429 let Constraints = "$src1 = $dst" in
4430 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
4432 } // ExeDomain = SSEPackedInt
4434 //===---------------------------------------------------------------------===//
4435 // SSE2 - Packed Mask Creation
4436 //===---------------------------------------------------------------------===//
4438 let ExeDomain = SSEPackedInt in {
4440 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4441 "pmovmskb\t{$src, $dst|$dst, $src}",
4442 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4443 IIC_SSE_MOVMSK>, VEX;
4444 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4445 "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;
4447 let Predicates = [HasAVX2] in {
4448 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4449 "pmovmskb\t{$src, $dst|$dst, $src}",
4450 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX;
4451 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4452 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4455 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4456 "pmovmskb\t{$src, $dst|$dst, $src}",
4457 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4460 } // ExeDomain = SSEPackedInt
4462 //===---------------------------------------------------------------------===//
4463 // SSE2 - Conditional Store
4464 //===---------------------------------------------------------------------===//
4466 let ExeDomain = SSEPackedInt in {
4469 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4470 (ins VR128:$src, VR128:$mask),
4471 "maskmovdqu\t{$mask, $src|$src, $mask}",
4472 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4473 IIC_SSE_MASKMOV>, VEX;
4475 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4476 (ins VR128:$src, VR128:$mask),
4477 "maskmovdqu\t{$mask, $src|$src, $mask}",
4478 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4479 IIC_SSE_MASKMOV>, VEX;
4482 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4483 "maskmovdqu\t{$mask, $src|$src, $mask}",
4484 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4487 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4488 "maskmovdqu\t{$mask, $src|$src, $mask}",
4489 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4492 } // ExeDomain = SSEPackedInt
4494 //===---------------------------------------------------------------------===//
4495 // SSE2 - Move Doubleword
4496 //===---------------------------------------------------------------------===//
4498 //===---------------------------------------------------------------------===//
4499 // Move Int Doubleword to Packed Double Int
4501 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4502 "movd\t{$src, $dst|$dst, $src}",
4504 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4506 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4507 "movd\t{$src, $dst|$dst, $src}",
4509 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4512 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4513 "mov{d|q}\t{$src, $dst|$dst, $src}",
4515 (v2i64 (scalar_to_vector GR64:$src)))],
4516 IIC_SSE_MOVDQ>, VEX;
4517 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4518 "mov{d|q}\t{$src, $dst|$dst, $src}",
4519 [(set FR64:$dst, (bitconvert GR64:$src))],
4520 IIC_SSE_MOVDQ>, VEX;
4522 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4523 "movd\t{$src, $dst|$dst, $src}",
4525 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>;
4526 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4527 "movd\t{$src, $dst|$dst, $src}",
4529 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4531 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4532 "mov{d|q}\t{$src, $dst|$dst, $src}",
4534 (v2i64 (scalar_to_vector GR64:$src)))],
4536 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4537 "mov{d|q}\t{$src, $dst|$dst, $src}",
4538 [(set FR64:$dst, (bitconvert GR64:$src))],
4541 //===---------------------------------------------------------------------===//
4542 // Move Int Doubleword to Single Scalar
4544 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4545 "movd\t{$src, $dst|$dst, $src}",
4546 [(set FR32:$dst, (bitconvert GR32:$src))],
4547 IIC_SSE_MOVDQ>, VEX;
4549 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4550 "movd\t{$src, $dst|$dst, $src}",
4551 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4554 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4555 "movd\t{$src, $dst|$dst, $src}",
4556 [(set FR32:$dst, (bitconvert GR32:$src))],
4559 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4560 "movd\t{$src, $dst|$dst, $src}",
4561 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4564 //===---------------------------------------------------------------------===//
4565 // Move Packed Doubleword Int to Packed Double Int
4567 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4568 "movd\t{$src, $dst|$dst, $src}",
4569 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4570 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX;
4571 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4572 (ins i32mem:$dst, VR128:$src),
4573 "movd\t{$src, $dst|$dst, $src}",
4574 [(store (i32 (vector_extract (v4i32 VR128:$src),
4575 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4577 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4578 "movd\t{$src, $dst|$dst, $src}",
4579 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4580 (iPTR 0)))], IIC_SSE_MOVD_ToGP>;
4581 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4582 "movd\t{$src, $dst|$dst, $src}",
4583 [(store (i32 (vector_extract (v4i32 VR128:$src),
4584 (iPTR 0))), addr:$dst)],
4587 //===---------------------------------------------------------------------===//
4588 // Move Packed Doubleword Int first element to Doubleword Int
4590 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4591 "mov{d|q}\t{$src, $dst|$dst, $src}",
4592 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4595 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4597 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4598 "mov{d|q}\t{$src, $dst|$dst, $src}",
4599 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4603 //===---------------------------------------------------------------------===//
4604 // Bitcast FR64 <-> GR64
4606 let Predicates = [HasAVX] in
4607 def VMOV64toSDrm : SSDI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4608 "vmovq\t{$src, $dst|$dst, $src}",
4609 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4611 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4612 "mov{d|q}\t{$src, $dst|$dst, $src}",
4613 [(set GR64:$dst, (bitconvert FR64:$src))],
4614 IIC_SSE_MOVDQ>, VEX;
4615 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4616 "movq\t{$src, $dst|$dst, $src}",
4617 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4618 IIC_SSE_MOVDQ>, VEX;
4620 def MOV64toSDrm : SSDI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4621 "movq\t{$src, $dst|$dst, $src}",
4622 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4624 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4625 "mov{d|q}\t{$src, $dst|$dst, $src}",
4626 [(set GR64:$dst, (bitconvert FR64:$src))],
4628 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4629 "movq\t{$src, $dst|$dst, $src}",
4630 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4633 //===---------------------------------------------------------------------===//
4634 // Move Scalar Single to Double Int
4636 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4637 "movd\t{$src, $dst|$dst, $src}",
4638 [(set GR32:$dst, (bitconvert FR32:$src))],
4639 IIC_SSE_MOVD_ToGP>, VEX;
4640 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4641 "movd\t{$src, $dst|$dst, $src}",
4642 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4643 IIC_SSE_MOVDQ>, VEX;
4644 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4645 "movd\t{$src, $dst|$dst, $src}",
4646 [(set GR32:$dst, (bitconvert FR32:$src))],
4648 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4649 "movd\t{$src, $dst|$dst, $src}",
4650 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4653 //===---------------------------------------------------------------------===//
4654 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4656 let AddedComplexity = 15 in {
4657 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4658 "movd\t{$src, $dst|$dst, $src}",
4659 [(set VR128:$dst, (v4i32 (X86vzmovl
4660 (v4i32 (scalar_to_vector GR32:$src)))))],
4661 IIC_SSE_MOVDQ>, VEX;
4662 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4663 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4664 [(set VR128:$dst, (v2i64 (X86vzmovl
4665 (v2i64 (scalar_to_vector GR64:$src)))))],
4669 let AddedComplexity = 15 in {
4670 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4671 "movd\t{$src, $dst|$dst, $src}",
4672 [(set VR128:$dst, (v4i32 (X86vzmovl
4673 (v4i32 (scalar_to_vector GR32:$src)))))],
4675 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4676 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4677 [(set VR128:$dst, (v2i64 (X86vzmovl
4678 (v2i64 (scalar_to_vector GR64:$src)))))],
4682 let AddedComplexity = 20 in {
4683 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4684 "movd\t{$src, $dst|$dst, $src}",
4686 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4687 (loadi32 addr:$src))))))],
4688 IIC_SSE_MOVDQ>, VEX;
4689 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4690 "movd\t{$src, $dst|$dst, $src}",
4692 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4693 (loadi32 addr:$src))))))],
4697 let Predicates = [HasAVX] in {
4698 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4699 let AddedComplexity = 20 in {
4700 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4701 (VMOVZDI2PDIrm addr:$src)>;
4702 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4703 (VMOVZDI2PDIrm addr:$src)>;
4705 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4706 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4707 (v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
4708 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4709 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4710 (v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
4711 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4714 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4715 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4716 (MOVZDI2PDIrm addr:$src)>;
4717 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4718 (MOVZDI2PDIrm addr:$src)>;
4721 // These are the correct encodings of the instructions so that we know how to
4722 // read correct assembly, even though we continue to emit the wrong ones for
4723 // compatibility with Darwin's buggy assembler.
4724 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4725 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4726 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4727 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4728 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4729 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4730 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4731 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4732 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4733 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4734 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4735 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4737 //===---------------------------------------------------------------------===//
4738 // SSE2 - Move Quadword
4739 //===---------------------------------------------------------------------===//
4741 //===---------------------------------------------------------------------===//
4742 // Move Quadword Int to Packed Quadword Int
4744 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4745 "vmovq\t{$src, $dst|$dst, $src}",
4747 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4748 VEX, Requires<[HasAVX]>;
4749 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4750 "movq\t{$src, $dst|$dst, $src}",
4752 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4754 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
4756 //===---------------------------------------------------------------------===//
4757 // Move Packed Quadword Int to Quadword Int
4759 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4760 "movq\t{$src, $dst|$dst, $src}",
4761 [(store (i64 (vector_extract (v2i64 VR128:$src),
4762 (iPTR 0))), addr:$dst)],
4763 IIC_SSE_MOVDQ>, VEX;
4764 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4765 "movq\t{$src, $dst|$dst, $src}",
4766 [(store (i64 (vector_extract (v2i64 VR128:$src),
4767 (iPTR 0))), addr:$dst)],
4770 //===---------------------------------------------------------------------===//
4771 // Store / copy lower 64-bits of a XMM register.
4773 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4774 "movq\t{$src, $dst|$dst, $src}",
4775 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4776 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4777 "movq\t{$src, $dst|$dst, $src}",
4778 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4781 let AddedComplexity = 20 in
4782 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4783 "vmovq\t{$src, $dst|$dst, $src}",
4785 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4786 (loadi64 addr:$src))))))],
4788 XS, VEX, Requires<[HasAVX]>;
4790 let AddedComplexity = 20 in
4791 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4792 "movq\t{$src, $dst|$dst, $src}",
4794 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4795 (loadi64 addr:$src))))))],
4797 XS, Requires<[HasSSE2]>;
4799 let Predicates = [HasAVX], AddedComplexity = 20 in {
4800 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4801 (VMOVZQI2PQIrm addr:$src)>;
4802 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4803 (VMOVZQI2PQIrm addr:$src)>;
4804 def : Pat<(v2i64 (X86vzload addr:$src)),
4805 (VMOVZQI2PQIrm addr:$src)>;
4808 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4809 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4810 (MOVZQI2PQIrm addr:$src)>;
4811 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4812 (MOVZQI2PQIrm addr:$src)>;
4813 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4816 let Predicates = [HasAVX] in {
4817 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4818 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4819 def : Pat<(v4i64 (X86vzload addr:$src)),
4820 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4823 //===---------------------------------------------------------------------===//
4824 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4825 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4827 let AddedComplexity = 15 in
4828 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4829 "vmovq\t{$src, $dst|$dst, $src}",
4830 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4832 XS, VEX, Requires<[HasAVX]>;
4833 let AddedComplexity = 15 in
4834 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4835 "movq\t{$src, $dst|$dst, $src}",
4836 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4838 XS, Requires<[HasSSE2]>;
4840 let AddedComplexity = 20 in
4841 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4842 "vmovq\t{$src, $dst|$dst, $src}",
4843 [(set VR128:$dst, (v2i64 (X86vzmovl
4844 (loadv2i64 addr:$src))))],
4846 XS, VEX, Requires<[HasAVX]>;
4847 let AddedComplexity = 20 in {
4848 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4849 "movq\t{$src, $dst|$dst, $src}",
4850 [(set VR128:$dst, (v2i64 (X86vzmovl
4851 (loadv2i64 addr:$src))))],
4853 XS, Requires<[HasSSE2]>;
4856 let AddedComplexity = 20 in {
4857 let Predicates = [HasAVX] in {
4858 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4859 (VMOVZPQILo2PQIrm addr:$src)>;
4860 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4861 (VMOVZPQILo2PQIrr VR128:$src)>;
4863 let Predicates = [HasSSE2] in {
4864 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4865 (MOVZPQILo2PQIrm addr:$src)>;
4866 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4867 (MOVZPQILo2PQIrr VR128:$src)>;
4871 // Instructions to match in the assembler
4872 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4873 "movq\t{$src, $dst|$dst, $src}", [],
4874 IIC_SSE_MOVDQ>, VEX, VEX_W;
4875 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4876 "movq\t{$src, $dst|$dst, $src}", [],
4877 IIC_SSE_MOVDQ>, VEX, VEX_W;
4878 // Recognize "movd" with GR64 destination, but encode as a "movq"
4879 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4880 "movd\t{$src, $dst|$dst, $src}", [],
4881 IIC_SSE_MOVDQ>, VEX, VEX_W;
4883 // Instructions for the disassembler
4884 // xr = XMM register
4887 let Predicates = [HasAVX] in
4888 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4889 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4890 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4891 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, XS;
4893 //===---------------------------------------------------------------------===//
4894 // SSE3 - Conversion Instructions
4895 //===---------------------------------------------------------------------===//
4897 // Convert Packed Double FP to Packed DW Integers
4898 let Predicates = [HasAVX] in {
4899 // The assembler can recognize rr 256-bit instructions by seeing a ymm
4900 // register, but the same isn't true when using memory operands instead.
4901 // Provide other assembly rr and rm forms to address this explicitly.
4902 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4903 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4904 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4905 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4908 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4909 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4910 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4911 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4914 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4915 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>, VEX;
4916 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
4917 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4920 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4921 "cvtpd2dq\t{$src, $dst|$dst, $src}", [],
4923 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4924 "cvtpd2dq\t{$src, $dst|$dst, $src}", [],
4927 let Predicates = [HasAVX] in {
4928 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
4929 (VCVTTPD2DQYrr VR256:$src)>;
4930 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
4931 (VCVTTPD2DQYrm addr:$src)>;
4932 } // Predicates = [HasAVX]
4934 // Convert Packed DW Integers to Packed Double FP
4935 let Predicates = [HasAVX] in {
4936 def VCVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4937 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4938 def VCVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4939 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4940 def VCVTDQ2PDYrm : SSDI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
4941 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4942 def VCVTDQ2PDYrr : SSDI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
4943 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4946 def CVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4947 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
4949 def CVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4950 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
4953 // AVX 256-bit register conversion intrinsics
4954 let Predicates = [HasAVX] in {
4955 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
4956 (VCVTDQ2PDYrr VR128:$src)>;
4957 def : Pat<(int_x86_avx_cvtdq2_pd_256 (bitconvert (memopv2i64 addr:$src))),
4958 (VCVTDQ2PDYrm addr:$src)>;
4960 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
4961 (VCVTPD2DQYrr VR256:$src)>;
4962 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
4963 (VCVTPD2DQYrm addr:$src)>;
4965 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
4966 (VCVTDQ2PDYrr VR128:$src)>;
4967 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
4968 (VCVTDQ2PDYrm addr:$src)>;
4969 } // Predicates = [HasAVX]
4971 //===---------------------------------------------------------------------===//
4972 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4973 //===---------------------------------------------------------------------===//
4974 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4975 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4976 X86MemOperand x86memop> {
4977 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4978 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4979 [(set RC:$dst, (vt (OpNode RC:$src)))],
4981 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4982 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4983 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4987 let Predicates = [HasAVX] in {
4988 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4989 v4f32, VR128, memopv4f32, f128mem>, VEX;
4990 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4991 v4f32, VR128, memopv4f32, f128mem>, VEX;
4992 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4993 v8f32, VR256, memopv8f32, f256mem>, VEX;
4994 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4995 v8f32, VR256, memopv8f32, f256mem>, VEX;
4997 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4998 memopv4f32, f128mem>;
4999 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5000 memopv4f32, f128mem>;
5002 let Predicates = [HasAVX] in {
5003 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5004 (VMOVSHDUPrr VR128:$src)>;
5005 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5006 (VMOVSHDUPrm addr:$src)>;
5007 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5008 (VMOVSLDUPrr VR128:$src)>;
5009 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5010 (VMOVSLDUPrm addr:$src)>;
5011 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5012 (VMOVSHDUPYrr VR256:$src)>;
5013 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
5014 (VMOVSHDUPYrm addr:$src)>;
5015 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5016 (VMOVSLDUPYrr VR256:$src)>;
5017 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
5018 (VMOVSLDUPYrm addr:$src)>;
5021 let Predicates = [HasSSE3] in {
5022 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5023 (MOVSHDUPrr VR128:$src)>;
5024 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5025 (MOVSHDUPrm addr:$src)>;
5026 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5027 (MOVSLDUPrr VR128:$src)>;
5028 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5029 (MOVSLDUPrm addr:$src)>;
5032 //===---------------------------------------------------------------------===//
5033 // SSE3 - Replicate Double FP - MOVDDUP
5034 //===---------------------------------------------------------------------===//
5036 multiclass sse3_replicate_dfp<string OpcodeStr> {
5037 let neverHasSideEffects = 1 in
5038 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5039 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5040 [], IIC_SSE_MOV_LH>;
5041 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5042 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5045 (scalar_to_vector (loadf64 addr:$src)))))],
5049 // FIXME: Merge with above classe when there're patterns for the ymm version
5050 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5051 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5052 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5053 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>;
5054 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5055 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5058 (scalar_to_vector (loadf64 addr:$src)))))]>;
5061 let Predicates = [HasAVX] in {
5062 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5063 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
5066 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5068 let Predicates = [HasAVX] in {
5069 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5070 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5071 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5072 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5073 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5074 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5075 def : Pat<(X86Movddup (bc_v2f64
5076 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5077 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5080 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
5081 (VMOVDDUPYrm addr:$src)>;
5082 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
5083 (VMOVDDUPYrm addr:$src)>;
5084 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5085 (VMOVDDUPYrm addr:$src)>;
5086 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5087 (VMOVDDUPYrr VR256:$src)>;
5090 let Predicates = [HasSSE3] in {
5091 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5092 (MOVDDUPrm addr:$src)>;
5093 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5094 (MOVDDUPrm addr:$src)>;
5095 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5096 (MOVDDUPrm addr:$src)>;
5097 def : Pat<(X86Movddup (bc_v2f64
5098 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5099 (MOVDDUPrm addr:$src)>;
5102 //===---------------------------------------------------------------------===//
5103 // SSE3 - Move Unaligned Integer
5104 //===---------------------------------------------------------------------===//
5106 let Predicates = [HasAVX] in {
5107 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5108 "vlddqu\t{$src, $dst|$dst, $src}",
5109 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5110 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5111 "vlddqu\t{$src, $dst|$dst, $src}",
5112 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
5114 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5115 "lddqu\t{$src, $dst|$dst, $src}",
5116 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5119 //===---------------------------------------------------------------------===//
5120 // SSE3 - Arithmetic
5121 //===---------------------------------------------------------------------===//
5123 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5124 X86MemOperand x86memop, OpndItins itins,
5126 def rr : I<0xD0, MRMSrcReg,
5127 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5129 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5130 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5131 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>;
5132 def rm : I<0xD0, MRMSrcMem,
5133 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5135 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5136 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5137 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>;
5140 let Predicates = [HasAVX] in {
5141 let ExeDomain = SSEPackedSingle in {
5142 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5143 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5144 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5145 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5147 let ExeDomain = SSEPackedDouble in {
5148 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5149 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5150 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5151 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5154 let Constraints = "$src1 = $dst", Predicates = [HasSSE3] in {
5155 let ExeDomain = SSEPackedSingle in
5156 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5157 f128mem, SSE_ALU_F32P>, TB, XD;
5158 let ExeDomain = SSEPackedDouble in
5159 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5160 f128mem, SSE_ALU_F64P>, TB, OpSize;
5163 //===---------------------------------------------------------------------===//
5164 // SSE3 Instructions
5165 //===---------------------------------------------------------------------===//
5168 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5169 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5170 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5172 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5173 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5174 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5176 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5178 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5179 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5180 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5181 IIC_SSE_HADDSUB_RM>;
5183 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5184 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5185 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5187 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5188 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5189 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5191 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5193 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5194 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5195 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5196 IIC_SSE_HADDSUB_RM>;
5199 let Predicates = [HasAVX] in {
5200 let ExeDomain = SSEPackedSingle in {
5201 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5202 X86fhadd, 0>, VEX_4V;
5203 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5204 X86fhsub, 0>, VEX_4V;
5205 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5206 X86fhadd, 0>, VEX_4V;
5207 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5208 X86fhsub, 0>, VEX_4V;
5210 let ExeDomain = SSEPackedDouble in {
5211 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5212 X86fhadd, 0>, VEX_4V;
5213 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5214 X86fhsub, 0>, VEX_4V;
5215 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5216 X86fhadd, 0>, VEX_4V;
5217 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5218 X86fhsub, 0>, VEX_4V;
5222 let Constraints = "$src1 = $dst" in {
5223 let ExeDomain = SSEPackedSingle in {
5224 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5225 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5227 let ExeDomain = SSEPackedDouble in {
5228 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5229 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5233 //===---------------------------------------------------------------------===//
5234 // SSSE3 - Packed Absolute Instructions
5235 //===---------------------------------------------------------------------===//
5238 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5239 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5240 Intrinsic IntId128> {
5241 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5243 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5244 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5247 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5249 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5252 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5256 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5257 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5258 Intrinsic IntId256> {
5259 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5261 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5262 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5265 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5267 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5270 (bitconvert (memopv4i64 addr:$src))))]>, OpSize;
5273 let Predicates = [HasAVX] in {
5274 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5275 int_x86_ssse3_pabs_b_128>, VEX;
5276 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5277 int_x86_ssse3_pabs_w_128>, VEX;
5278 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5279 int_x86_ssse3_pabs_d_128>, VEX;
5282 let Predicates = [HasAVX2] in {
5283 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5284 int_x86_avx2_pabs_b>, VEX;
5285 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5286 int_x86_avx2_pabs_w>, VEX;
5287 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5288 int_x86_avx2_pabs_d>, VEX;
5291 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5292 int_x86_ssse3_pabs_b_128>;
5293 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5294 int_x86_ssse3_pabs_w_128>;
5295 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5296 int_x86_ssse3_pabs_d_128>;
5298 //===---------------------------------------------------------------------===//
5299 // SSSE3 - Packed Binary Operator Instructions
5300 //===---------------------------------------------------------------------===//
5302 def SSE_PHADDSUBD : OpndItins<
5303 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5305 def SSE_PHADDSUBSW : OpndItins<
5306 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5308 def SSE_PHADDSUBW : OpndItins<
5309 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5311 def SSE_PSHUFB : OpndItins<
5312 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5314 def SSE_PSIGN : OpndItins<
5315 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5317 def SSE_PMULHRSW : OpndItins<
5318 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5321 /// SS3I_binop_rm - Simple SSSE3 bin op
5322 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5323 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5324 X86MemOperand x86memop, OpndItins itins,
5326 let isCommutable = 1 in
5327 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5328 (ins RC:$src1, RC:$src2),
5330 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5331 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5332 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5334 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5335 (ins RC:$src1, x86memop:$src2),
5337 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5338 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5340 (OpVT (OpNode RC:$src1,
5341 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize;
5344 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5345 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5346 Intrinsic IntId128, OpndItins itins,
5348 let isCommutable = 1 in
5349 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5350 (ins VR128:$src1, VR128:$src2),
5352 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5353 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5354 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5356 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5357 (ins VR128:$src1, i128mem:$src2),
5359 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5360 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5362 (IntId128 VR128:$src1,
5363 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
5366 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5367 Intrinsic IntId256> {
5368 let isCommutable = 1 in
5369 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5370 (ins VR256:$src1, VR256:$src2),
5371 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5372 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5374 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5375 (ins VR256:$src1, i256mem:$src2),
5376 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5378 (IntId256 VR256:$src1,
5379 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5382 let ImmT = NoImm, Predicates = [HasAVX] in {
5383 let isCommutable = 0 in {
5384 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5385 memopv2i64, i128mem,
5386 SSE_PHADDSUBW, 0>, VEX_4V;
5387 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5388 memopv2i64, i128mem,
5389 SSE_PHADDSUBD, 0>, VEX_4V;
5390 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5391 memopv2i64, i128mem,
5392 SSE_PHADDSUBW, 0>, VEX_4V;
5393 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5394 memopv2i64, i128mem,
5395 SSE_PHADDSUBD, 0>, VEX_4V;
5396 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5397 memopv2i64, i128mem,
5398 SSE_PSIGN, 0>, VEX_4V;
5399 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5400 memopv2i64, i128mem,
5401 SSE_PSIGN, 0>, VEX_4V;
5402 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5403 memopv2i64, i128mem,
5404 SSE_PSIGN, 0>, VEX_4V;
5405 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5406 memopv2i64, i128mem,
5407 SSE_PSHUFB, 0>, VEX_4V;
5408 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5409 int_x86_ssse3_phadd_sw_128,
5410 SSE_PHADDSUBSW, 0>, VEX_4V;
5411 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5412 int_x86_ssse3_phsub_sw_128,
5413 SSE_PHADDSUBSW, 0>, VEX_4V;
5414 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5415 int_x86_ssse3_pmadd_ub_sw_128,
5416 SSE_PMADD, 0>, VEX_4V;
5418 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5419 int_x86_ssse3_pmul_hr_sw_128,
5420 SSE_PMULHRSW, 0>, VEX_4V;
5423 let ImmT = NoImm, Predicates = [HasAVX2] in {
5424 let isCommutable = 0 in {
5425 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5426 memopv4i64, i256mem,
5427 SSE_PHADDSUBW, 0>, VEX_4V;
5428 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5429 memopv4i64, i256mem,
5430 SSE_PHADDSUBW, 0>, VEX_4V;
5431 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5432 memopv4i64, i256mem,
5433 SSE_PHADDSUBW, 0>, VEX_4V;
5434 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5435 memopv4i64, i256mem,
5436 SSE_PHADDSUBW, 0>, VEX_4V;
5437 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5438 memopv4i64, i256mem,
5439 SSE_PHADDSUBW, 0>, VEX_4V;
5440 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5441 memopv4i64, i256mem,
5442 SSE_PHADDSUBW, 0>, VEX_4V;
5443 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5444 memopv4i64, i256mem,
5445 SSE_PHADDSUBW, 0>, VEX_4V;
5446 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5447 memopv4i64, i256mem,
5448 SSE_PHADDSUBW, 0>, VEX_4V;
5449 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5450 int_x86_avx2_phadd_sw>, VEX_4V;
5451 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5452 int_x86_avx2_phsub_sw>, VEX_4V;
5453 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5454 int_x86_avx2_pmadd_ub_sw>, VEX_4V;
5456 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5457 int_x86_avx2_pmul_hr_sw>, VEX_4V;
5460 // None of these have i8 immediate fields.
5461 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5462 let isCommutable = 0 in {
5463 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5464 memopv2i64, i128mem, SSE_PHADDSUBW>;
5465 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5466 memopv2i64, i128mem, SSE_PHADDSUBD>;
5467 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5468 memopv2i64, i128mem, SSE_PHADDSUBW>;
5469 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5470 memopv2i64, i128mem, SSE_PHADDSUBD>;
5471 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5472 memopv2i64, i128mem, SSE_PSIGN>;
5473 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5474 memopv2i64, i128mem, SSE_PSIGN>;
5475 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5476 memopv2i64, i128mem, SSE_PSIGN>;
5477 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5478 memopv2i64, i128mem, SSE_PSHUFB>;
5479 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5480 int_x86_ssse3_phadd_sw_128,
5482 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5483 int_x86_ssse3_phsub_sw_128,
5485 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5486 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5488 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5489 int_x86_ssse3_pmul_hr_sw_128,
5493 //===---------------------------------------------------------------------===//
5494 // SSSE3 - Packed Align Instruction Patterns
5495 //===---------------------------------------------------------------------===//
5497 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
5498 let neverHasSideEffects = 1 in {
5499 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5500 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5502 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5504 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5505 [], IIC_SSE_PALIGNR>, OpSize;
5507 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5508 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5510 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5512 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5513 [], IIC_SSE_PALIGNR>, OpSize;
5517 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
5518 let neverHasSideEffects = 1 in {
5519 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5520 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5522 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5525 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5526 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5528 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5533 let Predicates = [HasAVX] in
5534 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5535 let Predicates = [HasAVX2] in
5536 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V;
5537 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
5538 defm PALIGN : ssse3_palign<"palignr">;
5540 let Predicates = [HasAVX2] in {
5541 def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5542 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5543 def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5544 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5545 def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5546 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5547 def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5548 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5551 let Predicates = [HasAVX] in {
5552 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5553 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5554 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5555 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5556 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5557 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5558 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5559 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5562 let Predicates = [HasSSSE3] in {
5563 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5564 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5565 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5566 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5567 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5568 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5569 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5570 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5573 //===---------------------------------------------------------------------===//
5574 // SSSE3 - Thread synchronization
5575 //===---------------------------------------------------------------------===//
5577 let usesCustomInserter = 1 in {
5578 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5579 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5580 Requires<[HasSSE3]>;
5581 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
5582 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>,
5583 Requires<[HasSSE3]>;
5586 let Uses = [EAX, ECX, EDX] in
5587 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5588 TB, Requires<[HasSSE3]>;
5589 let Uses = [ECX, EAX] in
5590 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", [], IIC_SSE_MWAIT>,
5591 TB, Requires<[HasSSE3]>;
5593 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5594 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5596 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5597 Requires<[In32BitMode]>;
5598 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5599 Requires<[In64BitMode]>;
5601 //===----------------------------------------------------------------------===//
5602 // SSE4.1 - Packed Move with Sign/Zero Extend
5603 //===----------------------------------------------------------------------===//
5605 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5606 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5607 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5608 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5610 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5611 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5613 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5617 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5619 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5620 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5621 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5623 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5624 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5625 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5628 let Predicates = [HasAVX] in {
5629 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5631 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5633 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5635 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5637 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5639 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5643 let Predicates = [HasAVX2] in {
5644 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5645 int_x86_avx2_pmovsxbw>, VEX;
5646 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5647 int_x86_avx2_pmovsxwd>, VEX;
5648 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5649 int_x86_avx2_pmovsxdq>, VEX;
5650 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5651 int_x86_avx2_pmovzxbw>, VEX;
5652 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5653 int_x86_avx2_pmovzxwd>, VEX;
5654 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5655 int_x86_avx2_pmovzxdq>, VEX;
5658 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5659 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5660 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5661 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5662 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5663 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5665 let Predicates = [HasAVX] in {
5666 // Common patterns involving scalar load.
5667 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5668 (VPMOVSXBWrm addr:$src)>;
5669 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5670 (VPMOVSXBWrm addr:$src)>;
5672 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5673 (VPMOVSXWDrm addr:$src)>;
5674 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5675 (VPMOVSXWDrm addr:$src)>;
5677 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5678 (VPMOVSXDQrm addr:$src)>;
5679 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5680 (VPMOVSXDQrm addr:$src)>;
5682 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5683 (VPMOVZXBWrm addr:$src)>;
5684 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5685 (VPMOVZXBWrm addr:$src)>;
5687 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5688 (VPMOVZXWDrm addr:$src)>;
5689 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5690 (VPMOVZXWDrm addr:$src)>;
5692 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5693 (VPMOVZXDQrm addr:$src)>;
5694 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5695 (VPMOVZXDQrm addr:$src)>;
5698 let Predicates = [HasSSE41] in {
5699 // Common patterns involving scalar load.
5700 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5701 (PMOVSXBWrm addr:$src)>;
5702 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5703 (PMOVSXBWrm addr:$src)>;
5705 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5706 (PMOVSXWDrm addr:$src)>;
5707 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5708 (PMOVSXWDrm addr:$src)>;
5710 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5711 (PMOVSXDQrm addr:$src)>;
5712 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5713 (PMOVSXDQrm addr:$src)>;
5715 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5716 (PMOVZXBWrm addr:$src)>;
5717 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5718 (PMOVZXBWrm addr:$src)>;
5720 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5721 (PMOVZXWDrm addr:$src)>;
5722 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5723 (PMOVZXWDrm addr:$src)>;
5725 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5726 (PMOVZXDQrm addr:$src)>;
5727 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5728 (PMOVZXDQrm addr:$src)>;
5731 let Predicates = [HasAVX2] in {
5732 let AddedComplexity = 15 in {
5733 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5734 (VPMOVZXDQYrr VR128:$src)>;
5735 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5736 (VPMOVZXWDYrr VR128:$src)>;
5739 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5740 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5743 let Predicates = [HasAVX] in {
5744 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5745 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5748 let Predicates = [HasSSE41] in {
5749 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5750 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5754 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5755 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5756 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5757 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5759 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5760 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5762 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5766 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5768 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5769 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5770 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5772 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5773 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5775 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5779 let Predicates = [HasAVX] in {
5780 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5782 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5784 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5786 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5790 let Predicates = [HasAVX2] in {
5791 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5792 int_x86_avx2_pmovsxbd>, VEX;
5793 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5794 int_x86_avx2_pmovsxwq>, VEX;
5795 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5796 int_x86_avx2_pmovzxbd>, VEX;
5797 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5798 int_x86_avx2_pmovzxwq>, VEX;
5801 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5802 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5803 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5804 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5806 let Predicates = [HasAVX] in {
5807 // Common patterns involving scalar load
5808 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5809 (VPMOVSXBDrm addr:$src)>;
5810 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5811 (VPMOVSXWQrm addr:$src)>;
5813 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5814 (VPMOVZXBDrm addr:$src)>;
5815 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5816 (VPMOVZXWQrm addr:$src)>;
5819 let Predicates = [HasSSE41] in {
5820 // Common patterns involving scalar load
5821 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5822 (PMOVSXBDrm addr:$src)>;
5823 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5824 (PMOVSXWQrm addr:$src)>;
5826 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5827 (PMOVZXBDrm addr:$src)>;
5828 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5829 (PMOVZXWQrm addr:$src)>;
5832 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5833 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5834 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5835 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5837 // Expecting a i16 load any extended to i32 value.
5838 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5839 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5840 [(set VR128:$dst, (IntId (bitconvert
5841 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5845 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5847 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5848 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5849 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5851 // Expecting a i16 load any extended to i32 value.
5852 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5853 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5854 [(set VR256:$dst, (IntId (bitconvert
5855 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5859 let Predicates = [HasAVX] in {
5860 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5862 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5865 let Predicates = [HasAVX2] in {
5866 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5867 int_x86_avx2_pmovsxbq>, VEX;
5868 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5869 int_x86_avx2_pmovzxbq>, VEX;
5871 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5872 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5874 let Predicates = [HasAVX] in {
5875 // Common patterns involving scalar load
5876 def : Pat<(int_x86_sse41_pmovsxbq
5877 (bitconvert (v4i32 (X86vzmovl
5878 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5879 (VPMOVSXBQrm addr:$src)>;
5881 def : Pat<(int_x86_sse41_pmovzxbq
5882 (bitconvert (v4i32 (X86vzmovl
5883 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5884 (VPMOVZXBQrm addr:$src)>;
5887 let Predicates = [HasSSE41] in {
5888 // Common patterns involving scalar load
5889 def : Pat<(int_x86_sse41_pmovsxbq
5890 (bitconvert (v4i32 (X86vzmovl
5891 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5892 (PMOVSXBQrm addr:$src)>;
5894 def : Pat<(int_x86_sse41_pmovzxbq
5895 (bitconvert (v4i32 (X86vzmovl
5896 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5897 (PMOVZXBQrm addr:$src)>;
5900 //===----------------------------------------------------------------------===//
5901 // SSE4.1 - Extract Instructions
5902 //===----------------------------------------------------------------------===//
5904 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5905 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5906 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5907 (ins VR128:$src1, i32i8imm:$src2),
5908 !strconcat(OpcodeStr,
5909 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5910 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5912 let neverHasSideEffects = 1, mayStore = 1 in
5913 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5914 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5915 !strconcat(OpcodeStr,
5916 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5919 // There's an AssertZext in the way of writing the store pattern
5920 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5923 let Predicates = [HasAVX] in {
5924 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5925 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5926 (ins VR128:$src1, i32i8imm:$src2),
5927 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5930 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5933 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5934 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5935 let neverHasSideEffects = 1, mayStore = 1 in
5936 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5937 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5938 !strconcat(OpcodeStr,
5939 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5942 // There's an AssertZext in the way of writing the store pattern
5943 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5946 let Predicates = [HasAVX] in
5947 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5949 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5952 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5953 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5954 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5955 (ins VR128:$src1, i32i8imm:$src2),
5956 !strconcat(OpcodeStr,
5957 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5959 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5960 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5961 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5962 !strconcat(OpcodeStr,
5963 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5964 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5965 addr:$dst)]>, OpSize;
5968 let Predicates = [HasAVX] in
5969 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5971 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5973 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5974 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5975 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5976 (ins VR128:$src1, i32i8imm:$src2),
5977 !strconcat(OpcodeStr,
5978 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5980 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5981 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5982 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5983 !strconcat(OpcodeStr,
5984 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5985 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5986 addr:$dst)]>, OpSize, REX_W;
5989 let Predicates = [HasAVX] in
5990 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5992 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5994 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5996 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5997 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5998 (ins VR128:$src1, i32i8imm:$src2),
5999 !strconcat(OpcodeStr,
6000 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6002 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
6004 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6005 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
6006 !strconcat(OpcodeStr,
6007 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6008 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6009 addr:$dst)]>, OpSize;
6012 let ExeDomain = SSEPackedSingle in {
6013 let Predicates = [HasAVX] in {
6014 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6015 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
6016 (ins VR128:$src1, i32i8imm:$src2),
6017 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
6020 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
6023 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6024 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6027 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6029 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6032 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6033 Requires<[HasSSE41]>;
6035 //===----------------------------------------------------------------------===//
6036 // SSE4.1 - Insert Instructions
6037 //===----------------------------------------------------------------------===//
6039 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6040 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6041 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6043 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6045 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6047 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
6048 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6049 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6051 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6053 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6055 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6056 imm:$src3))]>, OpSize;
6059 let Predicates = [HasAVX] in
6060 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6061 let Constraints = "$src1 = $dst" in
6062 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6064 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6065 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6066 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6068 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6070 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6072 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6074 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6075 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6077 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6079 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6081 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6082 imm:$src3)))]>, OpSize;
6085 let Predicates = [HasAVX] in
6086 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6087 let Constraints = "$src1 = $dst" in
6088 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6090 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6091 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6092 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6094 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6096 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6098 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6100 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6101 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6103 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6105 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6107 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6108 imm:$src3)))]>, OpSize;
6111 let Predicates = [HasAVX] in
6112 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6113 let Constraints = "$src1 = $dst" in
6114 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6116 // insertps has a few different modes, there's the first two here below which
6117 // are optimized inserts that won't zero arbitrary elements in the destination
6118 // vector. The next one matches the intrinsic and could zero arbitrary elements
6119 // in the target vector.
6120 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
6121 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6122 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6124 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6126 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6128 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
6130 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6131 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6133 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6135 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6137 (X86insrtps VR128:$src1,
6138 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6139 imm:$src3))]>, OpSize;
6142 let ExeDomain = SSEPackedSingle in {
6143 let Predicates = [HasAVX] in
6144 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6145 let Constraints = "$src1 = $dst" in
6146 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
6149 //===----------------------------------------------------------------------===//
6150 // SSE4.1 - Round Instructions
6151 //===----------------------------------------------------------------------===//
6153 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6154 X86MemOperand x86memop, RegisterClass RC,
6155 PatFrag mem_frag32, PatFrag mem_frag64,
6156 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6157 let ExeDomain = SSEPackedSingle in {
6158 // Intrinsic operation, reg.
6159 // Vector intrinsic operation, reg
6160 def PSr : SS4AIi8<opcps, MRMSrcReg,
6161 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6162 !strconcat(OpcodeStr,
6163 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6164 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
6167 // Vector intrinsic operation, mem
6168 def PSm : SS4AIi8<opcps, MRMSrcMem,
6169 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6170 !strconcat(OpcodeStr,
6171 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6173 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
6175 } // ExeDomain = SSEPackedSingle
6177 let ExeDomain = SSEPackedDouble in {
6178 // Vector intrinsic operation, reg
6179 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6180 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6181 !strconcat(OpcodeStr,
6182 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6183 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
6186 // Vector intrinsic operation, mem
6187 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6188 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6189 !strconcat(OpcodeStr,
6190 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6192 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
6194 } // ExeDomain = SSEPackedDouble
6197 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6200 Intrinsic F64Int, bit Is2Addr = 1> {
6201 let ExeDomain = GenericDomain in {
6203 def SSr : SS4AIi8<opcss, MRMSrcReg,
6204 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6206 !strconcat(OpcodeStr,
6207 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6208 !strconcat(OpcodeStr,
6209 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6212 // Intrinsic operation, reg.
6213 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6214 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6216 !strconcat(OpcodeStr,
6217 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6218 !strconcat(OpcodeStr,
6219 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6220 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6223 // Intrinsic operation, mem.
6224 def SSm : SS4AIi8<opcss, MRMSrcMem,
6225 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6227 !strconcat(OpcodeStr,
6228 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6229 !strconcat(OpcodeStr,
6230 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6232 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6236 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6237 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6239 !strconcat(OpcodeStr,
6240 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6241 !strconcat(OpcodeStr,
6242 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6245 // Intrinsic operation, reg.
6246 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6247 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6249 !strconcat(OpcodeStr,
6250 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6251 !strconcat(OpcodeStr,
6252 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6253 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6256 // Intrinsic operation, mem.
6257 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6258 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6260 !strconcat(OpcodeStr,
6261 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6262 !strconcat(OpcodeStr,
6263 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6265 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6267 } // ExeDomain = GenericDomain
6270 // FP round - roundss, roundps, roundsd, roundpd
6271 let Predicates = [HasAVX] in {
6273 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6274 memopv4f32, memopv2f64,
6275 int_x86_sse41_round_ps,
6276 int_x86_sse41_round_pd>, VEX;
6277 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6278 memopv8f32, memopv4f64,
6279 int_x86_avx_round_ps_256,
6280 int_x86_avx_round_pd_256>, VEX;
6281 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6282 int_x86_sse41_round_ss,
6283 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6285 def : Pat<(ffloor FR32:$src),
6286 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6287 def : Pat<(f64 (ffloor FR64:$src)),
6288 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6289 def : Pat<(f32 (fnearbyint FR32:$src)),
6290 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6291 def : Pat<(f64 (fnearbyint FR64:$src)),
6292 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6293 def : Pat<(f32 (fceil FR32:$src)),
6294 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6295 def : Pat<(f64 (fceil FR64:$src)),
6296 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6297 def : Pat<(f32 (frint FR32:$src)),
6298 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6299 def : Pat<(f64 (frint FR64:$src)),
6300 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6301 def : Pat<(f32 (ftrunc FR32:$src)),
6302 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6303 def : Pat<(f64 (ftrunc FR64:$src)),
6304 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6307 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6308 memopv4f32, memopv2f64,
6309 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6310 let Constraints = "$src1 = $dst" in
6311 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6312 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6314 def : Pat<(ffloor FR32:$src),
6315 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6316 def : Pat<(f64 (ffloor FR64:$src)),
6317 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6318 def : Pat<(f32 (fnearbyint FR32:$src)),
6319 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6320 def : Pat<(f64 (fnearbyint FR64:$src)),
6321 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6322 def : Pat<(f32 (fceil FR32:$src)),
6323 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6324 def : Pat<(f64 (fceil FR64:$src)),
6325 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6326 def : Pat<(f32 (frint FR32:$src)),
6327 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6328 def : Pat<(f64 (frint FR64:$src)),
6329 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6330 def : Pat<(f32 (ftrunc FR32:$src)),
6331 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6332 def : Pat<(f64 (ftrunc FR64:$src)),
6333 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6335 //===----------------------------------------------------------------------===//
6336 // SSE4.1 - Packed Bit Test
6337 //===----------------------------------------------------------------------===//
6339 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6340 // the intel intrinsic that corresponds to this.
6341 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6342 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6343 "vptest\t{$src2, $src1|$src1, $src2}",
6344 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6346 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6347 "vptest\t{$src2, $src1|$src1, $src2}",
6348 [(set EFLAGS,(X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6351 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6352 "vptest\t{$src2, $src1|$src1, $src2}",
6353 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6355 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6356 "vptest\t{$src2, $src1|$src1, $src2}",
6357 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6361 let Defs = [EFLAGS] in {
6362 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6363 "ptest\t{$src2, $src1|$src1, $src2}",
6364 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6366 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6367 "ptest\t{$src2, $src1|$src1, $src2}",
6368 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6372 // The bit test instructions below are AVX only
6373 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6374 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6375 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6376 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6377 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6378 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6379 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6380 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6384 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6385 let ExeDomain = SSEPackedSingle in {
6386 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6387 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
6389 let ExeDomain = SSEPackedDouble in {
6390 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6391 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
6395 //===----------------------------------------------------------------------===//
6396 // SSE4.1 - Misc Instructions
6397 //===----------------------------------------------------------------------===//
6399 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6400 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6401 "popcnt{w}\t{$src, $dst|$dst, $src}",
6402 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6404 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6405 "popcnt{w}\t{$src, $dst|$dst, $src}",
6406 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6407 (implicit EFLAGS)]>, OpSize, XS;
6409 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6410 "popcnt{l}\t{$src, $dst|$dst, $src}",
6411 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6413 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6414 "popcnt{l}\t{$src, $dst|$dst, $src}",
6415 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6416 (implicit EFLAGS)]>, XS;
6418 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6419 "popcnt{q}\t{$src, $dst|$dst, $src}",
6420 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6422 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6423 "popcnt{q}\t{$src, $dst|$dst, $src}",
6424 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6425 (implicit EFLAGS)]>, XS;
6430 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6431 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6432 Intrinsic IntId128> {
6433 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6435 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6436 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6437 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6439 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6442 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6445 let Predicates = [HasAVX] in
6446 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6447 int_x86_sse41_phminposuw>, VEX;
6448 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6449 int_x86_sse41_phminposuw>;
6451 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6452 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6453 Intrinsic IntId128, bit Is2Addr = 1> {
6454 let isCommutable = 1 in
6455 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6456 (ins VR128:$src1, VR128:$src2),
6458 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6459 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6460 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6461 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6462 (ins VR128:$src1, i128mem:$src2),
6464 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6465 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6467 (IntId128 VR128:$src1,
6468 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6471 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6472 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6473 Intrinsic IntId256> {
6474 let isCommutable = 1 in
6475 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6476 (ins VR256:$src1, VR256:$src2),
6477 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6478 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6479 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6480 (ins VR256:$src1, i256mem:$src2),
6481 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6483 (IntId256 VR256:$src1,
6484 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6487 let Predicates = [HasAVX] in {
6488 let isCommutable = 0 in
6489 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6491 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
6493 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
6495 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
6497 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
6499 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
6501 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
6503 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
6505 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
6507 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6511 let Predicates = [HasAVX2] in {
6512 let isCommutable = 0 in
6513 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6514 int_x86_avx2_packusdw>, VEX_4V;
6515 defm VPMINSB : SS41I_binop_rm_int_y<0x38, "vpminsb",
6516 int_x86_avx2_pmins_b>, VEX_4V;
6517 defm VPMINSD : SS41I_binop_rm_int_y<0x39, "vpminsd",
6518 int_x86_avx2_pmins_d>, VEX_4V;
6519 defm VPMINUD : SS41I_binop_rm_int_y<0x3B, "vpminud",
6520 int_x86_avx2_pminu_d>, VEX_4V;
6521 defm VPMINUW : SS41I_binop_rm_int_y<0x3A, "vpminuw",
6522 int_x86_avx2_pminu_w>, VEX_4V;
6523 defm VPMAXSB : SS41I_binop_rm_int_y<0x3C, "vpmaxsb",
6524 int_x86_avx2_pmaxs_b>, VEX_4V;
6525 defm VPMAXSD : SS41I_binop_rm_int_y<0x3D, "vpmaxsd",
6526 int_x86_avx2_pmaxs_d>, VEX_4V;
6527 defm VPMAXUD : SS41I_binop_rm_int_y<0x3F, "vpmaxud",
6528 int_x86_avx2_pmaxu_d>, VEX_4V;
6529 defm VPMAXUW : SS41I_binop_rm_int_y<0x3E, "vpmaxuw",
6530 int_x86_avx2_pmaxu_w>, VEX_4V;
6531 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6532 int_x86_avx2_pmul_dq>, VEX_4V;
6535 let Constraints = "$src1 = $dst" in {
6536 let isCommutable = 0 in
6537 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6538 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
6539 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
6540 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
6541 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
6542 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
6543 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
6544 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
6545 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
6546 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6549 /// SS48I_binop_rm - Simple SSE41 binary operator.
6550 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6551 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6552 X86MemOperand x86memop, bit Is2Addr = 1> {
6553 let isCommutable = 1 in
6554 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6555 (ins RC:$src1, RC:$src2),
6557 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6558 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6559 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6560 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6561 (ins RC:$src1, x86memop:$src2),
6563 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6564 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6566 (OpVT (OpNode RC:$src1,
6567 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6570 let Predicates = [HasAVX] in {
6571 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6572 memopv2i64, i128mem, 0>, VEX_4V;
6573 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6574 memopv2i64, i128mem, 0>, VEX_4V;
6576 let Predicates = [HasAVX2] in {
6577 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6578 memopv4i64, i256mem, 0>, VEX_4V;
6579 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6580 memopv4i64, i256mem, 0>, VEX_4V;
6583 let Constraints = "$src1 = $dst" in {
6584 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6585 memopv2i64, i128mem>;
6586 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6587 memopv2i64, i128mem>;
6590 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6591 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6592 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6593 X86MemOperand x86memop, bit Is2Addr = 1> {
6594 let isCommutable = 1 in
6595 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6596 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6598 !strconcat(OpcodeStr,
6599 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6600 !strconcat(OpcodeStr,
6601 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6602 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6604 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6605 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6607 !strconcat(OpcodeStr,
6608 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6609 !strconcat(OpcodeStr,
6610 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6613 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6617 let Predicates = [HasAVX] in {
6618 let isCommutable = 0 in {
6619 let ExeDomain = SSEPackedSingle in {
6620 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6621 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6622 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6623 int_x86_avx_blend_ps_256, VR256, memopv8f32, i256mem, 0>, VEX_4V;
6625 let ExeDomain = SSEPackedDouble in {
6626 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6627 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6628 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6629 int_x86_avx_blend_pd_256, VR256, memopv4f64, i256mem, 0>, VEX_4V;
6631 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6632 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6633 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6634 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6636 let ExeDomain = SSEPackedSingle in
6637 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6638 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6639 let ExeDomain = SSEPackedDouble in
6640 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6641 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6642 let ExeDomain = SSEPackedSingle in
6643 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6644 VR256, memopv8f32, i256mem, 0>, VEX_4V;
6647 let Predicates = [HasAVX2] in {
6648 let isCommutable = 0 in {
6649 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6650 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6651 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6652 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6656 let Constraints = "$src1 = $dst" in {
6657 let isCommutable = 0 in {
6658 let ExeDomain = SSEPackedSingle in
6659 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6660 VR128, memopv4f32, i128mem>;
6661 let ExeDomain = SSEPackedDouble in
6662 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6663 VR128, memopv2f64, i128mem>;
6664 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6665 VR128, memopv2i64, i128mem>;
6666 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6667 VR128, memopv2i64, i128mem>;
6669 let ExeDomain = SSEPackedSingle in
6670 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6671 VR128, memopv4f32, i128mem>;
6672 let ExeDomain = SSEPackedDouble in
6673 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6674 VR128, memopv2f64, i128mem>;
6677 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6678 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6679 RegisterClass RC, X86MemOperand x86memop,
6680 PatFrag mem_frag, Intrinsic IntId> {
6681 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6682 (ins RC:$src1, RC:$src2, RC:$src3),
6683 !strconcat(OpcodeStr,
6684 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6685 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6686 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6688 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6689 (ins RC:$src1, x86memop:$src2, RC:$src3),
6690 !strconcat(OpcodeStr,
6691 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6693 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6695 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6698 let Predicates = [HasAVX] in {
6699 let ExeDomain = SSEPackedDouble in {
6700 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
6701 memopv2f64, int_x86_sse41_blendvpd>;
6702 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
6703 memopv4f64, int_x86_avx_blendv_pd_256>;
6704 } // ExeDomain = SSEPackedDouble
6705 let ExeDomain = SSEPackedSingle in {
6706 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
6707 memopv4f32, int_x86_sse41_blendvps>;
6708 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
6709 memopv8f32, int_x86_avx_blendv_ps_256>;
6710 } // ExeDomain = SSEPackedSingle
6711 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6712 memopv2i64, int_x86_sse41_pblendvb>;
6715 let Predicates = [HasAVX2] in {
6716 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6717 memopv4i64, int_x86_avx2_pblendvb>;
6720 let Predicates = [HasAVX] in {
6721 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6722 (v16i8 VR128:$src2))),
6723 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6724 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6725 (v4i32 VR128:$src2))),
6726 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6727 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6728 (v4f32 VR128:$src2))),
6729 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6730 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6731 (v2i64 VR128:$src2))),
6732 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6733 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6734 (v2f64 VR128:$src2))),
6735 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6736 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6737 (v8i32 VR256:$src2))),
6738 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6739 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6740 (v8f32 VR256:$src2))),
6741 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6742 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6743 (v4i64 VR256:$src2))),
6744 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6745 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6746 (v4f64 VR256:$src2))),
6747 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6749 def : Pat<(v8f32 (X86Blendps (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6751 (VBLENDPSYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6752 def : Pat<(v4f64 (X86Blendpd (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6754 (VBLENDPDYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6756 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6758 (VPBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6759 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6761 (VBLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6762 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6764 (VBLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6767 let Predicates = [HasAVX2] in {
6768 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6769 (v32i8 VR256:$src2))),
6770 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6771 def : Pat<(v16i16 (X86Blendpw (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6773 (VPBLENDWYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6776 /// SS41I_ternary_int - SSE 4.1 ternary operator
6777 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6778 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6780 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6781 (ins VR128:$src1, VR128:$src2),
6782 !strconcat(OpcodeStr,
6783 "\t{$src2, $dst|$dst, $src2}"),
6784 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6787 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6788 (ins VR128:$src1, i128mem:$src2),
6789 !strconcat(OpcodeStr,
6790 "\t{$src2, $dst|$dst, $src2}"),
6793 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
6797 let ExeDomain = SSEPackedDouble in
6798 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64,
6799 int_x86_sse41_blendvpd>;
6800 let ExeDomain = SSEPackedSingle in
6801 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32,
6802 int_x86_sse41_blendvps>;
6803 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64,
6804 int_x86_sse41_pblendvb>;
6806 let Predicates = [HasSSE41] in {
6807 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6808 (v16i8 VR128:$src2))),
6809 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6810 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6811 (v4i32 VR128:$src2))),
6812 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6813 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6814 (v4f32 VR128:$src2))),
6815 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6816 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6817 (v2i64 VR128:$src2))),
6818 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6819 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6820 (v2f64 VR128:$src2))),
6821 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6823 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6825 (PBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6826 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6828 (BLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6829 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6831 (BLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6835 let Predicates = [HasAVX] in
6836 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6837 "vmovntdqa\t{$src, $dst|$dst, $src}",
6838 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6840 let Predicates = [HasAVX2] in
6841 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
6842 "vmovntdqa\t{$src, $dst|$dst, $src}",
6843 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
6845 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6846 "movntdqa\t{$src, $dst|$dst, $src}",
6847 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6850 //===----------------------------------------------------------------------===//
6851 // SSE4.2 - Compare Instructions
6852 //===----------------------------------------------------------------------===//
6854 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
6855 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6856 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6857 X86MemOperand x86memop, bit Is2Addr = 1> {
6858 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
6859 (ins RC:$src1, RC:$src2),
6861 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6862 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6863 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6865 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
6866 (ins RC:$src1, x86memop:$src2),
6868 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6869 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6871 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
6874 let Predicates = [HasAVX] in
6875 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
6876 memopv2i64, i128mem, 0>, VEX_4V;
6878 let Predicates = [HasAVX2] in
6879 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
6880 memopv4i64, i256mem, 0>, VEX_4V;
6882 let Constraints = "$src1 = $dst" in
6883 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
6884 memopv2i64, i128mem>;
6886 //===----------------------------------------------------------------------===//
6887 // SSE4.2 - String/text Processing Instructions
6888 //===----------------------------------------------------------------------===//
6890 // Packed Compare Implicit Length Strings, Return Mask
6891 multiclass pseudo_pcmpistrm<string asm> {
6892 def REG : PseudoI<(outs VR128:$dst),
6893 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6894 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6896 def MEM : PseudoI<(outs VR128:$dst),
6897 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6898 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6899 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6902 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6903 let AddedComplexity = 1 in
6904 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6905 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
6908 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1, Predicates = [HasAVX] in {
6909 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6910 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6911 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6913 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6914 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6915 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6918 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
6919 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6920 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6921 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6923 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6924 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6925 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6928 // Packed Compare Explicit Length Strings, Return Mask
6929 multiclass pseudo_pcmpestrm<string asm> {
6930 def REG : PseudoI<(outs VR128:$dst),
6931 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6932 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6933 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6934 def MEM : PseudoI<(outs VR128:$dst),
6935 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6936 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6937 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6940 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6941 let AddedComplexity = 1 in
6942 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6943 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
6946 let Predicates = [HasAVX],
6947 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6948 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6949 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6950 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6952 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6953 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6954 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6957 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6958 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6959 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6960 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6962 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6963 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6964 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6967 // Packed Compare Implicit Length Strings, Return Index
6968 let Defs = [ECX, EFLAGS] in {
6969 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
6970 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6971 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6972 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6973 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
6974 (implicit EFLAGS)]>, OpSize;
6975 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6976 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6977 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6978 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
6979 (implicit EFLAGS)]>, OpSize;
6983 let Predicates = [HasAVX] in {
6984 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
6986 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
6988 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
6990 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
6992 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
6994 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
6998 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
6999 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
7000 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
7001 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
7002 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
7003 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
7005 // Packed Compare Explicit Length Strings, Return Index
7006 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
7007 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
7008 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7009 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7010 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7011 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
7012 (implicit EFLAGS)]>, OpSize;
7013 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7014 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7015 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7017 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
7018 (implicit EFLAGS)]>, OpSize;
7022 let Predicates = [HasAVX] in {
7023 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
7025 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
7027 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
7029 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
7031 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
7033 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
7037 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
7038 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
7039 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
7040 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
7041 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
7042 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
7044 //===----------------------------------------------------------------------===//
7045 // SSE4.2 - CRC Instructions
7046 //===----------------------------------------------------------------------===//
7048 // No CRC instructions have AVX equivalents
7050 // crc intrinsic instruction
7051 // This set of instructions are only rm, the only difference is the size
7053 let Constraints = "$src1 = $dst" in {
7054 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
7055 (ins GR32:$src1, i8mem:$src2),
7056 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7058 (int_x86_sse42_crc32_32_8 GR32:$src1,
7059 (load addr:$src2)))]>;
7060 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
7061 (ins GR32:$src1, GR8:$src2),
7062 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7064 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
7065 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7066 (ins GR32:$src1, i16mem:$src2),
7067 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7069 (int_x86_sse42_crc32_32_16 GR32:$src1,
7070 (load addr:$src2)))]>,
7072 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7073 (ins GR32:$src1, GR16:$src2),
7074 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7076 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
7078 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7079 (ins GR32:$src1, i32mem:$src2),
7080 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7082 (int_x86_sse42_crc32_32_32 GR32:$src1,
7083 (load addr:$src2)))]>;
7084 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7085 (ins GR32:$src1, GR32:$src2),
7086 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7088 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
7089 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
7090 (ins GR64:$src1, i8mem:$src2),
7091 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7093 (int_x86_sse42_crc32_64_8 GR64:$src1,
7094 (load addr:$src2)))]>,
7096 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
7097 (ins GR64:$src1, GR8:$src2),
7098 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7100 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
7102 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
7103 (ins GR64:$src1, i64mem:$src2),
7104 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7106 (int_x86_sse42_crc32_64_64 GR64:$src1,
7107 (load addr:$src2)))]>,
7109 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
7110 (ins GR64:$src1, GR64:$src2),
7111 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7113 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
7117 //===----------------------------------------------------------------------===//
7118 // AES-NI Instructions
7119 //===----------------------------------------------------------------------===//
7121 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7122 Intrinsic IntId128, bit Is2Addr = 1> {
7123 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7124 (ins VR128:$src1, VR128:$src2),
7126 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7127 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7128 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7130 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7131 (ins VR128:$src1, i128mem:$src2),
7133 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7134 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7136 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7139 // Perform One Round of an AES Encryption/Decryption Flow
7140 let Predicates = [HasAVX, HasAES] in {
7141 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7142 int_x86_aesni_aesenc, 0>, VEX_4V;
7143 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7144 int_x86_aesni_aesenclast, 0>, VEX_4V;
7145 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7146 int_x86_aesni_aesdec, 0>, VEX_4V;
7147 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7148 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7151 let Constraints = "$src1 = $dst" in {
7152 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7153 int_x86_aesni_aesenc>;
7154 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7155 int_x86_aesni_aesenclast>;
7156 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7157 int_x86_aesni_aesdec>;
7158 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7159 int_x86_aesni_aesdeclast>;
7162 // Perform the AES InvMixColumn Transformation
7163 let Predicates = [HasAVX, HasAES] in {
7164 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7166 "vaesimc\t{$src1, $dst|$dst, $src1}",
7168 (int_x86_aesni_aesimc VR128:$src1))]>,
7170 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7171 (ins i128mem:$src1),
7172 "vaesimc\t{$src1, $dst|$dst, $src1}",
7173 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7176 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7178 "aesimc\t{$src1, $dst|$dst, $src1}",
7180 (int_x86_aesni_aesimc VR128:$src1))]>,
7182 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7183 (ins i128mem:$src1),
7184 "aesimc\t{$src1, $dst|$dst, $src1}",
7185 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7188 // AES Round Key Generation Assist
7189 let Predicates = [HasAVX, HasAES] in {
7190 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7191 (ins VR128:$src1, i8imm:$src2),
7192 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7194 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7196 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7197 (ins i128mem:$src1, i8imm:$src2),
7198 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7200 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7203 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7204 (ins VR128:$src1, i8imm:$src2),
7205 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7207 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7209 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7210 (ins i128mem:$src1, i8imm:$src2),
7211 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7213 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7216 //===----------------------------------------------------------------------===//
7217 // PCLMUL Instructions
7218 //===----------------------------------------------------------------------===//
7220 // AVX carry-less Multiplication instructions
7221 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7222 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7223 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7225 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7227 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7228 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7229 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7230 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7231 (memopv2i64 addr:$src2), imm:$src3))]>;
7233 // Carry-less Multiplication instructions
7234 let Constraints = "$src1 = $dst" in {
7235 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7236 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7237 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7239 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7241 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7242 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7243 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7244 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7245 (memopv2i64 addr:$src2), imm:$src3))]>;
7246 } // Constraints = "$src1 = $dst"
7249 multiclass pclmul_alias<string asm, int immop> {
7250 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7251 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7253 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7254 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7256 def : InstAlias<!strconcat("vpclmul", asm,
7257 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7258 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7260 def : InstAlias<!strconcat("vpclmul", asm,
7261 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7262 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7264 defm : pclmul_alias<"hqhq", 0x11>;
7265 defm : pclmul_alias<"hqlq", 0x01>;
7266 defm : pclmul_alias<"lqhq", 0x10>;
7267 defm : pclmul_alias<"lqlq", 0x00>;
7269 //===----------------------------------------------------------------------===//
7270 // SSE4A Instructions
7271 //===----------------------------------------------------------------------===//
7273 let Predicates = [HasSSE4A] in {
7275 let Constraints = "$src = $dst" in {
7276 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7277 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7278 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7279 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7280 imm:$idx))]>, TB, OpSize;
7281 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7282 (ins VR128:$src, VR128:$mask),
7283 "extrq\t{$mask, $src|$src, $mask}",
7284 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7285 VR128:$mask))]>, TB, OpSize;
7287 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7288 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7289 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7290 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7291 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7292 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7293 (ins VR128:$src, VR128:$mask),
7294 "insertq\t{$mask, $src|$src, $mask}",
7295 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7296 VR128:$mask))]>, XD;
7299 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7300 "movntss\t{$src, $dst|$dst, $src}",
7301 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7303 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7304 "movntsd\t{$src, $dst|$dst, $src}",
7305 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7308 //===----------------------------------------------------------------------===//
7310 //===----------------------------------------------------------------------===//
7312 //===----------------------------------------------------------------------===//
7313 // VBROADCAST - Load from memory and broadcast to all elements of the
7314 // destination operand
7316 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7317 X86MemOperand x86memop, Intrinsic Int> :
7318 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7319 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7320 [(set RC:$dst, (Int addr:$src))]>, VEX;
7322 // AVX2 adds register forms
7323 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7325 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7326 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7327 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7329 let ExeDomain = SSEPackedSingle in {
7330 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7331 int_x86_avx_vbroadcast_ss>;
7332 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7333 int_x86_avx_vbroadcast_ss_256>;
7335 let ExeDomain = SSEPackedDouble in
7336 def VBROADCASTSDrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7337 int_x86_avx_vbroadcast_sd_256>;
7338 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7339 int_x86_avx_vbroadcastf128_pd_256>;
7341 let ExeDomain = SSEPackedSingle in {
7342 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7343 int_x86_avx2_vbroadcast_ss_ps>;
7344 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7345 int_x86_avx2_vbroadcast_ss_ps_256>;
7347 let ExeDomain = SSEPackedDouble in
7348 def VBROADCASTSDrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7349 int_x86_avx2_vbroadcast_sd_pd_256>;
7351 let Predicates = [HasAVX2] in
7352 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7353 int_x86_avx2_vbroadcasti128>;
7355 let Predicates = [HasAVX] in
7356 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7357 (VBROADCASTF128 addr:$src)>;
7360 //===----------------------------------------------------------------------===//
7361 // VINSERTF128 - Insert packed floating-point values
7363 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7364 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7365 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7366 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7369 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7370 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7371 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7375 let Predicates = [HasAVX] in {
7376 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7378 (VINSERTF128rr VR256:$src1, VR128:$src2,
7379 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7380 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7382 (VINSERTF128rr VR256:$src1, VR128:$src2,
7383 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7384 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7386 (VINSERTF128rr VR256:$src1, VR128:$src2,
7387 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7388 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7390 (VINSERTF128rr VR256:$src1, VR128:$src2,
7391 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7392 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7394 (VINSERTF128rr VR256:$src1, VR128:$src2,
7395 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7396 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7398 (VINSERTF128rr VR256:$src1, VR128:$src2,
7399 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7401 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7403 (VINSERTF128rm VR256:$src1, addr:$src2,
7404 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7405 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7407 (VINSERTF128rm VR256:$src1, addr:$src2,
7408 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7409 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7411 (VINSERTF128rm VR256:$src1, addr:$src2,
7412 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7415 //===----------------------------------------------------------------------===//
7416 // VEXTRACTF128 - Extract packed floating-point values
7418 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7419 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7420 (ins VR256:$src1, i8imm:$src2),
7421 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7424 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7425 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7426 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7430 // Extract and store.
7431 let Predicates = [HasAVX] in {
7432 def : Pat<(alignedstore (int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2), addr:$dst),
7433 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7434 def : Pat<(alignedstore (int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2), addr:$dst),
7435 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7436 def : Pat<(alignedstore (int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2), addr:$dst),
7437 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7439 def : Pat<(int_x86_sse_storeu_ps addr:$dst, (int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2)),
7440 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7441 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, (int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2)),
7442 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7443 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, (bc_v16i8 (int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2))),
7444 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7448 let Predicates = [HasAVX] in {
7449 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
7450 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7451 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
7452 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7453 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
7454 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7456 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7457 (v4f32 (VEXTRACTF128rr
7458 (v8f32 VR256:$src1),
7459 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7460 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7461 (v2f64 (VEXTRACTF128rr
7462 (v4f64 VR256:$src1),
7463 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7464 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7465 (v2i64 (VEXTRACTF128rr
7466 (v4i64 VR256:$src1),
7467 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7468 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7469 (v4i32 (VEXTRACTF128rr
7470 (v8i32 VR256:$src1),
7471 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7472 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7473 (v8i16 (VEXTRACTF128rr
7474 (v16i16 VR256:$src1),
7475 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7476 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7477 (v16i8 (VEXTRACTF128rr
7478 (v32i8 VR256:$src1),
7479 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7482 //===----------------------------------------------------------------------===//
7483 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7485 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7486 Intrinsic IntLd, Intrinsic IntLd256,
7487 Intrinsic IntSt, Intrinsic IntSt256> {
7488 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7489 (ins VR128:$src1, f128mem:$src2),
7490 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7491 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7493 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7494 (ins VR256:$src1, f256mem:$src2),
7495 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7496 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7498 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7499 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7500 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7501 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7502 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7503 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7504 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7505 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7508 let ExeDomain = SSEPackedSingle in
7509 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7510 int_x86_avx_maskload_ps,
7511 int_x86_avx_maskload_ps_256,
7512 int_x86_avx_maskstore_ps,
7513 int_x86_avx_maskstore_ps_256>;
7514 let ExeDomain = SSEPackedDouble in
7515 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7516 int_x86_avx_maskload_pd,
7517 int_x86_avx_maskload_pd_256,
7518 int_x86_avx_maskstore_pd,
7519 int_x86_avx_maskstore_pd_256>;
7521 //===----------------------------------------------------------------------===//
7522 // VPERMIL - Permute Single and Double Floating-Point Values
7524 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7525 RegisterClass RC, X86MemOperand x86memop_f,
7526 X86MemOperand x86memop_i, PatFrag i_frag,
7527 Intrinsic IntVar, ValueType vt> {
7528 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7529 (ins RC:$src1, RC:$src2),
7530 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7531 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7532 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7533 (ins RC:$src1, x86memop_i:$src2),
7534 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7535 [(set RC:$dst, (IntVar RC:$src1,
7536 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7538 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7539 (ins RC:$src1, i8imm:$src2),
7540 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7541 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7542 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7543 (ins x86memop_f:$src1, i8imm:$src2),
7544 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7546 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7549 let ExeDomain = SSEPackedSingle in {
7550 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7551 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7552 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7553 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>;
7555 let ExeDomain = SSEPackedDouble in {
7556 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7557 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7558 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7559 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>;
7562 let Predicates = [HasAVX] in {
7563 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7564 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7565 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7566 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7567 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7569 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7570 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7571 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7573 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7574 (VPERMILPDri VR128:$src1, imm:$imm)>;
7575 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7576 (VPERMILPDmi addr:$src1, imm:$imm)>;
7579 //===----------------------------------------------------------------------===//
7580 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7582 let ExeDomain = SSEPackedSingle in {
7583 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7584 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7585 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7586 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7587 (i8 imm:$src3))))]>, VEX_4V;
7588 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7589 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7590 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7591 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7592 (i8 imm:$src3)))]>, VEX_4V;
7595 let Predicates = [HasAVX] in {
7596 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7597 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7598 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7599 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7600 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7601 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7602 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7603 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7604 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7605 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7607 def : Pat<(v8f32 (X86VPerm2x128 VR256:$src1,
7608 (memopv8f32 addr:$src2), (i8 imm:$imm))),
7609 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7610 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7611 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7612 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7613 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7614 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7615 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7616 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7617 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7618 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7619 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7620 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7621 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7622 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7623 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7624 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7627 //===----------------------------------------------------------------------===//
7628 // VZERO - Zero YMM registers
7630 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7631 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7632 // Zero All YMM registers
7633 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7634 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7636 // Zero Upper bits of YMM registers
7637 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7638 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7641 //===----------------------------------------------------------------------===//
7642 // Half precision conversion instructions
7643 //===----------------------------------------------------------------------===//
7644 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7645 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7646 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7647 [(set RC:$dst, (Int VR128:$src))]>,
7649 let neverHasSideEffects = 1, mayLoad = 1 in
7650 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7651 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7654 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7655 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7656 (ins RC:$src1, i32i8imm:$src2),
7657 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7658 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7660 let neverHasSideEffects = 1, mayStore = 1 in
7661 def mr : Ii8<0x1D, MRMDestMem, (outs),
7662 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
7663 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7667 let Predicates = [HasAVX, HasF16C] in {
7668 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7669 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>;
7670 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7671 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>;
7674 //===----------------------------------------------------------------------===//
7675 // AVX2 Instructions
7676 //===----------------------------------------------------------------------===//
7678 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7679 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7680 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7681 X86MemOperand x86memop> {
7682 let isCommutable = 1 in
7683 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7684 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7685 !strconcat(OpcodeStr,
7686 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7687 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7689 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7690 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7691 !strconcat(OpcodeStr,
7692 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7695 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7699 let isCommutable = 0 in {
7700 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7701 VR128, memopv2i64, i128mem>;
7702 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7703 VR256, memopv4i64, i256mem>;
7706 //===----------------------------------------------------------------------===//
7707 // VPBROADCAST - Load from memory and broadcast to all elements of the
7708 // destination operand
7710 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7711 X86MemOperand x86memop, PatFrag ld_frag,
7712 Intrinsic Int128, Intrinsic Int256> {
7713 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7714 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7715 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7716 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7717 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7719 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7720 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7721 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7722 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX;
7723 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7724 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7726 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7729 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7730 int_x86_avx2_pbroadcastb_128,
7731 int_x86_avx2_pbroadcastb_256>;
7732 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7733 int_x86_avx2_pbroadcastw_128,
7734 int_x86_avx2_pbroadcastw_256>;
7735 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7736 int_x86_avx2_pbroadcastd_128,
7737 int_x86_avx2_pbroadcastd_256>;
7738 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7739 int_x86_avx2_pbroadcastq_128,
7740 int_x86_avx2_pbroadcastq_256>;
7742 let Predicates = [HasAVX2] in {
7743 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7744 (VPBROADCASTBrm addr:$src)>;
7745 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7746 (VPBROADCASTBYrm addr:$src)>;
7747 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7748 (VPBROADCASTWrm addr:$src)>;
7749 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7750 (VPBROADCASTWYrm addr:$src)>;
7751 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7752 (VPBROADCASTDrm addr:$src)>;
7753 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7754 (VPBROADCASTDYrm addr:$src)>;
7755 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
7756 (VPBROADCASTQrm addr:$src)>;
7757 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7758 (VPBROADCASTQYrm addr:$src)>;
7760 // Provide fallback in case the load node that is used in the patterns above
7761 // is used by additional users, which prevents the pattern selection.
7762 let AddedComplexity = 20 in {
7763 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7765 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss))>;
7766 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7768 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss))>;
7769 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7771 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd))>;
7773 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7775 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss))>;
7776 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7778 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss))>;
7779 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7781 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd))>;
7785 // AVX1 broadcast patterns
7786 let Predicates = [HasAVX] in {
7787 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7788 (VBROADCASTSSYrm addr:$src)>;
7789 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7790 (VBROADCASTSDrm addr:$src)>;
7791 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
7792 (VBROADCASTSSYrm addr:$src)>;
7793 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
7794 (VBROADCASTSDrm addr:$src)>;
7795 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
7796 (VBROADCASTSSrm addr:$src)>;
7797 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7798 (VBROADCASTSSrm addr:$src)>;
7800 // Provide fallback in case the load node that is used in the patterns above
7801 // is used by additional users, which prevents the pattern selection.
7802 let AddedComplexity = 20 in {
7803 // 128bit broadcasts:
7804 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7806 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss), 0)>;
7807 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7808 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
7810 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss), 0),
7813 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss),
7815 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7816 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
7818 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd), 0),
7821 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd),
7824 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7826 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss), 0)>;
7827 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7828 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
7830 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss), 0),
7833 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss),
7835 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7836 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
7838 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd), 0),
7841 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd),
7846 //===----------------------------------------------------------------------===//
7847 // VPERM - Permute instructions
7850 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7852 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7853 (ins VR256:$src1, VR256:$src2),
7854 !strconcat(OpcodeStr,
7855 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7857 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>, VEX_4V;
7858 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7859 (ins VR256:$src1, i256mem:$src2),
7860 !strconcat(OpcodeStr,
7861 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7863 (OpVT (X86VPermv VR256:$src1,
7864 (bitconvert (mem_frag addr:$src2)))))]>,
7868 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, v8i32>;
7869 let ExeDomain = SSEPackedSingle in
7870 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, v8f32>;
7872 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7874 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7875 (ins VR256:$src1, i8imm:$src2),
7876 !strconcat(OpcodeStr,
7877 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7879 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>, VEX;
7880 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
7881 (ins i256mem:$src1, i8imm:$src2),
7882 !strconcat(OpcodeStr,
7883 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7885 (OpVT (X86VPermi (mem_frag addr:$src1),
7886 (i8 imm:$src2))))]>, VEX;
7889 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, v4i64>, VEX_W;
7890 let ExeDomain = SSEPackedDouble in
7891 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, v4f64>, VEX_W;
7893 //===----------------------------------------------------------------------===//
7894 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
7896 let AddedComplexity = 1 in {
7897 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7898 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7899 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7900 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7901 (i8 imm:$src3))))]>, VEX_4V;
7902 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
7903 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7904 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7905 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
7906 (i8 imm:$src3)))]>, VEX_4V;
7909 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7910 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7911 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7912 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7913 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7914 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7915 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7917 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
7919 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7920 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7921 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7922 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7923 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
7925 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7929 //===----------------------------------------------------------------------===//
7930 // VINSERTI128 - Insert packed integer values
7932 let neverHasSideEffects = 1 in {
7933 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7934 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7935 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7938 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
7939 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
7940 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7944 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7945 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7947 (VINSERTI128rr VR256:$src1, VR128:$src2,
7948 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7949 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7951 (VINSERTI128rr VR256:$src1, VR128:$src2,
7952 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7953 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7955 (VINSERTI128rr VR256:$src1, VR128:$src2,
7956 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7957 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7959 (VINSERTI128rr VR256:$src1, VR128:$src2,
7960 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7963 //===----------------------------------------------------------------------===//
7964 // VEXTRACTI128 - Extract packed integer values
7966 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
7967 (ins VR256:$src1, i8imm:$src2),
7968 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7970 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
7972 let neverHasSideEffects = 1, mayStore = 1 in
7973 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
7974 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
7975 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, VEX;
7977 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7978 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7979 (v2i64 (VEXTRACTI128rr
7980 (v4i64 VR256:$src1),
7981 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7982 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7983 (v4i32 (VEXTRACTI128rr
7984 (v8i32 VR256:$src1),
7985 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7986 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7987 (v8i16 (VEXTRACTI128rr
7988 (v16i16 VR256:$src1),
7989 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7990 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7991 (v16i8 (VEXTRACTI128rr
7992 (v32i8 VR256:$src1),
7993 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7996 //===----------------------------------------------------------------------===//
7997 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
7999 multiclass avx2_pmovmask<string OpcodeStr,
8000 Intrinsic IntLd128, Intrinsic IntLd256,
8001 Intrinsic IntSt128, Intrinsic IntSt256> {
8002 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8003 (ins VR128:$src1, i128mem:$src2),
8004 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8005 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8006 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8007 (ins VR256:$src1, i256mem:$src2),
8008 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8009 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>, VEX_4V;
8010 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8011 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8012 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8013 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8014 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8015 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8016 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8017 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
8020 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8021 int_x86_avx2_maskload_d,
8022 int_x86_avx2_maskload_d_256,
8023 int_x86_avx2_maskstore_d,
8024 int_x86_avx2_maskstore_d_256>;
8025 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8026 int_x86_avx2_maskload_q,
8027 int_x86_avx2_maskload_q_256,
8028 int_x86_avx2_maskstore_q,
8029 int_x86_avx2_maskstore_q_256>, VEX_W;
8032 //===----------------------------------------------------------------------===//
8033 // Variable Bit Shifts
8035 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8036 ValueType vt128, ValueType vt256> {
8037 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8038 (ins VR128:$src1, VR128:$src2),
8039 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8041 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8043 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8044 (ins VR128:$src1, i128mem:$src2),
8045 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8047 (vt128 (OpNode VR128:$src1,
8048 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
8050 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8051 (ins VR256:$src1, VR256:$src2),
8052 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8054 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8056 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8057 (ins VR256:$src1, i256mem:$src2),
8058 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8060 (vt256 (OpNode VR256:$src1,
8061 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
8065 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8066 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8067 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8068 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8069 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;