1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_DEFAULT, d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
80 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
81 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
82 string OpcodeStr, X86MemOperand x86memop,
83 list<dag> pat_rr, list<dag> pat_rm,
85 bit rr_hasSideEffects = 0> {
86 let isCommutable = 1, neverHasSideEffects = rr_hasSideEffects in
87 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
89 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
90 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
91 pat_rr, IIC_DEFAULT, d>;
92 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
94 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
95 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
96 pat_rm, IIC_DEFAULT, d>;
99 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
100 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
101 string asm, string SSEVer, string FPSizeStr,
102 X86MemOperand x86memop, PatFrag mem_frag,
103 Domain d, bit Is2Addr = 1> {
104 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
106 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
107 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
108 [(set RC:$dst, (!cast<Intrinsic>(
109 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
110 RC:$src1, RC:$src2))], IIC_DEFAULT, d>;
111 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
113 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
114 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
115 [(set RC:$dst, (!cast<Intrinsic>(
116 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
117 RC:$src1, (mem_frag addr:$src2)))], IIC_DEFAULT, d>;
120 //===----------------------------------------------------------------------===//
121 // Non-instruction patterns
122 //===----------------------------------------------------------------------===//
124 // A vector extract of the first f32/f64 position is a subregister copy
125 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
126 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
127 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
128 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
130 // A 128-bit subvector extract from the first 256-bit vector position
131 // is a subregister copy that needs no instruction.
132 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
133 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
134 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
135 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
137 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
138 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
139 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
140 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
142 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
143 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
144 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
145 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
147 // A 128-bit subvector insert to the first 256-bit vector position
148 // is a subregister copy that needs no instruction.
149 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
150 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
151 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
152 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
153 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
154 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
155 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
156 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
157 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
158 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
159 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
160 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
162 // Implicitly promote a 32-bit scalar to a vector.
163 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
164 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
165 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
166 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
167 // Implicitly promote a 64-bit scalar to a vector.
168 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
169 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
170 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
171 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
173 // Bitcasts between 128-bit vector types. Return the original type since
174 // no instruction is needed for the conversion
175 let Predicates = [HasSSE2] in {
176 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
177 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
178 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
179 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
180 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
181 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
182 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
183 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
184 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
185 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
186 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
187 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
188 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
189 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
190 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
191 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
192 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
193 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
194 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
195 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
196 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
197 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
198 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
199 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
200 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
201 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
202 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
203 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
204 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
205 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
208 // Bitcasts between 256-bit vector types. Return the original type since
209 // no instruction is needed for the conversion
210 let Predicates = [HasAVX] in {
211 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
212 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
213 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
214 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
215 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
216 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
217 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
218 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
219 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
220 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
221 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
222 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
223 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
224 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
225 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
226 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
227 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
228 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
229 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
230 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
231 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
232 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
233 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
234 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
235 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
236 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
237 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
238 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
239 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
240 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
243 // Alias instructions that map fld0 to pxor for sse.
244 // This is expanded by ExpandPostRAPseudos.
245 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
247 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
248 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
249 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
250 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
253 //===----------------------------------------------------------------------===//
254 // AVX & SSE - Zero/One Vectors
255 //===----------------------------------------------------------------------===//
257 // Alias instruction that maps zero vector to pxor / xorp* for sse.
258 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
259 // swizzled by ExecutionDepsFix to pxor.
260 // We set canFoldAsLoad because this can be converted to a constant-pool
261 // load of an all-zeros value if folding it would be beneficial.
262 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
263 isPseudo = 1, neverHasSideEffects = 1 in {
264 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "", []>;
267 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
268 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
269 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
270 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
271 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
272 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
275 // The same as done above but for AVX. The 256-bit ISA does not support PI,
276 // and doesn't need it because on sandy bridge the register is set to zero
277 // at the rename stage without using any execution unit, so SET0PSY
278 // and SET0PDY can be used for vector int instructions without penalty
279 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
280 // JIT implementatioan, it does not expand the instructions below like
281 // X86MCInstLower does.
282 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
283 isCodeGenOnly = 1 in {
284 let Predicates = [HasAVX] in {
285 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
286 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
287 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
288 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
290 let Predicates = [HasAVX2], neverHasSideEffects = 1 in
291 def AVX2_SET0 : PDI<0xef, MRMInitReg, (outs VR256:$dst), (ins), "",
295 let Predicates = [HasAVX2], AddedComplexity = 5 in {
296 def : Pat<(v4i64 immAllZerosV), (AVX2_SET0)>;
297 def : Pat<(v8i32 immAllZerosV), (AVX2_SET0)>;
298 def : Pat<(v16i16 immAllZerosV), (AVX2_SET0)>;
299 def : Pat<(v32i8 immAllZerosV), (AVX2_SET0)>;
302 // AVX has no support for 256-bit integer instructions, but since the 128-bit
303 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
304 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
305 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
306 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
308 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
309 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
310 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
312 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
313 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
314 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
316 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
317 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
318 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
320 // We set canFoldAsLoad because this can be converted to a constant-pool
321 // load of an all-ones value if folding it would be beneficial.
322 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
323 // JIT implementation, it does not expand the instructions below like
324 // X86MCInstLower does.
325 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
326 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in {
327 let Predicates = [HasAVX] in
328 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
329 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
330 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
331 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
332 let Predicates = [HasAVX2] in
333 def AVX2_SETALLONES : PDI<0x76, MRMInitReg, (outs VR256:$dst), (ins), "",
334 [(set VR256:$dst, (v8i32 immAllOnesV))]>, VEX_4V;
338 //===----------------------------------------------------------------------===//
339 // SSE 1 & 2 - Move FP Scalar Instructions
341 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
342 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
343 // is used instead. Register-to-register movss/movsd is not modeled as an
344 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
345 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
346 //===----------------------------------------------------------------------===//
348 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
349 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
350 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
352 // Loading from memory automatically zeroing upper bits.
353 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
354 PatFrag mem_pat, string OpcodeStr> :
355 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
356 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
357 [(set RC:$dst, (mem_pat addr:$src))]>;
360 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
361 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
363 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
364 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
367 // For the disassembler
368 let isCodeGenOnly = 1 in {
369 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
370 (ins VR128:$src1, FR32:$src2),
371 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
373 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
374 (ins VR128:$src1, FR64:$src2),
375 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
379 let canFoldAsLoad = 1, isReMaterializable = 1 in {
380 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
382 let AddedComplexity = 20 in
383 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
387 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
388 "movss\t{$src, $dst|$dst, $src}",
389 [(store FR32:$src, addr:$dst)]>, XS, VEX, VEX_LIG;
390 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
391 "movsd\t{$src, $dst|$dst, $src}",
392 [(store FR64:$src, addr:$dst)]>, XD, VEX, VEX_LIG;
395 let Constraints = "$src1 = $dst" in {
396 def MOVSSrr : sse12_move_rr<FR32, v4f32,
397 "movss\t{$src2, $dst|$dst, $src2}">, XS;
398 def MOVSDrr : sse12_move_rr<FR64, v2f64,
399 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
401 // For the disassembler
402 let isCodeGenOnly = 1 in {
403 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
404 (ins VR128:$src1, FR32:$src2),
405 "movss\t{$src2, $dst|$dst, $src2}", []>, XS;
406 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
407 (ins VR128:$src1, FR64:$src2),
408 "movsd\t{$src2, $dst|$dst, $src2}", []>, XD;
412 let canFoldAsLoad = 1, isReMaterializable = 1 in {
413 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
415 let AddedComplexity = 20 in
416 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
419 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
420 "movss\t{$src, $dst|$dst, $src}",
421 [(store FR32:$src, addr:$dst)]>;
422 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
423 "movsd\t{$src, $dst|$dst, $src}",
424 [(store FR64:$src, addr:$dst)]>;
427 let Predicates = [HasAVX] in {
428 let AddedComplexity = 15 in {
429 // Extract the low 32-bit value from one vector and insert it into another.
430 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
431 (VMOVSSrr (v4f32 VR128:$src1),
432 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
433 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
434 (VMOVSSrr (v4i32 VR128:$src1),
435 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
437 // Extract the low 64-bit value from one vector and insert it into another.
438 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
439 (VMOVSDrr (v2f64 VR128:$src1),
440 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
441 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
442 (VMOVSDrr (v2i64 VR128:$src1),
443 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
445 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
446 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
447 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
448 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
449 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
451 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
452 // MOVS{S,D} to the lower bits.
453 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
454 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
455 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
456 (VMOVSSrr (v4f32 (V_SET0)),
457 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
458 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
459 (VMOVSSrr (v4i32 (V_SET0)),
460 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
461 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
462 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
464 // Move low f32 and clear high bits.
465 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
466 (SUBREG_TO_REG (i32 0),
467 (VMOVSSrr (v4f32 (V_SET0)),
468 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_ss)), sub_xmm)>;
469 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
470 (SUBREG_TO_REG (i32 0),
471 (VMOVSSrr (v4i32 (V_SET0)),
472 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_ss)), sub_xmm)>;
475 let AddedComplexity = 20 in {
476 // MOVSSrm zeros the high parts of the register; represent this
477 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
478 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
479 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
480 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
481 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
482 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
483 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
485 // MOVSDrm zeros the high parts of the register; represent this
486 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
487 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
488 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
489 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
490 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
491 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
492 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
493 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
494 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
495 def : Pat<(v2f64 (X86vzload addr:$src)),
496 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
498 // Represent the same patterns above but in the form they appear for
500 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
501 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (i32 0)))),
502 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
503 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
504 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
505 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
506 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
507 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
508 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
510 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
511 (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
512 (SUBREG_TO_REG (i32 0),
513 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
515 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
516 (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
517 (SUBREG_TO_REG (i64 0),
518 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
520 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
521 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (i32 0)))),
522 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
524 // Move low f64 and clear high bits.
525 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
526 (SUBREG_TO_REG (i32 0),
527 (VMOVSDrr (v2f64 (V_SET0)),
528 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_sd)), sub_xmm)>;
530 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
531 (SUBREG_TO_REG (i32 0),
532 (VMOVSDrr (v2i64 (V_SET0)),
533 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_sd)), sub_xmm)>;
535 // Extract and store.
536 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
539 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
540 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
543 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
545 // Shuffle with VMOVSS
546 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
547 (VMOVSSrr VR128:$src1, FR32:$src2)>;
548 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
549 (VMOVSSrr (v4i32 VR128:$src1),
550 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
551 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
552 (VMOVSSrr (v4f32 VR128:$src1),
553 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
556 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
557 (SUBREG_TO_REG (i32 0),
558 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_ss),
559 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_ss)), sub_xmm)>;
560 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
561 (SUBREG_TO_REG (i32 0),
562 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_ss),
563 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_ss)), sub_xmm)>;
565 // Shuffle with VMOVSD
566 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
567 (VMOVSDrr VR128:$src1, FR64:$src2)>;
568 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
569 (VMOVSDrr (v2i64 VR128:$src1),
570 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
571 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
572 (VMOVSDrr (v2f64 VR128:$src1),
573 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
574 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
575 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
577 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
578 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
582 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
583 (SUBREG_TO_REG (i32 0),
584 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_sd),
585 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_sd)), sub_xmm)>;
586 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
587 (SUBREG_TO_REG (i32 0),
588 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_sd),
589 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_sd)), sub_xmm)>;
592 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
593 // is during lowering, where it's not possible to recognize the fold cause
594 // it has two uses through a bitcast. One use disappears at isel time and the
595 // fold opportunity reappears.
596 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
597 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),
599 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
600 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),
602 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
603 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
605 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
606 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
610 let Predicates = [HasSSE1] in {
611 let AddedComplexity = 15 in {
612 // Extract the low 32-bit value from one vector and insert it into another.
613 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
614 (MOVSSrr (v4f32 VR128:$src1),
615 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
616 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
617 (MOVSSrr (v4i32 VR128:$src1),
618 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
620 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
621 // MOVSS to the lower bits.
622 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
623 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
624 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
625 (MOVSSrr (v4f32 (V_SET0)),
626 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
627 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
628 (MOVSSrr (v4i32 (V_SET0)),
629 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
632 let AddedComplexity = 20 in {
633 // MOVSSrm zeros the high parts of the register; represent this
634 // with SUBREG_TO_REG.
635 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
636 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
637 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
638 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
639 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
640 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
643 // Extract and store.
644 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
647 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
649 // Shuffle with MOVSS
650 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
651 (MOVSSrr VR128:$src1, FR32:$src2)>;
652 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
653 (MOVSSrr (v4i32 VR128:$src1),
654 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
655 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
656 (MOVSSrr (v4f32 VR128:$src1),
657 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
660 let Predicates = [HasSSE2] in {
661 let AddedComplexity = 15 in {
662 // Extract the low 64-bit value from one vector and insert it into another.
663 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
664 (MOVSDrr (v2f64 VR128:$src1),
665 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
666 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
667 (MOVSDrr (v2i64 VR128:$src1),
668 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
670 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
671 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
672 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
673 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
674 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
676 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
677 // MOVSD to the lower bits.
678 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
679 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
682 let AddedComplexity = 20 in {
683 // MOVSDrm zeros the high parts of the register; represent this
684 // with SUBREG_TO_REG.
685 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
686 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
687 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
688 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
689 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
690 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
691 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
692 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
693 def : Pat<(v2f64 (X86vzload addr:$src)),
694 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
697 // Extract and store.
698 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
701 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
703 // Shuffle with MOVSD
704 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
705 (MOVSDrr VR128:$src1, FR64:$src2)>;
706 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
707 (MOVSDrr (v2i64 VR128:$src1),
708 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
709 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
710 (MOVSDrr (v2f64 VR128:$src1),
711 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
712 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
713 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
714 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
715 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
717 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
718 // is during lowering, where it's not possible to recognize the fold cause
719 // it has two uses through a bitcast. One use disappears at isel time and the
720 // fold opportunity reappears.
721 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
722 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),sub_sd))>;
723 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
724 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),sub_sd))>;
725 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
726 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
727 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
728 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
731 //===----------------------------------------------------------------------===//
732 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
733 //===----------------------------------------------------------------------===//
735 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
736 X86MemOperand x86memop, PatFrag ld_frag,
737 string asm, Domain d,
738 bit IsReMaterializable = 1> {
739 let neverHasSideEffects = 1 in
740 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
741 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], IIC_DEFAULT, d>;
742 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
743 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
744 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
745 [(set RC:$dst, (ld_frag addr:$src))], IIC_DEFAULT, d>;
748 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
749 "movaps", SSEPackedSingle>, TB, VEX;
750 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
751 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
752 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
753 "movups", SSEPackedSingle>, TB, VEX;
754 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
755 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
757 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
758 "movaps", SSEPackedSingle>, TB, VEX;
759 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
760 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
761 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
762 "movups", SSEPackedSingle>, TB, VEX;
763 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
764 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
765 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
766 "movaps", SSEPackedSingle>, TB;
767 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
768 "movapd", SSEPackedDouble>, TB, OpSize;
769 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
770 "movups", SSEPackedSingle>, TB;
771 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
772 "movupd", SSEPackedDouble, 0>, TB, OpSize;
774 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
775 "movaps\t{$src, $dst|$dst, $src}",
776 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
777 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
778 "movapd\t{$src, $dst|$dst, $src}",
779 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
780 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
781 "movups\t{$src, $dst|$dst, $src}",
782 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
783 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
784 "movupd\t{$src, $dst|$dst, $src}",
785 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
786 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
787 "movaps\t{$src, $dst|$dst, $src}",
788 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)]>, VEX;
789 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
790 "movapd\t{$src, $dst|$dst, $src}",
791 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)]>, VEX;
792 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
793 "movups\t{$src, $dst|$dst, $src}",
794 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
795 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
796 "movupd\t{$src, $dst|$dst, $src}",
797 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
800 let isCodeGenOnly = 1 in {
801 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
803 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
804 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
806 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
807 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
809 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
810 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
812 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
813 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
815 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
816 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
818 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
819 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
821 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
822 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
824 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
827 let Predicates = [HasAVX] in {
828 def : Pat<(v8i32 (X86vzmovl
829 (insert_subvector undef, (v4i32 VR128:$src), (i32 0)))),
830 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
831 def : Pat<(v4i64 (X86vzmovl
832 (insert_subvector undef, (v2i64 VR128:$src), (i32 0)))),
833 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
834 def : Pat<(v8f32 (X86vzmovl
835 (insert_subvector undef, (v4f32 VR128:$src), (i32 0)))),
836 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
837 def : Pat<(v4f64 (X86vzmovl
838 (insert_subvector undef, (v2f64 VR128:$src), (i32 0)))),
839 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
843 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
844 (VMOVUPSYmr addr:$dst, VR256:$src)>;
845 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
846 (VMOVUPDYmr addr:$dst, VR256:$src)>;
848 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
849 "movaps\t{$src, $dst|$dst, $src}",
850 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
851 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
852 "movapd\t{$src, $dst|$dst, $src}",
853 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
854 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
855 "movups\t{$src, $dst|$dst, $src}",
856 [(store (v4f32 VR128:$src), addr:$dst)]>;
857 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
858 "movupd\t{$src, $dst|$dst, $src}",
859 [(store (v2f64 VR128:$src), addr:$dst)]>;
862 let isCodeGenOnly = 1 in {
863 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
864 "movaps\t{$src, $dst|$dst, $src}", []>;
865 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
866 "movapd\t{$src, $dst|$dst, $src}", []>;
867 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
868 "movups\t{$src, $dst|$dst, $src}", []>;
869 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
870 "movupd\t{$src, $dst|$dst, $src}", []>;
873 let Predicates = [HasAVX] in {
874 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
875 (VMOVUPSmr addr:$dst, VR128:$src)>;
876 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
877 (VMOVUPDmr addr:$dst, VR128:$src)>;
880 let Predicates = [HasSSE1] in
881 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
882 (MOVUPSmr addr:$dst, VR128:$src)>;
883 let Predicates = [HasSSE2] in
884 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
885 (MOVUPDmr addr:$dst, VR128:$src)>;
887 // Use vmovaps/vmovups for AVX integer load/store.
888 let Predicates = [HasAVX] in {
889 // 128-bit load/store
890 def : Pat<(alignedloadv2i64 addr:$src),
891 (VMOVAPSrm addr:$src)>;
892 def : Pat<(loadv2i64 addr:$src),
893 (VMOVUPSrm addr:$src)>;
895 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
896 (VMOVAPSmr addr:$dst, VR128:$src)>;
897 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
898 (VMOVAPSmr addr:$dst, VR128:$src)>;
899 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
900 (VMOVAPSmr addr:$dst, VR128:$src)>;
901 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
902 (VMOVAPSmr addr:$dst, VR128:$src)>;
903 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
904 (VMOVUPSmr addr:$dst, VR128:$src)>;
905 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
906 (VMOVUPSmr addr:$dst, VR128:$src)>;
907 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
908 (VMOVUPSmr addr:$dst, VR128:$src)>;
909 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
910 (VMOVUPSmr addr:$dst, VR128:$src)>;
912 // 256-bit load/store
913 def : Pat<(alignedloadv4i64 addr:$src),
914 (VMOVAPSYrm addr:$src)>;
915 def : Pat<(loadv4i64 addr:$src),
916 (VMOVUPSYrm addr:$src)>;
917 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
918 (VMOVAPSYmr addr:$dst, VR256:$src)>;
919 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
920 (VMOVAPSYmr addr:$dst, VR256:$src)>;
921 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
922 (VMOVAPSYmr addr:$dst, VR256:$src)>;
923 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
924 (VMOVAPSYmr addr:$dst, VR256:$src)>;
925 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
926 (VMOVUPSYmr addr:$dst, VR256:$src)>;
927 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
928 (VMOVUPSYmr addr:$dst, VR256:$src)>;
929 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
930 (VMOVUPSYmr addr:$dst, VR256:$src)>;
931 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
932 (VMOVUPSYmr addr:$dst, VR256:$src)>;
935 // Use movaps / movups for SSE integer load / store (one byte shorter).
936 // The instructions selected below are then converted to MOVDQA/MOVDQU
937 // during the SSE domain pass.
938 let Predicates = [HasSSE1] in {
939 def : Pat<(alignedloadv2i64 addr:$src),
940 (MOVAPSrm addr:$src)>;
941 def : Pat<(loadv2i64 addr:$src),
942 (MOVUPSrm addr:$src)>;
944 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
945 (MOVAPSmr addr:$dst, VR128:$src)>;
946 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
947 (MOVAPSmr addr:$dst, VR128:$src)>;
948 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
949 (MOVAPSmr addr:$dst, VR128:$src)>;
950 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
951 (MOVAPSmr addr:$dst, VR128:$src)>;
952 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
953 (MOVUPSmr addr:$dst, VR128:$src)>;
954 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
955 (MOVUPSmr addr:$dst, VR128:$src)>;
956 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
957 (MOVUPSmr addr:$dst, VR128:$src)>;
958 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
959 (MOVUPSmr addr:$dst, VR128:$src)>;
962 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
963 // bits are disregarded. FIXME: Set encoding to pseudo!
964 let neverHasSideEffects = 1 in {
965 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
966 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
967 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
968 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
969 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
970 "movaps\t{$src, $dst|$dst, $src}", []>;
971 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
972 "movapd\t{$src, $dst|$dst, $src}", []>;
975 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
976 // bits are disregarded. FIXME: Set encoding to pseudo!
977 let canFoldAsLoad = 1, isReMaterializable = 1 in {
978 let isCodeGenOnly = 1 in {
979 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
980 "movaps\t{$src, $dst|$dst, $src}",
981 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>, VEX;
982 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
983 "movapd\t{$src, $dst|$dst, $src}",
984 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>, VEX;
986 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
987 "movaps\t{$src, $dst|$dst, $src}",
988 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
989 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
990 "movapd\t{$src, $dst|$dst, $src}",
991 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
994 //===----------------------------------------------------------------------===//
995 // SSE 1 & 2 - Move Low packed FP Instructions
996 //===----------------------------------------------------------------------===//
998 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
999 PatFrag mov_frag, string base_opc,
1001 def PSrm : PI<opc, MRMSrcMem,
1002 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1003 !strconcat(base_opc, "s", asm_opr),
1006 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1007 IIC_DEFAULT, SSEPackedSingle>, TB;
1009 def PDrm : PI<opc, MRMSrcMem,
1010 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
1011 !strconcat(base_opc, "d", asm_opr),
1012 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
1013 (scalar_to_vector (loadf64 addr:$src2)))))],
1014 IIC_DEFAULT, SSEPackedDouble>, TB, OpSize;
1017 let AddedComplexity = 20 in {
1018 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
1019 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
1021 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1022 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
1023 "\t{$src2, $dst|$dst, $src2}">;
1026 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1027 "movlps\t{$src, $dst|$dst, $src}",
1028 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1029 (iPTR 0))), addr:$dst)]>, VEX;
1030 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1031 "movlpd\t{$src, $dst|$dst, $src}",
1032 [(store (f64 (vector_extract (v2f64 VR128:$src),
1033 (iPTR 0))), addr:$dst)]>, VEX;
1034 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1035 "movlps\t{$src, $dst|$dst, $src}",
1036 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1037 (iPTR 0))), addr:$dst)]>;
1038 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1039 "movlpd\t{$src, $dst|$dst, $src}",
1040 [(store (f64 (vector_extract (v2f64 VR128:$src),
1041 (iPTR 0))), addr:$dst)]>;
1043 let Predicates = [HasAVX] in {
1044 let AddedComplexity = 20 in {
1045 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
1046 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
1047 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1048 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
1049 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1050 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
1051 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
1052 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1053 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
1054 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1057 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1058 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1059 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1060 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
1061 VR128:$src2)), addr:$src1),
1062 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1064 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
1065 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1066 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1067 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1068 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1070 // Shuffle with VMOVLPS
1071 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1072 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1073 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1074 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1075 def : Pat<(X86Movlps VR128:$src1,
1076 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1077 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1079 // Shuffle with VMOVLPD
1080 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1081 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1082 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1083 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1084 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1085 (scalar_to_vector (loadf64 addr:$src2)))),
1086 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1089 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1091 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1092 def : Pat<(store (v4i32 (X86Movlps
1093 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1094 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1095 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1097 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1098 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1100 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1103 let Predicates = [HasSSE1] in {
1104 let AddedComplexity = 20 in {
1105 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
1106 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
1107 (MOVLPSrm VR128:$src1, addr:$src2)>;
1108 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
1109 (MOVLPSrm VR128:$src1, addr:$src2)>;
1112 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1113 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1114 (iPTR 0))), addr:$src1),
1115 (MOVLPSmr addr:$src1, VR128:$src2)>;
1116 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1117 (MOVLPSmr addr:$src1, VR128:$src2)>;
1118 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
1119 VR128:$src2)), addr:$src1),
1120 (MOVLPSmr addr:$src1, VR128:$src2)>;
1122 // Shuffle with MOVLPS
1123 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1124 (MOVLPSrm VR128:$src1, addr:$src2)>;
1125 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1126 (MOVLPSrm VR128:$src1, addr:$src2)>;
1127 def : Pat<(X86Movlps VR128:$src1,
1128 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1129 (MOVLPSrm VR128:$src1, addr:$src2)>;
1130 def : Pat<(X86Movlps VR128:$src1,
1131 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1132 (MOVLPSrm VR128:$src1, addr:$src2)>;
1135 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1137 (MOVLPSmr addr:$src1, VR128:$src2)>;
1138 def : Pat<(store (v4i32 (X86Movlps
1139 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1141 (MOVLPSmr addr:$src1, VR128:$src2)>;
1144 let Predicates = [HasSSE2] in {
1145 let AddedComplexity = 20 in {
1146 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
1147 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
1148 (MOVLPDrm VR128:$src1, addr:$src2)>;
1149 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
1150 (MOVLPDrm VR128:$src1, addr:$src2)>;
1153 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
1154 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1155 (MOVLPDmr addr:$src1, VR128:$src2)>;
1156 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1157 (MOVLPDmr addr:$src1, VR128:$src2)>;
1159 // Shuffle with MOVLPD
1160 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1161 (MOVLPDrm VR128:$src1, addr:$src2)>;
1162 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1163 (MOVLPDrm VR128:$src1, addr:$src2)>;
1164 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1165 (scalar_to_vector (loadf64 addr:$src2)))),
1166 (MOVLPDrm VR128:$src1, addr:$src2)>;
1169 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1171 (MOVLPDmr addr:$src1, VR128:$src2)>;
1172 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1174 (MOVLPDmr addr:$src1, VR128:$src2)>;
1177 //===----------------------------------------------------------------------===//
1178 // SSE 1 & 2 - Move Hi packed FP Instructions
1179 //===----------------------------------------------------------------------===//
1181 let AddedComplexity = 20 in {
1182 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1183 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
1185 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1186 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1187 "\t{$src2, $dst|$dst, $src2}">;
1190 // v2f64 extract element 1 is always custom lowered to unpack high to low
1191 // and extract element 0 so the non-store version isn't too horrible.
1192 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1193 "movhps\t{$src, $dst|$dst, $src}",
1194 [(store (f64 (vector_extract
1195 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1196 (undef)), (iPTR 0))), addr:$dst)]>,
1198 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1199 "movhpd\t{$src, $dst|$dst, $src}",
1200 [(store (f64 (vector_extract
1201 (v2f64 (unpckh VR128:$src, (undef))),
1202 (iPTR 0))), addr:$dst)]>,
1204 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1205 "movhps\t{$src, $dst|$dst, $src}",
1206 [(store (f64 (vector_extract
1207 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1208 (undef)), (iPTR 0))), addr:$dst)]>;
1209 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1210 "movhpd\t{$src, $dst|$dst, $src}",
1211 [(store (f64 (vector_extract
1212 (v2f64 (unpckh VR128:$src, (undef))),
1213 (iPTR 0))), addr:$dst)]>;
1215 let Predicates = [HasAVX] in {
1217 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1218 (VMOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1219 def : Pat<(X86Movlhps VR128:$src1,
1220 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1221 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1222 def : Pat<(X86Movlhps VR128:$src1,
1223 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1224 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(X86Movlhps VR128:$src1,
1226 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1227 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1229 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1230 // is during lowering, where it's not possible to recognize the load fold
1231 // cause it has two uses through a bitcast. One use disappears at isel time
1232 // and the fold opportunity reappears.
1233 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1234 (scalar_to_vector (loadf64 addr:$src2)))),
1235 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1237 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1238 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1239 (scalar_to_vector (loadf64 addr:$src2)))),
1240 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1243 def : Pat<(store (f64 (vector_extract
1244 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1245 (bc_v2f64 (v4f32 VR128:$src))), (iPTR 0))), addr:$dst),
1246 (VMOVHPSmr addr:$dst, VR128:$src)>;
1247 def : Pat<(store (f64 (vector_extract
1248 (v2f64 (X86Unpckh VR128:$src, VR128:$src)), (iPTR 0))), addr:$dst),
1249 (VMOVHPDmr addr:$dst, VR128:$src)>;
1252 let Predicates = [HasSSE1] in {
1254 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1255 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1256 def : Pat<(X86Movlhps VR128:$src1,
1257 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1258 (MOVHPSrm VR128:$src1, addr:$src2)>;
1259 def : Pat<(X86Movlhps VR128:$src1,
1260 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1261 (MOVHPSrm VR128:$src1, addr:$src2)>;
1262 def : Pat<(X86Movlhps VR128:$src1,
1263 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1264 (MOVHPSrm VR128:$src1, addr:$src2)>;
1267 def : Pat<(store (f64 (vector_extract
1268 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1269 (bc_v2f64 (v4f32 VR128:$src))), (iPTR 0))), addr:$dst),
1270 (MOVHPSmr addr:$dst, VR128:$src)>;
1273 let Predicates = [HasSSE2] in {
1274 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1275 // is during lowering, where it's not possible to recognize the load fold
1276 // cause it has two uses through a bitcast. One use disappears at isel time
1277 // and the fold opportunity reappears.
1278 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1279 (scalar_to_vector (loadf64 addr:$src2)))),
1280 (MOVHPDrm VR128:$src1, addr:$src2)>;
1282 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1283 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1284 (scalar_to_vector (loadf64 addr:$src2)))),
1285 (MOVHPDrm VR128:$src1, addr:$src2)>;
1288 def : Pat<(store (f64 (vector_extract
1289 (v2f64 (X86Unpckh VR128:$src, VR128:$src)), (iPTR 0))),addr:$dst),
1290 (MOVHPDmr addr:$dst, VR128:$src)>;
1293 //===----------------------------------------------------------------------===//
1294 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1295 //===----------------------------------------------------------------------===//
1297 let AddedComplexity = 20 in {
1298 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1299 (ins VR128:$src1, VR128:$src2),
1300 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1302 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))]>,
1304 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1305 (ins VR128:$src1, VR128:$src2),
1306 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1308 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))]>,
1311 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1312 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1313 (ins VR128:$src1, VR128:$src2),
1314 "movlhps\t{$src2, $dst|$dst, $src2}",
1316 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))]>;
1317 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1318 (ins VR128:$src1, VR128:$src2),
1319 "movhlps\t{$src2, $dst|$dst, $src2}",
1321 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))]>;
1324 let Predicates = [HasAVX] in {
1326 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1327 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1328 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1329 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1332 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1333 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1336 let Predicates = [HasSSE1] in {
1338 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1339 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1340 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1341 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1344 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1345 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1348 //===----------------------------------------------------------------------===//
1349 // SSE 1 & 2 - Conversion Instructions
1350 //===----------------------------------------------------------------------===//
1352 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1353 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1355 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1356 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
1357 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1358 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
1361 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1362 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1363 string asm, Domain d> {
1364 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1365 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1367 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1368 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1372 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1373 X86MemOperand x86memop, string asm> {
1374 let neverHasSideEffects = 1 in {
1375 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1376 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1378 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1379 (ins DstRC:$src1, x86memop:$src),
1380 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1381 } // neverHasSideEffects = 1
1384 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1385 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1387 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1388 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1390 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1391 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX,
1393 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1394 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
1395 VEX, VEX_W, VEX_LIG;
1397 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1398 // register, but the same isn't true when only using memory operands,
1399 // provide other assembly "l" and "q" forms to address this explicitly
1400 // where appropriate to do so.
1401 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
1403 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
1404 VEX_4V, VEX_W, VEX_LIG;
1405 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
1407 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
1409 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
1410 VEX_4V, VEX_W, VEX_LIG;
1412 let Predicates = [HasAVX], AddedComplexity = 1 in {
1413 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1414 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1415 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1416 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1417 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1418 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1419 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1420 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1422 def : Pat<(f32 (sint_to_fp GR32:$src)),
1423 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1424 def : Pat<(f32 (sint_to_fp GR64:$src)),
1425 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1426 def : Pat<(f64 (sint_to_fp GR32:$src)),
1427 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1428 def : Pat<(f64 (sint_to_fp GR64:$src)),
1429 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1432 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1433 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
1434 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1435 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1436 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1437 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
1438 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1439 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1440 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1441 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
1442 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1443 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1444 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1445 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
1446 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1447 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1449 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1450 // and/or XMM operand(s).
1452 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1453 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
1455 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1456 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1457 [(set DstRC:$dst, (Int SrcRC:$src))]>;
1458 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
1459 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1460 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
1463 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1464 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1465 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
1466 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1468 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1469 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1470 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
1471 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1472 (ins DstRC:$src1, x86memop:$src2),
1474 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1475 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1476 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
1479 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1480 f128mem, load, "cvtsd2si">, XD, VEX, VEX_LIG;
1481 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1482 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
1483 XD, VEX, VEX_W, VEX_LIG;
1485 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1486 f128mem, load, "cvtsd2si{l}">, XD;
1487 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1488 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
1491 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1492 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
1493 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1494 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
1496 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1497 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
1498 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1499 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
1502 let Constraints = "$src1 = $dst" in {
1503 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1504 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1506 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1507 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1508 "cvtsi2ss{q}">, XS, REX_W;
1509 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1510 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1512 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1513 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1514 "cvtsi2sd">, XD, REX_W;
1519 // Aliases for intrinsics
1520 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1521 f32mem, load, "cvttss2si">, XS, VEX;
1522 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1523 int_x86_sse_cvttss2si64, f32mem, load,
1524 "cvttss2si">, XS, VEX, VEX_W;
1525 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1526 f128mem, load, "cvttsd2si">, XD, VEX;
1527 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1528 int_x86_sse2_cvttsd2si64, f128mem, load,
1529 "cvttsd2si">, XD, VEX, VEX_W;
1530 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1531 f32mem, load, "cvttss2si">, XS;
1532 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1533 int_x86_sse_cvttss2si64, f32mem, load,
1534 "cvttss2si{q}">, XS, REX_W;
1535 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1536 f128mem, load, "cvttsd2si">, XD;
1537 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1538 int_x86_sse2_cvttsd2si64, f128mem, load,
1539 "cvttsd2si{q}">, XD, REX_W;
1541 let Pattern = []<dag> in {
1542 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
1543 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS,
1545 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
1546 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1548 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
1549 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1550 SSEPackedSingle>, TB, VEX;
1551 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
1552 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1553 SSEPackedSingle>, TB, VEX;
1556 let Pattern = []<dag> in {
1557 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
1558 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
1559 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
1560 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1561 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
1562 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1563 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
1566 let Predicates = [HasAVX] in {
1567 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1568 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1569 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1570 (VCVTSS2SIrm addr:$src)>;
1571 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1572 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1573 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1574 (VCVTSS2SI64rm addr:$src)>;
1577 let Predicates = [HasSSE1] in {
1578 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1579 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1580 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1581 (CVTSS2SIrm addr:$src)>;
1582 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1583 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1584 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1585 (CVTSS2SI64rm addr:$src)>;
1590 // Convert scalar double to scalar single
1591 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1592 (ins FR64:$src1, FR64:$src2),
1593 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
1596 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1597 (ins FR64:$src1, f64mem:$src2),
1598 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1599 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1601 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1604 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1605 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1606 [(set FR32:$dst, (fround FR64:$src))]>;
1607 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1608 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1609 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1610 Requires<[HasSSE2, OptForSize]>;
1612 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1613 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
1615 let Constraints = "$src1 = $dst" in
1616 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1617 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
1619 // Convert scalar single to scalar double
1620 // SSE2 instructions with XS prefix
1621 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1622 (ins FR32:$src1, FR32:$src2),
1623 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1624 []>, XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1626 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1627 (ins FR32:$src1, f32mem:$src2),
1628 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1629 []>, XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1631 let Predicates = [HasAVX] in {
1632 def : Pat<(f64 (fextend FR32:$src)),
1633 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
1634 def : Pat<(fextend (loadf32 addr:$src)),
1635 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1636 def : Pat<(extloadf32 addr:$src),
1637 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1640 def : Pat<(extloadf32 addr:$src),
1641 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (MOVSSrm addr:$src))>,
1642 Requires<[HasAVX, OptForSpeed]>;
1644 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1645 "cvtss2sd\t{$src, $dst|$dst, $src}",
1646 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1647 Requires<[HasSSE2]>;
1648 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1649 "cvtss2sd\t{$src, $dst|$dst, $src}",
1650 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1651 Requires<[HasSSE2, OptForSize]>;
1653 // extload f32 -> f64. This matches load+fextend because we have a hack in
1654 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1656 // Since these loads aren't folded into the fextend, we have to match it
1658 def : Pat<(fextend (loadf32 addr:$src)),
1659 (CVTSS2SDrm addr:$src)>, Requires<[HasSSE2]>;
1660 def : Pat<(extloadf32 addr:$src),
1661 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1663 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1664 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1665 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1666 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1667 VR128:$src2))]>, XS, VEX_4V,
1669 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1670 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1671 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1672 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1673 (load addr:$src2)))]>, XS, VEX_4V,
1675 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1676 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1677 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1678 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1679 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1680 VR128:$src2))]>, XS,
1681 Requires<[HasSSE2]>;
1682 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1683 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1684 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1685 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1686 (load addr:$src2)))]>, XS,
1687 Requires<[HasSSE2]>;
1690 // Convert doubleword to packed single/double fp
1691 // SSE2 instructions without OpSize prefix
1692 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1693 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1694 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1695 TB, VEX, Requires<[HasAVX]>;
1696 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1697 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1698 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1699 (bitconvert (memopv2i64 addr:$src))))]>,
1700 TB, VEX, Requires<[HasAVX]>;
1701 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1702 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1703 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1704 TB, Requires<[HasSSE2]>;
1705 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1706 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1707 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1708 (bitconvert (memopv2i64 addr:$src))))]>,
1709 TB, Requires<[HasSSE2]>;
1711 // FIXME: why the non-intrinsic version is described as SSE3?
1712 // SSE2 instructions with XS prefix
1713 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1714 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1715 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1716 XS, VEX, Requires<[HasAVX]>;
1717 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1718 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1719 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1720 (bitconvert (memopv2i64 addr:$src))))]>,
1721 XS, VEX, Requires<[HasAVX]>;
1722 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1723 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1724 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1725 XS, Requires<[HasSSE2]>;
1726 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1727 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1728 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1729 (bitconvert (memopv2i64 addr:$src))))]>,
1730 XS, Requires<[HasSSE2]>;
1733 // Convert packed single/double fp to doubleword
1734 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1735 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1736 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1737 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1738 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1739 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1740 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1741 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1742 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1743 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1744 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1745 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1747 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1748 "cvtps2dq\t{$src, $dst|$dst, $src}",
1749 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
1751 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1753 "cvtps2dq\t{$src, $dst|$dst, $src}",
1754 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1755 (memop addr:$src)))]>, VEX;
1756 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1757 "cvtps2dq\t{$src, $dst|$dst, $src}",
1758 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1759 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1760 "cvtps2dq\t{$src, $dst|$dst, $src}",
1761 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1762 (memop addr:$src)))]>;
1764 // SSE2 packed instructions with XD prefix
1765 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1766 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1767 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1768 XD, VEX, Requires<[HasAVX]>;
1769 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1770 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1771 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1772 (memop addr:$src)))]>,
1773 XD, VEX, Requires<[HasAVX]>;
1774 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1775 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1776 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1777 XD, Requires<[HasSSE2]>;
1778 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1779 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1780 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1781 (memop addr:$src)))]>,
1782 XD, Requires<[HasSSE2]>;
1785 // Convert with truncation packed single/double fp to doubleword
1786 // SSE2 packed instructions with XS prefix
1787 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1788 "cvttps2dq\t{$src, $dst|$dst, $src}",
1790 (int_x86_sse2_cvttps2dq VR128:$src))]>, VEX;
1791 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1792 "cvttps2dq\t{$src, $dst|$dst, $src}",
1793 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1794 (memop addr:$src)))]>, VEX;
1795 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1796 "cvttps2dq\t{$src, $dst|$dst, $src}",
1798 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))]>, VEX;
1799 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1800 "cvttps2dq\t{$src, $dst|$dst, $src}",
1801 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
1802 (memopv8f32 addr:$src)))]>, VEX;
1804 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1805 "cvttps2dq\t{$src, $dst|$dst, $src}",
1807 (int_x86_sse2_cvttps2dq VR128:$src))]>;
1808 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1809 "cvttps2dq\t{$src, $dst|$dst, $src}",
1811 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
1813 let Predicates = [HasAVX] in {
1814 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1815 (Int_VCVTDQ2PSrr VR128:$src)>;
1816 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1817 (Int_VCVTDQ2PSrm addr:$src)>;
1819 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1820 (VCVTTPS2DQrr VR128:$src)>;
1821 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1822 (VCVTTPS2DQrm addr:$src)>;
1824 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1825 (VCVTDQ2PSYrr VR256:$src)>;
1826 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
1827 (VCVTDQ2PSYrm addr:$src)>;
1829 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1830 (VCVTTPS2DQYrr VR256:$src)>;
1831 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
1832 (VCVTTPS2DQYrm addr:$src)>;
1835 let Predicates = [HasSSE2] in {
1836 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1837 (Int_CVTDQ2PSrr VR128:$src)>;
1838 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1839 (Int_CVTDQ2PSrm addr:$src)>;
1841 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1842 (CVTTPS2DQrr VR128:$src)>;
1843 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1844 (CVTTPS2DQrm addr:$src)>;
1847 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1848 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1850 (int_x86_sse2_cvttpd2dq VR128:$src))]>, VEX;
1851 let isCodeGenOnly = 1 in
1852 def VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1853 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1854 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1855 (memop addr:$src)))]>, VEX;
1856 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1857 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1858 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1859 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1860 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1861 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1862 (memop addr:$src)))]>;
1864 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1865 // register, but the same isn't true when using memory operands instead.
1866 // Provide other assembly rr and rm forms to address this explicitly.
1867 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1868 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1871 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1872 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1873 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1874 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1877 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1878 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
1879 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1880 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1882 // Convert packed single to packed double
1883 let Predicates = [HasAVX] in {
1884 // SSE2 instructions without OpSize prefix
1885 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1886 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1887 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1888 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1889 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1890 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1891 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1892 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1894 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1895 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1896 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1897 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1899 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1900 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1901 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1902 TB, VEX, Requires<[HasAVX]>;
1903 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1904 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1905 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1906 (load addr:$src)))]>,
1907 TB, VEX, Requires<[HasAVX]>;
1908 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1909 "cvtps2pd\t{$src, $dst|$dst, $src}",
1910 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1911 TB, Requires<[HasSSE2]>;
1912 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1913 "cvtps2pd\t{$src, $dst|$dst, $src}",
1914 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1915 (load addr:$src)))]>,
1916 TB, Requires<[HasSSE2]>;
1918 // Convert packed double to packed single
1919 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1920 // register, but the same isn't true when using memory operands instead.
1921 // Provide other assembly rr and rm forms to address this explicitly.
1922 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1923 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1924 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1925 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1928 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1929 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1930 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1931 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1934 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1935 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1936 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1937 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1938 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1939 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1940 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1941 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1944 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1945 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1946 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1947 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1949 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1950 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1951 (memop addr:$src)))]>;
1952 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1953 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1954 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1955 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1956 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1957 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1958 (memop addr:$src)))]>;
1960 // AVX 256-bit register conversion intrinsics
1961 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1962 // whenever possible to avoid declaring two versions of each one.
1963 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1964 (VCVTDQ2PSYrr VR256:$src)>;
1965 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
1966 (VCVTDQ2PSYrm addr:$src)>;
1968 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1969 (VCVTPD2PSYrr VR256:$src)>;
1970 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1971 (VCVTPD2PSYrm addr:$src)>;
1973 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1974 (VCVTPS2DQYrr VR256:$src)>;
1975 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1976 (VCVTPS2DQYrm addr:$src)>;
1978 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1979 (VCVTPS2PDYrr VR128:$src)>;
1980 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1981 (VCVTPS2PDYrm addr:$src)>;
1983 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1984 (VCVTTPD2DQYrr VR256:$src)>;
1985 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1986 (VCVTTPD2DQYrm addr:$src)>;
1988 // Match fround and fextend for 128/256-bit conversions
1989 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
1990 (VCVTPD2PSYrr VR256:$src)>;
1991 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
1992 (VCVTPD2PSYrm addr:$src)>;
1994 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
1995 (VCVTPS2PDYrr VR128:$src)>;
1996 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
1997 (VCVTPS2PDYrm addr:$src)>;
1999 //===----------------------------------------------------------------------===//
2000 // SSE 1 & 2 - Compare Instructions
2001 //===----------------------------------------------------------------------===//
2003 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2004 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2005 SDNode OpNode, ValueType VT, PatFrag ld_frag,
2006 string asm, string asm_alt> {
2007 def rr : SIi8<0xC2, MRMSrcReg,
2008 (outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
2009 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))]>;
2010 def rm : SIi8<0xC2, MRMSrcMem,
2011 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, SSECC:$cc), asm,
2012 [(set RC:$dst, (OpNode (VT RC:$src1),
2013 (ld_frag addr:$src2), imm:$cc))]>;
2015 // Accept explicit immediate argument form instead of comparison code.
2016 let neverHasSideEffects = 1 in {
2017 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2018 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, []>;
2020 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2021 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, []>;
2025 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, X86cmpss, f32, loadf32,
2026 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2027 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
2028 XS, VEX_4V, VEX_LIG;
2029 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, X86cmpsd, f64, loadf64,
2030 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2031 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
2032 XD, VEX_4V, VEX_LIG;
2034 let Constraints = "$src1 = $dst" in {
2035 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, X86cmpss, f32, loadf32,
2036 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2037 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}">,
2039 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, X86cmpsd, f64, loadf64,
2040 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2041 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}">,
2045 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
2046 Intrinsic Int, string asm> {
2047 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2048 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
2049 [(set VR128:$dst, (Int VR128:$src1,
2050 VR128:$src, imm:$cc))]>;
2051 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2052 (ins VR128:$src1, x86memop:$src, SSECC:$cc), asm,
2053 [(set VR128:$dst, (Int VR128:$src1,
2054 (load addr:$src), imm:$cc))]>;
2057 // Aliases to match intrinsics which expect XMM operand(s).
2058 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2059 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
2061 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2062 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
2064 let Constraints = "$src1 = $dst" in {
2065 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2066 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
2067 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2068 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
2072 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2073 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2074 ValueType vt, X86MemOperand x86memop,
2075 PatFrag ld_frag, string OpcodeStr, Domain d> {
2076 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2077 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2078 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2080 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2081 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2082 [(set EFLAGS, (OpNode (vt RC:$src1),
2083 (ld_frag addr:$src2)))],
2087 let Defs = [EFLAGS] in {
2088 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2089 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2090 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2091 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2093 let Pattern = []<dag> in {
2094 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2095 "comiss", SSEPackedSingle>, TB, VEX,
2097 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2098 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2102 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2103 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2104 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2105 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2107 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2108 load, "comiss", SSEPackedSingle>, TB, VEX;
2109 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2110 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2111 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2112 "ucomiss", SSEPackedSingle>, TB;
2113 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2114 "ucomisd", SSEPackedDouble>, TB, OpSize;
2116 let Pattern = []<dag> in {
2117 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2118 "comiss", SSEPackedSingle>, TB;
2119 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2120 "comisd", SSEPackedDouble>, TB, OpSize;
2123 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2124 load, "ucomiss", SSEPackedSingle>, TB;
2125 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2126 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2128 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2129 "comiss", SSEPackedSingle>, TB;
2130 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2131 "comisd", SSEPackedDouble>, TB, OpSize;
2132 } // Defs = [EFLAGS]
2134 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
2135 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2136 Intrinsic Int, string asm, string asm_alt,
2138 let isAsmParserOnly = 1 in {
2139 def rri : PIi8<0xC2, MRMSrcReg,
2140 (outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
2141 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2143 def rmi : PIi8<0xC2, MRMSrcMem,
2144 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, SSECC:$cc), asm,
2145 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2149 // Accept explicit immediate argument form instead of comparison code.
2150 def rri_alt : PIi8<0xC2, MRMSrcReg,
2151 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2152 asm_alt, [], IIC_DEFAULT, d>;
2153 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2154 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2155 asm_alt, [], IIC_DEFAULT, d>;
2158 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2159 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2160 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2161 SSEPackedSingle>, TB, VEX_4V;
2162 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2163 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2164 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2165 SSEPackedDouble>, TB, OpSize, VEX_4V;
2166 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
2167 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2168 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2169 SSEPackedSingle>, TB, VEX_4V;
2170 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
2171 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2172 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2173 SSEPackedDouble>, TB, OpSize, VEX_4V;
2174 let Constraints = "$src1 = $dst" in {
2175 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2176 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2177 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2178 SSEPackedSingle>, TB;
2179 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2180 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2181 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2182 SSEPackedDouble>, TB, OpSize;
2185 let Predicates = [HasAVX] in {
2186 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2187 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2188 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2189 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2190 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2191 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2192 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2193 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2195 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2196 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2197 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2198 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2199 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2200 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2201 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2202 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2205 let Predicates = [HasSSE1] in {
2206 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2207 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2208 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2209 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2212 let Predicates = [HasSSE2] in {
2213 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2214 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2215 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2216 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2219 //===----------------------------------------------------------------------===//
2220 // SSE 1 & 2 - Shuffle Instructions
2221 //===----------------------------------------------------------------------===//
2223 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2224 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2225 ValueType vt, string asm, PatFrag mem_frag,
2226 Domain d, bit IsConvertibleToThreeAddress = 0> {
2227 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2228 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2229 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2230 (i8 imm:$src3))))], IIC_DEFAULT, d>;
2231 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2232 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2233 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2234 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2235 (i8 imm:$src3))))], IIC_DEFAULT, d>;
2238 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2239 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2240 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2241 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2242 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2243 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2244 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2245 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2246 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2247 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2248 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2249 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2251 let Constraints = "$src1 = $dst" in {
2252 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2253 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2254 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2256 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2257 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2258 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2262 let Predicates = [HasAVX] in {
2263 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2264 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2265 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2266 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2267 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2268 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2269 // fall back to this for SSE1)
2270 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2271 (VSHUFPSrri VR128:$src2, VR128:$src1,
2272 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2273 // Special unary SHUFPSrri case.
2274 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2275 (VSHUFPSrri VR128:$src1, VR128:$src1,
2276 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2277 // Special unary SHUFPDrri cases.
2278 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2279 (VSHUFPDrri VR128:$src1, VR128:$src1,
2280 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2281 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2282 (VSHUFPDrri VR128:$src1, VR128:$src1,
2283 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2285 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2286 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2287 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2288 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2289 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2292 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2293 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2294 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2295 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2296 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2298 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2299 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2300 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2301 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2302 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2305 let Predicates = [HasSSE1] in {
2306 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2307 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2308 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2309 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2310 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2311 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2312 // fall back to this for SSE1)
2313 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2314 (SHUFPSrri VR128:$src2, VR128:$src1,
2315 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2318 let Predicates = [HasSSE2] in {
2319 // Generic SHUFPD patterns
2320 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2321 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2322 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2323 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2324 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2327 //===----------------------------------------------------------------------===//
2328 // SSE 1 & 2 - Unpack Instructions
2329 //===----------------------------------------------------------------------===//
2331 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2332 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
2333 PatFrag mem_frag, RegisterClass RC,
2334 X86MemOperand x86memop, string asm,
2336 def rr : PI<opc, MRMSrcReg,
2337 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2339 (vt (OpNode RC:$src1, RC:$src2)))],
2341 def rm : PI<opc, MRMSrcMem,
2342 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2344 (vt (OpNode RC:$src1,
2345 (mem_frag addr:$src2))))],
2349 let AddedComplexity = 10 in {
2350 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2351 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2352 SSEPackedSingle>, TB, VEX_4V;
2353 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2354 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2355 SSEPackedDouble>, TB, OpSize, VEX_4V;
2356 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2357 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2358 SSEPackedSingle>, TB, VEX_4V;
2359 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2360 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2361 SSEPackedDouble>, TB, OpSize, VEX_4V;
2363 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
2364 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2365 SSEPackedSingle>, TB, VEX_4V;
2366 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
2367 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2368 SSEPackedDouble>, TB, OpSize, VEX_4V;
2369 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
2370 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2371 SSEPackedSingle>, TB, VEX_4V;
2372 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
2373 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2374 SSEPackedDouble>, TB, OpSize, VEX_4V;
2376 let Constraints = "$src1 = $dst" in {
2377 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2378 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2379 SSEPackedSingle>, TB;
2380 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2381 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2382 SSEPackedDouble>, TB, OpSize;
2383 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2384 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2385 SSEPackedSingle>, TB;
2386 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2387 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2388 SSEPackedDouble>, TB, OpSize;
2389 } // Constraints = "$src1 = $dst"
2390 } // AddedComplexity
2392 let Predicates = [HasAVX], AddedComplexity = 1 in {
2393 def : Pat<(v4f32 (X86Unpckl VR128:$src1, (memopv4f32 addr:$src2))),
2394 (VUNPCKLPSrm VR128:$src1, addr:$src2)>;
2395 def : Pat<(v4f32 (X86Unpckl VR128:$src1, VR128:$src2)),
2396 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>;
2397 def : Pat<(v4f32 (X86Unpckh VR128:$src1, (memopv4f32 addr:$src2))),
2398 (VUNPCKHPSrm VR128:$src1, addr:$src2)>;
2399 def : Pat<(v4f32 (X86Unpckh VR128:$src1, VR128:$src2)),
2400 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>;
2402 def : Pat<(v8f32 (X86Unpckl VR256:$src1, (memopv8f32 addr:$src2))),
2403 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2404 def : Pat<(v8f32 (X86Unpckl VR256:$src1, VR256:$src2)),
2405 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2406 def : Pat<(v8f32 (X86Unpckh VR256:$src1, (memopv8f32 addr:$src2))),
2407 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2408 def : Pat<(v8f32 (X86Unpckh VR256:$src1, VR256:$src2)),
2409 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2411 def : Pat<(v2f64 (X86Unpckl VR128:$src1, (memopv2f64 addr:$src2))),
2412 (VUNPCKLPDrm VR128:$src1, addr:$src2)>;
2413 def : Pat<(v2f64 (X86Unpckl VR128:$src1, VR128:$src2)),
2414 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>;
2415 def : Pat<(v2f64 (X86Unpckh VR128:$src1, (memopv2f64 addr:$src2))),
2416 (VUNPCKHPDrm VR128:$src1, addr:$src2)>;
2417 def : Pat<(v2f64 (X86Unpckh VR128:$src1, VR128:$src2)),
2418 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>;
2420 def : Pat<(v4f64 (X86Unpckl VR256:$src1, (memopv4f64 addr:$src2))),
2421 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2422 def : Pat<(v4f64 (X86Unpckl VR256:$src1, VR256:$src2)),
2423 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2424 def : Pat<(v4f64 (X86Unpckh VR256:$src1, (memopv4f64 addr:$src2))),
2425 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2426 def : Pat<(v4f64 (X86Unpckh VR256:$src1, VR256:$src2)),
2427 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2429 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2430 // problem is during lowering, where it's not possible to recognize the load
2431 // fold cause it has two uses through a bitcast. One use disappears at isel
2432 // time and the fold opportunity reappears.
2433 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2434 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2437 let Predicates = [HasSSE1] in {
2438 def : Pat<(v4f32 (X86Unpckl VR128:$src1, (memopv4f32 addr:$src2))),
2439 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
2440 def : Pat<(v4f32 (X86Unpckl VR128:$src1, VR128:$src2)),
2441 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
2442 def : Pat<(v4f32 (X86Unpckh VR128:$src1, (memopv4f32 addr:$src2))),
2443 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
2444 def : Pat<(v4f32 (X86Unpckh VR128:$src1, VR128:$src2)),
2445 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
2448 let Predicates = [HasSSE2] in {
2449 def : Pat<(v2f64 (X86Unpckl VR128:$src1, (memopv2f64 addr:$src2))),
2450 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
2451 def : Pat<(v2f64 (X86Unpckl VR128:$src1, VR128:$src2)),
2452 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
2453 def : Pat<(v2f64 (X86Unpckh VR128:$src1, (memopv2f64 addr:$src2))),
2454 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
2455 def : Pat<(v2f64 (X86Unpckh VR128:$src1, VR128:$src2)),
2456 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
2458 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2459 // problem is during lowering, where it's not possible to recognize the load
2460 // fold cause it has two uses through a bitcast. One use disappears at isel
2461 // time and the fold opportunity reappears.
2462 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2463 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2466 //===----------------------------------------------------------------------===//
2467 // SSE 1 & 2 - Extract Floating-Point Sign mask
2468 //===----------------------------------------------------------------------===//
2470 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2471 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2473 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2474 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2475 [(set GR32:$dst, (Int RC:$src))], IIC_DEFAULT, d>;
2476 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2477 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2478 IIC_DEFAULT, d>, REX_W;
2481 let Predicates = [HasAVX] in {
2482 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2483 "movmskps", SSEPackedSingle>, TB, VEX;
2484 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2485 "movmskpd", SSEPackedDouble>, TB,
2487 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2488 "movmskps", SSEPackedSingle>, TB, VEX;
2489 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2490 "movmskpd", SSEPackedDouble>, TB,
2493 def : Pat<(i32 (X86fgetsign FR32:$src)),
2494 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2496 def : Pat<(i64 (X86fgetsign FR32:$src)),
2497 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2499 def : Pat<(i32 (X86fgetsign FR64:$src)),
2500 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2502 def : Pat<(i64 (X86fgetsign FR64:$src)),
2503 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2507 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2508 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_DEFAULT,
2509 SSEPackedSingle>, TB, VEX;
2510 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2511 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_DEFAULT,
2512 SSEPackedDouble>, TB,
2514 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2515 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_DEFAULT,
2516 SSEPackedSingle>, TB, VEX;
2517 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2518 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_DEFAULT,
2519 SSEPackedDouble>, TB,
2523 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2524 SSEPackedSingle>, TB;
2525 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2526 SSEPackedDouble>, TB, OpSize;
2528 def : Pat<(i32 (X86fgetsign FR32:$src)),
2529 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2530 sub_ss))>, Requires<[HasSSE1]>;
2531 def : Pat<(i64 (X86fgetsign FR32:$src)),
2532 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2533 sub_ss))>, Requires<[HasSSE1]>;
2534 def : Pat<(i32 (X86fgetsign FR64:$src)),
2535 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2536 sub_sd))>, Requires<[HasSSE2]>;
2537 def : Pat<(i64 (X86fgetsign FR64:$src)),
2538 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2539 sub_sd))>, Requires<[HasSSE2]>;
2541 //===---------------------------------------------------------------------===//
2542 // SSE2 - Packed Integer Logical Instructions
2543 //===---------------------------------------------------------------------===//
2545 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2547 /// PDI_binop_rm - Simple SSE2 binary operator.
2548 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2549 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2550 X86MemOperand x86memop, bit IsCommutable = 0,
2552 let isCommutable = IsCommutable in
2553 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2554 (ins RC:$src1, RC:$src2),
2556 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2557 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2558 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
2559 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2560 (ins RC:$src1, x86memop:$src2),
2562 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2563 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2564 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2565 (bitconvert (memop_frag addr:$src2)))))]>;
2567 } // ExeDomain = SSEPackedInt
2569 // These are ordered here for pattern ordering requirements with the fp versions
2571 let Predicates = [HasAVX] in {
2572 defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
2573 i128mem, 1, 0>, VEX_4V;
2574 defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
2575 i128mem, 1, 0>, VEX_4V;
2576 defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
2577 i128mem, 1, 0>, VEX_4V;
2578 defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
2579 i128mem, 0, 0>, VEX_4V;
2582 let Constraints = "$src1 = $dst" in {
2583 defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
2585 defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
2587 defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
2589 defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
2591 } // Constraints = "$src1 = $dst"
2593 let Predicates = [HasAVX2] in {
2594 defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
2595 i256mem, 1, 0>, VEX_4V;
2596 defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
2597 i256mem, 1, 0>, VEX_4V;
2598 defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
2599 i256mem, 1, 0>, VEX_4V;
2600 defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
2601 i256mem, 0, 0>, VEX_4V;
2604 //===----------------------------------------------------------------------===//
2605 // SSE 1 & 2 - Logical Instructions
2606 //===----------------------------------------------------------------------===//
2608 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2610 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2612 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2613 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, TB, VEX_4V;
2615 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2616 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, TB, OpSize, VEX_4V;
2618 let Constraints = "$src1 = $dst" in {
2619 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2620 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
2622 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2623 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
2627 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2628 let mayLoad = 0 in {
2629 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
2630 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
2631 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
2634 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2635 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
2637 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2639 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2641 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2642 // are all promoted to v2i64, and the patterns are covered by the int
2643 // version. This is needed in SSE only, because v2i64 isn't supported on
2644 // SSE1, but only on SSE2.
2645 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2646 !strconcat(OpcodeStr, "ps"), f128mem, [],
2647 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2648 (memopv2i64 addr:$src2)))], 0, 1>, TB, VEX_4V;
2650 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2651 !strconcat(OpcodeStr, "pd"), f128mem,
2652 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2653 (bc_v2i64 (v2f64 VR128:$src2))))],
2654 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2655 (memopv2i64 addr:$src2)))], 0>,
2657 let Constraints = "$src1 = $dst" in {
2658 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2659 !strconcat(OpcodeStr, "ps"), f128mem,
2660 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2661 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2662 (memopv2i64 addr:$src2)))]>, TB;
2664 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2665 !strconcat(OpcodeStr, "pd"), f128mem,
2666 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2667 (bc_v2i64 (v2f64 VR128:$src2))))],
2668 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2669 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2673 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2675 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2677 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2678 !strconcat(OpcodeStr, "ps"), f256mem,
2679 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2680 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2681 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2683 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2684 !strconcat(OpcodeStr, "pd"), f256mem,
2685 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2686 (bc_v4i64 (v4f64 VR256:$src2))))],
2687 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2688 (memopv4i64 addr:$src2)))], 0>,
2692 // AVX 256-bit packed logical ops forms
2693 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2694 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2695 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2696 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2698 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2699 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2700 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2701 let isCommutable = 0 in
2702 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2704 //===----------------------------------------------------------------------===//
2705 // SSE 1 & 2 - Arithmetic Instructions
2706 //===----------------------------------------------------------------------===//
2708 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2711 /// In addition, we also have a special variant of the scalar form here to
2712 /// represent the associated intrinsic operation. This form is unlike the
2713 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2714 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2716 /// These three forms can each be reg+reg or reg+mem.
2719 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2721 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2723 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2724 OpNode, FR32, f32mem, Is2Addr>, XS;
2725 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2726 OpNode, FR64, f64mem, Is2Addr>, XD;
2729 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2731 let mayLoad = 0 in {
2732 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2733 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
2734 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2735 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
2739 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2741 let mayLoad = 0 in {
2742 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2743 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
2744 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2745 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
2749 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2751 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2752 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
2753 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2754 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
2757 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2759 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2760 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2761 SSEPackedSingle, Is2Addr>, TB;
2763 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2764 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2765 SSEPackedDouble, Is2Addr>, TB, OpSize;
2768 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
2769 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2770 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2771 SSEPackedSingle, 0>, TB;
2773 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2774 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2775 SSEPackedDouble, 0>, TB, OpSize;
2778 // Binary Arithmetic instructions
2779 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
2780 basic_sse12_fp_binop_s_int<0x58, "add", 0>, VEX_4V, VEX_LIG;
2781 defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
2782 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
2783 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
2784 basic_sse12_fp_binop_s_int<0x59, "mul", 0>, VEX_4V, VEX_LIG;
2785 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
2786 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
2788 let isCommutable = 0 in {
2789 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
2790 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>, VEX_4V, VEX_LIG;
2791 defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
2792 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
2793 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
2794 basic_sse12_fp_binop_s_int<0x5E, "div", 0>, VEX_4V, VEX_LIG;
2795 defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
2796 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
2797 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
2798 basic_sse12_fp_binop_s_int<0x5F, "max", 0>, VEX_4V, VEX_LIG;
2799 defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
2800 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
2801 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
2802 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
2803 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
2804 basic_sse12_fp_binop_s_int<0x5D, "min", 0>, VEX_4V, VEX_LIG;
2805 defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
2806 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
2807 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
2808 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
2811 let Constraints = "$src1 = $dst" in {
2812 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
2813 basic_sse12_fp_binop_p<0x58, "add", fadd>,
2814 basic_sse12_fp_binop_s_int<0x58, "add">;
2815 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
2816 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
2817 basic_sse12_fp_binop_s_int<0x59, "mul">;
2819 let isCommutable = 0 in {
2820 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
2821 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
2822 basic_sse12_fp_binop_s_int<0x5C, "sub">;
2823 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
2824 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
2825 basic_sse12_fp_binop_s_int<0x5E, "div">;
2826 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
2827 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
2828 basic_sse12_fp_binop_s_int<0x5F, "max">,
2829 basic_sse12_fp_binop_p_int<0x5F, "max">;
2830 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
2831 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
2832 basic_sse12_fp_binop_s_int<0x5D, "min">,
2833 basic_sse12_fp_binop_p_int<0x5D, "min">;
2838 /// In addition, we also have a special variant of the scalar form here to
2839 /// represent the associated intrinsic operation. This form is unlike the
2840 /// plain scalar form, in that it takes an entire vector (instead of a
2841 /// scalar) and leaves the top elements undefined.
2843 /// And, we have a special variant form for a full-vector intrinsic form.
2845 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2846 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2847 SDNode OpNode, Intrinsic F32Int> {
2848 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2849 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2850 [(set FR32:$dst, (OpNode FR32:$src))]>;
2851 // For scalar unary operations, fold a load into the operation
2852 // only in OptForSize mode. It eliminates an instruction, but it also
2853 // eliminates a whole-register clobber (the load), so it introduces a
2854 // partial register update condition.
2855 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
2856 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2857 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
2858 Requires<[HasSSE1, OptForSize]>;
2859 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2860 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2861 [(set VR128:$dst, (F32Int VR128:$src))]>;
2862 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
2863 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2864 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
2867 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
2868 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2869 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
2870 !strconcat(OpcodeStr,
2871 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2873 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
2874 !strconcat(OpcodeStr,
2875 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2876 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
2877 (ins VR128:$src1, ssmem:$src2),
2878 !strconcat(OpcodeStr,
2879 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2882 /// sse1_fp_unop_p - SSE1 unops in packed form.
2883 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2884 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2885 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2886 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
2887 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2888 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2889 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
2892 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
2893 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2894 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2895 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2896 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
2897 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2898 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2899 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
2902 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
2903 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2904 Intrinsic V4F32Int> {
2905 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2906 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2907 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
2908 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2909 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2910 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
2913 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
2914 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2915 Intrinsic V4F32Int> {
2916 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2917 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2918 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
2919 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2920 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2921 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
2924 /// sse2_fp_unop_s - SSE2 unops in scalar form.
2925 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
2926 SDNode OpNode, Intrinsic F64Int> {
2927 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
2928 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2929 [(set FR64:$dst, (OpNode FR64:$src))]>;
2930 // See the comments in sse1_fp_unop_s for why this is OptForSize.
2931 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
2932 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2933 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
2934 Requires<[HasSSE2, OptForSize]>;
2935 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2936 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2937 [(set VR128:$dst, (F64Int VR128:$src))]>;
2938 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
2939 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2940 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
2943 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
2944 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2945 let neverHasSideEffects = 1 in {
2946 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
2947 !strconcat(OpcodeStr,
2948 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2950 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
2951 !strconcat(OpcodeStr,
2952 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2954 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
2955 (ins VR128:$src1, sdmem:$src2),
2956 !strconcat(OpcodeStr,
2957 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2960 /// sse2_fp_unop_p - SSE2 unops in vector forms.
2961 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
2963 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2964 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2965 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
2966 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2967 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2968 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
2971 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
2972 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2973 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2974 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2975 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
2976 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2977 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2978 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
2981 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
2982 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2983 Intrinsic V2F64Int> {
2984 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2985 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2986 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
2987 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2988 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2989 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
2992 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
2993 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2994 Intrinsic V2F64Int> {
2995 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2996 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2997 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
2998 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2999 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3000 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
3003 let Predicates = [HasAVX] in {
3005 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
3006 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
3008 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
3009 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
3010 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
3011 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
3012 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
3013 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
3014 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
3015 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
3018 // Reciprocal approximations. Note that these typically require refinement
3019 // in order to obtain suitable precision.
3020 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
3021 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
3022 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
3023 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
3024 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
3026 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
3027 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
3028 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
3029 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
3030 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
3033 let AddedComplexity = 1 in {
3034 def : Pat<(f32 (fsqrt FR32:$src)),
3035 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3036 def : Pat<(f32 (fsqrt (load addr:$src))),
3037 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3038 Requires<[HasAVX, OptForSize]>;
3039 def : Pat<(f64 (fsqrt FR64:$src)),
3040 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3041 def : Pat<(f64 (fsqrt (load addr:$src))),
3042 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3043 Requires<[HasAVX, OptForSize]>;
3045 def : Pat<(f32 (X86frsqrt FR32:$src)),
3046 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3047 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3048 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3049 Requires<[HasAVX, OptForSize]>;
3051 def : Pat<(f32 (X86frcp FR32:$src)),
3052 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3053 def : Pat<(f32 (X86frcp (load addr:$src))),
3054 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3055 Requires<[HasAVX, OptForSize]>;
3058 let Predicates = [HasAVX], AddedComplexity = 1 in {
3059 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3060 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3061 (VSQRTSSr (f32 (IMPLICIT_DEF)),
3062 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3064 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3065 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3067 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3068 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
3069 (VSQRTSDr (f64 (IMPLICIT_DEF)),
3070 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
3072 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3073 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3075 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3076 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3077 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3078 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3080 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3081 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3083 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3084 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3085 (VRCPSSr (f32 (IMPLICIT_DEF)),
3086 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3088 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3089 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3093 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
3094 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
3095 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
3096 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
3097 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
3098 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
3100 // Reciprocal approximations. Note that these typically require refinement
3101 // in order to obtain suitable precision.
3102 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
3103 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
3104 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
3105 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
3106 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
3107 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
3109 // There is no f64 version of the reciprocal approximation instructions.
3111 //===----------------------------------------------------------------------===//
3112 // SSE 1 & 2 - Non-temporal stores
3113 //===----------------------------------------------------------------------===//
3115 let AddedComplexity = 400 in { // Prefer non-temporal versions
3116 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3117 (ins f128mem:$dst, VR128:$src),
3118 "movntps\t{$src, $dst|$dst, $src}",
3119 [(alignednontemporalstore (v4f32 VR128:$src),
3121 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3122 (ins f128mem:$dst, VR128:$src),
3123 "movntpd\t{$src, $dst|$dst, $src}",
3124 [(alignednontemporalstore (v2f64 VR128:$src),
3127 let ExeDomain = SSEPackedInt in
3128 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3129 (ins f128mem:$dst, VR128:$src),
3130 "movntdq\t{$src, $dst|$dst, $src}",
3131 [(alignednontemporalstore (v2i64 VR128:$src),
3134 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3135 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3137 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3138 (ins f256mem:$dst, VR256:$src),
3139 "movntps\t{$src, $dst|$dst, $src}",
3140 [(alignednontemporalstore (v8f32 VR256:$src),
3142 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3143 (ins f256mem:$dst, VR256:$src),
3144 "movntpd\t{$src, $dst|$dst, $src}",
3145 [(alignednontemporalstore (v4f64 VR256:$src),
3147 let ExeDomain = SSEPackedInt in
3148 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3149 (ins f256mem:$dst, VR256:$src),
3150 "movntdq\t{$src, $dst|$dst, $src}",
3151 [(alignednontemporalstore (v4i64 VR256:$src),
3155 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
3156 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3157 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
3158 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
3159 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
3160 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
3162 let AddedComplexity = 400 in { // Prefer non-temporal versions
3163 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3164 "movntps\t{$src, $dst|$dst, $src}",
3165 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
3166 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3167 "movntpd\t{$src, $dst|$dst, $src}",
3168 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
3170 let ExeDomain = SSEPackedInt in
3171 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3172 "movntdq\t{$src, $dst|$dst, $src}",
3173 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)]>;
3175 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3176 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3178 // There is no AVX form for instructions below this point
3179 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3180 "movnti{l}\t{$src, $dst|$dst, $src}",
3181 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
3182 TB, Requires<[HasSSE2]>;
3183 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3184 "movnti{q}\t{$src, $dst|$dst, $src}",
3185 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
3186 TB, Requires<[HasSSE2]>;
3189 //===----------------------------------------------------------------------===//
3190 // SSE 1 & 2 - Prefetch and memory fence
3191 //===----------------------------------------------------------------------===//
3193 // Prefetch intrinsic.
3194 let Predicates = [HasSSE1] in {
3195 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3196 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>, TB;
3197 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3198 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>, TB;
3199 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3200 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>, TB;
3201 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3202 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>, TB;
3206 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3207 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3208 TB, Requires<[HasSSE2]>;
3210 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3211 // was introduced with SSE2, it's backward compatible.
3212 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3214 // Load, store, and memory fence
3215 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3216 "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
3217 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3218 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3219 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3220 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3222 def : Pat<(X86SFence), (SFENCE)>;
3223 def : Pat<(X86LFence), (LFENCE)>;
3224 def : Pat<(X86MFence), (MFENCE)>;
3226 //===----------------------------------------------------------------------===//
3227 // SSE 1 & 2 - Load/Store XCSR register
3228 //===----------------------------------------------------------------------===//
3230 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3231 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
3232 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3233 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
3235 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3236 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
3237 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3238 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
3240 //===---------------------------------------------------------------------===//
3241 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3242 //===---------------------------------------------------------------------===//
3244 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3246 let neverHasSideEffects = 1 in {
3247 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3248 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3249 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3250 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3252 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3253 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3254 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3255 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3258 let isCodeGenOnly = 1 in {
3259 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3260 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3261 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3262 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3263 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3264 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3265 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3266 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3269 let canFoldAsLoad = 1, mayLoad = 1 in {
3270 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3271 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3272 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3273 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3274 let Predicates = [HasAVX] in {
3275 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3276 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3277 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3278 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3282 let mayStore = 1 in {
3283 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3284 (ins i128mem:$dst, VR128:$src),
3285 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3286 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3287 (ins i256mem:$dst, VR256:$src),
3288 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3289 let Predicates = [HasAVX] in {
3290 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3291 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3292 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3293 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3297 let neverHasSideEffects = 1 in
3298 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3299 "movdqa\t{$src, $dst|$dst, $src}", []>;
3301 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3302 "movdqu\t{$src, $dst|$dst, $src}",
3303 []>, XS, Requires<[HasSSE2]>;
3306 let isCodeGenOnly = 1 in {
3307 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3308 "movdqa\t{$src, $dst|$dst, $src}", []>;
3310 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3311 "movdqu\t{$src, $dst|$dst, $src}",
3312 []>, XS, Requires<[HasSSE2]>;
3315 let canFoldAsLoad = 1, mayLoad = 1 in {
3316 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3317 "movdqa\t{$src, $dst|$dst, $src}",
3318 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
3319 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3320 "movdqu\t{$src, $dst|$dst, $src}",
3321 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
3322 XS, Requires<[HasSSE2]>;
3325 let mayStore = 1 in {
3326 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3327 "movdqa\t{$src, $dst|$dst, $src}",
3328 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
3329 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3330 "movdqu\t{$src, $dst|$dst, $src}",
3331 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
3332 XS, Requires<[HasSSE2]>;
3335 // Intrinsic forms of MOVDQU load and store
3336 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3337 "vmovdqu\t{$src, $dst|$dst, $src}",
3338 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3339 XS, VEX, Requires<[HasAVX]>;
3341 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3342 "movdqu\t{$src, $dst|$dst, $src}",
3343 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3344 XS, Requires<[HasSSE2]>;
3346 } // ExeDomain = SSEPackedInt
3348 let Predicates = [HasAVX] in {
3349 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3350 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3353 //===---------------------------------------------------------------------===//
3354 // SSE2 - Packed Integer Arithmetic Instructions
3355 //===---------------------------------------------------------------------===//
3357 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3359 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3360 RegisterClass RC, PatFrag memop_frag,
3361 X86MemOperand x86memop, bit IsCommutable = 0,
3363 let isCommutable = IsCommutable in
3364 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3365 (ins RC:$src1, RC:$src2),
3367 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3368 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3369 [(set RC:$dst, (IntId RC:$src1, RC:$src2))]>;
3370 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3371 (ins RC:$src1, x86memop:$src2),
3373 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3374 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3375 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))]>;
3378 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3379 string OpcodeStr, SDNode OpNode,
3380 SDNode OpNode2, RegisterClass RC,
3381 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3383 // src2 is always 128-bit
3384 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3385 (ins RC:$src1, VR128:$src2),
3387 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3388 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3389 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))]>;
3390 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3391 (ins RC:$src1, i128mem:$src2),
3393 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3394 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3395 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3396 (bc_frag (memopv2i64 addr:$src2)))))]>;
3397 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3398 (ins RC:$src1, i32i8imm:$src2),
3400 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3401 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3402 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))]>;
3405 /// PDI_binop_rm - Simple SSE2 binary operator with different src and dst types
3406 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3407 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3408 PatFrag memop_frag, X86MemOperand x86memop,
3409 bit IsCommutable = 0, bit Is2Addr = 1> {
3410 let isCommutable = IsCommutable in
3411 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3412 (ins RC:$src1, RC:$src2),
3414 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3415 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3416 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>;
3417 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3418 (ins RC:$src1, x86memop:$src2),
3420 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3421 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3422 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3423 (bitconvert (memop_frag addr:$src2)))))]>;
3425 } // ExeDomain = SSEPackedInt
3427 // 128-bit Integer Arithmetic
3429 let Predicates = [HasAVX] in {
3430 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, VR128, memopv2i64,
3431 i128mem, 1, 0 /*3addr*/>, VEX_4V;
3432 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
3433 i128mem, 1, 0>, VEX_4V;
3434 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
3435 i128mem, 1, 0>, VEX_4V;
3436 defm VPADDQ : PDI_binop_rm<0xD4, "vpaddq", add, v2i64, VR128, memopv2i64,
3437 i128mem, 1, 0>, VEX_4V;
3438 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
3439 i128mem, 1, 0>, VEX_4V;
3440 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
3441 i128mem, 0, 0>, VEX_4V;
3442 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
3443 i128mem, 0, 0>, VEX_4V;
3444 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
3445 i128mem, 0, 0>, VEX_4V;
3446 defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
3447 i128mem, 0, 0>, VEX_4V;
3448 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3449 memopv2i64, i128mem, 1, 0>, VEX_4V;
3452 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
3453 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3454 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w,
3455 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3456 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b,
3457 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3458 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w,
3459 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3460 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b,
3461 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3462 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w,
3463 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3464 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b,
3465 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3466 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w,
3467 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3468 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
3469 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3470 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
3471 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3472 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
3473 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3474 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
3475 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3476 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w,
3477 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3478 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b,
3479 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3480 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w,
3481 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3482 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b,
3483 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3484 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w,
3485 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3486 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
3487 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3490 let Predicates = [HasAVX2] in {
3491 defm VPADDBY : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
3492 i256mem, 1, 0>, VEX_4V;
3493 defm VPADDWY : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
3494 i256mem, 1, 0>, VEX_4V;
3495 defm VPADDDY : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
3496 i256mem, 1, 0>, VEX_4V;
3497 defm VPADDQY : PDI_binop_rm<0xD4, "vpaddq", add, v4i64, VR256, memopv4i64,
3498 i256mem, 1, 0>, VEX_4V;
3499 defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
3500 i256mem, 1, 0>, VEX_4V;
3501 defm VPSUBBY : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
3502 i256mem, 0, 0>, VEX_4V;
3503 defm VPSUBWY : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
3504 i256mem, 0, 0>, VEX_4V;
3505 defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
3506 i256mem, 0, 0>, VEX_4V;
3507 defm VPSUBQY : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
3508 i256mem, 0, 0>, VEX_4V;
3509 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3510 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3513 defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
3514 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3515 defm VPSUBSWY : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_avx2_psubs_w,
3516 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3517 defm VPSUBUSBY : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_avx2_psubus_b,
3518 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3519 defm VPSUBUSWY : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_avx2_psubus_w,
3520 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3521 defm VPADDSBY : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_avx2_padds_b,
3522 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3523 defm VPADDSWY : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_avx2_padds_w,
3524 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3525 defm VPADDUSBY : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_avx2_paddus_b,
3526 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3527 defm VPADDUSWY : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_avx2_paddus_w,
3528 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3529 defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
3530 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3531 defm VPMULHWY : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
3532 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3533 defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
3534 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3535 defm VPAVGBY : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
3536 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3537 defm VPAVGWY : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_avx2_pavg_w,
3538 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3539 defm VPMINUBY : PDI_binop_rm_int<0xDA, "vpminub", int_x86_avx2_pminu_b,
3540 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3541 defm VPMINSWY : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_avx2_pmins_w,
3542 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3543 defm VPMAXUBY : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_avx2_pmaxu_b,
3544 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3545 defm VPMAXSWY : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_avx2_pmaxs_w,
3546 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3547 defm VPSADBWY : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
3548 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3551 let Constraints = "$src1 = $dst" in {
3552 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, VR128, memopv2i64,
3554 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
3556 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
3558 defm PADDQ : PDI_binop_rm<0xD4, "paddq", add, v2i64, VR128, memopv2i64,
3560 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
3562 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
3564 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
3566 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
3568 defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
3570 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3571 memopv2i64, i128mem, 1>;
3574 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
3575 VR128, memopv2i64, i128mem>;
3576 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3577 VR128, memopv2i64, i128mem>;
3578 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b,
3579 VR128, memopv2i64, i128mem>;
3580 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w,
3581 VR128, memopv2i64, i128mem>;
3582 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3583 VR128, memopv2i64, i128mem, 1>;
3584 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3585 VR128, memopv2i64, i128mem, 1>;
3586 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3587 VR128, memopv2i64, i128mem, 1>;
3588 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3589 VR128, memopv2i64, i128mem, 1>;
3590 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3591 VR128, memopv2i64, i128mem, 1>;
3592 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3593 VR128, memopv2i64, i128mem, 1>;
3594 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3595 VR128, memopv2i64, i128mem, 1>;
3596 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3597 VR128, memopv2i64, i128mem, 1>;
3598 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3599 VR128, memopv2i64, i128mem, 1>;
3600 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b,
3601 VR128, memopv2i64, i128mem, 1>;
3602 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w,
3603 VR128, memopv2i64, i128mem, 1>;
3604 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b,
3605 VR128, memopv2i64, i128mem, 1>;
3606 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w,
3607 VR128, memopv2i64, i128mem, 1>;
3608 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3609 VR128, memopv2i64, i128mem, 1>;
3611 } // Constraints = "$src1 = $dst"
3613 //===---------------------------------------------------------------------===//
3614 // SSE2 - Packed Integer Logical Instructions
3615 //===---------------------------------------------------------------------===//
3617 let Predicates = [HasAVX] in {
3618 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3619 VR128, v8i16, v8i16, bc_v8i16, 0>, VEX_4V;
3620 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3621 VR128, v4i32, v4i32, bc_v4i32, 0>, VEX_4V;
3622 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3623 VR128, v2i64, v2i64, bc_v2i64, 0>, VEX_4V;
3625 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3626 VR128, v8i16, v8i16, bc_v8i16, 0>, VEX_4V;
3627 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3628 VR128, v4i32, v4i32, bc_v4i32, 0>, VEX_4V;
3629 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3630 VR128, v2i64, v2i64, bc_v2i64, 0>, VEX_4V;
3632 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3633 VR128, v8i16, v8i16, bc_v8i16, 0>, VEX_4V;
3634 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3635 VR128, v4i32, v4i32, bc_v4i32, 0>, VEX_4V;
3637 let ExeDomain = SSEPackedInt in {
3638 // 128-bit logical shifts.
3639 def VPSLLDQri : PDIi8<0x73, MRM7r,
3640 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3641 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3643 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3645 def VPSRLDQri : PDIi8<0x73, MRM3r,
3646 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3647 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3649 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3651 // PSRADQri doesn't exist in SSE[1-3].
3653 } // Predicates = [HasAVX]
3655 let Predicates = [HasAVX2] in {
3656 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3657 VR256, v16i16, v8i16, bc_v8i16, 0>, VEX_4V;
3658 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3659 VR256, v8i32, v4i32, bc_v4i32, 0>, VEX_4V;
3660 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3661 VR256, v4i64, v2i64, bc_v2i64, 0>, VEX_4V;
3663 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3664 VR256, v16i16, v8i16, bc_v8i16, 0>, VEX_4V;
3665 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3666 VR256, v8i32, v4i32, bc_v4i32, 0>, VEX_4V;
3667 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3668 VR256, v4i64, v2i64, bc_v2i64, 0>, VEX_4V;
3670 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3671 VR256, v16i16, v8i16, bc_v8i16, 0>, VEX_4V;
3672 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3673 VR256, v8i32, v4i32, bc_v4i32, 0>, VEX_4V;
3675 let ExeDomain = SSEPackedInt in {
3676 // 256-bit logical shifts.
3677 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3678 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3679 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3681 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
3683 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3684 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3685 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3687 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
3689 // PSRADQYri doesn't exist in SSE[1-3].
3691 } // Predicates = [HasAVX2]
3693 let Constraints = "$src1 = $dst" in {
3694 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
3695 VR128, v8i16, v8i16, bc_v8i16>;
3696 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
3697 VR128, v4i32, v4i32, bc_v4i32>;
3698 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
3699 VR128, v2i64, v2i64, bc_v2i64>;
3701 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
3702 VR128, v8i16, v8i16, bc_v8i16>;
3703 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
3704 VR128, v4i32, v4i32, bc_v4i32>;
3705 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
3706 VR128, v2i64, v2i64, bc_v2i64>;
3708 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
3709 VR128, v8i16, v8i16, bc_v8i16>;
3710 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
3711 VR128, v4i32, v4i32, bc_v4i32>;
3713 let ExeDomain = SSEPackedInt in {
3714 // 128-bit logical shifts.
3715 def PSLLDQri : PDIi8<0x73, MRM7r,
3716 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3717 "pslldq\t{$src2, $dst|$dst, $src2}",
3719 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>;
3720 def PSRLDQri : PDIi8<0x73, MRM3r,
3721 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3722 "psrldq\t{$src2, $dst|$dst, $src2}",
3724 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>;
3725 // PSRADQri doesn't exist in SSE[1-3].
3727 } // Constraints = "$src1 = $dst"
3729 let Predicates = [HasAVX] in {
3730 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3731 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3732 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3733 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3734 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3735 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3737 // Shift up / down and insert zero's.
3738 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
3739 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3740 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
3741 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3744 let Predicates = [HasAVX2] in {
3745 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
3746 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
3747 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
3748 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
3751 let Predicates = [HasSSE2] in {
3752 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3753 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3754 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3755 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3756 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3757 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3759 // Shift up / down and insert zero's.
3760 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
3761 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3762 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
3763 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3766 //===---------------------------------------------------------------------===//
3767 // SSE2 - Packed Integer Comparison Instructions
3768 //===---------------------------------------------------------------------===//
3770 let Predicates = [HasAVX] in {
3771 defm VPCMPEQB : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v16i8,
3772 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3773 defm VPCMPEQW : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v8i16,
3774 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3775 defm VPCMPEQD : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v4i32,
3776 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3777 defm VPCMPGTB : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v16i8,
3778 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3779 defm VPCMPGTW : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v8i16,
3780 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3781 defm VPCMPGTD : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v4i32,
3782 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3785 let Predicates = [HasAVX2] in {
3786 defm VPCMPEQBY : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v32i8,
3787 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3788 defm VPCMPEQWY : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v16i16,
3789 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3790 defm VPCMPEQDY : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v8i32,
3791 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3792 defm VPCMPGTBY : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v32i8,
3793 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3794 defm VPCMPGTWY : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v16i16,
3795 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3796 defm VPCMPGTDY : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v8i32,
3797 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3800 let Constraints = "$src1 = $dst" in {
3801 defm PCMPEQB : PDI_binop_rm<0x74, "pcmpeqb", X86pcmpeq, v16i8,
3802 VR128, memopv2i64, i128mem, 1>;
3803 defm PCMPEQW : PDI_binop_rm<0x75, "pcmpeqw", X86pcmpeq, v8i16,
3804 VR128, memopv2i64, i128mem, 1>;
3805 defm PCMPEQD : PDI_binop_rm<0x76, "pcmpeqd", X86pcmpeq, v4i32,
3806 VR128, memopv2i64, i128mem, 1>;
3807 defm PCMPGTB : PDI_binop_rm<0x64, "pcmpgtb", X86pcmpgt, v16i8,
3808 VR128, memopv2i64, i128mem>;
3809 defm PCMPGTW : PDI_binop_rm<0x65, "pcmpgtw", X86pcmpgt, v8i16,
3810 VR128, memopv2i64, i128mem>;
3811 defm PCMPGTD : PDI_binop_rm<0x66, "pcmpgtd", X86pcmpgt, v4i32,
3812 VR128, memopv2i64, i128mem>;
3813 } // Constraints = "$src1 = $dst"
3815 //===---------------------------------------------------------------------===//
3816 // SSE2 - Packed Integer Pack Instructions
3817 //===---------------------------------------------------------------------===//
3819 let Predicates = [HasAVX] in {
3820 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
3821 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3822 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
3823 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3824 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
3825 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3828 let Predicates = [HasAVX2] in {
3829 defm VPACKSSWBY : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_avx2_packsswb,
3830 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3831 defm VPACKSSDWY : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_avx2_packssdw,
3832 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3833 defm VPACKUSWBY : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_avx2_packuswb,
3834 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3837 let Constraints = "$src1 = $dst" in {
3838 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
3839 VR128, memopv2i64, i128mem>;
3840 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
3841 VR128, memopv2i64, i128mem>;
3842 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
3843 VR128, memopv2i64, i128mem>;
3844 } // Constraints = "$src1 = $dst"
3846 //===---------------------------------------------------------------------===//
3847 // SSE2 - Packed Integer Shuffle Instructions
3848 //===---------------------------------------------------------------------===//
3850 let ExeDomain = SSEPackedInt in {
3851 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
3853 def ri : Ii8<0x70, MRMSrcReg,
3854 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
3855 !strconcat(OpcodeStr,
3856 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3857 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
3859 def mi : Ii8<0x70, MRMSrcMem,
3860 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
3861 !strconcat(OpcodeStr,
3862 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3863 [(set VR128:$dst, (vt (pshuf_frag:$src2
3864 (bc_frag (memopv2i64 addr:$src1)),
3868 multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, SDNode OpNode> {
3869 def Yri : Ii8<0x70, MRMSrcReg,
3870 (outs VR256:$dst), (ins VR256:$src1, i8imm:$src2),
3871 !strconcat(OpcodeStr,
3872 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3873 [(set VR256:$dst, (vt (OpNode VR256:$src1, (i8 imm:$src2))))]>;
3874 def Ymi : Ii8<0x70, MRMSrcMem,
3875 (outs VR256:$dst), (ins i256mem:$src1, i8imm:$src2),
3876 !strconcat(OpcodeStr,
3877 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3879 (vt (OpNode (bitconvert (memopv4i64 addr:$src1)),
3880 (i8 imm:$src2))))]>;
3882 } // ExeDomain = SSEPackedInt
3884 let Predicates = [HasAVX] in {
3885 let AddedComplexity = 5 in
3886 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize,
3889 // SSE2 with ImmT == Imm8 and XS prefix.
3890 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
3893 // SSE2 with ImmT == Imm8 and XD prefix.
3894 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
3897 let AddedComplexity = 5 in
3898 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3899 (VPSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3900 // Unary v4f32 shuffle with VPSHUF* in order to fold a load.
3901 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3902 (VPSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3904 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
3906 (VPSHUFDmi addr:$src1, imm:$imm)>;
3907 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
3908 (VPSHUFDmi addr:$src1, imm:$imm)>;
3909 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3910 (VPSHUFDri VR128:$src1, imm:$imm)>;
3911 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3912 (VPSHUFDri VR128:$src1, imm:$imm)>;
3913 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
3914 (VPSHUFHWri VR128:$src, imm:$imm)>;
3915 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
3917 (VPSHUFHWmi addr:$src, imm:$imm)>;
3918 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
3919 (VPSHUFLWri VR128:$src, imm:$imm)>;
3920 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
3922 (VPSHUFLWmi addr:$src, imm:$imm)>;
3925 let Predicates = [HasAVX2] in {
3926 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, X86PShufd>, TB, OpSize, VEX;
3927 defm VPSHUFHW : sse2_pshuffle_y<"vpshufhw", v16i16, X86PShufhw>, XS, VEX;
3928 defm VPSHUFLW : sse2_pshuffle_y<"vpshuflw", v16i16, X86PShuflw>, XD, VEX;
3931 let Predicates = [HasSSE2] in {
3932 let AddedComplexity = 5 in
3933 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
3935 // SSE2 with ImmT == Imm8 and XS prefix.
3936 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
3938 // SSE2 with ImmT == Imm8 and XD prefix.
3939 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
3941 let AddedComplexity = 5 in
3942 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3943 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3944 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3945 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3946 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3948 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
3950 (PSHUFDmi addr:$src1, imm:$imm)>;
3951 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
3952 (PSHUFDmi addr:$src1, imm:$imm)>;
3953 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3954 (PSHUFDri VR128:$src1, imm:$imm)>;
3955 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3956 (PSHUFDri VR128:$src1, imm:$imm)>;
3957 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
3958 (PSHUFHWri VR128:$src, imm:$imm)>;
3959 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
3961 (PSHUFHWmi addr:$src, imm:$imm)>;
3962 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
3963 (PSHUFLWri VR128:$src, imm:$imm)>;
3964 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
3966 (PSHUFLWmi addr:$src, imm:$imm)>;
3969 //===---------------------------------------------------------------------===//
3970 // SSE2 - Packed Integer Unpack Instructions
3971 //===---------------------------------------------------------------------===//
3973 let ExeDomain = SSEPackedInt in {
3974 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
3975 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
3976 def rr : PDI<opc, MRMSrcReg,
3977 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3979 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3980 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3981 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))]>;
3982 def rm : PDI<opc, MRMSrcMem,
3983 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3985 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3986 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3987 [(set VR128:$dst, (OpNode VR128:$src1,
3988 (bc_frag (memopv2i64
3992 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
3993 SDNode OpNode, PatFrag bc_frag> {
3994 def Yrr : PDI<opc, MRMSrcReg,
3995 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
3996 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3997 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
3998 def Yrm : PDI<opc, MRMSrcMem,
3999 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4000 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4001 [(set VR256:$dst, (OpNode VR256:$src1,
4002 (bc_frag (memopv4i64 addr:$src2))))]>;
4005 let Predicates = [HasAVX] in {
4006 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4007 bc_v16i8, 0>, VEX_4V;
4008 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4009 bc_v8i16, 0>, VEX_4V;
4010 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4011 bc_v4i32, 0>, VEX_4V;
4012 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4013 bc_v2i64, 0>, VEX_4V;
4015 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4016 bc_v16i8, 0>, VEX_4V;
4017 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4018 bc_v8i16, 0>, VEX_4V;
4019 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4020 bc_v4i32, 0>, VEX_4V;
4021 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4022 bc_v2i64, 0>, VEX_4V;
4025 let Predicates = [HasAVX2] in {
4026 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4028 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4030 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4032 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4035 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4037 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4039 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4041 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4045 let Constraints = "$src1 = $dst" in {
4046 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4048 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4050 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4052 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4055 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4057 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4059 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4061 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4064 } // ExeDomain = SSEPackedInt
4066 // Patterns for using AVX1 instructions with integer vectors
4067 // Here to give AVX2 priority
4068 let Predicates = [HasAVX] in {
4069 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4070 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
4071 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
4072 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
4073 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4074 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
4075 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
4076 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
4078 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
4079 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
4080 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
4081 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
4082 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
4083 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
4084 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
4085 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
4088 //===---------------------------------------------------------------------===//
4089 // SSE2 - Packed Integer Extract and Insert
4090 //===---------------------------------------------------------------------===//
4092 let ExeDomain = SSEPackedInt in {
4093 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4094 def rri : Ii8<0xC4, MRMSrcReg,
4095 (outs VR128:$dst), (ins VR128:$src1,
4096 GR32:$src2, i32i8imm:$src3),
4098 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4099 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4101 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
4102 def rmi : Ii8<0xC4, MRMSrcMem,
4103 (outs VR128:$dst), (ins VR128:$src1,
4104 i16mem:$src2, i32i8imm:$src3),
4106 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4107 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4109 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4114 let Predicates = [HasAVX] in
4115 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4116 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4117 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4118 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4119 imm:$src2))]>, TB, OpSize, VEX;
4120 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4121 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4122 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4123 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4127 let Predicates = [HasAVX] in {
4128 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4129 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4130 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4131 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4132 []>, TB, OpSize, VEX_4V;
4135 let Constraints = "$src1 = $dst" in
4136 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
4138 } // ExeDomain = SSEPackedInt
4140 //===---------------------------------------------------------------------===//
4141 // SSE2 - Packed Mask Creation
4142 //===---------------------------------------------------------------------===//
4144 let ExeDomain = SSEPackedInt in {
4146 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4147 "pmovmskb\t{$src, $dst|$dst, $src}",
4148 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
4149 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4150 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4152 let Predicates = [HasAVX2] in {
4153 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4154 "pmovmskb\t{$src, $dst|$dst, $src}",
4155 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX;
4156 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4157 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4160 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4161 "pmovmskb\t{$src, $dst|$dst, $src}",
4162 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
4164 } // ExeDomain = SSEPackedInt
4166 //===---------------------------------------------------------------------===//
4167 // SSE2 - Conditional Store
4168 //===---------------------------------------------------------------------===//
4170 let ExeDomain = SSEPackedInt in {
4173 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4174 (ins VR128:$src, VR128:$mask),
4175 "maskmovdqu\t{$mask, $src|$src, $mask}",
4176 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
4178 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4179 (ins VR128:$src, VR128:$mask),
4180 "maskmovdqu\t{$mask, $src|$src, $mask}",
4181 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
4184 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4185 "maskmovdqu\t{$mask, $src|$src, $mask}",
4186 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
4188 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4189 "maskmovdqu\t{$mask, $src|$src, $mask}",
4190 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
4192 } // ExeDomain = SSEPackedInt
4194 //===---------------------------------------------------------------------===//
4195 // SSE2 - Move Doubleword
4196 //===---------------------------------------------------------------------===//
4198 //===---------------------------------------------------------------------===//
4199 // Move Int Doubleword to Packed Double Int
4201 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4202 "movd\t{$src, $dst|$dst, $src}",
4204 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
4205 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4206 "movd\t{$src, $dst|$dst, $src}",
4208 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
4210 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4211 "mov{d|q}\t{$src, $dst|$dst, $src}",
4213 (v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
4214 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4215 "mov{d|q}\t{$src, $dst|$dst, $src}",
4216 [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
4218 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4219 "movd\t{$src, $dst|$dst, $src}",
4221 (v4i32 (scalar_to_vector GR32:$src)))]>;
4222 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4223 "movd\t{$src, $dst|$dst, $src}",
4225 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
4226 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4227 "mov{d|q}\t{$src, $dst|$dst, $src}",
4229 (v2i64 (scalar_to_vector GR64:$src)))]>;
4230 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4231 "mov{d|q}\t{$src, $dst|$dst, $src}",
4232 [(set FR64:$dst, (bitconvert GR64:$src))]>;
4234 //===---------------------------------------------------------------------===//
4235 // Move Int Doubleword to Single Scalar
4237 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4238 "movd\t{$src, $dst|$dst, $src}",
4239 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
4241 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4242 "movd\t{$src, $dst|$dst, $src}",
4243 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
4245 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4246 "movd\t{$src, $dst|$dst, $src}",
4247 [(set FR32:$dst, (bitconvert GR32:$src))]>;
4249 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4250 "movd\t{$src, $dst|$dst, $src}",
4251 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
4253 //===---------------------------------------------------------------------===//
4254 // Move Packed Doubleword Int to Packed Double Int
4256 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4257 "movd\t{$src, $dst|$dst, $src}",
4258 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4260 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4261 (ins i32mem:$dst, VR128:$src),
4262 "movd\t{$src, $dst|$dst, $src}",
4263 [(store (i32 (vector_extract (v4i32 VR128:$src),
4264 (iPTR 0))), addr:$dst)]>, VEX;
4265 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4266 "movd\t{$src, $dst|$dst, $src}",
4267 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4269 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4270 "movd\t{$src, $dst|$dst, $src}",
4271 [(store (i32 (vector_extract (v4i32 VR128:$src),
4272 (iPTR 0))), addr:$dst)]>;
4274 //===---------------------------------------------------------------------===//
4275 // Move Packed Doubleword Int first element to Doubleword Int
4277 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4278 "mov{d|q}\t{$src, $dst|$dst, $src}",
4279 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4281 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4283 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4284 "mov{d|q}\t{$src, $dst|$dst, $src}",
4285 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4288 //===---------------------------------------------------------------------===//
4289 // Bitcast FR64 <-> GR64
4291 let Predicates = [HasAVX] in
4292 def VMOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4293 "vmovq\t{$src, $dst|$dst, $src}",
4294 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4296 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4297 "mov{d|q}\t{$src, $dst|$dst, $src}",
4298 [(set GR64:$dst, (bitconvert FR64:$src))]>, VEX;
4299 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4300 "movq\t{$src, $dst|$dst, $src}",
4301 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>,
4304 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4305 "movq\t{$src, $dst|$dst, $src}",
4306 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
4307 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4308 "mov{d|q}\t{$src, $dst|$dst, $src}",
4309 [(set GR64:$dst, (bitconvert FR64:$src))]>;
4310 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4311 "movq\t{$src, $dst|$dst, $src}",
4312 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
4314 //===---------------------------------------------------------------------===//
4315 // Move Scalar Single to Double Int
4317 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4318 "movd\t{$src, $dst|$dst, $src}",
4319 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
4320 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4321 "movd\t{$src, $dst|$dst, $src}",
4322 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
4323 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4324 "movd\t{$src, $dst|$dst, $src}",
4325 [(set GR32:$dst, (bitconvert FR32:$src))]>;
4326 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4327 "movd\t{$src, $dst|$dst, $src}",
4328 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
4330 //===---------------------------------------------------------------------===//
4331 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4333 let AddedComplexity = 15 in {
4334 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4335 "movd\t{$src, $dst|$dst, $src}",
4336 [(set VR128:$dst, (v4i32 (X86vzmovl
4337 (v4i32 (scalar_to_vector GR32:$src)))))]>,
4339 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4340 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4341 [(set VR128:$dst, (v2i64 (X86vzmovl
4342 (v2i64 (scalar_to_vector GR64:$src)))))]>,
4345 let AddedComplexity = 15 in {
4346 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4347 "movd\t{$src, $dst|$dst, $src}",
4348 [(set VR128:$dst, (v4i32 (X86vzmovl
4349 (v4i32 (scalar_to_vector GR32:$src)))))]>;
4350 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4351 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4352 [(set VR128:$dst, (v2i64 (X86vzmovl
4353 (v2i64 (scalar_to_vector GR64:$src)))))]>;
4356 let AddedComplexity = 20 in {
4357 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4358 "movd\t{$src, $dst|$dst, $src}",
4360 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4361 (loadi32 addr:$src))))))]>,
4363 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4364 "movd\t{$src, $dst|$dst, $src}",
4366 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4367 (loadi32 addr:$src))))))]>;
4370 let Predicates = [HasAVX] in {
4371 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4372 let AddedComplexity = 20 in {
4373 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4374 (VMOVZDI2PDIrm addr:$src)>;
4375 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4376 (VMOVZDI2PDIrm addr:$src)>;
4378 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4379 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4380 (v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
4381 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4382 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4383 (v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
4384 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4387 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4388 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4389 (MOVZDI2PDIrm addr:$src)>;
4390 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4391 (MOVZDI2PDIrm addr:$src)>;
4394 // These are the correct encodings of the instructions so that we know how to
4395 // read correct assembly, even though we continue to emit the wrong ones for
4396 // compatibility with Darwin's buggy assembler.
4397 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4398 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4399 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4400 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4401 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4402 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4403 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4404 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4405 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4406 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4407 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4408 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4410 //===---------------------------------------------------------------------===//
4411 // SSE2 - Move Quadword
4412 //===---------------------------------------------------------------------===//
4414 //===---------------------------------------------------------------------===//
4415 // Move Quadword Int to Packed Quadword Int
4417 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4418 "vmovq\t{$src, $dst|$dst, $src}",
4420 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4421 VEX, Requires<[HasAVX]>;
4422 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4423 "movq\t{$src, $dst|$dst, $src}",
4425 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4426 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
4428 //===---------------------------------------------------------------------===//
4429 // Move Packed Quadword Int to Quadword Int
4431 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4432 "movq\t{$src, $dst|$dst, $src}",
4433 [(store (i64 (vector_extract (v2i64 VR128:$src),
4434 (iPTR 0))), addr:$dst)]>, VEX;
4435 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4436 "movq\t{$src, $dst|$dst, $src}",
4437 [(store (i64 (vector_extract (v2i64 VR128:$src),
4438 (iPTR 0))), addr:$dst)]>;
4440 //===---------------------------------------------------------------------===//
4441 // Store / copy lower 64-bits of a XMM register.
4443 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4444 "movq\t{$src, $dst|$dst, $src}",
4445 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4446 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4447 "movq\t{$src, $dst|$dst, $src}",
4448 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
4450 let AddedComplexity = 20 in
4451 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4452 "vmovq\t{$src, $dst|$dst, $src}",
4454 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4455 (loadi64 addr:$src))))))]>,
4456 XS, VEX, Requires<[HasAVX]>;
4458 let AddedComplexity = 20 in
4459 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4460 "movq\t{$src, $dst|$dst, $src}",
4462 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4463 (loadi64 addr:$src))))))]>,
4464 XS, Requires<[HasSSE2]>;
4466 let Predicates = [HasAVX], AddedComplexity = 20 in {
4467 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4468 (VMOVZQI2PQIrm addr:$src)>;
4469 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4470 (VMOVZQI2PQIrm addr:$src)>;
4471 def : Pat<(v2i64 (X86vzload addr:$src)),
4472 (VMOVZQI2PQIrm addr:$src)>;
4475 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4476 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4477 (MOVZQI2PQIrm addr:$src)>;
4478 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4479 (MOVZQI2PQIrm addr:$src)>;
4480 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4483 let Predicates = [HasAVX] in {
4484 def : Pat<(v4i64 (X86vzload addr:$src)),
4485 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4488 //===---------------------------------------------------------------------===//
4489 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4490 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4492 let AddedComplexity = 15 in
4493 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4494 "vmovq\t{$src, $dst|$dst, $src}",
4495 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4496 XS, VEX, Requires<[HasAVX]>;
4497 let AddedComplexity = 15 in
4498 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4499 "movq\t{$src, $dst|$dst, $src}",
4500 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4501 XS, Requires<[HasSSE2]>;
4503 let AddedComplexity = 20 in
4504 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4505 "vmovq\t{$src, $dst|$dst, $src}",
4506 [(set VR128:$dst, (v2i64 (X86vzmovl
4507 (loadv2i64 addr:$src))))]>,
4508 XS, VEX, Requires<[HasAVX]>;
4509 let AddedComplexity = 20 in {
4510 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4511 "movq\t{$src, $dst|$dst, $src}",
4512 [(set VR128:$dst, (v2i64 (X86vzmovl
4513 (loadv2i64 addr:$src))))]>,
4514 XS, Requires<[HasSSE2]>;
4517 let AddedComplexity = 20 in {
4518 let Predicates = [HasAVX] in {
4519 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4520 (VMOVZPQILo2PQIrm addr:$src)>;
4521 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4522 (VMOVZPQILo2PQIrr VR128:$src)>;
4524 let Predicates = [HasSSE2] in {
4525 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4526 (MOVZPQILo2PQIrm addr:$src)>;
4527 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4528 (MOVZPQILo2PQIrr VR128:$src)>;
4532 // Instructions to match in the assembler
4533 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4534 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4535 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4536 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4537 // Recognize "movd" with GR64 destination, but encode as a "movq"
4538 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4539 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4541 // Instructions for the disassembler
4542 // xr = XMM register
4545 let Predicates = [HasAVX] in
4546 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4547 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4548 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4549 "movq\t{$src, $dst|$dst, $src}", []>, XS;
4551 //===---------------------------------------------------------------------===//
4552 // SSE3 - Conversion Instructions
4553 //===---------------------------------------------------------------------===//
4555 // Convert Packed Double FP to Packed DW Integers
4556 let Predicates = [HasAVX] in {
4557 // The assembler can recognize rr 256-bit instructions by seeing a ymm
4558 // register, but the same isn't true when using memory operands instead.
4559 // Provide other assembly rr and rm forms to address this explicitly.
4560 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4561 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4562 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4563 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4566 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4567 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4568 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4569 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4572 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4573 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
4574 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
4575 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4578 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4579 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4580 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4581 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4583 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
4584 (VCVTTPD2DQYrr VR256:$src)>;
4585 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
4586 (VCVTTPD2DQYrm addr:$src)>;
4588 // Convert Packed DW Integers to Packed Double FP
4589 let Predicates = [HasAVX] in {
4590 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4591 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4592 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4593 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4594 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
4595 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4596 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
4597 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4600 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4601 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4602 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4603 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4605 // AVX 256-bit register conversion intrinsics
4606 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
4607 (VCVTDQ2PDYrr VR128:$src)>;
4608 def : Pat<(int_x86_avx_cvtdq2_pd_256 (bitconvert (memopv2i64 addr:$src))),
4609 (VCVTDQ2PDYrm addr:$src)>;
4611 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
4612 (VCVTPD2DQYrr VR256:$src)>;
4613 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
4614 (VCVTPD2DQYrm addr:$src)>;
4616 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
4617 (VCVTDQ2PDYrr VR128:$src)>;
4618 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
4619 (VCVTDQ2PDYrm addr:$src)>;
4621 //===---------------------------------------------------------------------===//
4622 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4623 //===---------------------------------------------------------------------===//
4624 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4625 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4626 X86MemOperand x86memop> {
4627 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4628 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4629 [(set RC:$dst, (vt (OpNode RC:$src)))]>;
4630 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4631 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4632 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>;
4635 let Predicates = [HasAVX] in {
4636 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4637 v4f32, VR128, memopv4f32, f128mem>, VEX;
4638 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4639 v4f32, VR128, memopv4f32, f128mem>, VEX;
4640 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4641 v8f32, VR256, memopv8f32, f256mem>, VEX;
4642 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4643 v8f32, VR256, memopv8f32, f256mem>, VEX;
4645 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4646 memopv4f32, f128mem>;
4647 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4648 memopv4f32, f128mem>;
4650 let Predicates = [HasAVX] in {
4651 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4652 (VMOVSHDUPrr VR128:$src)>;
4653 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4654 (VMOVSHDUPrm addr:$src)>;
4655 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4656 (VMOVSLDUPrr VR128:$src)>;
4657 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4658 (VMOVSLDUPrm addr:$src)>;
4659 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4660 (VMOVSHDUPYrr VR256:$src)>;
4661 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4662 (VMOVSHDUPYrm addr:$src)>;
4663 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4664 (VMOVSLDUPYrr VR256:$src)>;
4665 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4666 (VMOVSLDUPYrm addr:$src)>;
4669 let Predicates = [HasSSE3] in {
4670 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4671 (MOVSHDUPrr VR128:$src)>;
4672 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4673 (MOVSHDUPrm addr:$src)>;
4674 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4675 (MOVSLDUPrr VR128:$src)>;
4676 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4677 (MOVSLDUPrm addr:$src)>;
4680 //===---------------------------------------------------------------------===//
4681 // SSE3 - Replicate Double FP - MOVDDUP
4682 //===---------------------------------------------------------------------===//
4684 multiclass sse3_replicate_dfp<string OpcodeStr> {
4685 let neverHasSideEffects = 1 in
4686 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4687 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4689 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4690 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4693 (scalar_to_vector (loadf64 addr:$src)))))]>;
4696 // FIXME: Merge with above classe when there're patterns for the ymm version
4697 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4698 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4699 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4700 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>;
4701 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4702 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4705 (scalar_to_vector (loadf64 addr:$src)))))]>;
4708 let Predicates = [HasAVX] in {
4709 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4710 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
4713 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4715 let Predicates = [HasAVX] in {
4716 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4717 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4718 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4719 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4720 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4721 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4722 def : Pat<(X86Movddup (bc_v2f64
4723 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4724 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4727 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4728 (VMOVDDUPYrm addr:$src)>;
4729 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4730 (VMOVDDUPYrm addr:$src)>;
4731 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4732 (VMOVDDUPYrm addr:$src)>;
4733 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4734 (VMOVDDUPYrr VR256:$src)>;
4737 let Predicates = [HasSSE3] in {
4738 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4739 (MOVDDUPrm addr:$src)>;
4740 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4741 (MOVDDUPrm addr:$src)>;
4742 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4743 (MOVDDUPrm addr:$src)>;
4744 def : Pat<(X86Movddup (bc_v2f64
4745 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4746 (MOVDDUPrm addr:$src)>;
4749 //===---------------------------------------------------------------------===//
4750 // SSE3 - Move Unaligned Integer
4751 //===---------------------------------------------------------------------===//
4753 let Predicates = [HasAVX] in {
4754 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4755 "vlddqu\t{$src, $dst|$dst, $src}",
4756 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4757 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4758 "vlddqu\t{$src, $dst|$dst, $src}",
4759 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
4761 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4762 "lddqu\t{$src, $dst|$dst, $src}",
4763 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
4765 //===---------------------------------------------------------------------===//
4766 // SSE3 - Arithmetic
4767 //===---------------------------------------------------------------------===//
4769 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4770 X86MemOperand x86memop, bit Is2Addr = 1> {
4771 def rr : I<0xD0, MRMSrcReg,
4772 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4774 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4775 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4776 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
4777 def rm : I<0xD0, MRMSrcMem,
4778 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4780 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4781 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4782 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
4785 let Predicates = [HasAVX] in {
4786 let ExeDomain = SSEPackedSingle in {
4787 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4788 f128mem, 0>, TB, XD, VEX_4V;
4789 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4790 f256mem, 0>, TB, XD, VEX_4V;
4792 let ExeDomain = SSEPackedDouble in {
4793 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4794 f128mem, 0>, TB, OpSize, VEX_4V;
4795 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
4796 f256mem, 0>, TB, OpSize, VEX_4V;
4799 let Constraints = "$src1 = $dst", Predicates = [HasSSE3] in {
4800 let ExeDomain = SSEPackedSingle in
4801 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
4803 let ExeDomain = SSEPackedDouble in
4804 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
4805 f128mem>, TB, OpSize;
4808 //===---------------------------------------------------------------------===//
4809 // SSE3 Instructions
4810 //===---------------------------------------------------------------------===//
4813 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4814 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4815 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4817 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4818 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4819 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))]>;
4821 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4823 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4824 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4825 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))]>;
4827 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4828 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4829 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4831 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4832 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4833 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))]>;
4835 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4837 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4838 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4839 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))]>;
4842 let Predicates = [HasAVX] in {
4843 let ExeDomain = SSEPackedSingle in {
4844 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
4845 X86fhadd, 0>, VEX_4V;
4846 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
4847 X86fhsub, 0>, VEX_4V;
4848 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
4849 X86fhadd, 0>, VEX_4V;
4850 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
4851 X86fhsub, 0>, VEX_4V;
4853 let ExeDomain = SSEPackedDouble in {
4854 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
4855 X86fhadd, 0>, VEX_4V;
4856 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
4857 X86fhsub, 0>, VEX_4V;
4858 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
4859 X86fhadd, 0>, VEX_4V;
4860 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
4861 X86fhsub, 0>, VEX_4V;
4865 let Constraints = "$src1 = $dst" in {
4866 let ExeDomain = SSEPackedSingle in {
4867 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
4868 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
4870 let ExeDomain = SSEPackedDouble in {
4871 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
4872 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
4876 //===---------------------------------------------------------------------===//
4877 // SSSE3 - Packed Absolute Instructions
4878 //===---------------------------------------------------------------------===//
4881 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
4882 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
4883 Intrinsic IntId128> {
4884 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4886 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4887 [(set VR128:$dst, (IntId128 VR128:$src))]>,
4890 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4892 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4895 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
4898 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
4899 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
4900 Intrinsic IntId256> {
4901 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
4903 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4904 [(set VR256:$dst, (IntId256 VR256:$src))]>,
4907 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
4909 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4912 (bitconvert (memopv4i64 addr:$src))))]>, OpSize;
4915 let Predicates = [HasAVX] in {
4916 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
4917 int_x86_ssse3_pabs_b_128>, VEX;
4918 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
4919 int_x86_ssse3_pabs_w_128>, VEX;
4920 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
4921 int_x86_ssse3_pabs_d_128>, VEX;
4924 let Predicates = [HasAVX2] in {
4925 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
4926 int_x86_avx2_pabs_b>, VEX;
4927 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
4928 int_x86_avx2_pabs_w>, VEX;
4929 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
4930 int_x86_avx2_pabs_d>, VEX;
4933 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
4934 int_x86_ssse3_pabs_b_128>;
4935 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
4936 int_x86_ssse3_pabs_w_128>;
4937 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
4938 int_x86_ssse3_pabs_d_128>;
4940 //===---------------------------------------------------------------------===//
4941 // SSSE3 - Packed Binary Operator Instructions
4942 //===---------------------------------------------------------------------===//
4944 /// SS3I_binop_rm - Simple SSSE3 bin op
4945 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4946 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
4947 X86MemOperand x86memop, bit Is2Addr = 1> {
4948 let isCommutable = 1 in
4949 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
4950 (ins RC:$src1, RC:$src2),
4952 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4953 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4954 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
4956 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
4957 (ins RC:$src1, x86memop:$src2),
4959 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4960 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4962 (OpVT (OpNode RC:$src1,
4963 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
4966 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
4967 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
4968 Intrinsic IntId128, bit Is2Addr = 1> {
4969 let isCommutable = 1 in
4970 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4971 (ins VR128:$src1, VR128:$src2),
4973 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4974 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4975 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4977 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4978 (ins VR128:$src1, i128mem:$src2),
4980 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4981 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4983 (IntId128 VR128:$src1,
4984 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
4987 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
4988 Intrinsic IntId256> {
4989 let isCommutable = 1 in
4990 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
4991 (ins VR256:$src1, VR256:$src2),
4992 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4993 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
4995 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
4996 (ins VR256:$src1, i256mem:$src2),
4997 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4999 (IntId256 VR256:$src1,
5000 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5003 let ImmT = NoImm, Predicates = [HasAVX] in {
5004 let isCommutable = 0 in {
5005 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5006 memopv2i64, i128mem, 0>, VEX_4V;
5007 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5008 memopv2i64, i128mem, 0>, VEX_4V;
5009 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5010 memopv2i64, i128mem, 0>, VEX_4V;
5011 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5012 memopv2i64, i128mem, 0>, VEX_4V;
5013 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5014 memopv2i64, i128mem, 0>, VEX_4V;
5015 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5016 memopv2i64, i128mem, 0>, VEX_4V;
5017 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5018 memopv2i64, i128mem, 0>, VEX_4V;
5019 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5020 memopv2i64, i128mem, 0>, VEX_4V;
5021 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5022 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
5023 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5024 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
5025 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5026 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
5028 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5029 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
5032 let ImmT = NoImm, Predicates = [HasAVX2] in {
5033 let isCommutable = 0 in {
5034 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5035 memopv4i64, i256mem, 0>, VEX_4V;
5036 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5037 memopv4i64, i256mem, 0>, VEX_4V;
5038 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5039 memopv4i64, i256mem, 0>, VEX_4V;
5040 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5041 memopv4i64, i256mem, 0>, VEX_4V;
5042 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5043 memopv4i64, i256mem, 0>, VEX_4V;
5044 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5045 memopv4i64, i256mem, 0>, VEX_4V;
5046 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5047 memopv4i64, i256mem, 0>, VEX_4V;
5048 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5049 memopv4i64, i256mem, 0>, VEX_4V;
5050 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5051 int_x86_avx2_phadd_sw>, VEX_4V;
5052 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5053 int_x86_avx2_phsub_sw>, VEX_4V;
5054 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5055 int_x86_avx2_pmadd_ub_sw>, VEX_4V;
5057 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5058 int_x86_avx2_pmul_hr_sw>, VEX_4V;
5061 // None of these have i8 immediate fields.
5062 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5063 let isCommutable = 0 in {
5064 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5065 memopv2i64, i128mem>;
5066 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5067 memopv2i64, i128mem>;
5068 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5069 memopv2i64, i128mem>;
5070 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5071 memopv2i64, i128mem>;
5072 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5073 memopv2i64, i128mem>;
5074 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5075 memopv2i64, i128mem>;
5076 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5077 memopv2i64, i128mem>;
5078 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5079 memopv2i64, i128mem>;
5080 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5081 int_x86_ssse3_phadd_sw_128>;
5082 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5083 int_x86_ssse3_phsub_sw_128>;
5084 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5085 int_x86_ssse3_pmadd_ub_sw_128>;
5087 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5088 int_x86_ssse3_pmul_hr_sw_128>;
5091 //===---------------------------------------------------------------------===//
5092 // SSSE3 - Packed Align Instruction Patterns
5093 //===---------------------------------------------------------------------===//
5095 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
5096 let neverHasSideEffects = 1 in {
5097 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5098 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5100 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5102 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5105 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5106 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5108 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5110 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5115 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
5116 let neverHasSideEffects = 1 in {
5117 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5118 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5120 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5123 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5124 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5126 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5131 let Predicates = [HasAVX] in
5132 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5133 let Predicates = [HasAVX2] in
5134 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V;
5135 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
5136 defm PALIGN : ssse3_palign<"palignr">;
5138 let Predicates = [HasAVX2] in {
5139 def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5140 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5141 def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5142 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5143 def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5144 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5145 def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5146 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5149 let Predicates = [HasAVX] in {
5150 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5151 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5152 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5153 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5154 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5155 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5156 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5157 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5160 let Predicates = [HasSSSE3] in {
5161 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5162 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5163 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5164 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5165 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5166 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5167 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5168 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5171 //===---------------------------------------------------------------------===//
5172 // SSSE3 - Thread synchronization
5173 //===---------------------------------------------------------------------===//
5175 let usesCustomInserter = 1 in {
5176 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5177 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5178 Requires<[HasSSE3]>;
5179 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
5180 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>,
5181 Requires<[HasSSE3]>;
5184 let Uses = [EAX, ECX, EDX] in
5185 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
5186 Requires<[HasSSE3]>;
5187 let Uses = [ECX, EAX] in
5188 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
5189 Requires<[HasSSE3]>;
5191 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5192 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5194 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5195 Requires<[In32BitMode]>;
5196 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5197 Requires<[In64BitMode]>;
5199 //===----------------------------------------------------------------------===//
5200 // SSE4.1 - Packed Move with Sign/Zero Extend
5201 //===----------------------------------------------------------------------===//
5203 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5204 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5205 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5206 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5208 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5209 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5211 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5215 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5217 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5218 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5219 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5221 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5222 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5223 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5226 let Predicates = [HasAVX] in {
5227 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5229 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5231 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5233 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5235 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5237 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5241 let Predicates = [HasAVX2] in {
5242 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5243 int_x86_avx2_pmovsxbw>, VEX;
5244 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5245 int_x86_avx2_pmovsxwd>, VEX;
5246 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5247 int_x86_avx2_pmovsxdq>, VEX;
5248 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5249 int_x86_avx2_pmovzxbw>, VEX;
5250 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5251 int_x86_avx2_pmovzxwd>, VEX;
5252 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5253 int_x86_avx2_pmovzxdq>, VEX;
5256 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5257 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5258 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5259 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5260 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5261 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5263 let Predicates = [HasAVX] in {
5264 // Common patterns involving scalar load.
5265 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5266 (VPMOVSXBWrm addr:$src)>;
5267 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5268 (VPMOVSXBWrm addr:$src)>;
5270 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5271 (VPMOVSXWDrm addr:$src)>;
5272 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5273 (VPMOVSXWDrm addr:$src)>;
5275 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5276 (VPMOVSXDQrm addr:$src)>;
5277 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5278 (VPMOVSXDQrm addr:$src)>;
5280 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5281 (VPMOVZXBWrm addr:$src)>;
5282 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5283 (VPMOVZXBWrm addr:$src)>;
5285 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5286 (VPMOVZXWDrm addr:$src)>;
5287 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5288 (VPMOVZXWDrm addr:$src)>;
5290 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5291 (VPMOVZXDQrm addr:$src)>;
5292 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5293 (VPMOVZXDQrm addr:$src)>;
5296 let Predicates = [HasSSE41] in {
5297 // Common patterns involving scalar load.
5298 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5299 (PMOVSXBWrm addr:$src)>;
5300 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5301 (PMOVSXBWrm addr:$src)>;
5303 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5304 (PMOVSXWDrm addr:$src)>;
5305 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5306 (PMOVSXWDrm addr:$src)>;
5308 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5309 (PMOVSXDQrm addr:$src)>;
5310 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5311 (PMOVSXDQrm addr:$src)>;
5313 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5314 (PMOVZXBWrm addr:$src)>;
5315 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5316 (PMOVZXBWrm addr:$src)>;
5318 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5319 (PMOVZXWDrm addr:$src)>;
5320 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5321 (PMOVZXWDrm addr:$src)>;
5323 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5324 (PMOVZXDQrm addr:$src)>;
5325 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5326 (PMOVZXDQrm addr:$src)>;
5329 let Predicates = [HasAVX] in {
5330 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5331 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5334 let Predicates = [HasSSE41] in {
5335 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5336 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5340 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5341 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5342 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5343 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5345 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5346 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5348 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5352 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5354 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5355 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5356 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5358 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5359 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5361 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5365 let Predicates = [HasAVX] in {
5366 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5368 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5370 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5372 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5376 let Predicates = [HasAVX2] in {
5377 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5378 int_x86_avx2_pmovsxbd>, VEX;
5379 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5380 int_x86_avx2_pmovsxwq>, VEX;
5381 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5382 int_x86_avx2_pmovzxbd>, VEX;
5383 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5384 int_x86_avx2_pmovzxwq>, VEX;
5387 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5388 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5389 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5390 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5392 let Predicates = [HasAVX] in {
5393 // Common patterns involving scalar load
5394 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5395 (VPMOVSXBDrm addr:$src)>;
5396 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5397 (VPMOVSXWQrm addr:$src)>;
5399 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5400 (VPMOVZXBDrm addr:$src)>;
5401 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5402 (VPMOVZXWQrm addr:$src)>;
5405 let Predicates = [HasSSE41] in {
5406 // Common patterns involving scalar load
5407 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5408 (PMOVSXBDrm addr:$src)>;
5409 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5410 (PMOVSXWQrm addr:$src)>;
5412 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5413 (PMOVZXBDrm addr:$src)>;
5414 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5415 (PMOVZXWQrm addr:$src)>;
5418 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5419 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5420 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5421 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5423 // Expecting a i16 load any extended to i32 value.
5424 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5425 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5426 [(set VR128:$dst, (IntId (bitconvert
5427 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5431 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5433 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5434 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5435 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5437 // Expecting a i16 load any extended to i32 value.
5438 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5439 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5440 [(set VR256:$dst, (IntId (bitconvert
5441 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5445 let Predicates = [HasAVX] in {
5446 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5448 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5451 let Predicates = [HasAVX2] in {
5452 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5453 int_x86_avx2_pmovsxbq>, VEX;
5454 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5455 int_x86_avx2_pmovzxbq>, VEX;
5457 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5458 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5460 let Predicates = [HasAVX] in {
5461 // Common patterns involving scalar load
5462 def : Pat<(int_x86_sse41_pmovsxbq
5463 (bitconvert (v4i32 (X86vzmovl
5464 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5465 (VPMOVSXBQrm addr:$src)>;
5467 def : Pat<(int_x86_sse41_pmovzxbq
5468 (bitconvert (v4i32 (X86vzmovl
5469 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5470 (VPMOVZXBQrm addr:$src)>;
5473 let Predicates = [HasSSE41] in {
5474 // Common patterns involving scalar load
5475 def : Pat<(int_x86_sse41_pmovsxbq
5476 (bitconvert (v4i32 (X86vzmovl
5477 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5478 (PMOVSXBQrm addr:$src)>;
5480 def : Pat<(int_x86_sse41_pmovzxbq
5481 (bitconvert (v4i32 (X86vzmovl
5482 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5483 (PMOVZXBQrm addr:$src)>;
5486 //===----------------------------------------------------------------------===//
5487 // SSE4.1 - Extract Instructions
5488 //===----------------------------------------------------------------------===//
5490 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5491 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5492 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5493 (ins VR128:$src1, i32i8imm:$src2),
5494 !strconcat(OpcodeStr,
5495 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5496 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5498 let neverHasSideEffects = 1, mayStore = 1 in
5499 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5500 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5501 !strconcat(OpcodeStr,
5502 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5505 // There's an AssertZext in the way of writing the store pattern
5506 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5509 let Predicates = [HasAVX] in {
5510 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5511 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5512 (ins VR128:$src1, i32i8imm:$src2),
5513 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5516 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5519 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5520 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5521 let neverHasSideEffects = 1, mayStore = 1 in
5522 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5523 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5524 !strconcat(OpcodeStr,
5525 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5528 // There's an AssertZext in the way of writing the store pattern
5529 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5532 let Predicates = [HasAVX] in
5533 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5535 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5538 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5539 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5540 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5541 (ins VR128:$src1, i32i8imm:$src2),
5542 !strconcat(OpcodeStr,
5543 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5545 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5546 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5547 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5548 !strconcat(OpcodeStr,
5549 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5550 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5551 addr:$dst)]>, OpSize;
5554 let Predicates = [HasAVX] in
5555 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5557 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5559 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5560 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5561 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5562 (ins VR128:$src1, i32i8imm:$src2),
5563 !strconcat(OpcodeStr,
5564 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5566 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5567 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5568 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5569 !strconcat(OpcodeStr,
5570 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5571 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5572 addr:$dst)]>, OpSize, REX_W;
5575 let Predicates = [HasAVX] in
5576 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5578 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5580 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5582 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5583 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5584 (ins VR128:$src1, i32i8imm:$src2),
5585 !strconcat(OpcodeStr,
5586 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5588 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5590 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5591 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5592 !strconcat(OpcodeStr,
5593 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5594 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5595 addr:$dst)]>, OpSize;
5598 let ExeDomain = SSEPackedSingle in {
5599 let Predicates = [HasAVX] in {
5600 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5601 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5602 (ins VR128:$src1, i32i8imm:$src2),
5603 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
5606 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
5609 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
5610 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5613 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5615 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5618 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5619 Requires<[HasSSE41]>;
5621 //===----------------------------------------------------------------------===//
5622 // SSE4.1 - Insert Instructions
5623 //===----------------------------------------------------------------------===//
5625 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5626 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5627 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5629 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5631 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5633 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5634 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5635 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
5637 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5639 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5641 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
5642 imm:$src3))]>, OpSize;
5645 let Predicates = [HasAVX] in
5646 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
5647 let Constraints = "$src1 = $dst" in
5648 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
5650 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
5651 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5652 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5654 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5656 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5658 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
5660 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5661 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
5663 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5665 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5667 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
5668 imm:$src3)))]>, OpSize;
5671 let Predicates = [HasAVX] in
5672 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
5673 let Constraints = "$src1 = $dst" in
5674 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
5676 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
5677 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5678 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
5680 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5682 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5684 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
5686 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5687 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
5689 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5691 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5693 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
5694 imm:$src3)))]>, OpSize;
5697 let Predicates = [HasAVX] in
5698 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
5699 let Constraints = "$src1 = $dst" in
5700 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
5702 // insertps has a few different modes, there's the first two here below which
5703 // are optimized inserts that won't zero arbitrary elements in the destination
5704 // vector. The next one matches the intrinsic and could zero arbitrary elements
5705 // in the target vector.
5706 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
5707 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5708 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
5710 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5712 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5714 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
5716 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5717 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
5719 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5721 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5723 (X86insrtps VR128:$src1,
5724 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
5725 imm:$src3))]>, OpSize;
5728 let ExeDomain = SSEPackedSingle in {
5729 let Predicates = [HasAVX] in
5730 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
5731 let Constraints = "$src1 = $dst" in
5732 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
5735 //===----------------------------------------------------------------------===//
5736 // SSE4.1 - Round Instructions
5737 //===----------------------------------------------------------------------===//
5739 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
5740 X86MemOperand x86memop, RegisterClass RC,
5741 PatFrag mem_frag32, PatFrag mem_frag64,
5742 Intrinsic V4F32Int, Intrinsic V2F64Int> {
5743 let ExeDomain = SSEPackedSingle in {
5744 // Intrinsic operation, reg.
5745 // Vector intrinsic operation, reg
5746 def PSr : SS4AIi8<opcps, MRMSrcReg,
5747 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5748 !strconcat(OpcodeStr,
5749 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5750 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
5753 // Vector intrinsic operation, mem
5754 def PSm : SS4AIi8<opcps, MRMSrcMem,
5755 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5756 !strconcat(OpcodeStr,
5757 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5759 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
5761 } // ExeDomain = SSEPackedSingle
5763 let ExeDomain = SSEPackedDouble in {
5764 // Vector intrinsic operation, reg
5765 def PDr : SS4AIi8<opcpd, MRMSrcReg,
5766 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5767 !strconcat(OpcodeStr,
5768 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5769 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
5772 // Vector intrinsic operation, mem
5773 def PDm : SS4AIi8<opcpd, MRMSrcMem,
5774 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5775 !strconcat(OpcodeStr,
5776 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5778 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
5780 } // ExeDomain = SSEPackedDouble
5783 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
5786 Intrinsic F64Int, bit Is2Addr = 1> {
5787 let ExeDomain = GenericDomain in {
5789 def SSr : SS4AIi8<opcss, MRMSrcReg,
5790 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
5792 !strconcat(OpcodeStr,
5793 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5794 !strconcat(OpcodeStr,
5795 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5798 // Intrinsic operation, reg.
5799 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
5800 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5802 !strconcat(OpcodeStr,
5803 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5804 !strconcat(OpcodeStr,
5805 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5806 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
5809 // Intrinsic operation, mem.
5810 def SSm : SS4AIi8<opcss, MRMSrcMem,
5811 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
5813 !strconcat(OpcodeStr,
5814 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5815 !strconcat(OpcodeStr,
5816 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5818 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
5822 def SDr : SS4AIi8<opcsd, MRMSrcReg,
5823 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
5825 !strconcat(OpcodeStr,
5826 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5827 !strconcat(OpcodeStr,
5828 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5831 // Intrinsic operation, reg.
5832 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
5833 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5835 !strconcat(OpcodeStr,
5836 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5837 !strconcat(OpcodeStr,
5838 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5839 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
5842 // Intrinsic operation, mem.
5843 def SDm : SS4AIi8<opcsd, MRMSrcMem,
5844 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
5846 !strconcat(OpcodeStr,
5847 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5848 !strconcat(OpcodeStr,
5849 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5851 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
5853 } // ExeDomain = GenericDomain
5856 // FP round - roundss, roundps, roundsd, roundpd
5857 let Predicates = [HasAVX] in {
5859 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
5860 memopv4f32, memopv2f64,
5861 int_x86_sse41_round_ps,
5862 int_x86_sse41_round_pd>, VEX;
5863 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
5864 memopv8f32, memopv4f64,
5865 int_x86_avx_round_ps_256,
5866 int_x86_avx_round_pd_256>, VEX;
5867 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
5868 int_x86_sse41_round_ss,
5869 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
5871 def : Pat<(ffloor FR32:$src),
5872 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
5873 def : Pat<(f64 (ffloor FR64:$src)),
5874 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
5875 def : Pat<(f32 (fnearbyint FR32:$src)),
5876 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
5877 def : Pat<(f64 (fnearbyint FR64:$src)),
5878 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
5879 def : Pat<(f32 (fceil FR32:$src)),
5880 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
5881 def : Pat<(f64 (fceil FR64:$src)),
5882 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
5883 def : Pat<(f32 (frint FR32:$src)),
5884 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
5885 def : Pat<(f64 (frint FR64:$src)),
5886 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
5887 def : Pat<(f32 (ftrunc FR32:$src)),
5888 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
5889 def : Pat<(f64 (ftrunc FR64:$src)),
5890 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
5893 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
5894 memopv4f32, memopv2f64,
5895 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
5896 let Constraints = "$src1 = $dst" in
5897 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
5898 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
5900 def : Pat<(ffloor FR32:$src),
5901 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
5902 def : Pat<(f64 (ffloor FR64:$src)),
5903 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
5904 def : Pat<(f32 (fnearbyint FR32:$src)),
5905 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
5906 def : Pat<(f64 (fnearbyint FR64:$src)),
5907 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
5908 def : Pat<(f32 (fceil FR32:$src)),
5909 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
5910 def : Pat<(f64 (fceil FR64:$src)),
5911 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
5912 def : Pat<(f32 (frint FR32:$src)),
5913 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
5914 def : Pat<(f64 (frint FR64:$src)),
5915 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
5916 def : Pat<(f32 (ftrunc FR32:$src)),
5917 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
5918 def : Pat<(f64 (ftrunc FR64:$src)),
5919 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
5921 //===----------------------------------------------------------------------===//
5922 // SSE4.1 - Packed Bit Test
5923 //===----------------------------------------------------------------------===//
5925 // ptest instruction we'll lower to this in X86ISelLowering primarily from
5926 // the intel intrinsic that corresponds to this.
5927 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5928 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5929 "vptest\t{$src2, $src1|$src1, $src2}",
5930 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5932 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5933 "vptest\t{$src2, $src1|$src1, $src2}",
5934 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5937 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
5938 "vptest\t{$src2, $src1|$src1, $src2}",
5939 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
5941 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
5942 "vptest\t{$src2, $src1|$src1, $src2}",
5943 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
5947 let Defs = [EFLAGS] in {
5948 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5949 "ptest\t{$src2, $src1|$src1, $src2}",
5950 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5952 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5953 "ptest\t{$src2, $src1|$src1, $src2}",
5954 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5958 // The bit test instructions below are AVX only
5959 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
5960 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
5961 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
5962 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5963 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
5964 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
5965 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5966 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
5970 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5971 let ExeDomain = SSEPackedSingle in {
5972 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
5973 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
5975 let ExeDomain = SSEPackedDouble in {
5976 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
5977 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
5981 //===----------------------------------------------------------------------===//
5982 // SSE4.1 - Misc Instructions
5983 //===----------------------------------------------------------------------===//
5985 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
5986 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
5987 "popcnt{w}\t{$src, $dst|$dst, $src}",
5988 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
5990 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
5991 "popcnt{w}\t{$src, $dst|$dst, $src}",
5992 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
5993 (implicit EFLAGS)]>, OpSize, XS;
5995 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
5996 "popcnt{l}\t{$src, $dst|$dst, $src}",
5997 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
5999 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6000 "popcnt{l}\t{$src, $dst|$dst, $src}",
6001 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6002 (implicit EFLAGS)]>, XS;
6004 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6005 "popcnt{q}\t{$src, $dst|$dst, $src}",
6006 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6008 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6009 "popcnt{q}\t{$src, $dst|$dst, $src}",
6010 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6011 (implicit EFLAGS)]>, XS;
6016 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6017 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6018 Intrinsic IntId128> {
6019 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6021 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6022 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6023 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6025 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6028 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6031 let Predicates = [HasAVX] in
6032 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6033 int_x86_sse41_phminposuw>, VEX;
6034 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6035 int_x86_sse41_phminposuw>;
6037 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6038 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6039 Intrinsic IntId128, bit Is2Addr = 1> {
6040 let isCommutable = 1 in
6041 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6042 (ins VR128:$src1, VR128:$src2),
6044 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6045 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6046 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6047 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6048 (ins VR128:$src1, i128mem:$src2),
6050 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6051 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6053 (IntId128 VR128:$src1,
6054 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6057 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6058 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6059 Intrinsic IntId256> {
6060 let isCommutable = 1 in
6061 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6062 (ins VR256:$src1, VR256:$src2),
6063 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6064 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6065 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6066 (ins VR256:$src1, i256mem:$src2),
6067 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6069 (IntId256 VR256:$src1,
6070 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6073 let Predicates = [HasAVX] in {
6074 let isCommutable = 0 in
6075 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6077 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
6079 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
6081 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
6083 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
6085 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
6087 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
6089 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
6091 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
6093 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6097 let Predicates = [HasAVX2] in {
6098 let isCommutable = 0 in
6099 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6100 int_x86_avx2_packusdw>, VEX_4V;
6101 defm VPMINSB : SS41I_binop_rm_int_y<0x38, "vpminsb",
6102 int_x86_avx2_pmins_b>, VEX_4V;
6103 defm VPMINSD : SS41I_binop_rm_int_y<0x39, "vpminsd",
6104 int_x86_avx2_pmins_d>, VEX_4V;
6105 defm VPMINUD : SS41I_binop_rm_int_y<0x3B, "vpminud",
6106 int_x86_avx2_pminu_d>, VEX_4V;
6107 defm VPMINUW : SS41I_binop_rm_int_y<0x3A, "vpminuw",
6108 int_x86_avx2_pminu_w>, VEX_4V;
6109 defm VPMAXSB : SS41I_binop_rm_int_y<0x3C, "vpmaxsb",
6110 int_x86_avx2_pmaxs_b>, VEX_4V;
6111 defm VPMAXSD : SS41I_binop_rm_int_y<0x3D, "vpmaxsd",
6112 int_x86_avx2_pmaxs_d>, VEX_4V;
6113 defm VPMAXUD : SS41I_binop_rm_int_y<0x3F, "vpmaxud",
6114 int_x86_avx2_pmaxu_d>, VEX_4V;
6115 defm VPMAXUW : SS41I_binop_rm_int_y<0x3E, "vpmaxuw",
6116 int_x86_avx2_pmaxu_w>, VEX_4V;
6117 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6118 int_x86_avx2_pmul_dq>, VEX_4V;
6121 let Constraints = "$src1 = $dst" in {
6122 let isCommutable = 0 in
6123 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6124 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
6125 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
6126 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
6127 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
6128 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
6129 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
6130 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
6131 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
6132 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6135 /// SS48I_binop_rm - Simple SSE41 binary operator.
6136 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6137 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6138 X86MemOperand x86memop, bit Is2Addr = 1> {
6139 let isCommutable = 1 in
6140 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6141 (ins RC:$src1, RC:$src2),
6143 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6144 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6145 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6146 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6147 (ins RC:$src1, x86memop:$src2),
6149 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6150 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6152 (OpVT (OpNode RC:$src1,
6153 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6156 let Predicates = [HasAVX] in {
6157 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6158 memopv2i64, i128mem, 0>, VEX_4V;
6159 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6160 memopv2i64, i128mem, 0>, VEX_4V;
6162 let Predicates = [HasAVX2] in {
6163 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6164 memopv4i64, i256mem, 0>, VEX_4V;
6165 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6166 memopv4i64, i256mem, 0>, VEX_4V;
6169 let Constraints = "$src1 = $dst" in {
6170 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6171 memopv2i64, i128mem>;
6172 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6173 memopv2i64, i128mem>;
6176 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6177 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6178 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6179 X86MemOperand x86memop, bit Is2Addr = 1> {
6180 let isCommutable = 1 in
6181 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6182 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6184 !strconcat(OpcodeStr,
6185 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6186 !strconcat(OpcodeStr,
6187 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6188 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6190 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6191 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6193 !strconcat(OpcodeStr,
6194 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6195 !strconcat(OpcodeStr,
6196 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6199 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6203 let Predicates = [HasAVX] in {
6204 let isCommutable = 0 in {
6205 let ExeDomain = SSEPackedSingle in {
6206 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6207 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6208 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6209 int_x86_avx_blend_ps_256, VR256, memopv8f32, i256mem, 0>, VEX_4V;
6211 let ExeDomain = SSEPackedDouble in {
6212 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6213 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6214 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6215 int_x86_avx_blend_pd_256, VR256, memopv4f64, i256mem, 0>, VEX_4V;
6217 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6218 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6219 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6220 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6222 let ExeDomain = SSEPackedSingle in
6223 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6224 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6225 let ExeDomain = SSEPackedDouble in
6226 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6227 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6228 let ExeDomain = SSEPackedSingle in
6229 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6230 VR256, memopv8f32, i256mem, 0>, VEX_4V;
6233 let Predicates = [HasAVX2] in {
6234 let isCommutable = 0 in {
6235 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6236 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6237 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6238 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6242 let Constraints = "$src1 = $dst" in {
6243 let isCommutable = 0 in {
6244 let ExeDomain = SSEPackedSingle in
6245 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6246 VR128, memopv4f32, i128mem>;
6247 let ExeDomain = SSEPackedDouble in
6248 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6249 VR128, memopv2f64, i128mem>;
6250 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6251 VR128, memopv2i64, i128mem>;
6252 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6253 VR128, memopv2i64, i128mem>;
6255 let ExeDomain = SSEPackedSingle in
6256 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6257 VR128, memopv4f32, i128mem>;
6258 let ExeDomain = SSEPackedDouble in
6259 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6260 VR128, memopv2f64, i128mem>;
6263 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6264 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6265 RegisterClass RC, X86MemOperand x86memop,
6266 PatFrag mem_frag, Intrinsic IntId> {
6267 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6268 (ins RC:$src1, RC:$src2, RC:$src3),
6269 !strconcat(OpcodeStr,
6270 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6271 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6272 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6274 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6275 (ins RC:$src1, x86memop:$src2, RC:$src3),
6276 !strconcat(OpcodeStr,
6277 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6279 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6281 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6284 let Predicates = [HasAVX] in {
6285 let ExeDomain = SSEPackedDouble in {
6286 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
6287 memopv2f64, int_x86_sse41_blendvpd>;
6288 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
6289 memopv4f64, int_x86_avx_blendv_pd_256>;
6290 } // ExeDomain = SSEPackedDouble
6291 let ExeDomain = SSEPackedSingle in {
6292 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
6293 memopv4f32, int_x86_sse41_blendvps>;
6294 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
6295 memopv8f32, int_x86_avx_blendv_ps_256>;
6296 } // ExeDomain = SSEPackedSingle
6297 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6298 memopv2i64, int_x86_sse41_pblendvb>;
6301 let Predicates = [HasAVX2] in {
6302 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6303 memopv4i64, int_x86_avx2_pblendvb>;
6306 let Predicates = [HasAVX] in {
6307 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6308 (v16i8 VR128:$src2))),
6309 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6310 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6311 (v4i32 VR128:$src2))),
6312 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6313 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6314 (v4f32 VR128:$src2))),
6315 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6316 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6317 (v2i64 VR128:$src2))),
6318 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6319 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6320 (v2f64 VR128:$src2))),
6321 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6322 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6323 (v8i32 VR256:$src2))),
6324 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6325 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6326 (v8f32 VR256:$src2))),
6327 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6328 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6329 (v4i64 VR256:$src2))),
6330 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6331 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6332 (v4f64 VR256:$src2))),
6333 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6336 let Predicates = [HasAVX2] in {
6337 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6338 (v32i8 VR256:$src2))),
6339 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6342 /// SS41I_ternary_int - SSE 4.1 ternary operator
6343 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6344 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6346 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6347 (ins VR128:$src1, VR128:$src2),
6348 !strconcat(OpcodeStr,
6349 "\t{$src2, $dst|$dst, $src2}"),
6350 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6353 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6354 (ins VR128:$src1, i128mem:$src2),
6355 !strconcat(OpcodeStr,
6356 "\t{$src2, $dst|$dst, $src2}"),
6359 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
6363 let ExeDomain = SSEPackedDouble in
6364 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64,
6365 int_x86_sse41_blendvpd>;
6366 let ExeDomain = SSEPackedSingle in
6367 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32,
6368 int_x86_sse41_blendvps>;
6369 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64,
6370 int_x86_sse41_pblendvb>;
6372 let Predicates = [HasSSE41] in {
6373 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6374 (v16i8 VR128:$src2))),
6375 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6376 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6377 (v4i32 VR128:$src2))),
6378 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6379 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6380 (v4f32 VR128:$src2))),
6381 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6382 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6383 (v2i64 VR128:$src2))),
6384 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6385 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6386 (v2f64 VR128:$src2))),
6387 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6390 let Predicates = [HasAVX] in
6391 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6392 "vmovntdqa\t{$src, $dst|$dst, $src}",
6393 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6395 let Predicates = [HasAVX2] in
6396 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
6397 "vmovntdqa\t{$src, $dst|$dst, $src}",
6398 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
6400 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6401 "movntdqa\t{$src, $dst|$dst, $src}",
6402 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6405 //===----------------------------------------------------------------------===//
6406 // SSE4.2 - Compare Instructions
6407 //===----------------------------------------------------------------------===//
6409 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
6410 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6411 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6412 X86MemOperand x86memop, bit Is2Addr = 1> {
6413 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
6414 (ins RC:$src1, RC:$src2),
6416 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6417 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6418 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6420 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
6421 (ins RC:$src1, x86memop:$src2),
6423 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6424 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6426 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
6429 let Predicates = [HasAVX] in
6430 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
6431 memopv2i64, i128mem, 0>, VEX_4V;
6433 let Predicates = [HasAVX2] in
6434 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
6435 memopv4i64, i256mem, 0>, VEX_4V;
6437 let Constraints = "$src1 = $dst" in
6438 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
6439 memopv2i64, i128mem>;
6441 //===----------------------------------------------------------------------===//
6442 // SSE4.2 - String/text Processing Instructions
6443 //===----------------------------------------------------------------------===//
6445 // Packed Compare Implicit Length Strings, Return Mask
6446 multiclass pseudo_pcmpistrm<string asm> {
6447 def REG : PseudoI<(outs VR128:$dst),
6448 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6449 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6451 def MEM : PseudoI<(outs VR128:$dst),
6452 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6453 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6454 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6457 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6458 let AddedComplexity = 1 in
6459 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6460 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
6463 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1, Predicates = [HasAVX] in {
6464 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6465 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6466 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6468 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6469 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6470 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6473 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
6474 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6475 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6476 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6478 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6479 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6480 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6483 // Packed Compare Explicit Length Strings, Return Mask
6484 multiclass pseudo_pcmpestrm<string asm> {
6485 def REG : PseudoI<(outs VR128:$dst),
6486 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6487 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6488 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6489 def MEM : PseudoI<(outs VR128:$dst),
6490 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6491 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6492 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6495 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6496 let AddedComplexity = 1 in
6497 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6498 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
6501 let Predicates = [HasAVX],
6502 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6503 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6504 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6505 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6507 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6508 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6509 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6512 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6513 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6514 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6515 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6517 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6518 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6519 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6522 // Packed Compare Implicit Length Strings, Return Index
6523 let Defs = [ECX, EFLAGS] in {
6524 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
6525 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6526 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6527 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6528 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
6529 (implicit EFLAGS)]>, OpSize;
6530 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6531 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6532 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6533 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
6534 (implicit EFLAGS)]>, OpSize;
6538 let Predicates = [HasAVX] in {
6539 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
6541 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
6543 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
6545 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
6547 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
6549 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
6553 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
6554 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
6555 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
6556 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
6557 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
6558 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
6560 // Packed Compare Explicit Length Strings, Return Index
6561 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
6562 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
6563 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6564 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6565 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6566 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
6567 (implicit EFLAGS)]>, OpSize;
6568 def rm : SS42AI<0x61, MRMSrcMem, (outs),
6569 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6570 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6572 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
6573 (implicit EFLAGS)]>, OpSize;
6577 let Predicates = [HasAVX] in {
6578 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
6580 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
6582 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
6584 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
6586 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
6588 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
6592 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
6593 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
6594 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
6595 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
6596 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
6597 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
6599 //===----------------------------------------------------------------------===//
6600 // SSE4.2 - CRC Instructions
6601 //===----------------------------------------------------------------------===//
6603 // No CRC instructions have AVX equivalents
6605 // crc intrinsic instruction
6606 // This set of instructions are only rm, the only difference is the size
6608 let Constraints = "$src1 = $dst" in {
6609 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
6610 (ins GR32:$src1, i8mem:$src2),
6611 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6613 (int_x86_sse42_crc32_32_8 GR32:$src1,
6614 (load addr:$src2)))]>;
6615 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
6616 (ins GR32:$src1, GR8:$src2),
6617 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6619 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
6620 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6621 (ins GR32:$src1, i16mem:$src2),
6622 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6624 (int_x86_sse42_crc32_32_16 GR32:$src1,
6625 (load addr:$src2)))]>,
6627 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6628 (ins GR32:$src1, GR16:$src2),
6629 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6631 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
6633 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6634 (ins GR32:$src1, i32mem:$src2),
6635 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6637 (int_x86_sse42_crc32_32_32 GR32:$src1,
6638 (load addr:$src2)))]>;
6639 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6640 (ins GR32:$src1, GR32:$src2),
6641 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6643 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
6644 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
6645 (ins GR64:$src1, i8mem:$src2),
6646 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6648 (int_x86_sse42_crc32_64_8 GR64:$src1,
6649 (load addr:$src2)))]>,
6651 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
6652 (ins GR64:$src1, GR8:$src2),
6653 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6655 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
6657 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
6658 (ins GR64:$src1, i64mem:$src2),
6659 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6661 (int_x86_sse42_crc32_64_64 GR64:$src1,
6662 (load addr:$src2)))]>,
6664 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
6665 (ins GR64:$src1, GR64:$src2),
6666 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6668 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
6672 //===----------------------------------------------------------------------===//
6673 // AES-NI Instructions
6674 //===----------------------------------------------------------------------===//
6676 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
6677 Intrinsic IntId128, bit Is2Addr = 1> {
6678 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
6679 (ins VR128:$src1, VR128:$src2),
6681 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6682 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6683 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
6685 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
6686 (ins VR128:$src1, i128mem:$src2),
6688 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6689 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6691 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
6694 // Perform One Round of an AES Encryption/Decryption Flow
6695 let Predicates = [HasAVX, HasAES] in {
6696 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
6697 int_x86_aesni_aesenc, 0>, VEX_4V;
6698 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
6699 int_x86_aesni_aesenclast, 0>, VEX_4V;
6700 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
6701 int_x86_aesni_aesdec, 0>, VEX_4V;
6702 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
6703 int_x86_aesni_aesdeclast, 0>, VEX_4V;
6706 let Constraints = "$src1 = $dst" in {
6707 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
6708 int_x86_aesni_aesenc>;
6709 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
6710 int_x86_aesni_aesenclast>;
6711 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
6712 int_x86_aesni_aesdec>;
6713 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
6714 int_x86_aesni_aesdeclast>;
6717 // Perform the AES InvMixColumn Transformation
6718 let Predicates = [HasAVX, HasAES] in {
6719 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6721 "vaesimc\t{$src1, $dst|$dst, $src1}",
6723 (int_x86_aesni_aesimc VR128:$src1))]>,
6725 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
6726 (ins i128mem:$src1),
6727 "vaesimc\t{$src1, $dst|$dst, $src1}",
6728 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
6731 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6733 "aesimc\t{$src1, $dst|$dst, $src1}",
6735 (int_x86_aesni_aesimc VR128:$src1))]>,
6737 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
6738 (ins i128mem:$src1),
6739 "aesimc\t{$src1, $dst|$dst, $src1}",
6740 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
6743 // AES Round Key Generation Assist
6744 let Predicates = [HasAVX, HasAES] in {
6745 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
6746 (ins VR128:$src1, i8imm:$src2),
6747 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6749 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
6751 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
6752 (ins i128mem:$src1, i8imm:$src2),
6753 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6755 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
6758 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
6759 (ins VR128:$src1, i8imm:$src2),
6760 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6762 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
6764 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
6765 (ins i128mem:$src1, i8imm:$src2),
6766 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6768 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
6771 //===----------------------------------------------------------------------===//
6772 // CLMUL Instructions
6773 //===----------------------------------------------------------------------===//
6775 // Carry-less Multiplication instructions
6776 let neverHasSideEffects = 1 in {
6777 // AVX carry-less Multiplication instructions
6778 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
6779 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6780 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6784 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
6785 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6786 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6789 let Constraints = "$src1 = $dst" in {
6790 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
6791 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6792 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
6796 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
6797 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6798 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
6800 } // Constraints = "$src1 = $dst"
6801 } // neverHasSideEffects = 1
6804 multiclass pclmul_alias<string asm, int immop> {
6805 def : InstAlias<!strconcat("pclmul", asm,
6806 "dq {$src, $dst|$dst, $src}"),
6807 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
6809 def : InstAlias<!strconcat("pclmul", asm,
6810 "dq {$src, $dst|$dst, $src}"),
6811 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
6813 def : InstAlias<!strconcat("vpclmul", asm,
6814 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
6815 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
6817 def : InstAlias<!strconcat("vpclmul", asm,
6818 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
6819 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
6821 defm : pclmul_alias<"hqhq", 0x11>;
6822 defm : pclmul_alias<"hqlq", 0x01>;
6823 defm : pclmul_alias<"lqhq", 0x10>;
6824 defm : pclmul_alias<"lqlq", 0x00>;
6826 //===----------------------------------------------------------------------===//
6828 //===----------------------------------------------------------------------===//
6830 //===----------------------------------------------------------------------===//
6831 // VBROADCAST - Load from memory and broadcast to all elements of the
6832 // destination operand
6834 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
6835 X86MemOperand x86memop, Intrinsic Int> :
6836 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
6837 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6838 [(set RC:$dst, (Int addr:$src))]>, VEX;
6840 // AVX2 adds register forms
6841 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
6843 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
6844 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6845 [(set RC:$dst, (Int VR128:$src))]>, VEX;
6847 let ExeDomain = SSEPackedSingle in {
6848 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
6849 int_x86_avx_vbroadcast_ss>;
6850 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
6851 int_x86_avx_vbroadcast_ss_256>;
6853 let ExeDomain = SSEPackedDouble in
6854 def VBROADCASTSDrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
6855 int_x86_avx_vbroadcast_sd_256>;
6856 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
6857 int_x86_avx_vbroadcastf128_pd_256>;
6859 let ExeDomain = SSEPackedSingle in {
6860 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
6861 int_x86_avx2_vbroadcast_ss_ps>;
6862 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
6863 int_x86_avx2_vbroadcast_ss_ps_256>;
6865 let ExeDomain = SSEPackedDouble in
6866 def VBROADCASTSDrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
6867 int_x86_avx2_vbroadcast_sd_pd_256>;
6869 let Predicates = [HasAVX2] in
6870 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
6871 int_x86_avx2_vbroadcasti128>;
6873 let Predicates = [HasAVX] in
6874 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
6875 (VBROADCASTF128 addr:$src)>;
6878 //===----------------------------------------------------------------------===//
6879 // VINSERTF128 - Insert packed floating-point values
6881 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
6882 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
6883 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
6884 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6887 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
6888 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
6889 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6893 let Predicates = [HasAVX] in {
6894 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
6895 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6896 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
6897 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6898 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
6899 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6902 //===----------------------------------------------------------------------===//
6903 // VEXTRACTF128 - Extract packed floating-point values
6905 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
6906 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
6907 (ins VR256:$src1, i8imm:$src2),
6908 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6911 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
6912 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
6913 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6917 let Predicates = [HasAVX] in {
6918 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
6919 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6920 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
6921 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6922 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
6923 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6926 //===----------------------------------------------------------------------===//
6927 // VMASKMOV - Conditional SIMD Packed Loads and Stores
6929 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
6930 Intrinsic IntLd, Intrinsic IntLd256,
6931 Intrinsic IntSt, Intrinsic IntSt256> {
6932 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
6933 (ins VR128:$src1, f128mem:$src2),
6934 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6935 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
6937 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
6938 (ins VR256:$src1, f256mem:$src2),
6939 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6940 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
6942 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
6943 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
6944 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6945 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
6946 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
6947 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
6948 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6949 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
6952 let ExeDomain = SSEPackedSingle in
6953 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
6954 int_x86_avx_maskload_ps,
6955 int_x86_avx_maskload_ps_256,
6956 int_x86_avx_maskstore_ps,
6957 int_x86_avx_maskstore_ps_256>;
6958 let ExeDomain = SSEPackedDouble in
6959 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
6960 int_x86_avx_maskload_pd,
6961 int_x86_avx_maskload_pd_256,
6962 int_x86_avx_maskstore_pd,
6963 int_x86_avx_maskstore_pd_256>;
6965 //===----------------------------------------------------------------------===//
6966 // VPERMIL - Permute Single and Double Floating-Point Values
6968 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
6969 RegisterClass RC, X86MemOperand x86memop_f,
6970 X86MemOperand x86memop_i, PatFrag i_frag,
6971 Intrinsic IntVar, ValueType vt> {
6972 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
6973 (ins RC:$src1, RC:$src2),
6974 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6975 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
6976 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
6977 (ins RC:$src1, x86memop_i:$src2),
6978 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6979 [(set RC:$dst, (IntVar RC:$src1,
6980 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
6982 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
6983 (ins RC:$src1, i8imm:$src2),
6984 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6985 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
6986 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
6987 (ins x86memop_f:$src1, i8imm:$src2),
6988 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6990 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
6993 let ExeDomain = SSEPackedSingle in {
6994 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
6995 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
6996 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
6997 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>;
6999 let ExeDomain = SSEPackedDouble in {
7000 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7001 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7002 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7003 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>;
7006 let Predicates = [HasAVX] in {
7007 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7008 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7009 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7010 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7011 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7013 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7014 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7015 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7017 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7018 (VPERMILPDri VR128:$src1, imm:$imm)>;
7019 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7020 (VPERMILPDmi addr:$src1, imm:$imm)>;
7023 //===----------------------------------------------------------------------===//
7024 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7026 let ExeDomain = SSEPackedSingle in {
7027 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7028 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7029 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7030 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7031 (i8 imm:$src3))))]>, VEX_4V;
7032 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7033 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7034 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7035 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7036 (i8 imm:$src3)))]>, VEX_4V;
7039 let Predicates = [HasAVX] in {
7040 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7041 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7042 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7043 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7044 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7045 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7046 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7047 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7048 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7049 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7051 def : Pat<(v8f32 (X86VPerm2x128 VR256:$src1,
7052 (memopv8f32 addr:$src2), (i8 imm:$imm))),
7053 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7054 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7055 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7056 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7057 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7058 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7059 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7060 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7061 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7062 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7063 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7064 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7065 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7066 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7067 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7068 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7071 //===----------------------------------------------------------------------===//
7072 // VZERO - Zero YMM registers
7074 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7075 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7076 // Zero All YMM registers
7077 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7078 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7080 // Zero Upper bits of YMM registers
7081 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7082 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7085 //===----------------------------------------------------------------------===//
7086 // Half precision conversion instructions
7087 //===----------------------------------------------------------------------===//
7088 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7089 let Predicates = [HasAVX, HasF16C] in {
7090 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7091 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7092 [(set RC:$dst, (Int VR128:$src))]>,
7094 let neverHasSideEffects = 1, mayLoad = 1 in
7095 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7096 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7100 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7101 let Predicates = [HasAVX, HasF16C] in {
7102 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7103 (ins RC:$src1, i32i8imm:$src2),
7104 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7105 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7107 let neverHasSideEffects = 1, mayLoad = 1 in
7108 def mr : Ii8<0x1D, MRMDestMem, (outs x86memop:$dst),
7109 (ins RC:$src1, i32i8imm:$src2),
7110 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7115 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7116 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>;
7117 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7118 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>;
7120 //===----------------------------------------------------------------------===//
7121 // AVX2 Instructions
7122 //===----------------------------------------------------------------------===//
7124 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7125 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7126 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7127 X86MemOperand x86memop> {
7128 let isCommutable = 1 in
7129 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7130 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7131 !strconcat(OpcodeStr,
7132 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7133 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7135 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7136 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7137 !strconcat(OpcodeStr,
7138 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7141 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7145 let isCommutable = 0 in {
7146 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7147 VR128, memopv2i64, i128mem>;
7148 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7149 VR256, memopv4i64, i256mem>;
7152 //===----------------------------------------------------------------------===//
7153 // VPBROADCAST - Load from memory and broadcast to all elements of the
7154 // destination operand
7156 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7157 X86MemOperand x86memop, PatFrag ld_frag,
7158 Intrinsic Int128, Intrinsic Int256> {
7159 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7160 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7161 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7162 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7163 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7165 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7166 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7167 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7168 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX;
7169 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7170 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7172 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7175 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7176 int_x86_avx2_pbroadcastb_128,
7177 int_x86_avx2_pbroadcastb_256>;
7178 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7179 int_x86_avx2_pbroadcastw_128,
7180 int_x86_avx2_pbroadcastw_256>;
7181 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7182 int_x86_avx2_pbroadcastd_128,
7183 int_x86_avx2_pbroadcastd_256>;
7184 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7185 int_x86_avx2_pbroadcastq_128,
7186 int_x86_avx2_pbroadcastq_256>;
7188 let Predicates = [HasAVX2] in {
7189 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7190 (VPBROADCASTBrm addr:$src)>;
7191 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7192 (VPBROADCASTBYrm addr:$src)>;
7193 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7194 (VPBROADCASTWrm addr:$src)>;
7195 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7196 (VPBROADCASTWYrm addr:$src)>;
7197 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7198 (VPBROADCASTDrm addr:$src)>;
7199 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7200 (VPBROADCASTDYrm addr:$src)>;
7201 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
7202 (VPBROADCASTQrm addr:$src)>;
7203 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7204 (VPBROADCASTQYrm addr:$src)>;
7207 // AVX1 broadcast patterns
7208 let Predicates = [HasAVX] in {
7209 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7210 (VBROADCASTSSYrm addr:$src)>;
7211 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7212 (VBROADCASTSDrm addr:$src)>;
7213 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
7214 (VBROADCASTSSYrm addr:$src)>;
7215 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
7216 (VBROADCASTSDrm addr:$src)>;
7218 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
7219 (VBROADCASTSSrm addr:$src)>;
7220 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7221 (VBROADCASTSSrm addr:$src)>;
7224 //===----------------------------------------------------------------------===//
7225 // VPERM - Permute instructions
7228 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7230 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7231 (ins VR256:$src1, VR256:$src2),
7232 !strconcat(OpcodeStr,
7233 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7234 [(set VR256:$dst, (Int VR256:$src1, VR256:$src2))]>, VEX_4V;
7235 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7236 (ins VR256:$src1, i256mem:$src2),
7237 !strconcat(OpcodeStr,
7238 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7239 [(set VR256:$dst, (Int VR256:$src1,
7240 (bitconvert (mem_frag addr:$src2))))]>,
7244 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, int_x86_avx2_permd>;
7245 let ExeDomain = SSEPackedSingle in
7246 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, int_x86_avx2_permps>;
7248 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7250 def Yrr : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7251 (ins VR256:$src1, i8imm:$src2),
7252 !strconcat(OpcodeStr,
7253 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7254 [(set VR256:$dst, (Int VR256:$src1, imm:$src2))]>, VEX;
7255 def Yrm : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
7256 (ins i256mem:$src1, i8imm:$src2),
7257 !strconcat(OpcodeStr,
7258 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7259 [(set VR256:$dst, (Int (mem_frag addr:$src1), imm:$src2))]>,
7263 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, int_x86_avx2_permq>,
7265 let ExeDomain = SSEPackedDouble in
7266 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, int_x86_avx2_permpd>,
7269 //===----------------------------------------------------------------------===//
7270 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
7272 let AddedComplexity = 1 in {
7273 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7274 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7275 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7276 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7277 (i8 imm:$src3))))]>, VEX_4V;
7278 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
7279 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7280 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7281 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
7282 (i8 imm:$src3)))]>, VEX_4V;
7285 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7286 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7287 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7288 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7289 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7290 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7291 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7293 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
7295 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7296 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7297 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7298 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7299 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
7301 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7305 //===----------------------------------------------------------------------===//
7306 // VINSERTI128 - Insert packed integer values
7308 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7309 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7310 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7312 (int_x86_avx2_vinserti128 VR256:$src1, VR128:$src2, imm:$src3))]>,
7314 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
7315 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
7316 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7318 (int_x86_avx2_vinserti128 VR256:$src1, (memopv2i64 addr:$src2),
7319 imm:$src3))]>, VEX_4V;
7321 let Predicates = [HasAVX2] in {
7322 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7324 (VINSERTI128rr VR256:$src1, VR128:$src2,
7325 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7326 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7328 (VINSERTI128rr VR256:$src1, VR128:$src2,
7329 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7330 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7332 (VINSERTI128rr VR256:$src1, VR128:$src2,
7333 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7334 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7336 (VINSERTI128rr VR256:$src1, VR128:$src2,
7337 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7341 let Predicates = [HasAVX] in {
7342 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7344 (VINSERTF128rr VR256:$src1, VR128:$src2,
7345 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7346 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7348 (VINSERTF128rr VR256:$src1, VR128:$src2,
7349 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7350 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7352 (VINSERTF128rr VR256:$src1, VR128:$src2,
7353 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7354 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7356 (VINSERTF128rr VR256:$src1, VR128:$src2,
7357 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7358 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7360 (VINSERTF128rr VR256:$src1, VR128:$src2,
7361 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7362 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7364 (VINSERTF128rr VR256:$src1, VR128:$src2,
7365 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7368 //===----------------------------------------------------------------------===//
7369 // VEXTRACTI128 - Extract packed integer values
7371 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
7372 (ins VR256:$src1, i8imm:$src2),
7373 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7375 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
7377 let neverHasSideEffects = 1, mayStore = 1 in
7378 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
7379 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
7380 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, VEX;
7382 let Predicates = [HasAVX2] in {
7383 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7384 (v2i64 (VEXTRACTI128rr
7385 (v4i64 VR256:$src1),
7386 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7387 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7388 (v4i32 (VEXTRACTI128rr
7389 (v8i32 VR256:$src1),
7390 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7391 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7392 (v8i16 (VEXTRACTI128rr
7393 (v16i16 VR256:$src1),
7394 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7395 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7396 (v16i8 (VEXTRACTI128rr
7397 (v32i8 VR256:$src1),
7398 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7402 let Predicates = [HasAVX] in {
7403 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7404 (v4f32 (VEXTRACTF128rr
7405 (v8f32 VR256:$src1),
7406 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7407 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7408 (v2f64 (VEXTRACTF128rr
7409 (v4f64 VR256:$src1),
7410 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7411 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7412 (v2i64 (VEXTRACTF128rr
7413 (v4i64 VR256:$src1),
7414 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7415 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7416 (v4i32 (VEXTRACTF128rr
7417 (v8i32 VR256:$src1),
7418 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7419 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7420 (v8i16 (VEXTRACTF128rr
7421 (v16i16 VR256:$src1),
7422 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7423 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7424 (v16i8 (VEXTRACTF128rr
7425 (v32i8 VR256:$src1),
7426 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7429 //===----------------------------------------------------------------------===//
7430 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
7432 multiclass avx2_pmovmask<string OpcodeStr,
7433 Intrinsic IntLd128, Intrinsic IntLd256,
7434 Intrinsic IntSt128, Intrinsic IntSt256> {
7435 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
7436 (ins VR128:$src1, i128mem:$src2),
7437 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7438 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
7439 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
7440 (ins VR256:$src1, i256mem:$src2),
7441 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7442 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>, VEX_4V;
7443 def mr : AVX28I<0x8e, MRMDestMem, (outs),
7444 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
7445 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7446 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7447 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
7448 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
7449 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7450 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7453 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
7454 int_x86_avx2_maskload_d,
7455 int_x86_avx2_maskload_d_256,
7456 int_x86_avx2_maskstore_d,
7457 int_x86_avx2_maskstore_d_256>;
7458 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
7459 int_x86_avx2_maskload_q,
7460 int_x86_avx2_maskload_q_256,
7461 int_x86_avx2_maskstore_q,
7462 int_x86_avx2_maskstore_q_256>, VEX_W;
7465 //===----------------------------------------------------------------------===//
7466 // Variable Bit Shifts
7468 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
7469 ValueType vt128, ValueType vt256> {
7470 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
7471 (ins VR128:$src1, VR128:$src2),
7472 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7474 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
7476 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
7477 (ins VR128:$src1, i128mem:$src2),
7478 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7480 (vt128 (OpNode VR128:$src1,
7481 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
7483 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7484 (ins VR256:$src1, VR256:$src2),
7485 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7487 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
7489 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7490 (ins VR256:$src1, i256mem:$src2),
7491 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7493 (vt256 (OpNode VR256:$src1,
7494 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
7498 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
7499 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
7500 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
7501 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
7502 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;