1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 def SSE_BIT_ITINS_P : OpndItins<
124 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
127 let Sched = WriteVecALU in {
128 def SSE_INTALU_ITINS_P : OpndItins<
129 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
132 def SSE_INTALUQ_ITINS_P : OpndItins<
133 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
137 let Sched = WriteVecIMul in
138 def SSE_INTMUL_ITINS_P : OpndItins<
139 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
142 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
143 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
146 def SSE_MOVA_ITINS : OpndItins<
147 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
150 def SSE_MOVU_ITINS : OpndItins<
151 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
154 def SSE_DPPD_ITINS : OpndItins<
155 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
158 def SSE_DPPS_ITINS : OpndItins<
159 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
162 def DEFAULT_ITINS : OpndItins<
163 IIC_ALU_NONMEM, IIC_ALU_MEM
166 def SSE_EXTRACT_ITINS : OpndItins<
167 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
170 def SSE_INSERT_ITINS : OpndItins<
171 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
174 def SSE_MPSADBW_ITINS : OpndItins<
175 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
178 def SSE_PMULLD_ITINS : OpndItins<
179 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
182 //===----------------------------------------------------------------------===//
183 // SSE 1 & 2 Instructions Classes
184 //===----------------------------------------------------------------------===//
186 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
187 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
188 RegisterClass RC, X86MemOperand x86memop,
191 let isCommutable = 1 in {
192 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
194 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
195 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
196 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
197 Sched<[itins.Sched]>;
199 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
201 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
202 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
203 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
204 Sched<[itins.Sched.Folded, ReadAfterLd]>;
207 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
208 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
209 string asm, string SSEVer, string FPSizeStr,
210 Operand memopr, ComplexPattern mem_cpat,
213 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
215 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
216 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
217 [(set RC:$dst, (!cast<Intrinsic>(
218 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
219 RC:$src1, RC:$src2))], itins.rr>,
220 Sched<[itins.Sched]>;
221 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
223 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
224 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
225 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
226 SSEVer, "_", OpcodeStr, FPSizeStr))
227 RC:$src1, mem_cpat:$src2))], itins.rm>,
228 Sched<[itins.Sched.Folded, ReadAfterLd]>;
231 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
232 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
233 RegisterClass RC, ValueType vt,
234 X86MemOperand x86memop, PatFrag mem_frag,
235 Domain d, OpndItins itins, bit Is2Addr = 1> {
236 let isCommutable = 1 in
237 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
239 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
240 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
241 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
242 Sched<[itins.Sched]>;
244 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
246 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
247 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
248 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
250 Sched<[itins.Sched.Folded, ReadAfterLd]>;
253 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
254 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
255 string OpcodeStr, X86MemOperand x86memop,
256 list<dag> pat_rr, list<dag> pat_rm,
258 let isCommutable = 1, hasSideEffects = 0 in
259 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
261 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
262 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
263 pat_rr, NoItinerary, d>,
264 Sched<[WriteVecLogic]>;
265 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
267 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
268 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
269 pat_rm, NoItinerary, d>,
270 Sched<[WriteVecLogicLd, ReadAfterLd]>;
273 //===----------------------------------------------------------------------===//
274 // Non-instruction patterns
275 //===----------------------------------------------------------------------===//
277 // A vector extract of the first f32/f64 position is a subregister copy
278 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
279 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
280 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
281 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
283 // A 128-bit subvector extract from the first 256-bit vector position
284 // is a subregister copy that needs no instruction.
285 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
286 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
287 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
288 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
290 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
291 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
292 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
293 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
295 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
296 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
297 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
298 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
300 // A 128-bit subvector insert to the first 256-bit vector position
301 // is a subregister copy that needs no instruction.
302 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
303 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
304 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
305 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
306 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
307 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
308 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
309 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
310 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
311 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
312 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
313 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
314 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
317 // Implicitly promote a 32-bit scalar to a vector.
318 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
319 (COPY_TO_REGCLASS FR32:$src, VR128)>;
320 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
321 (COPY_TO_REGCLASS FR32:$src, VR128)>;
322 // Implicitly promote a 64-bit scalar to a vector.
323 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
324 (COPY_TO_REGCLASS FR64:$src, VR128)>;
325 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
326 (COPY_TO_REGCLASS FR64:$src, VR128)>;
328 // Bitcasts between 128-bit vector types. Return the original type since
329 // no instruction is needed for the conversion
330 let Predicates = [HasSSE2] in {
331 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
332 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
333 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
334 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
335 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
336 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
337 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
338 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
339 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
340 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
341 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
342 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
343 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
344 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
345 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
346 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
347 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
348 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
349 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
350 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
351 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
352 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
353 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
354 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
355 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
356 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
357 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
358 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
359 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
360 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
363 // Bitcasts between 256-bit vector types. Return the original type since
364 // no instruction is needed for the conversion
365 let Predicates = [HasAVX] in {
366 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
367 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
368 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
369 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
370 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
371 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
372 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
373 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
374 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
375 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
376 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
377 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
378 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
379 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
380 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
381 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
382 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
383 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
384 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
385 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
386 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
387 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
388 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
389 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
390 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
391 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
392 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
393 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
394 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
395 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
398 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
399 // This is expanded by ExpandPostRAPseudos.
400 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
401 isPseudo = 1, SchedRW = [WriteZero] in {
402 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
403 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
404 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
405 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
408 //===----------------------------------------------------------------------===//
409 // AVX & SSE - Zero/One Vectors
410 //===----------------------------------------------------------------------===//
412 // Alias instruction that maps zero vector to pxor / xorp* for sse.
413 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
414 // swizzled by ExecutionDepsFix to pxor.
415 // We set canFoldAsLoad because this can be converted to a constant-pool
416 // load of an all-zeros value if folding it would be beneficial.
417 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
418 isPseudo = 1, SchedRW = [WriteZero] in {
419 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
420 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
423 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
424 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
425 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
426 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
427 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
430 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
431 // and doesn't need it because on sandy bridge the register is set to zero
432 // at the rename stage without using any execution unit, so SET0PSY
433 // and SET0PDY can be used for vector int instructions without penalty
434 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
435 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
436 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
437 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
440 let Predicates = [HasAVX] in
441 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
443 let Predicates = [HasAVX2] in {
444 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
445 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
446 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
447 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
450 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
451 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
452 let Predicates = [HasAVX1Only] in {
453 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
454 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
455 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
457 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
458 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
459 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
461 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
462 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
463 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
465 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
466 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
467 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
470 // We set canFoldAsLoad because this can be converted to a constant-pool
471 // load of an all-ones value if folding it would be beneficial.
472 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
473 isPseudo = 1, SchedRW = [WriteZero] in {
474 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
475 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
476 let Predicates = [HasAVX2] in
477 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
478 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
482 //===----------------------------------------------------------------------===//
483 // SSE 1 & 2 - Move FP Scalar Instructions
485 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
486 // register copies because it's a partial register update; Register-to-register
487 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
488 // that the insert be implementable in terms of a copy, and just mentioned, we
489 // don't use movss/movsd for copies.
490 //===----------------------------------------------------------------------===//
492 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
493 X86MemOperand x86memop, string base_opc,
495 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
496 (ins VR128:$src1, RC:$src2),
497 !strconcat(base_opc, asm_opr),
498 [(set VR128:$dst, (vt (OpNode VR128:$src1,
499 (scalar_to_vector RC:$src2))))],
500 IIC_SSE_MOV_S_RR>, Sched<[WriteMove]>;
502 // For the disassembler
503 let isCodeGenOnly = 1, hasSideEffects = 0 in
504 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
505 (ins VR128:$src1, RC:$src2),
506 !strconcat(base_opc, asm_opr),
507 [], IIC_SSE_MOV_S_RR>, Sched<[WriteMove]>;
510 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
511 X86MemOperand x86memop, string OpcodeStr> {
513 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
514 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
517 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
518 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
519 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
520 VEX, VEX_LIG, Sched<[WriteStore]>;
522 let Constraints = "$src1 = $dst" in {
523 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
524 "\t{$src2, $dst|$dst, $src2}">;
527 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
528 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
529 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
533 // Loading from memory automatically zeroing upper bits.
534 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
535 PatFrag mem_pat, string OpcodeStr> {
536 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
537 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
538 [(set RC:$dst, (mem_pat addr:$src))],
539 IIC_SSE_MOV_S_RM>, VEX, VEX_LIG, Sched<[WriteLoad]>;
540 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
541 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
542 [(set RC:$dst, (mem_pat addr:$src))],
543 IIC_SSE_MOV_S_RM>, Sched<[WriteLoad]>;
546 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss">, XS;
547 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd">, XD;
549 let canFoldAsLoad = 1, isReMaterializable = 1 in {
550 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
552 let AddedComplexity = 20 in
553 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
557 let Predicates = [UseAVX] in {
558 let AddedComplexity = 15 in {
559 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
560 // MOVS{S,D} to the lower bits.
561 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
562 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
563 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
564 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
565 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
566 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
567 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
568 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
570 // Move low f32 and clear high bits.
571 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
572 (SUBREG_TO_REG (i32 0),
573 (VMOVSSrr (v4f32 (V_SET0)),
574 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
575 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
576 (SUBREG_TO_REG (i32 0),
577 (VMOVSSrr (v4i32 (V_SET0)),
578 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
581 let AddedComplexity = 20 in {
582 // MOVSSrm zeros the high parts of the register; represent this
583 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
584 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
585 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
586 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
587 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
588 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
589 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
591 // MOVSDrm zeros the high parts of the register; represent this
592 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
593 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
594 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
595 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
596 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
597 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
598 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
599 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
600 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
601 def : Pat<(v2f64 (X86vzload addr:$src)),
602 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
604 // Represent the same patterns above but in the form they appear for
606 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
607 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
608 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
609 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
610 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
611 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
612 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
613 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
614 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
616 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
617 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
618 (SUBREG_TO_REG (i32 0),
619 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
621 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
622 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
623 (SUBREG_TO_REG (i64 0),
624 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
626 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
627 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
628 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
630 // Move low f64 and clear high bits.
631 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
632 (SUBREG_TO_REG (i32 0),
633 (VMOVSDrr (v2f64 (V_SET0)),
634 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
636 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
637 (SUBREG_TO_REG (i32 0),
638 (VMOVSDrr (v2i64 (V_SET0)),
639 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
641 // Extract and store.
642 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
644 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
645 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
647 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
649 // Shuffle with VMOVSS
650 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
651 (VMOVSSrr (v4i32 VR128:$src1),
652 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
653 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
654 (VMOVSSrr (v4f32 VR128:$src1),
655 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
658 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
659 (SUBREG_TO_REG (i32 0),
660 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
661 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
663 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
664 (SUBREG_TO_REG (i32 0),
665 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
666 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
669 // Shuffle with VMOVSD
670 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
671 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
672 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
673 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
674 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
675 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
676 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
677 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
680 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
681 (SUBREG_TO_REG (i32 0),
682 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
683 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
685 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
686 (SUBREG_TO_REG (i32 0),
687 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
688 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
692 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
693 // is during lowering, where it's not possible to recognize the fold cause
694 // it has two uses through a bitcast. One use disappears at isel time and the
695 // fold opportunity reappears.
696 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
697 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
698 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
699 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
700 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
701 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
702 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
703 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
706 let Predicates = [UseSSE1] in {
707 let AddedComplexity = 15 in {
708 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
709 // MOVSS to the lower bits.
710 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
711 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
712 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
713 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
714 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
715 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
718 let AddedComplexity = 20 in {
719 // MOVSSrm already zeros the high parts of the register.
720 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
721 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
722 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
723 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
724 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
725 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
728 // Extract and store.
729 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
731 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
733 // Shuffle with MOVSS
734 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
735 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
736 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
737 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
740 let Predicates = [UseSSE2] in {
741 let AddedComplexity = 15 in {
742 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
743 // MOVSD to the lower bits.
744 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
745 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
748 let AddedComplexity = 20 in {
749 // MOVSDrm already zeros the high parts of the register.
750 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
751 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
752 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
753 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
754 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
755 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
756 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
757 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
758 def : Pat<(v2f64 (X86vzload addr:$src)),
759 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
762 // Extract and store.
763 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
765 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
767 // Shuffle with MOVSD
768 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
769 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
770 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
771 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
772 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
773 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
774 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
775 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
777 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
778 // is during lowering, where it's not possible to recognize the fold cause
779 // it has two uses through a bitcast. One use disappears at isel time and the
780 // fold opportunity reappears.
781 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
782 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
783 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
784 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
785 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
786 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
787 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
788 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
791 //===----------------------------------------------------------------------===//
792 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
793 //===----------------------------------------------------------------------===//
795 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
796 X86MemOperand x86memop, PatFrag ld_frag,
797 string asm, Domain d,
799 bit IsReMaterializable = 1> {
800 let neverHasSideEffects = 1 in
801 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
802 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
804 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
805 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
806 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
807 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
811 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
812 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
814 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
815 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
817 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
818 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
820 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
821 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
824 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
825 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
827 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
828 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
829 TB, OpSize, VEX, VEX_L;
830 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
831 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
833 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
834 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
835 TB, OpSize, VEX, VEX_L;
836 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
837 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
839 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
840 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
842 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
843 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
845 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
846 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
849 let SchedRW = [WriteStore] in {
850 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
851 "movaps\t{$src, $dst|$dst, $src}",
852 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
853 IIC_SSE_MOVA_P_MR>, VEX;
854 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
855 "movapd\t{$src, $dst|$dst, $src}",
856 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
857 IIC_SSE_MOVA_P_MR>, VEX;
858 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
859 "movups\t{$src, $dst|$dst, $src}",
860 [(store (v4f32 VR128:$src), addr:$dst)],
861 IIC_SSE_MOVU_P_MR>, VEX;
862 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
863 "movupd\t{$src, $dst|$dst, $src}",
864 [(store (v2f64 VR128:$src), addr:$dst)],
865 IIC_SSE_MOVU_P_MR>, VEX;
866 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
867 "movaps\t{$src, $dst|$dst, $src}",
868 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
869 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
870 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
871 "movapd\t{$src, $dst|$dst, $src}",
872 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
873 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
874 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
875 "movups\t{$src, $dst|$dst, $src}",
876 [(store (v8f32 VR256:$src), addr:$dst)],
877 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
878 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
879 "movupd\t{$src, $dst|$dst, $src}",
880 [(store (v4f64 VR256:$src), addr:$dst)],
881 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
885 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
886 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
888 "movaps\t{$src, $dst|$dst, $src}", [],
889 IIC_SSE_MOVA_P_RR>, VEX;
890 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
892 "movapd\t{$src, $dst|$dst, $src}", [],
893 IIC_SSE_MOVA_P_RR>, VEX;
894 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
896 "movups\t{$src, $dst|$dst, $src}", [],
897 IIC_SSE_MOVU_P_RR>, VEX;
898 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
900 "movupd\t{$src, $dst|$dst, $src}", [],
901 IIC_SSE_MOVU_P_RR>, VEX;
902 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
904 "movaps\t{$src, $dst|$dst, $src}", [],
905 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
906 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
908 "movapd\t{$src, $dst|$dst, $src}", [],
909 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
910 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
912 "movups\t{$src, $dst|$dst, $src}", [],
913 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
914 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
916 "movupd\t{$src, $dst|$dst, $src}", [],
917 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
920 let Predicates = [HasAVX] in {
921 def : Pat<(v8i32 (X86vzmovl
922 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
923 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
924 def : Pat<(v4i64 (X86vzmovl
925 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
926 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
927 def : Pat<(v8f32 (X86vzmovl
928 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
929 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
930 def : Pat<(v4f64 (X86vzmovl
931 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
932 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
936 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
937 (VMOVUPSYmr addr:$dst, VR256:$src)>;
938 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
939 (VMOVUPDYmr addr:$dst, VR256:$src)>;
941 let SchedRW = [WriteStore] in {
942 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
943 "movaps\t{$src, $dst|$dst, $src}",
944 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
946 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
947 "movapd\t{$src, $dst|$dst, $src}",
948 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
950 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
951 "movups\t{$src, $dst|$dst, $src}",
952 [(store (v4f32 VR128:$src), addr:$dst)],
954 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
955 "movupd\t{$src, $dst|$dst, $src}",
956 [(store (v2f64 VR128:$src), addr:$dst)],
961 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
962 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
963 "movaps\t{$src, $dst|$dst, $src}", [],
965 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
966 "movapd\t{$src, $dst|$dst, $src}", [],
968 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
969 "movups\t{$src, $dst|$dst, $src}", [],
971 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
972 "movupd\t{$src, $dst|$dst, $src}", [],
976 let Predicates = [HasAVX] in {
977 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
978 (VMOVUPSmr addr:$dst, VR128:$src)>;
979 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
980 (VMOVUPDmr addr:$dst, VR128:$src)>;
983 let Predicates = [UseSSE1] in
984 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
985 (MOVUPSmr addr:$dst, VR128:$src)>;
986 let Predicates = [UseSSE2] in
987 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
988 (MOVUPDmr addr:$dst, VR128:$src)>;
990 // Use vmovaps/vmovups for AVX integer load/store.
991 let Predicates = [HasAVX] in {
992 // 128-bit load/store
993 def : Pat<(alignedloadv2i64 addr:$src),
994 (VMOVAPSrm addr:$src)>;
995 def : Pat<(loadv2i64 addr:$src),
996 (VMOVUPSrm addr:$src)>;
998 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
999 (VMOVAPSmr addr:$dst, VR128:$src)>;
1000 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1001 (VMOVAPSmr addr:$dst, VR128:$src)>;
1002 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1003 (VMOVAPSmr addr:$dst, VR128:$src)>;
1004 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1005 (VMOVAPSmr addr:$dst, VR128:$src)>;
1006 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1007 (VMOVUPSmr addr:$dst, VR128:$src)>;
1008 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1009 (VMOVUPSmr addr:$dst, VR128:$src)>;
1010 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1011 (VMOVUPSmr addr:$dst, VR128:$src)>;
1012 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1013 (VMOVUPSmr addr:$dst, VR128:$src)>;
1015 // 256-bit load/store
1016 def : Pat<(alignedloadv4i64 addr:$src),
1017 (VMOVAPSYrm addr:$src)>;
1018 def : Pat<(loadv4i64 addr:$src),
1019 (VMOVUPSYrm addr:$src)>;
1020 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1021 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1022 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1023 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1024 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1025 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1026 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1027 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1028 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1029 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1030 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1031 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1032 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1033 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1034 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1035 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1037 // Special patterns for storing subvector extracts of lower 128-bits
1038 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1039 def : Pat<(alignedstore (v2f64 (extract_subvector
1040 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1041 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1042 def : Pat<(alignedstore (v4f32 (extract_subvector
1043 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1044 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1045 def : Pat<(alignedstore (v2i64 (extract_subvector
1046 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1047 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1048 def : Pat<(alignedstore (v4i32 (extract_subvector
1049 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1050 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1051 def : Pat<(alignedstore (v8i16 (extract_subvector
1052 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1053 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1054 def : Pat<(alignedstore (v16i8 (extract_subvector
1055 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1056 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1058 def : Pat<(store (v2f64 (extract_subvector
1059 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1060 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1061 def : Pat<(store (v4f32 (extract_subvector
1062 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1063 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1064 def : Pat<(store (v2i64 (extract_subvector
1065 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1066 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1067 def : Pat<(store (v4i32 (extract_subvector
1068 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1069 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1070 def : Pat<(store (v8i16 (extract_subvector
1071 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1072 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1073 def : Pat<(store (v16i8 (extract_subvector
1074 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1075 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1078 // Use movaps / movups for SSE integer load / store (one byte shorter).
1079 // The instructions selected below are then converted to MOVDQA/MOVDQU
1080 // during the SSE domain pass.
1081 let Predicates = [UseSSE1] in {
1082 def : Pat<(alignedloadv2i64 addr:$src),
1083 (MOVAPSrm addr:$src)>;
1084 def : Pat<(loadv2i64 addr:$src),
1085 (MOVUPSrm addr:$src)>;
1087 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1088 (MOVAPSmr addr:$dst, VR128:$src)>;
1089 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1090 (MOVAPSmr addr:$dst, VR128:$src)>;
1091 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1092 (MOVAPSmr addr:$dst, VR128:$src)>;
1093 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1094 (MOVAPSmr addr:$dst, VR128:$src)>;
1095 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1096 (MOVUPSmr addr:$dst, VR128:$src)>;
1097 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1098 (MOVUPSmr addr:$dst, VR128:$src)>;
1099 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1100 (MOVUPSmr addr:$dst, VR128:$src)>;
1101 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1102 (MOVUPSmr addr:$dst, VR128:$src)>;
1105 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1106 // bits are disregarded. FIXME: Set encoding to pseudo!
1107 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1108 let isCodeGenOnly = 1 in {
1109 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1110 "movaps\t{$src, $dst|$dst, $src}",
1111 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1112 IIC_SSE_MOVA_P_RM>, VEX;
1113 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1114 "movapd\t{$src, $dst|$dst, $src}",
1115 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1116 IIC_SSE_MOVA_P_RM>, VEX;
1118 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1119 "movaps\t{$src, $dst|$dst, $src}",
1120 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1122 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1123 "movapd\t{$src, $dst|$dst, $src}",
1124 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1128 //===----------------------------------------------------------------------===//
1129 // SSE 1 & 2 - Move Low packed FP Instructions
1130 //===----------------------------------------------------------------------===//
1132 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1133 string base_opc, string asm_opr,
1134 InstrItinClass itin> {
1135 def PSrm : PI<opc, MRMSrcMem,
1136 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1137 !strconcat(base_opc, "s", asm_opr),
1139 (psnode VR128:$src1,
1140 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1141 itin, SSEPackedSingle>, TB,
1142 Sched<[WriteShuffleLd, ReadAfterLd]>;
1144 def PDrm : PI<opc, MRMSrcMem,
1145 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1146 !strconcat(base_opc, "d", asm_opr),
1147 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1148 (scalar_to_vector (loadf64 addr:$src2)))))],
1149 itin, SSEPackedDouble>, TB, OpSize,
1150 Sched<[WriteShuffleLd, ReadAfterLd]>;
1154 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1155 string base_opc, InstrItinClass itin> {
1156 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1157 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1160 let Constraints = "$src1 = $dst" in
1161 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1162 "\t{$src2, $dst|$dst, $src2}",
1166 let AddedComplexity = 20 in {
1167 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1171 let SchedRW = [WriteStore] in {
1172 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1173 "movlps\t{$src, $dst|$dst, $src}",
1174 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1175 (iPTR 0))), addr:$dst)],
1176 IIC_SSE_MOV_LH>, VEX;
1177 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1178 "movlpd\t{$src, $dst|$dst, $src}",
1179 [(store (f64 (vector_extract (v2f64 VR128:$src),
1180 (iPTR 0))), addr:$dst)],
1181 IIC_SSE_MOV_LH>, VEX;
1182 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1183 "movlps\t{$src, $dst|$dst, $src}",
1184 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1185 (iPTR 0))), addr:$dst)],
1187 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1188 "movlpd\t{$src, $dst|$dst, $src}",
1189 [(store (f64 (vector_extract (v2f64 VR128:$src),
1190 (iPTR 0))), addr:$dst)],
1194 let Predicates = [HasAVX] in {
1195 // Shuffle with VMOVLPS
1196 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1197 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1198 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1199 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1201 // Shuffle with VMOVLPD
1202 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1203 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1204 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1205 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1208 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1210 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1211 def : Pat<(store (v4i32 (X86Movlps
1212 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1213 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1214 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1216 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1217 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1219 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1222 let Predicates = [UseSSE1] in {
1223 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1224 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1225 (iPTR 0))), addr:$src1),
1226 (MOVLPSmr addr:$src1, VR128:$src2)>;
1228 // Shuffle with MOVLPS
1229 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1230 (MOVLPSrm VR128:$src1, addr:$src2)>;
1231 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1232 (MOVLPSrm VR128:$src1, addr:$src2)>;
1233 def : Pat<(X86Movlps VR128:$src1,
1234 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1235 (MOVLPSrm VR128:$src1, addr:$src2)>;
1238 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1240 (MOVLPSmr addr:$src1, VR128:$src2)>;
1241 def : Pat<(store (v4i32 (X86Movlps
1242 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1244 (MOVLPSmr addr:$src1, VR128:$src2)>;
1247 let Predicates = [UseSSE2] in {
1248 // Shuffle with MOVLPD
1249 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1250 (MOVLPDrm VR128:$src1, addr:$src2)>;
1251 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1252 (MOVLPDrm VR128:$src1, addr:$src2)>;
1255 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1257 (MOVLPDmr addr:$src1, VR128:$src2)>;
1258 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1260 (MOVLPDmr addr:$src1, VR128:$src2)>;
1263 //===----------------------------------------------------------------------===//
1264 // SSE 1 & 2 - Move Hi packed FP Instructions
1265 //===----------------------------------------------------------------------===//
1267 let AddedComplexity = 20 in {
1268 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1272 let SchedRW = [WriteStore] in {
1273 // v2f64 extract element 1 is always custom lowered to unpack high to low
1274 // and extract element 0 so the non-store version isn't too horrible.
1275 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1276 "movhps\t{$src, $dst|$dst, $src}",
1277 [(store (f64 (vector_extract
1278 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1279 (bc_v2f64 (v4f32 VR128:$src))),
1280 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1281 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1282 "movhpd\t{$src, $dst|$dst, $src}",
1283 [(store (f64 (vector_extract
1284 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1285 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1286 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1287 "movhps\t{$src, $dst|$dst, $src}",
1288 [(store (f64 (vector_extract
1289 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1290 (bc_v2f64 (v4f32 VR128:$src))),
1291 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1292 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1293 "movhpd\t{$src, $dst|$dst, $src}",
1294 [(store (f64 (vector_extract
1295 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1296 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1299 let Predicates = [HasAVX] in {
1301 def : Pat<(X86Movlhps VR128:$src1,
1302 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1303 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1304 def : Pat<(X86Movlhps VR128:$src1,
1305 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1306 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1308 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1309 // is during lowering, where it's not possible to recognize the load fold
1310 // cause it has two uses through a bitcast. One use disappears at isel time
1311 // and the fold opportunity reappears.
1312 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1313 (scalar_to_vector (loadf64 addr:$src2)))),
1314 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1317 let Predicates = [UseSSE1] in {
1319 def : Pat<(X86Movlhps VR128:$src1,
1320 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1321 (MOVHPSrm VR128:$src1, addr:$src2)>;
1322 def : Pat<(X86Movlhps VR128:$src1,
1323 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1324 (MOVHPSrm VR128:$src1, addr:$src2)>;
1327 let Predicates = [UseSSE2] in {
1328 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1329 // is during lowering, where it's not possible to recognize the load fold
1330 // cause it has two uses through a bitcast. One use disappears at isel time
1331 // and the fold opportunity reappears.
1332 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1333 (scalar_to_vector (loadf64 addr:$src2)))),
1334 (MOVHPDrm VR128:$src1, addr:$src2)>;
1337 //===----------------------------------------------------------------------===//
1338 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1339 //===----------------------------------------------------------------------===//
1341 let AddedComplexity = 20, Predicates = [UseAVX] in {
1342 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1343 (ins VR128:$src1, VR128:$src2),
1344 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1346 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1348 VEX_4V, Sched<[WriteShuffle]>;
1349 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1350 (ins VR128:$src1, VR128:$src2),
1351 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1353 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1355 VEX_4V, Sched<[WriteShuffle]>;
1357 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1358 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1359 (ins VR128:$src1, VR128:$src2),
1360 "movlhps\t{$src2, $dst|$dst, $src2}",
1362 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1363 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
1364 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1365 (ins VR128:$src1, VR128:$src2),
1366 "movhlps\t{$src2, $dst|$dst, $src2}",
1368 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1369 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
1372 let Predicates = [UseAVX] in {
1374 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1375 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1376 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1377 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1380 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1381 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1384 let Predicates = [UseSSE1] in {
1386 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1387 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1388 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1389 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1392 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1393 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1396 //===----------------------------------------------------------------------===//
1397 // SSE 1 & 2 - Conversion Instructions
1398 //===----------------------------------------------------------------------===//
1400 def SSE_CVT_PD : OpndItins<
1401 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1404 let Sched = WriteCvtI2F in
1405 def SSE_CVT_PS : OpndItins<
1406 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1409 let Sched = WriteCvtI2F in
1410 def SSE_CVT_Scalar : OpndItins<
1411 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1414 let Sched = WriteCvtF2I in
1415 def SSE_CVT_SS2SI_32 : OpndItins<
1416 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1419 let Sched = WriteCvtF2I in
1420 def SSE_CVT_SS2SI_64 : OpndItins<
1421 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1424 let Sched = WriteCvtF2I in
1425 def SSE_CVT_SD2SI : OpndItins<
1426 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1429 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1430 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1431 string asm, OpndItins itins> {
1432 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1433 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1434 itins.rr>, Sched<[itins.Sched]>;
1435 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1436 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1437 itins.rm>, Sched<[itins.Sched.Folded]>;
1440 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1441 X86MemOperand x86memop, string asm, Domain d,
1443 let neverHasSideEffects = 1 in {
1444 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1445 [], itins.rr, d>, Sched<[itins.Sched]>;
1447 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1448 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1452 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1453 X86MemOperand x86memop, string asm> {
1454 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1455 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1456 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1457 Sched<[WriteCvtI2F]>;
1459 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1460 (ins DstRC:$src1, x86memop:$src),
1461 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1462 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1463 } // neverHasSideEffects = 1
1466 let Predicates = [UseAVX] in {
1467 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1468 "cvttss2si\t{$src, $dst|$dst, $src}",
1471 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1472 "cvttss2si\t{$src, $dst|$dst, $src}",
1474 XS, VEX, VEX_W, VEX_LIG;
1475 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1476 "cvttsd2si\t{$src, $dst|$dst, $src}",
1479 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1480 "cvttsd2si\t{$src, $dst|$dst, $src}",
1482 XD, VEX, VEX_W, VEX_LIG;
1484 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1485 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1486 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1487 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1488 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1489 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1490 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1491 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1492 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1493 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1494 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1495 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1496 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1497 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1498 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1499 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1501 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1502 // register, but the same isn't true when only using memory operands,
1503 // provide other assembly "l" and "q" forms to address this explicitly
1504 // where appropriate to do so.
1505 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1506 XS, VEX_4V, VEX_LIG;
1507 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1508 XS, VEX_4V, VEX_W, VEX_LIG;
1509 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1510 XD, VEX_4V, VEX_LIG;
1511 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1512 XD, VEX_4V, VEX_W, VEX_LIG;
1514 let Predicates = [UseAVX] in {
1515 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1516 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1517 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1518 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1520 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1521 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1522 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1523 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1524 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1525 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1526 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1527 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1529 def : Pat<(f32 (sint_to_fp GR32:$src)),
1530 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1531 def : Pat<(f32 (sint_to_fp GR64:$src)),
1532 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1533 def : Pat<(f64 (sint_to_fp GR32:$src)),
1534 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1535 def : Pat<(f64 (sint_to_fp GR64:$src)),
1536 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1539 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1540 "cvttss2si\t{$src, $dst|$dst, $src}",
1541 SSE_CVT_SS2SI_32>, XS;
1542 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1543 "cvttss2si\t{$src, $dst|$dst, $src}",
1544 SSE_CVT_SS2SI_64>, XS, REX_W;
1545 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1546 "cvttsd2si\t{$src, $dst|$dst, $src}",
1548 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1549 "cvttsd2si\t{$src, $dst|$dst, $src}",
1550 SSE_CVT_SD2SI>, XD, REX_W;
1551 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1552 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1553 SSE_CVT_Scalar>, XS;
1554 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1555 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1556 SSE_CVT_Scalar>, XS, REX_W;
1557 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1558 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1559 SSE_CVT_Scalar>, XD;
1560 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1561 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1562 SSE_CVT_Scalar>, XD, REX_W;
1564 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1565 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1566 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1567 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1568 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1569 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1570 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1571 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1572 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1573 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1574 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1575 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1576 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1577 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1578 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1579 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1581 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1582 (CVTSI2SSrm FR64:$dst, i32mem:$src)>;
1583 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1584 (CVTSI2SDrm FR64:$dst, i32mem:$src)>;
1586 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1587 // and/or XMM operand(s).
1589 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1590 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1591 string asm, OpndItins itins> {
1592 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1593 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1594 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1595 Sched<[itins.Sched]>;
1596 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1597 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1598 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1599 Sched<[itins.Sched.Folded]>;
1602 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1603 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1604 PatFrag ld_frag, string asm, OpndItins itins,
1606 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1608 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1609 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1610 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1611 itins.rr>, Sched<[itins.Sched]>;
1612 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1613 (ins DstRC:$src1, x86memop:$src2),
1615 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1616 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1617 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1618 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1621 let Predicates = [UseAVX] in {
1622 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1623 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1624 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1625 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1626 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1627 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1629 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1630 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1631 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1632 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1635 let Predicates = [UseAVX] in {
1636 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1637 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1638 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1639 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1640 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1641 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1643 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1644 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1645 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1646 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1647 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1648 SSE_CVT_Scalar, 0>, XD,
1651 let Constraints = "$src1 = $dst" in {
1652 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1653 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1654 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1655 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1656 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1657 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1658 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1659 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1660 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1661 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1662 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1663 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1668 // Aliases for intrinsics
1669 let Predicates = [UseAVX] in {
1670 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1671 ssmem, sse_load_f32, "cvttss2si",
1672 SSE_CVT_SS2SI_32>, XS, VEX;
1673 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1674 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1675 "cvttss2si", SSE_CVT_SS2SI_64>,
1677 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1678 sdmem, sse_load_f64, "cvttsd2si",
1679 SSE_CVT_SD2SI>, XD, VEX;
1680 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1681 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1682 "cvttsd2si", SSE_CVT_SD2SI>,
1685 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1686 ssmem, sse_load_f32, "cvttss2si",
1687 SSE_CVT_SS2SI_32>, XS;
1688 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1689 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1690 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1691 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1692 sdmem, sse_load_f64, "cvttsd2si",
1694 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1695 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1696 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1698 let Predicates = [UseAVX] in {
1699 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1700 ssmem, sse_load_f32, "cvtss2si",
1701 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1702 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1703 ssmem, sse_load_f32, "cvtss2si",
1704 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1706 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1707 ssmem, sse_load_f32, "cvtss2si",
1708 SSE_CVT_SS2SI_32>, XS;
1709 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1710 ssmem, sse_load_f32, "cvtss2si",
1711 SSE_CVT_SS2SI_64>, XS, REX_W;
1713 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1714 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1715 SSEPackedSingle, SSE_CVT_PS>,
1716 TB, VEX, Requires<[HasAVX]>;
1717 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1718 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1719 SSEPackedSingle, SSE_CVT_PS>,
1720 TB, VEX, VEX_L, Requires<[HasAVX]>;
1722 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1723 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1724 SSEPackedSingle, SSE_CVT_PS>,
1725 TB, Requires<[UseSSE2]>;
1727 let Predicates = [UseAVX] in {
1728 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1729 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1730 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1731 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1732 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1733 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1734 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1735 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1736 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1737 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1738 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1739 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1740 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1741 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1742 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1743 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1746 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1747 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1748 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1749 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1750 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1751 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1752 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1753 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1754 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1755 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1756 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1757 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1758 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1759 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1760 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1761 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1765 // Convert scalar double to scalar single
1766 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1767 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1768 (ins FR64:$src1, FR64:$src2),
1769 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1770 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1771 Sched<[WriteCvtF2F]>;
1773 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1774 (ins FR64:$src1, f64mem:$src2),
1775 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1776 [], IIC_SSE_CVT_Scalar_RM>,
1777 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1778 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1781 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1784 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1785 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1786 [(set FR32:$dst, (fround FR64:$src))],
1787 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1788 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1789 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1790 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1791 IIC_SSE_CVT_Scalar_RM>,
1793 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1795 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1796 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1797 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1799 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1800 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[UseAVX]>,
1801 Sched<[WriteCvtF2F]>;
1802 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1803 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1804 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1805 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1806 VR128:$src1, sse_load_f64:$src2))],
1807 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[UseAVX]>,
1808 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1810 let Constraints = "$src1 = $dst" in {
1811 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1812 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1813 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1815 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1816 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1817 Sched<[WriteCvtF2F]>;
1818 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1819 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1820 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1821 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1822 VR128:$src1, sse_load_f64:$src2))],
1823 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1824 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1827 // Convert scalar single to scalar double
1828 // SSE2 instructions with XS prefix
1829 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1830 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1831 (ins FR32:$src1, FR32:$src2),
1832 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1833 [], IIC_SSE_CVT_Scalar_RR>,
1834 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1835 Sched<[WriteCvtF2F]>;
1837 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1838 (ins FR32:$src1, f32mem:$src2),
1839 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1840 [], IIC_SSE_CVT_Scalar_RM>,
1841 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1842 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1845 def : Pat<(f64 (fextend FR32:$src)),
1846 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1847 def : Pat<(fextend (loadf32 addr:$src)),
1848 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1850 def : Pat<(extloadf32 addr:$src),
1851 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1852 Requires<[UseAVX, OptForSize]>;
1853 def : Pat<(extloadf32 addr:$src),
1854 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1855 Requires<[UseAVX, OptForSpeed]>;
1857 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1858 "cvtss2sd\t{$src, $dst|$dst, $src}",
1859 [(set FR64:$dst, (fextend FR32:$src))],
1860 IIC_SSE_CVT_Scalar_RR>, XS,
1861 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1862 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1863 "cvtss2sd\t{$src, $dst|$dst, $src}",
1864 [(set FR64:$dst, (extloadf32 addr:$src))],
1865 IIC_SSE_CVT_Scalar_RM>, XS,
1866 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1868 // extload f32 -> f64. This matches load+fextend because we have a hack in
1869 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1871 // Since these loads aren't folded into the fextend, we have to match it
1873 def : Pat<(fextend (loadf32 addr:$src)),
1874 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1875 def : Pat<(extloadf32 addr:$src),
1876 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1878 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1879 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1880 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1882 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1883 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[UseAVX]>,
1884 Sched<[WriteCvtF2F]>;
1885 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1886 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1887 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1889 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1890 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[UseAVX]>,
1891 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1892 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1893 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1894 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1895 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1897 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1898 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1899 Sched<[WriteCvtF2F]>;
1900 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1901 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1902 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1904 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1905 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1906 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1909 // Convert packed single/double fp to doubleword
1910 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1911 "cvtps2dq\t{$src, $dst|$dst, $src}",
1912 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1913 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1914 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1915 "cvtps2dq\t{$src, $dst|$dst, $src}",
1917 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1918 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1919 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1920 "cvtps2dq\t{$src, $dst|$dst, $src}",
1922 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1923 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1924 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1925 "cvtps2dq\t{$src, $dst|$dst, $src}",
1927 (int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)))],
1928 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1929 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1930 "cvtps2dq\t{$src, $dst|$dst, $src}",
1931 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1932 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1933 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1934 "cvtps2dq\t{$src, $dst|$dst, $src}",
1936 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1937 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1940 // Convert Packed Double FP to Packed DW Integers
1941 let Predicates = [HasAVX] in {
1942 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1943 // register, but the same isn't true when using memory operands instead.
1944 // Provide other assembly rr and rm forms to address this explicitly.
1945 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1946 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1947 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1948 VEX, Sched<[WriteCvtF2I]>;
1951 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1952 (VCVTPD2DQrr VR128:$dst, VR128:$src)>;
1953 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1954 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1956 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))]>, VEX,
1957 Sched<[WriteCvtF2ILd]>;
1960 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1961 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1963 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
1964 Sched<[WriteCvtF2I]>;
1965 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1966 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1968 (int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)))]>,
1969 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1970 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
1971 (VCVTPD2DQYrr VR128:$dst, VR256:$src)>;
1974 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1975 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1977 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
1978 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
1979 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1980 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1981 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1982 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
1984 // Convert with truncation packed single/double fp to doubleword
1985 // SSE2 packed instructions with XS prefix
1986 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1987 "cvttps2dq\t{$src, $dst|$dst, $src}",
1989 (int_x86_sse2_cvttps2dq VR128:$src))],
1990 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1991 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1992 "cvttps2dq\t{$src, $dst|$dst, $src}",
1993 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1994 (memopv4f32 addr:$src)))],
1995 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1996 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1997 "cvttps2dq\t{$src, $dst|$dst, $src}",
1999 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2000 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2001 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2002 "cvttps2dq\t{$src, $dst|$dst, $src}",
2003 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2004 (memopv8f32 addr:$src)))],
2005 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2006 Sched<[WriteCvtF2ILd]>;
2008 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2009 "cvttps2dq\t{$src, $dst|$dst, $src}",
2010 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2011 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2012 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2013 "cvttps2dq\t{$src, $dst|$dst, $src}",
2015 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2016 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2018 let Predicates = [HasAVX] in {
2019 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2020 (VCVTDQ2PSrr VR128:$src)>;
2021 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2022 (VCVTDQ2PSrm addr:$src)>;
2024 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2025 (VCVTDQ2PSrr VR128:$src)>;
2026 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2027 (VCVTDQ2PSrm addr:$src)>;
2029 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2030 (VCVTTPS2DQrr VR128:$src)>;
2031 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2032 (VCVTTPS2DQrm addr:$src)>;
2034 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2035 (VCVTDQ2PSYrr VR256:$src)>;
2036 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
2037 (VCVTDQ2PSYrm addr:$src)>;
2039 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2040 (VCVTTPS2DQYrr VR256:$src)>;
2041 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
2042 (VCVTTPS2DQYrm addr:$src)>;
2045 let Predicates = [UseSSE2] in {
2046 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2047 (CVTDQ2PSrr VR128:$src)>;
2048 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2049 (CVTDQ2PSrm addr:$src)>;
2051 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2052 (CVTDQ2PSrr VR128:$src)>;
2053 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2054 (CVTDQ2PSrm addr:$src)>;
2056 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2057 (CVTTPS2DQrr VR128:$src)>;
2058 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2059 (CVTTPS2DQrm addr:$src)>;
2062 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2063 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2065 (int_x86_sse2_cvttpd2dq VR128:$src))],
2066 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2068 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2069 // register, but the same isn't true when using memory operands instead.
2070 // Provide other assembly rr and rm forms to address this explicitly.
2073 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2074 (VCVTTPD2DQrr VR128:$dst, VR128:$src)>;
2075 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2076 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2077 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2078 (memopv2f64 addr:$src)))],
2079 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2082 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2083 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2085 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2086 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2087 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2088 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2090 (int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)))],
2091 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2092 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2093 (VCVTTPD2DQYrr VR128:$dst, VR256:$src)>;
2095 let Predicates = [HasAVX] in {
2096 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2097 (VCVTTPD2DQYrr VR256:$src)>;
2098 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
2099 (VCVTTPD2DQYrm addr:$src)>;
2100 } // Predicates = [HasAVX]
2102 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2103 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2104 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2105 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2106 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2107 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2108 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2109 (memopv2f64 addr:$src)))],
2111 Sched<[WriteCvtF2ILd]>;
2113 // Convert packed single to packed double
2114 let Predicates = [HasAVX] in {
2115 // SSE2 instructions without OpSize prefix
2116 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2117 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2118 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2119 IIC_SSE_CVT_PD_RR>, TB, VEX, Sched<[WriteCvtF2F]>;
2120 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2121 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2122 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2123 IIC_SSE_CVT_PD_RM>, TB, VEX, Sched<[WriteCvtF2FLd]>;
2124 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2125 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2127 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2128 IIC_SSE_CVT_PD_RR>, TB, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2129 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2130 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2132 (int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)))],
2133 IIC_SSE_CVT_PD_RM>, TB, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2136 let Predicates = [UseSSE2] in {
2137 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2138 "cvtps2pd\t{$src, $dst|$dst, $src}",
2139 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2140 IIC_SSE_CVT_PD_RR>, TB, Sched<[WriteCvtF2F]>;
2141 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2142 "cvtps2pd\t{$src, $dst|$dst, $src}",
2143 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2144 IIC_SSE_CVT_PD_RM>, TB, Sched<[WriteCvtF2FLd]>;
2147 // Convert Packed DW Integers to Packed Double FP
2148 let Predicates = [HasAVX] in {
2149 let neverHasSideEffects = 1, mayLoad = 1 in
2150 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2151 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2152 []>, VEX, Sched<[WriteCvtI2FLd]>;
2153 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2154 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2156 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2157 Sched<[WriteCvtI2F]>;
2158 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2159 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2161 (int_x86_avx_cvtdq2_pd_256
2162 (bitconvert (memopv2i64 addr:$src))))]>, VEX, VEX_L,
2163 Sched<[WriteCvtI2FLd]>;
2164 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2165 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2167 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2168 Sched<[WriteCvtI2F]>;
2171 let neverHasSideEffects = 1, mayLoad = 1 in
2172 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2173 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2174 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2175 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2176 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2177 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2178 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2180 // AVX 256-bit register conversion intrinsics
2181 let Predicates = [HasAVX] in {
2182 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2183 (VCVTDQ2PDYrr VR128:$src)>;
2184 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2185 (VCVTDQ2PDYrm addr:$src)>;
2186 } // Predicates = [HasAVX]
2188 // Convert packed double to packed single
2189 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2190 // register, but the same isn't true when using memory operands instead.
2191 // Provide other assembly rr and rm forms to address this explicitly.
2192 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2193 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2194 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2195 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2198 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2199 (VCVTPD2PSrr VR128:$dst, VR128:$src)>;
2200 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2201 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2203 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2204 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2207 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2208 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2210 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2211 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2212 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2213 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2215 (int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)))],
2216 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2217 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2218 (VCVTPD2PSYrr VR128:$dst, VR256:$src)>;
2220 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2221 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2222 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2223 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2224 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2225 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2227 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2228 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2231 // AVX 256-bit register conversion intrinsics
2232 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2233 // whenever possible to avoid declaring two versions of each one.
2234 let Predicates = [HasAVX] in {
2235 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2236 (VCVTDQ2PSYrr VR256:$src)>;
2237 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2238 (VCVTDQ2PSYrm addr:$src)>;
2240 // Match fround and fextend for 128/256-bit conversions
2241 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2242 (VCVTPD2PSrr VR128:$src)>;
2243 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2244 (VCVTPD2PSXrm addr:$src)>;
2245 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2246 (VCVTPD2PSYrr VR256:$src)>;
2247 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2248 (VCVTPD2PSYrm addr:$src)>;
2250 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2251 (VCVTPS2PDrr VR128:$src)>;
2252 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2253 (VCVTPS2PDYrr VR128:$src)>;
2254 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2255 (VCVTPS2PDYrm addr:$src)>;
2258 let Predicates = [UseSSE2] in {
2259 // Match fround and fextend for 128 conversions
2260 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2261 (CVTPD2PSrr VR128:$src)>;
2262 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2263 (CVTPD2PSrm addr:$src)>;
2265 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2266 (CVTPS2PDrr VR128:$src)>;
2269 //===----------------------------------------------------------------------===//
2270 // SSE 1 & 2 - Compare Instructions
2271 //===----------------------------------------------------------------------===//
2273 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2274 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2275 Operand CC, SDNode OpNode, ValueType VT,
2276 PatFrag ld_frag, string asm, string asm_alt,
2278 def rr : SIi8<0xC2, MRMSrcReg,
2279 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2280 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2281 itins.rr>, Sched<[itins.Sched]>;
2282 def rm : SIi8<0xC2, MRMSrcMem,
2283 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2284 [(set RC:$dst, (OpNode (VT RC:$src1),
2285 (ld_frag addr:$src2), imm:$cc))],
2287 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2289 // Accept explicit immediate argument form instead of comparison code.
2290 let neverHasSideEffects = 1 in {
2291 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2292 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2293 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2295 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2296 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2297 IIC_SSE_ALU_F32S_RM>,
2298 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2302 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2303 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2304 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2306 XS, VEX_4V, VEX_LIG;
2307 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2308 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2309 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2310 SSE_ALU_F32S>, // same latency as 32 bit compare
2311 XD, VEX_4V, VEX_LIG;
2313 let Constraints = "$src1 = $dst" in {
2314 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2315 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2316 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2318 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2319 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2320 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2325 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2326 Intrinsic Int, string asm, OpndItins itins> {
2327 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2328 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2329 [(set VR128:$dst, (Int VR128:$src1,
2330 VR128:$src, imm:$cc))],
2332 Sched<[itins.Sched]>;
2333 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2334 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2335 [(set VR128:$dst, (Int VR128:$src1,
2336 (load addr:$src), imm:$cc))],
2338 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2341 // Aliases to match intrinsics which expect XMM operand(s).
2342 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2343 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2346 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2347 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2348 SSE_ALU_F32S>, // same latency as f32
2350 let Constraints = "$src1 = $dst" in {
2351 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2352 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2354 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2355 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2361 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2362 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2363 ValueType vt, X86MemOperand x86memop,
2364 PatFrag ld_frag, string OpcodeStr> {
2365 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2366 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2367 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2370 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2371 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2372 [(set EFLAGS, (OpNode (vt RC:$src1),
2373 (ld_frag addr:$src2)))],
2375 Sched<[WriteFAddLd, ReadAfterLd]>;
2378 let Defs = [EFLAGS] in {
2379 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2380 "ucomiss">, TB, VEX, VEX_LIG;
2381 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2382 "ucomisd">, TB, OpSize, VEX, VEX_LIG;
2383 let Pattern = []<dag> in {
2384 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2385 "comiss">, TB, VEX, VEX_LIG;
2386 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2387 "comisd">, TB, OpSize, VEX, VEX_LIG;
2390 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2391 load, "ucomiss">, TB, VEX;
2392 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2393 load, "ucomisd">, TB, OpSize, VEX;
2395 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2396 load, "comiss">, TB, VEX;
2397 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2398 load, "comisd">, TB, OpSize, VEX;
2399 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2401 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2402 "ucomisd">, TB, OpSize;
2404 let Pattern = []<dag> in {
2405 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2407 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2408 "comisd">, TB, OpSize;
2411 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2412 load, "ucomiss">, TB;
2413 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2414 load, "ucomisd">, TB, OpSize;
2416 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2418 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2419 "comisd">, TB, OpSize;
2420 } // Defs = [EFLAGS]
2422 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2423 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2424 Operand CC, Intrinsic Int, string asm,
2425 string asm_alt, Domain d,
2426 OpndItins itins = SSE_ALU_F32P> {
2427 def rri : PIi8<0xC2, MRMSrcReg,
2428 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2429 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2432 def rmi : PIi8<0xC2, MRMSrcMem,
2433 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2434 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2436 Sched<[WriteFAddLd, ReadAfterLd]>;
2438 // Accept explicit immediate argument form instead of comparison code.
2439 let neverHasSideEffects = 1 in {
2440 def rri_alt : PIi8<0xC2, MRMSrcReg,
2441 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2442 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2443 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2444 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2445 asm_alt, [], itins.rm, d>,
2446 Sched<[WriteFAddLd, ReadAfterLd]>;
2450 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2451 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2452 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2453 SSEPackedSingle>, TB, VEX_4V;
2454 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2455 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2456 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2457 SSEPackedDouble>, TB, OpSize, VEX_4V;
2458 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2459 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2460 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2461 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2462 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2463 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2464 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2465 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2466 let Constraints = "$src1 = $dst" in {
2467 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2468 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2469 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2470 SSEPackedSingle, SSE_ALU_F32P>, TB;
2471 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2472 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2473 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2474 SSEPackedDouble, SSE_ALU_F64P>, TB, OpSize;
2477 let Predicates = [HasAVX] in {
2478 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2479 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2480 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2481 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2482 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2483 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2484 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2485 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2487 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2488 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2489 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2490 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2491 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2492 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2493 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2494 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2497 let Predicates = [UseSSE1] in {
2498 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2499 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2500 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2501 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2504 let Predicates = [UseSSE2] in {
2505 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2506 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2507 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2508 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2511 //===----------------------------------------------------------------------===//
2512 // SSE 1 & 2 - Shuffle Instructions
2513 //===----------------------------------------------------------------------===//
2515 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2516 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2517 ValueType vt, string asm, PatFrag mem_frag,
2518 Domain d, bit IsConvertibleToThreeAddress = 0> {
2519 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2520 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2521 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2522 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2523 Sched<[WriteShuffleLd, ReadAfterLd]>;
2524 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2525 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2526 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2527 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2528 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2529 Sched<[WriteShuffle]>;
2532 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2533 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2534 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2535 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2536 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2537 memopv8f32, SSEPackedSingle>, TB, VEX_4V, VEX_L;
2538 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2539 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2540 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2541 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2542 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2543 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2545 let Constraints = "$src1 = $dst" in {
2546 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2547 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2548 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2550 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2551 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2552 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2556 let Predicates = [HasAVX] in {
2557 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2558 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2559 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2560 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2561 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2563 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2564 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2565 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2566 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2567 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2570 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2571 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2572 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2573 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2574 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2576 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2577 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2578 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2579 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2580 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2583 let Predicates = [UseSSE1] in {
2584 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2585 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2586 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2587 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2588 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2591 let Predicates = [UseSSE2] in {
2592 // Generic SHUFPD patterns
2593 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2594 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2595 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2596 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2597 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2600 //===----------------------------------------------------------------------===//
2601 // SSE 1 & 2 - Unpack Instructions
2602 //===----------------------------------------------------------------------===//
2604 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2605 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2606 PatFrag mem_frag, RegisterClass RC,
2607 X86MemOperand x86memop, string asm,
2609 def rr : PI<opc, MRMSrcReg,
2610 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2612 (vt (OpNode RC:$src1, RC:$src2)))],
2613 IIC_SSE_UNPCK, d>, Sched<[WriteShuffle]>;
2614 def rm : PI<opc, MRMSrcMem,
2615 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2617 (vt (OpNode RC:$src1,
2618 (mem_frag addr:$src2))))],
2620 Sched<[WriteShuffleLd, ReadAfterLd]>;
2623 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2624 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2625 SSEPackedSingle>, TB, VEX_4V;
2626 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2627 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2628 SSEPackedDouble>, TB, OpSize, VEX_4V;
2629 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2630 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2631 SSEPackedSingle>, TB, VEX_4V;
2632 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2633 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2634 SSEPackedDouble>, TB, OpSize, VEX_4V;
2636 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2637 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2638 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2639 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2640 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2641 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2642 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2643 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2644 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2645 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2646 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2647 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2649 let Constraints = "$src1 = $dst" in {
2650 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2651 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2652 SSEPackedSingle>, TB;
2653 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2654 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2655 SSEPackedDouble>, TB, OpSize;
2656 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2657 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2658 SSEPackedSingle>, TB;
2659 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2660 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2661 SSEPackedDouble>, TB, OpSize;
2662 } // Constraints = "$src1 = $dst"
2664 let Predicates = [HasAVX1Only] in {
2665 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2666 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2667 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2668 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2669 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2670 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2671 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2672 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2674 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
2675 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2676 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2677 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2678 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
2679 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2680 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2681 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2684 let Predicates = [HasAVX] in {
2685 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2686 // problem is during lowering, where it's not possible to recognize the load
2687 // fold cause it has two uses through a bitcast. One use disappears at isel
2688 // time and the fold opportunity reappears.
2689 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2690 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2693 let Predicates = [UseSSE2] in {
2694 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2695 // problem is during lowering, where it's not possible to recognize the load
2696 // fold cause it has two uses through a bitcast. One use disappears at isel
2697 // time and the fold opportunity reappears.
2698 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2699 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2702 //===----------------------------------------------------------------------===//
2703 // SSE 1 & 2 - Extract Floating-Point Sign mask
2704 //===----------------------------------------------------------------------===//
2706 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2707 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2709 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2710 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2711 [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2712 Sched<[WriteVecLogic]>;
2713 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2714 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2715 IIC_SSE_MOVMSK, d>, REX_W, Sched<[WriteVecLogic]>;
2718 let Predicates = [HasAVX] in {
2719 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2720 "movmskps", SSEPackedSingle>, TB, VEX;
2721 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2722 "movmskpd", SSEPackedDouble>, TB,
2724 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2725 "movmskps", SSEPackedSingle>, TB,
2727 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2728 "movmskpd", SSEPackedDouble>, TB,
2731 def : Pat<(i32 (X86fgetsign FR32:$src)),
2732 (VMOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2733 def : Pat<(i64 (X86fgetsign FR32:$src)),
2734 (VMOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2735 def : Pat<(i32 (X86fgetsign FR64:$src)),
2736 (VMOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2737 def : Pat<(i64 (X86fgetsign FR64:$src)),
2738 (VMOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2741 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2742 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2743 SSEPackedSingle>, TB, VEX, Sched<[WriteVecLogic]>;
2744 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2745 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2746 SSEPackedDouble>, TB,
2747 OpSize, VEX, Sched<[WriteVecLogic]>;
2748 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2749 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2750 SSEPackedSingle>, TB, VEX, VEX_L, Sched<[WriteVecLogic]>;
2751 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2752 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2753 SSEPackedDouble>, TB,
2754 OpSize, VEX, VEX_L, Sched<[WriteVecLogic]>;
2757 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2758 SSEPackedSingle>, TB;
2759 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2760 SSEPackedDouble>, TB, OpSize;
2762 def : Pat<(i32 (X86fgetsign FR32:$src)),
2763 (MOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2764 Requires<[UseSSE1]>;
2765 def : Pat<(i64 (X86fgetsign FR32:$src)),
2766 (MOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2767 Requires<[UseSSE1]>;
2768 def : Pat<(i32 (X86fgetsign FR64:$src)),
2769 (MOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2770 Requires<[UseSSE2]>;
2771 def : Pat<(i64 (X86fgetsign FR64:$src)),
2772 (MOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2773 Requires<[UseSSE2]>;
2775 //===---------------------------------------------------------------------===//
2776 // SSE2 - Packed Integer Logical Instructions
2777 //===---------------------------------------------------------------------===//
2779 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2781 /// PDI_binop_rm - Simple SSE2 binary operator.
2782 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2783 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2784 X86MemOperand x86memop, OpndItins itins,
2785 bit IsCommutable, bit Is2Addr> {
2786 let isCommutable = IsCommutable in
2787 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2788 (ins RC:$src1, RC:$src2),
2790 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2791 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2792 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2793 Sched<[itins.Sched]>;
2794 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2795 (ins RC:$src1, x86memop:$src2),
2797 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2798 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2799 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2800 (bitconvert (memop_frag addr:$src2)))))],
2802 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2804 } // ExeDomain = SSEPackedInt
2806 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2807 ValueType OpVT128, ValueType OpVT256,
2808 OpndItins itins, bit IsCommutable = 0> {
2809 let Predicates = [HasAVX] in
2810 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2811 VR128, memopv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2813 let Constraints = "$src1 = $dst" in
2814 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2815 memopv2i64, i128mem, itins, IsCommutable, 1>;
2817 let Predicates = [HasAVX2] in
2818 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2819 OpVT256, VR256, memopv4i64, i256mem, itins,
2820 IsCommutable, 0>, VEX_4V, VEX_L;
2823 // These are ordered here for pattern ordering requirements with the fp versions
2825 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2826 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2827 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2828 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2829 SSE_BIT_ITINS_P, 0>;
2831 //===----------------------------------------------------------------------===//
2832 // SSE 1 & 2 - Logical Instructions
2833 //===----------------------------------------------------------------------===//
2835 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2837 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2838 SDNode OpNode, OpndItins itins> {
2839 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2840 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2843 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2844 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2847 let Constraints = "$src1 = $dst" in {
2848 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2849 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2852 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2853 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2858 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2859 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2861 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2863 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2866 let isCommutable = 0 in
2867 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", X86fandn,
2870 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2872 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2874 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2875 !strconcat(OpcodeStr, "ps"), f256mem,
2876 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2877 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2878 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V, VEX_L;
2880 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2881 !strconcat(OpcodeStr, "pd"), f256mem,
2882 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2883 (bc_v4i64 (v4f64 VR256:$src2))))],
2884 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2885 (memopv4i64 addr:$src2)))], 0>,
2886 TB, OpSize, VEX_4V, VEX_L;
2888 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2889 // are all promoted to v2i64, and the patterns are covered by the int
2890 // version. This is needed in SSE only, because v2i64 isn't supported on
2891 // SSE1, but only on SSE2.
2892 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2893 !strconcat(OpcodeStr, "ps"), f128mem, [],
2894 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2895 (memopv2i64 addr:$src2)))], 0>, TB, VEX_4V;
2897 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2898 !strconcat(OpcodeStr, "pd"), f128mem,
2899 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2900 (bc_v2i64 (v2f64 VR128:$src2))))],
2901 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2902 (memopv2i64 addr:$src2)))], 0>,
2905 let Constraints = "$src1 = $dst" in {
2906 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2907 !strconcat(OpcodeStr, "ps"), f128mem,
2908 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2909 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2910 (memopv2i64 addr:$src2)))]>, TB;
2912 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2913 !strconcat(OpcodeStr, "pd"), f128mem,
2914 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2915 (bc_v2i64 (v2f64 VR128:$src2))))],
2916 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2917 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2921 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2922 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2923 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2924 let isCommutable = 0 in
2925 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2927 //===----------------------------------------------------------------------===//
2928 // SSE 1 & 2 - Arithmetic Instructions
2929 //===----------------------------------------------------------------------===//
2931 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2934 /// In addition, we also have a special variant of the scalar form here to
2935 /// represent the associated intrinsic operation. This form is unlike the
2936 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2937 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2939 /// These three forms can each be reg+reg or reg+mem.
2942 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2944 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
2945 SDNode OpNode, SizeItins itins> {
2946 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2947 VR128, v4f32, f128mem, memopv4f32,
2948 SSEPackedSingle, itins.s, 0>, TB, VEX_4V;
2949 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2950 VR128, v2f64, f128mem, memopv2f64,
2951 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V;
2953 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
2954 OpNode, VR256, v8f32, f256mem, memopv8f32,
2955 SSEPackedSingle, itins.s, 0>, TB, VEX_4V, VEX_L;
2956 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
2957 OpNode, VR256, v4f64, f256mem, memopv4f64,
2958 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V, VEX_L;
2960 let Constraints = "$src1 = $dst" in {
2961 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2962 v4f32, f128mem, memopv4f32, SSEPackedSingle,
2964 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2965 v2f64, f128mem, memopv2f64, SSEPackedDouble,
2966 itins.d>, TB, OpSize;
2970 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2972 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2973 OpNode, FR32, f32mem, itins.s, 0>, XS, VEX_4V, VEX_LIG;
2974 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2975 OpNode, FR64, f64mem, itins.d, 0>, XD, VEX_4V, VEX_LIG;
2977 let Constraints = "$src1 = $dst" in {
2978 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2979 OpNode, FR32, f32mem, itins.s>, XS;
2980 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2981 OpNode, FR64, f64mem, itins.d>, XD;
2985 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2987 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2988 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2989 itins.s, 0>, XS, VEX_4V, VEX_LIG;
2990 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2991 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2992 itins.d, 0>, XD, VEX_4V, VEX_LIG;
2994 let Constraints = "$src1 = $dst" in {
2995 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2996 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2998 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2999 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3004 // Binary Arithmetic instructions
3005 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3006 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3007 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3008 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3009 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3010 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3011 let isCommutable = 0 in {
3012 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3013 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3014 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3015 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3016 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3017 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3018 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3019 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3020 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3021 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3022 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3023 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3026 let isCodeGenOnly = 1 in {
3027 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3028 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3029 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3030 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3034 /// In addition, we also have a special variant of the scalar form here to
3035 /// represent the associated intrinsic operation. This form is unlike the
3036 /// plain scalar form, in that it takes an entire vector (instead of a
3037 /// scalar) and leaves the top elements undefined.
3039 /// And, we have a special variant form for a full-vector intrinsic form.
3041 let Sched = WriteFSqrt in {
3042 def SSE_SQRTPS : OpndItins<
3043 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3046 def SSE_SQRTSS : OpndItins<
3047 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3050 def SSE_SQRTPD : OpndItins<
3051 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3054 def SSE_SQRTSD : OpndItins<
3055 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3059 let Sched = WriteFRcp in {
3060 def SSE_RCPP : OpndItins<
3061 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3064 def SSE_RCPS : OpndItins<
3065 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3069 /// sse1_fp_unop_s - SSE1 unops in scalar form.
3070 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3071 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3072 let Predicates = [HasAVX], hasSideEffects = 0 in {
3073 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3074 (ins FR32:$src1, FR32:$src2),
3075 !strconcat("v", OpcodeStr,
3076 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3077 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3078 let mayLoad = 1 in {
3079 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3080 (ins FR32:$src1,f32mem:$src2),
3081 !strconcat("v", OpcodeStr,
3082 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3083 []>, VEX_4V, VEX_LIG,
3084 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3085 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3086 (ins VR128:$src1, ssmem:$src2),
3087 !strconcat("v", OpcodeStr,
3088 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3089 []>, VEX_4V, VEX_LIG,
3090 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3094 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3095 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3096 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3097 // For scalar unary operations, fold a load into the operation
3098 // only in OptForSize mode. It eliminates an instruction, but it also
3099 // eliminates a whole-register clobber (the load), so it introduces a
3100 // partial register update condition.
3101 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3102 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3103 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3104 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3105 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3106 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3107 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>,
3108 Sched<[itins.Sched]>;
3109 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3110 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3111 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>,
3112 Sched<[itins.Sched.Folded]>;
3115 /// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.
3116 multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,
3118 let Predicates = [HasAVX], hasSideEffects = 0 in {
3119 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3120 (ins FR32:$src1, FR32:$src2),
3121 !strconcat("v", OpcodeStr,
3122 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3123 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3124 let mayLoad = 1 in {
3125 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3126 (ins FR32:$src1,f32mem:$src2),
3127 !strconcat("v", OpcodeStr,
3128 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3129 []>, VEX_4V, VEX_LIG,
3130 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3131 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3132 (ins VR128:$src1, ssmem:$src2),
3133 !strconcat("v", OpcodeStr,
3134 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3135 []>, VEX_4V, VEX_LIG,
3136 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3140 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3141 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3142 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3143 // For scalar unary operations, fold a load into the operation
3144 // only in OptForSize mode. It eliminates an instruction, but it also
3145 // eliminates a whole-register clobber (the load), so it introduces a
3146 // partial register update condition.
3147 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3148 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3149 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3150 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3151 let Constraints = "$src1 = $dst" in {
3152 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3153 (ins VR128:$src1, VR128:$src2),
3154 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3155 [], itins.rr>, Sched<[itins.Sched]>;
3156 let mayLoad = 1, hasSideEffects = 0 in
3157 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3158 (ins VR128:$src1, ssmem:$src2),
3159 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3160 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3164 /// sse1_fp_unop_p - SSE1 unops in packed form.
3165 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3167 let Predicates = [HasAVX] in {
3168 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3169 !strconcat("v", OpcodeStr,
3170 "ps\t{$src, $dst|$dst, $src}"),
3171 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3172 itins.rr>, VEX, Sched<[itins.Sched]>;
3173 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3174 !strconcat("v", OpcodeStr,
3175 "ps\t{$src, $dst|$dst, $src}"),
3176 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))],
3177 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3178 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3179 !strconcat("v", OpcodeStr,
3180 "ps\t{$src, $dst|$dst, $src}"),
3181 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3182 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3183 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3184 !strconcat("v", OpcodeStr,
3185 "ps\t{$src, $dst|$dst, $src}"),
3186 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))],
3187 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3190 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3191 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3192 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3193 Sched<[itins.Sched]>;
3194 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3195 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3196 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3197 Sched<[itins.Sched.Folded]>;
3200 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3201 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3202 Intrinsic V4F32Int, Intrinsic V8F32Int,
3204 let Predicates = [HasAVX] in {
3205 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3206 !strconcat("v", OpcodeStr,
3207 "ps\t{$src, $dst|$dst, $src}"),
3208 [(set VR128:$dst, (V4F32Int VR128:$src))],
3209 itins.rr>, VEX, Sched<[itins.Sched]>;
3210 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3211 !strconcat("v", OpcodeStr,
3212 "ps\t{$src, $dst|$dst, $src}"),
3213 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3214 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3215 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3216 !strconcat("v", OpcodeStr,
3217 "ps\t{$src, $dst|$dst, $src}"),
3218 [(set VR256:$dst, (V8F32Int VR256:$src))],
3219 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3220 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3222 !strconcat("v", OpcodeStr,
3223 "ps\t{$src, $dst|$dst, $src}"),
3224 [(set VR256:$dst, (V8F32Int (memopv8f32 addr:$src)))],
3225 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3228 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3229 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3230 [(set VR128:$dst, (V4F32Int VR128:$src))],
3231 itins.rr>, Sched<[itins.Sched]>;
3232 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3233 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3234 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3235 itins.rm>, Sched<[itins.Sched.Folded]>;
3238 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3239 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3240 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3241 let Predicates = [HasAVX], hasSideEffects = 0 in {
3242 def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),
3243 (ins FR64:$src1, FR64:$src2),
3244 !strconcat("v", OpcodeStr,
3245 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3246 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3247 let mayLoad = 1 in {
3248 def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
3249 (ins FR64:$src1,f64mem:$src2),
3250 !strconcat("v", OpcodeStr,
3251 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3252 []>, VEX_4V, VEX_LIG,
3253 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3254 def V#NAME#SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3255 (ins VR128:$src1, sdmem:$src2),
3256 !strconcat("v", OpcodeStr,
3257 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3258 []>, VEX_4V, VEX_LIG,
3259 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3263 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3264 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3265 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>,
3266 Sched<[itins.Sched]>;
3267 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3268 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3269 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3270 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3271 Requires<[UseSSE2, OptForSize]>, Sched<[itins.Sched.Folded]>;
3272 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3273 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3274 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>,
3275 Sched<[itins.Sched]>;
3276 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3277 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3278 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>,
3279 Sched<[itins.Sched.Folded]>;
3282 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3283 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3284 SDNode OpNode, OpndItins itins> {
3285 let Predicates = [HasAVX] in {
3286 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3287 !strconcat("v", OpcodeStr,
3288 "pd\t{$src, $dst|$dst, $src}"),
3289 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3290 itins.rr>, VEX, Sched<[itins.Sched]>;
3291 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3292 !strconcat("v", OpcodeStr,
3293 "pd\t{$src, $dst|$dst, $src}"),
3294 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))],
3295 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3296 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3297 !strconcat("v", OpcodeStr,
3298 "pd\t{$src, $dst|$dst, $src}"),
3299 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3300 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3301 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3302 !strconcat("v", OpcodeStr,
3303 "pd\t{$src, $dst|$dst, $src}"),
3304 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))],
3305 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3308 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3309 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3310 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3311 Sched<[itins.Sched]>;
3312 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3313 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3314 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3315 Sched<[itins.Sched.Folded]>;
3319 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3321 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3322 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3324 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3326 // Reciprocal approximations. Note that these typically require refinement
3327 // in order to obtain suitable precision.
3328 defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_SQRTSS>,
3329 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTPS>,
3330 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3331 int_x86_avx_rsqrt_ps_256, SSE_SQRTPS>;
3332 defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>,
3333 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3334 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3335 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3337 let Predicates = [UseAVX] in {
3338 def : Pat<(f32 (fsqrt FR32:$src)),
3339 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3340 def : Pat<(f32 (fsqrt (load addr:$src))),
3341 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3342 Requires<[HasAVX, OptForSize]>;
3343 def : Pat<(f64 (fsqrt FR64:$src)),
3344 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3345 def : Pat<(f64 (fsqrt (load addr:$src))),
3346 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3347 Requires<[HasAVX, OptForSize]>;
3349 def : Pat<(f32 (X86frsqrt FR32:$src)),
3350 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3351 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3352 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3353 Requires<[HasAVX, OptForSize]>;
3355 def : Pat<(f32 (X86frcp FR32:$src)),
3356 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3357 def : Pat<(f32 (X86frcp (load addr:$src))),
3358 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3359 Requires<[HasAVX, OptForSize]>;
3361 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3362 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3363 (COPY_TO_REGCLASS VR128:$src, FR32)),
3365 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3366 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3368 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3369 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3370 (COPY_TO_REGCLASS VR128:$src, FR64)),
3372 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3373 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3375 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3376 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3377 (COPY_TO_REGCLASS VR128:$src, FR32)),
3379 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3380 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3382 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3383 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3384 (COPY_TO_REGCLASS VR128:$src, FR32)),
3386 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3387 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3390 // Reciprocal approximations. Note that these typically require refinement
3391 // in order to obtain suitable precision.
3392 let Predicates = [UseSSE1] in {
3393 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3394 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3395 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3396 (RCPSSr_Int VR128:$src, VR128:$src)>;
3399 // There is no f64 version of the reciprocal approximation instructions.
3401 //===----------------------------------------------------------------------===//
3402 // SSE 1 & 2 - Non-temporal stores
3403 //===----------------------------------------------------------------------===//
3405 let AddedComplexity = 400 in { // Prefer non-temporal versions
3406 let SchedRW = [WriteStore] in {
3407 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3408 (ins f128mem:$dst, VR128:$src),
3409 "movntps\t{$src, $dst|$dst, $src}",
3410 [(alignednontemporalstore (v4f32 VR128:$src),
3412 IIC_SSE_MOVNT>, VEX;
3413 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3414 (ins f128mem:$dst, VR128:$src),
3415 "movntpd\t{$src, $dst|$dst, $src}",
3416 [(alignednontemporalstore (v2f64 VR128:$src),
3418 IIC_SSE_MOVNT>, VEX;
3420 let ExeDomain = SSEPackedInt in
3421 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3422 (ins f128mem:$dst, VR128:$src),
3423 "movntdq\t{$src, $dst|$dst, $src}",
3424 [(alignednontemporalstore (v2i64 VR128:$src),
3426 IIC_SSE_MOVNT>, VEX;
3428 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3429 (ins f256mem:$dst, VR256:$src),
3430 "movntps\t{$src, $dst|$dst, $src}",
3431 [(alignednontemporalstore (v8f32 VR256:$src),
3433 IIC_SSE_MOVNT>, VEX, VEX_L;
3434 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3435 (ins f256mem:$dst, VR256:$src),
3436 "movntpd\t{$src, $dst|$dst, $src}",
3437 [(alignednontemporalstore (v4f64 VR256:$src),
3439 IIC_SSE_MOVNT>, VEX, VEX_L;
3440 let ExeDomain = SSEPackedInt in
3441 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3442 (ins f256mem:$dst, VR256:$src),
3443 "movntdq\t{$src, $dst|$dst, $src}",
3444 [(alignednontemporalstore (v4i64 VR256:$src),
3446 IIC_SSE_MOVNT>, VEX, VEX_L;
3448 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3449 "movntps\t{$src, $dst|$dst, $src}",
3450 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3452 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3453 "movntpd\t{$src, $dst|$dst, $src}",
3454 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3457 let ExeDomain = SSEPackedInt in
3458 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3459 "movntdq\t{$src, $dst|$dst, $src}",
3460 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3463 // There is no AVX form for instructions below this point
3464 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3465 "movnti{l}\t{$src, $dst|$dst, $src}",
3466 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3468 TB, Requires<[HasSSE2]>;
3469 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3470 "movnti{q}\t{$src, $dst|$dst, $src}",
3471 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3473 TB, Requires<[HasSSE2]>;
3474 } // SchedRW = [WriteStore]
3476 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3477 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3479 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3480 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[UseSSE2]>;
3481 } // AddedComplexity
3483 //===----------------------------------------------------------------------===//
3484 // SSE 1 & 2 - Prefetch and memory fence
3485 //===----------------------------------------------------------------------===//
3487 // Prefetch intrinsic.
3488 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3489 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3490 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3491 IIC_SSE_PREFETCH>, TB;
3492 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3493 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3494 IIC_SSE_PREFETCH>, TB;
3495 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3496 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3497 IIC_SSE_PREFETCH>, TB;
3498 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3499 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3500 IIC_SSE_PREFETCH>, TB;
3503 // FIXME: How should these memory instructions be modeled?
3504 let SchedRW = [WriteLoad] in {
3506 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3507 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3508 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3510 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3511 // was introduced with SSE2, it's backward compatible.
3512 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
3514 // Load, store, and memory fence
3515 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3516 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3517 TB, Requires<[HasSSE1]>;
3518 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3519 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3520 TB, Requires<[HasSSE2]>;
3521 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3522 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3523 TB, Requires<[HasSSE2]>;
3526 def : Pat<(X86SFence), (SFENCE)>;
3527 def : Pat<(X86LFence), (LFENCE)>;
3528 def : Pat<(X86MFence), (MFENCE)>;
3530 //===----------------------------------------------------------------------===//
3531 // SSE 1 & 2 - Load/Store XCSR register
3532 //===----------------------------------------------------------------------===//
3534 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3535 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3536 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3537 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3538 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3539 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3541 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3542 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3543 IIC_SSE_LDMXCSR>, Sched<[WriteLoad]>;
3544 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3545 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3546 IIC_SSE_STMXCSR>, Sched<[WriteStore]>;
3548 //===---------------------------------------------------------------------===//
3549 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3550 //===---------------------------------------------------------------------===//
3552 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3554 let neverHasSideEffects = 1, SchedRW = [WriteMove] in {
3555 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3556 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3558 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3559 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3561 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3562 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3564 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3565 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3570 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
3571 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3572 "movdqa\t{$src, $dst|$dst, $src}", [],
3575 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3576 "movdqa\t{$src, $dst|$dst, $src}", [],
3577 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3578 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3579 "movdqu\t{$src, $dst|$dst, $src}", [],
3582 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3583 "movdqu\t{$src, $dst|$dst, $src}", [],
3584 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3587 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3588 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3589 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3590 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3592 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3593 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3595 let Predicates = [HasAVX] in {
3596 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3597 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3599 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3600 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3605 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3606 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3607 (ins i128mem:$dst, VR128:$src),
3608 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3610 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3611 (ins i256mem:$dst, VR256:$src),
3612 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3614 let Predicates = [HasAVX] in {
3615 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3616 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3618 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3619 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3624 let SchedRW = [WriteMove] in {
3625 let neverHasSideEffects = 1 in
3626 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3627 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3629 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3630 "movdqu\t{$src, $dst|$dst, $src}",
3631 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3634 let isCodeGenOnly = 1, hasSideEffects = 0 in {
3635 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3636 "movdqa\t{$src, $dst|$dst, $src}", [],
3639 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3640 "movdqu\t{$src, $dst|$dst, $src}",
3641 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3645 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3646 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3647 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3648 "movdqa\t{$src, $dst|$dst, $src}",
3649 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3651 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3652 "movdqu\t{$src, $dst|$dst, $src}",
3653 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3655 XS, Requires<[UseSSE2]>;
3658 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3659 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3660 "movdqa\t{$src, $dst|$dst, $src}",
3661 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3663 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3664 "movdqu\t{$src, $dst|$dst, $src}",
3665 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3667 XS, Requires<[UseSSE2]>;
3670 } // ExeDomain = SSEPackedInt
3672 let Predicates = [HasAVX] in {
3673 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3674 (VMOVDQUmr addr:$dst, VR128:$src)>;
3675 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3676 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3678 let Predicates = [UseSSE2] in
3679 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3680 (MOVDQUmr addr:$dst, VR128:$src)>;
3682 //===---------------------------------------------------------------------===//
3683 // SSE2 - Packed Integer Arithmetic Instructions
3684 //===---------------------------------------------------------------------===//
3686 let Sched = WriteVecIMul in
3687 def SSE_PMADD : OpndItins<
3688 IIC_SSE_PMADD, IIC_SSE_PMADD
3691 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3693 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3694 RegisterClass RC, PatFrag memop_frag,
3695 X86MemOperand x86memop,
3697 bit IsCommutable = 0,
3699 let isCommutable = IsCommutable in
3700 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3701 (ins RC:$src1, RC:$src2),
3703 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3704 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3705 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
3706 Sched<[itins.Sched]>;
3707 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3708 (ins RC:$src1, x86memop:$src2),
3710 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3711 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3712 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3713 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3716 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3717 Intrinsic IntId256, OpndItins itins,
3718 bit IsCommutable = 0> {
3719 let Predicates = [HasAVX] in
3720 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3721 VR128, memopv2i64, i128mem, itins,
3722 IsCommutable, 0>, VEX_4V;
3724 let Constraints = "$src1 = $dst" in
3725 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3726 i128mem, itins, IsCommutable, 1>;
3728 let Predicates = [HasAVX2] in
3729 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3730 VR256, memopv4i64, i256mem, itins,
3731 IsCommutable, 0>, VEX_4V, VEX_L;
3734 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3735 string OpcodeStr, SDNode OpNode,
3736 SDNode OpNode2, RegisterClass RC,
3737 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3738 ShiftOpndItins itins,
3740 // src2 is always 128-bit
3741 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3742 (ins RC:$src1, VR128:$src2),
3744 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3745 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3746 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3747 itins.rr>, Sched<[WriteVecShift]>;
3748 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3749 (ins RC:$src1, i128mem:$src2),
3751 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3752 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3753 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3754 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>,
3755 Sched<[WriteVecShiftLd, ReadAfterLd]>;
3756 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3757 (ins RC:$src1, i32i8imm:$src2),
3759 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3760 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3761 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))], itins.ri>,
3762 Sched<[WriteVecShift]>;
3765 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
3766 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3767 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3768 PatFrag memop_frag, X86MemOperand x86memop,
3770 bit IsCommutable = 0, bit Is2Addr = 1> {
3771 let isCommutable = IsCommutable in
3772 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3773 (ins RC:$src1, RC:$src2),
3775 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3776 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3777 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
3778 Sched<[itins.Sched]>;
3779 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3780 (ins RC:$src1, x86memop:$src2),
3782 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3783 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3784 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3785 (bitconvert (memop_frag addr:$src2)))))]>,
3786 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3788 } // ExeDomain = SSEPackedInt
3790 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
3791 SSE_INTALU_ITINS_P, 1>;
3792 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
3793 SSE_INTALU_ITINS_P, 1>;
3794 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
3795 SSE_INTALU_ITINS_P, 1>;
3796 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
3797 SSE_INTALUQ_ITINS_P, 1>;
3798 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
3799 SSE_INTMUL_ITINS_P, 1>;
3800 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
3801 SSE_INTALU_ITINS_P, 0>;
3802 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
3803 SSE_INTALU_ITINS_P, 0>;
3804 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
3805 SSE_INTALU_ITINS_P, 0>;
3806 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
3807 SSE_INTALUQ_ITINS_P, 0>;
3808 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
3809 SSE_INTALU_ITINS_P, 0>;
3810 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
3811 SSE_INTALU_ITINS_P, 0>;
3812 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
3813 SSE_INTALU_ITINS_P, 1>;
3814 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
3815 SSE_INTALU_ITINS_P, 1>;
3816 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
3817 SSE_INTALU_ITINS_P, 1>;
3818 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
3819 SSE_INTALU_ITINS_P, 1>;
3822 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
3823 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
3824 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3825 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
3826 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3827 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
3828 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3829 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
3830 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3831 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
3832 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3833 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
3834 defm PMULHUW : PDI_binop_all_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3835 int_x86_avx2_pmulhu_w, SSE_INTMUL_ITINS_P, 1>;
3836 defm PMULHW : PDI_binop_all_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3837 int_x86_avx2_pmulh_w, SSE_INTMUL_ITINS_P, 1>;
3838 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3839 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
3840 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3841 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
3842 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3843 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
3844 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3845 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
3847 let Predicates = [HasAVX] in
3848 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3849 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3851 let Predicates = [HasAVX2] in
3852 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3853 VR256, memopv4i64, i256mem,
3854 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3855 let Constraints = "$src1 = $dst" in
3856 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3857 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3859 //===---------------------------------------------------------------------===//
3860 // SSE2 - Packed Integer Logical Instructions
3861 //===---------------------------------------------------------------------===//
3863 let Predicates = [HasAVX] in {
3864 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3865 VR128, v8i16, v8i16, bc_v8i16,
3866 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3867 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3868 VR128, v4i32, v4i32, bc_v4i32,
3869 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3870 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3871 VR128, v2i64, v2i64, bc_v2i64,
3872 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3874 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3875 VR128, v8i16, v8i16, bc_v8i16,
3876 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3877 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3878 VR128, v4i32, v4i32, bc_v4i32,
3879 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3880 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3881 VR128, v2i64, v2i64, bc_v2i64,
3882 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3884 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3885 VR128, v8i16, v8i16, bc_v8i16,
3886 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3887 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3888 VR128, v4i32, v4i32, bc_v4i32,
3889 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3891 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
3892 // 128-bit logical shifts.
3893 def VPSLLDQri : PDIi8<0x73, MRM7r,
3894 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3895 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3897 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3899 def VPSRLDQri : PDIi8<0x73, MRM3r,
3900 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3901 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3903 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3905 // PSRADQri doesn't exist in SSE[1-3].
3907 } // Predicates = [HasAVX]
3909 let Predicates = [HasAVX2] in {
3910 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3911 VR256, v16i16, v8i16, bc_v8i16,
3912 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3913 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3914 VR256, v8i32, v4i32, bc_v4i32,
3915 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3916 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3917 VR256, v4i64, v2i64, bc_v2i64,
3918 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3920 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3921 VR256, v16i16, v8i16, bc_v8i16,
3922 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3923 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3924 VR256, v8i32, v4i32, bc_v4i32,
3925 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3926 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3927 VR256, v4i64, v2i64, bc_v2i64,
3928 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3930 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3931 VR256, v16i16, v8i16, bc_v8i16,
3932 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3933 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3934 VR256, v8i32, v4i32, bc_v4i32,
3935 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3937 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
3938 // 256-bit logical shifts.
3939 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3940 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3941 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3943 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
3945 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3946 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3947 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3949 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
3951 // PSRADQYri doesn't exist in SSE[1-3].
3953 } // Predicates = [HasAVX2]
3955 let Constraints = "$src1 = $dst" in {
3956 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
3957 VR128, v8i16, v8i16, bc_v8i16,
3958 SSE_INTSHIFT_ITINS_P>;
3959 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
3960 VR128, v4i32, v4i32, bc_v4i32,
3961 SSE_INTSHIFT_ITINS_P>;
3962 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
3963 VR128, v2i64, v2i64, bc_v2i64,
3964 SSE_INTSHIFT_ITINS_P>;
3966 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
3967 VR128, v8i16, v8i16, bc_v8i16,
3968 SSE_INTSHIFT_ITINS_P>;
3969 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
3970 VR128, v4i32, v4i32, bc_v4i32,
3971 SSE_INTSHIFT_ITINS_P>;
3972 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
3973 VR128, v2i64, v2i64, bc_v2i64,
3974 SSE_INTSHIFT_ITINS_P>;
3976 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
3977 VR128, v8i16, v8i16, bc_v8i16,
3978 SSE_INTSHIFT_ITINS_P>;
3979 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
3980 VR128, v4i32, v4i32, bc_v4i32,
3981 SSE_INTSHIFT_ITINS_P>;
3983 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
3984 // 128-bit logical shifts.
3985 def PSLLDQri : PDIi8<0x73, MRM7r,
3986 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3987 "pslldq\t{$src2, $dst|$dst, $src2}",
3989 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))],
3990 IIC_SSE_INTSHDQ_P_RI>;
3991 def PSRLDQri : PDIi8<0x73, MRM3r,
3992 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3993 "psrldq\t{$src2, $dst|$dst, $src2}",
3995 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))],
3996 IIC_SSE_INTSHDQ_P_RI>;
3997 // PSRADQri doesn't exist in SSE[1-3].
3999 } // Constraints = "$src1 = $dst"
4001 let Predicates = [HasAVX] in {
4002 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4003 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4004 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4005 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4006 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4007 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4009 // Shift up / down and insert zero's.
4010 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4011 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4012 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4013 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4016 let Predicates = [HasAVX2] in {
4017 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4018 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4019 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4020 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4023 let Predicates = [UseSSE2] in {
4024 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4025 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4026 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4027 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4028 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4029 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4031 // Shift up / down and insert zero's.
4032 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4033 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4034 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4035 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4038 //===---------------------------------------------------------------------===//
4039 // SSE2 - Packed Integer Comparison Instructions
4040 //===---------------------------------------------------------------------===//
4042 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4043 SSE_INTALU_ITINS_P, 1>;
4044 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4045 SSE_INTALU_ITINS_P, 1>;
4046 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4047 SSE_INTALU_ITINS_P, 1>;
4048 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4049 SSE_INTALU_ITINS_P, 0>;
4050 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4051 SSE_INTALU_ITINS_P, 0>;
4052 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4053 SSE_INTALU_ITINS_P, 0>;
4055 //===---------------------------------------------------------------------===//
4056 // SSE2 - Packed Integer Pack Instructions
4057 //===---------------------------------------------------------------------===//
4059 defm PACKSSWB : PDI_binop_all_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4060 int_x86_avx2_packsswb, SSE_INTALU_ITINS_P, 0>;
4061 defm PACKSSDW : PDI_binop_all_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4062 int_x86_avx2_packssdw, SSE_INTALU_ITINS_P, 0>;
4063 defm PACKUSWB : PDI_binop_all_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4064 int_x86_avx2_packuswb, SSE_INTALU_ITINS_P, 0>;
4066 //===---------------------------------------------------------------------===//
4067 // SSE2 - Packed Integer Shuffle Instructions
4068 //===---------------------------------------------------------------------===//
4070 let ExeDomain = SSEPackedInt in {
4071 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4073 let Predicates = [HasAVX] in {
4074 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4075 (ins VR128:$src1, i8imm:$src2),
4076 !strconcat("v", OpcodeStr,
4077 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4079 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4080 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4081 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4082 (ins i128mem:$src1, i8imm:$src2),
4083 !strconcat("v", OpcodeStr,
4084 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4086 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4087 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4088 Sched<[WriteShuffleLd]>;
4091 let Predicates = [HasAVX2] in {
4092 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4093 (ins VR256:$src1, i8imm:$src2),
4094 !strconcat("v", OpcodeStr,
4095 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4097 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4098 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4099 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4100 (ins i256mem:$src1, i8imm:$src2),
4101 !strconcat("v", OpcodeStr,
4102 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4104 (vt256 (OpNode (bitconvert (memopv4i64 addr:$src1)),
4105 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4106 Sched<[WriteShuffleLd]>;
4109 let Predicates = [UseSSE2] in {
4110 def ri : Ii8<0x70, MRMSrcReg,
4111 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4112 !strconcat(OpcodeStr,
4113 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4115 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4116 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4117 def mi : Ii8<0x70, MRMSrcMem,
4118 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4119 !strconcat(OpcodeStr,
4120 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4122 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4123 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4124 Sched<[WriteShuffleLd]>;
4127 } // ExeDomain = SSEPackedInt
4129 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, TB, OpSize;
4130 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4131 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4133 let Predicates = [HasAVX] in {
4134 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4135 (VPSHUFDmi addr:$src1, imm:$imm)>;
4136 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4137 (VPSHUFDri VR128:$src1, imm:$imm)>;
4140 let Predicates = [UseSSE2] in {
4141 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4142 (PSHUFDmi addr:$src1, imm:$imm)>;
4143 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4144 (PSHUFDri VR128:$src1, imm:$imm)>;
4147 //===---------------------------------------------------------------------===//
4148 // SSE2 - Packed Integer Unpack Instructions
4149 //===---------------------------------------------------------------------===//
4151 let ExeDomain = SSEPackedInt in {
4152 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4153 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4154 def rr : PDI<opc, MRMSrcReg,
4155 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4157 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4158 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4159 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4160 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4161 def rm : PDI<opc, MRMSrcMem,
4162 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4164 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4165 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4166 [(set VR128:$dst, (OpNode VR128:$src1,
4167 (bc_frag (memopv2i64
4170 Sched<[WriteShuffleLd, ReadAfterLd]>;
4173 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4174 SDNode OpNode, PatFrag bc_frag> {
4175 def Yrr : PDI<opc, MRMSrcReg,
4176 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4177 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4178 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4179 Sched<[WriteShuffle]>;
4180 def Yrm : PDI<opc, MRMSrcMem,
4181 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4182 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4183 [(set VR256:$dst, (OpNode VR256:$src1,
4184 (bc_frag (memopv4i64 addr:$src2))))]>,
4185 Sched<[WriteShuffleLd, ReadAfterLd]>;
4188 let Predicates = [HasAVX] in {
4189 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4190 bc_v16i8, 0>, VEX_4V;
4191 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4192 bc_v8i16, 0>, VEX_4V;
4193 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4194 bc_v4i32, 0>, VEX_4V;
4195 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4196 bc_v2i64, 0>, VEX_4V;
4198 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4199 bc_v16i8, 0>, VEX_4V;
4200 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4201 bc_v8i16, 0>, VEX_4V;
4202 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4203 bc_v4i32, 0>, VEX_4V;
4204 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4205 bc_v2i64, 0>, VEX_4V;
4208 let Predicates = [HasAVX2] in {
4209 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4210 bc_v32i8>, VEX_4V, VEX_L;
4211 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4212 bc_v16i16>, VEX_4V, VEX_L;
4213 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4214 bc_v8i32>, VEX_4V, VEX_L;
4215 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4216 bc_v4i64>, VEX_4V, VEX_L;
4218 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4219 bc_v32i8>, VEX_4V, VEX_L;
4220 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4221 bc_v16i16>, VEX_4V, VEX_L;
4222 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4223 bc_v8i32>, VEX_4V, VEX_L;
4224 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4225 bc_v4i64>, VEX_4V, VEX_L;
4228 let Constraints = "$src1 = $dst" in {
4229 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4231 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4233 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4235 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4238 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4240 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4242 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4244 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4247 } // ExeDomain = SSEPackedInt
4249 //===---------------------------------------------------------------------===//
4250 // SSE2 - Packed Integer Extract and Insert
4251 //===---------------------------------------------------------------------===//
4253 let ExeDomain = SSEPackedInt in {
4254 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4255 def rri : Ii8<0xC4, MRMSrcReg,
4256 (outs VR128:$dst), (ins VR128:$src1,
4257 GR32:$src2, i32i8imm:$src3),
4259 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4260 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4262 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>,
4263 Sched<[WriteShuffle]>;
4264 def rmi : Ii8<0xC4, MRMSrcMem,
4265 (outs VR128:$dst), (ins VR128:$src1,
4266 i16mem:$src2, i32i8imm:$src3),
4268 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4269 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4271 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4272 imm:$src3))], IIC_SSE_PINSRW>,
4273 Sched<[WriteShuffleLd, ReadAfterLd]>;
4277 let Predicates = [HasAVX] in
4278 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4279 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4280 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4281 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4282 imm:$src2))]>, TB, OpSize, VEX,
4283 Sched<[WriteShuffle]>;
4284 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4285 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4286 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4287 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4288 imm:$src2))], IIC_SSE_PEXTRW>,
4289 Sched<[WriteShuffleLd, ReadAfterLd]>;
4292 let Predicates = [HasAVX] in {
4293 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4294 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4295 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4296 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4297 []>, TB, OpSize, VEX_4V, Sched<[WriteShuffle]>;
4300 let Constraints = "$src1 = $dst" in
4301 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[UseSSE2]>;
4303 } // ExeDomain = SSEPackedInt
4305 //===---------------------------------------------------------------------===//
4306 // SSE2 - Packed Mask Creation
4307 //===---------------------------------------------------------------------===//
4309 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4311 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4312 "pmovmskb\t{$src, $dst|$dst, $src}",
4313 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4314 IIC_SSE_MOVMSK>, VEX;
4315 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4316 "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;
4318 let Predicates = [HasAVX2] in {
4319 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4320 "pmovmskb\t{$src, $dst|$dst, $src}",
4321 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX, VEX_L;
4322 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4323 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4326 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4327 "pmovmskb\t{$src, $dst|$dst, $src}",
4328 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4331 } // ExeDomain = SSEPackedInt
4333 //===---------------------------------------------------------------------===//
4334 // SSE2 - Conditional Store
4335 //===---------------------------------------------------------------------===//
4337 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4339 let Uses = [EDI], Predicates = [HasAVX,In32BitMode] in
4340 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4341 (ins VR128:$src, VR128:$mask),
4342 "maskmovdqu\t{$mask, $src|$src, $mask}",
4343 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4344 IIC_SSE_MASKMOV>, VEX;
4345 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4346 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4347 (ins VR128:$src, VR128:$mask),
4348 "maskmovdqu\t{$mask, $src|$src, $mask}",
4349 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4350 IIC_SSE_MASKMOV>, VEX;
4352 let Uses = [EDI], Predicates = [UseSSE2,In32BitMode] in
4353 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4354 "maskmovdqu\t{$mask, $src|$src, $mask}",
4355 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4357 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4358 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4359 "maskmovdqu\t{$mask, $src|$src, $mask}",
4360 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4363 } // ExeDomain = SSEPackedInt
4365 //===---------------------------------------------------------------------===//
4366 // SSE2 - Move Doubleword
4367 //===---------------------------------------------------------------------===//
4369 //===---------------------------------------------------------------------===//
4370 // Move Int Doubleword to Packed Double Int
4372 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4373 "movd\t{$src, $dst|$dst, $src}",
4375 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4376 VEX, Sched<[WriteMove]>;
4377 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4378 "movd\t{$src, $dst|$dst, $src}",
4380 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4382 VEX, Sched<[WriteLoad]>;
4383 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4384 "movq\t{$src, $dst|$dst, $src}",
4386 (v2i64 (scalar_to_vector GR64:$src)))],
4387 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4388 let isCodeGenOnly = 1 in
4389 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4390 "movq\t{$src, $dst|$dst, $src}",
4391 [(set FR64:$dst, (bitconvert GR64:$src))],
4392 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4394 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4395 "movd\t{$src, $dst|$dst, $src}",
4397 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4399 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4400 "movd\t{$src, $dst|$dst, $src}",
4402 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4403 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4404 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4405 "mov{d|q}\t{$src, $dst|$dst, $src}",
4407 (v2i64 (scalar_to_vector GR64:$src)))],
4408 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4409 let isCodeGenOnly = 1 in
4410 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4411 "mov{d|q}\t{$src, $dst|$dst, $src}",
4412 [(set FR64:$dst, (bitconvert GR64:$src))],
4413 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4415 //===---------------------------------------------------------------------===//
4416 // Move Int Doubleword to Single Scalar
4418 let isCodeGenOnly = 1 in {
4419 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4420 "movd\t{$src, $dst|$dst, $src}",
4421 [(set FR32:$dst, (bitconvert GR32:$src))],
4422 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4424 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4425 "movd\t{$src, $dst|$dst, $src}",
4426 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4428 VEX, Sched<[WriteLoad]>;
4429 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4430 "movd\t{$src, $dst|$dst, $src}",
4431 [(set FR32:$dst, (bitconvert GR32:$src))],
4432 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4434 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4435 "movd\t{$src, $dst|$dst, $src}",
4436 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4437 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4440 //===---------------------------------------------------------------------===//
4441 // Move Packed Doubleword Int to Packed Double Int
4443 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4444 "movd\t{$src, $dst|$dst, $src}",
4445 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4446 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4448 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4449 (ins i32mem:$dst, VR128:$src),
4450 "movd\t{$src, $dst|$dst, $src}",
4451 [(store (i32 (vector_extract (v4i32 VR128:$src),
4452 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4453 VEX, Sched<[WriteLoad]>;
4454 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4455 "movd\t{$src, $dst|$dst, $src}",
4456 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4457 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4459 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4460 "movd\t{$src, $dst|$dst, $src}",
4461 [(store (i32 (vector_extract (v4i32 VR128:$src),
4462 (iPTR 0))), addr:$dst)],
4463 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4465 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
4466 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4468 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
4469 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4471 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
4472 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4474 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
4475 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4477 //===---------------------------------------------------------------------===//
4478 // Move Packed Doubleword Int first element to Doubleword Int
4480 let SchedRW = [WriteMove] in {
4481 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4482 "movq\t{$src, $dst|$dst, $src}",
4483 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4488 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4489 "mov{d|q}\t{$src, $dst|$dst, $src}",
4490 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4495 //===---------------------------------------------------------------------===//
4496 // Bitcast FR64 <-> GR64
4498 let isCodeGenOnly = 1 in {
4499 let Predicates = [UseAVX] in
4500 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4501 "movq\t{$src, $dst|$dst, $src}",
4502 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4503 VEX, Sched<[WriteLoad]>;
4504 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4505 "movq\t{$src, $dst|$dst, $src}",
4506 [(set GR64:$dst, (bitconvert FR64:$src))],
4507 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4508 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4509 "movq\t{$src, $dst|$dst, $src}",
4510 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4511 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4513 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4514 "movq\t{$src, $dst|$dst, $src}",
4515 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4516 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4517 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4518 "mov{d|q}\t{$src, $dst|$dst, $src}",
4519 [(set GR64:$dst, (bitconvert FR64:$src))],
4520 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4521 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4522 "movq\t{$src, $dst|$dst, $src}",
4523 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4524 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4527 //===---------------------------------------------------------------------===//
4528 // Move Scalar Single to Double Int
4530 let isCodeGenOnly = 1 in {
4531 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4532 "movd\t{$src, $dst|$dst, $src}",
4533 [(set GR32:$dst, (bitconvert FR32:$src))],
4534 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4535 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4536 "movd\t{$src, $dst|$dst, $src}",
4537 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4538 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4539 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4540 "movd\t{$src, $dst|$dst, $src}",
4541 [(set GR32:$dst, (bitconvert FR32:$src))],
4542 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4543 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4544 "movd\t{$src, $dst|$dst, $src}",
4545 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4546 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4549 //===---------------------------------------------------------------------===//
4550 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4552 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
4553 let AddedComplexity = 15 in {
4554 def VMOVZDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4555 "movd\t{$src, $dst|$dst, $src}",
4556 [(set VR128:$dst, (v4i32 (X86vzmovl
4557 (v4i32 (scalar_to_vector GR32:$src)))))],
4558 IIC_SSE_MOVDQ>, VEX;
4559 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4560 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
4561 [(set VR128:$dst, (v2i64 (X86vzmovl
4562 (v2i64 (scalar_to_vector GR64:$src)))))],
4566 let AddedComplexity = 15 in {
4567 def MOVZDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4568 "movd\t{$src, $dst|$dst, $src}",
4569 [(set VR128:$dst, (v4i32 (X86vzmovl
4570 (v4i32 (scalar_to_vector GR32:$src)))))],
4572 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4573 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4574 [(set VR128:$dst, (v2i64 (X86vzmovl
4575 (v2i64 (scalar_to_vector GR64:$src)))))],
4578 } // isCodeGenOnly, SchedRW
4580 let isCodeGenOnly = 1, AddedComplexity = 20, SchedRW = [WriteLoad] in {
4581 def VMOVZDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4582 "movd\t{$src, $dst|$dst, $src}",
4584 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4585 (loadi32 addr:$src))))))],
4586 IIC_SSE_MOVDQ>, VEX;
4587 def MOVZDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4588 "movd\t{$src, $dst|$dst, $src}",
4590 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4591 (loadi32 addr:$src))))))],
4593 } // isCodeGenOnly, AddedComplexity, SchedRW
4595 let Predicates = [UseAVX] in {
4596 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4597 let AddedComplexity = 20 in {
4598 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4599 (VMOVZDI2PDIrm addr:$src)>;
4600 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4601 (VMOVZDI2PDIrm addr:$src)>;
4603 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4604 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4605 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4606 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4607 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4608 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4609 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4612 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4613 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4614 (MOVZDI2PDIrm addr:$src)>;
4615 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4616 (MOVZDI2PDIrm addr:$src)>;
4619 // These are the correct encodings of the instructions so that we know how to
4620 // read correct assembly, even though we continue to emit the wrong ones for
4621 // compatibility with Darwin's buggy assembler.
4622 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4623 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4624 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4625 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4626 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
4627 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4628 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4629 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4630 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4632 //===---------------------------------------------------------------------===//
4633 // SSE2 - Move Quadword
4634 //===---------------------------------------------------------------------===//
4636 //===---------------------------------------------------------------------===//
4637 // Move Quadword Int to Packed Quadword Int
4640 let SchedRW = [WriteLoad] in {
4641 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4642 "vmovq\t{$src, $dst|$dst, $src}",
4644 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4645 VEX, Requires<[UseAVX]>;
4646 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4647 "movq\t{$src, $dst|$dst, $src}",
4649 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4651 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4654 //===---------------------------------------------------------------------===//
4655 // Move Packed Quadword Int to Quadword Int
4657 let SchedRW = [WriteStore] in {
4658 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4659 "movq\t{$src, $dst|$dst, $src}",
4660 [(store (i64 (vector_extract (v2i64 VR128:$src),
4661 (iPTR 0))), addr:$dst)],
4662 IIC_SSE_MOVDQ>, VEX;
4663 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4664 "movq\t{$src, $dst|$dst, $src}",
4665 [(store (i64 (vector_extract (v2i64 VR128:$src),
4666 (iPTR 0))), addr:$dst)],
4670 //===---------------------------------------------------------------------===//
4671 // Store / copy lower 64-bits of a XMM register.
4673 def VMOVLQ128mr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4674 "movq\t{$src, $dst|$dst, $src}",
4675 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX,
4676 Sched<[WriteStore]>;
4677 def MOVLQ128mr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4678 "movq\t{$src, $dst|$dst, $src}",
4679 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4680 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4682 let isCodeGenOnly = 1, AddedComplexity = 20 in {
4683 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4684 "vmovq\t{$src, $dst|$dst, $src}",
4686 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4687 (loadi64 addr:$src))))))],
4689 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
4691 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4692 "movq\t{$src, $dst|$dst, $src}",
4694 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4695 (loadi64 addr:$src))))))],
4697 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
4700 let Predicates = [UseAVX], AddedComplexity = 20 in {
4701 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4702 (VMOVZQI2PQIrm addr:$src)>;
4703 def : Pat<(v2i64 (X86vzload addr:$src)),
4704 (VMOVZQI2PQIrm addr:$src)>;
4707 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4708 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4709 (MOVZQI2PQIrm addr:$src)>;
4710 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4713 let Predicates = [HasAVX] in {
4714 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4715 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4716 def : Pat<(v4i64 (X86vzload addr:$src)),
4717 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4720 //===---------------------------------------------------------------------===//
4721 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4722 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4724 let SchedRW = [WriteVecLogic] in {
4725 let AddedComplexity = 15 in
4726 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4727 "vmovq\t{$src, $dst|$dst, $src}",
4728 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4730 XS, VEX, Requires<[UseAVX]>;
4731 let AddedComplexity = 15 in
4732 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4733 "movq\t{$src, $dst|$dst, $src}",
4734 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4736 XS, Requires<[UseSSE2]>;
4739 let isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
4740 let AddedComplexity = 20 in
4741 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4742 "vmovq\t{$src, $dst|$dst, $src}",
4743 [(set VR128:$dst, (v2i64 (X86vzmovl
4744 (loadv2i64 addr:$src))))],
4746 XS, VEX, Requires<[UseAVX]>;
4747 let AddedComplexity = 20 in {
4748 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4749 "movq\t{$src, $dst|$dst, $src}",
4750 [(set VR128:$dst, (v2i64 (X86vzmovl
4751 (loadv2i64 addr:$src))))],
4753 XS, Requires<[UseSSE2]>;
4755 } // isCodeGenOnly, SchedRW
4757 let AddedComplexity = 20 in {
4758 let Predicates = [UseAVX] in {
4759 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4760 (VMOVZPQILo2PQIrr VR128:$src)>;
4762 let Predicates = [UseSSE2] in {
4763 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4764 (MOVZPQILo2PQIrr VR128:$src)>;
4768 //===---------------------------------------------------------------------===//
4769 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4770 //===---------------------------------------------------------------------===//
4771 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4772 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4773 X86MemOperand x86memop> {
4774 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4775 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4776 [(set RC:$dst, (vt (OpNode RC:$src)))],
4777 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
4778 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4779 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4780 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4781 IIC_SSE_MOV_LH>, Sched<[WriteShuffleLd]>;
4784 let Predicates = [HasAVX] in {
4785 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4786 v4f32, VR128, memopv4f32, f128mem>, VEX;
4787 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4788 v4f32, VR128, memopv4f32, f128mem>, VEX;
4789 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4790 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4791 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4792 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4794 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4795 memopv4f32, f128mem>;
4796 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4797 memopv4f32, f128mem>;
4799 let Predicates = [HasAVX] in {
4800 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4801 (VMOVSHDUPrr VR128:$src)>;
4802 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4803 (VMOVSHDUPrm addr:$src)>;
4804 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4805 (VMOVSLDUPrr VR128:$src)>;
4806 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4807 (VMOVSLDUPrm addr:$src)>;
4808 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4809 (VMOVSHDUPYrr VR256:$src)>;
4810 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4811 (VMOVSHDUPYrm addr:$src)>;
4812 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4813 (VMOVSLDUPYrr VR256:$src)>;
4814 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4815 (VMOVSLDUPYrm addr:$src)>;
4818 let Predicates = [UseSSE3] in {
4819 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4820 (MOVSHDUPrr VR128:$src)>;
4821 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4822 (MOVSHDUPrm addr:$src)>;
4823 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4824 (MOVSLDUPrr VR128:$src)>;
4825 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4826 (MOVSLDUPrm addr:$src)>;
4829 //===---------------------------------------------------------------------===//
4830 // SSE3 - Replicate Double FP - MOVDDUP
4831 //===---------------------------------------------------------------------===//
4833 multiclass sse3_replicate_dfp<string OpcodeStr> {
4834 let neverHasSideEffects = 1 in
4835 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4836 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4837 [], IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
4838 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4839 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4842 (scalar_to_vector (loadf64 addr:$src)))))],
4843 IIC_SSE_MOV_LH>, Sched<[WriteShuffleLd]>;
4846 // FIXME: Merge with above classe when there're patterns for the ymm version
4847 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4848 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4849 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4850 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
4851 Sched<[WriteShuffle]>;
4852 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4853 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4856 (scalar_to_vector (loadf64 addr:$src)))))]>,
4857 Sched<[WriteShuffleLd]>;
4860 let Predicates = [HasAVX] in {
4861 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4862 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
4865 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4867 let Predicates = [HasAVX] in {
4868 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4869 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4870 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4871 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4872 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4873 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4874 def : Pat<(X86Movddup (bc_v2f64
4875 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4876 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4879 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4880 (VMOVDDUPYrm addr:$src)>;
4881 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4882 (VMOVDDUPYrm addr:$src)>;
4883 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4884 (VMOVDDUPYrm addr:$src)>;
4885 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4886 (VMOVDDUPYrr VR256:$src)>;
4889 let Predicates = [UseSSE3] in {
4890 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4891 (MOVDDUPrm addr:$src)>;
4892 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4893 (MOVDDUPrm addr:$src)>;
4894 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4895 (MOVDDUPrm addr:$src)>;
4896 def : Pat<(X86Movddup (bc_v2f64
4897 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4898 (MOVDDUPrm addr:$src)>;
4901 //===---------------------------------------------------------------------===//
4902 // SSE3 - Move Unaligned Integer
4903 //===---------------------------------------------------------------------===//
4905 let SchedRW = [WriteLoad] in {
4906 let Predicates = [HasAVX] in {
4907 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4908 "vlddqu\t{$src, $dst|$dst, $src}",
4909 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4910 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4911 "vlddqu\t{$src, $dst|$dst, $src}",
4912 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
4915 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4916 "lddqu\t{$src, $dst|$dst, $src}",
4917 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
4921 //===---------------------------------------------------------------------===//
4922 // SSE3 - Arithmetic
4923 //===---------------------------------------------------------------------===//
4925 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4926 X86MemOperand x86memop, OpndItins itins,
4928 def rr : I<0xD0, MRMSrcReg,
4929 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4931 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4932 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4933 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
4934 Sched<[itins.Sched]>;
4935 def rm : I<0xD0, MRMSrcMem,
4936 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4938 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4939 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4940 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>,
4941 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4944 let Predicates = [HasAVX] in {
4945 let ExeDomain = SSEPackedSingle in {
4946 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4947 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
4948 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4949 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V, VEX_L;
4951 let ExeDomain = SSEPackedDouble in {
4952 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4953 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
4954 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
4955 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V, VEX_L;
4958 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
4959 let ExeDomain = SSEPackedSingle in
4960 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
4961 f128mem, SSE_ALU_F32P>, TB, XD;
4962 let ExeDomain = SSEPackedDouble in
4963 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
4964 f128mem, SSE_ALU_F64P>, TB, OpSize;
4967 //===---------------------------------------------------------------------===//
4968 // SSE3 Instructions
4969 //===---------------------------------------------------------------------===//
4972 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4973 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4974 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4976 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4977 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4978 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
4981 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4983 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4984 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4985 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
4986 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
4988 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4989 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4990 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4992 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4993 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4994 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
4997 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4999 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5000 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5001 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5002 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5005 let Predicates = [HasAVX] in {
5006 let ExeDomain = SSEPackedSingle in {
5007 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5008 X86fhadd, 0>, VEX_4V;
5009 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5010 X86fhsub, 0>, VEX_4V;
5011 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5012 X86fhadd, 0>, VEX_4V, VEX_L;
5013 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5014 X86fhsub, 0>, VEX_4V, VEX_L;
5016 let ExeDomain = SSEPackedDouble in {
5017 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5018 X86fhadd, 0>, VEX_4V;
5019 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5020 X86fhsub, 0>, VEX_4V;
5021 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5022 X86fhadd, 0>, VEX_4V, VEX_L;
5023 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5024 X86fhsub, 0>, VEX_4V, VEX_L;
5028 let Constraints = "$src1 = $dst" in {
5029 let ExeDomain = SSEPackedSingle in {
5030 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5031 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5033 let ExeDomain = SSEPackedDouble in {
5034 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5035 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5039 //===---------------------------------------------------------------------===//
5040 // SSSE3 - Packed Absolute Instructions
5041 //===---------------------------------------------------------------------===//
5044 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5045 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5046 Intrinsic IntId128> {
5047 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5049 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5050 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5051 OpSize, Sched<[WriteVecALU]>;
5053 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5055 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5058 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5059 OpSize, Sched<[WriteVecALULd]>;
5062 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5063 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5064 Intrinsic IntId256> {
5065 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5067 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5068 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5069 OpSize, Sched<[WriteVecALU]>;
5071 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5073 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5076 (bitconvert (memopv4i64 addr:$src))))]>, OpSize,
5077 Sched<[WriteVecALULd]>;
5080 // Helper fragments to match sext vXi1 to vXiY.
5081 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5083 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i32 15)))>;
5084 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i32 31)))>;
5085 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5087 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i32 15)))>;
5088 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i32 31)))>;
5090 let Predicates = [HasAVX] in {
5091 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5092 int_x86_ssse3_pabs_b_128>, VEX;
5093 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5094 int_x86_ssse3_pabs_w_128>, VEX;
5095 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5096 int_x86_ssse3_pabs_d_128>, VEX;
5099 (bc_v2i64 (v16i1sextv16i8)),
5100 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5101 (VPABSBrr128 VR128:$src)>;
5103 (bc_v2i64 (v8i1sextv8i16)),
5104 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5105 (VPABSWrr128 VR128:$src)>;
5107 (bc_v2i64 (v4i1sextv4i32)),
5108 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5109 (VPABSDrr128 VR128:$src)>;
5112 let Predicates = [HasAVX2] in {
5113 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5114 int_x86_avx2_pabs_b>, VEX, VEX_L;
5115 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5116 int_x86_avx2_pabs_w>, VEX, VEX_L;
5117 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5118 int_x86_avx2_pabs_d>, VEX, VEX_L;
5121 (bc_v4i64 (v32i1sextv32i8)),
5122 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5123 (VPABSBrr256 VR256:$src)>;
5125 (bc_v4i64 (v16i1sextv16i16)),
5126 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5127 (VPABSWrr256 VR256:$src)>;
5129 (bc_v4i64 (v8i1sextv8i32)),
5130 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5131 (VPABSDrr256 VR256:$src)>;
5134 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5135 int_x86_ssse3_pabs_b_128>;
5136 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5137 int_x86_ssse3_pabs_w_128>;
5138 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5139 int_x86_ssse3_pabs_d_128>;
5141 let Predicates = [HasSSSE3] in {
5143 (bc_v2i64 (v16i1sextv16i8)),
5144 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5145 (PABSBrr128 VR128:$src)>;
5147 (bc_v2i64 (v8i1sextv8i16)),
5148 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5149 (PABSWrr128 VR128:$src)>;
5151 (bc_v2i64 (v4i1sextv4i32)),
5152 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5153 (PABSDrr128 VR128:$src)>;
5156 //===---------------------------------------------------------------------===//
5157 // SSSE3 - Packed Binary Operator Instructions
5158 //===---------------------------------------------------------------------===//
5160 let Sched = WriteVecALU in {
5161 def SSE_PHADDSUBD : OpndItins<
5162 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5164 def SSE_PHADDSUBSW : OpndItins<
5165 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5167 def SSE_PHADDSUBW : OpndItins<
5168 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5171 let Sched = WriteShuffle in
5172 def SSE_PSHUFB : OpndItins<
5173 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5175 let Sched = WriteVecALU in
5176 def SSE_PSIGN : OpndItins<
5177 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5179 let Sched = WriteVecIMul in
5180 def SSE_PMULHRSW : OpndItins<
5181 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5184 /// SS3I_binop_rm - Simple SSSE3 bin op
5185 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5186 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5187 X86MemOperand x86memop, OpndItins itins,
5189 let isCommutable = 1 in
5190 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5191 (ins RC:$src1, RC:$src2),
5193 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5194 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5195 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5196 OpSize, Sched<[itins.Sched]>;
5197 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5198 (ins RC:$src1, x86memop:$src2),
5200 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5201 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5203 (OpVT (OpNode RC:$src1,
5204 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize,
5205 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5208 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5209 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5210 Intrinsic IntId128, OpndItins itins,
5212 let isCommutable = 1 in
5213 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5214 (ins VR128:$src1, VR128:$src2),
5216 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5217 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5218 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5219 OpSize, Sched<[itins.Sched]>;
5220 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5221 (ins VR128:$src1, i128mem:$src2),
5223 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5224 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5226 (IntId128 VR128:$src1,
5227 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize,
5228 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5231 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5232 Intrinsic IntId256> {
5233 let isCommutable = 1 in
5234 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5235 (ins VR256:$src1, VR256:$src2),
5236 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5237 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5239 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5240 (ins VR256:$src1, i256mem:$src2),
5241 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5243 (IntId256 VR256:$src1,
5244 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5247 let ImmT = NoImm, Predicates = [HasAVX] in {
5248 let isCommutable = 0 in {
5249 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5250 memopv2i64, i128mem,
5251 SSE_PHADDSUBW, 0>, VEX_4V;
5252 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5253 memopv2i64, i128mem,
5254 SSE_PHADDSUBD, 0>, VEX_4V;
5255 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5256 memopv2i64, i128mem,
5257 SSE_PHADDSUBW, 0>, VEX_4V;
5258 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5259 memopv2i64, i128mem,
5260 SSE_PHADDSUBD, 0>, VEX_4V;
5261 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5262 memopv2i64, i128mem,
5263 SSE_PSIGN, 0>, VEX_4V;
5264 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5265 memopv2i64, i128mem,
5266 SSE_PSIGN, 0>, VEX_4V;
5267 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5268 memopv2i64, i128mem,
5269 SSE_PSIGN, 0>, VEX_4V;
5270 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5271 memopv2i64, i128mem,
5272 SSE_PSHUFB, 0>, VEX_4V;
5273 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5274 int_x86_ssse3_phadd_sw_128,
5275 SSE_PHADDSUBSW, 0>, VEX_4V;
5276 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5277 int_x86_ssse3_phsub_sw_128,
5278 SSE_PHADDSUBSW, 0>, VEX_4V;
5279 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5280 int_x86_ssse3_pmadd_ub_sw_128,
5281 SSE_PMADD, 0>, VEX_4V;
5283 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5284 int_x86_ssse3_pmul_hr_sw_128,
5285 SSE_PMULHRSW, 0>, VEX_4V;
5288 let ImmT = NoImm, Predicates = [HasAVX2] in {
5289 let isCommutable = 0 in {
5290 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5291 memopv4i64, i256mem,
5292 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5293 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5294 memopv4i64, i256mem,
5295 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5296 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5297 memopv4i64, i256mem,
5298 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5299 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5300 memopv4i64, i256mem,
5301 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5302 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5303 memopv4i64, i256mem,
5304 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5305 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5306 memopv4i64, i256mem,
5307 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5308 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5309 memopv4i64, i256mem,
5310 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5311 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5312 memopv4i64, i256mem,
5313 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5314 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5315 int_x86_avx2_phadd_sw>, VEX_4V, VEX_L;
5316 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5317 int_x86_avx2_phsub_sw>, VEX_4V, VEX_L;
5318 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5319 int_x86_avx2_pmadd_ub_sw>, VEX_4V, VEX_L;
5321 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5322 int_x86_avx2_pmul_hr_sw>, VEX_4V, VEX_L;
5325 // None of these have i8 immediate fields.
5326 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5327 let isCommutable = 0 in {
5328 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5329 memopv2i64, i128mem, SSE_PHADDSUBW>;
5330 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5331 memopv2i64, i128mem, SSE_PHADDSUBD>;
5332 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5333 memopv2i64, i128mem, SSE_PHADDSUBW>;
5334 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5335 memopv2i64, i128mem, SSE_PHADDSUBD>;
5336 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5337 memopv2i64, i128mem, SSE_PSIGN>;
5338 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5339 memopv2i64, i128mem, SSE_PSIGN>;
5340 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5341 memopv2i64, i128mem, SSE_PSIGN>;
5342 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5343 memopv2i64, i128mem, SSE_PSHUFB>;
5344 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5345 int_x86_ssse3_phadd_sw_128,
5347 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5348 int_x86_ssse3_phsub_sw_128,
5350 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5351 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5353 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5354 int_x86_ssse3_pmul_hr_sw_128,
5358 //===---------------------------------------------------------------------===//
5359 // SSSE3 - Packed Align Instruction Patterns
5360 //===---------------------------------------------------------------------===//
5362 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5363 let neverHasSideEffects = 1 in {
5364 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5365 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5367 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5369 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5370 [], IIC_SSE_PALIGNRR>, OpSize, Sched<[WriteShuffle]>;
5372 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5373 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5375 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5377 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5378 [], IIC_SSE_PALIGNRM>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
5382 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5383 let neverHasSideEffects = 1 in {
5384 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5385 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5387 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5388 []>, OpSize, Sched<[WriteShuffle]>;
5390 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5391 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5393 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5394 []>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
5398 let Predicates = [HasAVX] in
5399 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5400 let Predicates = [HasAVX2] in
5401 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5402 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5403 defm PALIGN : ssse3_palignr<"palignr">;
5405 let Predicates = [HasAVX2] in {
5406 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5407 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5408 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5409 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5410 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5411 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5412 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5413 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5416 let Predicates = [HasAVX] in {
5417 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5418 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5419 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5420 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5421 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5422 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5423 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5424 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5427 let Predicates = [UseSSSE3] in {
5428 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5429 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5430 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5431 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5432 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5433 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5434 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5435 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5438 //===---------------------------------------------------------------------===//
5439 // SSSE3 - Thread synchronization
5440 //===---------------------------------------------------------------------===//
5442 let SchedRW = [WriteSystem] in {
5443 let usesCustomInserter = 1 in {
5444 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5445 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5446 Requires<[HasSSE3]>;
5449 let Uses = [EAX, ECX, EDX] in
5450 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5451 TB, Requires<[HasSSE3]>;
5452 let Uses = [ECX, EAX] in
5453 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5454 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5455 TB, Requires<[HasSSE3]>;
5458 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[In32BitMode]>;
5459 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5461 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
5462 Requires<[In32BitMode]>;
5463 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
5464 Requires<[In64BitMode]>;
5466 //===----------------------------------------------------------------------===//
5467 // SSE4.1 - Packed Move with Sign/Zero Extend
5468 //===----------------------------------------------------------------------===//
5470 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5471 OpndItins itins = DEFAULT_ITINS> {
5472 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5473 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5474 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>, OpSize;
5476 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5477 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5479 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))],
5483 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5485 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5486 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5487 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5489 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5490 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5491 [(set VR256:$dst, (IntId (load addr:$src)))]>,
5495 let Predicates = [HasAVX] in {
5496 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw",
5497 int_x86_sse41_pmovsxbw>, VEX;
5498 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd",
5499 int_x86_sse41_pmovsxwd>, VEX;
5500 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq",
5501 int_x86_sse41_pmovsxdq>, VEX;
5502 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw",
5503 int_x86_sse41_pmovzxbw>, VEX;
5504 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd",
5505 int_x86_sse41_pmovzxwd>, VEX;
5506 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq",
5507 int_x86_sse41_pmovzxdq>, VEX;
5510 let Predicates = [HasAVX2] in {
5511 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5512 int_x86_avx2_pmovsxbw>, VEX, VEX_L;
5513 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5514 int_x86_avx2_pmovsxwd>, VEX, VEX_L;
5515 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5516 int_x86_avx2_pmovsxdq>, VEX, VEX_L;
5517 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5518 int_x86_avx2_pmovzxbw>, VEX, VEX_L;
5519 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5520 int_x86_avx2_pmovzxwd>, VEX, VEX_L;
5521 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5522 int_x86_avx2_pmovzxdq>, VEX, VEX_L;
5525 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw, SSE_INTALU_ITINS_P>;
5526 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd, SSE_INTALU_ITINS_P>;
5527 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq, SSE_INTALU_ITINS_P>;
5528 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw, SSE_INTALU_ITINS_P>;
5529 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd, SSE_INTALU_ITINS_P>;
5530 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq, SSE_INTALU_ITINS_P>;
5532 let Predicates = [HasAVX] in {
5533 // Common patterns involving scalar load.
5534 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5535 (VPMOVSXBWrm addr:$src)>;
5536 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5537 (VPMOVSXBWrm addr:$src)>;
5538 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5539 (VPMOVSXBWrm addr:$src)>;
5541 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5542 (VPMOVSXWDrm addr:$src)>;
5543 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5544 (VPMOVSXWDrm addr:$src)>;
5545 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5546 (VPMOVSXWDrm addr:$src)>;
5548 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5549 (VPMOVSXDQrm addr:$src)>;
5550 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5551 (VPMOVSXDQrm addr:$src)>;
5552 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5553 (VPMOVSXDQrm addr:$src)>;
5555 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5556 (VPMOVZXBWrm addr:$src)>;
5557 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5558 (VPMOVZXBWrm addr:$src)>;
5559 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5560 (VPMOVZXBWrm addr:$src)>;
5562 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5563 (VPMOVZXWDrm addr:$src)>;
5564 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5565 (VPMOVZXWDrm addr:$src)>;
5566 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5567 (VPMOVZXWDrm addr:$src)>;
5569 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5570 (VPMOVZXDQrm addr:$src)>;
5571 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5572 (VPMOVZXDQrm addr:$src)>;
5573 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5574 (VPMOVZXDQrm addr:$src)>;
5577 let Predicates = [UseSSE41] in {
5578 // Common patterns involving scalar load.
5579 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5580 (PMOVSXBWrm addr:$src)>;
5581 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5582 (PMOVSXBWrm addr:$src)>;
5583 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5584 (PMOVSXBWrm addr:$src)>;
5586 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5587 (PMOVSXWDrm addr:$src)>;
5588 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5589 (PMOVSXWDrm addr:$src)>;
5590 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5591 (PMOVSXWDrm addr:$src)>;
5593 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5594 (PMOVSXDQrm addr:$src)>;
5595 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5596 (PMOVSXDQrm addr:$src)>;
5597 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5598 (PMOVSXDQrm addr:$src)>;
5600 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5601 (PMOVZXBWrm addr:$src)>;
5602 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5603 (PMOVZXBWrm addr:$src)>;
5604 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5605 (PMOVZXBWrm addr:$src)>;
5607 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5608 (PMOVZXWDrm addr:$src)>;
5609 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5610 (PMOVZXWDrm addr:$src)>;
5611 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5612 (PMOVZXWDrm addr:$src)>;
5614 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5615 (PMOVZXDQrm addr:$src)>;
5616 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5617 (PMOVZXDQrm addr:$src)>;
5618 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5619 (PMOVZXDQrm addr:$src)>;
5622 let Predicates = [HasAVX2] in {
5623 let AddedComplexity = 15 in {
5624 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5625 (VPMOVZXDQYrr VR128:$src)>;
5626 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5627 (VPMOVZXWDYrr VR128:$src)>;
5630 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5631 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5634 let Predicates = [HasAVX] in {
5635 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5636 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5639 let Predicates = [UseSSE41] in {
5640 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5641 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5645 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5646 OpndItins itins = DEFAULT_ITINS> {
5647 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5648 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5649 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>, OpSize;
5651 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5652 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5654 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))],
5659 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5661 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5662 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5663 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5665 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5666 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5668 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5672 let Predicates = [HasAVX] in {
5673 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5675 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5677 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5679 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5683 let Predicates = [HasAVX2] in {
5684 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5685 int_x86_avx2_pmovsxbd>, VEX, VEX_L;
5686 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5687 int_x86_avx2_pmovsxwq>, VEX, VEX_L;
5688 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5689 int_x86_avx2_pmovzxbd>, VEX, VEX_L;
5690 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5691 int_x86_avx2_pmovzxwq>, VEX, VEX_L;
5694 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd,
5695 SSE_INTALU_ITINS_P>;
5696 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq,
5697 SSE_INTALU_ITINS_P>;
5698 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd,
5699 SSE_INTALU_ITINS_P>;
5700 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq,
5701 SSE_INTALU_ITINS_P>;
5703 let Predicates = [HasAVX] in {
5704 // Common patterns involving scalar load
5705 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5706 (VPMOVSXBDrm addr:$src)>;
5707 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5708 (VPMOVSXWQrm addr:$src)>;
5710 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5711 (VPMOVZXBDrm addr:$src)>;
5712 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5713 (VPMOVZXWQrm addr:$src)>;
5716 let Predicates = [UseSSE41] in {
5717 // Common patterns involving scalar load
5718 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5719 (PMOVSXBDrm addr:$src)>;
5720 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5721 (PMOVSXWQrm addr:$src)>;
5723 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5724 (PMOVZXBDrm addr:$src)>;
5725 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5726 (PMOVZXWQrm addr:$src)>;
5729 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5730 OpndItins itins = DEFAULT_ITINS> {
5731 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5732 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5733 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5735 // Expecting a i16 load any extended to i32 value.
5736 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5737 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5738 [(set VR128:$dst, (IntId (bitconvert
5739 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5743 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5745 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5746 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5747 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5749 // Expecting a i16 load any extended to i32 value.
5750 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5751 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5752 [(set VR256:$dst, (IntId (bitconvert
5753 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5757 let Predicates = [HasAVX] in {
5758 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5760 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5763 let Predicates = [HasAVX2] in {
5764 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5765 int_x86_avx2_pmovsxbq>, VEX, VEX_L;
5766 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5767 int_x86_avx2_pmovzxbq>, VEX, VEX_L;
5769 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq,
5770 SSE_INTALU_ITINS_P>;
5771 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq,
5772 SSE_INTALU_ITINS_P>;
5774 let Predicates = [HasAVX2] in {
5775 def : Pat<(v16i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWYrr VR128:$src)>;
5776 def : Pat<(v8i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDYrr VR128:$src)>;
5777 def : Pat<(v4i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQYrr VR128:$src)>;
5779 def : Pat<(v8i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5780 def : Pat<(v4i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQYrr VR128:$src)>;
5782 def : Pat<(v4i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5784 def : Pat<(v16i16 (X86vsext (v32i8 VR256:$src))),
5785 (VPMOVSXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5786 def : Pat<(v8i32 (X86vsext (v32i8 VR256:$src))),
5787 (VPMOVSXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5788 def : Pat<(v4i64 (X86vsext (v32i8 VR256:$src))),
5789 (VPMOVSXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5791 def : Pat<(v8i32 (X86vsext (v16i16 VR256:$src))),
5792 (VPMOVSXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5793 def : Pat<(v4i64 (X86vsext (v16i16 VR256:$src))),
5794 (VPMOVSXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5796 def : Pat<(v4i64 (X86vsext (v8i32 VR256:$src))),
5797 (VPMOVSXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5799 def : Pat<(v8i32 (X86vsmovl (v8i16 (bitconvert (v2i64 (load addr:$src)))))),
5800 (VPMOVSXWDYrm addr:$src)>;
5801 def : Pat<(v4i64 (X86vsmovl (v4i32 (bitconvert (v2i64 (load addr:$src)))))),
5802 (VPMOVSXDQYrm addr:$src)>;
5804 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2i64
5805 (scalar_to_vector (loadi64 addr:$src))))))),
5806 (VPMOVSXBDYrm addr:$src)>;
5807 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2f64
5808 (scalar_to_vector (loadf64 addr:$src))))))),
5809 (VPMOVSXBDYrm addr:$src)>;
5811 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2i64
5812 (scalar_to_vector (loadi64 addr:$src))))))),
5813 (VPMOVSXWQYrm addr:$src)>;
5814 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2f64
5815 (scalar_to_vector (loadf64 addr:$src))))))),
5816 (VPMOVSXWQYrm addr:$src)>;
5818 def : Pat<(v4i64 (X86vsext (v16i8 (bitconvert (v4i32
5819 (scalar_to_vector (loadi32 addr:$src))))))),
5820 (VPMOVSXBQYrm addr:$src)>;
5823 let Predicates = [HasAVX] in {
5824 // Common patterns involving scalar load
5825 def : Pat<(int_x86_sse41_pmovsxbq
5826 (bitconvert (v4i32 (X86vzmovl
5827 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5828 (VPMOVSXBQrm addr:$src)>;
5830 def : Pat<(int_x86_sse41_pmovzxbq
5831 (bitconvert (v4i32 (X86vzmovl
5832 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5833 (VPMOVZXBQrm addr:$src)>;
5836 let Predicates = [UseSSE41] in {
5837 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (PMOVSXBWrr VR128:$src)>;
5838 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (PMOVSXBDrr VR128:$src)>;
5839 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (PMOVSXBQrr VR128:$src)>;
5841 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5842 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (PMOVSXWQrr VR128:$src)>;
5844 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5846 // Common patterns involving scalar load
5847 def : Pat<(int_x86_sse41_pmovsxbq
5848 (bitconvert (v4i32 (X86vzmovl
5849 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5850 (PMOVSXBQrm addr:$src)>;
5852 def : Pat<(int_x86_sse41_pmovzxbq
5853 (bitconvert (v4i32 (X86vzmovl
5854 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5855 (PMOVZXBQrm addr:$src)>;
5857 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
5858 (scalar_to_vector (loadi64 addr:$src))))))),
5859 (PMOVSXWDrm addr:$src)>;
5860 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
5861 (scalar_to_vector (loadf64 addr:$src))))))),
5862 (PMOVSXWDrm addr:$src)>;
5863 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
5864 (scalar_to_vector (loadi32 addr:$src))))))),
5865 (PMOVSXBDrm addr:$src)>;
5866 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
5867 (scalar_to_vector (loadi32 addr:$src))))))),
5868 (PMOVSXWQrm addr:$src)>;
5869 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
5870 (scalar_to_vector (extloadi32i16 addr:$src))))))),
5871 (PMOVSXBQrm addr:$src)>;
5872 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
5873 (scalar_to_vector (loadi64 addr:$src))))))),
5874 (PMOVSXDQrm addr:$src)>;
5875 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
5876 (scalar_to_vector (loadf64 addr:$src))))))),
5877 (PMOVSXDQrm addr:$src)>;
5878 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
5879 (scalar_to_vector (loadi64 addr:$src))))))),
5880 (PMOVSXBWrm addr:$src)>;
5881 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
5882 (scalar_to_vector (loadf64 addr:$src))))))),
5883 (PMOVSXBWrm addr:$src)>;
5886 let Predicates = [HasAVX2] in {
5887 def : Pat<(v16i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWYrr VR128:$src)>;
5888 def : Pat<(v8i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDYrr VR128:$src)>;
5889 def : Pat<(v4i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQYrr VR128:$src)>;
5891 def : Pat<(v8i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDYrr VR128:$src)>;
5892 def : Pat<(v4i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQYrr VR128:$src)>;
5894 def : Pat<(v4i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQYrr VR128:$src)>;
5896 def : Pat<(v16i16 (X86vzext (v32i8 VR256:$src))),
5897 (VPMOVZXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5898 def : Pat<(v8i32 (X86vzext (v32i8 VR256:$src))),
5899 (VPMOVZXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5900 def : Pat<(v4i64 (X86vzext (v32i8 VR256:$src))),
5901 (VPMOVZXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5903 def : Pat<(v8i32 (X86vzext (v16i16 VR256:$src))),
5904 (VPMOVZXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5905 def : Pat<(v4i64 (X86vzext (v16i16 VR256:$src))),
5906 (VPMOVZXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5908 def : Pat<(v4i64 (X86vzext (v8i32 VR256:$src))),
5909 (VPMOVZXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5912 let Predicates = [HasAVX] in {
5913 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWrr VR128:$src)>;
5914 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDrr VR128:$src)>;
5915 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQrr VR128:$src)>;
5917 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDrr VR128:$src)>;
5918 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQrr VR128:$src)>;
5920 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQrr VR128:$src)>;
5922 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5923 (VPMOVZXBWrm addr:$src)>;
5924 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5925 (VPMOVZXBWrm addr:$src)>;
5926 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5927 (VPMOVZXBDrm addr:$src)>;
5928 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
5929 (VPMOVZXBQrm addr:$src)>;
5931 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5932 (VPMOVZXWDrm addr:$src)>;
5933 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5934 (VPMOVZXWDrm addr:$src)>;
5935 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5936 (VPMOVZXWQrm addr:$src)>;
5938 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5939 (VPMOVZXDQrm addr:$src)>;
5940 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5941 (VPMOVZXDQrm addr:$src)>;
5942 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
5943 (VPMOVZXDQrm addr:$src)>;
5945 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWrr VR128:$src)>;
5946 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDrr VR128:$src)>;
5947 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQrr VR128:$src)>;
5949 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5950 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQrr VR128:$src)>;
5952 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5954 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
5955 (scalar_to_vector (loadi64 addr:$src))))))),
5956 (VPMOVSXWDrm addr:$src)>;
5957 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
5958 (scalar_to_vector (loadi64 addr:$src))))))),
5959 (VPMOVSXDQrm addr:$src)>;
5960 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
5961 (scalar_to_vector (loadf64 addr:$src))))))),
5962 (VPMOVSXWDrm addr:$src)>;
5963 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
5964 (scalar_to_vector (loadf64 addr:$src))))))),
5965 (VPMOVSXDQrm addr:$src)>;
5966 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
5967 (scalar_to_vector (loadi64 addr:$src))))))),
5968 (VPMOVSXBWrm addr:$src)>;
5969 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
5970 (scalar_to_vector (loadf64 addr:$src))))))),
5971 (VPMOVSXBWrm addr:$src)>;
5973 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
5974 (scalar_to_vector (loadi32 addr:$src))))))),
5975 (VPMOVSXBDrm addr:$src)>;
5976 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
5977 (scalar_to_vector (loadi32 addr:$src))))))),
5978 (VPMOVSXWQrm addr:$src)>;
5979 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
5980 (scalar_to_vector (extloadi32i16 addr:$src))))))),
5981 (VPMOVSXBQrm addr:$src)>;
5984 let Predicates = [UseSSE41] in {
5985 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (PMOVZXBWrr VR128:$src)>;
5986 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (PMOVZXBDrr VR128:$src)>;
5987 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (PMOVZXBQrr VR128:$src)>;
5989 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (PMOVZXWDrr VR128:$src)>;
5990 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (PMOVZXWQrr VR128:$src)>;
5992 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (PMOVZXDQrr VR128:$src)>;
5994 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5995 (PMOVZXBWrm addr:$src)>;
5996 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5997 (PMOVZXBWrm addr:$src)>;
5998 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5999 (PMOVZXBDrm addr:$src)>;
6000 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
6001 (PMOVZXBQrm addr:$src)>;
6003 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6004 (PMOVZXWDrm addr:$src)>;
6005 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6006 (PMOVZXWDrm addr:$src)>;
6007 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6008 (PMOVZXWQrm addr:$src)>;
6010 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6011 (PMOVZXDQrm addr:$src)>;
6012 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6013 (PMOVZXDQrm addr:$src)>;
6014 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
6015 (PMOVZXDQrm addr:$src)>;
6018 //===----------------------------------------------------------------------===//
6019 // SSE4.1 - Extract Instructions
6020 //===----------------------------------------------------------------------===//
6022 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6023 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6024 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6025 (ins VR128:$src1, i32i8imm:$src2),
6026 !strconcat(OpcodeStr,
6027 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6028 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
6030 let neverHasSideEffects = 1, mayStore = 1 in
6031 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6032 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
6033 !strconcat(OpcodeStr,
6034 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6037 // There's an AssertZext in the way of writing the store pattern
6038 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
6041 let Predicates = [HasAVX] in {
6042 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6043 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
6044 (ins VR128:$src1, i32i8imm:$src2),
6045 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
6048 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6051 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6052 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6053 let neverHasSideEffects = 1, mayStore = 1 in
6054 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6055 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
6056 !strconcat(OpcodeStr,
6057 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6060 // There's an AssertZext in the way of writing the store pattern
6061 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
6064 let Predicates = [HasAVX] in
6065 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6067 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6070 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6071 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6072 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6073 (ins VR128:$src1, i32i8imm:$src2),
6074 !strconcat(OpcodeStr,
6075 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6077 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
6078 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6079 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
6080 !strconcat(OpcodeStr,
6081 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6082 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6083 addr:$dst)]>, OpSize;
6086 let Predicates = [HasAVX] in
6087 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6089 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6091 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6092 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6093 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6094 (ins VR128:$src1, i32i8imm:$src2),
6095 !strconcat(OpcodeStr,
6096 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6098 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
6099 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6100 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
6101 !strconcat(OpcodeStr,
6102 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6103 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6104 addr:$dst)]>, OpSize, REX_W;
6107 let Predicates = [HasAVX] in
6108 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6110 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6112 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6114 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6115 OpndItins itins = DEFAULT_ITINS> {
6116 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6117 (ins VR128:$src1, i32i8imm:$src2),
6118 !strconcat(OpcodeStr,
6119 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6121 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6124 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6125 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
6126 !strconcat(OpcodeStr,
6127 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6128 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6129 addr:$dst)], itins.rm>, OpSize;
6132 let ExeDomain = SSEPackedSingle in {
6133 let Predicates = [UseAVX] in {
6134 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6135 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
6136 (ins VR128:$src1, i32i8imm:$src2),
6137 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6140 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6143 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6144 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6147 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6149 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6152 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6153 Requires<[UseSSE41]>;
6155 //===----------------------------------------------------------------------===//
6156 // SSE4.1 - Insert Instructions
6157 //===----------------------------------------------------------------------===//
6159 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6160 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6161 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6163 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6165 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6167 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
6168 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6169 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6171 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6173 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6175 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6176 imm:$src3))]>, OpSize;
6179 let Predicates = [HasAVX] in
6180 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6181 let Constraints = "$src1 = $dst" in
6182 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6184 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6185 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6186 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6188 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6190 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6192 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6194 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6195 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6197 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6199 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6201 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6202 imm:$src3)))]>, OpSize;
6205 let Predicates = [HasAVX] in
6206 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6207 let Constraints = "$src1 = $dst" in
6208 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6210 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6211 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6212 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6214 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6216 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6218 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6220 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6221 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6223 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6225 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6227 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6228 imm:$src3)))]>, OpSize;
6231 let Predicates = [HasAVX] in
6232 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6233 let Constraints = "$src1 = $dst" in
6234 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6236 // insertps has a few different modes, there's the first two here below which
6237 // are optimized inserts that won't zero arbitrary elements in the destination
6238 // vector. The next one matches the intrinsic and could zero arbitrary elements
6239 // in the target vector.
6240 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6241 OpndItins itins = DEFAULT_ITINS> {
6242 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6243 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6245 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6247 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6249 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6251 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6252 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6254 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6256 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6258 (X86insrtps VR128:$src1,
6259 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6260 imm:$src3))], itins.rm>, OpSize;
6263 let ExeDomain = SSEPackedSingle in {
6264 let Predicates = [UseAVX] in
6265 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6266 let Constraints = "$src1 = $dst" in
6267 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6270 //===----------------------------------------------------------------------===//
6271 // SSE4.1 - Round Instructions
6272 //===----------------------------------------------------------------------===//
6274 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6275 X86MemOperand x86memop, RegisterClass RC,
6276 PatFrag mem_frag32, PatFrag mem_frag64,
6277 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6278 let ExeDomain = SSEPackedSingle in {
6279 // Intrinsic operation, reg.
6280 // Vector intrinsic operation, reg
6281 def PSr : SS4AIi8<opcps, MRMSrcReg,
6282 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6283 !strconcat(OpcodeStr,
6284 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6285 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6286 IIC_SSE_ROUNDPS_REG>,
6289 // Vector intrinsic operation, mem
6290 def PSm : SS4AIi8<opcps, MRMSrcMem,
6291 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6292 !strconcat(OpcodeStr,
6293 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6295 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6296 IIC_SSE_ROUNDPS_MEM>,
6298 } // ExeDomain = SSEPackedSingle
6300 let ExeDomain = SSEPackedDouble in {
6301 // Vector intrinsic operation, reg
6302 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6303 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6304 !strconcat(OpcodeStr,
6305 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6306 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6307 IIC_SSE_ROUNDPS_REG>,
6310 // Vector intrinsic operation, mem
6311 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6312 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6313 !strconcat(OpcodeStr,
6314 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6316 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6317 IIC_SSE_ROUNDPS_REG>,
6319 } // ExeDomain = SSEPackedDouble
6322 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6325 Intrinsic F64Int, bit Is2Addr = 1> {
6326 let ExeDomain = GenericDomain in {
6328 let hasSideEffects = 0 in
6329 def SSr : SS4AIi8<opcss, MRMSrcReg,
6330 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6332 !strconcat(OpcodeStr,
6333 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6334 !strconcat(OpcodeStr,
6335 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6338 // Intrinsic operation, reg.
6339 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6340 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6342 !strconcat(OpcodeStr,
6343 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6344 !strconcat(OpcodeStr,
6345 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6346 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6349 // Intrinsic operation, mem.
6350 def SSm : SS4AIi8<opcss, MRMSrcMem,
6351 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6353 !strconcat(OpcodeStr,
6354 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6355 !strconcat(OpcodeStr,
6356 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6358 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6362 let hasSideEffects = 0 in
6363 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6364 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6366 !strconcat(OpcodeStr,
6367 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6368 !strconcat(OpcodeStr,
6369 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6372 // Intrinsic operation, reg.
6373 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6374 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6376 !strconcat(OpcodeStr,
6377 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6378 !strconcat(OpcodeStr,
6379 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6380 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6383 // Intrinsic operation, mem.
6384 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6385 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6387 !strconcat(OpcodeStr,
6388 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6389 !strconcat(OpcodeStr,
6390 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6392 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6394 } // ExeDomain = GenericDomain
6397 // FP round - roundss, roundps, roundsd, roundpd
6398 let Predicates = [HasAVX] in {
6400 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6401 memopv4f32, memopv2f64,
6402 int_x86_sse41_round_ps,
6403 int_x86_sse41_round_pd>, VEX;
6404 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6405 memopv8f32, memopv4f64,
6406 int_x86_avx_round_ps_256,
6407 int_x86_avx_round_pd_256>, VEX, VEX_L;
6408 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6409 int_x86_sse41_round_ss,
6410 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6412 def : Pat<(ffloor FR32:$src),
6413 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6414 def : Pat<(f64 (ffloor FR64:$src)),
6415 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6416 def : Pat<(f32 (fnearbyint FR32:$src)),
6417 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6418 def : Pat<(f64 (fnearbyint FR64:$src)),
6419 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6420 def : Pat<(f32 (fceil FR32:$src)),
6421 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6422 def : Pat<(f64 (fceil FR64:$src)),
6423 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6424 def : Pat<(f32 (frint FR32:$src)),
6425 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6426 def : Pat<(f64 (frint FR64:$src)),
6427 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6428 def : Pat<(f32 (ftrunc FR32:$src)),
6429 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6430 def : Pat<(f64 (ftrunc FR64:$src)),
6431 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6433 def : Pat<(v4f32 (ffloor VR128:$src)),
6434 (VROUNDPSr VR128:$src, (i32 0x1))>;
6435 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6436 (VROUNDPSr VR128:$src, (i32 0xC))>;
6437 def : Pat<(v4f32 (fceil VR128:$src)),
6438 (VROUNDPSr VR128:$src, (i32 0x2))>;
6439 def : Pat<(v4f32 (frint VR128:$src)),
6440 (VROUNDPSr VR128:$src, (i32 0x4))>;
6441 def : Pat<(v4f32 (ftrunc VR128:$src)),
6442 (VROUNDPSr VR128:$src, (i32 0x3))>;
6444 def : Pat<(v2f64 (ffloor VR128:$src)),
6445 (VROUNDPDr VR128:$src, (i32 0x1))>;
6446 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6447 (VROUNDPDr VR128:$src, (i32 0xC))>;
6448 def : Pat<(v2f64 (fceil VR128:$src)),
6449 (VROUNDPDr VR128:$src, (i32 0x2))>;
6450 def : Pat<(v2f64 (frint VR128:$src)),
6451 (VROUNDPDr VR128:$src, (i32 0x4))>;
6452 def : Pat<(v2f64 (ftrunc VR128:$src)),
6453 (VROUNDPDr VR128:$src, (i32 0x3))>;
6455 def : Pat<(v8f32 (ffloor VR256:$src)),
6456 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6457 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6458 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6459 def : Pat<(v8f32 (fceil VR256:$src)),
6460 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6461 def : Pat<(v8f32 (frint VR256:$src)),
6462 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6463 def : Pat<(v8f32 (ftrunc VR256:$src)),
6464 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6466 def : Pat<(v4f64 (ffloor VR256:$src)),
6467 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6468 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6469 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6470 def : Pat<(v4f64 (fceil VR256:$src)),
6471 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6472 def : Pat<(v4f64 (frint VR256:$src)),
6473 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6474 def : Pat<(v4f64 (ftrunc VR256:$src)),
6475 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6478 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6479 memopv4f32, memopv2f64,
6480 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6481 let Constraints = "$src1 = $dst" in
6482 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6483 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6485 let Predicates = [UseSSE41] in {
6486 def : Pat<(ffloor FR32:$src),
6487 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6488 def : Pat<(f64 (ffloor FR64:$src)),
6489 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6490 def : Pat<(f32 (fnearbyint FR32:$src)),
6491 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6492 def : Pat<(f64 (fnearbyint FR64:$src)),
6493 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6494 def : Pat<(f32 (fceil FR32:$src)),
6495 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6496 def : Pat<(f64 (fceil FR64:$src)),
6497 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6498 def : Pat<(f32 (frint FR32:$src)),
6499 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6500 def : Pat<(f64 (frint FR64:$src)),
6501 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6502 def : Pat<(f32 (ftrunc FR32:$src)),
6503 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6504 def : Pat<(f64 (ftrunc FR64:$src)),
6505 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6507 def : Pat<(v4f32 (ffloor VR128:$src)),
6508 (ROUNDPSr VR128:$src, (i32 0x1))>;
6509 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6510 (ROUNDPSr VR128:$src, (i32 0xC))>;
6511 def : Pat<(v4f32 (fceil VR128:$src)),
6512 (ROUNDPSr VR128:$src, (i32 0x2))>;
6513 def : Pat<(v4f32 (frint VR128:$src)),
6514 (ROUNDPSr VR128:$src, (i32 0x4))>;
6515 def : Pat<(v4f32 (ftrunc VR128:$src)),
6516 (ROUNDPSr VR128:$src, (i32 0x3))>;
6518 def : Pat<(v2f64 (ffloor VR128:$src)),
6519 (ROUNDPDr VR128:$src, (i32 0x1))>;
6520 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6521 (ROUNDPDr VR128:$src, (i32 0xC))>;
6522 def : Pat<(v2f64 (fceil VR128:$src)),
6523 (ROUNDPDr VR128:$src, (i32 0x2))>;
6524 def : Pat<(v2f64 (frint VR128:$src)),
6525 (ROUNDPDr VR128:$src, (i32 0x4))>;
6526 def : Pat<(v2f64 (ftrunc VR128:$src)),
6527 (ROUNDPDr VR128:$src, (i32 0x3))>;
6530 //===----------------------------------------------------------------------===//
6531 // SSE4.1 - Packed Bit Test
6532 //===----------------------------------------------------------------------===//
6534 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6535 // the intel intrinsic that corresponds to this.
6536 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6537 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6538 "vptest\t{$src2, $src1|$src1, $src2}",
6539 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6541 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6542 "vptest\t{$src2, $src1|$src1, $src2}",
6543 [(set EFLAGS,(X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6546 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6547 "vptest\t{$src2, $src1|$src1, $src2}",
6548 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6550 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6551 "vptest\t{$src2, $src1|$src1, $src2}",
6552 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6556 let Defs = [EFLAGS] in {
6557 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6558 "ptest\t{$src2, $src1|$src1, $src2}",
6559 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6561 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6562 "ptest\t{$src2, $src1|$src1, $src2}",
6563 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6567 // The bit test instructions below are AVX only
6568 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6569 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6570 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6571 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6572 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6573 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6574 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6575 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6579 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6580 let ExeDomain = SSEPackedSingle in {
6581 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6582 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>,
6585 let ExeDomain = SSEPackedDouble in {
6586 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6587 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>,
6592 //===----------------------------------------------------------------------===//
6593 // SSE4.1 - Misc Instructions
6594 //===----------------------------------------------------------------------===//
6596 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6597 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6598 "popcnt{w}\t{$src, $dst|$dst, $src}",
6599 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6602 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6603 "popcnt{w}\t{$src, $dst|$dst, $src}",
6604 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6605 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, OpSize, XS;
6607 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6608 "popcnt{l}\t{$src, $dst|$dst, $src}",
6609 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6612 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6613 "popcnt{l}\t{$src, $dst|$dst, $src}",
6614 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6615 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, XS;
6617 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6618 "popcnt{q}\t{$src, $dst|$dst, $src}",
6619 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
6622 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6623 "popcnt{q}\t{$src, $dst|$dst, $src}",
6624 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6625 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, XS;
6630 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6631 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6632 Intrinsic IntId128> {
6633 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6635 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6636 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6637 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6639 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6642 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6645 let Predicates = [HasAVX] in
6646 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6647 int_x86_sse41_phminposuw>, VEX;
6648 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6649 int_x86_sse41_phminposuw>;
6651 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6652 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6653 Intrinsic IntId128, bit Is2Addr = 1,
6654 OpndItins itins = DEFAULT_ITINS> {
6655 let isCommutable = 1 in
6656 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6657 (ins VR128:$src1, VR128:$src2),
6659 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6660 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6661 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))],
6663 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6664 (ins VR128:$src1, i128mem:$src2),
6666 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6667 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6669 (IntId128 VR128:$src1,
6670 (bitconvert (memopv2i64 addr:$src2))))],
6674 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
6675 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6676 Intrinsic IntId256> {
6677 let isCommutable = 1 in
6678 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6679 (ins VR256:$src1, VR256:$src2),
6680 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6681 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6682 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6683 (ins VR256:$src1, i256mem:$src2),
6684 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6686 (IntId256 VR256:$src1,
6687 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6691 /// SS48I_binop_rm - Simple SSE41 binary operator.
6692 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6693 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6694 X86MemOperand x86memop, bit Is2Addr = 1,
6695 OpndItins itins = DEFAULT_ITINS> {
6696 let isCommutable = 1 in
6697 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6698 (ins RC:$src1, RC:$src2),
6700 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6701 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6702 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6703 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6704 (ins RC:$src1, x86memop:$src2),
6706 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6707 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6709 (OpVT (OpNode RC:$src1,
6710 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6713 let Predicates = [HasAVX] in {
6714 let isCommutable = 0 in
6715 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6717 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
6718 memopv2i64, i128mem, 0>, VEX_4V;
6719 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
6720 memopv2i64, i128mem, 0>, VEX_4V;
6721 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
6722 memopv2i64, i128mem, 0>, VEX_4V;
6723 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
6724 memopv2i64, i128mem, 0>, VEX_4V;
6725 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
6726 memopv2i64, i128mem, 0>, VEX_4V;
6727 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
6728 memopv2i64, i128mem, 0>, VEX_4V;
6729 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
6730 memopv2i64, i128mem, 0>, VEX_4V;
6731 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
6732 memopv2i64, i128mem, 0>, VEX_4V;
6733 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6737 let Predicates = [HasAVX2] in {
6738 let isCommutable = 0 in
6739 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6740 int_x86_avx2_packusdw>, VEX_4V, VEX_L;
6741 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
6742 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6743 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
6744 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6745 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
6746 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6747 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
6748 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6749 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
6750 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6751 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
6752 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6753 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
6754 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6755 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
6756 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6757 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6758 int_x86_avx2_pmul_dq>, VEX_4V, VEX_L;
6761 let Constraints = "$src1 = $dst" in {
6762 let isCommutable = 0 in
6763 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6764 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
6765 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6766 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
6767 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6768 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
6769 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6770 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
6771 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6772 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
6773 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6774 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
6775 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6776 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
6777 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6778 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
6779 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6780 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq,
6781 1, SSE_INTMUL_ITINS_P>;
6784 let Predicates = [HasAVX] in {
6785 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6786 memopv2i64, i128mem, 0>, VEX_4V;
6787 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6788 memopv2i64, i128mem, 0>, VEX_4V;
6790 let Predicates = [HasAVX2] in {
6791 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6792 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6793 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6794 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6797 let Constraints = "$src1 = $dst" in {
6798 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6799 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
6800 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6801 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
6804 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6805 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6806 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6807 X86MemOperand x86memop, bit Is2Addr = 1,
6808 OpndItins itins = DEFAULT_ITINS> {
6809 let isCommutable = 1 in
6810 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6811 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6813 !strconcat(OpcodeStr,
6814 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6815 !strconcat(OpcodeStr,
6816 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6817 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
6819 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6820 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6822 !strconcat(OpcodeStr,
6823 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6824 !strconcat(OpcodeStr,
6825 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6828 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
6832 let Predicates = [HasAVX] in {
6833 let isCommutable = 0 in {
6834 let ExeDomain = SSEPackedSingle in {
6835 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6836 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6837 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6838 int_x86_avx_blend_ps_256, VR256, memopv8f32,
6839 f256mem, 0>, VEX_4V, VEX_L;
6841 let ExeDomain = SSEPackedDouble in {
6842 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6843 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6844 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6845 int_x86_avx_blend_pd_256,VR256, memopv4f64,
6846 f256mem, 0>, VEX_4V, VEX_L;
6848 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6849 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6850 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6851 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6853 let ExeDomain = SSEPackedSingle in
6854 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6855 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6856 let ExeDomain = SSEPackedDouble in
6857 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6858 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6859 let ExeDomain = SSEPackedSingle in
6860 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6861 VR256, memopv8f32, i256mem, 0>, VEX_4V, VEX_L;
6864 let Predicates = [HasAVX2] in {
6865 let isCommutable = 0 in {
6866 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6867 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6868 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6869 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6873 let Constraints = "$src1 = $dst" in {
6874 let isCommutable = 0 in {
6875 let ExeDomain = SSEPackedSingle in
6876 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6877 VR128, memopv4f32, f128mem,
6878 1, SSE_INTALU_ITINS_P>;
6879 let ExeDomain = SSEPackedDouble in
6880 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6881 VR128, memopv2f64, f128mem,
6882 1, SSE_INTALU_ITINS_P>;
6883 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6884 VR128, memopv2i64, i128mem,
6885 1, SSE_INTALU_ITINS_P>;
6886 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6887 VR128, memopv2i64, i128mem,
6888 1, SSE_INTMUL_ITINS_P>;
6890 let ExeDomain = SSEPackedSingle in
6891 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6892 VR128, memopv4f32, f128mem, 1,
6894 let ExeDomain = SSEPackedDouble in
6895 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6896 VR128, memopv2f64, f128mem, 1,
6900 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6901 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6902 RegisterClass RC, X86MemOperand x86memop,
6903 PatFrag mem_frag, Intrinsic IntId> {
6904 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6905 (ins RC:$src1, RC:$src2, RC:$src3),
6906 !strconcat(OpcodeStr,
6907 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6908 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6909 NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6911 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6912 (ins RC:$src1, x86memop:$src2, RC:$src3),
6913 !strconcat(OpcodeStr,
6914 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6916 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6918 NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6921 let Predicates = [HasAVX] in {
6922 let ExeDomain = SSEPackedDouble in {
6923 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
6924 memopv2f64, int_x86_sse41_blendvpd>;
6925 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
6926 memopv4f64, int_x86_avx_blendv_pd_256>, VEX_L;
6927 } // ExeDomain = SSEPackedDouble
6928 let ExeDomain = SSEPackedSingle in {
6929 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
6930 memopv4f32, int_x86_sse41_blendvps>;
6931 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
6932 memopv8f32, int_x86_avx_blendv_ps_256>, VEX_L;
6933 } // ExeDomain = SSEPackedSingle
6934 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6935 memopv2i64, int_x86_sse41_pblendvb>;
6938 let Predicates = [HasAVX2] in {
6939 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6940 memopv4i64, int_x86_avx2_pblendvb>, VEX_L;
6943 let Predicates = [HasAVX] in {
6944 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6945 (v16i8 VR128:$src2))),
6946 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6947 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6948 (v4i32 VR128:$src2))),
6949 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6950 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6951 (v4f32 VR128:$src2))),
6952 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6953 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6954 (v2i64 VR128:$src2))),
6955 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6956 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6957 (v2f64 VR128:$src2))),
6958 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6959 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6960 (v8i32 VR256:$src2))),
6961 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6962 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6963 (v8f32 VR256:$src2))),
6964 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6965 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6966 (v4i64 VR256:$src2))),
6967 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6968 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6969 (v4f64 VR256:$src2))),
6970 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6972 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6974 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6975 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6977 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6979 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6981 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
6982 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6984 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
6985 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6987 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
6990 let Predicates = [HasAVX2] in {
6991 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6992 (v32i8 VR256:$src2))),
6993 (VPBLENDVBYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
6994 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6996 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6999 /// SS41I_ternary_int - SSE 4.1 ternary operator
7000 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7001 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7002 X86MemOperand x86memop, Intrinsic IntId,
7003 OpndItins itins = DEFAULT_ITINS> {
7004 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7005 (ins VR128:$src1, VR128:$src2),
7006 !strconcat(OpcodeStr,
7007 "\t{$src2, $dst|$dst, $src2}"),
7008 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7011 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7012 (ins VR128:$src1, x86memop:$src2),
7013 !strconcat(OpcodeStr,
7014 "\t{$src2, $dst|$dst, $src2}"),
7017 (bitconvert (mem_frag addr:$src2)), XMM0))],
7022 let ExeDomain = SSEPackedDouble in
7023 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7024 int_x86_sse41_blendvpd>;
7025 let ExeDomain = SSEPackedSingle in
7026 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7027 int_x86_sse41_blendvps>;
7028 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7029 int_x86_sse41_pblendvb>;
7031 // Aliases with the implicit xmm0 argument
7032 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7033 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7034 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7035 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7036 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7037 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7038 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7039 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7040 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7041 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7042 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7043 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7045 let Predicates = [UseSSE41] in {
7046 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7047 (v16i8 VR128:$src2))),
7048 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7049 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7050 (v4i32 VR128:$src2))),
7051 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7052 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7053 (v4f32 VR128:$src2))),
7054 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7055 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7056 (v2i64 VR128:$src2))),
7057 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7058 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7059 (v2f64 VR128:$src2))),
7060 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7062 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7064 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7065 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7067 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7068 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7070 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7074 let Predicates = [HasAVX] in
7075 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7076 "vmovntdqa\t{$src, $dst|$dst, $src}",
7077 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7079 let Predicates = [HasAVX2] in
7080 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7081 "vmovntdqa\t{$src, $dst|$dst, $src}",
7082 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7084 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7085 "movntdqa\t{$src, $dst|$dst, $src}",
7086 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7089 //===----------------------------------------------------------------------===//
7090 // SSE4.2 - Compare Instructions
7091 //===----------------------------------------------------------------------===//
7093 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7094 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7095 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7096 X86MemOperand x86memop, bit Is2Addr = 1> {
7097 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7098 (ins RC:$src1, RC:$src2),
7100 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7101 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7102 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
7104 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7105 (ins RC:$src1, x86memop:$src2),
7107 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7108 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7110 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
7113 let Predicates = [HasAVX] in
7114 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7115 memopv2i64, i128mem, 0>, VEX_4V;
7117 let Predicates = [HasAVX2] in
7118 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7119 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
7121 let Constraints = "$src1 = $dst" in
7122 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7123 memopv2i64, i128mem>;
7125 //===----------------------------------------------------------------------===//
7126 // SSE4.2 - String/text Processing Instructions
7127 //===----------------------------------------------------------------------===//
7129 // Packed Compare Implicit Length Strings, Return Mask
7130 multiclass pseudo_pcmpistrm<string asm> {
7131 def REG : PseudoI<(outs VR128:$dst),
7132 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7133 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7135 def MEM : PseudoI<(outs VR128:$dst),
7136 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7137 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7138 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7141 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7142 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
7143 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
7146 multiclass pcmpistrm_SS42AI<string asm> {
7147 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7148 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7149 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7152 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7153 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7154 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7158 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
7159 let Predicates = [HasAVX] in
7160 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7161 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7164 // Packed Compare Explicit Length Strings, Return Mask
7165 multiclass pseudo_pcmpestrm<string asm> {
7166 def REG : PseudoI<(outs VR128:$dst),
7167 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7168 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7169 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7170 def MEM : PseudoI<(outs VR128:$dst),
7171 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7172 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7173 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
7176 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7177 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
7178 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
7181 multiclass SS42AI_pcmpestrm<string asm> {
7182 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7183 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7184 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7187 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7188 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7189 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7193 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7194 let Predicates = [HasAVX] in
7195 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7196 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7199 // Packed Compare Implicit Length Strings, Return Index
7200 multiclass pseudo_pcmpistri<string asm> {
7201 def REG : PseudoI<(outs GR32:$dst),
7202 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7203 [(set GR32:$dst, EFLAGS,
7204 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7205 def MEM : PseudoI<(outs GR32:$dst),
7206 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7207 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7208 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7211 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7212 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
7213 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
7216 multiclass SS42AI_pcmpistri<string asm> {
7217 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7218 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7219 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7222 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7223 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7224 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7228 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
7229 let Predicates = [HasAVX] in
7230 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7231 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7234 // Packed Compare Explicit Length Strings, Return Index
7235 multiclass pseudo_pcmpestri<string asm> {
7236 def REG : PseudoI<(outs GR32:$dst),
7237 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7238 [(set GR32:$dst, EFLAGS,
7239 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7240 def MEM : PseudoI<(outs GR32:$dst),
7241 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7242 [(set GR32:$dst, EFLAGS,
7243 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
7247 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7248 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
7249 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
7252 multiclass SS42AI_pcmpestri<string asm> {
7253 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7254 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7255 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7258 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7259 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7260 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7264 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7265 let Predicates = [HasAVX] in
7266 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7267 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7270 //===----------------------------------------------------------------------===//
7271 // SSE4.2 - CRC Instructions
7272 //===----------------------------------------------------------------------===//
7274 // No CRC instructions have AVX equivalents
7276 // crc intrinsic instruction
7277 // This set of instructions are only rm, the only difference is the size
7279 let Constraints = "$src1 = $dst" in {
7280 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
7281 (ins GR32:$src1, i8mem:$src2),
7282 "crc32{b}\t{$src2, $src1|$src1, $src2}",
7284 (int_x86_sse42_crc32_32_8 GR32:$src1,
7285 (load addr:$src2)))], IIC_CRC32_MEM>;
7286 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
7287 (ins GR32:$src1, GR8:$src2),
7288 "crc32{b}\t{$src2, $src1|$src1, $src2}",
7290 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))],
7292 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7293 (ins GR32:$src1, i16mem:$src2),
7294 "crc32{w}\t{$src2, $src1|$src1, $src2}",
7296 (int_x86_sse42_crc32_32_16 GR32:$src1,
7297 (load addr:$src2)))], IIC_CRC32_MEM>,
7299 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7300 (ins GR32:$src1, GR16:$src2),
7301 "crc32{w}\t{$src2, $src1|$src1, $src2}",
7303 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))],
7306 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7307 (ins GR32:$src1, i32mem:$src2),
7308 "crc32{l}\t{$src2, $src1|$src1, $src2}",
7310 (int_x86_sse42_crc32_32_32 GR32:$src1,
7311 (load addr:$src2)))], IIC_CRC32_MEM>;
7312 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7313 (ins GR32:$src1, GR32:$src2),
7314 "crc32{l}\t{$src2, $src1|$src1, $src2}",
7316 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))],
7318 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
7319 (ins GR64:$src1, i8mem:$src2),
7320 "crc32{b}\t{$src2, $src1|$src1, $src2}",
7322 (int_x86_sse42_crc32_64_8 GR64:$src1,
7323 (load addr:$src2)))], IIC_CRC32_MEM>,
7325 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
7326 (ins GR64:$src1, GR8:$src2),
7327 "crc32{b}\t{$src2, $src1|$src1, $src2}",
7329 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))],
7332 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
7333 (ins GR64:$src1, i64mem:$src2),
7334 "crc32{q}\t{$src2, $src1|$src1, $src2}",
7336 (int_x86_sse42_crc32_64_64 GR64:$src1,
7337 (load addr:$src2)))], IIC_CRC32_MEM>,
7339 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
7340 (ins GR64:$src1, GR64:$src2),
7341 "crc32{q}\t{$src2, $src1|$src1, $src2}",
7343 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))],
7348 //===----------------------------------------------------------------------===//
7349 // SHA-NI Instructions
7350 //===----------------------------------------------------------------------===//
7352 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7354 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7355 (ins VR128:$src1, VR128:$src2),
7356 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7358 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7359 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7361 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7362 (ins VR128:$src1, i128mem:$src2),
7363 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7365 (set VR128:$dst, (IntId VR128:$src1,
7366 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7367 (set VR128:$dst, (IntId VR128:$src1,
7368 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7371 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7372 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7373 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7374 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7376 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7377 (i8 imm:$src3)))]>, TA;
7378 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7379 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7380 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7382 (int_x86_sha1rnds4 VR128:$src1,
7383 (bc_v4i32 (memopv2i64 addr:$src2)),
7384 (i8 imm:$src3)))]>, TA;
7386 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7387 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7388 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7391 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7393 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7394 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7397 // Aliases with explicit %xmm0
7398 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7399 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7400 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7401 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7403 //===----------------------------------------------------------------------===//
7404 // AES-NI Instructions
7405 //===----------------------------------------------------------------------===//
7407 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7408 Intrinsic IntId128, bit Is2Addr = 1> {
7409 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7410 (ins VR128:$src1, VR128:$src2),
7412 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7413 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7414 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7416 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7417 (ins VR128:$src1, i128mem:$src2),
7419 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7420 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7422 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7425 // Perform One Round of an AES Encryption/Decryption Flow
7426 let Predicates = [HasAVX, HasAES] in {
7427 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7428 int_x86_aesni_aesenc, 0>, VEX_4V;
7429 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7430 int_x86_aesni_aesenclast, 0>, VEX_4V;
7431 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7432 int_x86_aesni_aesdec, 0>, VEX_4V;
7433 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7434 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7437 let Constraints = "$src1 = $dst" in {
7438 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7439 int_x86_aesni_aesenc>;
7440 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7441 int_x86_aesni_aesenclast>;
7442 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7443 int_x86_aesni_aesdec>;
7444 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7445 int_x86_aesni_aesdeclast>;
7448 // Perform the AES InvMixColumn Transformation
7449 let Predicates = [HasAVX, HasAES] in {
7450 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7452 "vaesimc\t{$src1, $dst|$dst, $src1}",
7454 (int_x86_aesni_aesimc VR128:$src1))]>,
7456 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7457 (ins i128mem:$src1),
7458 "vaesimc\t{$src1, $dst|$dst, $src1}",
7459 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7462 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7464 "aesimc\t{$src1, $dst|$dst, $src1}",
7466 (int_x86_aesni_aesimc VR128:$src1))]>,
7468 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7469 (ins i128mem:$src1),
7470 "aesimc\t{$src1, $dst|$dst, $src1}",
7471 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7474 // AES Round Key Generation Assist
7475 let Predicates = [HasAVX, HasAES] in {
7476 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7477 (ins VR128:$src1, i8imm:$src2),
7478 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7480 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7482 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7483 (ins i128mem:$src1, i8imm:$src2),
7484 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7486 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7489 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7490 (ins VR128:$src1, i8imm:$src2),
7491 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7493 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7495 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7496 (ins i128mem:$src1, i8imm:$src2),
7497 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7499 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7502 //===----------------------------------------------------------------------===//
7503 // PCLMUL Instructions
7504 //===----------------------------------------------------------------------===//
7506 // AVX carry-less Multiplication instructions
7507 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7508 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7509 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7511 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7513 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7514 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7515 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7516 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7517 (memopv2i64 addr:$src2), imm:$src3))]>;
7519 // Carry-less Multiplication instructions
7520 let Constraints = "$src1 = $dst" in {
7521 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7522 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7523 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7525 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
7526 IIC_SSE_PCLMULQDQ_RR>;
7528 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7529 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7530 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7531 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7532 (memopv2i64 addr:$src2), imm:$src3))],
7533 IIC_SSE_PCLMULQDQ_RM>;
7534 } // Constraints = "$src1 = $dst"
7537 multiclass pclmul_alias<string asm, int immop> {
7538 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7539 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7541 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7542 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7544 def : InstAlias<!strconcat("vpclmul", asm,
7545 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7546 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7548 def : InstAlias<!strconcat("vpclmul", asm,
7549 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7550 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7552 defm : pclmul_alias<"hqhq", 0x11>;
7553 defm : pclmul_alias<"hqlq", 0x01>;
7554 defm : pclmul_alias<"lqhq", 0x10>;
7555 defm : pclmul_alias<"lqlq", 0x00>;
7557 //===----------------------------------------------------------------------===//
7558 // SSE4A Instructions
7559 //===----------------------------------------------------------------------===//
7561 let Predicates = [HasSSE4A] in {
7563 let Constraints = "$src = $dst" in {
7564 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7565 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7566 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7567 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7568 imm:$idx))]>, TB, OpSize;
7569 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7570 (ins VR128:$src, VR128:$mask),
7571 "extrq\t{$mask, $src|$src, $mask}",
7572 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7573 VR128:$mask))]>, TB, OpSize;
7575 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7576 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7577 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7578 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7579 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7580 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7581 (ins VR128:$src, VR128:$mask),
7582 "insertq\t{$mask, $src|$src, $mask}",
7583 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7584 VR128:$mask))]>, XD;
7587 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7588 "movntss\t{$src, $dst|$dst, $src}",
7589 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7591 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7592 "movntsd\t{$src, $dst|$dst, $src}",
7593 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7596 //===----------------------------------------------------------------------===//
7598 //===----------------------------------------------------------------------===//
7600 //===----------------------------------------------------------------------===//
7601 // VBROADCAST - Load from memory and broadcast to all elements of the
7602 // destination operand
7604 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7605 X86MemOperand x86memop, Intrinsic Int> :
7606 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7607 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7608 [(set RC:$dst, (Int addr:$src))]>, VEX;
7610 // AVX2 adds register forms
7611 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7613 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7614 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7615 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7617 let ExeDomain = SSEPackedSingle in {
7618 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7619 int_x86_avx_vbroadcast_ss>;
7620 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7621 int_x86_avx_vbroadcast_ss_256>, VEX_L;
7623 let ExeDomain = SSEPackedDouble in
7624 def VBROADCASTSDYrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7625 int_x86_avx_vbroadcast_sd_256>, VEX_L;
7626 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7627 int_x86_avx_vbroadcastf128_pd_256>, VEX_L;
7629 let ExeDomain = SSEPackedSingle in {
7630 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7631 int_x86_avx2_vbroadcast_ss_ps>;
7632 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7633 int_x86_avx2_vbroadcast_ss_ps_256>, VEX_L;
7635 let ExeDomain = SSEPackedDouble in
7636 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7637 int_x86_avx2_vbroadcast_sd_pd_256>, VEX_L;
7639 let Predicates = [HasAVX2] in
7640 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7641 int_x86_avx2_vbroadcasti128>, VEX_L;
7643 let Predicates = [HasAVX] in
7644 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7645 (VBROADCASTF128 addr:$src)>;
7648 //===----------------------------------------------------------------------===//
7649 // VINSERTF128 - Insert packed floating-point values
7651 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7652 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7653 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7654 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7657 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7658 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7659 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7663 let Predicates = [HasAVX] in {
7664 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7666 (VINSERTF128rr VR256:$src1, VR128:$src2,
7667 (INSERT_get_vinsert128_imm VR256:$ins))>;
7668 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7670 (VINSERTF128rr VR256:$src1, VR128:$src2,
7671 (INSERT_get_vinsert128_imm VR256:$ins))>;
7673 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7675 (VINSERTF128rm VR256:$src1, addr:$src2,
7676 (INSERT_get_vinsert128_imm VR256:$ins))>;
7677 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7679 (VINSERTF128rm VR256:$src1, addr:$src2,
7680 (INSERT_get_vinsert128_imm VR256:$ins))>;
7683 let Predicates = [HasAVX1Only] in {
7684 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7686 (VINSERTF128rr VR256:$src1, VR128:$src2,
7687 (INSERT_get_vinsert128_imm VR256:$ins))>;
7688 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7690 (VINSERTF128rr VR256:$src1, VR128:$src2,
7691 (INSERT_get_vinsert128_imm VR256:$ins))>;
7692 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7694 (VINSERTF128rr VR256:$src1, VR128:$src2,
7695 (INSERT_get_vinsert128_imm VR256:$ins))>;
7696 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7698 (VINSERTF128rr VR256:$src1, VR128:$src2,
7699 (INSERT_get_vinsert128_imm VR256:$ins))>;
7701 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7703 (VINSERTF128rm VR256:$src1, addr:$src2,
7704 (INSERT_get_vinsert128_imm VR256:$ins))>;
7705 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
7706 (bc_v4i32 (loadv2i64 addr:$src2)),
7708 (VINSERTF128rm VR256:$src1, addr:$src2,
7709 (INSERT_get_vinsert128_imm VR256:$ins))>;
7710 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
7711 (bc_v16i8 (loadv2i64 addr:$src2)),
7713 (VINSERTF128rm VR256:$src1, addr:$src2,
7714 (INSERT_get_vinsert128_imm VR256:$ins))>;
7715 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
7716 (bc_v8i16 (loadv2i64 addr:$src2)),
7718 (VINSERTF128rm VR256:$src1, addr:$src2,
7719 (INSERT_get_vinsert128_imm VR256:$ins))>;
7722 //===----------------------------------------------------------------------===//
7723 // VEXTRACTF128 - Extract packed floating-point values
7725 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7726 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7727 (ins VR256:$src1, i8imm:$src2),
7728 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7731 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7732 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7733 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7738 let Predicates = [HasAVX] in {
7739 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7740 (v4f32 (VEXTRACTF128rr
7741 (v8f32 VR256:$src1),
7742 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7743 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7744 (v2f64 (VEXTRACTF128rr
7745 (v4f64 VR256:$src1),
7746 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7748 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
7749 (iPTR imm))), addr:$dst),
7750 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7751 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7752 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
7753 (iPTR imm))), addr:$dst),
7754 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7755 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7758 let Predicates = [HasAVX1Only] in {
7759 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7760 (v2i64 (VEXTRACTF128rr
7761 (v4i64 VR256:$src1),
7762 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7763 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7764 (v4i32 (VEXTRACTF128rr
7765 (v8i32 VR256:$src1),
7766 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7767 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7768 (v8i16 (VEXTRACTF128rr
7769 (v16i16 VR256:$src1),
7770 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7771 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7772 (v16i8 (VEXTRACTF128rr
7773 (v32i8 VR256:$src1),
7774 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7776 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
7777 (iPTR imm))), addr:$dst),
7778 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7779 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7780 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
7781 (iPTR imm))), addr:$dst),
7782 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7783 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7784 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
7785 (iPTR imm))), addr:$dst),
7786 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7787 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7788 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
7789 (iPTR imm))), addr:$dst),
7790 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7791 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7794 //===----------------------------------------------------------------------===//
7795 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7797 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7798 Intrinsic IntLd, Intrinsic IntLd256,
7799 Intrinsic IntSt, Intrinsic IntSt256> {
7800 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7801 (ins VR128:$src1, f128mem:$src2),
7802 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7803 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7805 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7806 (ins VR256:$src1, f256mem:$src2),
7807 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7808 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7810 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7811 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7812 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7813 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7814 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7815 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7816 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7817 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
7820 let ExeDomain = SSEPackedSingle in
7821 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7822 int_x86_avx_maskload_ps,
7823 int_x86_avx_maskload_ps_256,
7824 int_x86_avx_maskstore_ps,
7825 int_x86_avx_maskstore_ps_256>;
7826 let ExeDomain = SSEPackedDouble in
7827 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7828 int_x86_avx_maskload_pd,
7829 int_x86_avx_maskload_pd_256,
7830 int_x86_avx_maskstore_pd,
7831 int_x86_avx_maskstore_pd_256>;
7833 //===----------------------------------------------------------------------===//
7834 // VPERMIL - Permute Single and Double Floating-Point Values
7836 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7837 RegisterClass RC, X86MemOperand x86memop_f,
7838 X86MemOperand x86memop_i, PatFrag i_frag,
7839 Intrinsic IntVar, ValueType vt> {
7840 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7841 (ins RC:$src1, RC:$src2),
7842 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7843 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7844 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7845 (ins RC:$src1, x86memop_i:$src2),
7846 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7847 [(set RC:$dst, (IntVar RC:$src1,
7848 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7850 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7851 (ins RC:$src1, i8imm:$src2),
7852 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7853 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7854 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7855 (ins x86memop_f:$src1, i8imm:$src2),
7856 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7858 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7861 let ExeDomain = SSEPackedSingle in {
7862 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7863 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7864 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7865 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
7867 let ExeDomain = SSEPackedDouble in {
7868 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7869 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7870 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7871 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
7874 let Predicates = [HasAVX] in {
7875 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7876 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7877 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7878 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7879 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7881 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7882 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7883 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7885 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7886 (VPERMILPDri VR128:$src1, imm:$imm)>;
7887 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7888 (VPERMILPDmi addr:$src1, imm:$imm)>;
7891 //===----------------------------------------------------------------------===//
7892 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7894 let ExeDomain = SSEPackedSingle in {
7895 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7896 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7897 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7898 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7899 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
7900 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7901 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7902 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7903 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7904 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
7907 let Predicates = [HasAVX] in {
7908 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7909 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7910 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7911 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7912 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7915 let Predicates = [HasAVX1Only] in {
7916 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7917 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7918 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7919 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7920 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7921 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7922 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7923 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7925 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7926 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7927 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7928 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7929 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7930 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7931 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7932 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7933 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7934 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7935 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7936 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7939 //===----------------------------------------------------------------------===//
7940 // VZERO - Zero YMM registers
7942 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7943 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7944 // Zero All YMM registers
7945 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7946 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7948 // Zero Upper bits of YMM registers
7949 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7950 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7953 //===----------------------------------------------------------------------===//
7954 // Half precision conversion instructions
7955 //===----------------------------------------------------------------------===//
7956 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7957 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7958 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7959 [(set RC:$dst, (Int VR128:$src))]>,
7961 let neverHasSideEffects = 1, mayLoad = 1 in
7962 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7963 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7966 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7967 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7968 (ins RC:$src1, i32i8imm:$src2),
7969 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7970 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7972 let neverHasSideEffects = 1, mayStore = 1 in
7973 def mr : Ii8<0x1D, MRMDestMem, (outs),
7974 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
7975 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7979 let Predicates = [HasF16C] in {
7980 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7981 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
7982 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7983 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
7986 //===----------------------------------------------------------------------===//
7987 // AVX2 Instructions
7988 //===----------------------------------------------------------------------===//
7990 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7991 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7992 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7993 X86MemOperand x86memop> {
7994 let isCommutable = 1 in
7995 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7996 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7997 !strconcat(OpcodeStr,
7998 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7999 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
8001 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8002 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
8003 !strconcat(OpcodeStr,
8004 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8007 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
8011 let isCommutable = 0 in {
8012 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
8013 VR128, memopv2i64, i128mem>;
8014 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
8015 VR256, memopv4i64, i256mem>, VEX_L;
8018 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
8020 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
8021 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
8023 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
8025 //===----------------------------------------------------------------------===//
8026 // VPBROADCAST - Load from memory and broadcast to all elements of the
8027 // destination operand
8029 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8030 X86MemOperand x86memop, PatFrag ld_frag,
8031 Intrinsic Int128, Intrinsic Int256> {
8032 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8033 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8034 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
8035 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8036 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8038 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
8039 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8040 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8041 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX, VEX_L;
8042 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8043 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8045 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8049 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8050 int_x86_avx2_pbroadcastb_128,
8051 int_x86_avx2_pbroadcastb_256>;
8052 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8053 int_x86_avx2_pbroadcastw_128,
8054 int_x86_avx2_pbroadcastw_256>;
8055 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8056 int_x86_avx2_pbroadcastd_128,
8057 int_x86_avx2_pbroadcastd_256>;
8058 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8059 int_x86_avx2_pbroadcastq_128,
8060 int_x86_avx2_pbroadcastq_256>;
8062 let Predicates = [HasAVX2] in {
8063 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8064 (VPBROADCASTBrm addr:$src)>;
8065 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8066 (VPBROADCASTBYrm addr:$src)>;
8067 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8068 (VPBROADCASTWrm addr:$src)>;
8069 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8070 (VPBROADCASTWYrm addr:$src)>;
8071 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8072 (VPBROADCASTDrm addr:$src)>;
8073 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8074 (VPBROADCASTDYrm addr:$src)>;
8075 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8076 (VPBROADCASTQrm addr:$src)>;
8077 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8078 (VPBROADCASTQYrm addr:$src)>;
8080 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8081 (VPBROADCASTBrr VR128:$src)>;
8082 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8083 (VPBROADCASTBYrr VR128:$src)>;
8084 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8085 (VPBROADCASTWrr VR128:$src)>;
8086 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8087 (VPBROADCASTWYrr VR128:$src)>;
8088 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8089 (VPBROADCASTDrr VR128:$src)>;
8090 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8091 (VPBROADCASTDYrr VR128:$src)>;
8092 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8093 (VPBROADCASTQrr VR128:$src)>;
8094 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8095 (VPBROADCASTQYrr VR128:$src)>;
8096 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8097 (VBROADCASTSSrr VR128:$src)>;
8098 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8099 (VBROADCASTSSYrr VR128:$src)>;
8100 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8101 (VPBROADCASTQrr VR128:$src)>;
8102 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8103 (VBROADCASTSDYrr VR128:$src)>;
8105 // Provide fallback in case the load node that is used in the patterns above
8106 // is used by additional users, which prevents the pattern selection.
8107 let AddedComplexity = 20 in {
8108 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8109 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8110 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8111 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8112 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8113 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8115 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8116 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8117 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8118 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8119 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8120 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8124 // AVX1 broadcast patterns
8125 let Predicates = [HasAVX1Only] in {
8126 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8127 (VBROADCASTSSYrm addr:$src)>;
8128 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8129 (VBROADCASTSDYrm addr:$src)>;
8130 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8131 (VBROADCASTSSrm addr:$src)>;
8134 let Predicates = [HasAVX] in {
8135 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
8136 (VBROADCASTSSYrm addr:$src)>;
8137 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
8138 (VBROADCASTSDYrm addr:$src)>;
8139 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
8140 (VBROADCASTSSrm addr:$src)>;
8142 // Provide fallback in case the load node that is used in the patterns above
8143 // is used by additional users, which prevents the pattern selection.
8144 let AddedComplexity = 20 in {
8145 // 128bit broadcasts:
8146 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8147 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8148 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8149 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8150 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8151 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8152 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8153 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8154 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8155 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8157 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8158 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8159 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8160 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8161 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8162 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8163 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8164 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8165 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8166 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8170 //===----------------------------------------------------------------------===//
8171 // VPERM - Permute instructions
8174 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8176 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8177 (ins VR256:$src1, VR256:$src2),
8178 !strconcat(OpcodeStr,
8179 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8181 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8183 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8184 (ins VR256:$src1, i256mem:$src2),
8185 !strconcat(OpcodeStr,
8186 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8188 (OpVT (X86VPermv VR256:$src1,
8189 (bitconvert (mem_frag addr:$src2)))))]>,
8193 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, v8i32>;
8194 let ExeDomain = SSEPackedSingle in
8195 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, v8f32>;
8197 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8199 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8200 (ins VR256:$src1, i8imm:$src2),
8201 !strconcat(OpcodeStr,
8202 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8204 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8206 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8207 (ins i256mem:$src1, i8imm:$src2),
8208 !strconcat(OpcodeStr,
8209 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8211 (OpVT (X86VPermi (mem_frag addr:$src1),
8212 (i8 imm:$src2))))]>, VEX, VEX_L;
8215 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, v4i64>, VEX_W;
8216 let ExeDomain = SSEPackedDouble in
8217 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, v4f64>, VEX_W;
8219 //===----------------------------------------------------------------------===//
8220 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8222 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8223 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8224 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8225 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8226 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
8227 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8228 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8229 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8230 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
8231 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
8233 let Predicates = [HasAVX2] in {
8234 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8235 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8236 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8237 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8238 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8239 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8241 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
8243 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8244 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8245 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
8246 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8247 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
8249 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8253 //===----------------------------------------------------------------------===//
8254 // VINSERTI128 - Insert packed integer values
8256 let neverHasSideEffects = 1 in {
8257 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8258 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8259 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8262 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8263 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
8264 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8268 let Predicates = [HasAVX2] in {
8269 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8271 (VINSERTI128rr VR256:$src1, VR128:$src2,
8272 (INSERT_get_vinsert128_imm VR256:$ins))>;
8273 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8275 (VINSERTI128rr VR256:$src1, VR128:$src2,
8276 (INSERT_get_vinsert128_imm VR256:$ins))>;
8277 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8279 (VINSERTI128rr VR256:$src1, VR128:$src2,
8280 (INSERT_get_vinsert128_imm VR256:$ins))>;
8281 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8283 (VINSERTI128rr VR256:$src1, VR128:$src2,
8284 (INSERT_get_vinsert128_imm VR256:$ins))>;
8286 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8288 (VINSERTI128rm VR256:$src1, addr:$src2,
8289 (INSERT_get_vinsert128_imm VR256:$ins))>;
8290 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8291 (bc_v4i32 (loadv2i64 addr:$src2)),
8293 (VINSERTI128rm VR256:$src1, addr:$src2,
8294 (INSERT_get_vinsert128_imm VR256:$ins))>;
8295 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8296 (bc_v16i8 (loadv2i64 addr:$src2)),
8298 (VINSERTI128rm VR256:$src1, addr:$src2,
8299 (INSERT_get_vinsert128_imm VR256:$ins))>;
8300 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8301 (bc_v8i16 (loadv2i64 addr:$src2)),
8303 (VINSERTI128rm VR256:$src1, addr:$src2,
8304 (INSERT_get_vinsert128_imm VR256:$ins))>;
8307 //===----------------------------------------------------------------------===//
8308 // VEXTRACTI128 - Extract packed integer values
8310 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8311 (ins VR256:$src1, i8imm:$src2),
8312 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8314 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8316 let neverHasSideEffects = 1, mayStore = 1 in
8317 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8318 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
8319 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8322 let Predicates = [HasAVX2] in {
8323 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8324 (v2i64 (VEXTRACTI128rr
8325 (v4i64 VR256:$src1),
8326 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8327 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8328 (v4i32 (VEXTRACTI128rr
8329 (v8i32 VR256:$src1),
8330 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8331 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8332 (v8i16 (VEXTRACTI128rr
8333 (v16i16 VR256:$src1),
8334 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8335 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8336 (v16i8 (VEXTRACTI128rr
8337 (v32i8 VR256:$src1),
8338 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8340 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8341 (iPTR imm))), addr:$dst),
8342 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8343 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8344 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8345 (iPTR imm))), addr:$dst),
8346 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8347 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8348 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8349 (iPTR imm))), addr:$dst),
8350 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8351 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8352 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8353 (iPTR imm))), addr:$dst),
8354 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8355 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8358 //===----------------------------------------------------------------------===//
8359 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8361 multiclass avx2_pmovmask<string OpcodeStr,
8362 Intrinsic IntLd128, Intrinsic IntLd256,
8363 Intrinsic IntSt128, Intrinsic IntSt256> {
8364 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8365 (ins VR128:$src1, i128mem:$src2),
8366 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8367 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8368 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8369 (ins VR256:$src1, i256mem:$src2),
8370 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8371 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8373 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8374 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8375 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8376 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8377 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8378 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8379 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8380 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8383 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8384 int_x86_avx2_maskload_d,
8385 int_x86_avx2_maskload_d_256,
8386 int_x86_avx2_maskstore_d,
8387 int_x86_avx2_maskstore_d_256>;
8388 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8389 int_x86_avx2_maskload_q,
8390 int_x86_avx2_maskload_q_256,
8391 int_x86_avx2_maskstore_q,
8392 int_x86_avx2_maskstore_q_256>, VEX_W;
8395 //===----------------------------------------------------------------------===//
8396 // Variable Bit Shifts
8398 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8399 ValueType vt128, ValueType vt256> {
8400 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8401 (ins VR128:$src1, VR128:$src2),
8402 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8404 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8406 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8407 (ins VR128:$src1, i128mem:$src2),
8408 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8410 (vt128 (OpNode VR128:$src1,
8411 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
8413 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8414 (ins VR256:$src1, VR256:$src2),
8415 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8417 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8419 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8420 (ins VR256:$src1, i256mem:$src2),
8421 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8423 (vt256 (OpNode VR256:$src1,
8424 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
8428 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8429 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8430 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8431 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8432 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8434 //===----------------------------------------------------------------------===//
8435 // VGATHER - GATHER Operations
8436 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8437 X86MemOperand memop128, X86MemOperand memop256> {
8438 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8439 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8440 !strconcat(OpcodeStr,
8441 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8443 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8444 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8445 !strconcat(OpcodeStr,
8446 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8447 []>, VEX_4VOp3, VEX_L;
8450 let mayLoad = 1, Constraints
8451 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
8453 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8454 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8455 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8456 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;
8457 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8458 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8459 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8460 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;