1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 let isCommutable = 1 in
85 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
90 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
97 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
98 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
99 string asm, string SSEVer, string FPSizeStr,
100 X86MemOperand x86memop, PatFrag mem_frag,
101 Domain d, bit Is2Addr = 1> {
102 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
104 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
105 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
106 [(set RC:$dst, (!cast<Intrinsic>(
107 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
108 RC:$src1, RC:$src2))], d>;
109 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
111 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
113 [(set RC:$dst, (!cast<Intrinsic>(
114 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
115 RC:$src1, (mem_frag addr:$src2)))], d>;
118 //===----------------------------------------------------------------------===//
119 // SSE 1 & 2 - Move Instructions
120 //===----------------------------------------------------------------------===//
122 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
123 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
124 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
126 // Loading from memory automatically zeroing upper bits.
127 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
128 PatFrag mem_pat, string OpcodeStr> :
129 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
130 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
131 [(set RC:$dst, (mem_pat addr:$src))]>;
133 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
134 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
135 // is used instead. Register-to-register movss/movsd is not modeled as an
136 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
137 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
138 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
139 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
140 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
141 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
143 let canFoldAsLoad = 1, isReMaterializable = 1 in {
144 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
146 let AddedComplexity = 20 in
147 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
150 let Constraints = "$src1 = $dst" in {
151 def MOVSSrr : sse12_move_rr<FR32, v4f32,
152 "movss\t{$src2, $dst|$dst, $src2}">, XS;
153 def MOVSDrr : sse12_move_rr<FR64, v2f64,
154 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
157 let canFoldAsLoad = 1, isReMaterializable = 1 in {
158 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
160 let AddedComplexity = 20 in
161 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
164 let AddedComplexity = 15 in {
165 // Extract the low 32-bit value from one vector and insert it into another.
166 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
167 (MOVSSrr (v4f32 VR128:$src1),
168 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
169 // Extract the low 64-bit value from one vector and insert it into another.
170 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
171 (MOVSDrr (v2f64 VR128:$src1),
172 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
175 // Implicitly promote a 32-bit scalar to a vector.
176 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
177 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
178 // Implicitly promote a 64-bit scalar to a vector.
179 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
180 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
181 // Implicitly promote a 32-bit scalar to a vector.
182 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
183 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
184 // Implicitly promote a 64-bit scalar to a vector.
185 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
186 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
188 let AddedComplexity = 20 in {
189 // MOVSSrm zeros the high parts of the register; represent this
190 // with SUBREG_TO_REG.
191 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
192 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
193 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
194 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
195 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
196 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
197 // MOVSDrm zeros the high parts of the register; represent this
198 // with SUBREG_TO_REG.
199 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
200 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
201 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
202 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
203 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
204 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
205 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
206 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
207 def : Pat<(v2f64 (X86vzload addr:$src)),
208 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
211 // Store scalar value to memory.
212 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
213 "movss\t{$src, $dst|$dst, $src}",
214 [(store FR32:$src, addr:$dst)]>;
215 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
216 "movsd\t{$src, $dst|$dst, $src}",
217 [(store FR64:$src, addr:$dst)]>;
219 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
220 "movss\t{$src, $dst|$dst, $src}",
221 [(store FR32:$src, addr:$dst)]>, XS, VEX;
222 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
223 "movsd\t{$src, $dst|$dst, $src}",
224 [(store FR64:$src, addr:$dst)]>, XD, VEX;
226 // Extract and store.
227 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
230 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
231 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
234 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
236 // Move Aligned/Unaligned floating point values
237 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
238 X86MemOperand x86memop, PatFrag ld_frag,
239 string asm, Domain d,
240 bit IsReMaterializable = 1> {
241 let neverHasSideEffects = 1 in
242 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
243 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
244 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
245 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
246 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
247 [(set RC:$dst, (ld_frag addr:$src))], d>;
250 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
251 "movaps", SSEPackedSingle>, VEX;
252 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
253 "movapd", SSEPackedDouble>, OpSize, VEX;
254 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
255 "movups", SSEPackedSingle>, VEX;
256 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
257 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
259 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
260 "movaps", SSEPackedSingle>, VEX;
261 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
262 "movapd", SSEPackedDouble>, OpSize, VEX;
263 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
264 "movups", SSEPackedSingle>, VEX;
265 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
266 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
267 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
268 "movaps", SSEPackedSingle>, TB;
269 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
270 "movapd", SSEPackedDouble>, TB, OpSize;
271 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
272 "movups", SSEPackedSingle>, TB;
273 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
274 "movupd", SSEPackedDouble, 0>, TB, OpSize;
276 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
277 "movaps\t{$src, $dst|$dst, $src}",
278 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
279 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
280 "movapd\t{$src, $dst|$dst, $src}",
281 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
282 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
283 "movups\t{$src, $dst|$dst, $src}",
284 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
285 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
286 "movupd\t{$src, $dst|$dst, $src}",
287 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
288 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
289 "movaps\t{$src, $dst|$dst, $src}",
290 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
291 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
292 "movapd\t{$src, $dst|$dst, $src}",
293 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
294 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
295 "movups\t{$src, $dst|$dst, $src}",
296 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
297 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
298 "movupd\t{$src, $dst|$dst, $src}",
299 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
301 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
302 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
303 (VMOVUPSYmr addr:$dst, VR256:$src)>;
305 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
306 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
307 (VMOVUPDYmr addr:$dst, VR256:$src)>;
309 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
310 "movaps\t{$src, $dst|$dst, $src}",
311 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
312 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
313 "movapd\t{$src, $dst|$dst, $src}",
314 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
315 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
316 "movups\t{$src, $dst|$dst, $src}",
317 [(store (v4f32 VR128:$src), addr:$dst)]>;
318 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
319 "movupd\t{$src, $dst|$dst, $src}",
320 [(store (v2f64 VR128:$src), addr:$dst)]>;
322 // Intrinsic forms of MOVUPS/D load and store
323 def VMOVUPSmr_Int : VPSI<0x11, MRMDestMem, (outs),
324 (ins f128mem:$dst, VR128:$src),
325 "movups\t{$src, $dst|$dst, $src}",
326 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX;
327 def VMOVUPDmr_Int : VPDI<0x11, MRMDestMem, (outs),
328 (ins f128mem:$dst, VR128:$src),
329 "movupd\t{$src, $dst|$dst, $src}",
330 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX;
332 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
333 "movups\t{$src, $dst|$dst, $src}",
334 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
335 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
336 "movupd\t{$src, $dst|$dst, $src}",
337 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
339 // Move Low/High packed floating point values
340 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
341 PatFrag mov_frag, string base_opc,
343 def PSrm : PI<opc, MRMSrcMem,
344 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
345 !strconcat(base_opc, "s", asm_opr),
348 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
349 SSEPackedSingle>, TB;
351 def PDrm : PI<opc, MRMSrcMem,
352 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
353 !strconcat(base_opc, "d", asm_opr),
354 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
355 (scalar_to_vector (loadf64 addr:$src2)))))],
356 SSEPackedDouble>, TB, OpSize;
359 let AddedComplexity = 20 in {
360 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
361 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
362 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
363 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
365 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
366 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
367 "\t{$src2, $dst|$dst, $src2}">;
368 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
369 "\t{$src2, $dst|$dst, $src2}">;
372 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
373 "movlps\t{$src, $dst|$dst, $src}",
374 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
375 (iPTR 0))), addr:$dst)]>, VEX;
376 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
377 "movlpd\t{$src, $dst|$dst, $src}",
378 [(store (f64 (vector_extract (v2f64 VR128:$src),
379 (iPTR 0))), addr:$dst)]>, VEX;
380 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
381 "movlps\t{$src, $dst|$dst, $src}",
382 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
383 (iPTR 0))), addr:$dst)]>;
384 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
385 "movlpd\t{$src, $dst|$dst, $src}",
386 [(store (f64 (vector_extract (v2f64 VR128:$src),
387 (iPTR 0))), addr:$dst)]>;
389 // v2f64 extract element 1 is always custom lowered to unpack high to low
390 // and extract element 0 so the non-store version isn't too horrible.
391 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
392 "movhps\t{$src, $dst|$dst, $src}",
393 [(store (f64 (vector_extract
394 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
395 (undef)), (iPTR 0))), addr:$dst)]>,
397 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
398 "movhpd\t{$src, $dst|$dst, $src}",
399 [(store (f64 (vector_extract
400 (v2f64 (unpckh VR128:$src, (undef))),
401 (iPTR 0))), addr:$dst)]>,
403 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
404 "movhps\t{$src, $dst|$dst, $src}",
405 [(store (f64 (vector_extract
406 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
407 (undef)), (iPTR 0))), addr:$dst)]>;
408 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
409 "movhpd\t{$src, $dst|$dst, $src}",
410 [(store (f64 (vector_extract
411 (v2f64 (unpckh VR128:$src, (undef))),
412 (iPTR 0))), addr:$dst)]>;
414 let AddedComplexity = 20 in {
415 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
416 (ins VR128:$src1, VR128:$src2),
417 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
419 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
421 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
422 (ins VR128:$src1, VR128:$src2),
423 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
425 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
428 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
429 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
430 (ins VR128:$src1, VR128:$src2),
431 "movlhps\t{$src2, $dst|$dst, $src2}",
433 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
434 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
435 (ins VR128:$src1, VR128:$src2),
436 "movhlps\t{$src2, $dst|$dst, $src2}",
438 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
441 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
442 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
443 let AddedComplexity = 20 in {
444 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
445 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
446 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
447 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
450 //===----------------------------------------------------------------------===//
451 // SSE 1 & 2 - Conversion Instructions
452 //===----------------------------------------------------------------------===//
454 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
455 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
457 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
458 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
459 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
460 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
463 multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
464 X86MemOperand x86memop, string asm> {
465 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
467 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
471 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
472 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
473 string asm, Domain d> {
474 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
475 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
476 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
477 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
480 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
481 X86MemOperand x86memop, string asm> {
482 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
483 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
484 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
485 (ins DstRC:$src1, x86memop:$src),
486 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
489 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
490 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
491 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
492 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
494 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
495 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
496 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
497 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
500 // The assembler can recognize rr 64-bit instructions by seeing a rxx
501 // register, but the same isn't true when only using memory operands,
502 // provide other assembly "l" and "q" forms to address this explicitly
503 // where appropriate to do so.
504 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
506 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
508 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
510 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
512 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
515 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
516 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
517 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
518 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
519 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
520 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
521 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
522 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
523 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
524 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
525 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
526 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
527 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
528 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
529 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
530 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
532 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
533 // and/or XMM operand(s).
535 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
536 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
538 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
539 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
540 [(set DstRC:$dst, (Int SrcRC:$src))]>;
541 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
542 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
543 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
546 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
547 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
548 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
549 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
551 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
552 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
553 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
554 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
555 (ins DstRC:$src1, x86memop:$src2),
557 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
558 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
559 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
562 defm Int_VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
563 f32mem, load, "cvtss2si">, XS, VEX;
564 defm Int_VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
565 int_x86_sse_cvtss2si64, f32mem, load, "cvtss2si">,
567 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
568 f128mem, load, "cvtsd2si">, XD, VEX;
569 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
570 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
573 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
574 // Get rid of this hack or rename the intrinsics, there are several
575 // intructions that only match with the intrinsic form, why create duplicates
576 // to let them be recognized by the assembler?
577 defm VCVTSD2SI_alt : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
578 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
579 defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
580 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
581 defm Int_CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
582 f32mem, load, "cvtss2si">, XS;
583 defm Int_CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
584 f32mem, load, "cvtss2si{q}">, XS, REX_W;
585 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
586 f128mem, load, "cvtsd2si{l}">, XD;
587 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
588 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
591 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
592 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
593 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
594 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
596 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
597 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
598 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
599 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
602 let Constraints = "$src1 = $dst" in {
603 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
604 int_x86_sse_cvtsi2ss, i32mem, loadi32,
606 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
607 int_x86_sse_cvtsi642ss, i64mem, loadi64,
608 "cvtsi2ss{q}">, XS, REX_W;
609 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
610 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
612 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
613 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
614 "cvtsi2sd">, XD, REX_W;
619 // Aliases for intrinsics
620 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
621 f32mem, load, "cvttss2si">, XS, VEX;
622 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
623 int_x86_sse_cvttss2si64, f32mem, load,
624 "cvttss2si">, XS, VEX, VEX_W;
625 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
626 f128mem, load, "cvttsd2si">, XD, VEX;
627 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
628 int_x86_sse2_cvttsd2si64, f128mem, load,
629 "cvttsd2si">, XD, VEX, VEX_W;
630 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
631 f32mem, load, "cvttss2si">, XS;
632 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
633 int_x86_sse_cvttss2si64, f32mem, load,
634 "cvttss2si{q}">, XS, REX_W;
635 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
636 f128mem, load, "cvttsd2si">, XD;
637 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
638 int_x86_sse2_cvttsd2si64, f128mem, load,
639 "cvttsd2si{q}">, XD, REX_W;
641 let Pattern = []<dag> in {
642 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
643 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
644 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
645 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
647 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
648 "cvtdq2ps\t{$src, $dst|$dst, $src}",
649 SSEPackedSingle>, TB, VEX;
650 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
651 "cvtdq2ps\t{$src, $dst|$dst, $src}",
652 SSEPackedSingle>, TB, VEX;
654 let Pattern = []<dag> in {
655 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
656 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
657 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
658 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
659 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
660 "cvtdq2ps\t{$src, $dst|$dst, $src}",
661 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
666 // Convert scalar double to scalar single
667 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
668 (ins FR64:$src1, FR64:$src2),
669 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
671 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
672 (ins FR64:$src1, f64mem:$src2),
673 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
674 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
675 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
678 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
679 "cvtsd2ss\t{$src, $dst|$dst, $src}",
680 [(set FR32:$dst, (fround FR64:$src))]>;
681 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
682 "cvtsd2ss\t{$src, $dst|$dst, $src}",
683 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
684 Requires<[HasSSE2, OptForSize]>;
686 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
687 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
689 let Constraints = "$src1 = $dst" in
690 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
691 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
693 // Convert scalar single to scalar double
694 // SSE2 instructions with XS prefix
695 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
696 (ins FR32:$src1, FR32:$src2),
697 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
698 []>, XS, Requires<[HasAVX]>, VEX_4V;
699 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
700 (ins FR32:$src1, f32mem:$src2),
701 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
702 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
703 def : Pat<(f64 (fextend FR32:$src)), (VCVTSS2SDrr FR32:$src, FR32:$src)>,
706 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
707 "cvtss2sd\t{$src, $dst|$dst, $src}",
708 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
710 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
711 "cvtss2sd\t{$src, $dst|$dst, $src}",
712 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
713 Requires<[HasSSE2, OptForSize]>;
715 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
716 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
717 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
718 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
719 VR128:$src2))]>, XS, VEX_4V,
721 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
722 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
723 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
724 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
725 (load addr:$src2)))]>, XS, VEX_4V,
727 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
728 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
729 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
730 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
731 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
734 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
735 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
736 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
737 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
738 (load addr:$src2)))]>, XS,
742 def : Pat<(extloadf32 addr:$src),
743 (CVTSS2SDrr (MOVSSrm addr:$src))>,
744 Requires<[HasSSE2, OptForSpeed]>;
746 // Convert doubleword to packed single/double fp
747 // SSE2 instructions without OpSize prefix
748 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
749 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
750 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
751 TB, VEX, Requires<[HasAVX]>;
752 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
753 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
754 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
755 (bitconvert (memopv2i64 addr:$src))))]>,
756 TB, VEX, Requires<[HasAVX]>;
757 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
758 "cvtdq2ps\t{$src, $dst|$dst, $src}",
759 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
760 TB, Requires<[HasSSE2]>;
761 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
762 "cvtdq2ps\t{$src, $dst|$dst, $src}",
763 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
764 (bitconvert (memopv2i64 addr:$src))))]>,
765 TB, Requires<[HasSSE2]>;
767 // FIXME: why the non-intrinsic version is described as SSE3?
768 // SSE2 instructions with XS prefix
769 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
770 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
771 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
772 XS, VEX, Requires<[HasAVX]>;
773 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
774 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
775 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
776 (bitconvert (memopv2i64 addr:$src))))]>,
777 XS, VEX, Requires<[HasAVX]>;
778 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
779 "cvtdq2pd\t{$src, $dst|$dst, $src}",
780 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
781 XS, Requires<[HasSSE2]>;
782 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
783 "cvtdq2pd\t{$src, $dst|$dst, $src}",
784 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
785 (bitconvert (memopv2i64 addr:$src))))]>,
786 XS, Requires<[HasSSE2]>;
789 // Convert packed single/double fp to doubleword
790 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
791 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
792 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
793 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
794 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
795 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
796 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
797 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
798 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
799 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
800 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
801 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
803 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
804 "cvtps2dq\t{$src, $dst|$dst, $src}",
805 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
807 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
809 "cvtps2dq\t{$src, $dst|$dst, $src}",
810 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
811 (memop addr:$src)))]>, VEX;
812 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
813 "cvtps2dq\t{$src, $dst|$dst, $src}",
814 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
815 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
816 "cvtps2dq\t{$src, $dst|$dst, $src}",
817 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
818 (memop addr:$src)))]>;
820 // SSE2 packed instructions with XD prefix
821 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
822 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
823 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
824 XD, VEX, Requires<[HasAVX]>;
825 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
826 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
827 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
828 (memop addr:$src)))]>,
829 XD, VEX, Requires<[HasAVX]>;
830 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
831 "cvtpd2dq\t{$src, $dst|$dst, $src}",
832 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
833 XD, Requires<[HasSSE2]>;
834 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
835 "cvtpd2dq\t{$src, $dst|$dst, $src}",
836 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
837 (memop addr:$src)))]>,
838 XD, Requires<[HasSSE2]>;
841 // Convert with truncation packed single/double fp to doubleword
842 // SSE2 packed instructions with XS prefix
843 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
844 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
845 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
846 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
847 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
848 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
849 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
850 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
851 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
852 "cvttps2dq\t{$src, $dst|$dst, $src}",
854 (int_x86_sse2_cvttps2dq VR128:$src))]>;
855 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
856 "cvttps2dq\t{$src, $dst|$dst, $src}",
858 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
861 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
862 "vcvttps2dq\t{$src, $dst|$dst, $src}",
864 (int_x86_sse2_cvttps2dq VR128:$src))]>,
865 XS, VEX, Requires<[HasAVX]>;
866 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
867 "vcvttps2dq\t{$src, $dst|$dst, $src}",
868 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
869 (memop addr:$src)))]>,
870 XS, VEX, Requires<[HasAVX]>;
872 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
874 "cvttpd2dq\t{$src, $dst|$dst, $src}",
875 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
877 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
879 "cvttpd2dq\t{$src, $dst|$dst, $src}",
880 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
881 (memop addr:$src)))]>, VEX;
882 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
883 "cvttpd2dq\t{$src, $dst|$dst, $src}",
884 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
885 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
886 "cvttpd2dq\t{$src, $dst|$dst, $src}",
887 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
888 (memop addr:$src)))]>;
890 // The assembler can recognize rr 256-bit instructions by seeing a ymm
891 // register, but the same isn't true when using memory operands instead.
892 // Provide other assembly rr and rm forms to address this explicitly.
893 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
894 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
895 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
896 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
899 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
900 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
901 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
902 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
905 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
906 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
907 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
908 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
910 // Convert packed single to packed double
911 let Predicates = [HasAVX] in {
912 // SSE2 instructions without OpSize prefix
913 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
914 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
915 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
916 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
917 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
918 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
919 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
920 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
922 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
923 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
924 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
925 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
927 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
928 "vcvtps2pd\t{$src, $dst|$dst, $src}",
929 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
930 VEX, Requires<[HasAVX]>;
931 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
932 "vcvtps2pd\t{$src, $dst|$dst, $src}",
933 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
934 (load addr:$src)))]>,
935 VEX, Requires<[HasAVX]>;
936 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
937 "cvtps2pd\t{$src, $dst|$dst, $src}",
938 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
939 TB, Requires<[HasSSE2]>;
940 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
941 "cvtps2pd\t{$src, $dst|$dst, $src}",
942 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
943 (load addr:$src)))]>,
944 TB, Requires<[HasSSE2]>;
946 // Convert packed double to packed single
947 // The assembler can recognize rr 256-bit instructions by seeing a ymm
948 // register, but the same isn't true when using memory operands instead.
949 // Provide other assembly rr and rm forms to address this explicitly.
950 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
951 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
952 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
953 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
956 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
957 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
958 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
959 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
962 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
963 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
964 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
965 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
966 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
967 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
968 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
969 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
972 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
973 "cvtpd2ps\t{$src, $dst|$dst, $src}",
974 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
975 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
977 "cvtpd2ps\t{$src, $dst|$dst, $src}",
978 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
979 (memop addr:$src)))]>;
980 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
981 "cvtpd2ps\t{$src, $dst|$dst, $src}",
982 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
983 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
984 "cvtpd2ps\t{$src, $dst|$dst, $src}",
985 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
986 (memop addr:$src)))]>;
988 // AVX 256-bit register conversion intrinsics
989 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
990 // whenever possible to avoid declaring two versions of each one.
991 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
992 (VCVTDQ2PSYrr VR256:$src)>;
993 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
994 (VCVTDQ2PSYrm addr:$src)>;
996 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
997 (VCVTPD2PSYrr VR256:$src)>;
998 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
999 (VCVTPD2PSYrm addr:$src)>;
1001 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1002 (VCVTPS2DQYrr VR256:$src)>;
1003 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1004 (VCVTPS2DQYrm addr:$src)>;
1006 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1007 (VCVTPS2PDYrr VR128:$src)>;
1008 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1009 (VCVTPS2PDYrm addr:$src)>;
1011 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1012 (VCVTTPD2DQYrr VR256:$src)>;
1013 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1014 (VCVTTPD2DQYrm addr:$src)>;
1016 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1017 (VCVTTPS2DQYrr VR256:$src)>;
1018 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1019 (VCVTTPS2DQYrm addr:$src)>;
1021 //===----------------------------------------------------------------------===//
1022 // SSE 1 & 2 - Compare Instructions
1023 //===----------------------------------------------------------------------===//
1025 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1026 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1027 string asm, string asm_alt> {
1028 let isAsmParserOnly = 1 in {
1029 def rr : SIi8<0xC2, MRMSrcReg,
1030 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1033 def rm : SIi8<0xC2, MRMSrcMem,
1034 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1038 // Accept explicit immediate argument form instead of comparison code.
1039 def rr_alt : SIi8<0xC2, MRMSrcReg,
1040 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1043 def rm_alt : SIi8<0xC2, MRMSrcMem,
1044 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1048 let neverHasSideEffects = 1 in {
1049 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1050 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1051 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1053 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1054 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1055 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1059 let Constraints = "$src1 = $dst" in {
1060 def CMPSSrr : SIi8<0xC2, MRMSrcReg,
1061 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc),
1062 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1063 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2, imm:$cc))]>, XS;
1064 def CMPSSrm : SIi8<0xC2, MRMSrcMem,
1065 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc),
1066 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1067 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), (loadf32 addr:$src2), imm:$cc))]>, XS;
1068 def CMPSDrr : SIi8<0xC2, MRMSrcReg,
1069 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc),
1070 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1071 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2, imm:$cc))]>, XD;
1072 def CMPSDrm : SIi8<0xC2, MRMSrcMem,
1073 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc),
1074 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1075 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2), imm:$cc))]>, XD;
1077 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1078 def CMPSSrr_alt : SIi8<0xC2, MRMSrcReg,
1079 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
1080 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1081 def CMPSSrm_alt : SIi8<0xC2, MRMSrcMem,
1082 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
1083 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1084 def CMPSDrr_alt : SIi8<0xC2, MRMSrcReg,
1085 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
1086 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1087 def CMPSDrm_alt : SIi8<0xC2, MRMSrcMem,
1088 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
1089 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1092 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
1093 Intrinsic Int, string asm> {
1094 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1095 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1096 [(set VR128:$dst, (Int VR128:$src1,
1097 VR128:$src, imm:$cc))]>;
1098 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1099 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
1100 [(set VR128:$dst, (Int VR128:$src1,
1101 (load addr:$src), imm:$cc))]>;
1104 // Aliases to match intrinsics which expect XMM operand(s).
1105 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1106 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1108 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1109 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1111 let Constraints = "$src1 = $dst" in {
1112 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1113 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1114 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1115 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1119 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1120 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
1121 ValueType vt, X86MemOperand x86memop,
1122 PatFrag ld_frag, string OpcodeStr, Domain d> {
1123 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1124 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1125 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
1126 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
1127 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1128 [(set EFLAGS, (OpNode (vt RC:$src1),
1129 (ld_frag addr:$src2)))], d>;
1132 let Defs = [EFLAGS] in {
1133 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1134 "ucomiss", SSEPackedSingle>, VEX;
1135 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1136 "ucomisd", SSEPackedDouble>, OpSize, VEX;
1137 let Pattern = []<dag> in {
1138 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1139 "comiss", SSEPackedSingle>, VEX;
1140 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1141 "comisd", SSEPackedDouble>, OpSize, VEX;
1144 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1145 load, "ucomiss", SSEPackedSingle>, VEX;
1146 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1147 load, "ucomisd", SSEPackedDouble>, OpSize, VEX;
1149 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
1150 load, "comiss", SSEPackedSingle>, VEX;
1151 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
1152 load, "comisd", SSEPackedDouble>, OpSize, VEX;
1153 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1154 "ucomiss", SSEPackedSingle>, TB;
1155 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1156 "ucomisd", SSEPackedDouble>, TB, OpSize;
1158 let Pattern = []<dag> in {
1159 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1160 "comiss", SSEPackedSingle>, TB;
1161 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1162 "comisd", SSEPackedDouble>, TB, OpSize;
1165 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1166 load, "ucomiss", SSEPackedSingle>, TB;
1167 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1168 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
1170 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
1171 "comiss", SSEPackedSingle>, TB;
1172 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
1173 "comisd", SSEPackedDouble>, TB, OpSize;
1174 } // Defs = [EFLAGS]
1176 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
1177 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
1178 Intrinsic Int, string asm, string asm_alt,
1180 let isAsmParserOnly = 1 in {
1181 def rri : PIi8<0xC2, MRMSrcReg,
1182 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1183 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1184 def rmi : PIi8<0xC2, MRMSrcMem,
1185 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1186 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1189 // Accept explicit immediate argument form instead of comparison code.
1190 def rri_alt : PIi8<0xC2, MRMSrcReg,
1191 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1193 def rmi_alt : PIi8<0xC2, MRMSrcMem,
1194 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1198 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1199 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1200 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1201 SSEPackedSingle>, VEX_4V;
1202 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1203 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1204 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1205 SSEPackedDouble>, OpSize, VEX_4V;
1206 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
1207 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1208 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1209 SSEPackedSingle>, VEX_4V;
1210 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
1211 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1212 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1213 SSEPackedDouble>, OpSize, VEX_4V;
1214 let Constraints = "$src1 = $dst" in {
1215 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1216 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1217 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1218 SSEPackedSingle>, TB;
1219 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1220 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1221 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1222 SSEPackedDouble>, TB, OpSize;
1225 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1226 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1227 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1228 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1229 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1230 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1231 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1232 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1234 //===----------------------------------------------------------------------===//
1235 // SSE 1 & 2 - Shuffle Instructions
1236 //===----------------------------------------------------------------------===//
1238 /// sse12_shuffle - sse 1 & 2 shuffle instructions
1239 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
1240 ValueType vt, string asm, PatFrag mem_frag,
1241 Domain d, bit IsConvertibleToThreeAddress = 0> {
1242 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
1243 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
1244 [(set RC:$dst, (vt (shufp:$src3
1245 RC:$src1, (mem_frag addr:$src2))))], d>;
1246 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
1247 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
1248 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
1250 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
1253 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1254 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1255 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
1256 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
1257 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1258 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
1259 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1260 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1261 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1262 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
1263 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1264 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1266 let Constraints = "$src1 = $dst" in {
1267 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1268 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1269 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
1271 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1272 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1273 memopv2f64, SSEPackedDouble>, TB, OpSize;
1276 //===----------------------------------------------------------------------===//
1277 // SSE 1 & 2 - Unpack Instructions
1278 //===----------------------------------------------------------------------===//
1280 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
1281 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
1282 PatFrag mem_frag, RegisterClass RC,
1283 X86MemOperand x86memop, string asm,
1285 def rr : PI<opc, MRMSrcReg,
1286 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1288 (vt (OpNode RC:$src1, RC:$src2)))], d>;
1289 def rm : PI<opc, MRMSrcMem,
1290 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1292 (vt (OpNode RC:$src1,
1293 (mem_frag addr:$src2))))], d>;
1296 let AddedComplexity = 10 in {
1297 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1298 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1299 SSEPackedSingle>, VEX_4V;
1300 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1301 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1302 SSEPackedDouble>, OpSize, VEX_4V;
1303 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1304 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1305 SSEPackedSingle>, VEX_4V;
1306 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1307 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1308 SSEPackedDouble>, OpSize, VEX_4V;
1310 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
1311 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1312 SSEPackedSingle>, VEX_4V;
1313 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
1314 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1315 SSEPackedDouble>, OpSize, VEX_4V;
1316 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
1317 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1318 SSEPackedSingle>, VEX_4V;
1319 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
1320 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1321 SSEPackedDouble>, OpSize, VEX_4V;
1323 let Constraints = "$src1 = $dst" in {
1324 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1325 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1326 SSEPackedSingle>, TB;
1327 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1328 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1329 SSEPackedDouble>, TB, OpSize;
1330 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1331 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1332 SSEPackedSingle>, TB;
1333 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1334 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1335 SSEPackedDouble>, TB, OpSize;
1336 } // Constraints = "$src1 = $dst"
1337 } // AddedComplexity
1339 //===----------------------------------------------------------------------===//
1340 // SSE 1 & 2 - Extract Floating-Point Sign mask
1341 //===----------------------------------------------------------------------===//
1343 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
1344 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
1346 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
1347 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1348 [(set GR32:$dst, (Int RC:$src))], d>;
1349 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
1350 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
1354 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
1355 "movmskps", SSEPackedSingle>, VEX;
1356 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
1357 "movmskpd", SSEPackedDouble>, OpSize,
1359 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
1360 "movmskps", SSEPackedSingle>, VEX;
1361 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
1362 "movmskpd", SSEPackedDouble>, OpSize,
1364 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
1365 SSEPackedSingle>, TB;
1366 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
1367 SSEPackedDouble>, TB, OpSize;
1370 def MOVMSKPDrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1371 "movmskpd\t{$src, $dst|$dst, $src}",
1372 [(set GR32:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB, OpSize;
1373 def MOVMSKPDrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1374 "movmskpd\t{$src, $dst|$dst, $src}",
1375 [(set GR64:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB, OpSize;
1376 def MOVMSKPSrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
1377 "movmskps\t{$src, $dst|$dst, $src}",
1378 [(set GR32:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
1379 def MOVMSKPSrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1380 "movmskps\t{$src, $dst|$dst, $src}",
1381 [(set GR64:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
1384 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1385 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1386 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1387 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1389 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1390 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1391 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1392 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1395 //===----------------------------------------------------------------------===//
1396 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
1397 //===----------------------------------------------------------------------===//
1399 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
1400 // names that start with 'Fs'.
1402 // Alias instructions that map fld0 to pxor for sse.
1403 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1404 canFoldAsLoad = 1 in {
1405 // FIXME: Set encoding to pseudo!
1406 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1407 [(set FR32:$dst, fp32imm0)]>,
1408 Requires<[HasSSE1]>, TB, OpSize;
1409 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1410 [(set FR64:$dst, fpimm0)]>,
1411 Requires<[HasSSE2]>, TB, OpSize;
1412 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1413 [(set FR32:$dst, fp32imm0)]>,
1414 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1415 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1416 [(set FR64:$dst, fpimm0)]>,
1417 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1420 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1421 // bits are disregarded.
1422 let neverHasSideEffects = 1 in {
1423 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1424 "movaps\t{$src, $dst|$dst, $src}", []>;
1425 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1426 "movapd\t{$src, $dst|$dst, $src}", []>;
1429 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1430 // bits are disregarded.
1431 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1432 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1433 "movaps\t{$src, $dst|$dst, $src}",
1434 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
1435 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1436 "movapd\t{$src, $dst|$dst, $src}",
1437 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1440 //===----------------------------------------------------------------------===//
1441 // SSE 1 & 2 - Logical Instructions
1442 //===----------------------------------------------------------------------===//
1444 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
1446 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
1448 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
1449 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, VEX_4V;
1451 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
1452 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, OpSize, VEX_4V;
1454 let Constraints = "$src1 = $dst" in {
1455 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
1456 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
1458 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
1459 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
1463 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1464 let mayLoad = 0 in {
1465 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
1466 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
1467 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
1470 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
1471 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
1473 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
1475 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
1476 SDNode OpNode, int HasPat = 0,
1477 list<list<dag>> Pattern = []> {
1478 let Pattern = []<dag> in {
1479 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1480 !strconcat(OpcodeStr, "ps"), f128mem,
1481 !if(HasPat, Pattern[0], // rr
1482 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1484 !if(HasPat, Pattern[2], // rm
1485 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1486 (memopv2i64 addr:$src2)))]), 0>,
1489 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1490 !strconcat(OpcodeStr, "pd"), f128mem,
1491 !if(HasPat, Pattern[1], // rr
1492 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1495 !if(HasPat, Pattern[3], // rm
1496 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1497 (memopv2i64 addr:$src2)))]), 0>,
1500 let Constraints = "$src1 = $dst" in {
1501 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1502 !strconcat(OpcodeStr, "ps"), f128mem,
1503 !if(HasPat, Pattern[0], // rr
1504 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1506 !if(HasPat, Pattern[2], // rm
1507 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1508 (memopv2i64 addr:$src2)))])>, TB;
1510 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1511 !strconcat(OpcodeStr, "pd"), f128mem,
1512 !if(HasPat, Pattern[1], // rr
1513 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1516 !if(HasPat, Pattern[3], // rm
1517 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1518 (memopv2i64 addr:$src2)))])>,
1523 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
1525 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr> {
1526 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
1527 !strconcat(OpcodeStr, "ps"), f256mem, [], [], 0>, VEX_4V;
1529 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
1530 !strconcat(OpcodeStr, "pd"), f256mem, [], [], 0>, OpSize, VEX_4V;
1533 // AVX 256-bit packed logical ops forms
1534 defm VAND : sse12_fp_packed_logical_y<0x54, "and">;
1535 defm VOR : sse12_fp_packed_logical_y<0x56, "or">;
1536 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor">;
1537 let isCommutable = 0 in
1538 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn">;
1540 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
1541 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
1542 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
1543 let isCommutable = 0 in
1544 defm ANDN : sse12_fp_packed_logical<0x55, "andn", undef /* dummy */, 1, [
1546 [(set VR128:$dst, (X86pandn VR128:$src1, VR128:$src2))],
1550 [(set VR128:$dst, (X86pandn VR128:$src1, (memopv2i64 addr:$src2)))],
1554 //===----------------------------------------------------------------------===//
1555 // SSE 1 & 2 - Arithmetic Instructions
1556 //===----------------------------------------------------------------------===//
1558 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
1561 /// In addition, we also have a special variant of the scalar form here to
1562 /// represent the associated intrinsic operation. This form is unlike the
1563 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1564 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1566 /// These three forms can each be reg+reg or reg+mem.
1569 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
1571 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1573 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
1574 OpNode, FR32, f32mem, Is2Addr>, XS;
1575 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
1576 OpNode, FR64, f64mem, Is2Addr>, XD;
1579 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
1581 let mayLoad = 0 in {
1582 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
1583 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
1584 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
1585 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
1589 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
1591 let mayLoad = 0 in {
1592 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
1593 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
1594 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
1595 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
1599 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
1601 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1602 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
1603 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1604 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
1607 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
1609 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1610 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
1611 SSEPackedSingle, Is2Addr>, TB;
1613 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1614 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
1615 SSEPackedDouble, Is2Addr>, TB, OpSize;
1618 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
1619 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1620 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
1621 SSEPackedSingle, 0>, TB;
1623 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1624 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
1625 SSEPackedDouble, 0>, TB, OpSize;
1628 // Binary Arithmetic instructions
1629 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
1630 basic_sse12_fp_binop_s_int<0x58, "add", 0>,
1631 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
1632 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
1633 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
1634 basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
1635 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
1636 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
1638 let isCommutable = 0 in {
1639 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
1640 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
1641 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
1642 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
1643 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
1644 basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
1645 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
1646 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
1647 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
1648 basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
1649 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
1650 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
1651 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
1652 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
1653 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
1654 basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
1655 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
1656 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
1657 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
1658 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
1661 let Constraints = "$src1 = $dst" in {
1662 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
1663 basic_sse12_fp_binop_p<0x58, "add", fadd>,
1664 basic_sse12_fp_binop_s_int<0x58, "add">;
1665 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
1666 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
1667 basic_sse12_fp_binop_s_int<0x59, "mul">;
1669 let isCommutable = 0 in {
1670 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
1671 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
1672 basic_sse12_fp_binop_s_int<0x5C, "sub">;
1673 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
1674 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
1675 basic_sse12_fp_binop_s_int<0x5E, "div">;
1676 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
1677 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
1678 basic_sse12_fp_binop_s_int<0x5F, "max">,
1679 basic_sse12_fp_binop_p_int<0x5F, "max">;
1680 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
1681 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
1682 basic_sse12_fp_binop_s_int<0x5D, "min">,
1683 basic_sse12_fp_binop_p_int<0x5D, "min">;
1688 /// In addition, we also have a special variant of the scalar form here to
1689 /// represent the associated intrinsic operation. This form is unlike the
1690 /// plain scalar form, in that it takes an entire vector (instead of a
1691 /// scalar) and leaves the top elements undefined.
1693 /// And, we have a special variant form for a full-vector intrinsic form.
1695 /// sse1_fp_unop_s - SSE1 unops in scalar form.
1696 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
1697 SDNode OpNode, Intrinsic F32Int> {
1698 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1699 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1700 [(set FR32:$dst, (OpNode FR32:$src))]>;
1701 // For scalar unary operations, fold a load into the operation
1702 // only in OptForSize mode. It eliminates an instruction, but it also
1703 // eliminates a whole-register clobber (the load), so it introduces a
1704 // partial register update condition.
1705 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1706 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1707 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1708 Requires<[HasSSE1, OptForSize]>;
1709 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1710 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1711 [(set VR128:$dst, (F32Int VR128:$src))]>;
1712 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1713 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1714 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1717 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
1718 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1719 SDNode OpNode, Intrinsic F32Int> {
1720 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
1721 !strconcat(OpcodeStr,
1722 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1723 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
1724 !strconcat(OpcodeStr,
1725 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1726 []>, XS, Requires<[HasAVX, OptForSize]>;
1727 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1728 !strconcat(OpcodeStr,
1729 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1730 [(set VR128:$dst, (F32Int VR128:$src))]>;
1731 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1732 !strconcat(OpcodeStr,
1733 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1734 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1737 /// sse1_fp_unop_p - SSE1 unops in packed form.
1738 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1739 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1740 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1741 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
1742 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1743 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1744 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1747 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
1748 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1749 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1750 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1751 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
1752 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1753 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1754 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
1757 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
1758 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1759 Intrinsic V4F32Int> {
1760 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1761 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1762 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
1763 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1764 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1765 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1768 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
1769 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1770 Intrinsic V4F32Int> {
1771 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1772 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1773 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
1774 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1775 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1776 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
1779 /// sse2_fp_unop_s - SSE2 unops in scalar form.
1780 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
1781 SDNode OpNode, Intrinsic F64Int> {
1782 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1783 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1784 [(set FR64:$dst, (OpNode FR64:$src))]>;
1785 // See the comments in sse1_fp_unop_s for why this is OptForSize.
1786 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1787 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1788 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
1789 Requires<[HasSSE2, OptForSize]>;
1790 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1791 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1792 [(set VR128:$dst, (F64Int VR128:$src))]>;
1793 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1794 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1795 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1798 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
1799 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1800 SDNode OpNode, Intrinsic F64Int> {
1801 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1802 !strconcat(OpcodeStr,
1803 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1804 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1805 (ins FR64:$src1, f64mem:$src2),
1806 !strconcat(OpcodeStr,
1807 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1808 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1809 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1810 [(set VR128:$dst, (F64Int VR128:$src))]>;
1811 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1812 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1813 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1816 /// sse2_fp_unop_p - SSE2 unops in vector forms.
1817 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
1819 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1820 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1821 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
1822 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1823 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1824 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1827 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
1828 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1829 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1830 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1831 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
1832 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1833 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1834 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
1837 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
1838 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1839 Intrinsic V2F64Int> {
1840 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1841 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1842 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
1843 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1844 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1845 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1848 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
1849 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1850 Intrinsic V2F64Int> {
1851 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1852 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1853 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
1854 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1855 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1856 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
1859 let Predicates = [HasAVX] in {
1861 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ss>,
1862 sse2_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1865 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
1866 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
1867 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1868 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1869 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
1870 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
1871 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
1872 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
1875 // Reciprocal approximations. Note that these typically require refinement
1876 // in order to obtain suitable precision.
1877 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt", X86frsqrt,
1878 int_x86_sse_rsqrt_ss>, VEX_4V;
1879 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
1880 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
1881 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
1882 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
1884 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ss>,
1886 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
1887 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
1888 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
1889 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
1893 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
1894 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
1895 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
1896 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1897 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
1898 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
1900 // Reciprocal approximations. Note that these typically require refinement
1901 // in order to obtain suitable precision.
1902 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
1903 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
1904 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
1905 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
1906 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
1907 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
1909 // There is no f64 version of the reciprocal approximation instructions.
1911 //===----------------------------------------------------------------------===//
1912 // SSE 1 & 2 - Non-temporal stores
1913 //===----------------------------------------------------------------------===//
1915 let AddedComplexity = 400 in { // Prefer non-temporal versions
1916 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
1917 (ins f128mem:$dst, VR128:$src),
1918 "movntps\t{$src, $dst|$dst, $src}",
1919 [(alignednontemporalstore (v4f32 VR128:$src),
1921 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
1922 (ins f128mem:$dst, VR128:$src),
1923 "movntpd\t{$src, $dst|$dst, $src}",
1924 [(alignednontemporalstore (v2f64 VR128:$src),
1926 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
1927 (ins f128mem:$dst, VR128:$src),
1928 "movntdq\t{$src, $dst|$dst, $src}",
1929 [(alignednontemporalstore (v2f64 VR128:$src),
1932 let ExeDomain = SSEPackedInt in
1933 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
1934 (ins f128mem:$dst, VR128:$src),
1935 "movntdq\t{$src, $dst|$dst, $src}",
1936 [(alignednontemporalstore (v4f32 VR128:$src),
1939 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
1940 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
1942 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
1943 (ins f256mem:$dst, VR256:$src),
1944 "movntps\t{$src, $dst|$dst, $src}",
1945 [(alignednontemporalstore (v8f32 VR256:$src),
1947 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
1948 (ins f256mem:$dst, VR256:$src),
1949 "movntpd\t{$src, $dst|$dst, $src}",
1950 [(alignednontemporalstore (v4f64 VR256:$src),
1952 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
1953 (ins f256mem:$dst, VR256:$src),
1954 "movntdq\t{$src, $dst|$dst, $src}",
1955 [(alignednontemporalstore (v4f64 VR256:$src),
1957 let ExeDomain = SSEPackedInt in
1958 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
1959 (ins f256mem:$dst, VR256:$src),
1960 "movntdq\t{$src, $dst|$dst, $src}",
1961 [(alignednontemporalstore (v8f32 VR256:$src),
1965 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
1966 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
1967 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
1968 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
1969 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
1970 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
1972 let AddedComplexity = 400 in { // Prefer non-temporal versions
1973 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1974 "movntps\t{$src, $dst|$dst, $src}",
1975 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1976 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1977 "movntpd\t{$src, $dst|$dst, $src}",
1978 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
1980 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1981 "movntdq\t{$src, $dst|$dst, $src}",
1982 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
1984 let ExeDomain = SSEPackedInt in
1985 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1986 "movntdq\t{$src, $dst|$dst, $src}",
1987 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1989 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
1990 (MOVNTDQmr addr:$dst, VR128:$src)>;
1992 // There is no AVX form for instructions below this point
1993 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1994 "movnti\t{$src, $dst|$dst, $src}",
1995 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
1996 TB, Requires<[HasSSE2]>;
1997 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1998 "movnti\t{$src, $dst|$dst, $src}",
1999 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
2000 TB, Requires<[HasSSE2]>;
2003 //===----------------------------------------------------------------------===//
2004 // SSE 1 & 2 - Misc Instructions (No AVX form)
2005 //===----------------------------------------------------------------------===//
2007 // Prefetch intrinsic.
2008 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
2009 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
2010 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
2011 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
2012 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
2013 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
2014 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
2015 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
2017 // Load, store, and memory fence
2018 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
2019 TB, Requires<[HasSSE1]>;
2020 def : Pat<(X86SFence), (SFENCE)>;
2022 // Alias instructions that map zero vector to pxor / xorp* for sse.
2023 // We set canFoldAsLoad because this can be converted to a constant-pool
2024 // load of an all-zeros value if folding it would be beneficial.
2025 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
2026 // JIT implementation, it does not expand the instructions below like
2027 // X86MCInstLower does.
2028 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2029 isCodeGenOnly = 1 in {
2030 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2031 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2032 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2033 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
2034 let ExeDomain = SSEPackedInt in
2035 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2036 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2039 // The same as done above but for AVX. The 128-bit versions are the
2040 // same, but re-encoded. The 256-bit does not support PI version.
2041 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
2042 // JIT implementatioan, it does not expand the instructions below like
2043 // X86MCInstLower does.
2044 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2045 isCodeGenOnly = 1, Predicates = [HasAVX] in {
2046 def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2047 [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V;
2048 def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2049 [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V;
2050 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2051 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
2052 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2053 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
2054 let ExeDomain = SSEPackedInt in
2055 def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2056 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2059 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
2060 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
2061 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
2063 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2064 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
2066 // FIXME: According to the intel manual, DEST[127:64] <- SRC1[127:64], while
2067 // in the non-AVX version bits 127:64 aren't touched. Find a better way to
2068 // represent this instead of always zeroing SRC1. One possible solution is
2069 // to represent the instruction w/ something similar as the "$src1 = $dst"
2070 // constraint but without the tied operands.
2071 def : Pat<(extloadf32 addr:$src),
2072 (VCVTSS2SDrm (f32 (EXTRACT_SUBREG (AVX_SET0PS), sub_ss)), addr:$src)>,
2073 Requires<[HasAVX, OptForSpeed]>;
2075 //===----------------------------------------------------------------------===//
2076 // SSE 1 & 2 - Load/Store XCSR register
2077 //===----------------------------------------------------------------------===//
2079 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2080 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
2081 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2082 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
2084 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2085 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
2086 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2087 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
2089 //===---------------------------------------------------------------------===//
2090 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
2091 //===---------------------------------------------------------------------===//
2093 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2095 let neverHasSideEffects = 1 in {
2096 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2097 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2098 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2099 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2101 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2102 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2103 def VMOVDQUYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2104 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2106 let canFoldAsLoad = 1, mayLoad = 1 in {
2107 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2108 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2109 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2110 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2111 let Predicates = [HasAVX] in {
2112 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2113 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2114 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2115 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2119 let mayStore = 1 in {
2120 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
2121 (ins i128mem:$dst, VR128:$src),
2122 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2123 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
2124 (ins i256mem:$dst, VR256:$src),
2125 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2126 let Predicates = [HasAVX] in {
2127 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2128 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2129 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
2130 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2134 let neverHasSideEffects = 1 in
2135 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2136 "movdqa\t{$src, $dst|$dst, $src}", []>;
2138 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2139 "movdqu\t{$src, $dst|$dst, $src}",
2140 []>, XS, Requires<[HasSSE2]>;
2142 let canFoldAsLoad = 1, mayLoad = 1 in {
2143 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2144 "movdqa\t{$src, $dst|$dst, $src}",
2145 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
2146 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2147 "movdqu\t{$src, $dst|$dst, $src}",
2148 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2149 XS, Requires<[HasSSE2]>;
2152 let mayStore = 1 in {
2153 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2154 "movdqa\t{$src, $dst|$dst, $src}",
2155 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
2156 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2157 "movdqu\t{$src, $dst|$dst, $src}",
2158 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2159 XS, Requires<[HasSSE2]>;
2162 // Intrinsic forms of MOVDQU load and store
2163 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2164 "vmovdqu\t{$src, $dst|$dst, $src}",
2165 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2166 XS, VEX, Requires<[HasAVX]>;
2168 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2169 "movdqu\t{$src, $dst|$dst, $src}",
2170 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2171 XS, Requires<[HasSSE2]>;
2173 } // ExeDomain = SSEPackedInt
2175 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
2176 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
2177 (VMOVDQUYmr addr:$dst, VR256:$src)>;
2179 //===---------------------------------------------------------------------===//
2180 // SSE2 - Packed Integer Arithmetic Instructions
2181 //===---------------------------------------------------------------------===//
2183 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2185 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2186 bit IsCommutable = 0, bit Is2Addr = 1> {
2187 let isCommutable = IsCommutable in
2188 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2189 (ins VR128:$src1, VR128:$src2),
2191 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2192 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2193 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2194 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2195 (ins VR128:$src1, i128mem:$src2),
2197 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2198 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2199 [(set VR128:$dst, (IntId VR128:$src1,
2200 (bitconvert (memopv2i64 addr:$src2))))]>;
2203 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2204 string OpcodeStr, Intrinsic IntId,
2205 Intrinsic IntId2, bit Is2Addr = 1> {
2206 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2207 (ins VR128:$src1, VR128:$src2),
2209 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2210 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2211 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2212 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2213 (ins VR128:$src1, i128mem:$src2),
2215 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2216 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2217 [(set VR128:$dst, (IntId VR128:$src1,
2218 (bitconvert (memopv2i64 addr:$src2))))]>;
2219 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2220 (ins VR128:$src1, i32i8imm:$src2),
2222 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2223 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2224 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2227 /// PDI_binop_rm - Simple SSE2 binary operator.
2228 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2229 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
2230 let isCommutable = IsCommutable in
2231 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2232 (ins VR128:$src1, VR128:$src2),
2234 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2235 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2236 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2237 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2238 (ins VR128:$src1, i128mem:$src2),
2240 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2241 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2242 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2243 (bitconvert (memopv2i64 addr:$src2)))))]>;
2246 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2248 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2249 /// to collapse (bitconvert VT to VT) into its operand.
2251 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2252 bit IsCommutable = 0, bit Is2Addr = 1> {
2253 let isCommutable = IsCommutable in
2254 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2255 (ins VR128:$src1, VR128:$src2),
2257 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2258 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2259 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
2260 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2261 (ins VR128:$src1, i128mem:$src2),
2263 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2264 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2265 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
2268 } // ExeDomain = SSEPackedInt
2270 // 128-bit Integer Arithmetic
2272 let Predicates = [HasAVX] in {
2273 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
2274 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
2275 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
2276 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
2277 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
2278 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
2279 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
2280 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
2281 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
2284 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
2286 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
2288 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
2290 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
2292 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
2294 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
2296 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
2298 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
2300 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
2302 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
2304 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
2306 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
2308 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
2310 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
2312 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
2314 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
2316 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
2318 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
2320 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
2324 let Constraints = "$src1 = $dst" in {
2325 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2326 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2327 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2328 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2329 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2330 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2331 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2332 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2333 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2336 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2337 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2338 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2339 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2340 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2341 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2342 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2343 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2344 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2345 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
2346 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2347 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2348 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2349 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2350 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2351 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2352 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2353 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2354 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2356 } // Constraints = "$src1 = $dst"
2358 //===---------------------------------------------------------------------===//
2359 // SSE2 - Packed Integer Logical Instructions
2360 //===---------------------------------------------------------------------===//
2362 let Predicates = [HasAVX] in {
2363 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
2364 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
2366 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
2367 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
2369 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
2370 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
2373 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
2374 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
2376 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
2377 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
2379 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
2380 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
2383 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
2384 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
2386 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
2387 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
2390 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
2391 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
2392 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
2394 let ExeDomain = SSEPackedInt in {
2395 let neverHasSideEffects = 1 in {
2396 // 128-bit logical shifts.
2397 def VPSLLDQri : PDIi8<0x73, MRM7r,
2398 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2399 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2401 def VPSRLDQri : PDIi8<0x73, MRM3r,
2402 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2403 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2405 // PSRADQri doesn't exist in SSE[1-3].
2407 def VPANDNrr : PDI<0xDF, MRMSrcReg,
2408 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2409 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2410 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2411 VR128:$src2)))]>, VEX_4V;
2413 def VPANDNrm : PDI<0xDF, MRMSrcMem,
2414 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2415 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2416 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2417 (memopv2i64 addr:$src2))))]>,
2422 let Constraints = "$src1 = $dst" in {
2423 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2424 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2425 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2426 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2427 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2428 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2430 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2431 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2432 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2433 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2434 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2435 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2437 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2438 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2439 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2440 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2442 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2443 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
2444 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2446 let ExeDomain = SSEPackedInt in {
2447 let neverHasSideEffects = 1 in {
2448 // 128-bit logical shifts.
2449 def PSLLDQri : PDIi8<0x73, MRM7r,
2450 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2451 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2452 def PSRLDQri : PDIi8<0x73, MRM3r,
2453 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2454 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2455 // PSRADQri doesn't exist in SSE[1-3].
2457 def PANDNrr : PDI<0xDF, MRMSrcReg,
2458 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2459 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2461 def PANDNrm : PDI<0xDF, MRMSrcMem,
2462 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2463 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2465 } // Constraints = "$src1 = $dst"
2467 let Predicates = [HasAVX] in {
2468 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2469 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2470 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2471 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2472 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2473 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
2474 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2475 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
2476 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2477 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2479 // Shift up / down and insert zero's.
2480 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2481 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2482 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2483 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2486 let Predicates = [HasSSE2] in {
2487 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2488 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2489 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2490 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2491 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2492 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2493 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2494 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2495 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2496 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2498 // Shift up / down and insert zero's.
2499 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2500 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2501 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2502 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2505 //===---------------------------------------------------------------------===//
2506 // SSE2 - Packed Integer Comparison Instructions
2507 //===---------------------------------------------------------------------===//
2509 let Predicates = [HasAVX] in {
2510 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
2512 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
2514 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
2516 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
2518 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
2520 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
2524 let Constraints = "$src1 = $dst" in {
2525 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
2526 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
2527 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
2528 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2529 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2530 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2531 } // Constraints = "$src1 = $dst"
2533 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2534 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2535 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2536 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2537 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2538 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2539 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2540 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2541 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2542 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2543 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2544 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2546 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2547 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2548 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2549 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2550 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2551 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2552 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2553 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2554 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2555 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2556 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2557 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2559 //===---------------------------------------------------------------------===//
2560 // SSE2 - Packed Integer Pack Instructions
2561 //===---------------------------------------------------------------------===//
2563 let Predicates = [HasAVX] in {
2564 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
2566 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
2568 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
2572 let Constraints = "$src1 = $dst" in {
2573 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2574 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2575 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2576 } // Constraints = "$src1 = $dst"
2578 //===---------------------------------------------------------------------===//
2579 // SSE2 - Packed Integer Shuffle Instructions
2580 //===---------------------------------------------------------------------===//
2582 let ExeDomain = SSEPackedInt in {
2583 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
2585 def ri : Ii8<0x70, MRMSrcReg,
2586 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2587 !strconcat(OpcodeStr,
2588 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2589 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
2591 def mi : Ii8<0x70, MRMSrcMem,
2592 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2593 !strconcat(OpcodeStr,
2594 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2595 [(set VR128:$dst, (vt (pshuf_frag:$src2
2596 (bc_frag (memopv2i64 addr:$src1)),
2599 } // ExeDomain = SSEPackedInt
2601 let Predicates = [HasAVX] in {
2602 let AddedComplexity = 5 in
2603 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize,
2606 // SSE2 with ImmT == Imm8 and XS prefix.
2607 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
2610 // SSE2 with ImmT == Imm8 and XD prefix.
2611 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
2615 let Predicates = [HasSSE2] in {
2616 let AddedComplexity = 5 in
2617 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
2619 // SSE2 with ImmT == Imm8 and XS prefix.
2620 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
2622 // SSE2 with ImmT == Imm8 and XD prefix.
2623 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
2626 //===---------------------------------------------------------------------===//
2627 // SSE2 - Packed Integer Unpack Instructions
2628 //===---------------------------------------------------------------------===//
2630 let ExeDomain = SSEPackedInt in {
2631 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2632 PatFrag unp_frag, PatFrag bc_frag, bit Is2Addr = 1> {
2633 def rr : PDI<opc, MRMSrcReg,
2634 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2636 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2637 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2638 [(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
2639 def rm : PDI<opc, MRMSrcMem,
2640 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2642 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2643 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2644 [(set VR128:$dst, (unp_frag VR128:$src1,
2645 (bc_frag (memopv2i64
2649 let Predicates = [HasAVX] in {
2650 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, unpckl, bc_v16i8,
2652 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, unpckl, bc_v8i16,
2654 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, unpckl, bc_v4i32,
2657 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2658 /// knew to collapse (bitconvert VT to VT) into its operand.
2659 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2660 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2661 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2663 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>, VEX_4V;
2664 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2665 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2666 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2668 (v2i64 (unpckl VR128:$src1,
2669 (memopv2i64 addr:$src2))))]>, VEX_4V;
2671 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, unpckh, bc_v16i8,
2673 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, unpckh, bc_v8i16,
2675 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, unpckh, bc_v4i32,
2678 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2679 /// knew to collapse (bitconvert VT to VT) into its operand.
2680 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2681 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2682 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2684 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>, VEX_4V;
2685 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2686 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2687 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2689 (v2i64 (unpckh VR128:$src1,
2690 (memopv2i64 addr:$src2))))]>, VEX_4V;
2693 let Constraints = "$src1 = $dst" in {
2694 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, unpckl, bc_v16i8>;
2695 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, unpckl, bc_v8i16>;
2696 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, unpckl, bc_v4i32>;
2698 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2699 /// knew to collapse (bitconvert VT to VT) into its operand.
2700 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2701 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2702 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2704 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2705 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2706 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2707 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2709 (v2i64 (unpckl VR128:$src1,
2710 (memopv2i64 addr:$src2))))]>;
2712 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, unpckh, bc_v16i8>;
2713 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, unpckh, bc_v8i16>;
2714 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, unpckh, bc_v4i32>;
2716 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2717 /// knew to collapse (bitconvert VT to VT) into its operand.
2718 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2719 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2720 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2722 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2723 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2724 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2725 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2727 (v2i64 (unpckh VR128:$src1,
2728 (memopv2i64 addr:$src2))))]>;
2731 } // ExeDomain = SSEPackedInt
2733 //===---------------------------------------------------------------------===//
2734 // SSE2 - Packed Integer Extract and Insert
2735 //===---------------------------------------------------------------------===//
2737 let ExeDomain = SSEPackedInt in {
2738 multiclass sse2_pinsrw<bit Is2Addr = 1> {
2739 def rri : Ii8<0xC4, MRMSrcReg,
2740 (outs VR128:$dst), (ins VR128:$src1,
2741 GR32:$src2, i32i8imm:$src3),
2743 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2744 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2746 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2747 def rmi : Ii8<0xC4, MRMSrcMem,
2748 (outs VR128:$dst), (ins VR128:$src1,
2749 i16mem:$src2, i32i8imm:$src3),
2751 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2752 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2754 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2759 let Predicates = [HasAVX] in
2760 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
2761 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2762 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2763 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2764 imm:$src2))]>, OpSize, VEX;
2765 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2766 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2767 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2768 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2772 let Predicates = [HasAVX] in {
2773 defm VPINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
2774 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
2775 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2776 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2777 []>, OpSize, VEX_4V;
2780 let Constraints = "$src1 = $dst" in
2781 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
2783 } // ExeDomain = SSEPackedInt
2785 //===---------------------------------------------------------------------===//
2786 // SSE2 - Packed Mask Creation
2787 //===---------------------------------------------------------------------===//
2789 let ExeDomain = SSEPackedInt in {
2791 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2792 "pmovmskb\t{$src, $dst|$dst, $src}",
2793 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
2794 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2795 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
2796 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2797 "pmovmskb\t{$src, $dst|$dst, $src}",
2798 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2800 } // ExeDomain = SSEPackedInt
2802 //===---------------------------------------------------------------------===//
2803 // SSE2 - Conditional Store
2804 //===---------------------------------------------------------------------===//
2806 let ExeDomain = SSEPackedInt in {
2809 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
2810 (ins VR128:$src, VR128:$mask),
2811 "maskmovdqu\t{$mask, $src|$src, $mask}",
2812 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
2814 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
2815 (ins VR128:$src, VR128:$mask),
2816 "maskmovdqu\t{$mask, $src|$src, $mask}",
2817 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
2820 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2821 "maskmovdqu\t{$mask, $src|$src, $mask}",
2822 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2824 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2825 "maskmovdqu\t{$mask, $src|$src, $mask}",
2826 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2828 } // ExeDomain = SSEPackedInt
2830 //===---------------------------------------------------------------------===//
2831 // SSE2 - Move Doubleword
2832 //===---------------------------------------------------------------------===//
2834 // Move Int Doubleword to Packed Double Int
2835 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2836 "movd\t{$src, $dst|$dst, $src}",
2838 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
2839 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2840 "movd\t{$src, $dst|$dst, $src}",
2842 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
2844 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2845 "movd\t{$src, $dst|$dst, $src}",
2847 (v4i32 (scalar_to_vector GR32:$src)))]>;
2848 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2849 "movd\t{$src, $dst|$dst, $src}",
2851 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2852 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2853 "mov{d|q}\t{$src, $dst|$dst, $src}",
2855 (v2i64 (scalar_to_vector GR64:$src)))]>;
2856 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2857 "mov{d|q}\t{$src, $dst|$dst, $src}",
2858 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2861 // Move Int Doubleword to Single Scalar
2862 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2863 "movd\t{$src, $dst|$dst, $src}",
2864 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
2866 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2867 "movd\t{$src, $dst|$dst, $src}",
2868 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
2870 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2871 "movd\t{$src, $dst|$dst, $src}",
2872 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2874 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2875 "movd\t{$src, $dst|$dst, $src}",
2876 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2878 // Move Packed Doubleword Int to Packed Double Int
2879 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2880 "movd\t{$src, $dst|$dst, $src}",
2881 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2883 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
2884 (ins i32mem:$dst, VR128:$src),
2885 "movd\t{$src, $dst|$dst, $src}",
2886 [(store (i32 (vector_extract (v4i32 VR128:$src),
2887 (iPTR 0))), addr:$dst)]>, VEX;
2888 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2889 "movd\t{$src, $dst|$dst, $src}",
2890 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2892 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2893 "movd\t{$src, $dst|$dst, $src}",
2894 [(store (i32 (vector_extract (v4i32 VR128:$src),
2895 (iPTR 0))), addr:$dst)]>;
2897 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2898 "mov{d|q}\t{$src, $dst|$dst, $src}",
2899 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
2901 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2902 "movq\t{$src, $dst|$dst, $src}",
2903 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2905 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2906 "mov{d|q}\t{$src, $dst|$dst, $src}",
2907 [(set GR64:$dst, (bitconvert FR64:$src))]>;
2908 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2909 "movq\t{$src, $dst|$dst, $src}",
2910 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
2912 // Move Scalar Single to Double Int
2913 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2914 "movd\t{$src, $dst|$dst, $src}",
2915 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
2916 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2917 "movd\t{$src, $dst|$dst, $src}",
2918 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
2919 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2920 "movd\t{$src, $dst|$dst, $src}",
2921 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2922 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2923 "movd\t{$src, $dst|$dst, $src}",
2924 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2926 // movd / movq to XMM register zero-extends
2927 let AddedComplexity = 15 in {
2928 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2929 "movd\t{$src, $dst|$dst, $src}",
2930 [(set VR128:$dst, (v4i32 (X86vzmovl
2931 (v4i32 (scalar_to_vector GR32:$src)))))]>,
2933 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2934 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
2935 [(set VR128:$dst, (v2i64 (X86vzmovl
2936 (v2i64 (scalar_to_vector GR64:$src)))))]>,
2939 let AddedComplexity = 15 in {
2940 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2941 "movd\t{$src, $dst|$dst, $src}",
2942 [(set VR128:$dst, (v4i32 (X86vzmovl
2943 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2944 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2945 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
2946 [(set VR128:$dst, (v2i64 (X86vzmovl
2947 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2950 let AddedComplexity = 20 in {
2951 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2952 "movd\t{$src, $dst|$dst, $src}",
2954 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2955 (loadi32 addr:$src))))))]>,
2957 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2958 "movd\t{$src, $dst|$dst, $src}",
2960 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2961 (loadi32 addr:$src))))))]>;
2963 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2964 (MOVZDI2PDIrm addr:$src)>;
2965 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2966 (MOVZDI2PDIrm addr:$src)>;
2967 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2968 (MOVZDI2PDIrm addr:$src)>;
2971 //===---------------------------------------------------------------------===//
2972 // SSE2 - Move Quadword
2973 //===---------------------------------------------------------------------===//
2975 // Move Quadword Int to Packed Quadword Int
2976 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2977 "vmovq\t{$src, $dst|$dst, $src}",
2979 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2980 VEX, Requires<[HasAVX]>;
2981 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2982 "movq\t{$src, $dst|$dst, $src}",
2984 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2985 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
2987 // Move Packed Quadword Int to Quadword Int
2988 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2989 "movq\t{$src, $dst|$dst, $src}",
2990 [(store (i64 (vector_extract (v2i64 VR128:$src),
2991 (iPTR 0))), addr:$dst)]>, VEX;
2992 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2993 "movq\t{$src, $dst|$dst, $src}",
2994 [(store (i64 (vector_extract (v2i64 VR128:$src),
2995 (iPTR 0))), addr:$dst)]>;
2997 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
2998 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
3000 // Store / copy lower 64-bits of a XMM register.
3001 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3002 "movq\t{$src, $dst|$dst, $src}",
3003 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
3004 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3005 "movq\t{$src, $dst|$dst, $src}",
3006 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
3008 let AddedComplexity = 20 in
3009 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3010 "vmovq\t{$src, $dst|$dst, $src}",
3012 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3013 (loadi64 addr:$src))))))]>,
3014 XS, VEX, Requires<[HasAVX]>;
3016 let AddedComplexity = 20 in {
3017 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3018 "movq\t{$src, $dst|$dst, $src}",
3020 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3021 (loadi64 addr:$src))))))]>,
3022 XS, Requires<[HasSSE2]>;
3024 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3025 (MOVZQI2PQIrm addr:$src)>;
3026 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
3027 (MOVZQI2PQIrm addr:$src)>;
3028 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
3031 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
3032 // IA32 document. movq xmm1, xmm2 does clear the high bits.
3033 let AddedComplexity = 15 in
3034 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3035 "vmovq\t{$src, $dst|$dst, $src}",
3036 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3037 XS, VEX, Requires<[HasAVX]>;
3038 let AddedComplexity = 15 in
3039 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3040 "movq\t{$src, $dst|$dst, $src}",
3041 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3042 XS, Requires<[HasSSE2]>;
3044 let AddedComplexity = 20 in
3045 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3046 "vmovq\t{$src, $dst|$dst, $src}",
3047 [(set VR128:$dst, (v2i64 (X86vzmovl
3048 (loadv2i64 addr:$src))))]>,
3049 XS, VEX, Requires<[HasAVX]>;
3050 let AddedComplexity = 20 in {
3051 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3052 "movq\t{$src, $dst|$dst, $src}",
3053 [(set VR128:$dst, (v2i64 (X86vzmovl
3054 (loadv2i64 addr:$src))))]>,
3055 XS, Requires<[HasSSE2]>;
3057 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
3058 (MOVZPQILo2PQIrm addr:$src)>;
3061 // Instructions to match in the assembler
3062 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3063 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3064 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3065 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3066 // Recognize "movd" with GR64 destination, but encode as a "movq"
3067 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3068 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3070 // Instructions for the disassembler
3071 // xr = XMM register
3074 let Predicates = [HasAVX] in
3075 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3076 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
3077 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3078 "movq\t{$src, $dst|$dst, $src}", []>, XS;
3080 //===---------------------------------------------------------------------===//
3081 // SSE2 - Misc Instructions
3082 //===---------------------------------------------------------------------===//
3085 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3086 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3087 TB, Requires<[HasSSE2]>;
3089 // Load, store, and memory fence
3090 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3091 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3092 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3093 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3094 def : Pat<(X86LFence), (LFENCE)>;
3095 def : Pat<(X86MFence), (MFENCE)>;
3098 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3099 // was introduced with SSE2, it's backward compatible.
3100 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3102 // Alias instructions that map zero vector to pxor / xorp* for sse.
3103 // We set canFoldAsLoad because this can be converted to a constant-pool
3104 // load of an all-ones value if folding it would be beneficial.
3105 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3106 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
3107 // FIXME: Change encoding to pseudo.
3108 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3109 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
3111 //===---------------------------------------------------------------------===//
3112 // SSE3 - Conversion Instructions
3113 //===---------------------------------------------------------------------===//
3115 // Convert Packed Double FP to Packed DW Integers
3116 let Predicates = [HasAVX] in {
3117 // The assembler can recognize rr 256-bit instructions by seeing a ymm
3118 // register, but the same isn't true when using memory operands instead.
3119 // Provide other assembly rr and rm forms to address this explicitly.
3120 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3121 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3122 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3123 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3126 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3127 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3128 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3129 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3132 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3133 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
3134 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
3135 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
3138 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3139 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3140 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3141 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3143 // Convert Packed DW Integers to Packed Double FP
3144 let Predicates = [HasAVX] in {
3145 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3146 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3147 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3148 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3149 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
3150 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3151 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
3152 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3155 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3156 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3157 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3158 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3160 // AVX 256-bit register conversion intrinsics
3161 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
3162 (VCVTDQ2PDYrr VR128:$src)>;
3163 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
3164 (VCVTDQ2PDYrm addr:$src)>;
3166 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
3167 (VCVTPD2DQYrr VR256:$src)>;
3168 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
3169 (VCVTPD2DQYrm addr:$src)>;
3171 //===---------------------------------------------------------------------===//
3172 // SSE3 - Move Instructions
3173 //===---------------------------------------------------------------------===//
3175 // Replicate Single FP
3176 multiclass sse3_replicate_sfp<bits<8> op, PatFrag rep_frag, string OpcodeStr> {
3177 def rr : S3SI<op, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3178 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3179 [(set VR128:$dst, (v4f32 (rep_frag
3180 VR128:$src, (undef))))]>;
3181 def rm : S3SI<op, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3182 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3183 [(set VR128:$dst, (rep_frag
3184 (memopv4f32 addr:$src), (undef)))]>;
3187 multiclass sse3_replicate_sfp_y<bits<8> op, PatFrag rep_frag,
3189 def rr : S3SI<op, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3190 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
3191 def rm : S3SI<op, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3192 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
3195 let Predicates = [HasAVX] in {
3196 // FIXME: Merge above classes when we have patterns for the ymm version
3197 defm VMOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "vmovshdup">, VEX;
3198 defm VMOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "vmovsldup">, VEX;
3199 defm VMOVSHDUPY : sse3_replicate_sfp_y<0x16, movshdup, "vmovshdup">, VEX;
3200 defm VMOVSLDUPY : sse3_replicate_sfp_y<0x12, movsldup, "vmovsldup">, VEX;
3202 defm MOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "movshdup">;
3203 defm MOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "movsldup">;
3205 // Replicate Double FP
3206 multiclass sse3_replicate_dfp<string OpcodeStr> {
3207 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3208 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3209 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
3210 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
3211 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3213 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
3217 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
3218 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3219 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3221 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3222 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3226 let Predicates = [HasAVX] in {
3227 // FIXME: Merge above classes when we have patterns for the ymm version
3228 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
3229 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
3231 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
3233 // Move Unaligned Integer
3234 let Predicates = [HasAVX] in {
3235 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3236 "vlddqu\t{$src, $dst|$dst, $src}",
3237 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
3238 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3239 "vlddqu\t{$src, $dst|$dst, $src}",
3240 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
3242 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3243 "lddqu\t{$src, $dst|$dst, $src}",
3244 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
3246 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
3248 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3250 // Several Move patterns
3251 let AddedComplexity = 5 in {
3252 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
3253 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3254 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
3255 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3256 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
3257 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3258 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
3259 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3262 // vector_shuffle v1, <undef> <1, 1, 3, 3>
3263 let AddedComplexity = 15 in
3264 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
3265 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3266 let AddedComplexity = 20 in
3267 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3268 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
3270 // vector_shuffle v1, <undef> <0, 0, 2, 2>
3271 let AddedComplexity = 15 in
3272 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
3273 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3274 let AddedComplexity = 20 in
3275 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3276 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
3278 //===---------------------------------------------------------------------===//
3279 // SSE3 - Arithmetic
3280 //===---------------------------------------------------------------------===//
3282 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
3283 X86MemOperand x86memop, bit Is2Addr = 1> {
3284 def rr : I<0xD0, MRMSrcReg,
3285 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3287 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3288 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3289 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
3290 def rm : I<0xD0, MRMSrcMem,
3291 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3293 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3294 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3295 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
3298 let Predicates = [HasAVX],
3299 ExeDomain = SSEPackedDouble in {
3300 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
3301 f128mem, 0>, TB, XD, VEX_4V;
3302 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
3303 f128mem, 0>, TB, OpSize, VEX_4V;
3304 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
3305 f256mem, 0>, TB, XD, VEX_4V;
3306 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
3307 f256mem, 0>, TB, OpSize, VEX_4V;
3309 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
3310 ExeDomain = SSEPackedDouble in {
3311 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
3313 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
3314 f128mem>, TB, OpSize;
3317 //===---------------------------------------------------------------------===//
3318 // SSE3 Instructions
3319 //===---------------------------------------------------------------------===//
3322 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3323 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3324 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3326 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3327 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3328 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3330 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3332 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3333 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3334 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3336 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3337 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3338 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3340 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3341 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3342 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3344 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3346 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3347 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3348 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3351 let Predicates = [HasAVX] in {
3352 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
3353 int_x86_sse3_hadd_ps, 0>, VEX_4V;
3354 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
3355 int_x86_sse3_hadd_pd, 0>, VEX_4V;
3356 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
3357 int_x86_sse3_hsub_ps, 0>, VEX_4V;
3358 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
3359 int_x86_sse3_hsub_pd, 0>, VEX_4V;
3360 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
3361 int_x86_avx_hadd_ps_256, 0>, VEX_4V;
3362 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
3363 int_x86_avx_hadd_pd_256, 0>, VEX_4V;
3364 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
3365 int_x86_avx_hsub_ps_256, 0>, VEX_4V;
3366 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
3367 int_x86_avx_hsub_pd_256, 0>, VEX_4V;
3370 let Constraints = "$src1 = $dst" in {
3371 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
3372 int_x86_sse3_hadd_ps>;
3373 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
3374 int_x86_sse3_hadd_pd>;
3375 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
3376 int_x86_sse3_hsub_ps>;
3377 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
3378 int_x86_sse3_hsub_pd>;
3381 //===---------------------------------------------------------------------===//
3382 // SSSE3 - Packed Absolute Instructions
3383 //===---------------------------------------------------------------------===//
3386 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
3387 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
3388 PatFrag mem_frag128, Intrinsic IntId128> {
3389 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3391 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3392 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3395 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3397 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3400 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
3403 let Predicates = [HasAVX] in {
3404 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
3405 int_x86_ssse3_pabs_b_128>, VEX;
3406 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
3407 int_x86_ssse3_pabs_w_128>, VEX;
3408 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
3409 int_x86_ssse3_pabs_d_128>, VEX;
3412 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
3413 int_x86_ssse3_pabs_b_128>;
3414 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
3415 int_x86_ssse3_pabs_w_128>;
3416 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
3417 int_x86_ssse3_pabs_d_128>;
3419 //===---------------------------------------------------------------------===//
3420 // SSSE3 - Packed Binary Operator Instructions
3421 //===---------------------------------------------------------------------===//
3423 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
3424 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
3425 PatFrag mem_frag128, Intrinsic IntId128,
3427 let isCommutable = 1 in
3428 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3429 (ins VR128:$src1, VR128:$src2),
3431 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3432 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3433 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3435 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3436 (ins VR128:$src1, i128mem:$src2),
3438 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3439 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3441 (IntId128 VR128:$src1,
3442 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3445 let Predicates = [HasAVX] in {
3446 let isCommutable = 0 in {
3447 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
3448 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
3449 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
3450 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
3451 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
3452 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
3453 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
3454 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
3455 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
3456 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
3457 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
3458 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
3459 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
3460 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
3461 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
3462 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
3463 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
3464 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
3465 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
3466 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
3467 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
3468 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
3470 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
3471 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
3474 // None of these have i8 immediate fields.
3475 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
3476 let isCommutable = 0 in {
3477 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
3478 int_x86_ssse3_phadd_w_128>;
3479 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
3480 int_x86_ssse3_phadd_d_128>;
3481 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
3482 int_x86_ssse3_phadd_sw_128>;
3483 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
3484 int_x86_ssse3_phsub_w_128>;
3485 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
3486 int_x86_ssse3_phsub_d_128>;
3487 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
3488 int_x86_ssse3_phsub_sw_128>;
3489 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
3490 int_x86_ssse3_pmadd_ub_sw_128>;
3491 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
3492 int_x86_ssse3_pshuf_b_128>;
3493 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
3494 int_x86_ssse3_psign_b_128>;
3495 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
3496 int_x86_ssse3_psign_w_128>;
3497 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
3498 int_x86_ssse3_psign_d_128>;
3500 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
3501 int_x86_ssse3_pmul_hr_sw_128>;
3504 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
3505 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
3506 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
3507 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
3509 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
3510 (PSIGNBrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3511 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
3512 (PSIGNWrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3513 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
3514 (PSIGNDrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3516 //===---------------------------------------------------------------------===//
3517 // SSSE3 - Packed Align Instruction Patterns
3518 //===---------------------------------------------------------------------===//
3520 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
3521 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
3522 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3524 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3526 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3528 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
3529 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3531 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3533 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3537 let Predicates = [HasAVX] in
3538 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
3539 let Constraints = "$src1 = $dst" in
3540 defm PALIGN : ssse3_palign<"palignr">;
3542 let AddedComplexity = 5 in {
3543 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
3544 (PALIGNR128rr VR128:$src2, VR128:$src1,
3545 (SHUFFLE_get_palign_imm VR128:$src3))>,
3546 Requires<[HasSSSE3]>;
3547 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
3548 (PALIGNR128rr VR128:$src2, VR128:$src1,
3549 (SHUFFLE_get_palign_imm VR128:$src3))>,
3550 Requires<[HasSSSE3]>;
3551 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
3552 (PALIGNR128rr VR128:$src2, VR128:$src1,
3553 (SHUFFLE_get_palign_imm VR128:$src3))>,
3554 Requires<[HasSSSE3]>;
3555 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
3556 (PALIGNR128rr VR128:$src2, VR128:$src1,
3557 (SHUFFLE_get_palign_imm VR128:$src3))>,
3558 Requires<[HasSSSE3]>;
3561 //===---------------------------------------------------------------------===//
3562 // SSSE3 Misc Instructions
3563 //===---------------------------------------------------------------------===//
3565 // Thread synchronization
3566 let usesCustomInserter = 1 in {
3567 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
3568 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
3569 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
3570 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
3573 let Uses = [EAX, ECX, EDX] in
3574 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
3575 Requires<[HasSSE3]>;
3576 let Uses = [ECX, EAX] in
3577 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
3578 Requires<[HasSSE3]>;
3580 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
3581 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
3583 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
3584 Requires<[In32BitMode]>;
3585 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
3586 Requires<[In64BitMode]>;
3588 //===---------------------------------------------------------------------===//
3589 // Non-Instruction Patterns
3590 //===---------------------------------------------------------------------===//
3592 // extload f32 -> f64. This matches load+fextend because we have a hack in
3593 // the isel (PreprocessForFPConvert) that can introduce loads after dag
3595 // Since these loads aren't folded into the fextend, we have to match it
3597 let Predicates = [HasSSE2] in
3598 def : Pat<(fextend (loadf32 addr:$src)),
3599 (CVTSS2SDrm addr:$src)>;
3601 // FIXME: According to the intel manual, DEST[127:64] <- SRC1[127:64], while
3602 // in the non-AVX version bits 127:64 aren't touched. Find a better way to
3603 // represent this instead of always zeroing SRC1. One possible solution is
3604 // to represent the instruction w/ something similar as the "$src1 = $dst"
3605 // constraint but without the tied operands.
3606 let Predicates = [HasAVX] in
3607 def : Pat<(fextend (loadf32 addr:$src)),
3608 (VCVTSS2SDrm (f32 (EXTRACT_SUBREG (AVX_SET0PS), sub_ss)),
3612 let Predicates = [HasXMMInt] in {
3613 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
3614 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
3615 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
3616 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
3617 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
3618 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
3619 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
3620 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3621 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3622 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3623 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3624 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3625 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3626 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3627 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3628 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3629 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3630 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3631 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3632 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3633 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3634 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3635 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3636 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3637 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3638 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3639 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3640 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3641 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3642 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3645 let Predicates = [HasAVX] in {
3646 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
3649 // Move scalar to XMM zero-extended
3650 // movd to XMM register zero-extends
3651 let AddedComplexity = 15 in {
3652 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3653 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3654 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
3655 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3656 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
3657 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3658 (MOVSSrr (v4f32 (V_SET0PS)),
3659 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
3660 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3661 (MOVSSrr (v4i32 (V_SET0PI)),
3662 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
3665 // Splat v2f64 / v2i64
3666 let AddedComplexity = 10 in {
3667 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3668 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3669 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
3670 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3671 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3672 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3673 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
3674 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3677 // Special unary SHUFPSrri case.
3678 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3679 (SHUFPSrri VR128:$src1, VR128:$src1,
3680 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3681 let AddedComplexity = 5 in
3682 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3683 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3684 Requires<[HasSSE2]>;
3685 // Special unary SHUFPDrri case.
3686 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3687 (SHUFPDrri VR128:$src1, VR128:$src1,
3688 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3689 Requires<[HasSSE2]>;
3690 // Special unary SHUFPDrri case.
3691 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3692 (SHUFPDrri VR128:$src1, VR128:$src1,
3693 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3694 Requires<[HasSSE2]>;
3695 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3696 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3697 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3698 Requires<[HasSSE2]>;
3700 // Special binary v4i32 shuffle cases with SHUFPS.
3701 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3702 (SHUFPSrri VR128:$src1, VR128:$src2,
3703 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3704 Requires<[HasSSE2]>;
3705 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3706 (SHUFPSrmi VR128:$src1, addr:$src2,
3707 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3708 Requires<[HasSSE2]>;
3709 // Special binary v2i64 shuffle cases using SHUFPDrri.
3710 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3711 (SHUFPDrri VR128:$src1, VR128:$src2,
3712 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3713 Requires<[HasSSE2]>;
3715 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3716 let AddedComplexity = 15 in {
3717 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3718 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3719 Requires<[OptForSpeed, HasSSE2]>;
3720 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3721 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3722 Requires<[OptForSpeed, HasSSE2]>;
3724 let AddedComplexity = 10 in {
3725 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3726 (UNPCKLPSrr VR128:$src, VR128:$src)>;
3727 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3728 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
3729 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3730 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
3731 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3732 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3735 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3736 let AddedComplexity = 15 in {
3737 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3738 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3739 Requires<[OptForSpeed, HasSSE2]>;
3740 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3741 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3742 Requires<[OptForSpeed, HasSSE2]>;
3744 let AddedComplexity = 10 in {
3745 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3746 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3747 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3748 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3749 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3750 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3751 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3752 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3755 let AddedComplexity = 20 in {
3756 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3757 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3758 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3760 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3761 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3762 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3764 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3765 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3766 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3767 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3768 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3771 let AddedComplexity = 20 in {
3772 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3773 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3774 (MOVLPSrm VR128:$src1, addr:$src2)>;
3775 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3776 (MOVLPDrm VR128:$src1, addr:$src2)>;
3777 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3778 (MOVLPSrm VR128:$src1, addr:$src2)>;
3779 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3780 (MOVLPDrm VR128:$src1, addr:$src2)>;
3783 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3784 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3785 (MOVLPSmr addr:$src1, VR128:$src2)>;
3786 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3787 (MOVLPDmr addr:$src1, VR128:$src2)>;
3788 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3790 (MOVLPSmr addr:$src1, VR128:$src2)>;
3791 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3792 (MOVLPDmr addr:$src1, VR128:$src2)>;
3794 let AddedComplexity = 15 in {
3795 // Setting the lowest element in the vector.
3796 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3797 (MOVSSrr (v4i32 VR128:$src1),
3798 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3799 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3800 (MOVSDrr (v2i64 VR128:$src1),
3801 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
3803 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3804 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3805 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3806 Requires<[HasSSE2]>;
3807 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3808 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3809 Requires<[HasSSE2]>;
3812 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3813 // fall back to this for SSE1)
3814 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3815 (SHUFPSrri VR128:$src2, VR128:$src1,
3816 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3818 // Set lowest element and zero upper elements.
3819 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3820 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3822 // vector -> vector casts
3823 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3824 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3825 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3826 (CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3828 // Use movaps / movups for SSE integer load / store (one byte shorter).
3829 let Predicates = [HasSSE1] in {
3830 def : Pat<(alignedloadv4i32 addr:$src),
3831 (MOVAPSrm addr:$src)>;
3832 def : Pat<(loadv4i32 addr:$src),
3833 (MOVUPSrm addr:$src)>;
3834 def : Pat<(alignedloadv2i64 addr:$src),
3835 (MOVAPSrm addr:$src)>;
3836 def : Pat<(loadv2i64 addr:$src),
3837 (MOVUPSrm addr:$src)>;
3839 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3840 (MOVAPSmr addr:$dst, VR128:$src)>;
3841 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3842 (MOVAPSmr addr:$dst, VR128:$src)>;
3843 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3844 (MOVAPSmr addr:$dst, VR128:$src)>;
3845 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3846 (MOVAPSmr addr:$dst, VR128:$src)>;
3847 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3848 (MOVUPSmr addr:$dst, VR128:$src)>;
3849 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3850 (MOVUPSmr addr:$dst, VR128:$src)>;
3851 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3852 (MOVUPSmr addr:$dst, VR128:$src)>;
3853 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3854 (MOVUPSmr addr:$dst, VR128:$src)>;
3857 // Use vmovaps/vmovups for AVX 128-bit integer load/store (one byte shorter).
3858 let Predicates = [HasAVX] in {
3859 def : Pat<(alignedloadv4i32 addr:$src),
3860 (VMOVAPSrm addr:$src)>;
3861 def : Pat<(loadv4i32 addr:$src),
3862 (VMOVUPSrm addr:$src)>;
3863 def : Pat<(alignedloadv2i64 addr:$src),
3864 (VMOVAPSrm addr:$src)>;
3865 def : Pat<(loadv2i64 addr:$src),
3866 (VMOVUPSrm addr:$src)>;
3868 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3869 (VMOVAPSmr addr:$dst, VR128:$src)>;
3870 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3871 (VMOVAPSmr addr:$dst, VR128:$src)>;
3872 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3873 (VMOVAPSmr addr:$dst, VR128:$src)>;
3874 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3875 (VMOVAPSmr addr:$dst, VR128:$src)>;
3876 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3877 (VMOVUPSmr addr:$dst, VR128:$src)>;
3878 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3879 (VMOVUPSmr addr:$dst, VR128:$src)>;
3880 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3881 (VMOVUPSmr addr:$dst, VR128:$src)>;
3882 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3883 (VMOVUPSmr addr:$dst, VR128:$src)>;
3886 //===----------------------------------------------------------------------===//
3887 // SSE4.1 - Packed Move with Sign/Zero Extend
3888 //===----------------------------------------------------------------------===//
3890 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3891 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3892 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3893 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3895 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3896 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3898 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3902 let Predicates = [HasAVX] in {
3903 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
3905 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
3907 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
3909 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
3911 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
3913 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
3917 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3918 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3919 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3920 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3921 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3922 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3924 // Common patterns involving scalar load.
3925 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3926 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3927 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3928 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3930 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3931 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3932 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3933 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3935 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3936 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3937 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3938 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3940 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3941 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3942 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3943 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3945 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3946 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3947 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3948 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3950 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3951 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3952 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3953 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3956 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3957 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3958 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3959 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3961 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3962 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3964 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3968 let Predicates = [HasAVX] in {
3969 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
3971 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
3973 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
3975 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
3979 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3980 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3981 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3982 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3984 // Common patterns involving scalar load
3985 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3986 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3987 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3988 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3990 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3991 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3992 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3993 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3996 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3997 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3998 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3999 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4001 // Expecting a i16 load any extended to i32 value.
4002 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
4003 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4004 [(set VR128:$dst, (IntId (bitconvert
4005 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
4009 let Predicates = [HasAVX] in {
4010 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
4012 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
4015 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
4016 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
4018 // Common patterns involving scalar load
4019 def : Pat<(int_x86_sse41_pmovsxbq
4020 (bitconvert (v4i32 (X86vzmovl
4021 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4022 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
4024 def : Pat<(int_x86_sse41_pmovzxbq
4025 (bitconvert (v4i32 (X86vzmovl
4026 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4027 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
4029 //===----------------------------------------------------------------------===//
4030 // SSE4.1 - Extract Instructions
4031 //===----------------------------------------------------------------------===//
4033 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
4034 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
4035 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4036 (ins VR128:$src1, i32i8imm:$src2),
4037 !strconcat(OpcodeStr,
4038 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4039 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
4041 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4042 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
4043 !strconcat(OpcodeStr,
4044 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4047 // There's an AssertZext in the way of writing the store pattern
4048 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4051 let Predicates = [HasAVX] in {
4052 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
4053 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
4054 (ins VR128:$src1, i32i8imm:$src2),
4055 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
4058 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
4061 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
4062 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
4063 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4064 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
4065 !strconcat(OpcodeStr,
4066 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4069 // There's an AssertZext in the way of writing the store pattern
4070 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4073 let Predicates = [HasAVX] in
4074 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
4076 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
4079 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4080 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
4081 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4082 (ins VR128:$src1, i32i8imm:$src2),
4083 !strconcat(OpcodeStr,
4084 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4086 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
4087 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4088 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
4089 !strconcat(OpcodeStr,
4090 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4091 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
4092 addr:$dst)]>, OpSize;
4095 let Predicates = [HasAVX] in
4096 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
4098 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
4100 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4101 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
4102 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
4103 (ins VR128:$src1, i32i8imm:$src2),
4104 !strconcat(OpcodeStr,
4105 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4107 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
4108 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4109 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
4110 !strconcat(OpcodeStr,
4111 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4112 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
4113 addr:$dst)]>, OpSize, REX_W;
4116 let Predicates = [HasAVX] in
4117 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
4119 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
4121 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
4123 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
4124 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4125 (ins VR128:$src1, i32i8imm:$src2),
4126 !strconcat(OpcodeStr,
4127 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4129 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
4131 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4132 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
4133 !strconcat(OpcodeStr,
4134 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4135 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
4136 addr:$dst)]>, OpSize;
4139 let Predicates = [HasAVX] in {
4140 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
4141 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
4142 (ins VR128:$src1, i32i8imm:$src2),
4143 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
4146 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
4148 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
4149 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
4152 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
4153 Requires<[HasSSE41]>;
4155 //===----------------------------------------------------------------------===//
4156 // SSE4.1 - Insert Instructions
4157 //===----------------------------------------------------------------------===//
4159 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
4160 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4161 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4163 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4165 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4167 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
4168 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4169 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
4171 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4173 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4175 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
4176 imm:$src3))]>, OpSize;
4179 let Predicates = [HasAVX] in
4180 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
4181 let Constraints = "$src1 = $dst" in
4182 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
4184 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
4185 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4186 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4188 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4190 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4192 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
4194 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4195 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
4197 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4199 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4201 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
4202 imm:$src3)))]>, OpSize;
4205 let Predicates = [HasAVX] in
4206 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
4207 let Constraints = "$src1 = $dst" in
4208 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
4210 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
4211 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4212 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4214 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4216 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4218 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
4220 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4221 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
4223 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4225 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4227 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
4228 imm:$src3)))]>, OpSize;
4231 let Predicates = [HasAVX] in
4232 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
4233 let Constraints = "$src1 = $dst" in
4234 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
4236 // insertps has a few different modes, there's the first two here below which
4237 // are optimized inserts that won't zero arbitrary elements in the destination
4238 // vector. The next one matches the intrinsic and could zero arbitrary elements
4239 // in the target vector.
4240 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
4241 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4242 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4244 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4246 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4248 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
4250 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4251 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
4253 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4255 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4257 (X86insrtps VR128:$src1,
4258 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
4259 imm:$src3))]>, OpSize;
4262 let Constraints = "$src1 = $dst" in
4263 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
4264 let Predicates = [HasAVX] in
4265 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
4267 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4268 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4270 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4271 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4272 Requires<[HasSSE41]>;
4274 //===----------------------------------------------------------------------===//
4275 // SSE4.1 - Round Instructions
4276 //===----------------------------------------------------------------------===//
4278 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4279 X86MemOperand x86memop, RegisterClass RC,
4280 PatFrag mem_frag32, PatFrag mem_frag64,
4281 Intrinsic V4F32Int, Intrinsic V2F64Int> {
4282 // Intrinsic operation, reg.
4283 // Vector intrinsic operation, reg
4284 def PSr : SS4AIi8<opcps, MRMSrcReg,
4285 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4286 !strconcat(OpcodeStr,
4287 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4288 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
4291 // Vector intrinsic operation, mem
4292 def PSm : Ii8<opcps, MRMSrcMem,
4293 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4294 !strconcat(OpcodeStr,
4295 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4297 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4299 Requires<[HasSSE41]>;
4301 // Vector intrinsic operation, reg
4302 def PDr : SS4AIi8<opcpd, MRMSrcReg,
4303 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4304 !strconcat(OpcodeStr,
4305 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4306 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
4309 // Vector intrinsic operation, mem
4310 def PDm : SS4AIi8<opcpd, MRMSrcMem,
4311 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4312 !strconcat(OpcodeStr,
4313 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4315 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4319 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
4320 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
4321 // Intrinsic operation, reg.
4322 // Vector intrinsic operation, reg
4323 def PSr_AVX : SS4AIi8<opcps, MRMSrcReg,
4324 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4325 !strconcat(OpcodeStr,
4326 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4329 // Vector intrinsic operation, mem
4330 def PSm_AVX : Ii8<opcps, MRMSrcMem,
4331 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4332 !strconcat(OpcodeStr,
4333 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4334 []>, TA, OpSize, Requires<[HasSSE41]>;
4336 // Vector intrinsic operation, reg
4337 def PDr_AVX : SS4AIi8<opcpd, MRMSrcReg,
4338 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4339 !strconcat(OpcodeStr,
4340 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4343 // Vector intrinsic operation, mem
4344 def PDm_AVX : SS4AIi8<opcpd, MRMSrcMem,
4345 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4346 !strconcat(OpcodeStr,
4347 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4351 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4354 Intrinsic F64Int, bit Is2Addr = 1> {
4355 // Intrinsic operation, reg.
4356 def SSr : SS4AIi8<opcss, MRMSrcReg,
4357 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4359 !strconcat(OpcodeStr,
4360 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4361 !strconcat(OpcodeStr,
4362 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4363 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4366 // Intrinsic operation, mem.
4367 def SSm : SS4AIi8<opcss, MRMSrcMem,
4368 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4370 !strconcat(OpcodeStr,
4371 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4372 !strconcat(OpcodeStr,
4373 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4375 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
4378 // Intrinsic operation, reg.
4379 def SDr : SS4AIi8<opcsd, MRMSrcReg,
4380 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4382 !strconcat(OpcodeStr,
4383 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4384 !strconcat(OpcodeStr,
4385 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4386 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4389 // Intrinsic operation, mem.
4390 def SDm : SS4AIi8<opcsd, MRMSrcMem,
4391 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4393 !strconcat(OpcodeStr,
4394 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4395 !strconcat(OpcodeStr,
4396 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4398 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
4402 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
4404 // Intrinsic operation, reg.
4405 def SSr_AVX : SS4AIi8<opcss, MRMSrcReg,
4406 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4407 !strconcat(OpcodeStr,
4408 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4411 // Intrinsic operation, mem.
4412 def SSm_AVX : SS4AIi8<opcss, MRMSrcMem,
4413 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4414 !strconcat(OpcodeStr,
4415 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4418 // Intrinsic operation, reg.
4419 def SDr_AVX : SS4AIi8<opcsd, MRMSrcReg,
4420 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4421 !strconcat(OpcodeStr,
4422 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4425 // Intrinsic operation, mem.
4426 def SDm_AVX : SS4AIi8<opcsd, MRMSrcMem,
4427 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4428 !strconcat(OpcodeStr,
4429 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4433 // FP round - roundss, roundps, roundsd, roundpd
4434 let Predicates = [HasAVX] in {
4436 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
4437 memopv4f32, memopv2f64,
4438 int_x86_sse41_round_ps,
4439 int_x86_sse41_round_pd>, VEX;
4440 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
4441 memopv8f32, memopv4f64,
4442 int_x86_avx_round_ps_256,
4443 int_x86_avx_round_pd_256>, VEX;
4444 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
4445 int_x86_sse41_round_ss,
4446 int_x86_sse41_round_sd, 0>, VEX_4V;
4448 // Instructions for the assembler
4449 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
4451 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
4453 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
4456 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
4457 memopv4f32, memopv2f64,
4458 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
4459 let Constraints = "$src1 = $dst" in
4460 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
4461 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
4463 //===----------------------------------------------------------------------===//
4464 // SSE4.1 - Packed Bit Test
4465 //===----------------------------------------------------------------------===//
4467 // ptest instruction we'll lower to this in X86ISelLowering primarily from
4468 // the intel intrinsic that corresponds to this.
4469 let Defs = [EFLAGS], Predicates = [HasAVX] in {
4470 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4471 "vptest\t{$src2, $src1|$src1, $src2}",
4472 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4474 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4475 "vptest\t{$src2, $src1|$src1, $src2}",
4476 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4479 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
4480 "vptest\t{$src2, $src1|$src1, $src2}",
4481 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
4483 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
4484 "vptest\t{$src2, $src1|$src1, $src2}",
4485 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
4489 let Defs = [EFLAGS] in {
4490 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4491 "ptest \t{$src2, $src1|$src1, $src2}",
4492 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4494 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4495 "ptest \t{$src2, $src1|$src1, $src2}",
4496 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4500 // The bit test instructions below are AVX only
4501 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
4502 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
4503 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
4504 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4505 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
4506 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
4507 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4508 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
4512 let Defs = [EFLAGS], Predicates = [HasAVX] in {
4513 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
4514 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
4515 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
4516 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
4519 //===----------------------------------------------------------------------===//
4520 // SSE4.1 - Misc Instructions
4521 //===----------------------------------------------------------------------===//
4523 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4524 "popcnt{w}\t{$src, $dst|$dst, $src}",
4525 [(set GR16:$dst, (ctpop GR16:$src))]>, OpSize, XS;
4526 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4527 "popcnt{w}\t{$src, $dst|$dst, $src}",
4528 [(set GR16:$dst, (ctpop (loadi16 addr:$src)))]>, OpSize, XS;
4530 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4531 "popcnt{l}\t{$src, $dst|$dst, $src}",
4532 [(set GR32:$dst, (ctpop GR32:$src))]>, XS;
4533 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4534 "popcnt{l}\t{$src, $dst|$dst, $src}",
4535 [(set GR32:$dst, (ctpop (loadi32 addr:$src)))]>, XS;
4537 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4538 "popcnt{q}\t{$src, $dst|$dst, $src}",
4539 [(set GR64:$dst, (ctpop GR64:$src))]>, XS;
4540 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4541 "popcnt{q}\t{$src, $dst|$dst, $src}",
4542 [(set GR64:$dst, (ctpop (loadi64 addr:$src)))]>, XS;
4546 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
4547 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
4548 Intrinsic IntId128> {
4549 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4551 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4552 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
4553 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4555 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4558 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
4561 let Predicates = [HasAVX] in
4562 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
4563 int_x86_sse41_phminposuw>, VEX;
4564 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
4565 int_x86_sse41_phminposuw>;
4567 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
4568 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
4569 Intrinsic IntId128, bit Is2Addr = 1> {
4570 let isCommutable = 1 in
4571 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4572 (ins VR128:$src1, VR128:$src2),
4574 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4575 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4576 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
4577 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4578 (ins VR128:$src1, i128mem:$src2),
4580 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4581 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4583 (IntId128 VR128:$src1,
4584 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4587 let Predicates = [HasAVX] in {
4588 let isCommutable = 0 in
4589 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
4591 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
4593 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
4595 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
4597 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
4599 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
4601 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
4603 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
4605 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
4607 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
4609 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
4613 let Constraints = "$src1 = $dst" in {
4614 let isCommutable = 0 in
4615 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
4616 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
4617 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
4618 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
4619 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
4620 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
4621 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
4622 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
4623 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
4624 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
4625 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
4628 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
4629 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
4630 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
4631 (PCMPEQQrm VR128:$src1, addr:$src2)>;
4633 /// SS48I_binop_rm - Simple SSE41 binary operator.
4634 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4635 ValueType OpVT, bit Is2Addr = 1> {
4636 let isCommutable = 1 in
4637 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4638 (ins VR128:$src1, VR128:$src2),
4640 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4641 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4642 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
4644 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4645 (ins VR128:$src1, i128mem:$src2),
4647 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4648 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4649 [(set VR128:$dst, (OpNode VR128:$src1,
4650 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
4654 let Predicates = [HasAVX] in
4655 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
4656 let Constraints = "$src1 = $dst" in
4657 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
4659 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
4660 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
4661 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
4662 X86MemOperand x86memop, bit Is2Addr = 1> {
4663 let isCommutable = 1 in
4664 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
4665 (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4667 !strconcat(OpcodeStr,
4668 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4669 !strconcat(OpcodeStr,
4670 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4671 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
4673 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
4674 (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4676 !strconcat(OpcodeStr,
4677 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4678 !strconcat(OpcodeStr,
4679 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4682 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
4686 let Predicates = [HasAVX] in {
4687 let isCommutable = 0 in {
4688 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
4689 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4690 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
4691 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4692 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
4693 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4694 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
4695 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4696 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
4697 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4698 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
4699 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4701 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
4702 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4703 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
4704 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4705 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
4706 VR256, memopv32i8, i256mem, 0>, VEX_4V;
4709 let Constraints = "$src1 = $dst" in {
4710 let isCommutable = 0 in {
4711 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
4712 VR128, memopv16i8, i128mem>;
4713 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
4714 VR128, memopv16i8, i128mem>;
4715 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
4716 VR128, memopv16i8, i128mem>;
4717 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
4718 VR128, memopv16i8, i128mem>;
4720 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
4721 VR128, memopv16i8, i128mem>;
4722 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
4723 VR128, memopv16i8, i128mem>;
4726 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
4727 let Predicates = [HasAVX] in {
4728 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
4729 RegisterClass RC, X86MemOperand x86memop,
4730 PatFrag mem_frag, Intrinsic IntId> {
4731 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
4732 (ins RC:$src1, RC:$src2, RC:$src3),
4733 !strconcat(OpcodeStr,
4734 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4735 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
4736 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4738 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
4739 (ins RC:$src1, x86memop:$src2, RC:$src3),
4740 !strconcat(OpcodeStr,
4741 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4743 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
4745 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4749 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
4750 memopv16i8, int_x86_sse41_blendvpd>;
4751 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
4752 memopv16i8, int_x86_sse41_blendvps>;
4753 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
4754 memopv16i8, int_x86_sse41_pblendvb>;
4755 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
4756 memopv32i8, int_x86_avx_blendv_pd_256>;
4757 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
4758 memopv32i8, int_x86_avx_blendv_ps_256>;
4760 /// SS41I_ternary_int - SSE 4.1 ternary operator
4761 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
4762 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4763 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4764 (ins VR128:$src1, VR128:$src2),
4765 !strconcat(OpcodeStr,
4766 "\t{$src2, $dst|$dst, $src2}"),
4767 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
4770 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4771 (ins VR128:$src1, i128mem:$src2),
4772 !strconcat(OpcodeStr,
4773 "\t{$src2, $dst|$dst, $src2}"),
4776 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
4780 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
4781 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
4782 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
4784 def : Pat<(X86pblendv VR128:$src1, VR128:$src2, XMM0),
4785 (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
4787 let Predicates = [HasAVX] in
4788 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4789 "vmovntdqa\t{$src, $dst|$dst, $src}",
4790 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4792 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4793 "movntdqa\t{$src, $dst|$dst, $src}",
4794 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4797 //===----------------------------------------------------------------------===//
4798 // SSE4.2 - Compare Instructions
4799 //===----------------------------------------------------------------------===//
4801 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
4802 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
4803 Intrinsic IntId128, bit Is2Addr = 1> {
4804 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
4805 (ins VR128:$src1, VR128:$src2),
4807 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4808 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4809 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4811 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
4812 (ins VR128:$src1, i128mem:$src2),
4814 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4815 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4817 (IntId128 VR128:$src1,
4818 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4821 let Predicates = [HasAVX] in
4822 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
4824 let Constraints = "$src1 = $dst" in
4825 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
4827 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
4828 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
4829 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
4830 (PCMPGTQrm VR128:$src1, addr:$src2)>;
4832 //===----------------------------------------------------------------------===//
4833 // SSE4.2 - String/text Processing Instructions
4834 //===----------------------------------------------------------------------===//
4836 // Packed Compare Implicit Length Strings, Return Mask
4837 multiclass pseudo_pcmpistrm<string asm> {
4838 def REG : PseudoI<(outs VR128:$dst),
4839 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4840 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
4842 def MEM : PseudoI<(outs VR128:$dst),
4843 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4844 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
4845 VR128:$src1, (load addr:$src2), imm:$src3))]>;
4848 let Defs = [EFLAGS], usesCustomInserter = 1 in {
4849 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
4850 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
4853 let Defs = [XMM0, EFLAGS], Predicates = [HasAVX] in {
4854 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4855 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4856 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
4857 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4858 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4859 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
4862 let Defs = [XMM0, EFLAGS] in {
4863 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4864 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4865 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4866 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4867 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4868 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4871 // Packed Compare Explicit Length Strings, Return Mask
4872 multiclass pseudo_pcmpestrm<string asm> {
4873 def REG : PseudoI<(outs VR128:$dst),
4874 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4875 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4876 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
4877 def MEM : PseudoI<(outs VR128:$dst),
4878 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4879 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4880 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
4883 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
4884 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
4885 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
4888 let Predicates = [HasAVX],
4889 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4890 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4891 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4892 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
4893 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4894 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4895 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
4898 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4899 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4900 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4901 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4902 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4903 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4904 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4907 // Packed Compare Implicit Length Strings, Return Index
4908 let Defs = [ECX, EFLAGS] in {
4909 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
4910 def rr : SS42AI<0x63, MRMSrcReg, (outs),
4911 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4912 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
4913 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
4914 (implicit EFLAGS)]>, OpSize;
4915 def rm : SS42AI<0x63, MRMSrcMem, (outs),
4916 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4917 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
4918 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
4919 (implicit EFLAGS)]>, OpSize;
4923 let Predicates = [HasAVX] in {
4924 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
4926 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
4928 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
4930 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
4932 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
4934 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
4938 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
4939 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
4940 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
4941 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
4942 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
4943 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
4945 // Packed Compare Explicit Length Strings, Return Index
4946 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
4947 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
4948 def rr : SS42AI<0x61, MRMSrcReg, (outs),
4949 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4950 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
4951 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
4952 (implicit EFLAGS)]>, OpSize;
4953 def rm : SS42AI<0x61, MRMSrcMem, (outs),
4954 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4955 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
4957 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
4958 (implicit EFLAGS)]>, OpSize;
4962 let Predicates = [HasAVX] in {
4963 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
4965 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
4967 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
4969 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
4971 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
4973 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
4977 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
4978 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
4979 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
4980 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
4981 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
4982 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
4984 //===----------------------------------------------------------------------===//
4985 // SSE4.2 - CRC Instructions
4986 //===----------------------------------------------------------------------===//
4988 // No CRC instructions have AVX equivalents
4990 // crc intrinsic instruction
4991 // This set of instructions are only rm, the only difference is the size
4993 let Constraints = "$src1 = $dst" in {
4994 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
4995 (ins GR32:$src1, i8mem:$src2),
4996 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4998 (int_x86_sse42_crc32_32_8 GR32:$src1,
4999 (load addr:$src2)))]>;
5000 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
5001 (ins GR32:$src1, GR8:$src2),
5002 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5004 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
5005 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5006 (ins GR32:$src1, i16mem:$src2),
5007 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5009 (int_x86_sse42_crc32_32_16 GR32:$src1,
5010 (load addr:$src2)))]>,
5012 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5013 (ins GR32:$src1, GR16:$src2),
5014 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5016 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
5018 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5019 (ins GR32:$src1, i32mem:$src2),
5020 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5022 (int_x86_sse42_crc32_32_32 GR32:$src1,
5023 (load addr:$src2)))]>;
5024 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5025 (ins GR32:$src1, GR32:$src2),
5026 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5028 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
5029 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
5030 (ins GR64:$src1, i8mem:$src2),
5031 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5033 (int_x86_sse42_crc32_64_8 GR64:$src1,
5034 (load addr:$src2)))]>,
5036 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
5037 (ins GR64:$src1, GR8:$src2),
5038 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5040 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
5042 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
5043 (ins GR64:$src1, i64mem:$src2),
5044 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5046 (int_x86_sse42_crc32_64_64 GR64:$src1,
5047 (load addr:$src2)))]>,
5049 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
5050 (ins GR64:$src1, GR64:$src2),
5051 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5053 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
5057 //===----------------------------------------------------------------------===//
5058 // AES-NI Instructions
5059 //===----------------------------------------------------------------------===//
5061 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
5062 Intrinsic IntId128, bit Is2Addr = 1> {
5063 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
5064 (ins VR128:$src1, VR128:$src2),
5066 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5067 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5068 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5070 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
5071 (ins VR128:$src1, i128mem:$src2),
5073 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5074 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5076 (IntId128 VR128:$src1,
5077 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5080 // Perform One Round of an AES Encryption/Decryption Flow
5081 let Predicates = [HasAVX, HasAES] in {
5082 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
5083 int_x86_aesni_aesenc, 0>, VEX_4V;
5084 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
5085 int_x86_aesni_aesenclast, 0>, VEX_4V;
5086 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
5087 int_x86_aesni_aesdec, 0>, VEX_4V;
5088 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
5089 int_x86_aesni_aesdeclast, 0>, VEX_4V;
5092 let Constraints = "$src1 = $dst" in {
5093 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
5094 int_x86_aesni_aesenc>;
5095 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
5096 int_x86_aesni_aesenclast>;
5097 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
5098 int_x86_aesni_aesdec>;
5099 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
5100 int_x86_aesni_aesdeclast>;
5103 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
5104 (AESENCrr VR128:$src1, VR128:$src2)>;
5105 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
5106 (AESENCrm VR128:$src1, addr:$src2)>;
5107 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
5108 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
5109 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
5110 (AESENCLASTrm VR128:$src1, addr:$src2)>;
5111 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
5112 (AESDECrr VR128:$src1, VR128:$src2)>;
5113 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
5114 (AESDECrm VR128:$src1, addr:$src2)>;
5115 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
5116 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
5117 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
5118 (AESDECLASTrm VR128:$src1, addr:$src2)>;
5120 // Perform the AES InvMixColumn Transformation
5121 let Predicates = [HasAVX, HasAES] in {
5122 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5124 "vaesimc\t{$src1, $dst|$dst, $src1}",
5126 (int_x86_aesni_aesimc VR128:$src1))]>,
5128 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5129 (ins i128mem:$src1),
5130 "vaesimc\t{$src1, $dst|$dst, $src1}",
5132 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5135 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5137 "aesimc\t{$src1, $dst|$dst, $src1}",
5139 (int_x86_aesni_aesimc VR128:$src1))]>,
5141 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5142 (ins i128mem:$src1),
5143 "aesimc\t{$src1, $dst|$dst, $src1}",
5145 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5148 // AES Round Key Generation Assist
5149 let Predicates = [HasAVX, HasAES] in {
5150 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5151 (ins VR128:$src1, i8imm:$src2),
5152 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5154 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5156 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5157 (ins i128mem:$src1, i8imm:$src2),
5158 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5160 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5164 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5165 (ins VR128:$src1, i8imm:$src2),
5166 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5168 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5170 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5171 (ins i128mem:$src1, i8imm:$src2),
5172 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5174 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5178 //===----------------------------------------------------------------------===//
5179 // CLMUL Instructions
5180 //===----------------------------------------------------------------------===//
5182 // Only the AVX version of CLMUL instructions are described here.
5184 // Carry-less Multiplication instructions
5185 def VPCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5186 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5187 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5190 def VPCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5191 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5192 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5196 multiclass avx_vpclmul<string asm> {
5197 def rr : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
5198 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5201 def rm : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
5202 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5205 defm VPCLMULHQHQDQ : avx_vpclmul<"vpclmulhqhqdq">;
5206 defm VPCLMULHQLQDQ : avx_vpclmul<"vpclmulhqlqdq">;
5207 defm VPCLMULLQHQDQ : avx_vpclmul<"vpclmullqhqdq">;
5208 defm VPCLMULLQLQDQ : avx_vpclmul<"vpclmullqlqdq">;
5210 //===----------------------------------------------------------------------===//
5212 //===----------------------------------------------------------------------===//
5215 // Load from memory and broadcast to all elements of the destination operand
5216 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
5217 X86MemOperand x86memop, Intrinsic Int> :
5218 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5219 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5220 [(set RC:$dst, (Int addr:$src))]>, VEX;
5222 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
5223 int_x86_avx_vbroadcastss>;
5224 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
5225 int_x86_avx_vbroadcastss_256>;
5226 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
5227 int_x86_avx_vbroadcast_sd_256>;
5228 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
5229 int_x86_avx_vbroadcastf128_pd_256>;
5231 // Insert packed floating-point values
5232 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
5233 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
5234 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5236 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
5237 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
5238 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5241 // Extract packed floating-point values
5242 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
5243 (ins VR256:$src1, i8imm:$src2),
5244 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5246 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
5247 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
5248 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5251 // Conditional SIMD Packed Loads and Stores
5252 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
5253 Intrinsic IntLd, Intrinsic IntLd256,
5254 Intrinsic IntSt, Intrinsic IntSt256,
5255 PatFrag pf128, PatFrag pf256> {
5256 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
5257 (ins VR128:$src1, f128mem:$src2),
5258 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5259 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
5261 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
5262 (ins VR256:$src1, f256mem:$src2),
5263 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5264 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
5266 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
5267 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
5268 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5269 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
5270 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
5271 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
5272 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5273 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
5276 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
5277 int_x86_avx_maskload_ps,
5278 int_x86_avx_maskload_ps_256,
5279 int_x86_avx_maskstore_ps,
5280 int_x86_avx_maskstore_ps_256,
5281 memopv4f32, memopv8f32>;
5282 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
5283 int_x86_avx_maskload_pd,
5284 int_x86_avx_maskload_pd_256,
5285 int_x86_avx_maskstore_pd,
5286 int_x86_avx_maskstore_pd_256,
5287 memopv2f64, memopv4f64>;
5289 // Permute Floating-Point Values
5290 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
5291 RegisterClass RC, X86MemOperand x86memop_f,
5292 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
5293 Intrinsic IntVar, Intrinsic IntImm> {
5294 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
5295 (ins RC:$src1, RC:$src2),
5296 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5297 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
5298 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
5299 (ins RC:$src1, x86memop_i:$src2),
5300 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5301 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
5303 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
5304 (ins RC:$src1, i8imm:$src2),
5305 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5306 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
5307 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
5308 (ins x86memop_f:$src1, i8imm:$src2),
5309 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5310 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
5313 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
5314 memopv4f32, memopv4i32,
5315 int_x86_avx_vpermilvar_ps,
5316 int_x86_avx_vpermil_ps>;
5317 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
5318 memopv8f32, memopv8i32,
5319 int_x86_avx_vpermilvar_ps_256,
5320 int_x86_avx_vpermil_ps_256>;
5321 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
5322 memopv2f64, memopv2i64,
5323 int_x86_avx_vpermilvar_pd,
5324 int_x86_avx_vpermil_pd>;
5325 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
5326 memopv4f64, memopv4i64,
5327 int_x86_avx_vpermilvar_pd_256,
5328 int_x86_avx_vpermil_pd_256>;
5330 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
5331 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5332 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5334 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
5335 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
5336 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5339 // Zero All YMM registers
5340 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
5341 [(int_x86_avx_vzeroall)]>, VEX, VEX_L, Requires<[HasAVX]>;
5343 // Zero Upper bits of YMM registers
5344 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
5345 [(int_x86_avx_vzeroupper)]>, VEX, Requires<[HasAVX]>;
5347 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
5348 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5349 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
5350 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5351 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
5352 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5354 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
5356 (VINSERTF128rr VR256:$src1, VR128:$src2,
5357 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5358 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
5360 (VINSERTF128rr VR256:$src1, VR128:$src2,
5361 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5362 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
5364 (VINSERTF128rr VR256:$src1, VR128:$src2,
5365 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5366 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
5368 (VINSERTF128rr VR256:$src1, VR128:$src2,
5369 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5371 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
5372 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5373 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
5374 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5375 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
5376 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5378 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5379 (v4f32 (VEXTRACTF128rr
5380 (v8f32 VR256:$src1),
5381 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5382 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5383 (v2f64 (VEXTRACTF128rr
5384 (v4f64 VR256:$src1),
5385 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5386 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5387 (v4i32 (VEXTRACTF128rr
5388 (v8i32 VR256:$src1),
5389 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5390 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5391 (v2i64 (VEXTRACTF128rr
5392 (v4i64 VR256:$src1),
5393 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5395 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
5396 (VBROADCASTF128 addr:$src)>;
5398 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
5399 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5400 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
5401 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5402 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
5403 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5405 def : Pat<(int_x86_avx_vperm2f128_ps_256
5406 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
5407 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5408 def : Pat<(int_x86_avx_vperm2f128_pd_256
5409 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
5410 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5411 def : Pat<(int_x86_avx_vperm2f128_si_256
5412 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
5413 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5415 //===----------------------------------------------------------------------===//
5416 // SSE Shuffle pattern fragments
5417 //===----------------------------------------------------------------------===//
5419 // This is part of a "work in progress" refactoring. The idea is that all
5420 // vector shuffles are going to be translated into target specific nodes and
5421 // directly matched by the patterns below (which can be changed along the way)
5422 // The AVX version of some but not all of them are described here, and more
5423 // should come in a near future.
5425 // Shuffle with PSHUFD instruction folding loads. The first two patterns match
5426 // SSE2 loads, which are always promoted to v2i64. The last one should match
5427 // the SSE1 case, where the only legal load is v4f32, but there is no PSHUFD
5428 // in SSE2, how does it ever worked? Anyway, the pattern will remain here until
5429 // we investigate further.
5430 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5432 (VPSHUFDmi addr:$src1, imm:$imm)>, Requires<[HasAVX]>;
5433 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5435 (PSHUFDmi addr:$src1, imm:$imm)>;
5436 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
5438 (PSHUFDmi addr:$src1, imm:$imm)>; // FIXME: has this ever worked?
5440 // Shuffle with PSHUFD instruction.
5441 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5442 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5443 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5444 (PSHUFDri VR128:$src1, imm:$imm)>;
5446 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5447 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5448 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5449 (PSHUFDri VR128:$src1, imm:$imm)>;
5451 // Shuffle with SHUFPD instruction.
5452 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5453 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5454 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5455 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5456 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5457 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
5459 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5460 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5461 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5462 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5464 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5465 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5466 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5467 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5469 // Shuffle with SHUFPS instruction.
5470 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5471 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5472 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5473 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5474 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5475 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5477 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5478 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5479 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5480 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5482 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5483 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5484 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5485 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5486 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5487 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5489 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5490 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5491 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5492 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5494 // Shuffle with MOVHLPS instruction
5495 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
5496 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5497 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
5498 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5500 // Shuffle with MOVDDUP instruction
5501 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5502 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5503 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5504 (MOVDDUPrm addr:$src)>;
5506 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5507 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5508 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5509 (MOVDDUPrm addr:$src)>;
5511 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5512 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5513 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5514 (MOVDDUPrm addr:$src)>;
5516 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5517 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5518 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5519 (MOVDDUPrm addr:$src)>;
5521 def : Pat<(X86Movddup (bc_v2f64
5522 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5523 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5524 def : Pat<(X86Movddup (bc_v2f64
5525 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5526 (MOVDDUPrm addr:$src)>;
5529 // Shuffle with UNPCKLPS
5530 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
5531 (VUNPCKLPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5532 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
5533 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5534 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
5535 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
5537 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
5538 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5539 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
5540 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5541 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
5542 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
5544 // Shuffle with UNPCKHPS
5545 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
5546 (VUNPCKHPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5547 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
5548 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
5550 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
5551 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5552 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
5553 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
5555 // Shuffle with UNPCKLPD
5556 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
5557 (VUNPCKLPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5558 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
5559 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5560 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
5561 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
5563 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
5564 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5565 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
5566 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5567 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
5568 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
5570 // Shuffle with UNPCKHPD
5571 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
5572 (VUNPCKHPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5573 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
5574 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
5576 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
5577 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5578 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
5579 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
5581 // Shuffle with PUNPCKLBW
5582 def : Pat<(v16i8 (X86Punpcklbw VR128:$src1,
5583 (bc_v16i8 (memopv2i64 addr:$src2)))),
5584 (PUNPCKLBWrm VR128:$src1, addr:$src2)>;
5585 def : Pat<(v16i8 (X86Punpcklbw VR128:$src1, VR128:$src2)),
5586 (PUNPCKLBWrr VR128:$src1, VR128:$src2)>;
5588 // Shuffle with PUNPCKLWD
5589 def : Pat<(v8i16 (X86Punpcklwd VR128:$src1,
5590 (bc_v8i16 (memopv2i64 addr:$src2)))),
5591 (PUNPCKLWDrm VR128:$src1, addr:$src2)>;
5592 def : Pat<(v8i16 (X86Punpcklwd VR128:$src1, VR128:$src2)),
5593 (PUNPCKLWDrr VR128:$src1, VR128:$src2)>;
5595 // Shuffle with PUNPCKLDQ
5596 def : Pat<(v4i32 (X86Punpckldq VR128:$src1,
5597 (bc_v4i32 (memopv2i64 addr:$src2)))),
5598 (PUNPCKLDQrm VR128:$src1, addr:$src2)>;
5599 def : Pat<(v4i32 (X86Punpckldq VR128:$src1, VR128:$src2)),
5600 (PUNPCKLDQrr VR128:$src1, VR128:$src2)>;
5602 // Shuffle with PUNPCKLQDQ
5603 def : Pat<(v2i64 (X86Punpcklqdq VR128:$src1, (memopv2i64 addr:$src2))),
5604 (PUNPCKLQDQrm VR128:$src1, addr:$src2)>;
5605 def : Pat<(v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)),
5606 (PUNPCKLQDQrr VR128:$src1, VR128:$src2)>;
5608 // Shuffle with PUNPCKHBW
5609 def : Pat<(v16i8 (X86Punpckhbw VR128:$src1,
5610 (bc_v16i8 (memopv2i64 addr:$src2)))),
5611 (PUNPCKHBWrm VR128:$src1, addr:$src2)>;
5612 def : Pat<(v16i8 (X86Punpckhbw VR128:$src1, VR128:$src2)),
5613 (PUNPCKHBWrr VR128:$src1, VR128:$src2)>;
5615 // Shuffle with PUNPCKHWD
5616 def : Pat<(v8i16 (X86Punpckhwd VR128:$src1,
5617 (bc_v8i16 (memopv2i64 addr:$src2)))),
5618 (PUNPCKHWDrm VR128:$src1, addr:$src2)>;
5619 def : Pat<(v8i16 (X86Punpckhwd VR128:$src1, VR128:$src2)),
5620 (PUNPCKHWDrr VR128:$src1, VR128:$src2)>;
5622 // Shuffle with PUNPCKHDQ
5623 def : Pat<(v4i32 (X86Punpckhdq VR128:$src1,
5624 (bc_v4i32 (memopv2i64 addr:$src2)))),
5625 (PUNPCKHDQrm VR128:$src1, addr:$src2)>;
5626 def : Pat<(v4i32 (X86Punpckhdq VR128:$src1, VR128:$src2)),
5627 (PUNPCKHDQrr VR128:$src1, VR128:$src2)>;
5629 // Shuffle with PUNPCKHQDQ
5630 def : Pat<(v2i64 (X86Punpckhqdq VR128:$src1, (memopv2i64 addr:$src2))),
5631 (PUNPCKHQDQrm VR128:$src1, addr:$src2)>;
5632 def : Pat<(v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)),
5633 (PUNPCKHQDQrr VR128:$src1, VR128:$src2)>;
5635 // Shuffle with MOVLHPS
5636 def : Pat<(X86Movlhps VR128:$src1,
5637 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
5638 (MOVHPSrm VR128:$src1, addr:$src2)>;
5639 def : Pat<(X86Movlhps VR128:$src1,
5640 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
5641 (MOVHPSrm VR128:$src1, addr:$src2)>;
5642 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
5643 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
5644 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
5645 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
5646 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
5647 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
5649 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the problem
5650 // is during lowering, where it's not possible to recognize the load fold cause
5651 // it has two uses through a bitcast. One use disappears at isel time and the
5652 // fold opportunity reappears.
5653 def : Pat<(v2f64 (X86Movddup VR128:$src)),
5654 (UNPCKLPDrr VR128:$src, VR128:$src)>;
5656 // Shuffle with MOVLHPD
5657 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
5658 (scalar_to_vector (loadf64 addr:$src2)))),
5659 (MOVHPDrm VR128:$src1, addr:$src2)>;
5661 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
5662 // is during lowering, where it's not possible to recognize the load fold cause
5663 // it has two uses through a bitcast. One use disappears at isel time and the
5664 // fold opportunity reappears.
5665 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
5666 (scalar_to_vector (loadf64 addr:$src2)))),
5667 (MOVHPDrm VR128:$src1, addr:$src2)>;
5669 // Shuffle with MOVSS
5670 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
5671 (MOVSSrr VR128:$src1, FR32:$src2)>;
5672 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
5673 (MOVSSrr (v4i32 VR128:$src1),
5674 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
5675 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
5676 (MOVSSrr (v4f32 VR128:$src1),
5677 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
5678 // FIXME: Instead of a X86Movss there should be a X86Movlps here, the problem
5679 // is during lowering, where it's not possible to recognize the load fold cause
5680 // it has two uses through a bitcast. One use disappears at isel time and the
5681 // fold opportunity reappears.
5682 def : Pat<(X86Movss VR128:$src1,
5683 (bc_v4i32 (v2i64 (load addr:$src2)))),
5684 (MOVLPSrm VR128:$src1, addr:$src2)>;
5686 // Shuffle with MOVSD
5687 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
5688 (MOVSDrr VR128:$src1, FR64:$src2)>;
5689 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
5690 (MOVSDrr (v2i64 VR128:$src1),
5691 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
5692 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
5693 (MOVSDrr (v2f64 VR128:$src1),
5694 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
5695 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
5696 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
5697 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
5698 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
5700 // Shuffle with MOVSHDUP
5701 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5702 (MOVSHDUPrr VR128:$src)>;
5703 def : Pat<(X86Movshdup (bc_v4i32 (memopv2i64 addr:$src))),
5704 (MOVSHDUPrm addr:$src)>;
5706 def : Pat<(v4f32 (X86Movshdup VR128:$src)),
5707 (MOVSHDUPrr VR128:$src)>;
5708 def : Pat<(X86Movshdup (memopv4f32 addr:$src)),
5709 (MOVSHDUPrm addr:$src)>;
5711 // Shuffle with MOVSLDUP
5712 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5713 (MOVSLDUPrr VR128:$src)>;
5714 def : Pat<(X86Movsldup (bc_v4i32 (memopv2i64 addr:$src))),
5715 (MOVSLDUPrm addr:$src)>;
5717 def : Pat<(v4f32 (X86Movsldup VR128:$src)),
5718 (MOVSLDUPrr VR128:$src)>;
5719 def : Pat<(X86Movsldup (memopv4f32 addr:$src)),
5720 (MOVSLDUPrm addr:$src)>;
5722 // Shuffle with PSHUFHW
5723 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
5724 (PSHUFHWri VR128:$src, imm:$imm)>;
5725 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
5726 (PSHUFHWmi addr:$src, imm:$imm)>;
5728 // Shuffle with PSHUFLW
5729 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
5730 (PSHUFLWri VR128:$src, imm:$imm)>;
5731 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
5732 (PSHUFLWmi addr:$src, imm:$imm)>;
5734 // Shuffle with PALIGN
5735 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5736 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5737 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5738 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5739 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5740 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5741 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5742 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5744 // Shuffle with MOVLPS
5745 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
5746 (MOVLPSrm VR128:$src1, addr:$src2)>;
5747 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
5748 (MOVLPSrm VR128:$src1, addr:$src2)>;
5749 def : Pat<(X86Movlps VR128:$src1,
5750 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
5751 (MOVLPSrm VR128:$src1, addr:$src2)>;
5752 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
5753 // is during lowering, where it's not possible to recognize the load fold cause
5754 // it has two uses through a bitcast. One use disappears at isel time and the
5755 // fold opportunity reappears.
5756 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
5757 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
5759 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
5760 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
5762 // Shuffle with MOVLPD
5763 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
5764 (MOVLPDrm VR128:$src1, addr:$src2)>;
5765 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
5766 (MOVLPDrm VR128:$src1, addr:$src2)>;
5767 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
5768 (scalar_to_vector (loadf64 addr:$src2)))),
5769 (MOVLPDrm VR128:$src1, addr:$src2)>;
5771 // Extra patterns to match stores with MOVHPS/PD and MOVLPS/PD
5772 def : Pat<(store (f64 (vector_extract
5773 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))),addr:$dst),
5774 (MOVHPSmr addr:$dst, VR128:$src)>;
5775 def : Pat<(store (f64 (vector_extract
5776 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
5777 (MOVHPDmr addr:$dst, VR128:$src)>;
5779 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),addr:$src1),
5780 (MOVLPSmr addr:$src1, VR128:$src2)>;
5781 def : Pat<(store (v4i32 (X86Movlps
5782 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
5783 (MOVLPSmr addr:$src1, VR128:$src2)>;
5785 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
5786 (MOVLPDmr addr:$src1, VR128:$src2)>;
5787 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
5788 (MOVLPDmr addr:$src1, VR128:$src2)>;