1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 let isCommutable = 1 in
85 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
90 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
97 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
98 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
99 string asm, string SSEVer, string FPSizeStr,
100 X86MemOperand x86memop, PatFrag mem_frag,
101 Domain d, bit Is2Addr = 1> {
102 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
104 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
105 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
106 [(set RC:$dst, (!cast<Intrinsic>(
107 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
108 RC:$src1, RC:$src2))], d>;
109 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
111 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
113 [(set RC:$dst, (!cast<Intrinsic>(
114 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
115 RC:$src1, (mem_frag addr:$src2)))], d>;
118 //===----------------------------------------------------------------------===//
119 // Non-instruction patterns
120 //===----------------------------------------------------------------------===//
122 // A vector extract of the first f32/f64 position is a subregister copy
123 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
124 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
125 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
126 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
128 // A 128-bit subvector extract from the first 256-bit vector position
129 // is a subregister copy that needs no instruction.
130 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
131 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
132 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
133 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
135 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
136 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
137 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
138 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
140 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
141 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
142 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
143 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
145 // A 128-bit subvector insert to the first 256-bit vector position
146 // is a subregister copy that needs no instruction.
147 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
148 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
149 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
150 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
151 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
152 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
153 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
154 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
155 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
156 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
157 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
158 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
160 // Implicitly promote a 32-bit scalar to a vector.
161 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
162 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
163 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
164 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
165 // Implicitly promote a 64-bit scalar to a vector.
166 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
167 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
168 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
169 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
171 // Bitcasts between 128-bit vector types. Return the original type since
172 // no instruction is needed for the conversion
173 let Predicates = [HasXMMInt] in {
174 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
175 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
176 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
177 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
178 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
179 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
180 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
181 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
182 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
183 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
184 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
185 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
186 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
187 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
188 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
189 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
190 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
191 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
192 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
193 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
194 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
195 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
196 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
197 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
198 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
199 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
200 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
201 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
202 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
203 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
206 // Bitcasts between 256-bit vector types. Return the original type since
207 // no instruction is needed for the conversion
208 let Predicates = [HasAVX] in {
209 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
210 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
211 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
212 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
213 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
214 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
215 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
216 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
217 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
218 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
219 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
220 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
221 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
222 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
223 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
224 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
225 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
226 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
227 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
228 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
229 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
230 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
231 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
232 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
233 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
234 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
235 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
236 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
237 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
238 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
241 // Alias instructions that map fld0 to pxor for sse.
242 // FIXME: Set encoding to pseudo!
243 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
244 canFoldAsLoad = 1 in {
245 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
246 [(set FR32:$dst, fp32imm0)]>,
247 Requires<[HasSSE1]>, TB, OpSize;
248 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
249 [(set FR64:$dst, fpimm0)]>,
250 Requires<[HasSSE2]>, TB, OpSize;
251 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
252 [(set FR32:$dst, fp32imm0)]>,
253 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
254 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
255 [(set FR64:$dst, fpimm0)]>,
256 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
259 //===----------------------------------------------------------------------===//
260 // AVX & SSE - Zero/One Vectors
261 //===----------------------------------------------------------------------===//
263 // Alias instructions that map zero vector to pxor / xorp* for sse.
264 // We set canFoldAsLoad because this can be converted to a constant-pool
265 // load of an all-zeros value if folding it would be beneficial.
266 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
267 // JIT implementation, it does not expand the instructions below like
268 // X86MCInstLower does.
269 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
270 isCodeGenOnly = 1 in {
271 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
272 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
273 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
274 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
275 let ExeDomain = SSEPackedInt in
276 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
277 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
280 // The same as done above but for AVX. The 128-bit versions are the
281 // same, but re-encoded. The 256-bit does not support PI version, and
282 // doesn't need it because on sandy bridge the register is set to zero
283 // at the rename stage without using any execution unit, so SET0PSY
284 // and SET0PDY can be used for vector int instructions without penalty
285 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
286 // JIT implementatioan, it does not expand the instructions below like
287 // X86MCInstLower does.
288 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
289 isCodeGenOnly = 1, Predicates = [HasAVX] in {
290 def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
291 [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V;
292 def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
293 [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V;
294 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
295 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
296 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
297 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
298 let ExeDomain = SSEPackedInt in
299 def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
300 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
303 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
304 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
305 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
307 // AVX has no support for 256-bit integer instructions, but since the 128-bit
308 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
309 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
310 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
311 (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
313 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
314 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
315 (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
317 // We set canFoldAsLoad because this can be converted to a constant-pool
318 // load of an all-ones value if folding it would be beneficial.
319 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
320 // JIT implementation, it does not expand the instructions below like
321 // X86MCInstLower does.
322 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
323 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
324 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
325 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
326 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
327 isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in
328 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
329 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
332 //===----------------------------------------------------------------------===//
333 // SSE 1 & 2 - Move FP Scalar Instructions
335 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
336 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
337 // is used instead. Register-to-register movss/movsd is not modeled as an
338 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
339 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
340 //===----------------------------------------------------------------------===//
342 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
343 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
344 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
346 // Loading from memory automatically zeroing upper bits.
347 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
348 PatFrag mem_pat, string OpcodeStr> :
349 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
350 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
351 [(set RC:$dst, (mem_pat addr:$src))]>;
354 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
355 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
356 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
357 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
359 // For the disassembler
360 let isCodeGenOnly = 1 in {
361 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
362 (ins VR128:$src1, FR32:$src2),
363 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
365 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
366 (ins VR128:$src1, FR64:$src2),
367 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
371 let canFoldAsLoad = 1, isReMaterializable = 1 in {
372 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
373 let AddedComplexity = 20 in
374 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
377 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
378 "movss\t{$src, $dst|$dst, $src}",
379 [(store FR32:$src, addr:$dst)]>, XS, VEX;
380 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
381 "movsd\t{$src, $dst|$dst, $src}",
382 [(store FR64:$src, addr:$dst)]>, XD, VEX;
385 let Constraints = "$src1 = $dst" in {
386 def MOVSSrr : sse12_move_rr<FR32, v4f32,
387 "movss\t{$src2, $dst|$dst, $src2}">, XS;
388 def MOVSDrr : sse12_move_rr<FR64, v2f64,
389 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
391 // For the disassembler
392 let isCodeGenOnly = 1 in {
393 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
394 (ins VR128:$src1, FR32:$src2),
395 "movss\t{$src2, $dst|$dst, $src2}", []>, XS;
396 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
397 (ins VR128:$src1, FR64:$src2),
398 "movsd\t{$src2, $dst|$dst, $src2}", []>, XD;
402 let canFoldAsLoad = 1, isReMaterializable = 1 in {
403 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
405 let AddedComplexity = 20 in
406 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
409 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
410 "movss\t{$src, $dst|$dst, $src}",
411 [(store FR32:$src, addr:$dst)]>;
412 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
413 "movsd\t{$src, $dst|$dst, $src}",
414 [(store FR64:$src, addr:$dst)]>;
417 let Predicates = [HasSSE1] in {
418 let AddedComplexity = 15 in {
419 // Extract the low 32-bit value from one vector and insert it into another.
420 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
421 (MOVSSrr (v4f32 VR128:$src1),
422 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
423 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
424 (MOVSSrr (v4i32 VR128:$src1),
425 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
427 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
428 // MOVSS to the lower bits.
429 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
430 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
431 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
432 (MOVSSrr (v4f32 (V_SET0PS)),
433 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
434 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
435 (MOVSSrr (v4i32 (V_SET0PI)),
436 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
439 let AddedComplexity = 20 in {
440 // MOVSSrm zeros the high parts of the register; represent this
441 // with SUBREG_TO_REG.
442 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
443 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
444 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
445 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
446 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
447 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
450 // Extract and store.
451 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
454 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
456 // Shuffle with MOVSS
457 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
458 (MOVSSrr VR128:$src1, FR32:$src2)>;
459 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
460 (MOVSSrr (v4i32 VR128:$src1),
461 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
462 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
463 (MOVSSrr (v4f32 VR128:$src1),
464 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
467 let Predicates = [HasSSE2] in {
468 let AddedComplexity = 15 in {
469 // Extract the low 64-bit value from one vector and insert it into another.
470 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
471 (MOVSDrr (v2f64 VR128:$src1),
472 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
473 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
474 (MOVSDrr (v2i64 VR128:$src1),
475 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
477 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
478 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
479 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
480 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
481 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
483 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
484 // MOVSD to the lower bits.
485 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
486 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
489 let AddedComplexity = 20 in {
490 // MOVSDrm zeros the high parts of the register; represent this
491 // with SUBREG_TO_REG.
492 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
493 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
494 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
495 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
496 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
497 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
498 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
499 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
500 def : Pat<(v2f64 (X86vzload addr:$src)),
501 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
504 // Extract and store.
505 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
508 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
510 // Shuffle with MOVSD
511 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
512 (MOVSDrr VR128:$src1, FR64:$src2)>;
513 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
514 (MOVSDrr (v2i64 VR128:$src1),
515 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
516 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
517 (MOVSDrr (v2f64 VR128:$src1),
518 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
519 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
520 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
521 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
522 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
524 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
525 // is during lowering, where it's not possible to recognize the fold cause
526 // it has two uses through a bitcast. One use disappears at isel time and the
527 // fold opportunity reappears.
528 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
529 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
530 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
531 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
534 let Predicates = [HasAVX] in {
535 let AddedComplexity = 15 in {
536 // Extract the low 32-bit value from one vector and insert it into another.
537 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
538 (VMOVSSrr (v4f32 VR128:$src1),
539 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
540 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
541 (VMOVSSrr (v4i32 VR128:$src1),
542 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
544 // Extract the low 64-bit value from one vector and insert it into another.
545 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
546 (VMOVSDrr (v2f64 VR128:$src1),
547 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
548 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
549 (VMOVSDrr (v2i64 VR128:$src1),
550 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
552 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
553 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
554 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
555 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
556 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
558 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
559 // MOVS{S,D} to the lower bits.
560 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
561 (VMOVSSrr (v4f32 (AVX_SET0PS)), FR32:$src)>;
562 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
563 (VMOVSSrr (v4f32 (AVX_SET0PS)),
564 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
565 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
566 (VMOVSSrr (v4i32 (AVX_SET0PI)),
567 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
568 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
569 (VMOVSDrr (v2f64 (AVX_SET0PS)), FR64:$src)>;
572 let AddedComplexity = 20 in {
573 // MOVSSrm zeros the high parts of the register; represent this
574 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
575 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
576 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
577 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
578 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
579 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
580 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
582 // MOVSDrm zeros the high parts of the register; represent this
583 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
584 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
585 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
586 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
587 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
588 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
589 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
590 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
591 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
592 def : Pat<(v2f64 (X86vzload addr:$src)),
593 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
595 // Represent the same patterns above but in the form they appear for
597 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
598 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
599 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
600 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
601 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
602 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
604 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
605 (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
606 (SUBREG_TO_REG (i32 0),
607 (v4f32 (VMOVSSrr (v4f32 (AVX_SET0PS)), FR32:$src)),
609 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
610 (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
611 (SUBREG_TO_REG (i64 0),
612 (v2f64 (VMOVSDrr (v2f64 (AVX_SET0PS)), FR64:$src)),
615 // Extract and store.
616 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
619 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
620 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
623 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
625 // Shuffle with VMOVSS
626 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
627 (VMOVSSrr VR128:$src1, FR32:$src2)>;
628 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
629 (VMOVSSrr (v4i32 VR128:$src1),
630 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
631 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
632 (VMOVSSrr (v4f32 VR128:$src1),
633 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
635 // Shuffle with VMOVSD
636 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
637 (VMOVSDrr VR128:$src1, FR64:$src2)>;
638 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
639 (VMOVSDrr (v2i64 VR128:$src1),
640 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
641 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
642 (VMOVSDrr (v2f64 VR128:$src1),
643 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
644 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
645 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
647 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
648 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
651 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
652 // is during lowering, where it's not possible to recognize the fold cause
653 // it has two uses through a bitcast. One use disappears at isel time and the
654 // fold opportunity reappears.
655 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
656 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
658 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
659 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
663 //===----------------------------------------------------------------------===//
664 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
665 //===----------------------------------------------------------------------===//
667 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
668 X86MemOperand x86memop, PatFrag ld_frag,
669 string asm, Domain d,
670 bit IsReMaterializable = 1> {
671 let neverHasSideEffects = 1 in
672 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
673 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
674 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
675 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
676 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
677 [(set RC:$dst, (ld_frag addr:$src))], d>;
680 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
681 "movaps", SSEPackedSingle>, TB, VEX;
682 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
683 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
684 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
685 "movups", SSEPackedSingle>, TB, VEX;
686 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
687 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
689 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
690 "movaps", SSEPackedSingle>, TB, VEX;
691 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
692 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
693 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
694 "movups", SSEPackedSingle>, TB, VEX;
695 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
696 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
697 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
698 "movaps", SSEPackedSingle>, TB;
699 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
700 "movapd", SSEPackedDouble>, TB, OpSize;
701 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
702 "movups", SSEPackedSingle>, TB;
703 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
704 "movupd", SSEPackedDouble, 0>, TB, OpSize;
706 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
707 "movaps\t{$src, $dst|$dst, $src}",
708 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
709 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
710 "movapd\t{$src, $dst|$dst, $src}",
711 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
712 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
713 "movups\t{$src, $dst|$dst, $src}",
714 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
715 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
716 "movupd\t{$src, $dst|$dst, $src}",
717 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
718 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
719 "movaps\t{$src, $dst|$dst, $src}",
720 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)]>, VEX;
721 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
722 "movapd\t{$src, $dst|$dst, $src}",
723 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)]>, VEX;
724 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
725 "movups\t{$src, $dst|$dst, $src}",
726 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
727 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
728 "movupd\t{$src, $dst|$dst, $src}",
729 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
732 let isCodeGenOnly = 1 in {
733 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
735 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
736 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
738 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
739 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
741 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
742 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
744 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
745 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
747 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
748 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
750 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
751 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
753 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
754 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
756 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
759 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
760 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
761 (VMOVUPSYmr addr:$dst, VR256:$src)>;
763 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
764 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
765 (VMOVUPDYmr addr:$dst, VR256:$src)>;
767 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
768 "movaps\t{$src, $dst|$dst, $src}",
769 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
770 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
771 "movapd\t{$src, $dst|$dst, $src}",
772 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
773 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
774 "movups\t{$src, $dst|$dst, $src}",
775 [(store (v4f32 VR128:$src), addr:$dst)]>;
776 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
777 "movupd\t{$src, $dst|$dst, $src}",
778 [(store (v2f64 VR128:$src), addr:$dst)]>;
781 let isCodeGenOnly = 1 in {
782 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
783 "movaps\t{$src, $dst|$dst, $src}", []>;
784 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
785 "movapd\t{$src, $dst|$dst, $src}", []>;
786 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
787 "movups\t{$src, $dst|$dst, $src}", []>;
788 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
789 "movupd\t{$src, $dst|$dst, $src}", []>;
792 let Predicates = [HasAVX] in {
793 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
794 (VMOVUPSmr addr:$dst, VR128:$src)>;
795 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
796 (VMOVUPDmr addr:$dst, VR128:$src)>;
799 let Predicates = [HasSSE1] in
800 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
801 (MOVUPSmr addr:$dst, VR128:$src)>;
802 let Predicates = [HasSSE2] in
803 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
804 (MOVUPDmr addr:$dst, VR128:$src)>;
806 // Use movaps / movups for SSE integer load / store (one byte shorter).
807 // The instructions selected below are then converted to MOVDQA/MOVDQU
808 // during the SSE domain pass.
809 let Predicates = [HasSSE1] in {
810 def : Pat<(alignedloadv4i32 addr:$src),
811 (MOVAPSrm addr:$src)>;
812 def : Pat<(loadv4i32 addr:$src),
813 (MOVUPSrm addr:$src)>;
814 def : Pat<(alignedloadv2i64 addr:$src),
815 (MOVAPSrm addr:$src)>;
816 def : Pat<(loadv2i64 addr:$src),
817 (MOVUPSrm addr:$src)>;
819 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
820 (MOVAPSmr addr:$dst, VR128:$src)>;
821 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
822 (MOVAPSmr addr:$dst, VR128:$src)>;
823 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
824 (MOVAPSmr addr:$dst, VR128:$src)>;
825 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
826 (MOVAPSmr addr:$dst, VR128:$src)>;
827 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
828 (MOVUPSmr addr:$dst, VR128:$src)>;
829 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
830 (MOVUPSmr addr:$dst, VR128:$src)>;
831 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
832 (MOVUPSmr addr:$dst, VR128:$src)>;
833 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
834 (MOVUPSmr addr:$dst, VR128:$src)>;
837 // Use vmovaps/vmovups for AVX integer load/store.
838 let Predicates = [HasAVX] in {
839 // 128-bit load/store
840 def : Pat<(alignedloadv4i32 addr:$src),
841 (VMOVAPSrm addr:$src)>;
842 def : Pat<(loadv4i32 addr:$src),
843 (VMOVUPSrm addr:$src)>;
844 def : Pat<(alignedloadv2i64 addr:$src),
845 (VMOVAPSrm addr:$src)>;
846 def : Pat<(loadv2i64 addr:$src),
847 (VMOVUPSrm addr:$src)>;
849 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
850 (VMOVAPSmr addr:$dst, VR128:$src)>;
851 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
852 (VMOVAPSmr addr:$dst, VR128:$src)>;
853 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
854 (VMOVAPSmr addr:$dst, VR128:$src)>;
855 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
856 (VMOVAPSmr addr:$dst, VR128:$src)>;
857 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
858 (VMOVUPSmr addr:$dst, VR128:$src)>;
859 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
860 (VMOVUPSmr addr:$dst, VR128:$src)>;
861 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
862 (VMOVUPSmr addr:$dst, VR128:$src)>;
863 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
864 (VMOVUPSmr addr:$dst, VR128:$src)>;
866 // 256-bit load/store
867 def : Pat<(alignedloadv4i64 addr:$src),
868 (VMOVAPSYrm addr:$src)>;
869 def : Pat<(loadv4i64 addr:$src),
870 (VMOVUPSYrm addr:$src)>;
871 def : Pat<(alignedloadv8i32 addr:$src),
872 (VMOVAPSYrm addr:$src)>;
873 def : Pat<(loadv8i32 addr:$src),
874 (VMOVUPSYrm addr:$src)>;
875 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
876 (VMOVAPSYmr addr:$dst, VR256:$src)>;
877 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
878 (VMOVAPSYmr addr:$dst, VR256:$src)>;
879 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
880 (VMOVAPSYmr addr:$dst, VR256:$src)>;
881 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
882 (VMOVAPSYmr addr:$dst, VR256:$src)>;
883 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
884 (VMOVUPSYmr addr:$dst, VR256:$src)>;
885 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
886 (VMOVUPSYmr addr:$dst, VR256:$src)>;
887 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
888 (VMOVUPSYmr addr:$dst, VR256:$src)>;
889 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
890 (VMOVUPSYmr addr:$dst, VR256:$src)>;
893 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
894 // bits are disregarded. FIXME: Set encoding to pseudo!
895 let neverHasSideEffects = 1 in {
896 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
897 "movaps\t{$src, $dst|$dst, $src}", []>;
898 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
899 "movapd\t{$src, $dst|$dst, $src}", []>;
900 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
901 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
902 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
903 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
906 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
907 // bits are disregarded. FIXME: Set encoding to pseudo!
908 let canFoldAsLoad = 1, isReMaterializable = 1 in {
909 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
910 "movaps\t{$src, $dst|$dst, $src}",
911 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
912 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
913 "movapd\t{$src, $dst|$dst, $src}",
914 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
915 let isCodeGenOnly = 1 in {
916 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
917 "movaps\t{$src, $dst|$dst, $src}",
918 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>, VEX;
919 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
920 "movapd\t{$src, $dst|$dst, $src}",
921 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>, VEX;
925 //===----------------------------------------------------------------------===//
926 // SSE 1 & 2 - Move Low packed FP Instructions
927 //===----------------------------------------------------------------------===//
929 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
930 PatFrag mov_frag, string base_opc,
932 def PSrm : PI<opc, MRMSrcMem,
933 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
934 !strconcat(base_opc, "s", asm_opr),
937 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
938 SSEPackedSingle>, TB;
940 def PDrm : PI<opc, MRMSrcMem,
941 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
942 !strconcat(base_opc, "d", asm_opr),
943 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
944 (scalar_to_vector (loadf64 addr:$src2)))))],
945 SSEPackedDouble>, TB, OpSize;
948 let AddedComplexity = 20 in {
949 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
950 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
952 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
953 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
954 "\t{$src2, $dst|$dst, $src2}">;
957 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
958 "movlps\t{$src, $dst|$dst, $src}",
959 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
960 (iPTR 0))), addr:$dst)]>, VEX;
961 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
962 "movlpd\t{$src, $dst|$dst, $src}",
963 [(store (f64 (vector_extract (v2f64 VR128:$src),
964 (iPTR 0))), addr:$dst)]>, VEX;
965 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
966 "movlps\t{$src, $dst|$dst, $src}",
967 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
968 (iPTR 0))), addr:$dst)]>;
969 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
970 "movlpd\t{$src, $dst|$dst, $src}",
971 [(store (f64 (vector_extract (v2f64 VR128:$src),
972 (iPTR 0))), addr:$dst)]>;
974 let Predicates = [HasAVX] in {
975 let AddedComplexity = 20 in {
976 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
977 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
978 (VMOVLPSrm VR128:$src1, addr:$src2)>;
979 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
980 (VMOVLPSrm VR128:$src1, addr:$src2)>;
981 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
982 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
983 (VMOVLPDrm VR128:$src1, addr:$src2)>;
984 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
985 (VMOVLPDrm VR128:$src1, addr:$src2)>;
988 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
989 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
990 (VMOVLPSmr addr:$src1, VR128:$src2)>;
991 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
992 VR128:$src2)), addr:$src1),
993 (VMOVLPSmr addr:$src1, VR128:$src2)>;
995 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
996 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
997 (VMOVLPDmr addr:$src1, VR128:$src2)>;
998 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
999 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1001 // Shuffle with VMOVLPS
1002 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1003 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1004 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1005 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1006 def : Pat<(X86Movlps VR128:$src1,
1007 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1008 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1010 // Shuffle with VMOVLPD
1011 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1012 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1013 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1014 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1015 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1016 (scalar_to_vector (loadf64 addr:$src2)))),
1017 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1020 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1022 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1023 def : Pat<(store (v4i32 (X86Movlps
1024 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1025 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1026 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1028 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1029 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1031 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1034 let Predicates = [HasSSE1] in {
1035 let AddedComplexity = 20 in {
1036 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
1037 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
1038 (MOVLPSrm VR128:$src1, addr:$src2)>;
1039 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
1040 (MOVLPSrm VR128:$src1, addr:$src2)>;
1043 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1044 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1045 (MOVLPSmr addr:$src1, VR128:$src2)>;
1046 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
1047 VR128:$src2)), addr:$src1),
1048 (MOVLPSmr addr:$src1, VR128:$src2)>;
1050 // Shuffle with MOVLPS
1051 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1052 (MOVLPSrm VR128:$src1, addr:$src2)>;
1053 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1054 (MOVLPSrm VR128:$src1, addr:$src2)>;
1055 def : Pat<(X86Movlps VR128:$src1,
1056 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1057 (MOVLPSrm VR128:$src1, addr:$src2)>;
1060 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1062 (MOVLPSmr addr:$src1, VR128:$src2)>;
1063 def : Pat<(store (v4i32 (X86Movlps
1064 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1066 (MOVLPSmr addr:$src1, VR128:$src2)>;
1069 let Predicates = [HasSSE2] in {
1070 let AddedComplexity = 20 in {
1071 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
1072 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
1073 (MOVLPDrm VR128:$src1, addr:$src2)>;
1074 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
1075 (MOVLPDrm VR128:$src1, addr:$src2)>;
1078 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
1079 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1080 (MOVLPDmr addr:$src1, VR128:$src2)>;
1081 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1082 (MOVLPDmr addr:$src1, VR128:$src2)>;
1084 // Shuffle with MOVLPD
1085 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1086 (MOVLPDrm VR128:$src1, addr:$src2)>;
1087 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1088 (MOVLPDrm VR128:$src1, addr:$src2)>;
1089 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1090 (scalar_to_vector (loadf64 addr:$src2)))),
1091 (MOVLPDrm VR128:$src1, addr:$src2)>;
1094 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1096 (MOVLPDmr addr:$src1, VR128:$src2)>;
1097 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1099 (MOVLPDmr addr:$src1, VR128:$src2)>;
1102 //===----------------------------------------------------------------------===//
1103 // SSE 1 & 2 - Move Hi packed FP Instructions
1104 //===----------------------------------------------------------------------===//
1106 let AddedComplexity = 20 in {
1107 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1108 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
1110 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1111 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1112 "\t{$src2, $dst|$dst, $src2}">;
1115 // v2f64 extract element 1 is always custom lowered to unpack high to low
1116 // and extract element 0 so the non-store version isn't too horrible.
1117 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1118 "movhps\t{$src, $dst|$dst, $src}",
1119 [(store (f64 (vector_extract
1120 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1121 (undef)), (iPTR 0))), addr:$dst)]>,
1123 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1124 "movhpd\t{$src, $dst|$dst, $src}",
1125 [(store (f64 (vector_extract
1126 (v2f64 (unpckh VR128:$src, (undef))),
1127 (iPTR 0))), addr:$dst)]>,
1129 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1130 "movhps\t{$src, $dst|$dst, $src}",
1131 [(store (f64 (vector_extract
1132 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1133 (undef)), (iPTR 0))), addr:$dst)]>;
1134 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1135 "movhpd\t{$src, $dst|$dst, $src}",
1136 [(store (f64 (vector_extract
1137 (v2f64 (unpckh VR128:$src, (undef))),
1138 (iPTR 0))), addr:$dst)]>;
1140 let Predicates = [HasAVX] in {
1142 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1143 (VMOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1144 def : Pat<(X86Movlhps VR128:$src1,
1145 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1146 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1147 def : Pat<(X86Movlhps VR128:$src1,
1148 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1149 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1151 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
1152 // is during lowering, where it's not possible to recognize the load fold cause
1153 // it has two uses through a bitcast. One use disappears at isel time and the
1154 // fold opportunity reappears.
1155 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
1156 (scalar_to_vector (loadf64 addr:$src2)))),
1157 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1159 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1160 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1161 (scalar_to_vector (loadf64 addr:$src2)))),
1162 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1165 def : Pat<(store (f64 (vector_extract
1166 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1167 (VMOVHPSmr addr:$dst, VR128:$src)>;
1168 def : Pat<(store (f64 (vector_extract
1169 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1170 (VMOVHPDmr addr:$dst, VR128:$src)>;
1173 let Predicates = [HasSSE1] in {
1175 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1176 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1177 def : Pat<(X86Movlhps VR128:$src1,
1178 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1179 (MOVHPSrm VR128:$src1, addr:$src2)>;
1180 def : Pat<(X86Movlhps VR128:$src1,
1181 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1182 (MOVHPSrm VR128:$src1, addr:$src2)>;
1185 def : Pat<(store (f64 (vector_extract
1186 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1187 (MOVHPSmr addr:$dst, VR128:$src)>;
1190 let Predicates = [HasSSE2] in {
1191 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
1192 // is during lowering, where it's not possible to recognize the load fold cause
1193 // it has two uses through a bitcast. One use disappears at isel time and the
1194 // fold opportunity reappears.
1195 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
1196 (scalar_to_vector (loadf64 addr:$src2)))),
1197 (MOVHPDrm VR128:$src1, addr:$src2)>;
1199 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1200 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1201 (scalar_to_vector (loadf64 addr:$src2)))),
1202 (MOVHPDrm VR128:$src1, addr:$src2)>;
1205 def : Pat<(store (f64 (vector_extract
1206 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
1207 (MOVHPDmr addr:$dst, VR128:$src)>;
1210 //===----------------------------------------------------------------------===//
1211 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1212 //===----------------------------------------------------------------------===//
1214 let AddedComplexity = 20 in {
1215 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1216 (ins VR128:$src1, VR128:$src2),
1217 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1219 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
1221 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1222 (ins VR128:$src1, VR128:$src2),
1223 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1225 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
1228 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1229 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1230 (ins VR128:$src1, VR128:$src2),
1231 "movlhps\t{$src2, $dst|$dst, $src2}",
1233 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
1234 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1235 (ins VR128:$src1, VR128:$src2),
1236 "movhlps\t{$src2, $dst|$dst, $src2}",
1238 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
1241 let Predicates = [HasAVX] in {
1243 let AddedComplexity = 20 in {
1244 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1245 (VMOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1246 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1247 (VMOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1249 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
1250 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
1251 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1253 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
1254 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1255 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1256 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1257 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1258 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1261 let AddedComplexity = 20 in {
1262 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
1263 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
1264 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1266 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
1267 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
1268 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
1269 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
1270 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
1273 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
1274 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1275 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1276 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1279 let Predicates = [HasSSE1] in {
1281 let AddedComplexity = 20 in {
1282 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1283 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1284 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1285 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1287 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
1288 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
1289 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1291 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
1292 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1293 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1294 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1295 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1296 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1299 let AddedComplexity = 20 in {
1300 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
1301 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
1302 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1304 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
1305 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
1306 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
1307 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
1308 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
1311 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
1312 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1313 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1314 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1317 //===----------------------------------------------------------------------===//
1318 // SSE 1 & 2 - Conversion Instructions
1319 //===----------------------------------------------------------------------===//
1321 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1322 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1324 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1325 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
1326 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1327 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
1330 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1331 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1332 string asm, Domain d> {
1333 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1334 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
1335 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1336 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
1339 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1340 X86MemOperand x86memop, string asm> {
1341 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1342 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1343 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1344 (ins DstRC:$src1, x86memop:$src),
1345 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1348 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1349 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
1350 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1351 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1353 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1354 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
1355 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1356 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
1359 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1360 // register, but the same isn't true when only using memory operands,
1361 // provide other assembly "l" and "q" forms to address this explicitly
1362 // where appropriate to do so.
1363 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
1365 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
1367 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
1369 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
1371 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
1374 let Predicates = [HasAVX] in {
1375 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1376 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1377 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1378 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1379 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1380 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1381 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1382 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1384 def : Pat<(f32 (sint_to_fp GR32:$src)),
1385 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1386 def : Pat<(f32 (sint_to_fp GR64:$src)),
1387 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1388 def : Pat<(f64 (sint_to_fp GR32:$src)),
1389 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1390 def : Pat<(f64 (sint_to_fp GR64:$src)),
1391 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1394 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1395 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
1396 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1397 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1398 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1399 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
1400 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1401 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1402 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1403 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
1404 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1405 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1406 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1407 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
1408 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1409 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1411 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1412 // and/or XMM operand(s).
1414 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1415 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
1417 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1418 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1419 [(set DstRC:$dst, (Int SrcRC:$src))]>;
1420 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
1421 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1422 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
1425 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1426 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1427 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
1428 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1430 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1431 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1432 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
1433 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1434 (ins DstRC:$src1, x86memop:$src2),
1436 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1437 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1438 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
1441 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1442 f128mem, load, "cvtsd2si">, XD, VEX;
1443 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1444 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
1447 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
1448 // Get rid of this hack or rename the intrinsics, there are several
1449 // intructions that only match with the intrinsic form, why create duplicates
1450 // to let them be recognized by the assembler?
1451 let Pattern = []<dag> in {
1452 defm VCVTSD2SI : sse12_cvt_s<0x2D, FR64, GR32, undef, f64mem, load,
1453 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
1454 defm VCVTSD2SI64 : sse12_cvt_s<0x2D, FR64, GR64, undef, f64mem, load,
1455 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
1457 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1458 f128mem, load, "cvtsd2si{l}">, XD;
1459 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1460 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
1463 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1464 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
1465 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1466 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
1468 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1469 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
1470 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1471 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
1474 let Constraints = "$src1 = $dst" in {
1475 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1476 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1478 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1479 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1480 "cvtsi2ss{q}">, XS, REX_W;
1481 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1482 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1484 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1485 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1486 "cvtsi2sd">, XD, REX_W;
1491 // Aliases for intrinsics
1492 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1493 f32mem, load, "cvttss2si">, XS, VEX;
1494 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1495 int_x86_sse_cvttss2si64, f32mem, load,
1496 "cvttss2si">, XS, VEX, VEX_W;
1497 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1498 f128mem, load, "cvttsd2si">, XD, VEX;
1499 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1500 int_x86_sse2_cvttsd2si64, f128mem, load,
1501 "cvttsd2si">, XD, VEX, VEX_W;
1502 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1503 f32mem, load, "cvttss2si">, XS;
1504 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1505 int_x86_sse_cvttss2si64, f32mem, load,
1506 "cvttss2si{q}">, XS, REX_W;
1507 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1508 f128mem, load, "cvttsd2si">, XD;
1509 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1510 int_x86_sse2_cvttsd2si64, f128mem, load,
1511 "cvttsd2si{q}">, XD, REX_W;
1513 let Pattern = []<dag> in {
1514 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
1515 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
1516 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
1517 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1519 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
1520 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1521 SSEPackedSingle>, TB, VEX;
1522 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
1523 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1524 SSEPackedSingle>, TB, VEX;
1527 let Pattern = []<dag> in {
1528 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
1529 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
1530 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
1531 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1532 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
1533 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1534 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
1537 let Predicates = [HasSSE1] in {
1538 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1539 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1540 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1541 (CVTSS2SIrm addr:$src)>;
1542 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1543 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1544 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1545 (CVTSS2SI64rm addr:$src)>;
1548 let Predicates = [HasAVX] in {
1549 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1550 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1551 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1552 (VCVTSS2SIrm addr:$src)>;
1553 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1554 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1555 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1556 (VCVTSS2SI64rm addr:$src)>;
1561 // Convert scalar double to scalar single
1562 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1563 (ins FR64:$src1, FR64:$src2),
1564 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
1566 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1567 (ins FR64:$src1, f64mem:$src2),
1568 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1569 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
1571 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1574 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1575 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1576 [(set FR32:$dst, (fround FR64:$src))]>;
1577 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1578 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1579 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1580 Requires<[HasSSE2, OptForSize]>;
1582 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1583 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
1585 let Constraints = "$src1 = $dst" in
1586 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1587 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
1589 // Convert scalar single to scalar double
1590 // SSE2 instructions with XS prefix
1591 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1592 (ins FR32:$src1, FR32:$src2),
1593 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1594 []>, XS, Requires<[HasAVX]>, VEX_4V;
1595 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1596 (ins FR32:$src1, f32mem:$src2),
1597 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1598 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
1600 let Predicates = [HasAVX] in {
1601 def : Pat<(f64 (fextend FR32:$src)),
1602 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
1603 def : Pat<(fextend (loadf32 addr:$src)),
1604 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1605 def : Pat<(extloadf32 addr:$src),
1606 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1609 def : Pat<(extloadf32 addr:$src),
1610 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (MOVSSrm addr:$src))>,
1611 Requires<[HasAVX, OptForSpeed]>;
1613 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1614 "cvtss2sd\t{$src, $dst|$dst, $src}",
1615 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1616 Requires<[HasSSE2]>;
1617 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1618 "cvtss2sd\t{$src, $dst|$dst, $src}",
1619 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1620 Requires<[HasSSE2, OptForSize]>;
1622 // extload f32 -> f64. This matches load+fextend because we have a hack in
1623 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1625 // Since these loads aren't folded into the fextend, we have to match it
1627 def : Pat<(fextend (loadf32 addr:$src)),
1628 (CVTSS2SDrm addr:$src)>, Requires<[HasSSE2]>;
1629 def : Pat<(extloadf32 addr:$src),
1630 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1632 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1633 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1634 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1635 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1636 VR128:$src2))]>, XS, VEX_4V,
1638 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1639 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1640 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1641 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1642 (load addr:$src2)))]>, XS, VEX_4V,
1644 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1645 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1646 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1647 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1648 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1649 VR128:$src2))]>, XS,
1650 Requires<[HasSSE2]>;
1651 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1652 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1653 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1654 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1655 (load addr:$src2)))]>, XS,
1656 Requires<[HasSSE2]>;
1659 // Convert doubleword to packed single/double fp
1660 // SSE2 instructions without OpSize prefix
1661 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1662 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1663 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1664 TB, VEX, Requires<[HasAVX]>;
1665 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1666 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1667 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1668 (bitconvert (memopv2i64 addr:$src))))]>,
1669 TB, VEX, Requires<[HasAVX]>;
1670 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1671 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1672 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1673 TB, Requires<[HasSSE2]>;
1674 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1675 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1676 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1677 (bitconvert (memopv2i64 addr:$src))))]>,
1678 TB, Requires<[HasSSE2]>;
1680 // FIXME: why the non-intrinsic version is described as SSE3?
1681 // SSE2 instructions with XS prefix
1682 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1683 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1684 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1685 XS, VEX, Requires<[HasAVX]>;
1686 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1687 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1688 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1689 (bitconvert (memopv2i64 addr:$src))))]>,
1690 XS, VEX, Requires<[HasAVX]>;
1691 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1692 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1693 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1694 XS, Requires<[HasSSE2]>;
1695 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1696 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1697 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1698 (bitconvert (memopv2i64 addr:$src))))]>,
1699 XS, Requires<[HasSSE2]>;
1702 // Convert packed single/double fp to doubleword
1703 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1704 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1705 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1706 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1707 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1708 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1709 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1710 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1711 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1712 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1713 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1714 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1716 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1717 "cvtps2dq\t{$src, $dst|$dst, $src}",
1718 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
1720 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1722 "cvtps2dq\t{$src, $dst|$dst, $src}",
1723 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1724 (memop addr:$src)))]>, VEX;
1725 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1726 "cvtps2dq\t{$src, $dst|$dst, $src}",
1727 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1728 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1729 "cvtps2dq\t{$src, $dst|$dst, $src}",
1730 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1731 (memop addr:$src)))]>;
1733 // SSE2 packed instructions with XD prefix
1734 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1735 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1736 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1737 XD, VEX, Requires<[HasAVX]>;
1738 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1739 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1740 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1741 (memop addr:$src)))]>,
1742 XD, VEX, Requires<[HasAVX]>;
1743 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1744 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1745 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1746 XD, Requires<[HasSSE2]>;
1747 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1748 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1749 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1750 (memop addr:$src)))]>,
1751 XD, Requires<[HasSSE2]>;
1754 // Convert with truncation packed single/double fp to doubleword
1755 // SSE2 packed instructions with XS prefix
1756 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1757 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1758 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1759 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1760 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1761 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1762 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1763 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1764 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1765 "cvttps2dq\t{$src, $dst|$dst, $src}",
1767 (int_x86_sse2_cvttps2dq VR128:$src))]>;
1768 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1769 "cvttps2dq\t{$src, $dst|$dst, $src}",
1771 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
1773 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1774 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1776 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1777 XS, VEX, Requires<[HasAVX]>;
1778 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1779 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1780 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1781 (memop addr:$src)))]>,
1782 XS, VEX, Requires<[HasAVX]>;
1784 let Predicates = [HasSSE2] in {
1785 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1786 (Int_CVTDQ2PSrr VR128:$src)>;
1787 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1788 (CVTTPS2DQrr VR128:$src)>;
1791 let Predicates = [HasAVX] in {
1792 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1793 (Int_VCVTDQ2PSrr VR128:$src)>;
1794 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1795 (VCVTTPS2DQrr VR128:$src)>;
1796 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1797 (VCVTDQ2PSYrr VR256:$src)>;
1798 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1799 (VCVTTPS2DQYrr VR256:$src)>;
1802 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1803 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1805 (int_x86_sse2_cvttpd2dq VR128:$src))]>, VEX;
1806 let isCodeGenOnly = 1 in
1807 def VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1808 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1809 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1810 (memop addr:$src)))]>, VEX;
1811 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1812 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1813 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1814 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1815 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1816 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1817 (memop addr:$src)))]>;
1819 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1820 // register, but the same isn't true when using memory operands instead.
1821 // Provide other assembly rr and rm forms to address this explicitly.
1822 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1823 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1826 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1827 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1828 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1829 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1832 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1833 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
1834 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1835 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1837 // Convert packed single to packed double
1838 let Predicates = [HasAVX] in {
1839 // SSE2 instructions without OpSize prefix
1840 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1841 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1842 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1843 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1844 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1845 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1846 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1847 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1849 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1850 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1851 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1852 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1854 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1855 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1856 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1857 TB, VEX, Requires<[HasAVX]>;
1858 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1859 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1860 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1861 (load addr:$src)))]>,
1862 TB, VEX, Requires<[HasAVX]>;
1863 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1864 "cvtps2pd\t{$src, $dst|$dst, $src}",
1865 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1866 TB, Requires<[HasSSE2]>;
1867 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1868 "cvtps2pd\t{$src, $dst|$dst, $src}",
1869 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1870 (load addr:$src)))]>,
1871 TB, Requires<[HasSSE2]>;
1873 // Convert packed double to packed single
1874 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1875 // register, but the same isn't true when using memory operands instead.
1876 // Provide other assembly rr and rm forms to address this explicitly.
1877 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1878 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1879 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1880 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1883 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1884 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1885 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1886 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1889 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1890 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1891 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1892 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1893 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1894 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1895 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1896 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1899 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1900 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1901 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1902 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1904 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1905 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1906 (memop addr:$src)))]>;
1907 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1908 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1909 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1910 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1911 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1912 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1913 (memop addr:$src)))]>;
1915 // AVX 256-bit register conversion intrinsics
1916 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1917 // whenever possible to avoid declaring two versions of each one.
1918 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1919 (VCVTDQ2PSYrr VR256:$src)>;
1920 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
1921 (VCVTDQ2PSYrm addr:$src)>;
1923 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1924 (VCVTPD2PSYrr VR256:$src)>;
1925 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1926 (VCVTPD2PSYrm addr:$src)>;
1928 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1929 (VCVTPS2DQYrr VR256:$src)>;
1930 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1931 (VCVTPS2DQYrm addr:$src)>;
1933 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1934 (VCVTPS2PDYrr VR128:$src)>;
1935 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1936 (VCVTPS2PDYrm addr:$src)>;
1938 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1939 (VCVTTPD2DQYrr VR256:$src)>;
1940 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1941 (VCVTTPD2DQYrm addr:$src)>;
1943 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1944 (VCVTTPS2DQYrr VR256:$src)>;
1945 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1946 (VCVTTPS2DQYrm addr:$src)>;
1948 // Match fround and fextend for 128/256-bit conversions
1949 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
1950 (VCVTPD2PSYrr VR256:$src)>;
1951 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
1952 (VCVTPD2PSYrm addr:$src)>;
1954 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
1955 (VCVTPS2PDYrr VR128:$src)>;
1956 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
1957 (VCVTPS2PDYrm addr:$src)>;
1959 //===----------------------------------------------------------------------===//
1960 // SSE 1 & 2 - Compare Instructions
1961 //===----------------------------------------------------------------------===//
1963 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1964 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1965 string asm, string asm_alt> {
1966 let isAsmParserOnly = 1 in {
1967 def rr : SIi8<0xC2, MRMSrcReg,
1968 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1971 def rm : SIi8<0xC2, MRMSrcMem,
1972 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1976 // Accept explicit immediate argument form instead of comparison code.
1977 def rr_alt : SIi8<0xC2, MRMSrcReg,
1978 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1981 def rm_alt : SIi8<0xC2, MRMSrcMem,
1982 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1986 let neverHasSideEffects = 1 in {
1987 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1988 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1989 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1991 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1992 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1993 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1997 let Constraints = "$src1 = $dst" in {
1998 def CMPSSrr : SIi8<0xC2, MRMSrcReg,
1999 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc),
2000 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2001 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2,
2003 def CMPSSrm : SIi8<0xC2, MRMSrcMem,
2004 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc),
2005 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2006 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1),
2007 (loadf32 addr:$src2), imm:$cc))]>, XS;
2008 def CMPSDrr : SIi8<0xC2, MRMSrcReg,
2009 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc),
2010 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2011 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2,
2013 def CMPSDrm : SIi8<0xC2, MRMSrcMem,
2014 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc),
2015 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2016 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2),
2019 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
2020 def CMPSSrr_alt : SIi8<0xC2, MRMSrcReg,
2021 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
2022 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
2023 def CMPSSrm_alt : SIi8<0xC2, MRMSrcMem,
2024 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
2025 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
2026 def CMPSDrr_alt : SIi8<0xC2, MRMSrcReg,
2027 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
2028 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
2029 def CMPSDrm_alt : SIi8<0xC2, MRMSrcMem,
2030 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
2031 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
2034 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
2035 Intrinsic Int, string asm> {
2036 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2037 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
2038 [(set VR128:$dst, (Int VR128:$src1,
2039 VR128:$src, imm:$cc))]>;
2040 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2041 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
2042 [(set VR128:$dst, (Int VR128:$src1,
2043 (load addr:$src), imm:$cc))]>;
2046 // Aliases to match intrinsics which expect XMM operand(s).
2047 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2048 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
2050 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2051 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
2053 let Constraints = "$src1 = $dst" in {
2054 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2055 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
2056 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2057 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
2061 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2062 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2063 ValueType vt, X86MemOperand x86memop,
2064 PatFrag ld_frag, string OpcodeStr, Domain d> {
2065 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2066 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2067 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
2068 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2069 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2070 [(set EFLAGS, (OpNode (vt RC:$src1),
2071 (ld_frag addr:$src2)))], d>;
2074 let Defs = [EFLAGS] in {
2075 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2076 "ucomiss", SSEPackedSingle>, TB, VEX;
2077 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2078 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2079 let Pattern = []<dag> in {
2080 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2081 "comiss", SSEPackedSingle>, TB, VEX;
2082 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2083 "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2086 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2087 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2088 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2089 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2091 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2092 load, "comiss", SSEPackedSingle>, TB, VEX;
2093 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2094 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2095 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2096 "ucomiss", SSEPackedSingle>, TB;
2097 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2098 "ucomisd", SSEPackedDouble>, TB, OpSize;
2100 let Pattern = []<dag> in {
2101 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2102 "comiss", SSEPackedSingle>, TB;
2103 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2104 "comisd", SSEPackedDouble>, TB, OpSize;
2107 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2108 load, "ucomiss", SSEPackedSingle>, TB;
2109 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2110 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2112 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2113 "comiss", SSEPackedSingle>, TB;
2114 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2115 "comisd", SSEPackedDouble>, TB, OpSize;
2116 } // Defs = [EFLAGS]
2118 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
2119 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2120 Intrinsic Int, string asm, string asm_alt,
2122 let isAsmParserOnly = 1 in {
2123 def rri : PIi8<0xC2, MRMSrcReg,
2124 (outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
2125 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))], d>;
2126 def rmi : PIi8<0xC2, MRMSrcMem,
2127 (outs RC:$dst), (ins RC:$src1, f128mem:$src2, SSECC:$cc), asm,
2128 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))], d>;
2131 // Accept explicit immediate argument form instead of comparison code.
2132 def rri_alt : PIi8<0xC2, MRMSrcReg,
2133 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2135 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2136 (outs RC:$dst), (ins RC:$src1, f128mem:$src2, i8imm:$cc),
2140 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2141 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2142 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2143 SSEPackedSingle>, TB, VEX_4V;
2144 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2145 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2146 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2147 SSEPackedDouble>, TB, OpSize, VEX_4V;
2148 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
2149 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2150 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2151 SSEPackedSingle>, TB, VEX_4V;
2152 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
2153 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2154 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2155 SSEPackedDouble>, TB, OpSize, VEX_4V;
2156 let Constraints = "$src1 = $dst" in {
2157 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2158 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2159 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2160 SSEPackedSingle>, TB;
2161 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2162 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2163 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2164 SSEPackedDouble>, TB, OpSize;
2167 let Predicates = [HasSSE1] in {
2168 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2169 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2170 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2171 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2174 let Predicates = [HasSSE2] in {
2175 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2176 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2177 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2178 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2181 let Predicates = [HasAVX] in {
2182 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2183 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2184 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2185 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2186 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2187 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2188 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2189 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2191 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2192 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2193 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2194 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2195 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2196 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2197 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2198 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2201 //===----------------------------------------------------------------------===//
2202 // SSE 1 & 2 - Shuffle Instructions
2203 //===----------------------------------------------------------------------===//
2205 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2206 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2207 ValueType vt, string asm, PatFrag mem_frag,
2208 Domain d, bit IsConvertibleToThreeAddress = 0> {
2209 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2210 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
2211 [(set RC:$dst, (vt (shufp:$src3
2212 RC:$src1, (mem_frag addr:$src2))))], d>;
2213 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2214 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2215 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2217 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
2220 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2221 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2222 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2223 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2224 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2225 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2226 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2227 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2228 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2229 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2230 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2231 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2233 let Constraints = "$src1 = $dst" in {
2234 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2235 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2236 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2238 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2239 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2240 memopv2f64, SSEPackedDouble>, TB, OpSize;
2243 let Predicates = [HasSSE1] in {
2244 def : Pat<(v4f32 (X86Shufps VR128:$src1,
2245 (memopv4f32 addr:$src2), (i8 imm:$imm))),
2246 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2247 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2248 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2249 def : Pat<(v4i32 (X86Shufps VR128:$src1,
2250 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2251 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2252 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2253 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2254 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2255 // fall back to this for SSE1)
2256 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2257 (SHUFPSrri VR128:$src2, VR128:$src1,
2258 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2259 // Special unary SHUFPSrri case.
2260 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2261 (SHUFPSrri VR128:$src1, VR128:$src1,
2262 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2265 let Predicates = [HasSSE2] in {
2266 // Special binary v4i32 shuffle cases with SHUFPS.
2267 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2268 (SHUFPSrri VR128:$src1, VR128:$src2,
2269 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2270 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
2271 (bc_v4i32 (memopv2i64 addr:$src2)))),
2272 (SHUFPSrmi VR128:$src1, addr:$src2,
2273 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2274 // Special unary SHUFPDrri cases.
2275 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2276 (SHUFPDrri VR128:$src1, VR128:$src1,
2277 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2278 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2279 (SHUFPDrri VR128:$src1, VR128:$src1,
2280 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2281 // Special binary v2i64 shuffle cases using SHUFPDrri.
2282 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2283 (SHUFPDrri VR128:$src1, VR128:$src2,
2284 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2285 // Generic SHUFPD patterns
2286 def : Pat<(v2f64 (X86Shufps VR128:$src1,
2287 (memopv2f64 addr:$src2), (i8 imm:$imm))),
2288 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2289 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2290 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2291 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2292 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2295 let Predicates = [HasAVX] in {
2296 def : Pat<(v4f32 (X86Shufps VR128:$src1,
2297 (memopv4f32 addr:$src2), (i8 imm:$imm))),
2298 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2299 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2300 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2301 def : Pat<(v4i32 (X86Shufps VR128:$src1,
2302 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2303 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2304 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2305 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2306 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2307 // fall back to this for SSE1)
2308 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2309 (VSHUFPSrri VR128:$src2, VR128:$src1,
2310 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2311 // Special unary SHUFPSrri case.
2312 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2313 (VSHUFPSrri VR128:$src1, VR128:$src1,
2314 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2315 // Special binary v4i32 shuffle cases with SHUFPS.
2316 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2317 (VSHUFPSrri VR128:$src1, VR128:$src2,
2318 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2319 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
2320 (bc_v4i32 (memopv2i64 addr:$src2)))),
2321 (VSHUFPSrmi VR128:$src1, addr:$src2,
2322 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2323 // Special unary SHUFPDrri cases.
2324 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2325 (VSHUFPDrri VR128:$src1, VR128:$src1,
2326 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2327 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2328 (VSHUFPDrri VR128:$src1, VR128:$src1,
2329 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2330 // Special binary v2i64 shuffle cases using SHUFPDrri.
2331 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2332 (VSHUFPDrri VR128:$src1, VR128:$src2,
2333 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2335 def : Pat<(v2f64 (X86Shufps VR128:$src1,
2336 (memopv2f64 addr:$src2), (i8 imm:$imm))),
2337 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2338 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2339 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2340 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2341 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2344 def : Pat<(v8i32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2345 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2346 def : Pat<(v8i32 (X86Shufps VR256:$src1,
2347 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2348 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2350 def : Pat<(v8f32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2351 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2352 def : Pat<(v8f32 (X86Shufps VR256:$src1,
2353 (memopv8f32 addr:$src2), (i8 imm:$imm))),
2354 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2356 def : Pat<(v4i64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2357 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2358 def : Pat<(v4i64 (X86Shufpd VR256:$src1,
2359 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2360 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2362 def : Pat<(v4f64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2363 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2364 def : Pat<(v4f64 (X86Shufpd VR256:$src1,
2365 (memopv4f64 addr:$src2), (i8 imm:$imm))),
2366 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2369 //===----------------------------------------------------------------------===//
2370 // SSE 1 & 2 - Unpack Instructions
2371 //===----------------------------------------------------------------------===//
2373 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2374 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
2375 PatFrag mem_frag, RegisterClass RC,
2376 X86MemOperand x86memop, string asm,
2378 def rr : PI<opc, MRMSrcReg,
2379 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2381 (vt (OpNode RC:$src1, RC:$src2)))], d>;
2382 def rm : PI<opc, MRMSrcMem,
2383 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2385 (vt (OpNode RC:$src1,
2386 (mem_frag addr:$src2))))], d>;
2389 let AddedComplexity = 10 in {
2390 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2391 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2392 SSEPackedSingle>, TB, VEX_4V;
2393 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2394 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2395 SSEPackedDouble>, TB, OpSize, VEX_4V;
2396 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2397 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2398 SSEPackedSingle>, TB, VEX_4V;
2399 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2400 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2401 SSEPackedDouble>, TB, OpSize, VEX_4V;
2403 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
2404 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2405 SSEPackedSingle>, TB, VEX_4V;
2406 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
2407 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2408 SSEPackedDouble>, TB, OpSize, VEX_4V;
2409 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
2410 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2411 SSEPackedSingle>, TB, VEX_4V;
2412 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
2413 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2414 SSEPackedDouble>, TB, OpSize, VEX_4V;
2416 let Constraints = "$src1 = $dst" in {
2417 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2418 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2419 SSEPackedSingle>, TB;
2420 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2421 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2422 SSEPackedDouble>, TB, OpSize;
2423 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2424 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2425 SSEPackedSingle>, TB;
2426 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2427 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2428 SSEPackedDouble>, TB, OpSize;
2429 } // Constraints = "$src1 = $dst"
2430 } // AddedComplexity
2432 let Predicates = [HasSSE1] in {
2433 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
2434 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
2435 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
2436 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
2437 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
2438 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
2439 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
2440 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
2443 let Predicates = [HasSSE2] in {
2444 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
2445 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
2446 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
2447 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
2448 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
2449 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
2450 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
2451 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
2453 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
2454 // problem is during lowering, where it's not possible to recognize the load
2455 // fold cause it has two uses through a bitcast. One use disappears at isel
2456 // time and the fold opportunity reappears.
2457 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2458 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2460 let AddedComplexity = 10 in
2461 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2462 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2465 let Predicates = [HasAVX] in {
2466 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
2467 (VUNPCKLPSrm VR128:$src1, addr:$src2)>;
2468 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
2469 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>;
2470 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
2471 (VUNPCKHPSrm VR128:$src1, addr:$src2)>;
2472 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
2473 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>;
2475 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
2476 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2477 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
2478 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2479 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
2480 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2481 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, (memopv8i32 addr:$src2))),
2482 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2483 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, (memopv8f32 addr:$src2))),
2484 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2485 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
2486 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2487 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, (memopv8i32 addr:$src2))),
2488 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2489 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
2490 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2492 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
2493 (VUNPCKLPDrm VR128:$src1, addr:$src2)>;
2494 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
2495 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>;
2496 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
2497 (VUNPCKHPDrm VR128:$src1, addr:$src2)>;
2498 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
2499 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>;
2501 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
2502 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2503 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
2504 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2505 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, (memopv4i64 addr:$src2))),
2506 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2507 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
2508 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2509 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, (memopv4f64 addr:$src2))),
2510 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2511 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
2512 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2513 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, (memopv4i64 addr:$src2))),
2514 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2515 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
2516 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2518 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
2519 // problem is during lowering, where it's not possible to recognize the load
2520 // fold cause it has two uses through a bitcast. One use disappears at isel
2521 // time and the fold opportunity reappears.
2522 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2523 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2524 let AddedComplexity = 10 in
2525 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2526 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2529 //===----------------------------------------------------------------------===//
2530 // SSE 1 & 2 - Extract Floating-Point Sign mask
2531 //===----------------------------------------------------------------------===//
2533 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2534 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2536 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2537 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2538 [(set GR32:$dst, (Int RC:$src))], d>;
2539 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2540 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
2543 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2544 SSEPackedSingle>, TB;
2545 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2546 SSEPackedDouble>, TB, OpSize;
2548 def : Pat<(i32 (X86fgetsign FR32:$src)),
2549 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2550 sub_ss))>, Requires<[HasSSE1]>;
2551 def : Pat<(i64 (X86fgetsign FR32:$src)),
2552 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2553 sub_ss))>, Requires<[HasSSE1]>;
2554 def : Pat<(i32 (X86fgetsign FR64:$src)),
2555 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2556 sub_sd))>, Requires<[HasSSE2]>;
2557 def : Pat<(i64 (X86fgetsign FR64:$src)),
2558 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2559 sub_sd))>, Requires<[HasSSE2]>;
2561 let Predicates = [HasAVX] in {
2562 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2563 "movmskps", SSEPackedSingle>, TB, VEX;
2564 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2565 "movmskpd", SSEPackedDouble>, TB,
2567 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2568 "movmskps", SSEPackedSingle>, TB, VEX;
2569 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2570 "movmskpd", SSEPackedDouble>, TB,
2573 def : Pat<(i32 (X86fgetsign FR32:$src)),
2574 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2576 def : Pat<(i64 (X86fgetsign FR32:$src)),
2577 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2579 def : Pat<(i32 (X86fgetsign FR64:$src)),
2580 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2582 def : Pat<(i64 (X86fgetsign FR64:$src)),
2583 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2587 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2588 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2589 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2590 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
2592 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2593 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2594 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2595 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
2599 //===----------------------------------------------------------------------===//
2600 // SSE 1 & 2 - Logical Instructions
2601 //===----------------------------------------------------------------------===//
2603 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2605 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2607 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2608 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, TB, VEX_4V;
2610 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2611 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, TB, OpSize, VEX_4V;
2613 let Constraints = "$src1 = $dst" in {
2614 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2615 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
2617 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2618 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
2622 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2623 let mayLoad = 0 in {
2624 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
2625 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
2626 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
2629 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2630 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
2632 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2634 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2636 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2637 // are all promoted to v2i64, and the patterns are covered by the int
2638 // version. This is needed in SSE only, because v2i64 isn't supported on
2639 // SSE1, but only on SSE2.
2640 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2641 !strconcat(OpcodeStr, "ps"), f128mem, [],
2642 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2643 (memopv2i64 addr:$src2)))], 0>, TB, VEX_4V;
2645 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2646 !strconcat(OpcodeStr, "pd"), f128mem,
2647 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2648 (bc_v2i64 (v2f64 VR128:$src2))))],
2649 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2650 (memopv2i64 addr:$src2)))], 0>,
2652 let Constraints = "$src1 = $dst" in {
2653 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2654 !strconcat(OpcodeStr, "ps"), f128mem,
2655 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2656 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2657 (memopv2i64 addr:$src2)))]>, TB;
2659 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2660 !strconcat(OpcodeStr, "pd"), f128mem,
2661 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2662 (bc_v2i64 (v2f64 VR128:$src2))))],
2663 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2664 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2668 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2670 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2672 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2673 !strconcat(OpcodeStr, "ps"), f256mem,
2674 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2675 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2676 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2678 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2679 !strconcat(OpcodeStr, "pd"), f256mem,
2680 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2681 (bc_v4i64 (v4f64 VR256:$src2))))],
2682 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2683 (memopv4i64 addr:$src2)))], 0>,
2687 // AVX 256-bit packed logical ops forms
2688 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2689 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2690 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2691 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2693 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2694 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2695 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2696 let isCommutable = 0 in
2697 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2699 //===----------------------------------------------------------------------===//
2700 // SSE 1 & 2 - Arithmetic Instructions
2701 //===----------------------------------------------------------------------===//
2703 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2706 /// In addition, we also have a special variant of the scalar form here to
2707 /// represent the associated intrinsic operation. This form is unlike the
2708 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2709 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2711 /// These three forms can each be reg+reg or reg+mem.
2714 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2716 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2718 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2719 OpNode, FR32, f32mem, Is2Addr>, XS;
2720 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2721 OpNode, FR64, f64mem, Is2Addr>, XD;
2724 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2726 let mayLoad = 0 in {
2727 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2728 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
2729 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2730 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
2734 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2736 let mayLoad = 0 in {
2737 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2738 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
2739 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2740 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
2744 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2746 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2747 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
2748 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2749 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
2752 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2754 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2755 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2756 SSEPackedSingle, Is2Addr>, TB;
2758 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2759 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2760 SSEPackedDouble, Is2Addr>, TB, OpSize;
2763 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
2764 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2765 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2766 SSEPackedSingle, 0>, TB;
2768 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2769 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2770 SSEPackedDouble, 0>, TB, OpSize;
2773 // Binary Arithmetic instructions
2774 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
2775 basic_sse12_fp_binop_s_int<0x58, "add", 0>,
2776 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
2777 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
2778 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
2779 basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
2780 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
2781 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
2783 let isCommutable = 0 in {
2784 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
2785 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
2786 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
2787 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
2788 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
2789 basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
2790 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
2791 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
2792 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
2793 basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
2794 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
2795 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
2796 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
2797 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
2798 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
2799 basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
2800 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
2801 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
2802 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
2803 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
2806 let Constraints = "$src1 = $dst" in {
2807 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
2808 basic_sse12_fp_binop_p<0x58, "add", fadd>,
2809 basic_sse12_fp_binop_s_int<0x58, "add">;
2810 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
2811 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
2812 basic_sse12_fp_binop_s_int<0x59, "mul">;
2814 let isCommutable = 0 in {
2815 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
2816 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
2817 basic_sse12_fp_binop_s_int<0x5C, "sub">;
2818 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
2819 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
2820 basic_sse12_fp_binop_s_int<0x5E, "div">;
2821 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
2822 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
2823 basic_sse12_fp_binop_s_int<0x5F, "max">,
2824 basic_sse12_fp_binop_p_int<0x5F, "max">;
2825 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
2826 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
2827 basic_sse12_fp_binop_s_int<0x5D, "min">,
2828 basic_sse12_fp_binop_p_int<0x5D, "min">;
2833 /// In addition, we also have a special variant of the scalar form here to
2834 /// represent the associated intrinsic operation. This form is unlike the
2835 /// plain scalar form, in that it takes an entire vector (instead of a
2836 /// scalar) and leaves the top elements undefined.
2838 /// And, we have a special variant form for a full-vector intrinsic form.
2840 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2841 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2842 SDNode OpNode, Intrinsic F32Int> {
2843 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2844 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2845 [(set FR32:$dst, (OpNode FR32:$src))]>;
2846 // For scalar unary operations, fold a load into the operation
2847 // only in OptForSize mode. It eliminates an instruction, but it also
2848 // eliminates a whole-register clobber (the load), so it introduces a
2849 // partial register update condition.
2850 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
2851 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2852 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
2853 Requires<[HasSSE1, OptForSize]>;
2854 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2855 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2856 [(set VR128:$dst, (F32Int VR128:$src))]>;
2857 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
2858 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2859 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
2862 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
2863 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2864 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
2865 !strconcat(OpcodeStr,
2866 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2867 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
2868 !strconcat(OpcodeStr,
2869 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2870 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
2871 (ins ssmem:$src1, VR128:$src2),
2872 !strconcat(OpcodeStr,
2873 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2876 /// sse1_fp_unop_p - SSE1 unops in packed form.
2877 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2878 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2879 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2880 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
2881 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2882 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2883 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
2886 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
2887 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2888 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2889 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2890 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
2891 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2892 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2893 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
2896 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
2897 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2898 Intrinsic V4F32Int> {
2899 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2900 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2901 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
2902 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2903 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2904 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
2907 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
2908 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2909 Intrinsic V4F32Int> {
2910 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2911 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2912 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
2913 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2914 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2915 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
2918 /// sse2_fp_unop_s - SSE2 unops in scalar form.
2919 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
2920 SDNode OpNode, Intrinsic F64Int> {
2921 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
2922 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2923 [(set FR64:$dst, (OpNode FR64:$src))]>;
2924 // See the comments in sse1_fp_unop_s for why this is OptForSize.
2925 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
2926 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2927 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
2928 Requires<[HasSSE2, OptForSize]>;
2929 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2930 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2931 [(set VR128:$dst, (F64Int VR128:$src))]>;
2932 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
2933 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2934 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
2937 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
2938 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2939 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
2940 !strconcat(OpcodeStr,
2941 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2942 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
2943 !strconcat(OpcodeStr,
2944 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2945 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
2946 (ins VR128:$src1, sdmem:$src2),
2947 !strconcat(OpcodeStr,
2948 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2951 /// sse2_fp_unop_p - SSE2 unops in vector forms.
2952 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
2954 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2955 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2956 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
2957 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2958 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2959 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
2962 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
2963 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2964 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2965 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2966 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
2967 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2968 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2969 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
2972 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
2973 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2974 Intrinsic V2F64Int> {
2975 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2976 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2977 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
2978 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2979 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2980 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
2983 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
2984 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2985 Intrinsic V2F64Int> {
2986 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2987 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2988 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
2989 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2990 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2991 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
2994 let Predicates = [HasAVX] in {
2996 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
2997 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V;
2999 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
3000 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
3001 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
3002 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
3003 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
3004 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
3005 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
3006 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
3009 // Reciprocal approximations. Note that these typically require refinement
3010 // in order to obtain suitable precision.
3011 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V;
3012 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
3013 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
3014 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
3015 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
3017 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V;
3018 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
3019 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
3020 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
3021 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
3024 def : Pat<(f32 (fsqrt FR32:$src)),
3025 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3026 def : Pat<(f32 (fsqrt (load addr:$src))),
3027 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3028 Requires<[HasAVX, OptForSize]>;
3029 def : Pat<(f64 (fsqrt FR64:$src)),
3030 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3031 def : Pat<(f64 (fsqrt (load addr:$src))),
3032 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3033 Requires<[HasAVX, OptForSize]>;
3035 def : Pat<(f32 (X86frsqrt FR32:$src)),
3036 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3037 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3038 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3039 Requires<[HasAVX, OptForSize]>;
3041 def : Pat<(f32 (X86frcp FR32:$src)),
3042 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3043 def : Pat<(f32 (X86frcp (load addr:$src))),
3044 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3045 Requires<[HasAVX, OptForSize]>;
3047 let Predicates = [HasAVX] in {
3048 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3049 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3050 (VSQRTSSr (f32 (IMPLICIT_DEF)),
3051 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3053 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3054 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3056 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3057 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
3058 (VSQRTSDr (f64 (IMPLICIT_DEF)),
3059 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
3061 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3062 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3064 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3065 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3066 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3067 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3069 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3070 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3072 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3073 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3074 (VRCPSSr (f32 (IMPLICIT_DEF)),
3075 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3077 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3078 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3082 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
3083 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
3084 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
3085 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
3086 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
3087 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
3089 // Reciprocal approximations. Note that these typically require refinement
3090 // in order to obtain suitable precision.
3091 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
3092 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
3093 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
3094 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
3095 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
3096 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
3098 // There is no f64 version of the reciprocal approximation instructions.
3100 //===----------------------------------------------------------------------===//
3101 // SSE 1 & 2 - Non-temporal stores
3102 //===----------------------------------------------------------------------===//
3104 let AddedComplexity = 400 in { // Prefer non-temporal versions
3105 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3106 (ins f128mem:$dst, VR128:$src),
3107 "movntps\t{$src, $dst|$dst, $src}",
3108 [(alignednontemporalstore (v4f32 VR128:$src),
3110 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3111 (ins f128mem:$dst, VR128:$src),
3112 "movntpd\t{$src, $dst|$dst, $src}",
3113 [(alignednontemporalstore (v2f64 VR128:$src),
3115 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
3116 (ins f128mem:$dst, VR128:$src),
3117 "movntdq\t{$src, $dst|$dst, $src}",
3118 [(alignednontemporalstore (v2f64 VR128:$src),
3121 let ExeDomain = SSEPackedInt in
3122 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3123 (ins f128mem:$dst, VR128:$src),
3124 "movntdq\t{$src, $dst|$dst, $src}",
3125 [(alignednontemporalstore (v4f32 VR128:$src),
3128 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3129 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3131 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3132 (ins f256mem:$dst, VR256:$src),
3133 "movntps\t{$src, $dst|$dst, $src}",
3134 [(alignednontemporalstore (v8f32 VR256:$src),
3136 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3137 (ins f256mem:$dst, VR256:$src),
3138 "movntpd\t{$src, $dst|$dst, $src}",
3139 [(alignednontemporalstore (v4f64 VR256:$src),
3141 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
3142 (ins f256mem:$dst, VR256:$src),
3143 "movntdq\t{$src, $dst|$dst, $src}",
3144 [(alignednontemporalstore (v4f64 VR256:$src),
3146 let ExeDomain = SSEPackedInt in
3147 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3148 (ins f256mem:$dst, VR256:$src),
3149 "movntdq\t{$src, $dst|$dst, $src}",
3150 [(alignednontemporalstore (v8f32 VR256:$src),
3154 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
3155 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3156 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
3157 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
3158 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
3159 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
3161 let AddedComplexity = 400 in { // Prefer non-temporal versions
3162 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3163 "movntps\t{$src, $dst|$dst, $src}",
3164 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
3165 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3166 "movntpd\t{$src, $dst|$dst, $src}",
3167 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
3169 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3170 "movntdq\t{$src, $dst|$dst, $src}",
3171 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
3173 let ExeDomain = SSEPackedInt in
3174 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3175 "movntdq\t{$src, $dst|$dst, $src}",
3176 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
3178 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3179 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3181 // There is no AVX form for instructions below this point
3182 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3183 "movnti{l}\t{$src, $dst|$dst, $src}",
3184 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
3185 TB, Requires<[HasSSE2]>;
3186 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3187 "movnti{q}\t{$src, $dst|$dst, $src}",
3188 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
3189 TB, Requires<[HasSSE2]>;
3192 //===----------------------------------------------------------------------===//
3193 // SSE 1 & 2 - Prefetch and memory fence
3194 //===----------------------------------------------------------------------===//
3196 // Prefetch intrinsic.
3197 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
3198 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
3199 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
3200 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
3201 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
3202 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
3203 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
3204 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
3207 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3208 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3209 TB, Requires<[HasSSE2]>;
3211 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3212 // was introduced with SSE2, it's backward compatible.
3213 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3215 // Load, store, and memory fence
3216 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3217 "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
3218 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3219 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3220 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3221 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3223 def : Pat<(X86SFence), (SFENCE)>;
3224 def : Pat<(X86LFence), (LFENCE)>;
3225 def : Pat<(X86MFence), (MFENCE)>;
3227 //===----------------------------------------------------------------------===//
3228 // SSE 1 & 2 - Load/Store XCSR register
3229 //===----------------------------------------------------------------------===//
3231 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3232 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
3233 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3234 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
3236 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3237 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
3238 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3239 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
3241 //===---------------------------------------------------------------------===//
3242 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3243 //===---------------------------------------------------------------------===//
3245 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3247 let neverHasSideEffects = 1 in {
3248 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3249 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3250 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3251 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3253 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3254 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3255 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3256 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3259 let isCodeGenOnly = 1 in {
3260 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3261 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3262 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3263 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3264 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3265 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3266 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3267 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3270 let canFoldAsLoad = 1, mayLoad = 1 in {
3271 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3272 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3273 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3274 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3275 let Predicates = [HasAVX] in {
3276 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3277 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3278 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3279 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3283 let mayStore = 1 in {
3284 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3285 (ins i128mem:$dst, VR128:$src),
3286 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3287 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3288 (ins i256mem:$dst, VR256:$src),
3289 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3290 let Predicates = [HasAVX] in {
3291 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3292 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3293 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3294 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3298 let neverHasSideEffects = 1 in
3299 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3300 "movdqa\t{$src, $dst|$dst, $src}", []>;
3302 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3303 "movdqu\t{$src, $dst|$dst, $src}",
3304 []>, XS, Requires<[HasSSE2]>;
3307 let isCodeGenOnly = 1 in {
3308 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3309 "movdqa\t{$src, $dst|$dst, $src}", []>;
3311 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3312 "movdqu\t{$src, $dst|$dst, $src}",
3313 []>, XS, Requires<[HasSSE2]>;
3316 let canFoldAsLoad = 1, mayLoad = 1 in {
3317 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3318 "movdqa\t{$src, $dst|$dst, $src}",
3319 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
3320 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3321 "movdqu\t{$src, $dst|$dst, $src}",
3322 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
3323 XS, Requires<[HasSSE2]>;
3326 let mayStore = 1 in {
3327 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3328 "movdqa\t{$src, $dst|$dst, $src}",
3329 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
3330 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3331 "movdqu\t{$src, $dst|$dst, $src}",
3332 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
3333 XS, Requires<[HasSSE2]>;
3336 // Intrinsic forms of MOVDQU load and store
3337 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3338 "vmovdqu\t{$src, $dst|$dst, $src}",
3339 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3340 XS, VEX, Requires<[HasAVX]>;
3342 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3343 "movdqu\t{$src, $dst|$dst, $src}",
3344 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3345 XS, Requires<[HasSSE2]>;
3347 } // ExeDomain = SSEPackedInt
3349 let Predicates = [HasAVX] in {
3350 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
3351 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3352 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3355 //===---------------------------------------------------------------------===//
3356 // SSE2 - Packed Integer Arithmetic Instructions
3357 //===---------------------------------------------------------------------===//
3359 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3361 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3362 bit IsCommutable = 0, bit Is2Addr = 1> {
3363 let isCommutable = IsCommutable in
3364 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3365 (ins VR128:$src1, VR128:$src2),
3367 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3368 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3369 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
3370 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3371 (ins VR128:$src1, i128mem:$src2),
3373 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3374 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3375 [(set VR128:$dst, (IntId VR128:$src1,
3376 (bitconvert (memopv2i64 addr:$src2))))]>;
3379 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
3380 string OpcodeStr, Intrinsic IntId,
3381 Intrinsic IntId2, bit Is2Addr = 1> {
3382 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3383 (ins VR128:$src1, VR128:$src2),
3385 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3386 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3387 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
3388 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3389 (ins VR128:$src1, i128mem:$src2),
3391 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3392 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3393 [(set VR128:$dst, (IntId VR128:$src1,
3394 (bitconvert (memopv2i64 addr:$src2))))]>;
3395 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
3396 (ins VR128:$src1, i32i8imm:$src2),
3398 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3399 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3400 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
3403 /// PDI_binop_rm - Simple SSE2 binary operator.
3404 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3405 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
3406 let isCommutable = IsCommutable in
3407 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3408 (ins VR128:$src1, VR128:$src2),
3410 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3411 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3412 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
3413 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3414 (ins VR128:$src1, i128mem:$src2),
3416 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3417 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3418 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
3419 (bitconvert (memopv2i64 addr:$src2)))))]>;
3422 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
3424 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
3425 /// to collapse (bitconvert VT to VT) into its operand.
3427 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
3428 bit IsCommutable = 0, bit Is2Addr = 1> {
3429 let isCommutable = IsCommutable in
3430 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3431 (ins VR128:$src1, VR128:$src2),
3433 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3434 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3435 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
3436 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3437 (ins VR128:$src1, i128mem:$src2),
3439 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3440 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3441 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
3444 } // ExeDomain = SSEPackedInt
3446 // 128-bit Integer Arithmetic
3448 let Predicates = [HasAVX] in {
3449 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
3450 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
3451 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
3452 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
3453 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
3454 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
3455 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
3456 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
3457 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
3460 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
3462 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
3464 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
3466 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
3468 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
3470 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
3472 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
3474 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
3476 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
3478 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
3480 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
3482 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
3484 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
3486 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
3488 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
3490 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
3492 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
3494 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
3496 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
3500 let Constraints = "$src1 = $dst" in {
3501 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
3502 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
3503 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
3504 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
3505 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
3506 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
3507 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
3508 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
3509 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
3512 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
3513 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
3514 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
3515 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
3516 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
3517 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
3518 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
3519 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
3520 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
3521 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
3522 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
3523 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
3524 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
3525 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
3526 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
3527 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
3528 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
3529 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
3530 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
3532 } // Constraints = "$src1 = $dst"
3534 //===---------------------------------------------------------------------===//
3535 // SSE2 - Packed Integer Logical Instructions
3536 //===---------------------------------------------------------------------===//
3538 let Predicates = [HasAVX] in {
3539 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
3540 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
3542 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
3543 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
3545 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
3546 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
3549 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
3550 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
3552 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
3553 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
3555 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
3556 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
3559 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
3560 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
3562 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
3563 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
3566 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
3567 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
3568 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
3570 let ExeDomain = SSEPackedInt in {
3571 let neverHasSideEffects = 1 in {
3572 // 128-bit logical shifts.
3573 def VPSLLDQri : PDIi8<0x73, MRM7r,
3574 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3575 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3577 def VPSRLDQri : PDIi8<0x73, MRM3r,
3578 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3579 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3581 // PSRADQri doesn't exist in SSE[1-3].
3583 def VPANDNrr : PDI<0xDF, MRMSrcReg,
3584 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3585 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3587 (v2i64 (X86andnp VR128:$src1, VR128:$src2)))]>,VEX_4V;
3589 def VPANDNrm : PDI<0xDF, MRMSrcMem,
3590 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3591 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3592 [(set VR128:$dst, (X86andnp VR128:$src1,
3593 (memopv2i64 addr:$src2)))]>, VEX_4V;
3597 let Constraints = "$src1 = $dst" in {
3598 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
3599 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
3600 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
3601 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
3602 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
3603 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
3605 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
3606 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
3607 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
3608 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
3609 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
3610 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
3612 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
3613 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
3614 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
3615 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
3617 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
3618 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
3619 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
3621 let ExeDomain = SSEPackedInt in {
3622 let neverHasSideEffects = 1 in {
3623 // 128-bit logical shifts.
3624 def PSLLDQri : PDIi8<0x73, MRM7r,
3625 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3626 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
3627 def PSRLDQri : PDIi8<0x73, MRM3r,
3628 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3629 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
3630 // PSRADQri doesn't exist in SSE[1-3].
3632 def PANDNrr : PDI<0xDF, MRMSrcReg,
3633 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3634 "pandn\t{$src2, $dst|$dst, $src2}", []>;
3636 def PANDNrm : PDI<0xDF, MRMSrcMem,
3637 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3638 "pandn\t{$src2, $dst|$dst, $src2}", []>;
3640 } // Constraints = "$src1 = $dst"
3642 let Predicates = [HasAVX] in {
3643 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3644 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3645 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3646 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3647 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3648 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
3649 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3650 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
3651 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3652 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3654 // Shift up / down and insert zero's.
3655 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3656 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3657 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3658 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3661 let Predicates = [HasSSE2] in {
3662 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3663 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3664 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3665 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3666 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3667 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
3668 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3669 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
3670 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3671 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3673 // Shift up / down and insert zero's.
3674 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3675 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3676 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3677 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3680 //===---------------------------------------------------------------------===//
3681 // SSE2 - Packed Integer Comparison Instructions
3682 //===---------------------------------------------------------------------===//
3684 let Predicates = [HasAVX] in {
3685 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
3687 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
3689 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
3691 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
3693 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
3695 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
3698 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3699 (VPCMPEQBrr VR128:$src1, VR128:$src2)>;
3700 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
3701 (VPCMPEQBrm VR128:$src1, addr:$src2)>;
3702 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3703 (VPCMPEQWrr VR128:$src1, VR128:$src2)>;
3704 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
3705 (VPCMPEQWrm VR128:$src1, addr:$src2)>;
3706 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3707 (VPCMPEQDrr VR128:$src1, VR128:$src2)>;
3708 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
3709 (VPCMPEQDrm VR128:$src1, addr:$src2)>;
3711 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3712 (VPCMPGTBrr VR128:$src1, VR128:$src2)>;
3713 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
3714 (VPCMPGTBrm VR128:$src1, addr:$src2)>;
3715 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3716 (VPCMPGTWrr VR128:$src1, VR128:$src2)>;
3717 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
3718 (VPCMPGTWrm VR128:$src1, addr:$src2)>;
3719 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3720 (VPCMPGTDrr VR128:$src1, VR128:$src2)>;
3721 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
3722 (VPCMPGTDrm VR128:$src1, addr:$src2)>;
3725 let Constraints = "$src1 = $dst" in {
3726 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
3727 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
3728 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
3729 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
3730 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
3731 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
3732 } // Constraints = "$src1 = $dst"
3734 let Predicates = [HasSSE2] in {
3735 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3736 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
3737 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
3738 (PCMPEQBrm VR128:$src1, addr:$src2)>;
3739 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3740 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
3741 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
3742 (PCMPEQWrm VR128:$src1, addr:$src2)>;
3743 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3744 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
3745 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
3746 (PCMPEQDrm VR128:$src1, addr:$src2)>;
3748 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3749 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
3750 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
3751 (PCMPGTBrm VR128:$src1, addr:$src2)>;
3752 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3753 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
3754 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
3755 (PCMPGTWrm VR128:$src1, addr:$src2)>;
3756 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3757 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
3758 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
3759 (PCMPGTDrm VR128:$src1, addr:$src2)>;
3762 //===---------------------------------------------------------------------===//
3763 // SSE2 - Packed Integer Pack Instructions
3764 //===---------------------------------------------------------------------===//
3766 let Predicates = [HasAVX] in {
3767 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
3769 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
3771 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
3775 let Constraints = "$src1 = $dst" in {
3776 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
3777 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
3778 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
3779 } // Constraints = "$src1 = $dst"
3781 //===---------------------------------------------------------------------===//
3782 // SSE2 - Packed Integer Shuffle Instructions
3783 //===---------------------------------------------------------------------===//
3785 let ExeDomain = SSEPackedInt in {
3786 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
3788 def ri : Ii8<0x70, MRMSrcReg,
3789 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
3790 !strconcat(OpcodeStr,
3791 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3792 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
3794 def mi : Ii8<0x70, MRMSrcMem,
3795 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
3796 !strconcat(OpcodeStr,
3797 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3798 [(set VR128:$dst, (vt (pshuf_frag:$src2
3799 (bc_frag (memopv2i64 addr:$src1)),
3802 } // ExeDomain = SSEPackedInt
3804 let Predicates = [HasAVX] in {
3805 let AddedComplexity = 5 in
3806 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize,
3809 // SSE2 with ImmT == Imm8 and XS prefix.
3810 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
3813 // SSE2 with ImmT == Imm8 and XD prefix.
3814 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
3817 let AddedComplexity = 5 in
3818 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3819 (VPSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3820 // Unary v4f32 shuffle with VPSHUF* in order to fold a load.
3821 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3822 (VPSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3824 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
3826 (VPSHUFDmi addr:$src1, imm:$imm)>;
3827 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
3829 (VPSHUFDmi addr:$src1, imm:$imm)>;
3830 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3831 (VPSHUFDri VR128:$src1, imm:$imm)>;
3832 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3833 (VPSHUFDri VR128:$src1, imm:$imm)>;
3834 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
3835 (VPSHUFHWri VR128:$src, imm:$imm)>;
3836 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
3838 (VPSHUFHWmi addr:$src, imm:$imm)>;
3839 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
3840 (VPSHUFLWri VR128:$src, imm:$imm)>;
3841 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
3843 (VPSHUFLWmi addr:$src, imm:$imm)>;
3846 let Predicates = [HasSSE2] in {
3847 let AddedComplexity = 5 in
3848 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
3850 // SSE2 with ImmT == Imm8 and XS prefix.
3851 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
3853 // SSE2 with ImmT == Imm8 and XD prefix.
3854 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
3856 let AddedComplexity = 5 in
3857 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3858 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3859 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3860 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3861 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3863 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
3865 (PSHUFDmi addr:$src1, imm:$imm)>;
3866 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
3868 (PSHUFDmi addr:$src1, imm:$imm)>;
3869 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3870 (PSHUFDri VR128:$src1, imm:$imm)>;
3871 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3872 (PSHUFDri VR128:$src1, imm:$imm)>;
3873 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
3874 (PSHUFHWri VR128:$src, imm:$imm)>;
3875 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
3877 (PSHUFHWmi addr:$src, imm:$imm)>;
3878 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
3879 (PSHUFLWri VR128:$src, imm:$imm)>;
3880 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
3882 (PSHUFLWmi addr:$src, imm:$imm)>;
3885 //===---------------------------------------------------------------------===//
3886 // SSE2 - Packed Integer Unpack Instructions
3887 //===---------------------------------------------------------------------===//
3889 let ExeDomain = SSEPackedInt in {
3890 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
3891 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
3892 def rr : PDI<opc, MRMSrcReg,
3893 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3895 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3896 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3897 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))]>;
3898 def rm : PDI<opc, MRMSrcMem,
3899 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3901 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3902 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3903 [(set VR128:$dst, (OpNode VR128:$src1,
3904 (bc_frag (memopv2i64
3908 let Predicates = [HasAVX] in {
3909 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Punpcklbw,
3910 bc_v16i8, 0>, VEX_4V;
3911 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Punpcklwd,
3912 bc_v8i16, 0>, VEX_4V;
3913 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Punpckldq,
3914 bc_v4i32, 0>, VEX_4V;
3916 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3917 /// knew to collapse (bitconvert VT to VT) into its operand.
3918 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
3919 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3920 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3921 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
3922 VR128:$src2)))]>, VEX_4V;
3923 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
3924 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3925 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3926 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
3927 (memopv2i64 addr:$src2))))]>, VEX_4V;
3929 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Punpckhbw,
3930 bc_v16i8, 0>, VEX_4V;
3931 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Punpckhwd,
3932 bc_v8i16, 0>, VEX_4V;
3933 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Punpckhdq,
3934 bc_v4i32, 0>, VEX_4V;
3936 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3937 /// knew to collapse (bitconvert VT to VT) into its operand.
3938 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
3939 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3940 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3941 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
3942 VR128:$src2)))]>, VEX_4V;
3943 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
3944 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3945 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3946 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
3947 (memopv2i64 addr:$src2))))]>, VEX_4V;
3950 let Constraints = "$src1 = $dst" in {
3951 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Punpcklbw, bc_v16i8>;
3952 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Punpcklwd, bc_v8i16>;
3953 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Punpckldq, bc_v4i32>;
3955 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3956 /// knew to collapse (bitconvert VT to VT) into its operand.
3957 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
3958 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3959 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
3961 (v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)))]>;
3962 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
3963 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3964 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
3966 (v2i64 (X86Punpcklqdq VR128:$src1,
3967 (memopv2i64 addr:$src2))))]>;
3969 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Punpckhbw, bc_v16i8>;
3970 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Punpckhwd, bc_v8i16>;
3971 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Punpckhdq, bc_v4i32>;
3973 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3974 /// knew to collapse (bitconvert VT to VT) into its operand.
3975 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
3976 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3977 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
3979 (v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)))]>;
3980 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
3981 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3982 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
3984 (v2i64 (X86Punpckhqdq VR128:$src1,
3985 (memopv2i64 addr:$src2))))]>;
3987 } // ExeDomain = SSEPackedInt
3989 // Splat v2f64 / v2i64
3990 let AddedComplexity = 10 in {
3991 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3992 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3993 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3994 (VPUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasAVX]>;
3997 //===---------------------------------------------------------------------===//
3998 // SSE2 - Packed Integer Extract and Insert
3999 //===---------------------------------------------------------------------===//
4001 let ExeDomain = SSEPackedInt in {
4002 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4003 def rri : Ii8<0xC4, MRMSrcReg,
4004 (outs VR128:$dst), (ins VR128:$src1,
4005 GR32:$src2, i32i8imm:$src3),
4007 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4008 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4010 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
4011 def rmi : Ii8<0xC4, MRMSrcMem,
4012 (outs VR128:$dst), (ins VR128:$src1,
4013 i16mem:$src2, i32i8imm:$src3),
4015 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4016 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4018 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4023 let Predicates = [HasAVX] in
4024 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4025 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4026 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4027 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4028 imm:$src2))]>, TB, OpSize, VEX;
4029 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4030 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4031 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4032 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4036 let Predicates = [HasAVX] in {
4037 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4038 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4039 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4040 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4041 []>, TB, OpSize, VEX_4V;
4044 let Constraints = "$src1 = $dst" in
4045 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
4047 } // ExeDomain = SSEPackedInt
4049 //===---------------------------------------------------------------------===//
4050 // SSE2 - Packed Mask Creation
4051 //===---------------------------------------------------------------------===//
4053 let ExeDomain = SSEPackedInt in {
4055 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4056 "pmovmskb\t{$src, $dst|$dst, $src}",
4057 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
4058 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4059 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4060 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4061 "pmovmskb\t{$src, $dst|$dst, $src}",
4062 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
4064 } // ExeDomain = SSEPackedInt
4066 //===---------------------------------------------------------------------===//
4067 // SSE2 - Conditional Store
4068 //===---------------------------------------------------------------------===//
4070 let ExeDomain = SSEPackedInt in {
4073 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4074 (ins VR128:$src, VR128:$mask),
4075 "maskmovdqu\t{$mask, $src|$src, $mask}",
4076 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
4078 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4079 (ins VR128:$src, VR128:$mask),
4080 "maskmovdqu\t{$mask, $src|$src, $mask}",
4081 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
4084 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4085 "maskmovdqu\t{$mask, $src|$src, $mask}",
4086 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
4088 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4089 "maskmovdqu\t{$mask, $src|$src, $mask}",
4090 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
4092 } // ExeDomain = SSEPackedInt
4094 //===---------------------------------------------------------------------===//
4095 // SSE2 - Move Doubleword
4096 //===---------------------------------------------------------------------===//
4098 //===---------------------------------------------------------------------===//
4099 // Move Int Doubleword to Packed Double Int
4101 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4102 "movd\t{$src, $dst|$dst, $src}",
4104 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
4105 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4106 "movd\t{$src, $dst|$dst, $src}",
4108 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
4110 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4111 "mov{d|q}\t{$src, $dst|$dst, $src}",
4113 (v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
4114 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4115 "mov{d|q}\t{$src, $dst|$dst, $src}",
4116 [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
4118 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4119 "movd\t{$src, $dst|$dst, $src}",
4121 (v4i32 (scalar_to_vector GR32:$src)))]>;
4122 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4123 "movd\t{$src, $dst|$dst, $src}",
4125 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
4126 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4127 "mov{d|q}\t{$src, $dst|$dst, $src}",
4129 (v2i64 (scalar_to_vector GR64:$src)))]>;
4130 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4131 "mov{d|q}\t{$src, $dst|$dst, $src}",
4132 [(set FR64:$dst, (bitconvert GR64:$src))]>;
4134 //===---------------------------------------------------------------------===//
4135 // Move Int Doubleword to Single Scalar
4137 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4138 "movd\t{$src, $dst|$dst, $src}",
4139 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
4141 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4142 "movd\t{$src, $dst|$dst, $src}",
4143 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
4145 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4146 "movd\t{$src, $dst|$dst, $src}",
4147 [(set FR32:$dst, (bitconvert GR32:$src))]>;
4149 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4150 "movd\t{$src, $dst|$dst, $src}",
4151 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
4153 //===---------------------------------------------------------------------===//
4154 // Move Packed Doubleword Int to Packed Double Int
4156 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4157 "movd\t{$src, $dst|$dst, $src}",
4158 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4160 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4161 (ins i32mem:$dst, VR128:$src),
4162 "movd\t{$src, $dst|$dst, $src}",
4163 [(store (i32 (vector_extract (v4i32 VR128:$src),
4164 (iPTR 0))), addr:$dst)]>, VEX;
4165 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4166 "movd\t{$src, $dst|$dst, $src}",
4167 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4169 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4170 "movd\t{$src, $dst|$dst, $src}",
4171 [(store (i32 (vector_extract (v4i32 VR128:$src),
4172 (iPTR 0))), addr:$dst)]>;
4174 //===---------------------------------------------------------------------===//
4175 // Move Packed Doubleword Int first element to Doubleword Int
4177 let isCodeGenOnly = 1 in
4178 def VMOVPQIto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4179 "mov{d|q}\t{$src, $dst|$dst, $src}",
4180 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4183 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4184 "mov{d|q}\t{$src, $dst|$dst, $src}",
4185 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4188 //===---------------------------------------------------------------------===//
4189 // Bitcast FR64 <-> GR64
4191 let Predicates = [HasAVX] in
4192 def VMOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4193 "vmovq\t{$src, $dst|$dst, $src}",
4194 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4196 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4197 "mov{d|q}\t{$src, $dst|$dst, $src}",
4198 [(set GR64:$dst, (bitconvert FR64:$src))]>;
4199 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4200 "movq\t{$src, $dst|$dst, $src}",
4201 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
4203 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4204 "movq\t{$src, $dst|$dst, $src}",
4205 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
4206 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4207 "mov{d|q}\t{$src, $dst|$dst, $src}",
4208 [(set GR64:$dst, (bitconvert FR64:$src))]>;
4209 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4210 "movq\t{$src, $dst|$dst, $src}",
4211 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
4213 //===---------------------------------------------------------------------===//
4214 // Move Scalar Single to Double Int
4216 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4217 "movd\t{$src, $dst|$dst, $src}",
4218 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
4219 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4220 "movd\t{$src, $dst|$dst, $src}",
4221 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
4222 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4223 "movd\t{$src, $dst|$dst, $src}",
4224 [(set GR32:$dst, (bitconvert FR32:$src))]>;
4225 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4226 "movd\t{$src, $dst|$dst, $src}",
4227 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
4229 //===---------------------------------------------------------------------===//
4230 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4232 let AddedComplexity = 15 in {
4233 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4234 "movd\t{$src, $dst|$dst, $src}",
4235 [(set VR128:$dst, (v4i32 (X86vzmovl
4236 (v4i32 (scalar_to_vector GR32:$src)))))]>,
4238 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4239 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4240 [(set VR128:$dst, (v2i64 (X86vzmovl
4241 (v2i64 (scalar_to_vector GR64:$src)))))]>,
4244 let AddedComplexity = 15 in {
4245 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4246 "movd\t{$src, $dst|$dst, $src}",
4247 [(set VR128:$dst, (v4i32 (X86vzmovl
4248 (v4i32 (scalar_to_vector GR32:$src)))))]>;
4249 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4250 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4251 [(set VR128:$dst, (v2i64 (X86vzmovl
4252 (v2i64 (scalar_to_vector GR64:$src)))))]>;
4255 let AddedComplexity = 20 in {
4256 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4257 "movd\t{$src, $dst|$dst, $src}",
4259 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4260 (loadi32 addr:$src))))))]>,
4262 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4263 "movd\t{$src, $dst|$dst, $src}",
4265 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4266 (loadi32 addr:$src))))))]>;
4269 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4270 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
4271 (MOVZDI2PDIrm addr:$src)>;
4272 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4273 (MOVZDI2PDIrm addr:$src)>;
4274 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4275 (MOVZDI2PDIrm addr:$src)>;
4278 let Predicates = [HasAVX] in {
4279 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4280 let AddedComplexity = 20 in {
4281 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
4282 (VMOVZDI2PDIrm addr:$src)>;
4283 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4284 (VMOVZDI2PDIrm addr:$src)>;
4285 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4286 (VMOVZDI2PDIrm addr:$src)>;
4288 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4289 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4290 (v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
4291 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4292 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4293 (v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
4294 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4297 // These are the correct encodings of the instructions so that we know how to
4298 // read correct assembly, even though we continue to emit the wrong ones for
4299 // compatibility with Darwin's buggy assembler.
4300 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4301 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4302 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4303 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4304 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4305 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4306 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4307 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4308 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4309 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4310 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4311 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4313 //===---------------------------------------------------------------------===//
4314 // SSE2 - Move Quadword
4315 //===---------------------------------------------------------------------===//
4317 //===---------------------------------------------------------------------===//
4318 // Move Quadword Int to Packed Quadword Int
4320 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4321 "vmovq\t{$src, $dst|$dst, $src}",
4323 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4324 VEX, Requires<[HasAVX]>;
4325 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4326 "movq\t{$src, $dst|$dst, $src}",
4328 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4329 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
4331 //===---------------------------------------------------------------------===//
4332 // Move Packed Quadword Int to Quadword Int
4334 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4335 "movq\t{$src, $dst|$dst, $src}",
4336 [(store (i64 (vector_extract (v2i64 VR128:$src),
4337 (iPTR 0))), addr:$dst)]>, VEX;
4338 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4339 "movq\t{$src, $dst|$dst, $src}",
4340 [(store (i64 (vector_extract (v2i64 VR128:$src),
4341 (iPTR 0))), addr:$dst)]>;
4343 //===---------------------------------------------------------------------===//
4344 // Store / copy lower 64-bits of a XMM register.
4346 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4347 "movq\t{$src, $dst|$dst, $src}",
4348 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4349 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4350 "movq\t{$src, $dst|$dst, $src}",
4351 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
4353 let AddedComplexity = 20 in
4354 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4355 "vmovq\t{$src, $dst|$dst, $src}",
4357 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4358 (loadi64 addr:$src))))))]>,
4359 XS, VEX, Requires<[HasAVX]>;
4361 let AddedComplexity = 20 in
4362 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4363 "movq\t{$src, $dst|$dst, $src}",
4365 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4366 (loadi64 addr:$src))))))]>,
4367 XS, Requires<[HasSSE2]>;
4369 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4370 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4371 (MOVZQI2PQIrm addr:$src)>;
4372 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4373 (MOVZQI2PQIrm addr:$src)>;
4374 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4377 let Predicates = [HasAVX], AddedComplexity = 20 in {
4378 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4379 (VMOVZQI2PQIrm addr:$src)>;
4380 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4381 (VMOVZQI2PQIrm addr:$src)>;
4382 def : Pat<(v2i64 (X86vzload addr:$src)),
4383 (VMOVZQI2PQIrm addr:$src)>;
4386 //===---------------------------------------------------------------------===//
4387 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4388 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4390 let AddedComplexity = 15 in
4391 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4392 "vmovq\t{$src, $dst|$dst, $src}",
4393 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4394 XS, VEX, Requires<[HasAVX]>;
4395 let AddedComplexity = 15 in
4396 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4397 "movq\t{$src, $dst|$dst, $src}",
4398 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4399 XS, Requires<[HasSSE2]>;
4401 let AddedComplexity = 20 in
4402 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4403 "vmovq\t{$src, $dst|$dst, $src}",
4404 [(set VR128:$dst, (v2i64 (X86vzmovl
4405 (loadv2i64 addr:$src))))]>,
4406 XS, VEX, Requires<[HasAVX]>;
4407 let AddedComplexity = 20 in {
4408 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4409 "movq\t{$src, $dst|$dst, $src}",
4410 [(set VR128:$dst, (v2i64 (X86vzmovl
4411 (loadv2i64 addr:$src))))]>,
4412 XS, Requires<[HasSSE2]>;
4415 let AddedComplexity = 20 in {
4416 let Predicates = [HasSSE2] in {
4417 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
4418 (MOVZPQILo2PQIrm addr:$src)>;
4419 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4420 (MOVZPQILo2PQIrr VR128:$src)>;
4422 let Predicates = [HasAVX] in {
4423 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
4424 (VMOVZPQILo2PQIrm addr:$src)>;
4425 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4426 (VMOVZPQILo2PQIrr VR128:$src)>;
4430 // Instructions to match in the assembler
4431 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4432 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4433 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4434 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4435 // Recognize "movd" with GR64 destination, but encode as a "movq"
4436 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4437 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4439 // Instructions for the disassembler
4440 // xr = XMM register
4443 let Predicates = [HasAVX] in
4444 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4445 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4446 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4447 "movq\t{$src, $dst|$dst, $src}", []>, XS;
4449 //===---------------------------------------------------------------------===//
4450 // SSE3 - Conversion Instructions
4451 //===---------------------------------------------------------------------===//
4453 // Convert Packed Double FP to Packed DW Integers
4454 let Predicates = [HasAVX] in {
4455 // The assembler can recognize rr 256-bit instructions by seeing a ymm
4456 // register, but the same isn't true when using memory operands instead.
4457 // Provide other assembly rr and rm forms to address this explicitly.
4458 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4459 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4460 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4461 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4464 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4465 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4466 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4467 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4470 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4471 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
4472 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
4473 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4476 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4477 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4478 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4479 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4481 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
4482 (VCVTPD2DQYrr VR256:$src)>;
4483 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
4484 (VCVTPD2DQYrm addr:$src)>;
4486 // Convert Packed DW Integers to Packed Double FP
4487 let Predicates = [HasAVX] in {
4488 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4489 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4490 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4491 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4492 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
4493 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4494 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
4495 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4498 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4499 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4500 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4501 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4503 // AVX 256-bit register conversion intrinsics
4504 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
4505 (VCVTDQ2PDYrr VR128:$src)>;
4506 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
4507 (VCVTDQ2PDYrm addr:$src)>;
4509 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
4510 (VCVTPD2DQYrr VR256:$src)>;
4511 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
4512 (VCVTPD2DQYrm addr:$src)>;
4514 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
4515 (VCVTDQ2PDYrr VR128:$src)>;
4516 def : Pat<(v4f64 (sint_to_fp (memopv4i32 addr:$src))),
4517 (VCVTDQ2PDYrm addr:$src)>;
4519 //===---------------------------------------------------------------------===//
4520 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4521 //===---------------------------------------------------------------------===//
4522 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4523 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4524 X86MemOperand x86memop> {
4525 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4526 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4527 [(set RC:$dst, (vt (OpNode RC:$src)))]>;
4528 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4529 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4530 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>;
4533 let Predicates = [HasAVX] in {
4534 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4535 v4f32, VR128, memopv4f32, f128mem>, VEX;
4536 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4537 v4f32, VR128, memopv4f32, f128mem>, VEX;
4538 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4539 v8f32, VR256, memopv8f32, f256mem>, VEX;
4540 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4541 v8f32, VR256, memopv8f32, f256mem>, VEX;
4543 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4544 memopv4f32, f128mem>;
4545 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4546 memopv4f32, f128mem>;
4548 let Predicates = [HasSSE3] in {
4549 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4550 (MOVSHDUPrr VR128:$src)>;
4551 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4552 (MOVSHDUPrm addr:$src)>;
4553 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4554 (MOVSLDUPrr VR128:$src)>;
4555 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4556 (MOVSLDUPrm addr:$src)>;
4559 let Predicates = [HasAVX] in {
4560 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4561 (VMOVSHDUPrr VR128:$src)>;
4562 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4563 (VMOVSHDUPrm addr:$src)>;
4564 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4565 (VMOVSLDUPrr VR128:$src)>;
4566 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4567 (VMOVSLDUPrm addr:$src)>;
4568 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4569 (VMOVSHDUPYrr VR256:$src)>;
4570 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4571 (VMOVSHDUPYrm addr:$src)>;
4572 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4573 (VMOVSLDUPYrr VR256:$src)>;
4574 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4575 (VMOVSLDUPYrm addr:$src)>;
4578 //===---------------------------------------------------------------------===//
4579 // SSE3 - Replicate Double FP - MOVDDUP
4580 //===---------------------------------------------------------------------===//
4582 multiclass sse3_replicate_dfp<string OpcodeStr> {
4583 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4584 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4585 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
4586 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4587 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4589 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
4593 // FIXME: Merge with above classe when there're patterns for the ymm version
4594 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4595 let Predicates = [HasAVX] in {
4596 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4597 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4599 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4600 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4605 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4606 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4607 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
4609 let Predicates = [HasSSE3] in {
4610 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
4612 (MOVDDUPrm addr:$src)>;
4613 let AddedComplexity = 5 in {
4614 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
4615 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
4616 (MOVDDUPrm addr:$src)>;
4617 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
4618 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
4619 (MOVDDUPrm addr:$src)>;
4621 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4622 (MOVDDUPrm addr:$src)>;
4623 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4624 (MOVDDUPrm addr:$src)>;
4625 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4626 (MOVDDUPrm addr:$src)>;
4627 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
4628 (MOVDDUPrm addr:$src)>;
4629 def : Pat<(X86Movddup (bc_v2f64
4630 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4631 (MOVDDUPrm addr:$src)>;
4634 let Predicates = [HasAVX] in {
4635 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
4637 (VMOVDDUPrm addr:$src)>;
4638 let AddedComplexity = 5 in {
4639 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
4640 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
4641 (VMOVDDUPrm addr:$src)>;
4642 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
4643 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
4644 (VMOVDDUPrm addr:$src)>;
4646 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4647 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4648 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4649 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4650 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4651 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4652 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
4653 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4654 def : Pat<(X86Movddup (bc_v2f64
4655 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4656 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4659 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4660 (VMOVDDUPYrm addr:$src)>;
4661 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4662 (VMOVDDUPYrm addr:$src)>;
4663 def : Pat<(X86Movddup (v4f64 (scalar_to_vector (loadf64 addr:$src)))),
4664 (VMOVDDUPYrm addr:$src)>;
4665 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4666 (VMOVDDUPYrm addr:$src)>;
4667 def : Pat<(X86Movddup (v4f64 VR256:$src)),
4668 (VMOVDDUPYrr VR256:$src)>;
4669 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4670 (VMOVDDUPYrr VR256:$src)>;
4673 //===---------------------------------------------------------------------===//
4674 // SSE3 - Move Unaligned Integer
4675 //===---------------------------------------------------------------------===//
4677 let Predicates = [HasAVX] in {
4678 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4679 "vlddqu\t{$src, $dst|$dst, $src}",
4680 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4681 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4682 "vlddqu\t{$src, $dst|$dst, $src}",
4683 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
4685 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4686 "lddqu\t{$src, $dst|$dst, $src}",
4687 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
4689 //===---------------------------------------------------------------------===//
4690 // SSE3 - Arithmetic
4691 //===---------------------------------------------------------------------===//
4693 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4694 X86MemOperand x86memop, bit Is2Addr = 1> {
4695 def rr : I<0xD0, MRMSrcReg,
4696 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4698 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4699 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4700 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
4701 def rm : I<0xD0, MRMSrcMem,
4702 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4704 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4705 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4706 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
4709 let Predicates = [HasAVX],
4710 ExeDomain = SSEPackedDouble in {
4711 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4712 f128mem, 0>, TB, XD, VEX_4V;
4713 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4714 f128mem, 0>, TB, OpSize, VEX_4V;
4715 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4716 f256mem, 0>, TB, XD, VEX_4V;
4717 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
4718 f256mem, 0>, TB, OpSize, VEX_4V;
4720 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
4721 ExeDomain = SSEPackedDouble in {
4722 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
4724 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
4725 f128mem>, TB, OpSize;
4728 //===---------------------------------------------------------------------===//
4729 // SSE3 Instructions
4730 //===---------------------------------------------------------------------===//
4733 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4734 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
4735 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4737 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4738 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4739 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
4741 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4743 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4744 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4745 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
4747 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4748 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
4749 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4751 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4752 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4753 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
4755 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4757 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4758 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4759 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
4762 let Predicates = [HasAVX] in {
4763 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
4764 int_x86_sse3_hadd_ps, 0>, VEX_4V;
4765 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
4766 int_x86_sse3_hadd_pd, 0>, VEX_4V;
4767 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
4768 int_x86_sse3_hsub_ps, 0>, VEX_4V;
4769 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
4770 int_x86_sse3_hsub_pd, 0>, VEX_4V;
4771 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
4772 int_x86_avx_hadd_ps_256, 0>, VEX_4V;
4773 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
4774 int_x86_avx_hadd_pd_256, 0>, VEX_4V;
4775 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
4776 int_x86_avx_hsub_ps_256, 0>, VEX_4V;
4777 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
4778 int_x86_avx_hsub_pd_256, 0>, VEX_4V;
4781 let Constraints = "$src1 = $dst" in {
4782 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
4783 int_x86_sse3_hadd_ps>;
4784 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
4785 int_x86_sse3_hadd_pd>;
4786 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
4787 int_x86_sse3_hsub_ps>;
4788 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
4789 int_x86_sse3_hsub_pd>;
4792 //===---------------------------------------------------------------------===//
4793 // SSSE3 - Packed Absolute Instructions
4794 //===---------------------------------------------------------------------===//
4797 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
4798 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
4799 PatFrag mem_frag128, Intrinsic IntId128> {
4800 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4802 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4803 [(set VR128:$dst, (IntId128 VR128:$src))]>,
4806 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4808 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4811 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
4814 let Predicates = [HasAVX] in {
4815 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
4816 int_x86_ssse3_pabs_b_128>, VEX;
4817 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
4818 int_x86_ssse3_pabs_w_128>, VEX;
4819 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
4820 int_x86_ssse3_pabs_d_128>, VEX;
4823 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
4824 int_x86_ssse3_pabs_b_128>;
4825 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
4826 int_x86_ssse3_pabs_w_128>;
4827 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
4828 int_x86_ssse3_pabs_d_128>;
4830 //===---------------------------------------------------------------------===//
4831 // SSSE3 - Packed Binary Operator Instructions
4832 //===---------------------------------------------------------------------===//
4834 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
4835 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
4836 PatFrag mem_frag128, Intrinsic IntId128,
4838 let isCommutable = 1 in
4839 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4840 (ins VR128:$src1, VR128:$src2),
4842 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4843 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4844 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4846 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4847 (ins VR128:$src1, i128mem:$src2),
4849 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4850 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4852 (IntId128 VR128:$src1,
4853 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4856 let Predicates = [HasAVX] in {
4857 let isCommutable = 0 in {
4858 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
4859 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
4860 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
4861 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
4862 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
4863 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
4864 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
4865 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
4866 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
4867 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
4868 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
4869 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
4870 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
4871 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
4872 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
4873 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
4874 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
4875 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
4876 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
4877 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
4878 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
4879 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
4881 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
4882 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
4885 // None of these have i8 immediate fields.
4886 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
4887 let isCommutable = 0 in {
4888 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
4889 int_x86_ssse3_phadd_w_128>;
4890 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
4891 int_x86_ssse3_phadd_d_128>;
4892 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
4893 int_x86_ssse3_phadd_sw_128>;
4894 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
4895 int_x86_ssse3_phsub_w_128>;
4896 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
4897 int_x86_ssse3_phsub_d_128>;
4898 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
4899 int_x86_ssse3_phsub_sw_128>;
4900 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
4901 int_x86_ssse3_pmadd_ub_sw_128>;
4902 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
4903 int_x86_ssse3_pshuf_b_128>;
4904 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
4905 int_x86_ssse3_psign_b_128>;
4906 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
4907 int_x86_ssse3_psign_w_128>;
4908 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
4909 int_x86_ssse3_psign_d_128>;
4911 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
4912 int_x86_ssse3_pmul_hr_sw_128>;
4915 let Predicates = [HasSSSE3] in {
4916 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
4917 (PSHUFBrr128 VR128:$src, VR128:$mask)>;
4918 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
4919 (PSHUFBrm128 VR128:$src, addr:$mask)>;
4921 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
4922 (PSIGNBrr128 VR128:$src1, VR128:$src2)>;
4923 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
4924 (PSIGNWrr128 VR128:$src1, VR128:$src2)>;
4925 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
4926 (PSIGNDrr128 VR128:$src1, VR128:$src2)>;
4929 let Predicates = [HasAVX] in {
4930 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
4931 (VPSHUFBrr128 VR128:$src, VR128:$mask)>;
4932 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
4933 (VPSHUFBrm128 VR128:$src, addr:$mask)>;
4935 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
4936 (VPSIGNBrr128 VR128:$src1, VR128:$src2)>;
4937 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
4938 (VPSIGNWrr128 VR128:$src1, VR128:$src2)>;
4939 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
4940 (VPSIGNDrr128 VR128:$src1, VR128:$src2)>;
4943 //===---------------------------------------------------------------------===//
4944 // SSSE3 - Packed Align Instruction Patterns
4945 //===---------------------------------------------------------------------===//
4947 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
4948 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
4949 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4951 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4953 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4955 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
4956 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4958 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4960 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4964 let Predicates = [HasAVX] in
4965 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
4966 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
4967 defm PALIGN : ssse3_palign<"palignr">;
4969 let Predicates = [HasSSSE3] in {
4970 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4971 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4972 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4973 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4974 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4975 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4976 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4977 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4980 let Predicates = [HasAVX] in {
4981 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4982 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4983 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4984 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4985 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4986 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4987 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4988 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4991 //===---------------------------------------------------------------------===//
4992 // SSSE3 - Thread synchronization
4993 //===---------------------------------------------------------------------===//
4995 let usesCustomInserter = 1 in {
4996 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
4997 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
4998 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
4999 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
5002 let Uses = [EAX, ECX, EDX] in
5003 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
5004 Requires<[HasSSE3]>;
5005 let Uses = [ECX, EAX] in
5006 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
5007 Requires<[HasSSE3]>;
5009 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5010 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5012 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5013 Requires<[In32BitMode]>;
5014 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5015 Requires<[In64BitMode]>;
5017 //===----------------------------------------------------------------------===//
5018 // SSE4.1 - Packed Move with Sign/Zero Extend
5019 //===----------------------------------------------------------------------===//
5021 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5022 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5023 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5024 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5026 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5027 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5029 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5033 let Predicates = [HasAVX] in {
5034 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5036 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5038 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5040 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5042 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5044 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5048 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5049 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5050 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5051 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5052 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5053 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5055 let Predicates = [HasSSE41] in {
5056 // Common patterns involving scalar load.
5057 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5058 (PMOVSXBWrm addr:$src)>;
5059 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5060 (PMOVSXBWrm addr:$src)>;
5062 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5063 (PMOVSXWDrm addr:$src)>;
5064 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5065 (PMOVSXWDrm addr:$src)>;
5067 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5068 (PMOVSXDQrm addr:$src)>;
5069 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5070 (PMOVSXDQrm addr:$src)>;
5072 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5073 (PMOVZXBWrm addr:$src)>;
5074 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5075 (PMOVZXBWrm addr:$src)>;
5077 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5078 (PMOVZXWDrm addr:$src)>;
5079 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5080 (PMOVZXWDrm addr:$src)>;
5082 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5083 (PMOVZXDQrm addr:$src)>;
5084 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5085 (PMOVZXDQrm addr:$src)>;
5088 let Predicates = [HasAVX] in {
5089 // Common patterns involving scalar load.
5090 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5091 (VPMOVSXBWrm addr:$src)>;
5092 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5093 (VPMOVSXBWrm addr:$src)>;
5095 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5096 (VPMOVSXWDrm addr:$src)>;
5097 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5098 (VPMOVSXWDrm addr:$src)>;
5100 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5101 (VPMOVSXDQrm addr:$src)>;
5102 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5103 (VPMOVSXDQrm addr:$src)>;
5105 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5106 (VPMOVZXBWrm addr:$src)>;
5107 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5108 (VPMOVZXBWrm addr:$src)>;
5110 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5111 (VPMOVZXWDrm addr:$src)>;
5112 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5113 (VPMOVZXWDrm addr:$src)>;
5115 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5116 (VPMOVZXDQrm addr:$src)>;
5117 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5118 (VPMOVZXDQrm addr:$src)>;
5122 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5123 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5124 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5125 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5127 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5128 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5130 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5134 let Predicates = [HasAVX] in {
5135 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5137 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5139 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5141 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5145 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5146 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5147 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5148 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5150 let Predicates = [HasSSE41] in {
5151 // Common patterns involving scalar load
5152 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5153 (PMOVSXBDrm addr:$src)>;
5154 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5155 (PMOVSXWQrm addr:$src)>;
5157 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5158 (PMOVZXBDrm addr:$src)>;
5159 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5160 (PMOVZXWQrm addr:$src)>;
5163 let Predicates = [HasAVX] in {
5164 // Common patterns involving scalar load
5165 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5166 (VPMOVSXBDrm addr:$src)>;
5167 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5168 (VPMOVSXWQrm addr:$src)>;
5170 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5171 (VPMOVZXBDrm addr:$src)>;
5172 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5173 (VPMOVZXWQrm addr:$src)>;
5176 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5177 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5178 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5179 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5181 // Expecting a i16 load any extended to i32 value.
5182 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5183 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5184 [(set VR128:$dst, (IntId (bitconvert
5185 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5189 let Predicates = [HasAVX] in {
5190 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5192 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5195 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5196 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5198 let Predicates = [HasSSE41] in {
5199 // Common patterns involving scalar load
5200 def : Pat<(int_x86_sse41_pmovsxbq
5201 (bitconvert (v4i32 (X86vzmovl
5202 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5203 (PMOVSXBQrm addr:$src)>;
5205 def : Pat<(int_x86_sse41_pmovzxbq
5206 (bitconvert (v4i32 (X86vzmovl
5207 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5208 (PMOVZXBQrm addr:$src)>;
5211 let Predicates = [HasAVX] in {
5212 // Common patterns involving scalar load
5213 def : Pat<(int_x86_sse41_pmovsxbq
5214 (bitconvert (v4i32 (X86vzmovl
5215 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5216 (VPMOVSXBQrm addr:$src)>;
5218 def : Pat<(int_x86_sse41_pmovzxbq
5219 (bitconvert (v4i32 (X86vzmovl
5220 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5221 (VPMOVZXBQrm addr:$src)>;
5224 //===----------------------------------------------------------------------===//
5225 // SSE4.1 - Extract Instructions
5226 //===----------------------------------------------------------------------===//
5228 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5229 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5230 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5231 (ins VR128:$src1, i32i8imm:$src2),
5232 !strconcat(OpcodeStr,
5233 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5234 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5236 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5237 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5238 !strconcat(OpcodeStr,
5239 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5242 // There's an AssertZext in the way of writing the store pattern
5243 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5246 let Predicates = [HasAVX] in {
5247 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5248 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5249 (ins VR128:$src1, i32i8imm:$src2),
5250 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5253 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5256 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5257 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5258 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5259 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5260 !strconcat(OpcodeStr,
5261 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5264 // There's an AssertZext in the way of writing the store pattern
5265 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5268 let Predicates = [HasAVX] in
5269 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5271 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5274 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5275 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5276 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5277 (ins VR128:$src1, i32i8imm:$src2),
5278 !strconcat(OpcodeStr,
5279 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5281 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5282 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5283 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5284 !strconcat(OpcodeStr,
5285 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5286 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5287 addr:$dst)]>, OpSize;
5290 let Predicates = [HasAVX] in
5291 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5293 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5295 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5296 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5297 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5298 (ins VR128:$src1, i32i8imm:$src2),
5299 !strconcat(OpcodeStr,
5300 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5302 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5303 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5304 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5305 !strconcat(OpcodeStr,
5306 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5307 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5308 addr:$dst)]>, OpSize, REX_W;
5311 let Predicates = [HasAVX] in
5312 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5314 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5316 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5318 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5319 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5320 (ins VR128:$src1, i32i8imm:$src2),
5321 !strconcat(OpcodeStr,
5322 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5324 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5326 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5327 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5328 !strconcat(OpcodeStr,
5329 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5330 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5331 addr:$dst)]>, OpSize;
5334 let Predicates = [HasAVX] in {
5335 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5336 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5337 (ins VR128:$src1, i32i8imm:$src2),
5338 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
5341 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
5343 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
5344 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5347 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5348 Requires<[HasSSE41]>;
5349 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5352 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5355 //===----------------------------------------------------------------------===//
5356 // SSE4.1 - Insert Instructions
5357 //===----------------------------------------------------------------------===//
5359 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5360 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5361 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5363 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5365 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5367 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5368 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5369 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
5371 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5373 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5375 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
5376 imm:$src3))]>, OpSize;
5379 let Predicates = [HasAVX] in
5380 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
5381 let Constraints = "$src1 = $dst" in
5382 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
5384 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
5385 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5386 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5388 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5390 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5392 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
5394 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5395 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
5397 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5399 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5401 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
5402 imm:$src3)))]>, OpSize;
5405 let Predicates = [HasAVX] in
5406 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
5407 let Constraints = "$src1 = $dst" in
5408 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
5410 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
5411 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5412 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
5414 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5416 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5418 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
5420 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5421 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
5423 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5425 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5427 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
5428 imm:$src3)))]>, OpSize;
5431 let Predicates = [HasAVX] in
5432 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
5433 let Constraints = "$src1 = $dst" in
5434 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
5436 // insertps has a few different modes, there's the first two here below which
5437 // are optimized inserts that won't zero arbitrary elements in the destination
5438 // vector. The next one matches the intrinsic and could zero arbitrary elements
5439 // in the target vector.
5440 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
5441 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5442 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
5444 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5446 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5448 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
5450 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5451 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
5453 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5455 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5457 (X86insrtps VR128:$src1,
5458 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
5459 imm:$src3))]>, OpSize;
5462 let Constraints = "$src1 = $dst" in
5463 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
5464 let Predicates = [HasAVX] in
5465 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
5467 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
5468 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
5470 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
5471 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
5472 Requires<[HasSSE41]>;
5474 //===----------------------------------------------------------------------===//
5475 // SSE4.1 - Round Instructions
5476 //===----------------------------------------------------------------------===//
5478 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
5479 X86MemOperand x86memop, RegisterClass RC,
5480 PatFrag mem_frag32, PatFrag mem_frag64,
5481 Intrinsic V4F32Int, Intrinsic V2F64Int> {
5482 // Intrinsic operation, reg.
5483 // Vector intrinsic operation, reg
5484 def PSr : SS4AIi8<opcps, MRMSrcReg,
5485 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5486 !strconcat(OpcodeStr,
5487 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5488 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
5491 // Vector intrinsic operation, mem
5492 def PSm : Ii8<opcps, MRMSrcMem,
5493 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
5494 !strconcat(OpcodeStr,
5495 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5497 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
5499 Requires<[HasSSE41]>;
5501 // Vector intrinsic operation, reg
5502 def PDr : SS4AIi8<opcpd, MRMSrcReg,
5503 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5504 !strconcat(OpcodeStr,
5505 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5506 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
5509 // Vector intrinsic operation, mem
5510 def PDm : SS4AIi8<opcpd, MRMSrcMem,
5511 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
5512 !strconcat(OpcodeStr,
5513 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5515 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
5519 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
5520 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
5521 // Intrinsic operation, reg.
5522 // Vector intrinsic operation, reg
5523 def PSr_AVX : SS4AIi8<opcps, MRMSrcReg,
5524 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5525 !strconcat(OpcodeStr,
5526 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5529 // Vector intrinsic operation, mem
5530 def PSm_AVX : Ii8<opcps, MRMSrcMem,
5531 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5532 !strconcat(OpcodeStr,
5533 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5534 []>, TA, OpSize, Requires<[HasSSE41]>;
5536 // Vector intrinsic operation, reg
5537 def PDr_AVX : SS4AIi8<opcpd, MRMSrcReg,
5538 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5539 !strconcat(OpcodeStr,
5540 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5543 // Vector intrinsic operation, mem
5544 def PDm_AVX : SS4AIi8<opcpd, MRMSrcMem,
5545 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5546 !strconcat(OpcodeStr,
5547 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5551 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
5554 Intrinsic F64Int, bit Is2Addr = 1> {
5555 // Intrinsic operation, reg.
5556 def SSr : SS4AIi8<opcss, MRMSrcReg,
5557 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5559 !strconcat(OpcodeStr,
5560 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5561 !strconcat(OpcodeStr,
5562 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5563 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
5566 // Intrinsic operation, mem.
5567 def SSm : SS4AIi8<opcss, MRMSrcMem,
5568 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
5570 !strconcat(OpcodeStr,
5571 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5572 !strconcat(OpcodeStr,
5573 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5575 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
5578 // Intrinsic operation, reg.
5579 def SDr : SS4AIi8<opcsd, MRMSrcReg,
5580 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5582 !strconcat(OpcodeStr,
5583 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5584 !strconcat(OpcodeStr,
5585 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5586 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
5589 // Intrinsic operation, mem.
5590 def SDm : SS4AIi8<opcsd, MRMSrcMem,
5591 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
5593 !strconcat(OpcodeStr,
5594 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5595 !strconcat(OpcodeStr,
5596 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5598 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
5602 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
5604 // Intrinsic operation, reg.
5605 def SSr_AVX : SS4AIi8<opcss, MRMSrcReg,
5606 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5607 !strconcat(OpcodeStr,
5608 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5611 // Intrinsic operation, mem.
5612 def SSm_AVX : SS4AIi8<opcss, MRMSrcMem,
5613 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
5614 !strconcat(OpcodeStr,
5615 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5618 // Intrinsic operation, reg.
5619 def SDr_AVX : SS4AIi8<opcsd, MRMSrcReg,
5620 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5621 !strconcat(OpcodeStr,
5622 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5625 // Intrinsic operation, mem.
5626 def SDm_AVX : SS4AIi8<opcsd, MRMSrcMem,
5627 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
5628 !strconcat(OpcodeStr,
5629 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5633 // FP round - roundss, roundps, roundsd, roundpd
5634 let Predicates = [HasAVX] in {
5636 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
5637 memopv4f32, memopv2f64,
5638 int_x86_sse41_round_ps,
5639 int_x86_sse41_round_pd>, VEX;
5640 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
5641 memopv8f32, memopv4f64,
5642 int_x86_avx_round_ps_256,
5643 int_x86_avx_round_pd_256>, VEX;
5644 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
5645 int_x86_sse41_round_ss,
5646 int_x86_sse41_round_sd, 0>, VEX_4V;
5648 // Instructions for the assembler
5649 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
5651 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
5653 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
5656 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
5657 memopv4f32, memopv2f64,
5658 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
5659 let Constraints = "$src1 = $dst" in
5660 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
5661 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
5663 //===----------------------------------------------------------------------===//
5664 // SSE4.1 - Packed Bit Test
5665 //===----------------------------------------------------------------------===//
5667 // ptest instruction we'll lower to this in X86ISelLowering primarily from
5668 // the intel intrinsic that corresponds to this.
5669 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5670 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5671 "vptest\t{$src2, $src1|$src1, $src2}",
5672 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5674 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5675 "vptest\t{$src2, $src1|$src1, $src2}",
5676 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5679 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
5680 "vptest\t{$src2, $src1|$src1, $src2}",
5681 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
5683 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
5684 "vptest\t{$src2, $src1|$src1, $src2}",
5685 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
5689 let Defs = [EFLAGS] in {
5690 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5691 "ptest \t{$src2, $src1|$src1, $src2}",
5692 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5694 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5695 "ptest \t{$src2, $src1|$src1, $src2}",
5696 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5700 // The bit test instructions below are AVX only
5701 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
5702 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
5703 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
5704 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5705 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
5706 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
5707 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5708 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
5712 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5713 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
5714 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
5715 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
5716 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
5719 //===----------------------------------------------------------------------===//
5720 // SSE4.1 - Misc Instructions
5721 //===----------------------------------------------------------------------===//
5723 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
5724 "popcnt{w}\t{$src, $dst|$dst, $src}",
5725 [(set GR16:$dst, (ctpop GR16:$src))]>, OpSize, XS;
5726 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
5727 "popcnt{w}\t{$src, $dst|$dst, $src}",
5728 [(set GR16:$dst, (ctpop (loadi16 addr:$src)))]>, OpSize, XS;
5730 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
5731 "popcnt{l}\t{$src, $dst|$dst, $src}",
5732 [(set GR32:$dst, (ctpop GR32:$src))]>, XS;
5733 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
5734 "popcnt{l}\t{$src, $dst|$dst, $src}",
5735 [(set GR32:$dst, (ctpop (loadi32 addr:$src)))]>, XS;
5737 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
5738 "popcnt{q}\t{$src, $dst|$dst, $src}",
5739 [(set GR64:$dst, (ctpop GR64:$src))]>, XS;
5740 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
5741 "popcnt{q}\t{$src, $dst|$dst, $src}",
5742 [(set GR64:$dst, (ctpop (loadi64 addr:$src)))]>, XS;
5746 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
5747 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
5748 Intrinsic IntId128> {
5749 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5751 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5752 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
5753 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5755 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5758 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
5761 let Predicates = [HasAVX] in
5762 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
5763 int_x86_sse41_phminposuw>, VEX;
5764 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
5765 int_x86_sse41_phminposuw>;
5767 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
5768 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
5769 Intrinsic IntId128, bit Is2Addr = 1> {
5770 let isCommutable = 1 in
5771 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5772 (ins VR128:$src1, VR128:$src2),
5774 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5775 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5776 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
5777 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5778 (ins VR128:$src1, i128mem:$src2),
5780 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5781 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5783 (IntId128 VR128:$src1,
5784 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5787 let Predicates = [HasAVX] in {
5788 let isCommutable = 0 in
5789 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
5791 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
5793 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
5795 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
5797 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
5799 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
5801 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
5803 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
5805 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
5807 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
5809 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
5812 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
5813 (VPCMPEQQrr VR128:$src1, VR128:$src2)>;
5814 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
5815 (VPCMPEQQrm VR128:$src1, addr:$src2)>;
5818 let Constraints = "$src1 = $dst" in {
5819 let isCommutable = 0 in
5820 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
5821 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
5822 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
5823 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
5824 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
5825 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
5826 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
5827 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
5828 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
5829 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
5830 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
5833 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
5834 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
5835 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
5836 (PCMPEQQrm VR128:$src1, addr:$src2)>;
5838 /// SS48I_binop_rm - Simple SSE41 binary operator.
5839 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5840 ValueType OpVT, bit Is2Addr = 1> {
5841 let isCommutable = 1 in
5842 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5843 (ins VR128:$src1, VR128:$src2),
5845 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5846 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5847 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
5849 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5850 (ins VR128:$src1, i128mem:$src2),
5852 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5853 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5854 [(set VR128:$dst, (OpNode VR128:$src1,
5855 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
5859 let Predicates = [HasAVX] in
5860 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
5861 let Constraints = "$src1 = $dst" in
5862 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
5864 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
5865 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
5866 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
5867 X86MemOperand x86memop, bit Is2Addr = 1> {
5868 let isCommutable = 1 in
5869 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
5870 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
5872 !strconcat(OpcodeStr,
5873 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5874 !strconcat(OpcodeStr,
5875 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5876 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
5878 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
5879 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
5881 !strconcat(OpcodeStr,
5882 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5883 !strconcat(OpcodeStr,
5884 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5887 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
5891 let Predicates = [HasAVX] in {
5892 let isCommutable = 0 in {
5893 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
5894 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5895 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
5896 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5897 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
5898 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
5899 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
5900 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
5901 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
5902 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5903 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
5904 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5906 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
5907 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5908 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
5909 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5910 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
5911 VR256, memopv32i8, i256mem, 0>, VEX_4V;
5914 let Constraints = "$src1 = $dst" in {
5915 let isCommutable = 0 in {
5916 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
5917 VR128, memopv16i8, i128mem>;
5918 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
5919 VR128, memopv16i8, i128mem>;
5920 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
5921 VR128, memopv16i8, i128mem>;
5922 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
5923 VR128, memopv16i8, i128mem>;
5925 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
5926 VR128, memopv16i8, i128mem>;
5927 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
5928 VR128, memopv16i8, i128mem>;
5931 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
5932 let Predicates = [HasAVX] in {
5933 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
5934 RegisterClass RC, X86MemOperand x86memop,
5935 PatFrag mem_frag, Intrinsic IntId> {
5936 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
5937 (ins RC:$src1, RC:$src2, RC:$src3),
5938 !strconcat(OpcodeStr,
5939 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5940 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
5941 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
5943 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
5944 (ins RC:$src1, x86memop:$src2, RC:$src3),
5945 !strconcat(OpcodeStr,
5946 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5948 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
5950 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
5954 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
5955 memopv16i8, int_x86_sse41_blendvpd>;
5956 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
5957 memopv16i8, int_x86_sse41_blendvps>;
5958 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
5959 memopv16i8, int_x86_sse41_pblendvb>;
5960 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
5961 memopv32i8, int_x86_avx_blendv_pd_256>;
5962 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
5963 memopv32i8, int_x86_avx_blendv_ps_256>;
5965 let Predicates = [HasAVX] in {
5966 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
5967 (v16i8 VR128:$src2))),
5968 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
5969 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
5970 (v4i32 VR128:$src2))),
5971 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
5972 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
5973 (v4f32 VR128:$src2))),
5974 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
5975 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
5976 (v2i64 VR128:$src2))),
5977 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
5978 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
5979 (v2f64 VR128:$src2))),
5980 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
5981 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
5982 (v8i32 VR256:$src2))),
5983 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
5984 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
5985 (v8f32 VR256:$src2))),
5986 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
5987 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
5988 (v4i64 VR256:$src2))),
5989 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
5990 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
5991 (v4f64 VR256:$src2))),
5992 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
5995 /// SS41I_ternary_int - SSE 4.1 ternary operator
5996 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
5997 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5998 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5999 (ins VR128:$src1, VR128:$src2),
6000 !strconcat(OpcodeStr,
6001 "\t{$src2, $dst|$dst, $src2}"),
6002 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6005 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6006 (ins VR128:$src1, i128mem:$src2),
6007 !strconcat(OpcodeStr,
6008 "\t{$src2, $dst|$dst, $src2}"),
6011 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
6015 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
6016 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
6017 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
6019 let Predicates = [HasSSE41] in {
6020 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6021 (v16i8 VR128:$src2))),
6022 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6023 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6024 (v4i32 VR128:$src2))),
6025 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6026 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6027 (v4f32 VR128:$src2))),
6028 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6029 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6030 (v2i64 VR128:$src2))),
6031 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6032 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6033 (v2f64 VR128:$src2))),
6034 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6037 let Predicates = [HasAVX] in
6038 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6039 "vmovntdqa\t{$src, $dst|$dst, $src}",
6040 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6042 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6043 "movntdqa\t{$src, $dst|$dst, $src}",
6044 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6047 //===----------------------------------------------------------------------===//
6048 // SSE4.2 - Compare Instructions
6049 //===----------------------------------------------------------------------===//
6051 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
6052 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
6053 Intrinsic IntId128, bit Is2Addr = 1> {
6054 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
6055 (ins VR128:$src1, VR128:$src2),
6057 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6058 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6059 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
6061 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
6062 (ins VR128:$src1, i128mem:$src2),
6064 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6065 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6067 (IntId128 VR128:$src1,
6068 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
6071 let Predicates = [HasAVX] in {
6072 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
6075 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
6076 (VPCMPGTQrr VR128:$src1, VR128:$src2)>;
6077 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
6078 (VPCMPGTQrm VR128:$src1, addr:$src2)>;
6081 let Constraints = "$src1 = $dst" in
6082 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
6084 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
6085 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
6086 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
6087 (PCMPGTQrm VR128:$src1, addr:$src2)>;
6089 //===----------------------------------------------------------------------===//
6090 // SSE4.2 - String/text Processing Instructions
6091 //===----------------------------------------------------------------------===//
6093 // Packed Compare Implicit Length Strings, Return Mask
6094 multiclass pseudo_pcmpistrm<string asm> {
6095 def REG : PseudoI<(outs VR128:$dst),
6096 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6097 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6099 def MEM : PseudoI<(outs VR128:$dst),
6100 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6101 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6102 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6105 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6106 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
6107 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6110 let Defs = [XMM0, EFLAGS], Predicates = [HasAVX] in {
6111 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6112 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6113 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6114 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6115 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6116 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6119 let Defs = [XMM0, EFLAGS] in {
6120 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6121 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6122 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6123 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6124 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6125 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6128 // Packed Compare Explicit Length Strings, Return Mask
6129 multiclass pseudo_pcmpestrm<string asm> {
6130 def REG : PseudoI<(outs VR128:$dst),
6131 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6132 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6133 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6134 def MEM : PseudoI<(outs VR128:$dst),
6135 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6136 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6137 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6140 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6141 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
6142 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6145 let Predicates = [HasAVX],
6146 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
6147 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6148 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6149 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6150 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6151 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6152 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6155 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
6156 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6157 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6158 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6159 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6160 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6161 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6164 // Packed Compare Implicit Length Strings, Return Index
6165 let Defs = [ECX, EFLAGS] in {
6166 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
6167 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6168 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6169 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6170 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
6171 (implicit EFLAGS)]>, OpSize;
6172 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6173 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6174 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6175 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
6176 (implicit EFLAGS)]>, OpSize;
6180 let Predicates = [HasAVX] in {
6181 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
6183 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
6185 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
6187 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
6189 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
6191 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
6195 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
6196 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
6197 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
6198 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
6199 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
6200 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
6202 // Packed Compare Explicit Length Strings, Return Index
6203 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
6204 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
6205 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6206 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6207 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6208 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
6209 (implicit EFLAGS)]>, OpSize;
6210 def rm : SS42AI<0x61, MRMSrcMem, (outs),
6211 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6212 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6214 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
6215 (implicit EFLAGS)]>, OpSize;
6219 let Predicates = [HasAVX] in {
6220 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
6222 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
6224 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
6226 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
6228 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
6230 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
6234 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
6235 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
6236 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
6237 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
6238 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
6239 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
6241 //===----------------------------------------------------------------------===//
6242 // SSE4.2 - CRC Instructions
6243 //===----------------------------------------------------------------------===//
6245 // No CRC instructions have AVX equivalents
6247 // crc intrinsic instruction
6248 // This set of instructions are only rm, the only difference is the size
6250 let Constraints = "$src1 = $dst" in {
6251 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
6252 (ins GR32:$src1, i8mem:$src2),
6253 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6255 (int_x86_sse42_crc32_32_8 GR32:$src1,
6256 (load addr:$src2)))]>;
6257 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
6258 (ins GR32:$src1, GR8:$src2),
6259 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6261 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
6262 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6263 (ins GR32:$src1, i16mem:$src2),
6264 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6266 (int_x86_sse42_crc32_32_16 GR32:$src1,
6267 (load addr:$src2)))]>,
6269 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6270 (ins GR32:$src1, GR16:$src2),
6271 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6273 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
6275 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6276 (ins GR32:$src1, i32mem:$src2),
6277 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6279 (int_x86_sse42_crc32_32_32 GR32:$src1,
6280 (load addr:$src2)))]>;
6281 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6282 (ins GR32:$src1, GR32:$src2),
6283 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6285 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
6286 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
6287 (ins GR64:$src1, i8mem:$src2),
6288 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6290 (int_x86_sse42_crc32_64_8 GR64:$src1,
6291 (load addr:$src2)))]>,
6293 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
6294 (ins GR64:$src1, GR8:$src2),
6295 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6297 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
6299 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
6300 (ins GR64:$src1, i64mem:$src2),
6301 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6303 (int_x86_sse42_crc32_64_64 GR64:$src1,
6304 (load addr:$src2)))]>,
6306 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
6307 (ins GR64:$src1, GR64:$src2),
6308 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6310 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
6314 //===----------------------------------------------------------------------===//
6315 // AES-NI Instructions
6316 //===----------------------------------------------------------------------===//
6318 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
6319 Intrinsic IntId128, bit Is2Addr = 1> {
6320 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
6321 (ins VR128:$src1, VR128:$src2),
6323 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6324 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6325 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
6327 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
6328 (ins VR128:$src1, i128mem:$src2),
6330 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6331 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6333 (IntId128 VR128:$src1,
6334 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
6337 // Perform One Round of an AES Encryption/Decryption Flow
6338 let Predicates = [HasAVX, HasAES] in {
6339 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
6340 int_x86_aesni_aesenc, 0>, VEX_4V;
6341 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
6342 int_x86_aesni_aesenclast, 0>, VEX_4V;
6343 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
6344 int_x86_aesni_aesdec, 0>, VEX_4V;
6345 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
6346 int_x86_aesni_aesdeclast, 0>, VEX_4V;
6349 let Constraints = "$src1 = $dst" in {
6350 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
6351 int_x86_aesni_aesenc>;
6352 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
6353 int_x86_aesni_aesenclast>;
6354 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
6355 int_x86_aesni_aesdec>;
6356 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
6357 int_x86_aesni_aesdeclast>;
6360 let Predicates = [HasAES] in {
6361 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
6362 (AESENCrr VR128:$src1, VR128:$src2)>;
6363 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
6364 (AESENCrm VR128:$src1, addr:$src2)>;
6365 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
6366 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
6367 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
6368 (AESENCLASTrm VR128:$src1, addr:$src2)>;
6369 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
6370 (AESDECrr VR128:$src1, VR128:$src2)>;
6371 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
6372 (AESDECrm VR128:$src1, addr:$src2)>;
6373 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
6374 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
6375 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
6376 (AESDECLASTrm VR128:$src1, addr:$src2)>;
6379 let Predicates = [HasAVX, HasAES], AddedComplexity = 20 in {
6380 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
6381 (VAESENCrr VR128:$src1, VR128:$src2)>;
6382 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
6383 (VAESENCrm VR128:$src1, addr:$src2)>;
6384 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
6385 (VAESENCLASTrr VR128:$src1, VR128:$src2)>;
6386 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
6387 (VAESENCLASTrm VR128:$src1, addr:$src2)>;
6388 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
6389 (VAESDECrr VR128:$src1, VR128:$src2)>;
6390 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
6391 (VAESDECrm VR128:$src1, addr:$src2)>;
6392 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
6393 (VAESDECLASTrr VR128:$src1, VR128:$src2)>;
6394 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
6395 (VAESDECLASTrm VR128:$src1, addr:$src2)>;
6398 // Perform the AES InvMixColumn Transformation
6399 let Predicates = [HasAVX, HasAES] in {
6400 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6402 "vaesimc\t{$src1, $dst|$dst, $src1}",
6404 (int_x86_aesni_aesimc VR128:$src1))]>,
6406 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
6407 (ins i128mem:$src1),
6408 "vaesimc\t{$src1, $dst|$dst, $src1}",
6410 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
6413 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6415 "aesimc\t{$src1, $dst|$dst, $src1}",
6417 (int_x86_aesni_aesimc VR128:$src1))]>,
6419 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
6420 (ins i128mem:$src1),
6421 "aesimc\t{$src1, $dst|$dst, $src1}",
6423 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
6426 // AES Round Key Generation Assist
6427 let Predicates = [HasAVX, HasAES] in {
6428 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
6429 (ins VR128:$src1, i8imm:$src2),
6430 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6432 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
6434 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
6435 (ins i128mem:$src1, i8imm:$src2),
6436 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6438 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
6442 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
6443 (ins VR128:$src1, i8imm:$src2),
6444 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6446 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
6448 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
6449 (ins i128mem:$src1, i8imm:$src2),
6450 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6452 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
6456 //===----------------------------------------------------------------------===//
6457 // CLMUL Instructions
6458 //===----------------------------------------------------------------------===//
6460 // Carry-less Multiplication instructions
6461 let Constraints = "$src1 = $dst" in {
6462 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
6463 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6464 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
6467 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
6468 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6469 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
6473 // AVX carry-less Multiplication instructions
6474 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
6475 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6476 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6479 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
6480 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6481 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6485 multiclass pclmul_alias<string asm, int immop> {
6486 def : InstAlias<!strconcat("pclmul", asm,
6487 "dq {$src, $dst|$dst, $src}"),
6488 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
6490 def : InstAlias<!strconcat("pclmul", asm,
6491 "dq {$src, $dst|$dst, $src}"),
6492 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
6494 def : InstAlias<!strconcat("vpclmul", asm,
6495 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
6496 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
6498 def : InstAlias<!strconcat("vpclmul", asm,
6499 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
6500 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
6502 defm : pclmul_alias<"hqhq", 0x11>;
6503 defm : pclmul_alias<"hqlq", 0x01>;
6504 defm : pclmul_alias<"lqhq", 0x10>;
6505 defm : pclmul_alias<"lqlq", 0x00>;
6507 //===----------------------------------------------------------------------===//
6509 //===----------------------------------------------------------------------===//
6511 //===----------------------------------------------------------------------===//
6512 // VBROADCAST - Load from memory and broadcast to all elements of the
6513 // destination operand
6515 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
6516 X86MemOperand x86memop, Intrinsic Int> :
6517 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
6518 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6519 [(set RC:$dst, (Int addr:$src))]>, VEX;
6521 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
6522 int_x86_avx_vbroadcastss>;
6523 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
6524 int_x86_avx_vbroadcastss_256>;
6525 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
6526 int_x86_avx_vbroadcast_sd_256>;
6527 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
6528 int_x86_avx_vbroadcastf128_pd_256>;
6530 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
6531 (VBROADCASTF128 addr:$src)>;
6533 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
6534 (VBROADCASTSSY addr:$src)>;
6535 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
6536 (VBROADCASTSD addr:$src)>;
6537 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
6538 (VBROADCASTSSY addr:$src)>;
6539 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
6540 (VBROADCASTSD addr:$src)>;
6542 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
6543 (VBROADCASTSS addr:$src)>;
6544 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
6545 (VBROADCASTSS addr:$src)>;
6547 //===----------------------------------------------------------------------===//
6548 // VINSERTF128 - Insert packed floating-point values
6550 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
6551 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
6552 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6554 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
6555 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
6556 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6559 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
6560 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6561 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
6562 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6563 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
6564 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6566 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
6568 (VINSERTF128rr VR256:$src1, VR128:$src2,
6569 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6570 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
6572 (VINSERTF128rr VR256:$src1, VR128:$src2,
6573 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6574 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
6576 (VINSERTF128rr VR256:$src1, VR128:$src2,
6577 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6578 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
6580 (VINSERTF128rr VR256:$src1, VR128:$src2,
6581 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6582 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
6584 (VINSERTF128rr VR256:$src1, VR128:$src2,
6585 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6586 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
6588 (VINSERTF128rr VR256:$src1, VR128:$src2,
6589 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6591 //===----------------------------------------------------------------------===//
6592 // VEXTRACTF128 - Extract packed floating-point values
6594 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
6595 (ins VR256:$src1, i8imm:$src2),
6596 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6598 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
6599 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
6600 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6603 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
6604 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6605 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
6606 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6607 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
6608 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6610 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6611 (v4f32 (VEXTRACTF128rr
6612 (v8f32 VR256:$src1),
6613 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6614 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6615 (v2f64 (VEXTRACTF128rr
6616 (v4f64 VR256:$src1),
6617 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6618 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6619 (v4i32 (VEXTRACTF128rr
6620 (v8i32 VR256:$src1),
6621 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6622 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6623 (v2i64 (VEXTRACTF128rr
6624 (v4i64 VR256:$src1),
6625 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6626 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6627 (v8i16 (VEXTRACTF128rr
6628 (v16i16 VR256:$src1),
6629 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6630 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6631 (v16i8 (VEXTRACTF128rr
6632 (v32i8 VR256:$src1),
6633 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6635 //===----------------------------------------------------------------------===//
6636 // VMASKMOV - Conditional SIMD Packed Loads and Stores
6638 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
6639 Intrinsic IntLd, Intrinsic IntLd256,
6640 Intrinsic IntSt, Intrinsic IntSt256,
6641 PatFrag pf128, PatFrag pf256> {
6642 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
6643 (ins VR128:$src1, f128mem:$src2),
6644 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6645 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
6647 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
6648 (ins VR256:$src1, f256mem:$src2),
6649 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6650 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
6652 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
6653 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
6654 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6655 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
6656 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
6657 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
6658 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6659 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
6662 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
6663 int_x86_avx_maskload_ps,
6664 int_x86_avx_maskload_ps_256,
6665 int_x86_avx_maskstore_ps,
6666 int_x86_avx_maskstore_ps_256,
6667 memopv4f32, memopv8f32>;
6668 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
6669 int_x86_avx_maskload_pd,
6670 int_x86_avx_maskload_pd_256,
6671 int_x86_avx_maskstore_pd,
6672 int_x86_avx_maskstore_pd_256,
6673 memopv2f64, memopv4f64>;
6675 //===----------------------------------------------------------------------===//
6676 // VPERMIL - Permute Single and Double Floating-Point Values
6678 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
6679 RegisterClass RC, X86MemOperand x86memop_f,
6680 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
6681 Intrinsic IntVar, Intrinsic IntImm> {
6682 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
6683 (ins RC:$src1, RC:$src2),
6684 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6685 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
6686 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
6687 (ins RC:$src1, x86memop_i:$src2),
6688 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6689 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
6691 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
6692 (ins RC:$src1, i8imm:$src2),
6693 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6694 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
6695 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
6696 (ins x86memop_f:$src1, i8imm:$src2),
6697 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6698 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
6701 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
6702 memopv4f32, memopv4i32,
6703 int_x86_avx_vpermilvar_ps,
6704 int_x86_avx_vpermil_ps>;
6705 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
6706 memopv8f32, memopv8i32,
6707 int_x86_avx_vpermilvar_ps_256,
6708 int_x86_avx_vpermil_ps_256>;
6709 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
6710 memopv2f64, memopv2i64,
6711 int_x86_avx_vpermilvar_pd,
6712 int_x86_avx_vpermil_pd>;
6713 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
6714 memopv4f64, memopv4i64,
6715 int_x86_avx_vpermilvar_pd_256,
6716 int_x86_avx_vpermil_pd_256>;
6718 def : Pat<(v8f32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
6719 (VPERMILPSYri VR256:$src1, imm:$imm)>;
6720 def : Pat<(v4f64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
6721 (VPERMILPDYri VR256:$src1, imm:$imm)>;
6722 def : Pat<(v8i32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
6723 (VPERMILPSYri VR256:$src1, imm:$imm)>;
6724 def : Pat<(v4i64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
6725 (VPERMILPDYri VR256:$src1, imm:$imm)>;
6727 //===----------------------------------------------------------------------===//
6728 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
6730 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
6731 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
6732 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6734 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
6735 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
6736 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6739 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
6740 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6741 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
6742 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6743 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
6744 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6746 def : Pat<(int_x86_avx_vperm2f128_ps_256
6747 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
6748 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6749 def : Pat<(int_x86_avx_vperm2f128_pd_256
6750 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
6751 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6752 def : Pat<(int_x86_avx_vperm2f128_si_256
6753 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
6754 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6756 def : Pat<(v8f32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6757 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6758 def : Pat<(v8i32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6759 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6760 def : Pat<(v4i64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6761 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6762 def : Pat<(v4f64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6763 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6764 def : Pat<(v32i8 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6765 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6766 def : Pat<(v16i16 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6767 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6769 //===----------------------------------------------------------------------===//
6770 // VZERO - Zero YMM registers
6772 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
6773 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
6774 // Zero All YMM registers
6775 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
6776 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
6778 // Zero Upper bits of YMM registers
6779 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
6780 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;