1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
24 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
25 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
26 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
27 [SDNPCommutative, SDNPAssociative]>;
28 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
33 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
34 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
35 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
36 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
37 def X86pextrb : SDNode<"X86ISD::PEXTRB",
38 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
39 def X86pextrw : SDNode<"X86ISD::PEXTRW",
40 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
41 def X86pinsrb : SDNode<"X86ISD::PINSRB",
42 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
43 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
44 def X86pinsrw : SDNode<"X86ISD::PINSRW",
45 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
46 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
47 def X86insrtps : SDNode<"X86ISD::INSERTPS",
48 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
49 SDTCisVT<2, f32>, SDTCisPtrTy<3>]>>;
50 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
51 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
52 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
53 [SDNPHasChain, SDNPMayLoad]>;
55 //===----------------------------------------------------------------------===//
56 // SSE Complex Patterns
57 //===----------------------------------------------------------------------===//
59 // These are 'extloads' from a scalar to the low element of a vector, zeroing
60 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
62 def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
63 [SDNPHasChain, SDNPMayLoad]>;
64 def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
65 [SDNPHasChain, SDNPMayLoad]>;
67 def ssmem : Operand<v4f32> {
68 let PrintMethod = "printf32mem";
69 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
71 def sdmem : Operand<v2f64> {
72 let PrintMethod = "printf64mem";
73 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
76 //===----------------------------------------------------------------------===//
77 // SSE pattern fragments
78 //===----------------------------------------------------------------------===//
80 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
81 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
82 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
83 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
85 // Like 'store', but always requires vector alignment.
86 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
87 (st node:$val, node:$ptr), [{
88 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
89 return !ST->isTruncatingStore() &&
90 ST->getAddressingMode() == ISD::UNINDEXED &&
91 ST->getAlignment() >= 16;
95 // Like 'load', but always requires vector alignment.
96 def alignedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
97 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
98 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
99 LD->getAddressingMode() == ISD::UNINDEXED &&
100 LD->getAlignment() >= 16;
104 def alignedloadfsf32 : PatFrag<(ops node:$ptr), (f32 (alignedload node:$ptr))>;
105 def alignedloadfsf64 : PatFrag<(ops node:$ptr), (f64 (alignedload node:$ptr))>;
106 def alignedloadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (alignedload node:$ptr))>;
107 def alignedloadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (alignedload node:$ptr))>;
108 def alignedloadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (alignedload node:$ptr))>;
109 def alignedloadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (alignedload node:$ptr))>;
111 // Like 'load', but uses special alignment checks suitable for use in
112 // memory operands in most SSE instructions, which are required to
113 // be naturally aligned on some targets but not on others.
114 // FIXME: Actually implement support for targets that don't require the
115 // alignment. This probably wants a subtarget predicate.
116 def memop : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
117 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
118 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
119 LD->getAddressingMode() == ISD::UNINDEXED &&
120 LD->getAlignment() >= 16;
124 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
125 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
126 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
127 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
128 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
129 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
130 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
132 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
134 // FIXME: 8 byte alignment for mmx reads is not required
135 def memop64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
136 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
137 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
138 LD->getAddressingMode() == ISD::UNINDEXED &&
139 LD->getAlignment() >= 8;
143 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
144 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
145 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
146 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
148 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
149 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
150 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
151 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
152 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
153 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
155 def fp32imm0 : PatLeaf<(f32 fpimm), [{
156 return N->isExactlyValue(+0.0);
159 def PSxLDQ_imm : SDNodeXForm<imm, [{
160 // Transformation function: imm >> 3
161 return getI32Imm(N->getValue() >> 3);
164 def SSE_CC_imm : SDNodeXForm<cond, [{
167 default: Val = 0; assert(0 && "Unexpected CondCode"); break;
168 case ISD::SETOEQ: Val = 0; break;
169 case ISD::SETOLT: Val = 1; break;
170 case ISD::SETOLE: Val = 2; break;
171 case ISD::SETUO: Val = 3; break;
172 case ISD::SETONE: Val = 4; break;
173 case ISD::SETOGE: Val = 5; break;
174 case ISD::SETOGT: Val = 6; break;
175 case ISD::SETO: Val = 7; break;
177 return getI8Imm(Val);
180 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
182 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
183 return getI8Imm(X86::getShuffleSHUFImmediate(N));
186 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
188 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
189 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
192 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
194 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
195 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
198 def SSE_splat_mask : PatLeaf<(build_vector), [{
199 return X86::isSplatMask(N);
200 }], SHUFFLE_get_shuf_imm>;
202 def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
203 return X86::isSplatLoMask(N);
206 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
207 return X86::isMOVHLPSMask(N);
210 def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
211 return X86::isMOVHLPS_v_undef_Mask(N);
214 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
215 return X86::isMOVHPMask(N);
218 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
219 return X86::isMOVLPMask(N);
222 def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
223 return X86::isMOVLMask(N);
226 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
227 return X86::isMOVSHDUPMask(N);
230 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
231 return X86::isMOVSLDUPMask(N);
234 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
235 return X86::isUNPCKLMask(N);
238 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
239 return X86::isUNPCKHMask(N);
242 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
243 return X86::isUNPCKL_v_undef_Mask(N);
246 def UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
247 return X86::isUNPCKH_v_undef_Mask(N);
250 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
251 return X86::isPSHUFDMask(N);
252 }], SHUFFLE_get_shuf_imm>;
254 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
255 return X86::isPSHUFHWMask(N);
256 }], SHUFFLE_get_pshufhw_imm>;
258 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
259 return X86::isPSHUFLWMask(N);
260 }], SHUFFLE_get_pshuflw_imm>;
262 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
263 return X86::isPSHUFDMask(N);
264 }], SHUFFLE_get_shuf_imm>;
266 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
267 return X86::isSHUFPMask(N);
268 }], SHUFFLE_get_shuf_imm>;
270 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
271 return X86::isSHUFPMask(N);
272 }], SHUFFLE_get_shuf_imm>;
275 //===----------------------------------------------------------------------===//
276 // SSE scalar FP Instructions
277 //===----------------------------------------------------------------------===//
279 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
280 // scheduler into a branch sequence.
281 // These are expanded by the scheduler.
282 let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
283 def CMOV_FR32 : I<0, Pseudo,
284 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
285 "#CMOV_FR32 PSEUDO!",
286 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
288 def CMOV_FR64 : I<0, Pseudo,
289 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
290 "#CMOV_FR64 PSEUDO!",
291 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
293 def CMOV_V4F32 : I<0, Pseudo,
294 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
295 "#CMOV_V4F32 PSEUDO!",
297 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
299 def CMOV_V2F64 : I<0, Pseudo,
300 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
301 "#CMOV_V2F64 PSEUDO!",
303 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
305 def CMOV_V2I64 : I<0, Pseudo,
306 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
307 "#CMOV_V2I64 PSEUDO!",
309 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
313 //===----------------------------------------------------------------------===//
315 //===----------------------------------------------------------------------===//
318 let neverHasSideEffects = 1 in
319 def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
320 "movss\t{$src, $dst|$dst, $src}", []>;
321 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
322 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
323 "movss\t{$src, $dst|$dst, $src}",
324 [(set FR32:$dst, (loadf32 addr:$src))]>;
325 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
326 "movss\t{$src, $dst|$dst, $src}",
327 [(store FR32:$src, addr:$dst)]>;
329 // Conversion instructions
330 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
331 "cvttss2si\t{$src, $dst|$dst, $src}",
332 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
333 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
334 "cvttss2si\t{$src, $dst|$dst, $src}",
335 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
336 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
337 "cvtsi2ss\t{$src, $dst|$dst, $src}",
338 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
339 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
340 "cvtsi2ss\t{$src, $dst|$dst, $src}",
341 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
343 // Match intrinsics which expect XMM operand(s).
344 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
345 "cvtss2si\t{$src, $dst|$dst, $src}",
346 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
347 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
348 "cvtss2si\t{$src, $dst|$dst, $src}",
349 [(set GR32:$dst, (int_x86_sse_cvtss2si
350 (load addr:$src)))]>;
352 // Match intrinisics which expect MM and XMM operand(s).
353 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
354 "cvtps2pi\t{$src, $dst|$dst, $src}",
355 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
356 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
357 "cvtps2pi\t{$src, $dst|$dst, $src}",
358 [(set VR64:$dst, (int_x86_sse_cvtps2pi
359 (load addr:$src)))]>;
360 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
361 "cvttps2pi\t{$src, $dst|$dst, $src}",
362 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
363 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
364 "cvttps2pi\t{$src, $dst|$dst, $src}",
365 [(set VR64:$dst, (int_x86_sse_cvttps2pi
366 (load addr:$src)))]>;
367 let Constraints = "$src1 = $dst" in {
368 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
369 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
370 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
371 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
373 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
374 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
375 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
376 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
377 (load addr:$src2)))]>;
380 // Aliases for intrinsics
381 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
382 "cvttss2si\t{$src, $dst|$dst, $src}",
384 (int_x86_sse_cvttss2si VR128:$src))]>;
385 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
386 "cvttss2si\t{$src, $dst|$dst, $src}",
388 (int_x86_sse_cvttss2si(load addr:$src)))]>;
390 let Constraints = "$src1 = $dst" in {
391 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
392 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
393 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
394 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
396 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
397 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
398 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
399 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
400 (loadi32 addr:$src2)))]>;
403 // Comparison instructions
404 let Constraints = "$src1 = $dst" in {
405 let neverHasSideEffects = 1 in
406 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
407 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
408 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
409 let neverHasSideEffects = 1, mayLoad = 1 in
410 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
411 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
412 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
415 let Defs = [EFLAGS] in {
416 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
417 "ucomiss\t{$src2, $src1|$src1, $src2}",
418 [(X86cmp FR32:$src1, FR32:$src2), (implicit EFLAGS)]>;
419 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
420 "ucomiss\t{$src2, $src1|$src1, $src2}",
421 [(X86cmp FR32:$src1, (loadf32 addr:$src2)),
425 // Aliases to match intrinsics which expect XMM operand(s).
426 let Constraints = "$src1 = $dst" in {
427 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
428 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
429 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
430 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
431 VR128:$src, imm:$cc))]>;
432 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
433 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src, SSECC:$cc),
434 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
435 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
436 (load addr:$src), imm:$cc))]>;
439 let Defs = [EFLAGS] in {
440 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs),
441 (ins VR128:$src1, VR128:$src2),
442 "ucomiss\t{$src2, $src1|$src1, $src2}",
443 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2),
445 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),
446 (ins VR128:$src1, f128mem:$src2),
447 "ucomiss\t{$src2, $src1|$src1, $src2}",
448 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2)),
451 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs),
452 (ins VR128:$src1, VR128:$src2),
453 "comiss\t{$src2, $src1|$src1, $src2}",
454 [(X86comi (v4f32 VR128:$src1), VR128:$src2),
456 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs),
457 (ins VR128:$src1, f128mem:$src2),
458 "comiss\t{$src2, $src1|$src1, $src2}",
459 [(X86comi (v4f32 VR128:$src1), (load addr:$src2)),
463 // Aliases of packed SSE1 instructions for scalar use. These all have names that
466 // Alias instructions that map fld0 to pxor for sse.
467 let isReMaterializable = 1 in
468 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
469 "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
470 Requires<[HasSSE1]>, TB, OpSize;
472 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
474 let neverHasSideEffects = 1 in
475 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
476 "movaps\t{$src, $dst|$dst, $src}", []>;
478 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
480 let isSimpleLoad = 1 in
481 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
482 "movaps\t{$src, $dst|$dst, $src}",
483 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
485 // Alias bitwise logical operations using SSE logical ops on packed FP values.
486 let Constraints = "$src1 = $dst" in {
487 let isCommutable = 1 in {
488 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
489 "andps\t{$src2, $dst|$dst, $src2}",
490 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
491 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
492 "orps\t{$src2, $dst|$dst, $src2}",
493 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
494 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
495 "xorps\t{$src2, $dst|$dst, $src2}",
496 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
499 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
500 "andps\t{$src2, $dst|$dst, $src2}",
501 [(set FR32:$dst, (X86fand FR32:$src1,
502 (memopfsf32 addr:$src2)))]>;
503 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
504 "orps\t{$src2, $dst|$dst, $src2}",
505 [(set FR32:$dst, (X86for FR32:$src1,
506 (memopfsf32 addr:$src2)))]>;
507 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
508 "xorps\t{$src2, $dst|$dst, $src2}",
509 [(set FR32:$dst, (X86fxor FR32:$src1,
510 (memopfsf32 addr:$src2)))]>;
511 let neverHasSideEffects = 1 in {
512 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
513 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
514 "andnps\t{$src2, $dst|$dst, $src2}", []>;
517 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
518 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
519 "andnps\t{$src2, $dst|$dst, $src2}", []>;
523 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
525 /// In addition, we also have a special variant of the scalar form here to
526 /// represent the associated intrinsic operation. This form is unlike the
527 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
528 /// and leaves the top elements undefined.
530 /// These three forms can each be reg+reg or reg+mem, so there are a total of
531 /// six "instructions".
533 let Constraints = "$src1 = $dst" in {
534 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
535 SDNode OpNode, Intrinsic F32Int,
536 bit Commutable = 0> {
537 // Scalar operation, reg+reg.
538 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
539 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
540 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
541 let isCommutable = Commutable;
544 // Scalar operation, reg+mem.
545 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
546 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
547 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
549 // Vector operation, reg+reg.
550 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
551 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
552 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
553 let isCommutable = Commutable;
556 // Vector operation, reg+mem.
557 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
558 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
559 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
561 // Intrinsic operation, reg+reg.
562 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
563 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
564 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
565 let isCommutable = Commutable;
568 // Intrinsic operation, reg+mem.
569 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
570 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
571 [(set VR128:$dst, (F32Int VR128:$src1,
572 sse_load_f32:$src2))]>;
576 // Arithmetic instructions
577 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
578 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
579 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
580 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
582 /// sse1_fp_binop_rm - Other SSE1 binops
584 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
585 /// instructions for a full-vector intrinsic form. Operations that map
586 /// onto C operators don't use this form since they just use the plain
587 /// vector form instead of having a separate vector intrinsic form.
589 /// This provides a total of eight "instructions".
591 let Constraints = "$src1 = $dst" in {
592 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
596 bit Commutable = 0> {
598 // Scalar operation, reg+reg.
599 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
600 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
601 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
602 let isCommutable = Commutable;
605 // Scalar operation, reg+mem.
606 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
607 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
608 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
610 // Vector operation, reg+reg.
611 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
612 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
613 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
614 let isCommutable = Commutable;
617 // Vector operation, reg+mem.
618 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
619 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
620 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
622 // Intrinsic operation, reg+reg.
623 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
624 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
625 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
626 let isCommutable = Commutable;
629 // Intrinsic operation, reg+mem.
630 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
631 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
632 [(set VR128:$dst, (F32Int VR128:$src1,
633 sse_load_f32:$src2))]>;
635 // Vector intrinsic operation, reg+reg.
636 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
637 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
638 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
639 let isCommutable = Commutable;
642 // Vector intrinsic operation, reg+mem.
643 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
644 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
645 [(set VR128:$dst, (V4F32Int VR128:$src1, (load addr:$src2)))]>;
649 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
650 int_x86_sse_max_ss, int_x86_sse_max_ps>;
651 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
652 int_x86_sse_min_ss, int_x86_sse_min_ps>;
654 //===----------------------------------------------------------------------===//
655 // SSE packed FP Instructions
658 let neverHasSideEffects = 1 in
659 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
660 "movaps\t{$src, $dst|$dst, $src}", []>;
661 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
662 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
663 "movaps\t{$src, $dst|$dst, $src}",
664 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
666 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
667 "movaps\t{$src, $dst|$dst, $src}",
668 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
670 let neverHasSideEffects = 1 in
671 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
672 "movups\t{$src, $dst|$dst, $src}", []>;
673 let isSimpleLoad = 1 in
674 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
675 "movups\t{$src, $dst|$dst, $src}",
676 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
677 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
678 "movups\t{$src, $dst|$dst, $src}",
679 [(store (v4f32 VR128:$src), addr:$dst)]>;
681 // Intrinsic forms of MOVUPS load and store
682 let isSimpleLoad = 1 in
683 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
684 "movups\t{$src, $dst|$dst, $src}",
685 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
686 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
687 "movups\t{$src, $dst|$dst, $src}",
688 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
690 let Constraints = "$src1 = $dst" in {
691 let AddedComplexity = 20 in {
692 def MOVLPSrm : PSI<0x12, MRMSrcMem,
693 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
694 "movlps\t{$src2, $dst|$dst, $src2}",
696 (v4f32 (vector_shuffle VR128:$src1,
697 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
698 MOVLP_shuffle_mask)))]>;
699 def MOVHPSrm : PSI<0x16, MRMSrcMem,
700 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
701 "movhps\t{$src2, $dst|$dst, $src2}",
703 (v4f32 (vector_shuffle VR128:$src1,
704 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
705 MOVHP_shuffle_mask)))]>;
707 } // Constraints = "$src1 = $dst"
710 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
711 "movlps\t{$src, $dst|$dst, $src}",
712 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
713 (iPTR 0))), addr:$dst)]>;
715 // v2f64 extract element 1 is always custom lowered to unpack high to low
716 // and extract element 0 so the non-store version isn't too horrible.
717 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
718 "movhps\t{$src, $dst|$dst, $src}",
719 [(store (f64 (vector_extract
720 (v2f64 (vector_shuffle
721 (bc_v2f64 (v4f32 VR128:$src)), (undef),
722 UNPCKH_shuffle_mask)), (iPTR 0))),
725 let Constraints = "$src1 = $dst" in {
726 let AddedComplexity = 15 in {
727 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
728 "movlhps\t{$src2, $dst|$dst, $src2}",
730 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
731 MOVHP_shuffle_mask)))]>;
733 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
734 "movhlps\t{$src2, $dst|$dst, $src2}",
736 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
737 MOVHLPS_shuffle_mask)))]>;
739 } // Constraints = "$src1 = $dst"
745 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
747 /// In addition, we also have a special variant of the scalar form here to
748 /// represent the associated intrinsic operation. This form is unlike the
749 /// plain scalar form, in that it takes an entire vector (instead of a
750 /// scalar) and leaves the top elements undefined.
752 /// And, we have a special variant form for a full-vector intrinsic form.
754 /// These four forms can each have a reg or a mem operand, so there are a
755 /// total of eight "instructions".
757 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
761 bit Commutable = 0> {
762 // Scalar operation, reg.
763 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
764 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
765 [(set FR32:$dst, (OpNode FR32:$src))]> {
766 let isCommutable = Commutable;
769 // Scalar operation, mem.
770 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
771 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
772 [(set FR32:$dst, (OpNode (load addr:$src)))]>;
774 // Vector operation, reg.
775 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
776 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
777 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
778 let isCommutable = Commutable;
781 // Vector operation, mem.
782 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
783 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
784 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
786 // Intrinsic operation, reg.
787 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
788 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
789 [(set VR128:$dst, (F32Int VR128:$src))]> {
790 let isCommutable = Commutable;
793 // Intrinsic operation, mem.
794 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
795 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
796 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
798 // Vector intrinsic operation, reg
799 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
800 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
801 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
802 let isCommutable = Commutable;
805 // Vector intrinsic operation, mem
806 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
807 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
808 [(set VR128:$dst, (V4F32Int (load addr:$src)))]>;
812 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
813 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
815 // Reciprocal approximations. Note that these typically require refinement
816 // in order to obtain suitable precision.
817 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
818 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
819 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
820 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
823 let Constraints = "$src1 = $dst" in {
824 let isCommutable = 1 in {
825 def ANDPSrr : PSI<0x54, MRMSrcReg,
826 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
827 "andps\t{$src2, $dst|$dst, $src2}",
828 [(set VR128:$dst, (v2i64
829 (and VR128:$src1, VR128:$src2)))]>;
830 def ORPSrr : PSI<0x56, MRMSrcReg,
831 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
832 "orps\t{$src2, $dst|$dst, $src2}",
833 [(set VR128:$dst, (v2i64
834 (or VR128:$src1, VR128:$src2)))]>;
835 def XORPSrr : PSI<0x57, MRMSrcReg,
836 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
837 "xorps\t{$src2, $dst|$dst, $src2}",
838 [(set VR128:$dst, (v2i64
839 (xor VR128:$src1, VR128:$src2)))]>;
842 def ANDPSrm : PSI<0x54, MRMSrcMem,
843 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
844 "andps\t{$src2, $dst|$dst, $src2}",
845 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
846 (memopv2i64 addr:$src2)))]>;
847 def ORPSrm : PSI<0x56, MRMSrcMem,
848 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
849 "orps\t{$src2, $dst|$dst, $src2}",
850 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
851 (memopv2i64 addr:$src2)))]>;
852 def XORPSrm : PSI<0x57, MRMSrcMem,
853 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
854 "xorps\t{$src2, $dst|$dst, $src2}",
855 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
856 (memopv2i64 addr:$src2)))]>;
857 def ANDNPSrr : PSI<0x55, MRMSrcReg,
858 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
859 "andnps\t{$src2, $dst|$dst, $src2}",
861 (v2i64 (and (xor VR128:$src1,
862 (bc_v2i64 (v4i32 immAllOnesV))),
864 def ANDNPSrm : PSI<0x55, MRMSrcMem,
865 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
866 "andnps\t{$src2, $dst|$dst, $src2}",
868 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
869 (bc_v2i64 (v4i32 immAllOnesV))),
870 (memopv2i64 addr:$src2))))]>;
873 let Constraints = "$src1 = $dst" in {
874 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
875 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
876 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
877 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
878 VR128:$src, imm:$cc))]>;
879 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
880 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
881 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
882 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
883 (load addr:$src), imm:$cc))]>;
885 def : Pat<(v4i32 (vsetcc (v4f32 VR128:$src1), VR128:$src2, cond:$cc)),
886 (CMPPSrri VR128:$src1, VR128:$src2, (SSE_CC_imm cond:$cc))>;
887 def : Pat<(v4i32 (vsetcc (v4f32 VR128:$src1), (memop addr:$src2), cond:$cc)),
888 (CMPPSrmi VR128:$src1, addr:$src2, (SSE_CC_imm cond:$cc))>;
890 // Shuffle and unpack instructions
891 let Constraints = "$src1 = $dst" in {
892 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
893 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
894 (outs VR128:$dst), (ins VR128:$src1,
895 VR128:$src2, i32i8imm:$src3),
896 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
898 (v4f32 (vector_shuffle
899 VR128:$src1, VR128:$src2,
900 SHUFP_shuffle_mask:$src3)))]>;
901 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
902 (outs VR128:$dst), (ins VR128:$src1,
903 f128mem:$src2, i32i8imm:$src3),
904 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
906 (v4f32 (vector_shuffle
907 VR128:$src1, (memopv4f32 addr:$src2),
908 SHUFP_shuffle_mask:$src3)))]>;
910 let AddedComplexity = 10 in {
911 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
912 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
913 "unpckhps\t{$src2, $dst|$dst, $src2}",
915 (v4f32 (vector_shuffle
916 VR128:$src1, VR128:$src2,
917 UNPCKH_shuffle_mask)))]>;
918 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
919 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
920 "unpckhps\t{$src2, $dst|$dst, $src2}",
922 (v4f32 (vector_shuffle
923 VR128:$src1, (memopv4f32 addr:$src2),
924 UNPCKH_shuffle_mask)))]>;
926 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
927 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
928 "unpcklps\t{$src2, $dst|$dst, $src2}",
930 (v4f32 (vector_shuffle
931 VR128:$src1, VR128:$src2,
932 UNPCKL_shuffle_mask)))]>;
933 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
934 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
935 "unpcklps\t{$src2, $dst|$dst, $src2}",
937 (v4f32 (vector_shuffle
938 VR128:$src1, (memopv4f32 addr:$src2),
939 UNPCKL_shuffle_mask)))]>;
941 } // Constraints = "$src1 = $dst"
944 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
945 "movmskps\t{$src, $dst|$dst, $src}",
946 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
947 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
948 "movmskpd\t{$src, $dst|$dst, $src}",
949 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
951 // Prefetch intrinsic.
952 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
953 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
954 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
955 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
956 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
957 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
958 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
959 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
961 // Non-temporal stores
962 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
963 "movntps\t{$src, $dst|$dst, $src}",
964 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
966 // Load, store, and memory fence
967 def SFENCE : PSI<0xAE, MRM7m, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
970 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
971 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
972 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
973 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
975 // Alias instructions that map zero vector to pxor / xorp* for sse.
976 let isReMaterializable = 1 in
977 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
979 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
981 let Predicates = [HasSSE1] in {
982 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
983 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
984 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
985 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
986 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
989 // FR32 to 128-bit vector conversion.
990 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
991 "movss\t{$src, $dst|$dst, $src}",
993 (v4f32 (scalar_to_vector FR32:$src)))]>;
994 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
995 "movss\t{$src, $dst|$dst, $src}",
997 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
999 // FIXME: may not be able to eliminate this movss with coalescing the src and
1000 // dest register classes are different. We really want to write this pattern
1002 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1003 // (f32 FR32:$src)>;
1004 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src),
1005 "movss\t{$src, $dst|$dst, $src}",
1006 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
1008 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
1009 "movss\t{$src, $dst|$dst, $src}",
1010 [(store (f32 (vector_extract (v4f32 VR128:$src),
1011 (iPTR 0))), addr:$dst)]>;
1014 // Move to lower bits of a VR128, leaving upper bits alone.
1015 // Three operand (but two address) aliases.
1016 let Constraints = "$src1 = $dst" in {
1017 let neverHasSideEffects = 1 in
1018 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
1019 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
1020 "movss\t{$src2, $dst|$dst, $src2}", []>;
1022 let AddedComplexity = 15 in
1023 def MOVLPSrr : SSI<0x10, MRMSrcReg,
1024 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1025 "movss\t{$src2, $dst|$dst, $src2}",
1027 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
1028 MOVL_shuffle_mask)))]>;
1031 // Move to lower bits of a VR128 and zeroing upper bits.
1032 // Loading from memory automatically zeroing upper bits.
1033 let AddedComplexity = 20 in
1034 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1035 "movss\t{$src, $dst|$dst, $src}",
1036 [(set VR128:$dst, (v4f32 (X86vzmovl (v4f32 (scalar_to_vector
1037 (loadf32 addr:$src))))))]>;
1039 def : Pat<(v4f32 (X86vzmovl (memopv4f32 addr:$src))),
1040 (MOVZSS2PSrm addr:$src)>;
1042 //===----------------------------------------------------------------------===//
1043 // SSE2 Instructions
1044 //===----------------------------------------------------------------------===//
1046 // Move Instructions
1047 let neverHasSideEffects = 1 in
1048 def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1049 "movsd\t{$src, $dst|$dst, $src}", []>;
1050 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1051 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1052 "movsd\t{$src, $dst|$dst, $src}",
1053 [(set FR64:$dst, (loadf64 addr:$src))]>;
1054 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1055 "movsd\t{$src, $dst|$dst, $src}",
1056 [(store FR64:$src, addr:$dst)]>;
1058 // Conversion instructions
1059 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1060 "cvttsd2si\t{$src, $dst|$dst, $src}",
1061 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1062 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1063 "cvttsd2si\t{$src, $dst|$dst, $src}",
1064 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1065 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1066 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1067 [(set FR32:$dst, (fround FR64:$src))]>;
1068 def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1069 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1070 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
1071 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1072 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1073 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1074 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1075 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1076 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1078 // SSE2 instructions with XS prefix
1079 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1080 "cvtss2sd\t{$src, $dst|$dst, $src}",
1081 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1082 Requires<[HasSSE2]>;
1083 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1084 "cvtss2sd\t{$src, $dst|$dst, $src}",
1085 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1086 Requires<[HasSSE2]>;
1088 // Match intrinsics which expect XMM operand(s).
1089 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1090 "cvtsd2si\t{$src, $dst|$dst, $src}",
1091 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1092 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1093 "cvtsd2si\t{$src, $dst|$dst, $src}",
1094 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1095 (load addr:$src)))]>;
1097 // Match intrinisics which expect MM and XMM operand(s).
1098 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1099 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1100 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1101 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1102 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1103 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1104 (load addr:$src)))]>;
1105 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1106 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1107 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1108 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1109 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1110 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1111 (load addr:$src)))]>;
1112 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1113 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1114 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1115 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1116 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1117 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1118 (load addr:$src)))]>;
1120 // Aliases for intrinsics
1121 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1122 "cvttsd2si\t{$src, $dst|$dst, $src}",
1124 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1125 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1126 "cvttsd2si\t{$src, $dst|$dst, $src}",
1127 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1128 (load addr:$src)))]>;
1130 // Comparison instructions
1131 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1132 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1133 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1134 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1136 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1137 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1138 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1141 let Defs = [EFLAGS] in {
1142 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1143 "ucomisd\t{$src2, $src1|$src1, $src2}",
1144 [(X86cmp FR64:$src1, FR64:$src2), (implicit EFLAGS)]>;
1145 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1146 "ucomisd\t{$src2, $src1|$src1, $src2}",
1147 [(X86cmp FR64:$src1, (loadf64 addr:$src2)),
1148 (implicit EFLAGS)]>;
1151 // Aliases to match intrinsics which expect XMM operand(s).
1152 let Constraints = "$src1 = $dst" in {
1153 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1154 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1155 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1156 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1157 VR128:$src, imm:$cc))]>;
1158 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1159 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1160 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1161 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1162 (load addr:$src), imm:$cc))]>;
1165 let Defs = [EFLAGS] in {
1166 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1167 "ucomisd\t{$src2, $src1|$src1, $src2}",
1168 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1169 (implicit EFLAGS)]>;
1170 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1171 "ucomisd\t{$src2, $src1|$src1, $src2}",
1172 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2)),
1173 (implicit EFLAGS)]>;
1175 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1176 "comisd\t{$src2, $src1|$src1, $src2}",
1177 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1178 (implicit EFLAGS)]>;
1179 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1180 "comisd\t{$src2, $src1|$src1, $src2}",
1181 [(X86comi (v2f64 VR128:$src1), (load addr:$src2)),
1182 (implicit EFLAGS)]>;
1185 // Aliases of packed SSE2 instructions for scalar use. These all have names that
1188 // Alias instructions that map fld0 to pxor for sse.
1189 let isReMaterializable = 1 in
1190 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
1191 "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
1192 Requires<[HasSSE2]>, TB, OpSize;
1194 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1196 let neverHasSideEffects = 1 in
1197 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1198 "movapd\t{$src, $dst|$dst, $src}", []>;
1200 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1202 let isSimpleLoad = 1 in
1203 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1204 "movapd\t{$src, $dst|$dst, $src}",
1205 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1207 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1208 let Constraints = "$src1 = $dst" in {
1209 let isCommutable = 1 in {
1210 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst),
1211 (ins FR64:$src1, FR64:$src2),
1212 "andpd\t{$src2, $dst|$dst, $src2}",
1213 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1214 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst),
1215 (ins FR64:$src1, FR64:$src2),
1216 "orpd\t{$src2, $dst|$dst, $src2}",
1217 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1218 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst),
1219 (ins FR64:$src1, FR64:$src2),
1220 "xorpd\t{$src2, $dst|$dst, $src2}",
1221 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1224 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst),
1225 (ins FR64:$src1, f128mem:$src2),
1226 "andpd\t{$src2, $dst|$dst, $src2}",
1227 [(set FR64:$dst, (X86fand FR64:$src1,
1228 (memopfsf64 addr:$src2)))]>;
1229 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst),
1230 (ins FR64:$src1, f128mem:$src2),
1231 "orpd\t{$src2, $dst|$dst, $src2}",
1232 [(set FR64:$dst, (X86for FR64:$src1,
1233 (memopfsf64 addr:$src2)))]>;
1234 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst),
1235 (ins FR64:$src1, f128mem:$src2),
1236 "xorpd\t{$src2, $dst|$dst, $src2}",
1237 [(set FR64:$dst, (X86fxor FR64:$src1,
1238 (memopfsf64 addr:$src2)))]>;
1240 let neverHasSideEffects = 1 in {
1241 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1242 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1243 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1245 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1246 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1247 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1251 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1253 /// In addition, we also have a special variant of the scalar form here to
1254 /// represent the associated intrinsic operation. This form is unlike the
1255 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1256 /// and leaves the top elements undefined.
1258 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1259 /// six "instructions".
1261 let Constraints = "$src1 = $dst" in {
1262 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1263 SDNode OpNode, Intrinsic F64Int,
1264 bit Commutable = 0> {
1265 // Scalar operation, reg+reg.
1266 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1267 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1268 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1269 let isCommutable = Commutable;
1272 // Scalar operation, reg+mem.
1273 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2),
1274 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1275 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1277 // Vector operation, reg+reg.
1278 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1279 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1280 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1281 let isCommutable = Commutable;
1284 // Vector operation, reg+mem.
1285 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1286 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1287 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1289 // Intrinsic operation, reg+reg.
1290 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1291 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1292 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1293 let isCommutable = Commutable;
1296 // Intrinsic operation, reg+mem.
1297 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1298 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1299 [(set VR128:$dst, (F64Int VR128:$src1,
1300 sse_load_f64:$src2))]>;
1304 // Arithmetic instructions
1305 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1306 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1307 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1308 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1310 /// sse2_fp_binop_rm - Other SSE2 binops
1312 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1313 /// instructions for a full-vector intrinsic form. Operations that map
1314 /// onto C operators don't use this form since they just use the plain
1315 /// vector form instead of having a separate vector intrinsic form.
1317 /// This provides a total of eight "instructions".
1319 let Constraints = "$src1 = $dst" in {
1320 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1324 bit Commutable = 0> {
1326 // Scalar operation, reg+reg.
1327 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1328 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1329 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1330 let isCommutable = Commutable;
1333 // Scalar operation, reg+mem.
1334 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2),
1335 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1336 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1338 // Vector operation, reg+reg.
1339 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1340 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1341 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1342 let isCommutable = Commutable;
1345 // Vector operation, reg+mem.
1346 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1347 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1348 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1350 // Intrinsic operation, reg+reg.
1351 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1352 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1353 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1354 let isCommutable = Commutable;
1357 // Intrinsic operation, reg+mem.
1358 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1359 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1360 [(set VR128:$dst, (F64Int VR128:$src1,
1361 sse_load_f64:$src2))]>;
1363 // Vector intrinsic operation, reg+reg.
1364 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1365 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1366 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1367 let isCommutable = Commutable;
1370 // Vector intrinsic operation, reg+mem.
1371 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1372 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1373 [(set VR128:$dst, (V2F64Int VR128:$src1, (load addr:$src2)))]>;
1377 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1378 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1379 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1380 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1382 //===----------------------------------------------------------------------===//
1383 // SSE packed FP Instructions
1385 // Move Instructions
1386 let neverHasSideEffects = 1 in
1387 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1388 "movapd\t{$src, $dst|$dst, $src}", []>;
1389 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1390 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1391 "movapd\t{$src, $dst|$dst, $src}",
1392 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1394 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1395 "movapd\t{$src, $dst|$dst, $src}",
1396 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1398 let neverHasSideEffects = 1 in
1399 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1400 "movupd\t{$src, $dst|$dst, $src}", []>;
1401 let isSimpleLoad = 1 in
1402 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1403 "movupd\t{$src, $dst|$dst, $src}",
1404 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1405 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1406 "movupd\t{$src, $dst|$dst, $src}",
1407 [(store (v2f64 VR128:$src), addr:$dst)]>;
1409 // Intrinsic forms of MOVUPD load and store
1410 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1411 "movupd\t{$src, $dst|$dst, $src}",
1412 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1413 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1414 "movupd\t{$src, $dst|$dst, $src}",
1415 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1417 let Constraints = "$src1 = $dst" in {
1418 let AddedComplexity = 20 in {
1419 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1420 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1421 "movlpd\t{$src2, $dst|$dst, $src2}",
1423 (v2f64 (vector_shuffle VR128:$src1,
1424 (scalar_to_vector (loadf64 addr:$src2)),
1425 MOVLP_shuffle_mask)))]>;
1426 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1427 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1428 "movhpd\t{$src2, $dst|$dst, $src2}",
1430 (v2f64 (vector_shuffle VR128:$src1,
1431 (scalar_to_vector (loadf64 addr:$src2)),
1432 MOVHP_shuffle_mask)))]>;
1433 } // AddedComplexity
1434 } // Constraints = "$src1 = $dst"
1436 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1437 "movlpd\t{$src, $dst|$dst, $src}",
1438 [(store (f64 (vector_extract (v2f64 VR128:$src),
1439 (iPTR 0))), addr:$dst)]>;
1441 // v2f64 extract element 1 is always custom lowered to unpack high to low
1442 // and extract element 0 so the non-store version isn't too horrible.
1443 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1444 "movhpd\t{$src, $dst|$dst, $src}",
1445 [(store (f64 (vector_extract
1446 (v2f64 (vector_shuffle VR128:$src, (undef),
1447 UNPCKH_shuffle_mask)), (iPTR 0))),
1450 // SSE2 instructions without OpSize prefix
1451 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1452 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1453 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1454 TB, Requires<[HasSSE2]>;
1455 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1456 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1457 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1458 (bitconvert (memopv2i64 addr:$src))))]>,
1459 TB, Requires<[HasSSE2]>;
1461 // SSE2 instructions with XS prefix
1462 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1463 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1464 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1465 XS, Requires<[HasSSE2]>;
1466 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1467 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1468 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1469 (bitconvert (memopv2i64 addr:$src))))]>,
1470 XS, Requires<[HasSSE2]>;
1472 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1473 "cvtps2dq\t{$src, $dst|$dst, $src}",
1474 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1475 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1476 "cvtps2dq\t{$src, $dst|$dst, $src}",
1477 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1478 (load addr:$src)))]>;
1479 // SSE2 packed instructions with XS prefix
1480 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1481 "cvttps2dq\t{$src, $dst|$dst, $src}",
1482 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
1483 XS, Requires<[HasSSE2]>;
1484 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1485 "cvttps2dq\t{$src, $dst|$dst, $src}",
1486 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1487 (load addr:$src)))]>,
1488 XS, Requires<[HasSSE2]>;
1490 // SSE2 packed instructions with XD prefix
1491 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1492 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1493 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1494 XD, Requires<[HasSSE2]>;
1495 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1496 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1497 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1498 (load addr:$src)))]>,
1499 XD, Requires<[HasSSE2]>;
1501 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1502 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1503 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1504 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1505 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1506 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1507 (load addr:$src)))]>;
1509 // SSE2 instructions without OpSize prefix
1510 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1511 "cvtps2pd\t{$src, $dst|$dst, $src}",
1512 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1513 TB, Requires<[HasSSE2]>;
1514 def Int_CVTPS2PDrm : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins f64mem:$src),
1515 "cvtps2pd\t{$src, $dst|$dst, $src}",
1516 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1517 (load addr:$src)))]>,
1518 TB, Requires<[HasSSE2]>;
1520 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1521 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1522 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1523 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins f128mem:$src),
1524 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1525 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1526 (load addr:$src)))]>;
1528 // Match intrinsics which expect XMM operand(s).
1529 // Aliases for intrinsics
1530 let Constraints = "$src1 = $dst" in {
1531 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1532 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1533 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1534 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1536 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1537 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1538 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1539 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1540 (loadi32 addr:$src2)))]>;
1541 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1542 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1543 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1544 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1546 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1547 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1548 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1549 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1550 (load addr:$src2)))]>;
1551 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1552 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1553 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1554 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1555 VR128:$src2))]>, XS,
1556 Requires<[HasSSE2]>;
1557 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1558 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1559 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1560 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1561 (load addr:$src2)))]>, XS,
1562 Requires<[HasSSE2]>;
1567 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1569 /// In addition, we also have a special variant of the scalar form here to
1570 /// represent the associated intrinsic operation. This form is unlike the
1571 /// plain scalar form, in that it takes an entire vector (instead of a
1572 /// scalar) and leaves the top elements undefined.
1574 /// And, we have a special variant form for a full-vector intrinsic form.
1576 /// These four forms can each have a reg or a mem operand, so there are a
1577 /// total of eight "instructions".
1579 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1583 bit Commutable = 0> {
1584 // Scalar operation, reg.
1585 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1586 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1587 [(set FR64:$dst, (OpNode FR64:$src))]> {
1588 let isCommutable = Commutable;
1591 // Scalar operation, mem.
1592 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1593 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1594 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1596 // Vector operation, reg.
1597 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1598 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1599 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1600 let isCommutable = Commutable;
1603 // Vector operation, mem.
1604 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1605 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1606 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1608 // Intrinsic operation, reg.
1609 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1610 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1611 [(set VR128:$dst, (F64Int VR128:$src))]> {
1612 let isCommutable = Commutable;
1615 // Intrinsic operation, mem.
1616 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1617 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1618 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1620 // Vector intrinsic operation, reg
1621 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1622 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1623 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1624 let isCommutable = Commutable;
1627 // Vector intrinsic operation, mem
1628 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1629 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1630 [(set VR128:$dst, (V2F64Int (load addr:$src)))]>;
1634 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1635 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1637 // There is no f64 version of the reciprocal approximation instructions.
1640 let Constraints = "$src1 = $dst" in {
1641 let isCommutable = 1 in {
1642 def ANDPDrr : PDI<0x54, MRMSrcReg,
1643 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1644 "andpd\t{$src2, $dst|$dst, $src2}",
1646 (and (bc_v2i64 (v2f64 VR128:$src1)),
1647 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1648 def ORPDrr : PDI<0x56, MRMSrcReg,
1649 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1650 "orpd\t{$src2, $dst|$dst, $src2}",
1652 (or (bc_v2i64 (v2f64 VR128:$src1)),
1653 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1654 def XORPDrr : PDI<0x57, MRMSrcReg,
1655 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1656 "xorpd\t{$src2, $dst|$dst, $src2}",
1658 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1659 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1662 def ANDPDrm : PDI<0x54, MRMSrcMem,
1663 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1664 "andpd\t{$src2, $dst|$dst, $src2}",
1666 (and (bc_v2i64 (v2f64 VR128:$src1)),
1667 (memopv2i64 addr:$src2)))]>;
1668 def ORPDrm : PDI<0x56, MRMSrcMem,
1669 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1670 "orpd\t{$src2, $dst|$dst, $src2}",
1672 (or (bc_v2i64 (v2f64 VR128:$src1)),
1673 (memopv2i64 addr:$src2)))]>;
1674 def XORPDrm : PDI<0x57, MRMSrcMem,
1675 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1676 "xorpd\t{$src2, $dst|$dst, $src2}",
1678 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1679 (memopv2i64 addr:$src2)))]>;
1680 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1681 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1682 "andnpd\t{$src2, $dst|$dst, $src2}",
1684 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1685 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1686 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1687 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1688 "andnpd\t{$src2, $dst|$dst, $src2}",
1690 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1691 (memopv2i64 addr:$src2)))]>;
1694 let Constraints = "$src1 = $dst" in {
1695 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1696 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1697 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1698 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1699 VR128:$src, imm:$cc))]>;
1700 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1701 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1702 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1703 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1704 (load addr:$src), imm:$cc))]>;
1706 def : Pat<(v2i64 (vsetcc (v2f64 VR128:$src1), VR128:$src2, cond:$cc)),
1707 (CMPPDrri VR128:$src1, VR128:$src2, (SSE_CC_imm cond:$cc))>;
1708 def : Pat<(v2i64 (vsetcc (v2f64 VR128:$src1), (memop addr:$src2), cond:$cc)),
1709 (CMPPDrmi VR128:$src1, addr:$src2, (SSE_CC_imm cond:$cc))>;
1711 // Shuffle and unpack instructions
1712 let Constraints = "$src1 = $dst" in {
1713 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1714 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1715 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1716 [(set VR128:$dst, (v2f64 (vector_shuffle
1717 VR128:$src1, VR128:$src2,
1718 SHUFP_shuffle_mask:$src3)))]>;
1719 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1720 (outs VR128:$dst), (ins VR128:$src1,
1721 f128mem:$src2, i8imm:$src3),
1722 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1724 (v2f64 (vector_shuffle
1725 VR128:$src1, (memopv2f64 addr:$src2),
1726 SHUFP_shuffle_mask:$src3)))]>;
1728 let AddedComplexity = 10 in {
1729 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1730 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1731 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1733 (v2f64 (vector_shuffle
1734 VR128:$src1, VR128:$src2,
1735 UNPCKH_shuffle_mask)))]>;
1736 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1737 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1738 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1740 (v2f64 (vector_shuffle
1741 VR128:$src1, (memopv2f64 addr:$src2),
1742 UNPCKH_shuffle_mask)))]>;
1744 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1745 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1746 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1748 (v2f64 (vector_shuffle
1749 VR128:$src1, VR128:$src2,
1750 UNPCKL_shuffle_mask)))]>;
1751 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1752 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1753 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1755 (v2f64 (vector_shuffle
1756 VR128:$src1, (memopv2f64 addr:$src2),
1757 UNPCKL_shuffle_mask)))]>;
1758 } // AddedComplexity
1759 } // Constraints = "$src1 = $dst"
1762 //===----------------------------------------------------------------------===//
1763 // SSE integer instructions
1765 // Move Instructions
1766 let neverHasSideEffects = 1 in
1767 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1768 "movdqa\t{$src, $dst|$dst, $src}", []>;
1769 let isSimpleLoad = 1, mayLoad = 1 in
1770 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1771 "movdqa\t{$src, $dst|$dst, $src}",
1772 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1774 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1775 "movdqa\t{$src, $dst|$dst, $src}",
1776 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1777 let isSimpleLoad = 1, mayLoad = 1 in
1778 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1779 "movdqu\t{$src, $dst|$dst, $src}",
1780 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1781 XS, Requires<[HasSSE2]>;
1783 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1784 "movdqu\t{$src, $dst|$dst, $src}",
1785 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1786 XS, Requires<[HasSSE2]>;
1788 // Intrinsic forms of MOVDQU load and store
1789 let isSimpleLoad = 1 in
1790 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1791 "movdqu\t{$src, $dst|$dst, $src}",
1792 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1793 XS, Requires<[HasSSE2]>;
1794 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1795 "movdqu\t{$src, $dst|$dst, $src}",
1796 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1797 XS, Requires<[HasSSE2]>;
1799 let Constraints = "$src1 = $dst" in {
1801 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1802 bit Commutable = 0> {
1803 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1804 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1805 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1806 let isCommutable = Commutable;
1808 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1809 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1810 [(set VR128:$dst, (IntId VR128:$src1,
1811 (bitconvert (memopv2i64 addr:$src2))))]>;
1814 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1816 Intrinsic IntId, Intrinsic IntId2> {
1817 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1818 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1819 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1820 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1821 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1822 [(set VR128:$dst, (IntId VR128:$src1,
1823 (bitconvert (memopv2i64 addr:$src2))))]>;
1824 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1825 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1826 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
1829 /// PDI_binop_rm - Simple SSE2 binary operator.
1830 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1831 ValueType OpVT, bit Commutable = 0> {
1832 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1833 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1834 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1835 let isCommutable = Commutable;
1837 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1838 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1839 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1840 (bitconvert (memopv2i64 addr:$src2)))))]>;
1843 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1845 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1846 /// to collapse (bitconvert VT to VT) into its operand.
1848 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1849 bit Commutable = 0> {
1850 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1851 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1852 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1853 let isCommutable = Commutable;
1855 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1856 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1857 [(set VR128:$dst, (OpNode VR128:$src1,(memopv2i64 addr:$src2)))]>;
1860 } // Constraints = "$src1 = $dst"
1862 // 128-bit Integer Arithmetic
1864 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1865 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1866 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1867 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1869 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1870 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1871 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1872 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1874 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1875 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1876 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1877 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1879 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1880 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1881 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1882 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1884 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1886 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1887 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1888 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1890 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1892 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1893 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1896 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1897 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1898 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1899 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1900 defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
1903 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
1904 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
1905 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
1906 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
1907 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
1908 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
1910 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
1911 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
1912 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
1913 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
1914 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x72, MRM2r, "psrlq",
1915 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
1917 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
1918 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
1919 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x71, MRM4r, "psrad",
1920 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
1922 // 128-bit logical shifts.
1923 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1924 def PSLLDQri : PDIi8<0x73, MRM7r,
1925 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1926 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
1927 def PSRLDQri : PDIi8<0x73, MRM3r,
1928 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1929 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
1930 // PSRADQri doesn't exist in SSE[1-3].
1933 let Predicates = [HasSSE2] in {
1934 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1935 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1936 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1937 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1938 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
1939 (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1943 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1944 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1945 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1947 let Constraints = "$src1 = $dst" in {
1948 def PANDNrr : PDI<0xDF, MRMSrcReg,
1949 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1950 "pandn\t{$src2, $dst|$dst, $src2}",
1951 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1954 def PANDNrm : PDI<0xDF, MRMSrcMem,
1955 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1956 "pandn\t{$src2, $dst|$dst, $src2}",
1957 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1958 (memopv2i64 addr:$src2))))]>;
1961 // SSE2 Integer comparison
1962 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
1963 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
1964 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
1965 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
1966 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
1967 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
1969 // Pack instructions
1970 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
1971 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
1972 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
1974 // Shuffle and unpack instructions
1975 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
1976 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
1977 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1978 [(set VR128:$dst, (v4i32 (vector_shuffle
1979 VR128:$src1, (undef),
1980 PSHUFD_shuffle_mask:$src2)))]>;
1981 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
1982 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
1983 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1984 [(set VR128:$dst, (v4i32 (vector_shuffle
1985 (bc_v4i32(memopv2i64 addr:$src1)),
1987 PSHUFD_shuffle_mask:$src2)))]>;
1989 // SSE2 with ImmT == Imm8 and XS prefix.
1990 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
1991 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
1992 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1993 [(set VR128:$dst, (v8i16 (vector_shuffle
1994 VR128:$src1, (undef),
1995 PSHUFHW_shuffle_mask:$src2)))]>,
1996 XS, Requires<[HasSSE2]>;
1997 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
1998 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
1999 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2000 [(set VR128:$dst, (v8i16 (vector_shuffle
2001 (bc_v8i16 (memopv2i64 addr:$src1)),
2003 PSHUFHW_shuffle_mask:$src2)))]>,
2004 XS, Requires<[HasSSE2]>;
2006 // SSE2 with ImmT == Imm8 and XD prefix.
2007 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2008 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2009 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2010 [(set VR128:$dst, (v8i16 (vector_shuffle
2011 VR128:$src1, (undef),
2012 PSHUFLW_shuffle_mask:$src2)))]>,
2013 XD, Requires<[HasSSE2]>;
2014 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2015 (outs VR128:$dst), (ins i128mem:$src1, i32i8imm:$src2),
2016 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2017 [(set VR128:$dst, (v8i16 (vector_shuffle
2018 (bc_v8i16 (memopv2i64 addr:$src1)),
2020 PSHUFLW_shuffle_mask:$src2)))]>,
2021 XD, Requires<[HasSSE2]>;
2024 let Constraints = "$src1 = $dst" in {
2025 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
2026 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2027 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2029 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2030 UNPCKL_shuffle_mask)))]>;
2031 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
2032 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2033 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2035 (v16i8 (vector_shuffle VR128:$src1,
2036 (bc_v16i8 (memopv2i64 addr:$src2)),
2037 UNPCKL_shuffle_mask)))]>;
2038 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
2039 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2040 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2042 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2043 UNPCKL_shuffle_mask)))]>;
2044 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
2045 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2046 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2048 (v8i16 (vector_shuffle VR128:$src1,
2049 (bc_v8i16 (memopv2i64 addr:$src2)),
2050 UNPCKL_shuffle_mask)))]>;
2051 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2052 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2053 "punpckldq\t{$src2, $dst|$dst, $src2}",
2055 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2056 UNPCKL_shuffle_mask)))]>;
2057 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2058 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2059 "punpckldq\t{$src2, $dst|$dst, $src2}",
2061 (v4i32 (vector_shuffle VR128:$src1,
2062 (bc_v4i32 (memopv2i64 addr:$src2)),
2063 UNPCKL_shuffle_mask)))]>;
2064 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2065 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2066 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2068 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2069 UNPCKL_shuffle_mask)))]>;
2070 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2071 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2072 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2074 (v2i64 (vector_shuffle VR128:$src1,
2075 (memopv2i64 addr:$src2),
2076 UNPCKL_shuffle_mask)))]>;
2078 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2079 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2080 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2082 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2083 UNPCKH_shuffle_mask)))]>;
2084 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2085 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2086 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2088 (v16i8 (vector_shuffle VR128:$src1,
2089 (bc_v16i8 (memopv2i64 addr:$src2)),
2090 UNPCKH_shuffle_mask)))]>;
2091 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2092 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2093 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2095 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2096 UNPCKH_shuffle_mask)))]>;
2097 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2098 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2099 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2101 (v8i16 (vector_shuffle VR128:$src1,
2102 (bc_v8i16 (memopv2i64 addr:$src2)),
2103 UNPCKH_shuffle_mask)))]>;
2104 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2105 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2106 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2108 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2109 UNPCKH_shuffle_mask)))]>;
2110 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2111 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2112 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2114 (v4i32 (vector_shuffle VR128:$src1,
2115 (bc_v4i32 (memopv2i64 addr:$src2)),
2116 UNPCKH_shuffle_mask)))]>;
2117 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2118 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2119 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2121 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2122 UNPCKH_shuffle_mask)))]>;
2123 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2124 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2125 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2127 (v2i64 (vector_shuffle VR128:$src1,
2128 (memopv2i64 addr:$src2),
2129 UNPCKH_shuffle_mask)))]>;
2133 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2134 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2135 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2136 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2138 let Constraints = "$src1 = $dst" in {
2139 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2140 (outs VR128:$dst), (ins VR128:$src1,
2141 GR32:$src2, i32i8imm:$src3),
2142 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2144 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2145 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2146 (outs VR128:$dst), (ins VR128:$src1,
2147 i16mem:$src2, i32i8imm:$src3),
2148 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2150 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2155 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2156 "pmovmskb\t{$src, $dst|$dst, $src}",
2157 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2159 // Conditional store
2161 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2162 "maskmovdqu\t{$mask, $src|$src, $mask}",
2163 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2165 // Non-temporal stores
2166 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2167 "movntpd\t{$src, $dst|$dst, $src}",
2168 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2169 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2170 "movntdq\t{$src, $dst|$dst, $src}",
2171 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2172 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2173 "movnti\t{$src, $dst|$dst, $src}",
2174 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2175 TB, Requires<[HasSSE2]>;
2178 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2179 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2180 TB, Requires<[HasSSE2]>;
2182 // Load, store, and memory fence
2183 def LFENCE : I<0xAE, MRM5m, (outs), (ins),
2184 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2185 def MFENCE : I<0xAE, MRM6m, (outs), (ins),
2186 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2188 //TODO: custom lower this so as to never even generate the noop
2189 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2191 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2192 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2193 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2196 // Alias instructions that map zero vector to pxor / xorp* for sse.
2197 let isReMaterializable = 1 in
2198 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
2199 "pcmpeqd\t$dst, $dst",
2200 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2202 // FR64 to 128-bit vector conversion.
2203 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src),
2204 "movsd\t{$src, $dst|$dst, $src}",
2206 (v2f64 (scalar_to_vector FR64:$src)))]>;
2207 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2208 "movsd\t{$src, $dst|$dst, $src}",
2210 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2212 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2213 "movd\t{$src, $dst|$dst, $src}",
2215 (v4i32 (scalar_to_vector GR32:$src)))]>;
2216 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2217 "movd\t{$src, $dst|$dst, $src}",
2219 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2221 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2222 "movd\t{$src, $dst|$dst, $src}",
2223 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2225 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2226 "movd\t{$src, $dst|$dst, $src}",
2227 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2229 // SSE2 instructions with XS prefix
2230 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2231 "movq\t{$src, $dst|$dst, $src}",
2233 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2234 Requires<[HasSSE2]>;
2235 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2236 "movq\t{$src, $dst|$dst, $src}",
2237 [(store (i64 (vector_extract (v2i64 VR128:$src),
2238 (iPTR 0))), addr:$dst)]>;
2240 // FIXME: may not be able to eliminate this movss with coalescing the src and
2241 // dest register classes are different. We really want to write this pattern
2243 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2244 // (f32 FR32:$src)>;
2245 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src),
2246 "movsd\t{$src, $dst|$dst, $src}",
2247 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2249 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
2250 "movsd\t{$src, $dst|$dst, $src}",
2251 [(store (f64 (vector_extract (v2f64 VR128:$src),
2252 (iPTR 0))), addr:$dst)]>;
2253 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2254 "movd\t{$src, $dst|$dst, $src}",
2255 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2257 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2258 "movd\t{$src, $dst|$dst, $src}",
2259 [(store (i32 (vector_extract (v4i32 VR128:$src),
2260 (iPTR 0))), addr:$dst)]>;
2262 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2263 "movd\t{$src, $dst|$dst, $src}",
2264 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2265 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2266 "movd\t{$src, $dst|$dst, $src}",
2267 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2270 // Move to lower bits of a VR128, leaving upper bits alone.
2271 // Three operand (but two address) aliases.
2272 let Constraints = "$src1 = $dst" in {
2273 let neverHasSideEffects = 1 in
2274 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
2275 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
2276 "movsd\t{$src2, $dst|$dst, $src2}", []>;
2278 let AddedComplexity = 15 in
2279 def MOVLPDrr : SDI<0x10, MRMSrcReg,
2280 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2281 "movsd\t{$src2, $dst|$dst, $src2}",
2283 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2284 MOVL_shuffle_mask)))]>;
2287 // Store / copy lower 64-bits of a XMM register.
2288 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2289 "movq\t{$src, $dst|$dst, $src}",
2290 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2292 // Move to lower bits of a VR128 and zeroing upper bits.
2293 // Loading from memory automatically zeroing upper bits.
2294 let AddedComplexity = 20 in {
2295 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2296 "movsd\t{$src, $dst|$dst, $src}",
2298 (v2f64 (X86vzmovl (v2f64 (scalar_to_vector
2299 (loadf64 addr:$src))))))]>;
2301 def : Pat<(v2f64 (X86vzmovl (memopv2f64 addr:$src))),
2302 (MOVZSD2PDrm addr:$src)>;
2303 def : Pat<(v2f64 (X86vzload addr:$src)), (MOVZSD2PDrm addr:$src)>;
2306 // movd / movq to XMM register zero-extends
2307 let AddedComplexity = 15 in {
2308 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2309 "movd\t{$src, $dst|$dst, $src}",
2310 [(set VR128:$dst, (v4i32 (X86vzmovl
2311 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2312 // This is X86-64 only.
2313 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2314 "mov{d|q}\t{$src, $dst|$dst, $src}",
2315 [(set VR128:$dst, (v2i64 (X86vzmovl
2316 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2319 let AddedComplexity = 20 in {
2320 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2321 "movd\t{$src, $dst|$dst, $src}",
2323 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2324 (loadi32 addr:$src))))))]>;
2325 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2326 "movq\t{$src, $dst|$dst, $src}",
2328 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2329 (loadi64 addr:$src))))))]>, XS,
2330 Requires<[HasSSE2]>;
2332 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2335 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2336 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2337 let AddedComplexity = 15 in
2338 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2339 "movq\t{$src, $dst|$dst, $src}",
2340 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2341 XS, Requires<[HasSSE2]>;
2343 let AddedComplexity = 20 in
2344 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2345 "movq\t{$src, $dst|$dst, $src}",
2346 [(set VR128:$dst, (v2i64 (X86vzmovl
2347 (memopv2i64 addr:$src))))]>,
2348 XS, Requires<[HasSSE2]>;
2350 //===----------------------------------------------------------------------===//
2351 // SSE3 Instructions
2352 //===----------------------------------------------------------------------===//
2354 // Move Instructions
2355 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2356 "movshdup\t{$src, $dst|$dst, $src}",
2357 [(set VR128:$dst, (v4f32 (vector_shuffle
2358 VR128:$src, (undef),
2359 MOVSHDUP_shuffle_mask)))]>;
2360 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2361 "movshdup\t{$src, $dst|$dst, $src}",
2362 [(set VR128:$dst, (v4f32 (vector_shuffle
2363 (memopv4f32 addr:$src), (undef),
2364 MOVSHDUP_shuffle_mask)))]>;
2366 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2367 "movsldup\t{$src, $dst|$dst, $src}",
2368 [(set VR128:$dst, (v4f32 (vector_shuffle
2369 VR128:$src, (undef),
2370 MOVSLDUP_shuffle_mask)))]>;
2371 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2372 "movsldup\t{$src, $dst|$dst, $src}",
2373 [(set VR128:$dst, (v4f32 (vector_shuffle
2374 (memopv4f32 addr:$src), (undef),
2375 MOVSLDUP_shuffle_mask)))]>;
2377 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2378 "movddup\t{$src, $dst|$dst, $src}",
2379 [(set VR128:$dst, (v2f64 (vector_shuffle
2380 VR128:$src, (undef),
2381 SSE_splat_lo_mask)))]>;
2382 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2383 "movddup\t{$src, $dst|$dst, $src}",
2385 (v2f64 (vector_shuffle
2386 (scalar_to_vector (loadf64 addr:$src)),
2388 SSE_splat_lo_mask)))]>;
2391 let Constraints = "$src1 = $dst" in {
2392 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2393 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2394 "addsubps\t{$src2, $dst|$dst, $src2}",
2395 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2397 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2398 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2399 "addsubps\t{$src2, $dst|$dst, $src2}",
2400 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2401 (load addr:$src2)))]>;
2402 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2403 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2404 "addsubpd\t{$src2, $dst|$dst, $src2}",
2405 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2407 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2408 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2409 "addsubpd\t{$src2, $dst|$dst, $src2}",
2410 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2411 (load addr:$src2)))]>;
2414 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2415 "lddqu\t{$src, $dst|$dst, $src}",
2416 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2419 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2420 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2421 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2422 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2423 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2424 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2425 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2426 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
2427 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2428 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2429 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2430 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2431 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2432 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2433 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2434 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
2436 let Constraints = "$src1 = $dst" in {
2437 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2438 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2439 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2440 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2441 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2442 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2443 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2444 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2447 // Thread synchronization
2448 def MONITOR : I<0xC8, RawFrm, (outs), (ins), "monitor",
2449 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2450 def MWAIT : I<0xC9, RawFrm, (outs), (ins), "mwait",
2451 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2453 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2454 let AddedComplexity = 15 in
2455 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2456 MOVSHDUP_shuffle_mask)),
2457 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2458 let AddedComplexity = 20 in
2459 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2460 MOVSHDUP_shuffle_mask)),
2461 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2463 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2464 let AddedComplexity = 15 in
2465 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2466 MOVSLDUP_shuffle_mask)),
2467 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2468 let AddedComplexity = 20 in
2469 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2470 MOVSLDUP_shuffle_mask)),
2471 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2473 //===----------------------------------------------------------------------===//
2474 // SSSE3 Instructions
2475 //===----------------------------------------------------------------------===//
2477 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2478 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2479 Intrinsic IntId64, Intrinsic IntId128> {
2480 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2481 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2482 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2484 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2485 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2487 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2489 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2491 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2492 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2495 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2497 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2500 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2503 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2504 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2505 Intrinsic IntId64, Intrinsic IntId128> {
2506 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2508 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2509 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2511 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2513 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2516 (bitconvert (memopv4i16 addr:$src))))]>;
2518 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2520 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2521 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2524 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2526 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2529 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2532 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2533 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2534 Intrinsic IntId64, Intrinsic IntId128> {
2535 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2537 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2538 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2540 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2542 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2545 (bitconvert (memopv2i32 addr:$src))))]>;
2547 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2549 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2550 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2553 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2555 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2558 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2561 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2562 int_x86_ssse3_pabs_b,
2563 int_x86_ssse3_pabs_b_128>;
2564 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2565 int_x86_ssse3_pabs_w,
2566 int_x86_ssse3_pabs_w_128>;
2567 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2568 int_x86_ssse3_pabs_d,
2569 int_x86_ssse3_pabs_d_128>;
2571 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2572 let Constraints = "$src1 = $dst" in {
2573 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2574 Intrinsic IntId64, Intrinsic IntId128,
2575 bit Commutable = 0> {
2576 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2577 (ins VR64:$src1, VR64:$src2),
2578 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2579 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2580 let isCommutable = Commutable;
2582 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2583 (ins VR64:$src1, i64mem:$src2),
2584 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2586 (IntId64 VR64:$src1,
2587 (bitconvert (memopv8i8 addr:$src2))))]>;
2589 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2590 (ins VR128:$src1, VR128:$src2),
2591 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2592 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2594 let isCommutable = Commutable;
2596 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2597 (ins VR128:$src1, i128mem:$src2),
2598 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2600 (IntId128 VR128:$src1,
2601 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2605 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2606 let Constraints = "$src1 = $dst" in {
2607 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2608 Intrinsic IntId64, Intrinsic IntId128,
2609 bit Commutable = 0> {
2610 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2611 (ins VR64:$src1, VR64:$src2),
2612 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2613 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2614 let isCommutable = Commutable;
2616 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2617 (ins VR64:$src1, i64mem:$src2),
2618 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2620 (IntId64 VR64:$src1,
2621 (bitconvert (memopv4i16 addr:$src2))))]>;
2623 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2624 (ins VR128:$src1, VR128:$src2),
2625 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2626 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2628 let isCommutable = Commutable;
2630 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2631 (ins VR128:$src1, i128mem:$src2),
2632 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2634 (IntId128 VR128:$src1,
2635 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2639 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2640 let Constraints = "$src1 = $dst" in {
2641 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2642 Intrinsic IntId64, Intrinsic IntId128,
2643 bit Commutable = 0> {
2644 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2645 (ins VR64:$src1, VR64:$src2),
2646 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2647 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2648 let isCommutable = Commutable;
2650 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2651 (ins VR64:$src1, i64mem:$src2),
2652 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2654 (IntId64 VR64:$src1,
2655 (bitconvert (memopv2i32 addr:$src2))))]>;
2657 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2658 (ins VR128:$src1, VR128:$src2),
2659 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2660 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2662 let isCommutable = Commutable;
2664 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2665 (ins VR128:$src1, i128mem:$src2),
2666 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2668 (IntId128 VR128:$src1,
2669 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2673 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2674 int_x86_ssse3_phadd_w,
2675 int_x86_ssse3_phadd_w_128, 1>;
2676 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2677 int_x86_ssse3_phadd_d,
2678 int_x86_ssse3_phadd_d_128, 1>;
2679 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2680 int_x86_ssse3_phadd_sw,
2681 int_x86_ssse3_phadd_sw_128, 1>;
2682 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2683 int_x86_ssse3_phsub_w,
2684 int_x86_ssse3_phsub_w_128>;
2685 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2686 int_x86_ssse3_phsub_d,
2687 int_x86_ssse3_phsub_d_128>;
2688 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2689 int_x86_ssse3_phsub_sw,
2690 int_x86_ssse3_phsub_sw_128>;
2691 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2692 int_x86_ssse3_pmadd_ub_sw,
2693 int_x86_ssse3_pmadd_ub_sw_128, 1>;
2694 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2695 int_x86_ssse3_pmul_hr_sw,
2696 int_x86_ssse3_pmul_hr_sw_128, 1>;
2697 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2698 int_x86_ssse3_pshuf_b,
2699 int_x86_ssse3_pshuf_b_128>;
2700 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2701 int_x86_ssse3_psign_b,
2702 int_x86_ssse3_psign_b_128>;
2703 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2704 int_x86_ssse3_psign_w,
2705 int_x86_ssse3_psign_w_128>;
2706 defm PSIGND : SS3I_binop_rm_int_32<0x09, "psignd",
2707 int_x86_ssse3_psign_d,
2708 int_x86_ssse3_psign_d_128>;
2710 let Constraints = "$src1 = $dst" in {
2711 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2712 (ins VR64:$src1, VR64:$src2, i16imm:$src3),
2713 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2715 (int_x86_ssse3_palign_r
2716 VR64:$src1, VR64:$src2,
2718 def PALIGNR64rm : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2719 (ins VR64:$src1, i64mem:$src2, i16imm:$src3),
2720 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2722 (int_x86_ssse3_palign_r
2724 (bitconvert (memopv2i32 addr:$src2)),
2727 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2728 (ins VR128:$src1, VR128:$src2, i32imm:$src3),
2729 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2731 (int_x86_ssse3_palign_r_128
2732 VR128:$src1, VR128:$src2,
2733 imm:$src3))]>, OpSize;
2734 def PALIGNR128rm : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2735 (ins VR128:$src1, i128mem:$src2, i32imm:$src3),
2736 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2738 (int_x86_ssse3_palign_r_128
2740 (bitconvert (memopv4i32 addr:$src2)),
2741 imm:$src3))]>, OpSize;
2744 //===----------------------------------------------------------------------===//
2745 // Non-Instruction Patterns
2746 //===----------------------------------------------------------------------===//
2748 // extload f32 -> f64. This matches load+fextend because we have a hack in
2749 // the isel (PreprocessForFPConvert) that can introduce loads after dag combine.
2750 // Since these loads aren't folded into the fextend, we have to match it
2752 let Predicates = [HasSSE2] in
2753 def : Pat<(fextend (loadf32 addr:$src)),
2754 (CVTSS2SDrm addr:$src)>;
2757 let Predicates = [HasSSE2] in {
2758 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2759 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2760 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2761 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2762 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2763 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2764 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2765 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2766 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2767 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2768 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2769 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2770 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2771 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2772 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2773 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2774 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2775 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2776 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2777 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2778 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2779 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2780 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2781 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2782 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2783 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2784 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2785 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2786 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2787 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2790 // Move scalar to XMM zero-extended
2791 // movd to XMM register zero-extends
2792 let AddedComplexity = 15 in {
2793 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2794 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
2795 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2796 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
2797 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
2798 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
2799 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE2]>;
2802 // Splat v2f64 / v2i64
2803 let AddedComplexity = 10 in {
2804 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2805 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2806 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2807 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2808 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2809 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2810 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2811 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2814 // Special unary SHUFPSrri case.
2815 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2816 SHUFP_unary_shuffle_mask:$sm)),
2817 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2818 Requires<[HasSSE1]>;
2819 // Special unary SHUFPDrri case.
2820 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (undef),
2821 SHUFP_unary_shuffle_mask:$sm)),
2822 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2823 Requires<[HasSSE2]>;
2824 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2825 def : Pat<(vector_shuffle (bc_v4i32 (memopv4f32 addr:$src1)), (undef),
2826 SHUFP_unary_shuffle_mask:$sm),
2827 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2828 Requires<[HasSSE2]>;
2829 // Special binary v4i32 shuffle cases with SHUFPS.
2830 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (v4i32 VR128:$src2),
2831 PSHUFD_binary_shuffle_mask:$sm)),
2832 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2833 Requires<[HasSSE2]>;
2834 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
2835 (bc_v4i32 (memopv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm)),
2836 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2837 Requires<[HasSSE2]>;
2838 // Special binary v2i64 shuffle cases using SHUFPDrri.
2839 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2840 SHUFP_shuffle_mask:$sm)),
2841 (SHUFPDrri VR128:$src1, VR128:$src2, SHUFP_shuffle_mask:$sm)>,
2842 Requires<[HasSSE2]>;
2843 // Special unary SHUFPDrri case.
2844 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (undef),
2845 SHUFP_unary_shuffle_mask:$sm)),
2846 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2847 Requires<[HasSSE2]>;
2849 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2850 let AddedComplexity = 10 in {
2851 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2852 UNPCKL_v_undef_shuffle_mask)),
2853 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2854 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2855 UNPCKL_v_undef_shuffle_mask)),
2856 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2857 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2858 UNPCKL_v_undef_shuffle_mask)),
2859 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2860 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2861 UNPCKL_v_undef_shuffle_mask)),
2862 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2865 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2866 let AddedComplexity = 10 in {
2867 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2868 UNPCKH_v_undef_shuffle_mask)),
2869 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2870 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2871 UNPCKH_v_undef_shuffle_mask)),
2872 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2873 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2874 UNPCKH_v_undef_shuffle_mask)),
2875 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2876 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2877 UNPCKH_v_undef_shuffle_mask)),
2878 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2881 let AddedComplexity = 15 in {
2882 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2883 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2884 MOVHP_shuffle_mask)),
2885 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2887 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2888 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2889 MOVHLPS_shuffle_mask)),
2890 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
2892 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
2893 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2894 MOVHLPS_v_undef_shuffle_mask)),
2895 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2896 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
2897 MOVHLPS_v_undef_shuffle_mask)),
2898 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2901 let AddedComplexity = 20 in {
2902 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2903 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
2904 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memopv4f32 addr:$src2),
2905 MOVLP_shuffle_mask)),
2906 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2907 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memopv2f64 addr:$src2),
2908 MOVLP_shuffle_mask)),
2909 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2910 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memopv4f32 addr:$src2),
2911 MOVHP_shuffle_mask)),
2912 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2913 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memopv2f64 addr:$src2),
2914 MOVHP_shuffle_mask)),
2915 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2917 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)),
2918 MOVLP_shuffle_mask)),
2919 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2920 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memopv2i64 addr:$src2),
2921 MOVLP_shuffle_mask)),
2922 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2923 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)),
2924 MOVHP_shuffle_mask)),
2925 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2926 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memopv2i64 addr:$src2),
2927 MOVLP_shuffle_mask)),
2928 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2931 let AddedComplexity = 15 in {
2932 // Setting the lowest element in the vector.
2933 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2934 MOVL_shuffle_mask)),
2935 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2936 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2937 MOVL_shuffle_mask)),
2938 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2940 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
2941 def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
2942 MOVLP_shuffle_mask)),
2943 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2944 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2945 MOVLP_shuffle_mask)),
2946 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2949 // Set lowest element and zero upper elements.
2950 let AddedComplexity = 15 in
2951 def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc, VR128:$src,
2952 MOVL_shuffle_mask)),
2953 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
2954 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
2955 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
2957 // FIXME: Temporary workaround since 2-wide shuffle is broken.
2958 def : Pat<(int_x86_sse2_movs_d VR128:$src1, VR128:$src2),
2959 (v2f64 (MOVLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2960 def : Pat<(int_x86_sse2_loadh_pd VR128:$src1, addr:$src2),
2961 (v2f64 (MOVHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2962 def : Pat<(int_x86_sse2_loadl_pd VR128:$src1, addr:$src2),
2963 (v2f64 (MOVLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2964 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, VR128:$src2, imm:$src3),
2965 (v2f64 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$src3))>,
2966 Requires<[HasSSE2]>;
2967 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, (load addr:$src2), imm:$src3),
2968 (v2f64 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$src3))>,
2969 Requires<[HasSSE2]>;
2970 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, VR128:$src2),
2971 (v2f64 (UNPCKHPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2972 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, (load addr:$src2)),
2973 (v2f64 (UNPCKHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2974 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, VR128:$src2),
2975 (v2f64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2976 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, (load addr:$src2)),
2977 (v2f64 (UNPCKLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2978 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, VR128:$src2),
2979 (v2i64 (PUNPCKHQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2980 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, (load addr:$src2)),
2981 (v2i64 (PUNPCKHQDQrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2982 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, VR128:$src2),
2983 (v2i64 (PUNPCKLQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2984 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, (load addr:$src2)),
2985 (PUNPCKLQDQrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2987 // Some special case pandn patterns.
2988 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2990 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2991 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2993 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2994 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2996 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2998 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2999 (memopv2i64 addr:$src2))),
3000 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3001 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3002 (memopv2i64 addr:$src2))),
3003 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3004 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3005 (memopv2i64 addr:$src2))),
3006 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3008 // vector -> vector casts
3009 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3010 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3011 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3012 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3014 // Use movaps / movups for SSE integer load / store (one byte shorter).
3015 def : Pat<(alignedloadv4i32 addr:$src),
3016 (MOVAPSrm addr:$src)>, Requires<[HasSSE1]>;
3017 def : Pat<(loadv4i32 addr:$src),
3018 (MOVUPSrm addr:$src)>, Requires<[HasSSE1]>;
3019 def : Pat<(alignedloadv2i64 addr:$src),
3020 (MOVAPSrm addr:$src)>, Requires<[HasSSE2]>;
3021 def : Pat<(loadv2i64 addr:$src),
3022 (MOVUPSrm addr:$src)>, Requires<[HasSSE2]>;
3024 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3025 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3026 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3027 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3028 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3029 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3030 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3031 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3032 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3033 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3034 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3035 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3036 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3037 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3038 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3039 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3041 //===----------------------------------------------------------------------===//
3042 // SSE4.1 Instructions
3043 //===----------------------------------------------------------------------===//
3045 multiclass sse41_fp_unop_rm<bits<8> opcss, bits<8> opcps,
3046 bits<8> opcsd, bits<8> opcpd,
3051 Intrinsic V2F64Int> {
3052 // Intrinsic operation, reg.
3053 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3054 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3055 !strconcat(OpcodeStr,
3056 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3057 [(set VR128:$dst, (F32Int VR128:$src1, imm:$src2))]>,
3060 // Intrinsic operation, mem.
3061 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3062 (outs VR128:$dst), (ins ssmem:$src1, i32i8imm:$src2),
3063 !strconcat(OpcodeStr,
3064 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3065 [(set VR128:$dst, (F32Int sse_load_f32:$src1, imm:$src2))]>,
3068 // Vector intrinsic operation, reg
3069 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3070 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3071 !strconcat(OpcodeStr,
3072 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3073 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3076 // Vector intrinsic operation, mem
3077 def PSm_Int : SS4AIi8<opcps, MRMSrcMem,
3078 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3079 !strconcat(OpcodeStr,
3080 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3081 [(set VR128:$dst, (V4F32Int (load addr:$src1),imm:$src2))]>,
3084 // Intrinsic operation, reg.
3085 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3086 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3087 !strconcat(OpcodeStr,
3088 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3089 [(set VR128:$dst, (F64Int VR128:$src1, imm:$src2))]>,
3092 // Intrinsic operation, mem.
3093 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3094 (outs VR128:$dst), (ins sdmem:$src1, i32i8imm:$src2),
3095 !strconcat(OpcodeStr,
3096 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3097 [(set VR128:$dst, (F64Int sse_load_f64:$src1, imm:$src2))]>,
3100 // Vector intrinsic operation, reg
3101 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3102 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3103 !strconcat(OpcodeStr,
3104 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3105 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3108 // Vector intrinsic operation, mem
3109 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3110 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3111 !strconcat(OpcodeStr,
3112 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3113 [(set VR128:$dst, (V2F64Int (load addr:$src1),imm:$src2))]>,
3117 // FP round - roundss, roundps, roundsd, roundpd
3118 defm ROUND : sse41_fp_unop_rm<0x0A, 0x08, 0x0B, 0x09, "round",
3119 int_x86_sse41_round_ss, int_x86_sse41_round_ps,
3120 int_x86_sse41_round_sd, int_x86_sse41_round_pd>;
3122 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3123 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3124 Intrinsic IntId128> {
3125 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3127 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3128 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3129 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3131 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3134 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3137 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3138 int_x86_sse41_phminposuw>;
3140 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3141 let Constraints = "$src1 = $dst" in {
3142 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3143 Intrinsic IntId128, bit Commutable = 0> {
3144 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3145 (ins VR128:$src1, VR128:$src2),
3146 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3147 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3149 let isCommutable = Commutable;
3151 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3152 (ins VR128:$src1, i128mem:$src2),
3153 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3155 (IntId128 VR128:$src1,
3156 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3160 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3161 int_x86_sse41_pcmpeqq, 1>;
3162 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3163 int_x86_sse41_packusdw, 0>;
3164 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3165 int_x86_sse41_pminsb, 1>;
3166 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3167 int_x86_sse41_pminsd, 1>;
3168 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3169 int_x86_sse41_pminud, 1>;
3170 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3171 int_x86_sse41_pminuw, 1>;
3172 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3173 int_x86_sse41_pmaxsb, 1>;
3174 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3175 int_x86_sse41_pmaxsd, 1>;
3176 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3177 int_x86_sse41_pmaxud, 1>;
3178 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3179 int_x86_sse41_pmaxuw, 1>;
3180 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq",
3181 int_x86_sse41_pmuldq, 1>;
3184 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3185 let Constraints = "$src1 = $dst" in {
3186 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, SDNode OpNode,
3187 Intrinsic IntId128, bit Commutable = 0> {
3188 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3189 (ins VR128:$src1, VR128:$src2),
3190 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3191 [(set VR128:$dst, (OpNode (v4i32 VR128:$src1),
3192 VR128:$src2))]>, OpSize {
3193 let isCommutable = Commutable;
3195 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3196 (ins VR128:$src1, VR128:$src2),
3197 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3198 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3200 let isCommutable = Commutable;
3202 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3203 (ins VR128:$src1, i128mem:$src2),
3204 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3206 (OpNode VR128:$src1, (memopv4i32 addr:$src2)))]>, OpSize;
3207 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3208 (ins VR128:$src1, i128mem:$src2),
3209 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3211 (IntId128 VR128:$src1, (memopv4i32 addr:$src2)))]>,
3215 defm PMULLD : SS41I_binop_patint<0x40, "pmulld", mul,
3216 int_x86_sse41_pmulld, 1>;
3219 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3220 let Constraints = "$src1 = $dst" in {
3221 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3222 Intrinsic IntId128, bit Commutable = 0> {
3223 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3224 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3225 !strconcat(OpcodeStr,
3226 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3228 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3230 let isCommutable = Commutable;
3232 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3233 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3234 !strconcat(OpcodeStr,
3235 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3237 (IntId128 VR128:$src1,
3238 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3243 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3244 int_x86_sse41_blendps, 0>;
3245 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3246 int_x86_sse41_blendpd, 0>;
3247 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3248 int_x86_sse41_pblendw, 0>;
3249 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3250 int_x86_sse41_dpps, 1>;
3251 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3252 int_x86_sse41_dppd, 1>;
3253 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3254 int_x86_sse41_mpsadbw, 0>;
3257 /// SS41I_ternary_int - SSE 4.1 ternary operator
3258 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3259 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3260 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3261 (ins VR128:$src1, VR128:$src2),
3262 !strconcat(OpcodeStr,
3263 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3264 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3267 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3268 (ins VR128:$src1, i128mem:$src2),
3269 !strconcat(OpcodeStr,
3270 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3273 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3277 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3278 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3279 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3282 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3283 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3284 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3285 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3287 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3288 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3290 (IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
3293 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3294 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3295 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3296 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3297 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3298 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3300 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3301 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3302 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3303 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3305 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3306 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3308 (IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
3311 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3312 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3313 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3314 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3316 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3317 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3318 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3319 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3321 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3322 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3324 (IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
3327 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3328 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovsxbq", int_x86_sse41_pmovzxbq>;
3331 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3332 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3333 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3334 (ins VR128:$src1, i32i8imm:$src2),
3335 !strconcat(OpcodeStr,
3336 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3337 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3339 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3340 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3341 !strconcat(OpcodeStr,
3342 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3345 // There's an AssertZext in the way of writing the store pattern
3346 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3349 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3352 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3353 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3354 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3355 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3356 !strconcat(OpcodeStr,
3357 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3360 // There's an AssertZext in the way of writing the store pattern
3361 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3364 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3367 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3368 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3369 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3370 (ins VR128:$src1, i32i8imm:$src2),
3371 !strconcat(OpcodeStr,
3372 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3374 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3375 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3376 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3377 !strconcat(OpcodeStr,
3378 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3379 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3380 addr:$dst)]>, OpSize;
3383 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3386 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3388 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3389 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3390 (ins VR128:$src1, i32i8imm:$src2),
3391 !strconcat(OpcodeStr,
3392 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3394 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3396 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3397 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3398 !strconcat(OpcodeStr,
3399 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3400 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3401 addr:$dst)]>, OpSize;
3404 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3406 let Constraints = "$src1 = $dst" in {
3407 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3408 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3409 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3410 !strconcat(OpcodeStr,
3411 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3413 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3414 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3415 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3416 !strconcat(OpcodeStr,
3417 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3419 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3420 imm:$src3))]>, OpSize;
3424 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3426 let Constraints = "$src1 = $dst" in {
3427 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3428 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3429 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3430 !strconcat(OpcodeStr,
3431 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3433 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3435 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3436 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3437 !strconcat(OpcodeStr,
3438 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3440 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3441 imm:$src3)))]>, OpSize;
3445 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3447 let Constraints = "$src1 = $dst" in {
3448 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3449 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3450 (ins VR128:$src1, FR32:$src2, i32i8imm:$src3),
3451 !strconcat(OpcodeStr,
3452 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3454 (X86insrtps VR128:$src1, FR32:$src2, imm:$src3))]>, OpSize;
3455 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3456 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3457 !strconcat(OpcodeStr,
3458 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3460 (X86insrtps VR128:$src1, (loadf32 addr:$src2),
3461 imm:$src3))]>, OpSize;
3465 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3467 let Defs = [EFLAGS] in {
3468 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3469 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3470 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3471 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3474 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3475 "movntdqa\t{$src, $dst|$dst, $src}",
3476 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;