1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pextrb : SDNode<"X86ISD::PEXTRB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
41 def X86pextrw : SDNode<"X86ISD::PEXTRW",
42 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
43 def X86pinsrb : SDNode<"X86ISD::PINSRB",
44 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
45 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
46 def X86pinsrw : SDNode<"X86ISD::PINSRW",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86insrtps : SDNode<"X86ISD::INSERTPS",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, f32>, SDTCisPtrTy<3>]>>;
52 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
53 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
54 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
55 [SDNPHasChain, SDNPMayLoad]>;
56 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
57 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
58 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
59 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
60 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
61 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
62 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
63 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
65 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
66 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
67 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
69 //===----------------------------------------------------------------------===//
70 // SSE Complex Patterns
71 //===----------------------------------------------------------------------===//
73 // These are 'extloads' from a scalar to the low element of a vector, zeroing
74 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
76 def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
77 [SDNPHasChain, SDNPMayLoad]>;
78 def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
79 [SDNPHasChain, SDNPMayLoad]>;
81 def ssmem : Operand<v4f32> {
82 let PrintMethod = "printf32mem";
83 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
85 def sdmem : Operand<v2f64> {
86 let PrintMethod = "printf64mem";
87 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
90 //===----------------------------------------------------------------------===//
91 // SSE pattern fragments
92 //===----------------------------------------------------------------------===//
94 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
95 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
96 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
97 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
99 // Like 'store', but always requires vector alignment.
100 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
101 (store node:$val, node:$ptr), [{
102 return cast<StoreSDNode>(N)->getAlignment() >= 16;
105 // Like 'load', but always requires vector alignment.
106 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
107 return cast<LoadSDNode>(N)->getAlignment() >= 16;
110 def alignedloadfsf32 : PatFrag<(ops node:$ptr), (f32 (alignedload node:$ptr))>;
111 def alignedloadfsf64 : PatFrag<(ops node:$ptr), (f64 (alignedload node:$ptr))>;
112 def alignedloadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (alignedload node:$ptr))>;
113 def alignedloadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (alignedload node:$ptr))>;
114 def alignedloadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (alignedload node:$ptr))>;
115 def alignedloadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (alignedload node:$ptr))>;
117 // Like 'load', but uses special alignment checks suitable for use in
118 // memory operands in most SSE instructions, which are required to
119 // be naturally aligned on some targets but not on others.
120 // FIXME: Actually implement support for targets that don't require the
121 // alignment. This probably wants a subtarget predicate.
122 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
123 return cast<LoadSDNode>(N)->getAlignment() >= 16;
126 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
127 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
128 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
129 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
130 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
131 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
132 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
134 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
136 // FIXME: 8 byte alignment for mmx reads is not required
137 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
138 return cast<LoadSDNode>(N)->getAlignment() >= 8;
141 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
142 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
143 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
144 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
146 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
147 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
148 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
149 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
150 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
151 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
153 def vzmovl_v2i64 : PatFrag<(ops node:$src),
154 (bitconvert (v2i64 (X86vzmovl
155 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
156 def vzmovl_v4i32 : PatFrag<(ops node:$src),
157 (bitconvert (v4i32 (X86vzmovl
158 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
160 def vzload_v2i64 : PatFrag<(ops node:$src),
161 (bitconvert (v2i64 (X86vzload node:$src)))>;
164 def fp32imm0 : PatLeaf<(f32 fpimm), [{
165 return N->isExactlyValue(+0.0);
168 def PSxLDQ_imm : SDNodeXForm<imm, [{
169 // Transformation function: imm >> 3
170 return getI32Imm(N->getZExtValue() >> 3);
173 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
175 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
176 return getI8Imm(X86::getShuffleSHUFImmediate(N));
179 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
181 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
182 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
185 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
187 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
188 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
191 def SSE_splat_mask : PatLeaf<(build_vector), [{
192 return X86::isSplatMask(N);
193 }], SHUFFLE_get_shuf_imm>;
195 def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
196 return X86::isSplatLoMask(N);
199 def MOVDDUP_shuffle_mask : PatLeaf<(build_vector), [{
200 return X86::isMOVDDUPMask(N);
203 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
204 return X86::isMOVHLPSMask(N);
207 def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
208 return X86::isMOVHLPS_v_undef_Mask(N);
211 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
212 return X86::isMOVHPMask(N);
215 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
216 return X86::isMOVLPMask(N);
219 def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
220 return X86::isMOVLMask(N);
223 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
224 return X86::isMOVSHDUPMask(N);
227 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
228 return X86::isMOVSLDUPMask(N);
231 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
232 return X86::isUNPCKLMask(N);
235 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
236 return X86::isUNPCKHMask(N);
239 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
240 return X86::isUNPCKL_v_undef_Mask(N);
243 def UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
244 return X86::isUNPCKH_v_undef_Mask(N);
247 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
248 return X86::isPSHUFDMask(N);
249 }], SHUFFLE_get_shuf_imm>;
251 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
252 return X86::isPSHUFHWMask(N);
253 }], SHUFFLE_get_pshufhw_imm>;
255 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
256 return X86::isPSHUFLWMask(N);
257 }], SHUFFLE_get_pshuflw_imm>;
259 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
260 return X86::isPSHUFDMask(N);
261 }], SHUFFLE_get_shuf_imm>;
263 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
264 return X86::isSHUFPMask(N);
265 }], SHUFFLE_get_shuf_imm>;
267 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
268 return X86::isSHUFPMask(N);
269 }], SHUFFLE_get_shuf_imm>;
272 //===----------------------------------------------------------------------===//
273 // SSE scalar FP Instructions
274 //===----------------------------------------------------------------------===//
276 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
277 // scheduler into a branch sequence.
278 // These are expanded by the scheduler.
279 let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
280 def CMOV_FR32 : I<0, Pseudo,
281 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
282 "#CMOV_FR32 PSEUDO!",
283 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
285 def CMOV_FR64 : I<0, Pseudo,
286 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
287 "#CMOV_FR64 PSEUDO!",
288 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
290 def CMOV_V4F32 : I<0, Pseudo,
291 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
292 "#CMOV_V4F32 PSEUDO!",
294 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
296 def CMOV_V2F64 : I<0, Pseudo,
297 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
298 "#CMOV_V2F64 PSEUDO!",
300 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
302 def CMOV_V2I64 : I<0, Pseudo,
303 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
304 "#CMOV_V2I64 PSEUDO!",
306 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
310 //===----------------------------------------------------------------------===//
312 //===----------------------------------------------------------------------===//
315 let neverHasSideEffects = 1 in
316 def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
317 "movss\t{$src, $dst|$dst, $src}", []>;
318 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
319 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
320 "movss\t{$src, $dst|$dst, $src}",
321 [(set FR32:$dst, (loadf32 addr:$src))]>;
322 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
323 "movss\t{$src, $dst|$dst, $src}",
324 [(store FR32:$src, addr:$dst)]>;
326 // Conversion instructions
327 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
328 "cvttss2si\t{$src, $dst|$dst, $src}",
329 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
330 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
331 "cvttss2si\t{$src, $dst|$dst, $src}",
332 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
333 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
334 "cvtsi2ss\t{$src, $dst|$dst, $src}",
335 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
336 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
337 "cvtsi2ss\t{$src, $dst|$dst, $src}",
338 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
340 // Match intrinsics which expect XMM operand(s).
341 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
342 "cvtss2si\t{$src, $dst|$dst, $src}",
343 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
344 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
345 "cvtss2si\t{$src, $dst|$dst, $src}",
346 [(set GR32:$dst, (int_x86_sse_cvtss2si
347 (load addr:$src)))]>;
349 // Match intrinisics which expect MM and XMM operand(s).
350 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
351 "cvtps2pi\t{$src, $dst|$dst, $src}",
352 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
353 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
354 "cvtps2pi\t{$src, $dst|$dst, $src}",
355 [(set VR64:$dst, (int_x86_sse_cvtps2pi
356 (load addr:$src)))]>;
357 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
358 "cvttps2pi\t{$src, $dst|$dst, $src}",
359 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
360 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
361 "cvttps2pi\t{$src, $dst|$dst, $src}",
362 [(set VR64:$dst, (int_x86_sse_cvttps2pi
363 (load addr:$src)))]>;
364 let Constraints = "$src1 = $dst" in {
365 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
366 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
367 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
368 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
370 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
371 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
372 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
373 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
374 (load addr:$src2)))]>;
377 // Aliases for intrinsics
378 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
379 "cvttss2si\t{$src, $dst|$dst, $src}",
381 (int_x86_sse_cvttss2si VR128:$src))]>;
382 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
383 "cvttss2si\t{$src, $dst|$dst, $src}",
385 (int_x86_sse_cvttss2si(load addr:$src)))]>;
387 let Constraints = "$src1 = $dst" in {
388 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
389 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
390 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
391 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
393 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
394 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
395 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
396 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
397 (loadi32 addr:$src2)))]>;
400 // Comparison instructions
401 let Constraints = "$src1 = $dst" in {
402 let neverHasSideEffects = 1 in
403 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
404 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
405 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
406 let neverHasSideEffects = 1, mayLoad = 1 in
407 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
408 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
409 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
412 let Defs = [EFLAGS] in {
413 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
414 "ucomiss\t{$src2, $src1|$src1, $src2}",
415 [(X86cmp FR32:$src1, FR32:$src2), (implicit EFLAGS)]>;
416 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
417 "ucomiss\t{$src2, $src1|$src1, $src2}",
418 [(X86cmp FR32:$src1, (loadf32 addr:$src2)),
422 // Aliases to match intrinsics which expect XMM operand(s).
423 let Constraints = "$src1 = $dst" in {
424 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
425 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
426 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
427 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
428 VR128:$src, imm:$cc))]>;
429 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
430 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src, SSECC:$cc),
431 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
432 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
433 (load addr:$src), imm:$cc))]>;
436 let Defs = [EFLAGS] in {
437 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs),
438 (ins VR128:$src1, VR128:$src2),
439 "ucomiss\t{$src2, $src1|$src1, $src2}",
440 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2),
442 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),
443 (ins VR128:$src1, f128mem:$src2),
444 "ucomiss\t{$src2, $src1|$src1, $src2}",
445 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2)),
448 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs),
449 (ins VR128:$src1, VR128:$src2),
450 "comiss\t{$src2, $src1|$src1, $src2}",
451 [(X86comi (v4f32 VR128:$src1), VR128:$src2),
453 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs),
454 (ins VR128:$src1, f128mem:$src2),
455 "comiss\t{$src2, $src1|$src1, $src2}",
456 [(X86comi (v4f32 VR128:$src1), (load addr:$src2)),
460 // Aliases of packed SSE1 instructions for scalar use. These all have names that
463 // Alias instructions that map fld0 to pxor for sse.
464 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
465 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
466 "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
467 Requires<[HasSSE1]>, TB, OpSize;
469 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
471 let neverHasSideEffects = 1 in
472 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
473 "movaps\t{$src, $dst|$dst, $src}", []>;
475 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
477 let isSimpleLoad = 1 in
478 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
479 "movaps\t{$src, $dst|$dst, $src}",
480 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
482 // Alias bitwise logical operations using SSE logical ops on packed FP values.
483 let Constraints = "$src1 = $dst" in {
484 let isCommutable = 1 in {
485 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
486 "andps\t{$src2, $dst|$dst, $src2}",
487 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
488 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
489 "orps\t{$src2, $dst|$dst, $src2}",
490 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
491 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
492 "xorps\t{$src2, $dst|$dst, $src2}",
493 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
496 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
497 "andps\t{$src2, $dst|$dst, $src2}",
498 [(set FR32:$dst, (X86fand FR32:$src1,
499 (memopfsf32 addr:$src2)))]>;
500 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
501 "orps\t{$src2, $dst|$dst, $src2}",
502 [(set FR32:$dst, (X86for FR32:$src1,
503 (memopfsf32 addr:$src2)))]>;
504 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
505 "xorps\t{$src2, $dst|$dst, $src2}",
506 [(set FR32:$dst, (X86fxor FR32:$src1,
507 (memopfsf32 addr:$src2)))]>;
508 let neverHasSideEffects = 1 in {
509 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
510 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
511 "andnps\t{$src2, $dst|$dst, $src2}", []>;
514 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
515 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
516 "andnps\t{$src2, $dst|$dst, $src2}", []>;
520 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
522 /// In addition, we also have a special variant of the scalar form here to
523 /// represent the associated intrinsic operation. This form is unlike the
524 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
525 /// and leaves the top elements undefined.
527 /// These three forms can each be reg+reg or reg+mem, so there are a total of
528 /// six "instructions".
530 let Constraints = "$src1 = $dst" in {
531 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
532 SDNode OpNode, Intrinsic F32Int,
533 bit Commutable = 0> {
534 // Scalar operation, reg+reg.
535 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
536 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
537 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
538 let isCommutable = Commutable;
541 // Scalar operation, reg+mem.
542 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
543 (ins FR32:$src1, f32mem:$src2),
544 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
545 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
547 // Vector operation, reg+reg.
548 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
549 (ins VR128:$src1, VR128:$src2),
550 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
551 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
552 let isCommutable = Commutable;
555 // Vector operation, reg+mem.
556 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
557 (ins VR128:$src1, f128mem:$src2),
558 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
559 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
561 // Intrinsic operation, reg+reg.
562 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
563 (ins VR128:$src1, VR128:$src2),
564 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
565 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
566 let isCommutable = Commutable;
569 // Intrinsic operation, reg+mem.
570 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
571 (ins VR128:$src1, ssmem:$src2),
572 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
573 [(set VR128:$dst, (F32Int VR128:$src1,
574 sse_load_f32:$src2))]>;
578 // Arithmetic instructions
579 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
580 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
581 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
582 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
584 /// sse1_fp_binop_rm - Other SSE1 binops
586 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
587 /// instructions for a full-vector intrinsic form. Operations that map
588 /// onto C operators don't use this form since they just use the plain
589 /// vector form instead of having a separate vector intrinsic form.
591 /// This provides a total of eight "instructions".
593 let Constraints = "$src1 = $dst" in {
594 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
598 bit Commutable = 0> {
600 // Scalar operation, reg+reg.
601 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
602 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
603 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
604 let isCommutable = Commutable;
607 // Scalar operation, reg+mem.
608 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
609 (ins FR32:$src1, f32mem:$src2),
610 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
611 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
613 // Vector operation, reg+reg.
614 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
615 (ins VR128:$src1, VR128:$src2),
616 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
617 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
618 let isCommutable = Commutable;
621 // Vector operation, reg+mem.
622 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
623 (ins VR128:$src1, f128mem:$src2),
624 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
625 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
627 // Intrinsic operation, reg+reg.
628 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
629 (ins VR128:$src1, VR128:$src2),
630 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
631 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
632 let isCommutable = Commutable;
635 // Intrinsic operation, reg+mem.
636 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
637 (ins VR128:$src1, ssmem:$src2),
638 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
639 [(set VR128:$dst, (F32Int VR128:$src1,
640 sse_load_f32:$src2))]>;
642 // Vector intrinsic operation, reg+reg.
643 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
644 (ins VR128:$src1, VR128:$src2),
645 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
646 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
647 let isCommutable = Commutable;
650 // Vector intrinsic operation, reg+mem.
651 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
652 (ins VR128:$src1, f128mem:$src2),
653 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
654 [(set VR128:$dst, (V4F32Int VR128:$src1, (memopv4f32 addr:$src2)))]>;
658 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
659 int_x86_sse_max_ss, int_x86_sse_max_ps>;
660 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
661 int_x86_sse_min_ss, int_x86_sse_min_ps>;
663 //===----------------------------------------------------------------------===//
664 // SSE packed FP Instructions
667 let neverHasSideEffects = 1 in
668 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
669 "movaps\t{$src, $dst|$dst, $src}", []>;
670 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
671 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
672 "movaps\t{$src, $dst|$dst, $src}",
673 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
675 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
676 "movaps\t{$src, $dst|$dst, $src}",
677 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
679 let neverHasSideEffects = 1 in
680 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
681 "movups\t{$src, $dst|$dst, $src}", []>;
682 let isSimpleLoad = 1 in
683 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
684 "movups\t{$src, $dst|$dst, $src}",
685 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
686 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
687 "movups\t{$src, $dst|$dst, $src}",
688 [(store (v4f32 VR128:$src), addr:$dst)]>;
690 // Intrinsic forms of MOVUPS load and store
691 let isSimpleLoad = 1 in
692 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
693 "movups\t{$src, $dst|$dst, $src}",
694 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
695 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
696 "movups\t{$src, $dst|$dst, $src}",
697 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
699 let Constraints = "$src1 = $dst" in {
700 let AddedComplexity = 20 in {
701 def MOVLPSrm : PSI<0x12, MRMSrcMem,
702 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
703 "movlps\t{$src2, $dst|$dst, $src2}",
705 (v4f32 (vector_shuffle VR128:$src1,
706 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
707 MOVLP_shuffle_mask)))]>;
708 def MOVHPSrm : PSI<0x16, MRMSrcMem,
709 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
710 "movhps\t{$src2, $dst|$dst, $src2}",
712 (v4f32 (vector_shuffle VR128:$src1,
713 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
714 MOVHP_shuffle_mask)))]>;
716 } // Constraints = "$src1 = $dst"
719 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
720 "movlps\t{$src, $dst|$dst, $src}",
721 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
722 (iPTR 0))), addr:$dst)]>;
724 // v2f64 extract element 1 is always custom lowered to unpack high to low
725 // and extract element 0 so the non-store version isn't too horrible.
726 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
727 "movhps\t{$src, $dst|$dst, $src}",
728 [(store (f64 (vector_extract
729 (v2f64 (vector_shuffle
730 (bc_v2f64 (v4f32 VR128:$src)), (undef),
731 UNPCKH_shuffle_mask)), (iPTR 0))),
734 let Constraints = "$src1 = $dst" in {
735 let AddedComplexity = 20 in {
736 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
737 "movlhps\t{$src2, $dst|$dst, $src2}",
739 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
740 MOVHP_shuffle_mask)))]>;
742 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
743 "movhlps\t{$src2, $dst|$dst, $src2}",
745 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
746 MOVHLPS_shuffle_mask)))]>;
748 } // Constraints = "$src1 = $dst"
750 let AddedComplexity = 20 in
751 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef), MOVDDUP_shuffle_mask)),
752 (MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
759 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
761 /// In addition, we also have a special variant of the scalar form here to
762 /// represent the associated intrinsic operation. This form is unlike the
763 /// plain scalar form, in that it takes an entire vector (instead of a
764 /// scalar) and leaves the top elements undefined.
766 /// And, we have a special variant form for a full-vector intrinsic form.
768 /// These four forms can each have a reg or a mem operand, so there are a
769 /// total of eight "instructions".
771 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
775 bit Commutable = 0> {
776 // Scalar operation, reg.
777 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
778 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
779 [(set FR32:$dst, (OpNode FR32:$src))]> {
780 let isCommutable = Commutable;
783 // Scalar operation, mem.
784 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
785 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
786 [(set FR32:$dst, (OpNode (load addr:$src)))]>;
788 // Vector operation, reg.
789 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
790 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
791 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
792 let isCommutable = Commutable;
795 // Vector operation, mem.
796 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
797 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
798 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
800 // Intrinsic operation, reg.
801 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
802 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
803 [(set VR128:$dst, (F32Int VR128:$src))]> {
804 let isCommutable = Commutable;
807 // Intrinsic operation, mem.
808 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
809 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
810 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
812 // Vector intrinsic operation, reg
813 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
814 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
815 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
816 let isCommutable = Commutable;
819 // Vector intrinsic operation, mem
820 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
821 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
822 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
826 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
827 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
829 // Reciprocal approximations. Note that these typically require refinement
830 // in order to obtain suitable precision.
831 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
832 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
833 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
834 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
837 let Constraints = "$src1 = $dst" in {
838 let isCommutable = 1 in {
839 def ANDPSrr : PSI<0x54, MRMSrcReg,
840 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
841 "andps\t{$src2, $dst|$dst, $src2}",
842 [(set VR128:$dst, (v2i64
843 (and VR128:$src1, VR128:$src2)))]>;
844 def ORPSrr : PSI<0x56, MRMSrcReg,
845 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
846 "orps\t{$src2, $dst|$dst, $src2}",
847 [(set VR128:$dst, (v2i64
848 (or VR128:$src1, VR128:$src2)))]>;
849 def XORPSrr : PSI<0x57, MRMSrcReg,
850 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
851 "xorps\t{$src2, $dst|$dst, $src2}",
852 [(set VR128:$dst, (v2i64
853 (xor VR128:$src1, VR128:$src2)))]>;
856 def ANDPSrm : PSI<0x54, MRMSrcMem,
857 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
858 "andps\t{$src2, $dst|$dst, $src2}",
859 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
860 (memopv2i64 addr:$src2)))]>;
861 def ORPSrm : PSI<0x56, MRMSrcMem,
862 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
863 "orps\t{$src2, $dst|$dst, $src2}",
864 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
865 (memopv2i64 addr:$src2)))]>;
866 def XORPSrm : PSI<0x57, MRMSrcMem,
867 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
868 "xorps\t{$src2, $dst|$dst, $src2}",
869 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
870 (memopv2i64 addr:$src2)))]>;
871 def ANDNPSrr : PSI<0x55, MRMSrcReg,
872 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
873 "andnps\t{$src2, $dst|$dst, $src2}",
875 (v2i64 (and (xor VR128:$src1,
876 (bc_v2i64 (v4i32 immAllOnesV))),
878 def ANDNPSrm : PSI<0x55, MRMSrcMem,
879 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
880 "andnps\t{$src2, $dst|$dst, $src2}",
882 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
883 (bc_v2i64 (v4i32 immAllOnesV))),
884 (memopv2i64 addr:$src2))))]>;
887 let Constraints = "$src1 = $dst" in {
888 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
889 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
890 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
891 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
892 VR128:$src, imm:$cc))]>;
893 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
894 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
895 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
896 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
897 (memop addr:$src), imm:$cc))]>;
899 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
900 (CMPPSrri VR128:$src1, VR128:$src2, imm:$cc)>;
901 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
902 (CMPPSrmi VR128:$src1, addr:$src2, imm:$cc)>;
904 // Shuffle and unpack instructions
905 let Constraints = "$src1 = $dst" in {
906 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
907 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
908 (outs VR128:$dst), (ins VR128:$src1,
909 VR128:$src2, i32i8imm:$src3),
910 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
912 (v4f32 (vector_shuffle
913 VR128:$src1, VR128:$src2,
914 SHUFP_shuffle_mask:$src3)))]>;
915 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
916 (outs VR128:$dst), (ins VR128:$src1,
917 f128mem:$src2, i32i8imm:$src3),
918 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
920 (v4f32 (vector_shuffle
921 VR128:$src1, (memopv4f32 addr:$src2),
922 SHUFP_shuffle_mask:$src3)))]>;
924 let AddedComplexity = 10 in {
925 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
926 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
927 "unpckhps\t{$src2, $dst|$dst, $src2}",
929 (v4f32 (vector_shuffle
930 VR128:$src1, VR128:$src2,
931 UNPCKH_shuffle_mask)))]>;
932 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
933 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
934 "unpckhps\t{$src2, $dst|$dst, $src2}",
936 (v4f32 (vector_shuffle
937 VR128:$src1, (memopv4f32 addr:$src2),
938 UNPCKH_shuffle_mask)))]>;
940 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
941 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
942 "unpcklps\t{$src2, $dst|$dst, $src2}",
944 (v4f32 (vector_shuffle
945 VR128:$src1, VR128:$src2,
946 UNPCKL_shuffle_mask)))]>;
947 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
948 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
949 "unpcklps\t{$src2, $dst|$dst, $src2}",
951 (v4f32 (vector_shuffle
952 VR128:$src1, (memopv4f32 addr:$src2),
953 UNPCKL_shuffle_mask)))]>;
955 } // Constraints = "$src1 = $dst"
958 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
959 "movmskps\t{$src, $dst|$dst, $src}",
960 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
961 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
962 "movmskpd\t{$src, $dst|$dst, $src}",
963 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
965 // Prefetch intrinsic.
966 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
967 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
968 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
969 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
970 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
971 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
972 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
973 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
975 // Non-temporal stores
976 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
977 "movntps\t{$src, $dst|$dst, $src}",
978 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
980 // Load, store, and memory fence
981 def SFENCE : PSI<0xAE, MRM7m, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
984 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
985 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
986 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
987 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
989 // Alias instructions that map zero vector to pxor / xorp* for sse.
990 // We set isSimpleLoad because this can be converted to a constant-pool
991 // load of an all-zeros value if folding it would be beneficial.
992 let isReMaterializable = 1, isAsCheapAsAMove = 1, isSimpleLoad = 1 in
993 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
995 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
997 let Predicates = [HasSSE1] in {
998 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
999 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
1000 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
1001 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
1002 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
1005 // FR32 to 128-bit vector conversion.
1006 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
1007 "movss\t{$src, $dst|$dst, $src}",
1009 (v4f32 (scalar_to_vector FR32:$src)))]>;
1010 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1011 "movss\t{$src, $dst|$dst, $src}",
1013 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
1015 // FIXME: may not be able to eliminate this movss with coalescing the src and
1016 // dest register classes are different. We really want to write this pattern
1018 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1019 // (f32 FR32:$src)>;
1020 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src),
1021 "movss\t{$src, $dst|$dst, $src}",
1022 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
1024 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
1025 "movss\t{$src, $dst|$dst, $src}",
1026 [(store (f32 (vector_extract (v4f32 VR128:$src),
1027 (iPTR 0))), addr:$dst)]>;
1030 // Move to lower bits of a VR128, leaving upper bits alone.
1031 // Three operand (but two address) aliases.
1032 let Constraints = "$src1 = $dst" in {
1033 let neverHasSideEffects = 1 in
1034 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
1035 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
1036 "movss\t{$src2, $dst|$dst, $src2}", []>;
1038 let AddedComplexity = 15 in
1039 def MOVLPSrr : SSI<0x10, MRMSrcReg,
1040 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1041 "movss\t{$src2, $dst|$dst, $src2}",
1043 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
1044 MOVL_shuffle_mask)))]>;
1047 // Move to lower bits of a VR128 and zeroing upper bits.
1048 // Loading from memory automatically zeroing upper bits.
1049 let AddedComplexity = 20 in
1050 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1051 "movss\t{$src, $dst|$dst, $src}",
1052 [(set VR128:$dst, (v4f32 (X86vzmovl (v4f32 (scalar_to_vector
1053 (loadf32 addr:$src))))))]>;
1055 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1056 (MOVZSS2PSrm addr:$src)>;
1058 //===----------------------------------------------------------------------===//
1059 // SSE2 Instructions
1060 //===----------------------------------------------------------------------===//
1062 // Move Instructions
1063 let neverHasSideEffects = 1 in
1064 def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1065 "movsd\t{$src, $dst|$dst, $src}", []>;
1066 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1067 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1068 "movsd\t{$src, $dst|$dst, $src}",
1069 [(set FR64:$dst, (loadf64 addr:$src))]>;
1070 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1071 "movsd\t{$src, $dst|$dst, $src}",
1072 [(store FR64:$src, addr:$dst)]>;
1074 // Conversion instructions
1075 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1076 "cvttsd2si\t{$src, $dst|$dst, $src}",
1077 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1078 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1079 "cvttsd2si\t{$src, $dst|$dst, $src}",
1080 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1081 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1082 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1083 [(set FR32:$dst, (fround FR64:$src))]>;
1084 def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1085 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1086 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
1087 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1088 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1089 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1090 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1091 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1092 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1094 // SSE2 instructions with XS prefix
1095 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1096 "cvtss2sd\t{$src, $dst|$dst, $src}",
1097 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1098 Requires<[HasSSE2]>;
1099 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1100 "cvtss2sd\t{$src, $dst|$dst, $src}",
1101 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1102 Requires<[HasSSE2]>;
1104 // Match intrinsics which expect XMM operand(s).
1105 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1106 "cvtsd2si\t{$src, $dst|$dst, $src}",
1107 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1108 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1109 "cvtsd2si\t{$src, $dst|$dst, $src}",
1110 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1111 (load addr:$src)))]>;
1113 // Match intrinisics which expect MM and XMM operand(s).
1114 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1115 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1116 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1117 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1118 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1119 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1120 (memop addr:$src)))]>;
1121 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1122 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1123 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1124 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1125 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1126 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1127 (memop addr:$src)))]>;
1128 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1129 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1130 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1131 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1132 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1133 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1134 (load addr:$src)))]>;
1136 // Aliases for intrinsics
1137 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1138 "cvttsd2si\t{$src, $dst|$dst, $src}",
1140 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1141 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1142 "cvttsd2si\t{$src, $dst|$dst, $src}",
1143 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1144 (load addr:$src)))]>;
1146 // Comparison instructions
1147 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1148 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1149 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1150 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1152 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1153 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1154 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1157 let Defs = [EFLAGS] in {
1158 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1159 "ucomisd\t{$src2, $src1|$src1, $src2}",
1160 [(X86cmp FR64:$src1, FR64:$src2), (implicit EFLAGS)]>;
1161 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1162 "ucomisd\t{$src2, $src1|$src1, $src2}",
1163 [(X86cmp FR64:$src1, (loadf64 addr:$src2)),
1164 (implicit EFLAGS)]>;
1167 // Aliases to match intrinsics which expect XMM operand(s).
1168 let Constraints = "$src1 = $dst" in {
1169 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1170 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1171 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1172 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1173 VR128:$src, imm:$cc))]>;
1174 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1175 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1176 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1177 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1178 (load addr:$src), imm:$cc))]>;
1181 let Defs = [EFLAGS] in {
1182 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1183 "ucomisd\t{$src2, $src1|$src1, $src2}",
1184 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1185 (implicit EFLAGS)]>;
1186 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1187 "ucomisd\t{$src2, $src1|$src1, $src2}",
1188 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2)),
1189 (implicit EFLAGS)]>;
1191 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1192 "comisd\t{$src2, $src1|$src1, $src2}",
1193 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1194 (implicit EFLAGS)]>;
1195 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1196 "comisd\t{$src2, $src1|$src1, $src2}",
1197 [(X86comi (v2f64 VR128:$src1), (load addr:$src2)),
1198 (implicit EFLAGS)]>;
1201 // Aliases of packed SSE2 instructions for scalar use. These all have names that
1204 // Alias instructions that map fld0 to pxor for sse.
1205 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1206 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
1207 "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
1208 Requires<[HasSSE2]>, TB, OpSize;
1210 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1212 let neverHasSideEffects = 1 in
1213 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1214 "movapd\t{$src, $dst|$dst, $src}", []>;
1216 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1218 let isSimpleLoad = 1 in
1219 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1220 "movapd\t{$src, $dst|$dst, $src}",
1221 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1223 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1224 let Constraints = "$src1 = $dst" in {
1225 let isCommutable = 1 in {
1226 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst),
1227 (ins FR64:$src1, FR64:$src2),
1228 "andpd\t{$src2, $dst|$dst, $src2}",
1229 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1230 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst),
1231 (ins FR64:$src1, FR64:$src2),
1232 "orpd\t{$src2, $dst|$dst, $src2}",
1233 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1234 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst),
1235 (ins FR64:$src1, FR64:$src2),
1236 "xorpd\t{$src2, $dst|$dst, $src2}",
1237 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1240 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst),
1241 (ins FR64:$src1, f128mem:$src2),
1242 "andpd\t{$src2, $dst|$dst, $src2}",
1243 [(set FR64:$dst, (X86fand FR64:$src1,
1244 (memopfsf64 addr:$src2)))]>;
1245 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst),
1246 (ins FR64:$src1, f128mem:$src2),
1247 "orpd\t{$src2, $dst|$dst, $src2}",
1248 [(set FR64:$dst, (X86for FR64:$src1,
1249 (memopfsf64 addr:$src2)))]>;
1250 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst),
1251 (ins FR64:$src1, f128mem:$src2),
1252 "xorpd\t{$src2, $dst|$dst, $src2}",
1253 [(set FR64:$dst, (X86fxor FR64:$src1,
1254 (memopfsf64 addr:$src2)))]>;
1256 let neverHasSideEffects = 1 in {
1257 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1258 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1259 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1261 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1262 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1263 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1267 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1269 /// In addition, we also have a special variant of the scalar form here to
1270 /// represent the associated intrinsic operation. This form is unlike the
1271 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1272 /// and leaves the top elements undefined.
1274 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1275 /// six "instructions".
1277 let Constraints = "$src1 = $dst" in {
1278 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1279 SDNode OpNode, Intrinsic F64Int,
1280 bit Commutable = 0> {
1281 // Scalar operation, reg+reg.
1282 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1283 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1284 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1285 let isCommutable = Commutable;
1288 // Scalar operation, reg+mem.
1289 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2),
1290 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1291 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1293 // Vector operation, reg+reg.
1294 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1295 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1296 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1297 let isCommutable = Commutable;
1300 // Vector operation, reg+mem.
1301 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1302 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1303 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1305 // Intrinsic operation, reg+reg.
1306 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1307 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1308 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1309 let isCommutable = Commutable;
1312 // Intrinsic operation, reg+mem.
1313 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1314 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1315 [(set VR128:$dst, (F64Int VR128:$src1,
1316 sse_load_f64:$src2))]>;
1320 // Arithmetic instructions
1321 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1322 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1323 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1324 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1326 /// sse2_fp_binop_rm - Other SSE2 binops
1328 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1329 /// instructions for a full-vector intrinsic form. Operations that map
1330 /// onto C operators don't use this form since they just use the plain
1331 /// vector form instead of having a separate vector intrinsic form.
1333 /// This provides a total of eight "instructions".
1335 let Constraints = "$src1 = $dst" in {
1336 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1340 bit Commutable = 0> {
1342 // Scalar operation, reg+reg.
1343 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1344 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1345 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1346 let isCommutable = Commutable;
1349 // Scalar operation, reg+mem.
1350 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1351 (ins FR64:$src1, f64mem:$src2),
1352 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1353 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1355 // Vector operation, reg+reg.
1356 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1357 (ins VR128:$src1, VR128:$src2),
1358 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1359 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1360 let isCommutable = Commutable;
1363 // Vector operation, reg+mem.
1364 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1365 (ins VR128:$src1, f128mem:$src2),
1366 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1367 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1369 // Intrinsic operation, reg+reg.
1370 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1371 (ins VR128:$src1, VR128:$src2),
1372 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1373 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1374 let isCommutable = Commutable;
1377 // Intrinsic operation, reg+mem.
1378 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1379 (ins VR128:$src1, sdmem:$src2),
1380 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1381 [(set VR128:$dst, (F64Int VR128:$src1,
1382 sse_load_f64:$src2))]>;
1384 // Vector intrinsic operation, reg+reg.
1385 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1386 (ins VR128:$src1, VR128:$src2),
1387 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1388 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1389 let isCommutable = Commutable;
1392 // Vector intrinsic operation, reg+mem.
1393 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1394 (ins VR128:$src1, f128mem:$src2),
1395 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1396 [(set VR128:$dst, (V2F64Int VR128:$src1,
1397 (memopv2f64 addr:$src2)))]>;
1401 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1402 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1403 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1404 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1406 //===----------------------------------------------------------------------===//
1407 // SSE packed FP Instructions
1409 // Move Instructions
1410 let neverHasSideEffects = 1 in
1411 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1412 "movapd\t{$src, $dst|$dst, $src}", []>;
1413 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1414 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1415 "movapd\t{$src, $dst|$dst, $src}",
1416 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1418 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1419 "movapd\t{$src, $dst|$dst, $src}",
1420 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1422 let neverHasSideEffects = 1 in
1423 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1424 "movupd\t{$src, $dst|$dst, $src}", []>;
1425 let isSimpleLoad = 1 in
1426 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1427 "movupd\t{$src, $dst|$dst, $src}",
1428 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1429 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1430 "movupd\t{$src, $dst|$dst, $src}",
1431 [(store (v2f64 VR128:$src), addr:$dst)]>;
1433 // Intrinsic forms of MOVUPD load and store
1434 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1435 "movupd\t{$src, $dst|$dst, $src}",
1436 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1437 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1438 "movupd\t{$src, $dst|$dst, $src}",
1439 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1441 let Constraints = "$src1 = $dst" in {
1442 let AddedComplexity = 20 in {
1443 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1444 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1445 "movlpd\t{$src2, $dst|$dst, $src2}",
1447 (v2f64 (vector_shuffle VR128:$src1,
1448 (scalar_to_vector (loadf64 addr:$src2)),
1449 MOVLP_shuffle_mask)))]>;
1450 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1451 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1452 "movhpd\t{$src2, $dst|$dst, $src2}",
1454 (v2f64 (vector_shuffle VR128:$src1,
1455 (scalar_to_vector (loadf64 addr:$src2)),
1456 MOVHP_shuffle_mask)))]>;
1457 } // AddedComplexity
1458 } // Constraints = "$src1 = $dst"
1460 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1461 "movlpd\t{$src, $dst|$dst, $src}",
1462 [(store (f64 (vector_extract (v2f64 VR128:$src),
1463 (iPTR 0))), addr:$dst)]>;
1465 // v2f64 extract element 1 is always custom lowered to unpack high to low
1466 // and extract element 0 so the non-store version isn't too horrible.
1467 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1468 "movhpd\t{$src, $dst|$dst, $src}",
1469 [(store (f64 (vector_extract
1470 (v2f64 (vector_shuffle VR128:$src, (undef),
1471 UNPCKH_shuffle_mask)), (iPTR 0))),
1474 // SSE2 instructions without OpSize prefix
1475 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1476 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1477 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1478 TB, Requires<[HasSSE2]>;
1479 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1480 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1481 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1482 (bitconvert (memopv2i64 addr:$src))))]>,
1483 TB, Requires<[HasSSE2]>;
1485 // SSE2 instructions with XS prefix
1486 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1487 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1488 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1489 XS, Requires<[HasSSE2]>;
1490 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1491 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1492 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1493 (bitconvert (memopv2i64 addr:$src))))]>,
1494 XS, Requires<[HasSSE2]>;
1496 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1497 "cvtps2dq\t{$src, $dst|$dst, $src}",
1498 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1499 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1500 "cvtps2dq\t{$src, $dst|$dst, $src}",
1501 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1502 (memop addr:$src)))]>;
1503 // SSE2 packed instructions with XS prefix
1504 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1505 "cvttps2dq\t{$src, $dst|$dst, $src}",
1506 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
1507 XS, Requires<[HasSSE2]>;
1508 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1509 "cvttps2dq\t{$src, $dst|$dst, $src}",
1510 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1511 (memop addr:$src)))]>,
1512 XS, Requires<[HasSSE2]>;
1514 // SSE2 packed instructions with XD prefix
1515 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1516 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1517 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1518 XD, Requires<[HasSSE2]>;
1519 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1520 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1521 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1522 (memop addr:$src)))]>,
1523 XD, Requires<[HasSSE2]>;
1525 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1526 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1527 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1528 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1529 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1530 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1531 (memop addr:$src)))]>;
1533 // SSE2 instructions without OpSize prefix
1534 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1535 "cvtps2pd\t{$src, $dst|$dst, $src}",
1536 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1537 TB, Requires<[HasSSE2]>;
1538 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1539 "cvtps2pd\t{$src, $dst|$dst, $src}",
1540 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1541 (load addr:$src)))]>,
1542 TB, Requires<[HasSSE2]>;
1544 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1545 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1546 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1547 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1548 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1549 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1550 (memop addr:$src)))]>;
1552 // Match intrinsics which expect XMM operand(s).
1553 // Aliases for intrinsics
1554 let Constraints = "$src1 = $dst" in {
1555 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1556 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1557 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1558 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1560 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1561 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1562 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1563 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1564 (loadi32 addr:$src2)))]>;
1565 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1566 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1567 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1568 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1570 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1571 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1572 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1573 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1574 (load addr:$src2)))]>;
1575 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1576 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1577 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1578 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1579 VR128:$src2))]>, XS,
1580 Requires<[HasSSE2]>;
1581 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1582 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1583 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1584 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1585 (load addr:$src2)))]>, XS,
1586 Requires<[HasSSE2]>;
1591 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1593 /// In addition, we also have a special variant of the scalar form here to
1594 /// represent the associated intrinsic operation. This form is unlike the
1595 /// plain scalar form, in that it takes an entire vector (instead of a
1596 /// scalar) and leaves the top elements undefined.
1598 /// And, we have a special variant form for a full-vector intrinsic form.
1600 /// These four forms can each have a reg or a mem operand, so there are a
1601 /// total of eight "instructions".
1603 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1607 bit Commutable = 0> {
1608 // Scalar operation, reg.
1609 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1610 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1611 [(set FR64:$dst, (OpNode FR64:$src))]> {
1612 let isCommutable = Commutable;
1615 // Scalar operation, mem.
1616 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1617 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1618 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1620 // Vector operation, reg.
1621 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1622 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1623 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1624 let isCommutable = Commutable;
1627 // Vector operation, mem.
1628 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1629 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1630 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1632 // Intrinsic operation, reg.
1633 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1634 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1635 [(set VR128:$dst, (F64Int VR128:$src))]> {
1636 let isCommutable = Commutable;
1639 // Intrinsic operation, mem.
1640 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1641 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1642 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1644 // Vector intrinsic operation, reg
1645 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1646 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1647 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1648 let isCommutable = Commutable;
1651 // Vector intrinsic operation, mem
1652 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1653 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1654 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1658 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1659 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1661 // There is no f64 version of the reciprocal approximation instructions.
1664 let Constraints = "$src1 = $dst" in {
1665 let isCommutable = 1 in {
1666 def ANDPDrr : PDI<0x54, MRMSrcReg,
1667 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1668 "andpd\t{$src2, $dst|$dst, $src2}",
1670 (and (bc_v2i64 (v2f64 VR128:$src1)),
1671 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1672 def ORPDrr : PDI<0x56, MRMSrcReg,
1673 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1674 "orpd\t{$src2, $dst|$dst, $src2}",
1676 (or (bc_v2i64 (v2f64 VR128:$src1)),
1677 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1678 def XORPDrr : PDI<0x57, MRMSrcReg,
1679 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1680 "xorpd\t{$src2, $dst|$dst, $src2}",
1682 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1683 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1686 def ANDPDrm : PDI<0x54, MRMSrcMem,
1687 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1688 "andpd\t{$src2, $dst|$dst, $src2}",
1690 (and (bc_v2i64 (v2f64 VR128:$src1)),
1691 (memopv2i64 addr:$src2)))]>;
1692 def ORPDrm : PDI<0x56, MRMSrcMem,
1693 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1694 "orpd\t{$src2, $dst|$dst, $src2}",
1696 (or (bc_v2i64 (v2f64 VR128:$src1)),
1697 (memopv2i64 addr:$src2)))]>;
1698 def XORPDrm : PDI<0x57, MRMSrcMem,
1699 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1700 "xorpd\t{$src2, $dst|$dst, $src2}",
1702 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1703 (memopv2i64 addr:$src2)))]>;
1704 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1705 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1706 "andnpd\t{$src2, $dst|$dst, $src2}",
1708 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1709 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1710 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1711 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1712 "andnpd\t{$src2, $dst|$dst, $src2}",
1714 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1715 (memopv2i64 addr:$src2)))]>;
1718 let Constraints = "$src1 = $dst" in {
1719 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1720 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1721 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1722 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1723 VR128:$src, imm:$cc))]>;
1724 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1725 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1726 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1727 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1728 (memop addr:$src), imm:$cc))]>;
1730 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1731 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1732 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1733 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1735 // Shuffle and unpack instructions
1736 let Constraints = "$src1 = $dst" in {
1737 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1738 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1739 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1740 [(set VR128:$dst, (v2f64 (vector_shuffle
1741 VR128:$src1, VR128:$src2,
1742 SHUFP_shuffle_mask:$src3)))]>;
1743 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1744 (outs VR128:$dst), (ins VR128:$src1,
1745 f128mem:$src2, i8imm:$src3),
1746 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1748 (v2f64 (vector_shuffle
1749 VR128:$src1, (memopv2f64 addr:$src2),
1750 SHUFP_shuffle_mask:$src3)))]>;
1752 let AddedComplexity = 10 in {
1753 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1754 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1755 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1757 (v2f64 (vector_shuffle
1758 VR128:$src1, VR128:$src2,
1759 UNPCKH_shuffle_mask)))]>;
1760 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1761 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1762 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1764 (v2f64 (vector_shuffle
1765 VR128:$src1, (memopv2f64 addr:$src2),
1766 UNPCKH_shuffle_mask)))]>;
1768 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1769 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1770 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1772 (v2f64 (vector_shuffle
1773 VR128:$src1, VR128:$src2,
1774 UNPCKL_shuffle_mask)))]>;
1775 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1776 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1777 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1779 (v2f64 (vector_shuffle
1780 VR128:$src1, (memopv2f64 addr:$src2),
1781 UNPCKL_shuffle_mask)))]>;
1782 } // AddedComplexity
1783 } // Constraints = "$src1 = $dst"
1786 //===----------------------------------------------------------------------===//
1787 // SSE integer instructions
1789 // Move Instructions
1790 let neverHasSideEffects = 1 in
1791 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1792 "movdqa\t{$src, $dst|$dst, $src}", []>;
1793 let isSimpleLoad = 1, mayLoad = 1 in
1794 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1795 "movdqa\t{$src, $dst|$dst, $src}",
1796 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1798 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1799 "movdqa\t{$src, $dst|$dst, $src}",
1800 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1801 let isSimpleLoad = 1, mayLoad = 1 in
1802 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1803 "movdqu\t{$src, $dst|$dst, $src}",
1804 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1805 XS, Requires<[HasSSE2]>;
1807 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1808 "movdqu\t{$src, $dst|$dst, $src}",
1809 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1810 XS, Requires<[HasSSE2]>;
1812 // Intrinsic forms of MOVDQU load and store
1813 let isSimpleLoad = 1 in
1814 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1815 "movdqu\t{$src, $dst|$dst, $src}",
1816 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1817 XS, Requires<[HasSSE2]>;
1818 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1819 "movdqu\t{$src, $dst|$dst, $src}",
1820 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1821 XS, Requires<[HasSSE2]>;
1823 let Constraints = "$src1 = $dst" in {
1825 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1826 bit Commutable = 0> {
1827 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1828 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1829 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1830 let isCommutable = Commutable;
1832 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1833 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1834 [(set VR128:$dst, (IntId VR128:$src1,
1835 (bitconvert (memopv2i64 addr:$src2))))]>;
1838 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1840 Intrinsic IntId, Intrinsic IntId2> {
1841 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1842 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1843 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1844 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1845 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1846 [(set VR128:$dst, (IntId VR128:$src1,
1847 (bitconvert (memopv2i64 addr:$src2))))]>;
1848 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1849 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1850 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
1853 /// PDI_binop_rm - Simple SSE2 binary operator.
1854 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1855 ValueType OpVT, bit Commutable = 0> {
1856 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1857 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1858 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1859 let isCommutable = Commutable;
1861 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1862 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1863 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1864 (bitconvert (memopv2i64 addr:$src2)))))]>;
1867 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1869 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1870 /// to collapse (bitconvert VT to VT) into its operand.
1872 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1873 bit Commutable = 0> {
1874 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1875 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1876 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1877 let isCommutable = Commutable;
1879 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1880 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1881 [(set VR128:$dst, (OpNode VR128:$src1,(memopv2i64 addr:$src2)))]>;
1884 } // Constraints = "$src1 = $dst"
1886 // 128-bit Integer Arithmetic
1888 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1889 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1890 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1891 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1893 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1894 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1895 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1896 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1898 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1899 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1900 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1901 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1903 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1904 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1905 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1906 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1908 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1910 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1911 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1912 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1914 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1916 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1917 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1920 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1921 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1922 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1923 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1924 defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
1927 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
1928 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
1929 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
1930 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
1931 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
1932 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
1934 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
1935 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
1936 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
1937 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
1938 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
1939 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
1941 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
1942 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
1943 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
1944 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
1946 // 128-bit logical shifts.
1947 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1948 def PSLLDQri : PDIi8<0x73, MRM7r,
1949 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1950 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
1951 def PSRLDQri : PDIi8<0x73, MRM3r,
1952 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1953 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
1954 // PSRADQri doesn't exist in SSE[1-3].
1957 let Predicates = [HasSSE2] in {
1958 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1959 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1960 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1961 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1962 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
1963 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
1964 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
1965 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
1966 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
1967 (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1969 // Shift up / down and insert zero's.
1970 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
1971 (v2i64 (PSLLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1972 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
1973 (v2i64 (PSRLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1977 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1978 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1979 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1981 let Constraints = "$src1 = $dst" in {
1982 def PANDNrr : PDI<0xDF, MRMSrcReg,
1983 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1984 "pandn\t{$src2, $dst|$dst, $src2}",
1985 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1988 def PANDNrm : PDI<0xDF, MRMSrcMem,
1989 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1990 "pandn\t{$src2, $dst|$dst, $src2}",
1991 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1992 (memopv2i64 addr:$src2))))]>;
1995 // SSE2 Integer comparison
1996 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
1997 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
1998 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
1999 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2000 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2001 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2003 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2004 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2005 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2006 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2007 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2008 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2009 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2010 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2011 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2012 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2013 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2014 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2016 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2017 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2018 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2019 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2020 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2021 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2022 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2023 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2024 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2025 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2026 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2027 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2030 // Pack instructions
2031 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2032 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2033 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2035 // Shuffle and unpack instructions
2036 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2037 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2038 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2039 [(set VR128:$dst, (v4i32 (vector_shuffle
2040 VR128:$src1, (undef),
2041 PSHUFD_shuffle_mask:$src2)))]>;
2042 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2043 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2044 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2045 [(set VR128:$dst, (v4i32 (vector_shuffle
2046 (bc_v4i32(memopv2i64 addr:$src1)),
2048 PSHUFD_shuffle_mask:$src2)))]>;
2050 // SSE2 with ImmT == Imm8 and XS prefix.
2051 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2052 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2053 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2054 [(set VR128:$dst, (v8i16 (vector_shuffle
2055 VR128:$src1, (undef),
2056 PSHUFHW_shuffle_mask:$src2)))]>,
2057 XS, Requires<[HasSSE2]>;
2058 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2059 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2060 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2061 [(set VR128:$dst, (v8i16 (vector_shuffle
2062 (bc_v8i16 (memopv2i64 addr:$src1)),
2064 PSHUFHW_shuffle_mask:$src2)))]>,
2065 XS, Requires<[HasSSE2]>;
2067 // SSE2 with ImmT == Imm8 and XD prefix.
2068 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2069 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2070 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2071 [(set VR128:$dst, (v8i16 (vector_shuffle
2072 VR128:$src1, (undef),
2073 PSHUFLW_shuffle_mask:$src2)))]>,
2074 XD, Requires<[HasSSE2]>;
2075 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2076 (outs VR128:$dst), (ins i128mem:$src1, i32i8imm:$src2),
2077 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2078 [(set VR128:$dst, (v8i16 (vector_shuffle
2079 (bc_v8i16 (memopv2i64 addr:$src1)),
2081 PSHUFLW_shuffle_mask:$src2)))]>,
2082 XD, Requires<[HasSSE2]>;
2085 let Constraints = "$src1 = $dst" in {
2086 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
2087 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2088 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2090 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2091 UNPCKL_shuffle_mask)))]>;
2092 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
2093 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2094 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2096 (v16i8 (vector_shuffle VR128:$src1,
2097 (bc_v16i8 (memopv2i64 addr:$src2)),
2098 UNPCKL_shuffle_mask)))]>;
2099 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
2100 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2101 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2103 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2104 UNPCKL_shuffle_mask)))]>;
2105 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
2106 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2107 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2109 (v8i16 (vector_shuffle VR128:$src1,
2110 (bc_v8i16 (memopv2i64 addr:$src2)),
2111 UNPCKL_shuffle_mask)))]>;
2112 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2113 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2114 "punpckldq\t{$src2, $dst|$dst, $src2}",
2116 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2117 UNPCKL_shuffle_mask)))]>;
2118 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2119 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2120 "punpckldq\t{$src2, $dst|$dst, $src2}",
2122 (v4i32 (vector_shuffle VR128:$src1,
2123 (bc_v4i32 (memopv2i64 addr:$src2)),
2124 UNPCKL_shuffle_mask)))]>;
2125 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2126 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2127 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2129 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2130 UNPCKL_shuffle_mask)))]>;
2131 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2132 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2133 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2135 (v2i64 (vector_shuffle VR128:$src1,
2136 (memopv2i64 addr:$src2),
2137 UNPCKL_shuffle_mask)))]>;
2139 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2140 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2141 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2143 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2144 UNPCKH_shuffle_mask)))]>;
2145 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2146 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2147 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2149 (v16i8 (vector_shuffle VR128:$src1,
2150 (bc_v16i8 (memopv2i64 addr:$src2)),
2151 UNPCKH_shuffle_mask)))]>;
2152 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2153 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2154 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2156 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2157 UNPCKH_shuffle_mask)))]>;
2158 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2159 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2160 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2162 (v8i16 (vector_shuffle VR128:$src1,
2163 (bc_v8i16 (memopv2i64 addr:$src2)),
2164 UNPCKH_shuffle_mask)))]>;
2165 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2166 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2167 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2169 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2170 UNPCKH_shuffle_mask)))]>;
2171 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2172 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2173 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2175 (v4i32 (vector_shuffle VR128:$src1,
2176 (bc_v4i32 (memopv2i64 addr:$src2)),
2177 UNPCKH_shuffle_mask)))]>;
2178 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2179 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2180 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2182 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2183 UNPCKH_shuffle_mask)))]>;
2184 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2185 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2186 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2188 (v2i64 (vector_shuffle VR128:$src1,
2189 (memopv2i64 addr:$src2),
2190 UNPCKH_shuffle_mask)))]>;
2194 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2195 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2196 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2197 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2199 let Constraints = "$src1 = $dst" in {
2200 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2201 (outs VR128:$dst), (ins VR128:$src1,
2202 GR32:$src2, i32i8imm:$src3),
2203 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2205 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2206 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2207 (outs VR128:$dst), (ins VR128:$src1,
2208 i16mem:$src2, i32i8imm:$src3),
2209 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2211 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2216 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2217 "pmovmskb\t{$src, $dst|$dst, $src}",
2218 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2220 // Conditional store
2222 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2223 "maskmovdqu\t{$mask, $src|$src, $mask}",
2224 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2226 // Non-temporal stores
2227 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2228 "movntpd\t{$src, $dst|$dst, $src}",
2229 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2230 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2231 "movntdq\t{$src, $dst|$dst, $src}",
2232 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2233 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2234 "movnti\t{$src, $dst|$dst, $src}",
2235 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2236 TB, Requires<[HasSSE2]>;
2239 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2240 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2241 TB, Requires<[HasSSE2]>;
2243 // Load, store, and memory fence
2244 def LFENCE : I<0xAE, MRM5r, (outs), (ins),
2245 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2246 def MFENCE : I<0xAE, MRM6r, (outs), (ins),
2247 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2249 //TODO: custom lower this so as to never even generate the noop
2250 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2252 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2253 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2254 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2257 // Alias instructions that map zero vector to pxor / xorp* for sse.
2258 // We set isSimpleLoad because this can be converted to a constant-pool
2259 // load of an all-ones value if folding it would be beneficial.
2260 let isReMaterializable = 1, isAsCheapAsAMove = 1, isSimpleLoad = 1 in
2261 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
2262 "pcmpeqd\t$dst, $dst",
2263 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2265 // FR64 to 128-bit vector conversion.
2266 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src),
2267 "movsd\t{$src, $dst|$dst, $src}",
2269 (v2f64 (scalar_to_vector FR64:$src)))]>;
2270 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2271 "movsd\t{$src, $dst|$dst, $src}",
2273 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2275 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2276 "movd\t{$src, $dst|$dst, $src}",
2278 (v4i32 (scalar_to_vector GR32:$src)))]>;
2279 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2280 "movd\t{$src, $dst|$dst, $src}",
2282 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2284 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2285 "movd\t{$src, $dst|$dst, $src}",
2286 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2288 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2289 "movd\t{$src, $dst|$dst, $src}",
2290 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2292 // SSE2 instructions with XS prefix
2293 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2294 "movq\t{$src, $dst|$dst, $src}",
2296 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2297 Requires<[HasSSE2]>;
2298 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2299 "movq\t{$src, $dst|$dst, $src}",
2300 [(store (i64 (vector_extract (v2i64 VR128:$src),
2301 (iPTR 0))), addr:$dst)]>;
2303 // FIXME: may not be able to eliminate this movss with coalescing the src and
2304 // dest register classes are different. We really want to write this pattern
2306 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2307 // (f32 FR32:$src)>;
2308 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src),
2309 "movsd\t{$src, $dst|$dst, $src}",
2310 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2312 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
2313 "movsd\t{$src, $dst|$dst, $src}",
2314 [(store (f64 (vector_extract (v2f64 VR128:$src),
2315 (iPTR 0))), addr:$dst)]>;
2316 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2317 "movd\t{$src, $dst|$dst, $src}",
2318 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2320 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2321 "movd\t{$src, $dst|$dst, $src}",
2322 [(store (i32 (vector_extract (v4i32 VR128:$src),
2323 (iPTR 0))), addr:$dst)]>;
2325 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2326 "movd\t{$src, $dst|$dst, $src}",
2327 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2328 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2329 "movd\t{$src, $dst|$dst, $src}",
2330 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2333 // Move to lower bits of a VR128, leaving upper bits alone.
2334 // Three operand (but two address) aliases.
2335 let Constraints = "$src1 = $dst" in {
2336 let neverHasSideEffects = 1 in
2337 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
2338 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
2339 "movsd\t{$src2, $dst|$dst, $src2}", []>;
2341 let AddedComplexity = 15 in
2342 def MOVLPDrr : SDI<0x10, MRMSrcReg,
2343 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2344 "movsd\t{$src2, $dst|$dst, $src2}",
2346 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2347 MOVL_shuffle_mask)))]>;
2350 // Store / copy lower 64-bits of a XMM register.
2351 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2352 "movq\t{$src, $dst|$dst, $src}",
2353 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2355 // Move to lower bits of a VR128 and zeroing upper bits.
2356 // Loading from memory automatically zeroing upper bits.
2357 let AddedComplexity = 20 in {
2358 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2359 "movsd\t{$src, $dst|$dst, $src}",
2361 (v2f64 (X86vzmovl (v2f64 (scalar_to_vector
2362 (loadf64 addr:$src))))))]>;
2364 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2365 (MOVZSD2PDrm addr:$src)>;
2366 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2367 (MOVZSD2PDrm addr:$src)>;
2368 def : Pat<(v2f64 (X86vzload addr:$src)), (MOVZSD2PDrm addr:$src)>;
2371 // movd / movq to XMM register zero-extends
2372 let AddedComplexity = 15 in {
2373 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2374 "movd\t{$src, $dst|$dst, $src}",
2375 [(set VR128:$dst, (v4i32 (X86vzmovl
2376 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2377 // This is X86-64 only.
2378 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2379 "mov{d|q}\t{$src, $dst|$dst, $src}",
2380 [(set VR128:$dst, (v2i64 (X86vzmovl
2381 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2384 let AddedComplexity = 20 in {
2385 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2386 "movd\t{$src, $dst|$dst, $src}",
2388 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2389 (loadi32 addr:$src))))))]>;
2391 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2392 (MOVZDI2PDIrm addr:$src)>;
2393 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2394 (MOVZDI2PDIrm addr:$src)>;
2395 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2396 (MOVZDI2PDIrm addr:$src)>;
2398 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2399 "movq\t{$src, $dst|$dst, $src}",
2401 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2402 (loadi64 addr:$src))))))]>, XS,
2403 Requires<[HasSSE2]>;
2405 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2406 (MOVZQI2PQIrm addr:$src)>;
2407 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2408 (MOVZQI2PQIrm addr:$src)>;
2409 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2412 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2413 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2414 let AddedComplexity = 15 in
2415 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2416 "movq\t{$src, $dst|$dst, $src}",
2417 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2418 XS, Requires<[HasSSE2]>;
2420 let AddedComplexity = 20 in {
2421 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2422 "movq\t{$src, $dst|$dst, $src}",
2423 [(set VR128:$dst, (v2i64 (X86vzmovl
2424 (loadv2i64 addr:$src))))]>,
2425 XS, Requires<[HasSSE2]>;
2427 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2428 (MOVZPQILo2PQIrm addr:$src)>;
2431 //===----------------------------------------------------------------------===//
2432 // SSE3 Instructions
2433 //===----------------------------------------------------------------------===//
2435 // Move Instructions
2436 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2437 "movshdup\t{$src, $dst|$dst, $src}",
2438 [(set VR128:$dst, (v4f32 (vector_shuffle
2439 VR128:$src, (undef),
2440 MOVSHDUP_shuffle_mask)))]>;
2441 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2442 "movshdup\t{$src, $dst|$dst, $src}",
2443 [(set VR128:$dst, (v4f32 (vector_shuffle
2444 (memopv4f32 addr:$src), (undef),
2445 MOVSHDUP_shuffle_mask)))]>;
2447 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2448 "movsldup\t{$src, $dst|$dst, $src}",
2449 [(set VR128:$dst, (v4f32 (vector_shuffle
2450 VR128:$src, (undef),
2451 MOVSLDUP_shuffle_mask)))]>;
2452 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2453 "movsldup\t{$src, $dst|$dst, $src}",
2454 [(set VR128:$dst, (v4f32 (vector_shuffle
2455 (memopv4f32 addr:$src), (undef),
2456 MOVSLDUP_shuffle_mask)))]>;
2458 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2459 "movddup\t{$src, $dst|$dst, $src}",
2461 (v2f64 (vector_shuffle VR128:$src, (undef),
2462 MOVDDUP_shuffle_mask)))]>;
2463 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2464 "movddup\t{$src, $dst|$dst, $src}",
2466 (v2f64 (vector_shuffle
2467 (scalar_to_vector (loadf64 addr:$src)),
2468 (undef), MOVDDUP_shuffle_mask)))]>;
2470 def : Pat<(vector_shuffle
2471 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
2472 (undef), MOVDDUP_shuffle_mask),
2473 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2474 def : Pat<(vector_shuffle
2475 (memopv2f64 addr:$src), (undef), MOVDDUP_shuffle_mask),
2476 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2480 let Constraints = "$src1 = $dst" in {
2481 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2482 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2483 "addsubps\t{$src2, $dst|$dst, $src2}",
2484 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2486 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2487 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2488 "addsubps\t{$src2, $dst|$dst, $src2}",
2489 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2490 (memop addr:$src2)))]>;
2491 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2492 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2493 "addsubpd\t{$src2, $dst|$dst, $src2}",
2494 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2496 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2497 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2498 "addsubpd\t{$src2, $dst|$dst, $src2}",
2499 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2500 (memop addr:$src2)))]>;
2503 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2504 "lddqu\t{$src, $dst|$dst, $src}",
2505 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2508 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2509 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2510 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2511 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2512 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2513 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2514 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2515 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2516 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2517 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2518 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2519 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2520 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2521 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2522 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2523 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2525 let Constraints = "$src1 = $dst" in {
2526 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2527 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2528 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2529 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2530 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2531 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2532 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2533 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2536 // Thread synchronization
2537 def MONITOR : I<0xC8, RawFrm, (outs), (ins), "monitor",
2538 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2539 def MWAIT : I<0xC9, RawFrm, (outs), (ins), "mwait",
2540 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2542 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2543 let AddedComplexity = 15 in
2544 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2545 MOVSHDUP_shuffle_mask)),
2546 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2547 let AddedComplexity = 20 in
2548 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2549 MOVSHDUP_shuffle_mask)),
2550 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2552 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2553 let AddedComplexity = 15 in
2554 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2555 MOVSLDUP_shuffle_mask)),
2556 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2557 let AddedComplexity = 20 in
2558 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2559 MOVSLDUP_shuffle_mask)),
2560 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2562 //===----------------------------------------------------------------------===//
2563 // SSSE3 Instructions
2564 //===----------------------------------------------------------------------===//
2566 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2567 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2568 Intrinsic IntId64, Intrinsic IntId128> {
2569 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2570 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2571 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2573 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2574 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2576 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2578 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2580 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2581 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2584 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2586 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2589 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2592 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2593 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2594 Intrinsic IntId64, Intrinsic IntId128> {
2595 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2597 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2598 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2600 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2602 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2605 (bitconvert (memopv4i16 addr:$src))))]>;
2607 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2609 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2610 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2613 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2615 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2618 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2621 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2622 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2623 Intrinsic IntId64, Intrinsic IntId128> {
2624 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2626 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2627 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2629 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2631 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2634 (bitconvert (memopv2i32 addr:$src))))]>;
2636 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2638 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2639 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2642 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2644 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2647 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2650 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2651 int_x86_ssse3_pabs_b,
2652 int_x86_ssse3_pabs_b_128>;
2653 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2654 int_x86_ssse3_pabs_w,
2655 int_x86_ssse3_pabs_w_128>;
2656 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2657 int_x86_ssse3_pabs_d,
2658 int_x86_ssse3_pabs_d_128>;
2660 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2661 let Constraints = "$src1 = $dst" in {
2662 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2663 Intrinsic IntId64, Intrinsic IntId128,
2664 bit Commutable = 0> {
2665 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2666 (ins VR64:$src1, VR64:$src2),
2667 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2668 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2669 let isCommutable = Commutable;
2671 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2672 (ins VR64:$src1, i64mem:$src2),
2673 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2675 (IntId64 VR64:$src1,
2676 (bitconvert (memopv8i8 addr:$src2))))]>;
2678 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2679 (ins VR128:$src1, VR128:$src2),
2680 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2681 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2683 let isCommutable = Commutable;
2685 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2686 (ins VR128:$src1, i128mem:$src2),
2687 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2689 (IntId128 VR128:$src1,
2690 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2694 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2695 let Constraints = "$src1 = $dst" in {
2696 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2697 Intrinsic IntId64, Intrinsic IntId128,
2698 bit Commutable = 0> {
2699 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2700 (ins VR64:$src1, VR64:$src2),
2701 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2702 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2703 let isCommutable = Commutable;
2705 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2706 (ins VR64:$src1, i64mem:$src2),
2707 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2709 (IntId64 VR64:$src1,
2710 (bitconvert (memopv4i16 addr:$src2))))]>;
2712 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2713 (ins VR128:$src1, VR128:$src2),
2714 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2715 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2717 let isCommutable = Commutable;
2719 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2720 (ins VR128:$src1, i128mem:$src2),
2721 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2723 (IntId128 VR128:$src1,
2724 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2728 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2729 let Constraints = "$src1 = $dst" in {
2730 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2731 Intrinsic IntId64, Intrinsic IntId128,
2732 bit Commutable = 0> {
2733 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2734 (ins VR64:$src1, VR64:$src2),
2735 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2736 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2737 let isCommutable = Commutable;
2739 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2740 (ins VR64:$src1, i64mem:$src2),
2741 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2743 (IntId64 VR64:$src1,
2744 (bitconvert (memopv2i32 addr:$src2))))]>;
2746 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2747 (ins VR128:$src1, VR128:$src2),
2748 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2749 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2751 let isCommutable = Commutable;
2753 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2754 (ins VR128:$src1, i128mem:$src2),
2755 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2757 (IntId128 VR128:$src1,
2758 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2762 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2763 int_x86_ssse3_phadd_w,
2764 int_x86_ssse3_phadd_w_128>;
2765 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2766 int_x86_ssse3_phadd_d,
2767 int_x86_ssse3_phadd_d_128>;
2768 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2769 int_x86_ssse3_phadd_sw,
2770 int_x86_ssse3_phadd_sw_128>;
2771 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2772 int_x86_ssse3_phsub_w,
2773 int_x86_ssse3_phsub_w_128>;
2774 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2775 int_x86_ssse3_phsub_d,
2776 int_x86_ssse3_phsub_d_128>;
2777 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2778 int_x86_ssse3_phsub_sw,
2779 int_x86_ssse3_phsub_sw_128>;
2780 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2781 int_x86_ssse3_pmadd_ub_sw,
2782 int_x86_ssse3_pmadd_ub_sw_128>;
2783 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2784 int_x86_ssse3_pmul_hr_sw,
2785 int_x86_ssse3_pmul_hr_sw_128, 1>;
2786 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2787 int_x86_ssse3_pshuf_b,
2788 int_x86_ssse3_pshuf_b_128>;
2789 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2790 int_x86_ssse3_psign_b,
2791 int_x86_ssse3_psign_b_128>;
2792 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2793 int_x86_ssse3_psign_w,
2794 int_x86_ssse3_psign_w_128>;
2795 defm PSIGND : SS3I_binop_rm_int_32<0x09, "psignd",
2796 int_x86_ssse3_psign_d,
2797 int_x86_ssse3_psign_d_128>;
2799 let Constraints = "$src1 = $dst" in {
2800 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2801 (ins VR64:$src1, VR64:$src2, i16imm:$src3),
2802 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2804 (int_x86_ssse3_palign_r
2805 VR64:$src1, VR64:$src2,
2807 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2808 (ins VR64:$src1, i64mem:$src2, i16imm:$src3),
2809 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2811 (int_x86_ssse3_palign_r
2813 (bitconvert (memopv2i32 addr:$src2)),
2816 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2817 (ins VR128:$src1, VR128:$src2, i32imm:$src3),
2818 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2820 (int_x86_ssse3_palign_r_128
2821 VR128:$src1, VR128:$src2,
2822 imm:$src3))]>, OpSize;
2823 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2824 (ins VR128:$src1, i128mem:$src2, i32imm:$src3),
2825 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2827 (int_x86_ssse3_palign_r_128
2829 (bitconvert (memopv4i32 addr:$src2)),
2830 imm:$src3))]>, OpSize;
2833 //===----------------------------------------------------------------------===//
2834 // Non-Instruction Patterns
2835 //===----------------------------------------------------------------------===//
2837 // extload f32 -> f64. This matches load+fextend because we have a hack in
2838 // the isel (PreprocessForFPConvert) that can introduce loads after dag combine.
2839 // Since these loads aren't folded into the fextend, we have to match it
2841 let Predicates = [HasSSE2] in
2842 def : Pat<(fextend (loadf32 addr:$src)),
2843 (CVTSS2SDrm addr:$src)>;
2846 let Predicates = [HasSSE2] in {
2847 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2848 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2849 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2850 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2851 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2852 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2853 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2854 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2855 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2856 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2857 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2858 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2859 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2860 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2861 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2862 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2863 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2864 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2865 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2866 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2867 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2868 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2869 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2870 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2871 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2872 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2873 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2874 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2875 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2876 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2879 // Move scalar to XMM zero-extended
2880 // movd to XMM register zero-extends
2881 let AddedComplexity = 15 in {
2882 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2883 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
2884 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2885 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
2886 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE1]>;
2887 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
2888 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>;
2889 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
2890 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>;
2893 // Splat v2f64 / v2i64
2894 let AddedComplexity = 10 in {
2895 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2896 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2897 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2898 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2899 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2900 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2901 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2902 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2905 // Special unary SHUFPSrri case.
2906 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2907 SHUFP_unary_shuffle_mask:$sm)),
2908 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2909 Requires<[HasSSE1]>;
2910 // Special unary SHUFPDrri case.
2911 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (undef),
2912 SHUFP_unary_shuffle_mask:$sm)),
2913 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2914 Requires<[HasSSE2]>;
2915 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2916 def : Pat<(vector_shuffle (bc_v4i32 (memopv4f32 addr:$src1)), (undef),
2917 SHUFP_unary_shuffle_mask:$sm),
2918 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2919 Requires<[HasSSE2]>;
2921 // Special binary v4i32 shuffle cases with SHUFPS.
2922 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (v4i32 VR128:$src2),
2923 PSHUFD_binary_shuffle_mask:$sm)),
2924 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2925 Requires<[HasSSE2]>;
2926 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
2927 (bc_v4i32 (memopv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm)),
2928 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2929 Requires<[HasSSE2]>;
2930 // Special binary v2i64 shuffle cases using SHUFPDrri.
2931 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2932 SHUFP_shuffle_mask:$sm)),
2933 (SHUFPDrri VR128:$src1, VR128:$src2, SHUFP_shuffle_mask:$sm)>,
2934 Requires<[HasSSE2]>;
2935 // Special unary SHUFPDrri case.
2936 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (undef),
2937 SHUFP_unary_shuffle_mask:$sm)),
2938 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2939 Requires<[HasSSE2]>;
2941 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2942 let AddedComplexity = 15 in {
2943 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2944 UNPCKL_v_undef_shuffle_mask:$sm)),
2945 (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
2946 Requires<[OptForSpeed, HasSSE2]>;
2947 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2948 UNPCKL_v_undef_shuffle_mask:$sm)),
2949 (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
2950 Requires<[OptForSpeed, HasSSE2]>;
2952 let AddedComplexity = 10 in {
2953 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2954 UNPCKL_v_undef_shuffle_mask)),
2955 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2956 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2957 UNPCKL_v_undef_shuffle_mask)),
2958 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2959 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2960 UNPCKL_v_undef_shuffle_mask)),
2961 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2962 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2963 UNPCKL_v_undef_shuffle_mask)),
2964 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2967 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2968 let AddedComplexity = 15 in {
2969 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2970 UNPCKH_v_undef_shuffle_mask:$sm)),
2971 (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
2972 Requires<[OptForSpeed, HasSSE2]>;
2973 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2974 UNPCKH_v_undef_shuffle_mask:$sm)),
2975 (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
2976 Requires<[OptForSpeed, HasSSE2]>;
2978 let AddedComplexity = 10 in {
2979 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2980 UNPCKH_v_undef_shuffle_mask)),
2981 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2982 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2983 UNPCKH_v_undef_shuffle_mask)),
2984 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2985 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2986 UNPCKH_v_undef_shuffle_mask)),
2987 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2988 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2989 UNPCKH_v_undef_shuffle_mask)),
2990 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2993 let AddedComplexity = 20 in {
2994 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2995 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2996 MOVHP_shuffle_mask)),
2997 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2999 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3000 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
3001 MOVHLPS_shuffle_mask)),
3002 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3004 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3005 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
3006 MOVHLPS_v_undef_shuffle_mask)),
3007 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3008 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
3009 MOVHLPS_v_undef_shuffle_mask)),
3010 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3013 let AddedComplexity = 20 in {
3014 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3015 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
3016 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memop addr:$src2),
3017 MOVLP_shuffle_mask)),
3018 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
3019 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memop addr:$src2),
3020 MOVLP_shuffle_mask)),
3021 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3022 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memop addr:$src2),
3023 MOVHP_shuffle_mask)),
3024 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
3025 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memop addr:$src2),
3026 MOVHP_shuffle_mask)),
3027 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3029 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
3030 (bc_v4i32 (memopv2i64 addr:$src2)),
3031 MOVLP_shuffle_mask)),
3032 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3033 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memop addr:$src2),
3034 MOVLP_shuffle_mask)),
3035 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3036 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
3037 (bc_v4i32 (memopv2i64 addr:$src2)),
3038 MOVHP_shuffle_mask)),
3039 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
3040 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memop addr:$src2),
3041 MOVHP_shuffle_mask)),
3042 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3045 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3046 // (store (vector_shuffle (load addr), v2, <0, 1, 4, 5>), addr) using MOVHPS
3047 def : Pat<(store (v4f32 (vector_shuffle (memop addr:$src1), VR128:$src2,
3048 MOVLP_shuffle_mask)), addr:$src1),
3049 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3050 def : Pat<(store (v2f64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3051 MOVLP_shuffle_mask)), addr:$src1),
3052 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3053 def : Pat<(store (v4f32 (vector_shuffle (memop addr:$src1), VR128:$src2,
3054 MOVHP_shuffle_mask)), addr:$src1),
3055 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3056 def : Pat<(store (v2f64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3057 MOVHP_shuffle_mask)), addr:$src1),
3058 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3060 def : Pat<(store (v4i32 (vector_shuffle
3061 (bc_v4i32 (memopv2i64 addr:$src1)), VR128:$src2,
3062 MOVLP_shuffle_mask)), addr:$src1),
3063 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3064 def : Pat<(store (v2i64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3065 MOVLP_shuffle_mask)), addr:$src1),
3066 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3067 def : Pat<(store (v4i32 (vector_shuffle
3068 (bc_v4i32 (memopv2i64 addr:$src1)), VR128:$src2,
3069 MOVHP_shuffle_mask)), addr:$src1),
3070 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3071 def : Pat<(store (v2i64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3072 MOVHP_shuffle_mask)), addr:$src1),
3073 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3076 let AddedComplexity = 15 in {
3077 // Setting the lowest element in the vector.
3078 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
3079 MOVL_shuffle_mask)),
3080 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3081 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
3082 MOVL_shuffle_mask)),
3083 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3085 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
3086 def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
3087 MOVLP_shuffle_mask)),
3088 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3089 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
3090 MOVLP_shuffle_mask)),
3091 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3094 // Set lowest element and zero upper elements.
3095 let AddedComplexity = 15 in
3096 def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc, VR128:$src,
3097 MOVL_shuffle_mask)),
3098 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3099 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3100 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3102 // Some special case pandn patterns.
3103 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3105 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3106 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3108 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3109 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3111 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3113 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3114 (memop addr:$src2))),
3115 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3116 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3117 (memop addr:$src2))),
3118 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3119 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3120 (memop addr:$src2))),
3121 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3123 // vector -> vector casts
3124 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3125 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3126 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3127 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3128 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3129 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3130 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3131 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3133 // Use movaps / movups for SSE integer load / store (one byte shorter).
3134 def : Pat<(alignedloadv4i32 addr:$src),
3135 (MOVAPSrm addr:$src)>, Requires<[HasSSE1]>;
3136 def : Pat<(loadv4i32 addr:$src),
3137 (MOVUPSrm addr:$src)>, Requires<[HasSSE1]>;
3138 def : Pat<(alignedloadv2i64 addr:$src),
3139 (MOVAPSrm addr:$src)>, Requires<[HasSSE2]>;
3140 def : Pat<(loadv2i64 addr:$src),
3141 (MOVUPSrm addr:$src)>, Requires<[HasSSE2]>;
3143 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3144 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3145 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3146 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3147 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3148 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3149 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3150 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3151 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3152 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3153 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3154 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3155 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3156 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3157 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3158 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3160 //===----------------------------------------------------------------------===//
3161 // SSE4.1 Instructions
3162 //===----------------------------------------------------------------------===//
3164 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3167 Intrinsic V2F64Int> {
3168 // Intrinsic operation, reg.
3169 // Vector intrinsic operation, reg
3170 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3171 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3172 !strconcat(OpcodeStr,
3173 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3174 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3177 // Vector intrinsic operation, mem
3178 def PSm_Int : SS4AIi8<opcps, MRMSrcMem,
3179 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3180 !strconcat(OpcodeStr,
3181 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3183 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3186 // Vector intrinsic operation, reg
3187 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3188 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3189 !strconcat(OpcodeStr,
3190 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3191 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3194 // Vector intrinsic operation, mem
3195 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3196 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3197 !strconcat(OpcodeStr,
3198 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3200 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3204 let Constraints = "$src1 = $dst" in {
3205 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3209 // Intrinsic operation, reg.
3210 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3212 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3213 !strconcat(OpcodeStr,
3214 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3216 (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3219 // Intrinsic operation, mem.
3220 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3222 (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3223 !strconcat(OpcodeStr,
3224 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3226 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
3229 // Intrinsic operation, reg.
3230 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3232 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3233 !strconcat(OpcodeStr,
3234 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3236 (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3239 // Intrinsic operation, mem.
3240 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3242 (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
3243 !strconcat(OpcodeStr,
3244 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3246 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
3251 // FP round - roundss, roundps, roundsd, roundpd
3252 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
3253 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
3254 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
3255 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
3257 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3258 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3259 Intrinsic IntId128> {
3260 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3262 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3263 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3264 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3266 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3269 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3272 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3273 int_x86_sse41_phminposuw>;
3275 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3276 let Constraints = "$src1 = $dst" in {
3277 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3278 Intrinsic IntId128, bit Commutable = 0> {
3279 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3280 (ins VR128:$src1, VR128:$src2),
3281 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3282 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3284 let isCommutable = Commutable;
3286 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3287 (ins VR128:$src1, i128mem:$src2),
3288 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3290 (IntId128 VR128:$src1,
3291 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3295 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3296 int_x86_sse41_pcmpeqq, 1>;
3297 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3298 int_x86_sse41_packusdw, 0>;
3299 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3300 int_x86_sse41_pminsb, 1>;
3301 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3302 int_x86_sse41_pminsd, 1>;
3303 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3304 int_x86_sse41_pminud, 1>;
3305 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3306 int_x86_sse41_pminuw, 1>;
3307 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3308 int_x86_sse41_pmaxsb, 1>;
3309 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3310 int_x86_sse41_pmaxsd, 1>;
3311 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3312 int_x86_sse41_pmaxud, 1>;
3313 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3314 int_x86_sse41_pmaxuw, 1>;
3316 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3317 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3318 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3319 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3322 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3323 let Constraints = "$src1 = $dst" in {
3324 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3325 SDNode OpNode, Intrinsic IntId128,
3326 bit Commutable = 0> {
3327 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3328 (ins VR128:$src1, VR128:$src2),
3329 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3330 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3331 VR128:$src2))]>, OpSize {
3332 let isCommutable = Commutable;
3334 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3335 (ins VR128:$src1, VR128:$src2),
3336 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3337 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3339 let isCommutable = Commutable;
3341 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3342 (ins VR128:$src1, i128mem:$src2),
3343 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3345 (OpNode VR128:$src1, (memop addr:$src2)))]>, OpSize;
3346 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3347 (ins VR128:$src1, i128mem:$src2),
3348 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3350 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3354 defm PMULLD : SS41I_binop_patint<0x40, "pmulld", v4i32, mul,
3355 int_x86_sse41_pmulld, 1>;
3356 defm PMULDQ : SS41I_binop_patint<0x28, "pmuldq", v2i64, mul,
3357 int_x86_sse41_pmuldq, 1>;
3360 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3361 let Constraints = "$src1 = $dst" in {
3362 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3363 Intrinsic IntId128, bit Commutable = 0> {
3364 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3365 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3366 !strconcat(OpcodeStr,
3367 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3369 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3371 let isCommutable = Commutable;
3373 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3374 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3375 !strconcat(OpcodeStr,
3376 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3378 (IntId128 VR128:$src1,
3379 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3384 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3385 int_x86_sse41_blendps, 0>;
3386 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3387 int_x86_sse41_blendpd, 0>;
3388 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3389 int_x86_sse41_pblendw, 0>;
3390 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3391 int_x86_sse41_dpps, 1>;
3392 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3393 int_x86_sse41_dppd, 1>;
3394 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3395 int_x86_sse41_mpsadbw, 1>;
3398 /// SS41I_ternary_int - SSE 4.1 ternary operator
3399 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3400 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3401 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3402 (ins VR128:$src1, VR128:$src2),
3403 !strconcat(OpcodeStr,
3404 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3405 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3408 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3409 (ins VR128:$src1, i128mem:$src2),
3410 !strconcat(OpcodeStr,
3411 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3414 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3418 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3419 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3420 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3423 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3424 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3425 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3426 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3428 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3429 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3431 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3435 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3436 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3437 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3438 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3439 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3440 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3442 // Common patterns involving scalar load.
3443 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3444 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3445 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3446 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3448 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3449 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3450 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3451 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3453 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3454 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3455 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3456 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3458 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3459 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3460 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3461 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3463 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3464 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3465 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3466 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3468 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3469 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3470 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3471 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3474 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3475 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3476 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3477 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3479 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3480 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3482 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3486 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3487 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3488 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3489 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3491 // Common patterns involving scalar load
3492 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3493 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3494 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3495 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3497 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3498 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3499 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3500 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3503 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3504 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3505 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3506 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3508 // Expecting a i16 load any extended to i32 value.
3509 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3510 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3511 [(set VR128:$dst, (IntId (bitconvert
3512 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3516 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3517 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovsxbq", int_x86_sse41_pmovzxbq>;
3519 // Common patterns involving scalar load
3520 def : Pat<(int_x86_sse41_pmovsxbq
3521 (bitconvert (v4i32 (X86vzmovl
3522 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3523 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3525 def : Pat<(int_x86_sse41_pmovzxbq
3526 (bitconvert (v4i32 (X86vzmovl
3527 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3528 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3531 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3532 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3533 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3534 (ins VR128:$src1, i32i8imm:$src2),
3535 !strconcat(OpcodeStr,
3536 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3537 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3539 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3540 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3541 !strconcat(OpcodeStr,
3542 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3545 // There's an AssertZext in the way of writing the store pattern
3546 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3549 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3552 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3553 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3554 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3555 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3556 !strconcat(OpcodeStr,
3557 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3560 // There's an AssertZext in the way of writing the store pattern
3561 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3564 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3567 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3568 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3569 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3570 (ins VR128:$src1, i32i8imm:$src2),
3571 !strconcat(OpcodeStr,
3572 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3574 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3575 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3576 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3577 !strconcat(OpcodeStr,
3578 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3579 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3580 addr:$dst)]>, OpSize;
3583 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3586 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3588 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3589 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3590 (ins VR128:$src1, i32i8imm:$src2),
3591 !strconcat(OpcodeStr,
3592 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3594 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3596 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3597 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3598 !strconcat(OpcodeStr,
3599 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3600 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3601 addr:$dst)]>, OpSize;
3604 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3606 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3607 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3610 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3611 Requires<[HasSSE41]>;
3613 let Constraints = "$src1 = $dst" in {
3614 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3615 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3616 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3617 !strconcat(OpcodeStr,
3618 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3620 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3621 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3622 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3623 !strconcat(OpcodeStr,
3624 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3626 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3627 imm:$src3))]>, OpSize;
3631 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3633 let Constraints = "$src1 = $dst" in {
3634 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3635 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3636 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3637 !strconcat(OpcodeStr,
3638 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3640 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3642 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3643 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3644 !strconcat(OpcodeStr,
3645 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3647 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3648 imm:$src3)))]>, OpSize;
3652 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3654 let Constraints = "$src1 = $dst" in {
3655 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3656 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3657 (ins VR128:$src1, FR32:$src2, i32i8imm:$src3),
3658 !strconcat(OpcodeStr,
3659 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3661 (X86insrtps VR128:$src1, FR32:$src2, imm:$src3))]>, OpSize;
3662 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3663 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3664 !strconcat(OpcodeStr,
3665 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3667 (X86insrtps VR128:$src1, (loadf32 addr:$src2),
3668 imm:$src3))]>, OpSize;
3672 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3674 let Defs = [EFLAGS] in {
3675 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3676 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3677 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3678 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3681 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3682 "movntdqa\t{$src, $dst|$dst, $src}",
3683 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
3685 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3686 let Constraints = "$src1 = $dst" in {
3687 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3688 Intrinsic IntId128, bit Commutable = 0> {
3689 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3690 (ins VR128:$src1, VR128:$src2),
3691 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3692 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3694 let isCommutable = Commutable;
3696 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3697 (ins VR128:$src1, i128mem:$src2),
3698 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3700 (IntId128 VR128:$src1,
3701 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3705 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3707 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3708 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3709 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3710 (PCMPGTQrm VR128:$src1, addr:$src2)>;