1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 let isCommutable = 1 in
85 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
90 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
97 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
98 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
99 string asm, string SSEVer, string FPSizeStr,
100 X86MemOperand x86memop, PatFrag mem_frag,
101 Domain d, bit Is2Addr = 1> {
102 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
104 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
105 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
106 [(set RC:$dst, (!cast<Intrinsic>(
107 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
108 RC:$src1, RC:$src2))], d>;
109 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
111 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
113 [(set RC:$dst, (!cast<Intrinsic>(
114 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
115 RC:$src1, (mem_frag addr:$src2)))], d>;
118 //===----------------------------------------------------------------------===//
119 // SSE 1 & 2 - Move Instructions
120 //===----------------------------------------------------------------------===//
122 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
123 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
124 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
126 // Loading from memory automatically zeroing upper bits.
127 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
128 PatFrag mem_pat, string OpcodeStr> :
129 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
130 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
131 [(set RC:$dst, (mem_pat addr:$src))]>;
133 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
134 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
135 // is used instead. Register-to-register movss/movsd is not modeled as an
136 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
137 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
138 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
139 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
140 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
141 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
143 let canFoldAsLoad = 1, isReMaterializable = 1 in {
144 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
146 let AddedComplexity = 20 in
147 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
150 let Constraints = "$src1 = $dst" in {
151 def MOVSSrr : sse12_move_rr<FR32, v4f32,
152 "movss\t{$src2, $dst|$dst, $src2}">, XS;
153 def MOVSDrr : sse12_move_rr<FR64, v2f64,
154 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
157 let canFoldAsLoad = 1, isReMaterializable = 1 in {
158 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
160 let AddedComplexity = 20 in
161 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
164 let AddedComplexity = 15 in {
165 // Extract the low 32-bit value from one vector and insert it into another.
166 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
167 (MOVSSrr (v4f32 VR128:$src1),
168 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
169 // Extract the low 64-bit value from one vector and insert it into another.
170 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
171 (MOVSDrr (v2f64 VR128:$src1),
172 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
175 // Implicitly promote a 32-bit scalar to a vector.
176 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
177 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
178 // Implicitly promote a 64-bit scalar to a vector.
179 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
180 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
181 // Implicitly promote a 32-bit scalar to a vector.
182 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
183 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
184 // Implicitly promote a 64-bit scalar to a vector.
185 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
186 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
188 let AddedComplexity = 20 in {
189 // MOVSSrm zeros the high parts of the register; represent this
190 // with SUBREG_TO_REG.
191 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
192 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
193 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
194 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
195 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
196 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
197 // MOVSDrm zeros the high parts of the register; represent this
198 // with SUBREG_TO_REG.
199 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
200 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
201 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
202 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
203 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
204 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
205 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
206 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
207 def : Pat<(v2f64 (X86vzload addr:$src)),
208 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
211 // Store scalar value to memory.
212 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
213 "movss\t{$src, $dst|$dst, $src}",
214 [(store FR32:$src, addr:$dst)]>;
215 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
216 "movsd\t{$src, $dst|$dst, $src}",
217 [(store FR64:$src, addr:$dst)]>;
219 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
220 "movss\t{$src, $dst|$dst, $src}",
221 [(store FR32:$src, addr:$dst)]>, XS, VEX;
222 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
223 "movsd\t{$src, $dst|$dst, $src}",
224 [(store FR64:$src, addr:$dst)]>, XD, VEX;
226 // Extract and store.
227 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
230 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
231 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
234 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
236 // Move Aligned/Unaligned floating point values
237 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
238 X86MemOperand x86memop, PatFrag ld_frag,
239 string asm, Domain d,
240 bit IsReMaterializable = 1> {
241 let neverHasSideEffects = 1 in
242 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
243 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
244 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
245 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
246 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
247 [(set RC:$dst, (ld_frag addr:$src))], d>;
250 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
251 "movaps", SSEPackedSingle>, VEX;
252 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
253 "movapd", SSEPackedDouble>, OpSize, VEX;
254 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
255 "movups", SSEPackedSingle>, VEX;
256 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
257 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
259 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
260 "movaps", SSEPackedSingle>, VEX;
261 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
262 "movapd", SSEPackedDouble>, OpSize, VEX;
263 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
264 "movups", SSEPackedSingle>, VEX;
265 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
266 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
267 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
268 "movaps", SSEPackedSingle>, TB;
269 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
270 "movapd", SSEPackedDouble>, TB, OpSize;
271 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
272 "movups", SSEPackedSingle>, TB;
273 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
274 "movupd", SSEPackedDouble, 0>, TB, OpSize;
276 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
277 "movaps\t{$src, $dst|$dst, $src}",
278 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
279 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
280 "movapd\t{$src, $dst|$dst, $src}",
281 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
282 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
283 "movups\t{$src, $dst|$dst, $src}",
284 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
285 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
286 "movupd\t{$src, $dst|$dst, $src}",
287 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
288 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
289 "movaps\t{$src, $dst|$dst, $src}",
290 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
291 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
292 "movapd\t{$src, $dst|$dst, $src}",
293 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
294 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
295 "movups\t{$src, $dst|$dst, $src}",
296 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
297 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
298 "movupd\t{$src, $dst|$dst, $src}",
299 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
301 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
302 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
303 (VMOVUPSYmr addr:$dst, VR256:$src)>;
305 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
306 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
307 (VMOVUPDYmr addr:$dst, VR256:$src)>;
309 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
310 "movaps\t{$src, $dst|$dst, $src}",
311 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
312 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
313 "movapd\t{$src, $dst|$dst, $src}",
314 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
315 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
316 "movups\t{$src, $dst|$dst, $src}",
317 [(store (v4f32 VR128:$src), addr:$dst)]>;
318 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
319 "movupd\t{$src, $dst|$dst, $src}",
320 [(store (v2f64 VR128:$src), addr:$dst)]>;
322 // Intrinsic forms of MOVUPS/D load and store
323 def VMOVUPSmr_Int : VPSI<0x11, MRMDestMem, (outs),
324 (ins f128mem:$dst, VR128:$src),
325 "movups\t{$src, $dst|$dst, $src}",
326 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX;
327 def VMOVUPDmr_Int : VPDI<0x11, MRMDestMem, (outs),
328 (ins f128mem:$dst, VR128:$src),
329 "movupd\t{$src, $dst|$dst, $src}",
330 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX;
332 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
333 "movups\t{$src, $dst|$dst, $src}",
334 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
335 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
336 "movupd\t{$src, $dst|$dst, $src}",
337 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
339 // Move Low/High packed floating point values
340 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
341 PatFrag mov_frag, string base_opc,
343 def PSrm : PI<opc, MRMSrcMem,
344 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
345 !strconcat(base_opc, "s", asm_opr),
348 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
349 SSEPackedSingle>, TB;
351 def PDrm : PI<opc, MRMSrcMem,
352 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
353 !strconcat(base_opc, "d", asm_opr),
354 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
355 (scalar_to_vector (loadf64 addr:$src2)))))],
356 SSEPackedDouble>, TB, OpSize;
359 let AddedComplexity = 20 in {
360 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
361 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
362 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
363 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
365 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
366 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
367 "\t{$src2, $dst|$dst, $src2}">;
368 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
369 "\t{$src2, $dst|$dst, $src2}">;
372 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
373 "movlps\t{$src, $dst|$dst, $src}",
374 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
375 (iPTR 0))), addr:$dst)]>, VEX;
376 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
377 "movlpd\t{$src, $dst|$dst, $src}",
378 [(store (f64 (vector_extract (v2f64 VR128:$src),
379 (iPTR 0))), addr:$dst)]>, VEX;
380 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
381 "movlps\t{$src, $dst|$dst, $src}",
382 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
383 (iPTR 0))), addr:$dst)]>;
384 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
385 "movlpd\t{$src, $dst|$dst, $src}",
386 [(store (f64 (vector_extract (v2f64 VR128:$src),
387 (iPTR 0))), addr:$dst)]>;
389 // v2f64 extract element 1 is always custom lowered to unpack high to low
390 // and extract element 0 so the non-store version isn't too horrible.
391 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
392 "movhps\t{$src, $dst|$dst, $src}",
393 [(store (f64 (vector_extract
394 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
395 (undef)), (iPTR 0))), addr:$dst)]>,
397 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
398 "movhpd\t{$src, $dst|$dst, $src}",
399 [(store (f64 (vector_extract
400 (v2f64 (unpckh VR128:$src, (undef))),
401 (iPTR 0))), addr:$dst)]>,
403 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
404 "movhps\t{$src, $dst|$dst, $src}",
405 [(store (f64 (vector_extract
406 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
407 (undef)), (iPTR 0))), addr:$dst)]>;
408 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
409 "movhpd\t{$src, $dst|$dst, $src}",
410 [(store (f64 (vector_extract
411 (v2f64 (unpckh VR128:$src, (undef))),
412 (iPTR 0))), addr:$dst)]>;
414 let AddedComplexity = 20 in {
415 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
416 (ins VR128:$src1, VR128:$src2),
417 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
419 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
421 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
422 (ins VR128:$src1, VR128:$src2),
423 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
425 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
428 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
429 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
430 (ins VR128:$src1, VR128:$src2),
431 "movlhps\t{$src2, $dst|$dst, $src2}",
433 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
434 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
435 (ins VR128:$src1, VR128:$src2),
436 "movhlps\t{$src2, $dst|$dst, $src2}",
438 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
441 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
442 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
443 let AddedComplexity = 20 in {
444 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
445 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
446 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
447 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
450 //===----------------------------------------------------------------------===//
451 // SSE 1 & 2 - Conversion Instructions
452 //===----------------------------------------------------------------------===//
454 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
455 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
457 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
458 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
459 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
460 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
463 multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
464 X86MemOperand x86memop, string asm> {
465 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
467 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
471 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
472 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
473 string asm, Domain d> {
474 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
475 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
476 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
477 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
480 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
481 X86MemOperand x86memop, string asm> {
482 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
483 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
484 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
485 (ins DstRC:$src1, x86memop:$src),
486 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
489 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
490 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
491 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
492 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
494 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
495 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
496 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
497 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
500 // The assembler can recognize rr 64-bit instructions by seeing a rxx
501 // register, but the same isn't true when only using memory operands,
502 // provide other assembly "l" and "q" forms to address this explicitly
503 // where appropriate to do so.
504 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
506 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
508 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
510 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
512 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
515 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
516 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
517 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
518 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
519 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
520 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
521 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
522 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
523 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
524 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
525 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
526 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
527 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
528 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
529 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
530 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
532 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
533 // and/or XMM operand(s).
535 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
536 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
538 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
539 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
540 [(set DstRC:$dst, (Int SrcRC:$src))]>;
541 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
542 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
543 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
546 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
547 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
548 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
549 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
551 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
552 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
553 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
554 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
555 (ins DstRC:$src1, x86memop:$src2),
557 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
558 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
559 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
562 defm Int_VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
563 f32mem, load, "cvtss2si">, XS, VEX;
564 defm Int_VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
565 int_x86_sse_cvtss2si64, f32mem, load, "cvtss2si">,
567 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
568 f128mem, load, "cvtsd2si">, XD, VEX;
569 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
570 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
573 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
574 // Get rid of this hack or rename the intrinsics, there are several
575 // intructions that only match with the intrinsic form, why create duplicates
576 // to let them be recognized by the assembler?
577 defm VCVTSD2SI_alt : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
578 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
579 defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
580 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
581 defm Int_CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
582 f32mem, load, "cvtss2si">, XS;
583 defm Int_CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
584 f32mem, load, "cvtss2si{q}">, XS, REX_W;
585 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
586 f128mem, load, "cvtsd2si{l}">, XD;
587 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
588 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
591 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
592 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
593 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
594 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
596 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
597 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
598 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
599 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
602 let Constraints = "$src1 = $dst" in {
603 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
604 int_x86_sse_cvtsi2ss, i32mem, loadi32,
606 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
607 int_x86_sse_cvtsi642ss, i64mem, loadi64,
608 "cvtsi2ss{q}">, XS, REX_W;
609 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
610 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
612 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
613 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
614 "cvtsi2sd">, XD, REX_W;
619 // Aliases for intrinsics
620 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
621 f32mem, load, "cvttss2si">, XS, VEX;
622 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
623 int_x86_sse_cvttss2si64, f32mem, load,
624 "cvttss2si">, XS, VEX, VEX_W;
625 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
626 f128mem, load, "cvttsd2si">, XD, VEX;
627 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
628 int_x86_sse2_cvttsd2si64, f128mem, load,
629 "cvttsd2si">, XD, VEX, VEX_W;
630 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
631 f32mem, load, "cvttss2si">, XS;
632 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
633 int_x86_sse_cvttss2si64, f32mem, load,
634 "cvttss2si{q}">, XS, REX_W;
635 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
636 f128mem, load, "cvttsd2si">, XD;
637 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
638 int_x86_sse2_cvttsd2si64, f128mem, load,
639 "cvttsd2si{q}">, XD, REX_W;
641 let Pattern = []<dag> in {
642 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
643 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
644 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
645 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
647 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
648 "cvtdq2ps\t{$src, $dst|$dst, $src}",
649 SSEPackedSingle>, TB, VEX;
650 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
651 "cvtdq2ps\t{$src, $dst|$dst, $src}",
652 SSEPackedSingle>, TB, VEX;
654 let Pattern = []<dag> in {
655 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
656 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
657 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
658 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
659 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
660 "cvtdq2ps\t{$src, $dst|$dst, $src}",
661 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
666 // Convert scalar double to scalar single
667 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
668 (ins FR64:$src1, FR64:$src2),
669 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
671 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
672 (ins FR64:$src1, f64mem:$src2),
673 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
674 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
675 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
678 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
679 "cvtsd2ss\t{$src, $dst|$dst, $src}",
680 [(set FR32:$dst, (fround FR64:$src))]>;
681 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
682 "cvtsd2ss\t{$src, $dst|$dst, $src}",
683 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
684 Requires<[HasSSE2, OptForSize]>;
686 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
687 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
689 let Constraints = "$src1 = $dst" in
690 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
691 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
693 // Convert scalar single to scalar double
694 // SSE2 instructions with XS prefix
695 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
696 (ins FR32:$src1, FR32:$src2),
697 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
698 []>, XS, Requires<[HasAVX]>, VEX_4V;
699 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
700 (ins FR32:$src1, f32mem:$src2),
701 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
702 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
703 def : Pat<(f64 (fextend FR32:$src)), (VCVTSS2SDrr FR32:$src, FR32:$src)>,
706 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
707 "cvtss2sd\t{$src, $dst|$dst, $src}",
708 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
710 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
711 "cvtss2sd\t{$src, $dst|$dst, $src}",
712 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
713 Requires<[HasSSE2, OptForSize]>;
715 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
716 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
717 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
718 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
719 VR128:$src2))]>, XS, VEX_4V,
721 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
722 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
723 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
724 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
725 (load addr:$src2)))]>, XS, VEX_4V,
727 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
728 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
729 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
730 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
731 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
734 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
735 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
736 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
737 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
738 (load addr:$src2)))]>, XS,
742 def : Pat<(extloadf32 addr:$src),
743 (CVTSS2SDrr (MOVSSrm addr:$src))>,
744 Requires<[HasSSE2, OptForSpeed]>;
746 // Convert doubleword to packed single/double fp
747 // SSE2 instructions without OpSize prefix
748 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
749 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
750 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
751 TB, VEX, Requires<[HasAVX]>;
752 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
753 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
754 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
755 (bitconvert (memopv2i64 addr:$src))))]>,
756 TB, VEX, Requires<[HasAVX]>;
757 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
758 "cvtdq2ps\t{$src, $dst|$dst, $src}",
759 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
760 TB, Requires<[HasSSE2]>;
761 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
762 "cvtdq2ps\t{$src, $dst|$dst, $src}",
763 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
764 (bitconvert (memopv2i64 addr:$src))))]>,
765 TB, Requires<[HasSSE2]>;
767 // FIXME: why the non-intrinsic version is described as SSE3?
768 // SSE2 instructions with XS prefix
769 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
770 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
771 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
772 XS, VEX, Requires<[HasAVX]>;
773 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
774 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
775 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
776 (bitconvert (memopv2i64 addr:$src))))]>,
777 XS, VEX, Requires<[HasAVX]>;
778 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
779 "cvtdq2pd\t{$src, $dst|$dst, $src}",
780 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
781 XS, Requires<[HasSSE2]>;
782 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
783 "cvtdq2pd\t{$src, $dst|$dst, $src}",
784 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
785 (bitconvert (memopv2i64 addr:$src))))]>,
786 XS, Requires<[HasSSE2]>;
789 // Convert packed single/double fp to doubleword
790 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
791 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
792 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
793 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
794 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
795 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
796 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
797 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
798 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
799 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
800 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
801 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
803 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
804 "cvtps2dq\t{$src, $dst|$dst, $src}",
805 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
807 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
809 "cvtps2dq\t{$src, $dst|$dst, $src}",
810 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
811 (memop addr:$src)))]>, VEX;
812 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
813 "cvtps2dq\t{$src, $dst|$dst, $src}",
814 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
815 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
816 "cvtps2dq\t{$src, $dst|$dst, $src}",
817 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
818 (memop addr:$src)))]>;
820 // SSE2 packed instructions with XD prefix
821 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
822 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
823 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
824 XD, VEX, Requires<[HasAVX]>;
825 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
826 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
827 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
828 (memop addr:$src)))]>,
829 XD, VEX, Requires<[HasAVX]>;
830 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
831 "cvtpd2dq\t{$src, $dst|$dst, $src}",
832 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
833 XD, Requires<[HasSSE2]>;
834 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
835 "cvtpd2dq\t{$src, $dst|$dst, $src}",
836 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
837 (memop addr:$src)))]>,
838 XD, Requires<[HasSSE2]>;
841 // Convert with truncation packed single/double fp to doubleword
842 // SSE2 packed instructions with XS prefix
843 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
844 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
845 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
846 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
847 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
848 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
849 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
850 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
851 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
852 "cvttps2dq\t{$src, $dst|$dst, $src}",
854 (int_x86_sse2_cvttps2dq VR128:$src))]>;
855 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
856 "cvttps2dq\t{$src, $dst|$dst, $src}",
858 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
861 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
862 "vcvttps2dq\t{$src, $dst|$dst, $src}",
864 (int_x86_sse2_cvttps2dq VR128:$src))]>,
865 XS, VEX, Requires<[HasAVX]>;
866 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
867 "vcvttps2dq\t{$src, $dst|$dst, $src}",
868 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
869 (memop addr:$src)))]>,
870 XS, VEX, Requires<[HasAVX]>;
872 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
874 "cvttpd2dq\t{$src, $dst|$dst, $src}",
875 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
877 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
879 "cvttpd2dq\t{$src, $dst|$dst, $src}",
880 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
881 (memop addr:$src)))]>, VEX;
882 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
883 "cvttpd2dq\t{$src, $dst|$dst, $src}",
884 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
885 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
886 "cvttpd2dq\t{$src, $dst|$dst, $src}",
887 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
888 (memop addr:$src)))]>;
890 // The assembler can recognize rr 256-bit instructions by seeing a ymm
891 // register, but the same isn't true when using memory operands instead.
892 // Provide other assembly rr and rm forms to address this explicitly.
893 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
894 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
895 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
896 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
899 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
900 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
901 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
902 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
905 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
906 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
907 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
908 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
910 // Convert packed single to packed double
911 let Predicates = [HasAVX] in {
912 // SSE2 instructions without OpSize prefix
913 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
914 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
915 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
916 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
917 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
918 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
919 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
920 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
922 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
923 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
924 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
925 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
927 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
928 "vcvtps2pd\t{$src, $dst|$dst, $src}",
929 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
930 VEX, Requires<[HasAVX]>;
931 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
932 "vcvtps2pd\t{$src, $dst|$dst, $src}",
933 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
934 (load addr:$src)))]>,
935 VEX, Requires<[HasAVX]>;
936 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
937 "cvtps2pd\t{$src, $dst|$dst, $src}",
938 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
939 TB, Requires<[HasSSE2]>;
940 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
941 "cvtps2pd\t{$src, $dst|$dst, $src}",
942 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
943 (load addr:$src)))]>,
944 TB, Requires<[HasSSE2]>;
946 // Convert packed double to packed single
947 // The assembler can recognize rr 256-bit instructions by seeing a ymm
948 // register, but the same isn't true when using memory operands instead.
949 // Provide other assembly rr and rm forms to address this explicitly.
950 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
951 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
952 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
953 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
956 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
957 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
958 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
959 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
962 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
963 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
964 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
965 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
966 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
967 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
968 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
969 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
972 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
973 "cvtpd2ps\t{$src, $dst|$dst, $src}",
974 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
975 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
977 "cvtpd2ps\t{$src, $dst|$dst, $src}",
978 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
979 (memop addr:$src)))]>;
980 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
981 "cvtpd2ps\t{$src, $dst|$dst, $src}",
982 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
983 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
984 "cvtpd2ps\t{$src, $dst|$dst, $src}",
985 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
986 (memop addr:$src)))]>;
988 // AVX 256-bit register conversion intrinsics
989 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
990 // whenever possible to avoid declaring two versions of each one.
991 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
992 (VCVTDQ2PSYrr VR256:$src)>;
993 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
994 (VCVTDQ2PSYrm addr:$src)>;
996 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
997 (VCVTPD2PSYrr VR256:$src)>;
998 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
999 (VCVTPD2PSYrm addr:$src)>;
1001 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1002 (VCVTPS2DQYrr VR256:$src)>;
1003 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1004 (VCVTPS2DQYrm addr:$src)>;
1006 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1007 (VCVTPS2PDYrr VR128:$src)>;
1008 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1009 (VCVTPS2PDYrm addr:$src)>;
1011 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1012 (VCVTTPD2DQYrr VR256:$src)>;
1013 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1014 (VCVTTPD2DQYrm addr:$src)>;
1016 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1017 (VCVTTPS2DQYrr VR256:$src)>;
1018 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1019 (VCVTTPS2DQYrm addr:$src)>;
1021 //===----------------------------------------------------------------------===//
1022 // SSE 1 & 2 - Compare Instructions
1023 //===----------------------------------------------------------------------===//
1025 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1026 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1027 string asm, string asm_alt> {
1028 let isAsmParserOnly = 1 in {
1029 def rr : SIi8<0xC2, MRMSrcReg,
1030 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1033 def rm : SIi8<0xC2, MRMSrcMem,
1034 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1038 // Accept explicit immediate argument form instead of comparison code.
1039 def rr_alt : SIi8<0xC2, MRMSrcReg,
1040 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1043 def rm_alt : SIi8<0xC2, MRMSrcMem,
1044 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1048 let neverHasSideEffects = 1 in {
1049 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1050 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1051 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1053 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1054 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1055 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1059 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1060 defm CMPSS : sse12_cmp_scalar<FR32, f32mem,
1061 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
1062 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}">, XS;
1063 defm CMPSD : sse12_cmp_scalar<FR64, f64mem,
1064 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1065 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}">, XD;
1068 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
1069 Intrinsic Int, string asm> {
1070 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1071 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1072 [(set VR128:$dst, (Int VR128:$src1,
1073 VR128:$src, imm:$cc))]>;
1074 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1075 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
1076 [(set VR128:$dst, (Int VR128:$src1,
1077 (load addr:$src), imm:$cc))]>;
1080 // Aliases to match intrinsics which expect XMM operand(s).
1081 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1082 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1084 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1085 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1087 let Constraints = "$src1 = $dst" in {
1088 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1089 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1090 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1091 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1095 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1096 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
1097 ValueType vt, X86MemOperand x86memop,
1098 PatFrag ld_frag, string OpcodeStr, Domain d> {
1099 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1100 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1101 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
1102 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
1103 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1104 [(set EFLAGS, (OpNode (vt RC:$src1),
1105 (ld_frag addr:$src2)))], d>;
1108 let Defs = [EFLAGS] in {
1109 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1110 "ucomiss", SSEPackedSingle>, VEX;
1111 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1112 "ucomisd", SSEPackedDouble>, OpSize, VEX;
1113 let Pattern = []<dag> in {
1114 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1115 "comiss", SSEPackedSingle>, VEX;
1116 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1117 "comisd", SSEPackedDouble>, OpSize, VEX;
1120 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1121 load, "ucomiss", SSEPackedSingle>, VEX;
1122 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1123 load, "ucomisd", SSEPackedDouble>, OpSize, VEX;
1125 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
1126 load, "comiss", SSEPackedSingle>, VEX;
1127 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
1128 load, "comisd", SSEPackedDouble>, OpSize, VEX;
1129 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1130 "ucomiss", SSEPackedSingle>, TB;
1131 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1132 "ucomisd", SSEPackedDouble>, TB, OpSize;
1134 let Pattern = []<dag> in {
1135 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1136 "comiss", SSEPackedSingle>, TB;
1137 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1138 "comisd", SSEPackedDouble>, TB, OpSize;
1141 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1142 load, "ucomiss", SSEPackedSingle>, TB;
1143 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1144 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
1146 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
1147 "comiss", SSEPackedSingle>, TB;
1148 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
1149 "comisd", SSEPackedDouble>, TB, OpSize;
1150 } // Defs = [EFLAGS]
1152 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
1153 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
1154 Intrinsic Int, string asm, string asm_alt,
1156 let isAsmParserOnly = 1 in {
1157 def rri : PIi8<0xC2, MRMSrcReg,
1158 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1159 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1160 def rmi : PIi8<0xC2, MRMSrcMem,
1161 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1162 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1165 // Accept explicit immediate argument form instead of comparison code.
1166 def rri_alt : PIi8<0xC2, MRMSrcReg,
1167 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1169 def rmi_alt : PIi8<0xC2, MRMSrcMem,
1170 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1174 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1175 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1176 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1177 SSEPackedSingle>, VEX_4V;
1178 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1179 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1180 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1181 SSEPackedDouble>, OpSize, VEX_4V;
1182 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
1183 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1184 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1185 SSEPackedSingle>, VEX_4V;
1186 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
1187 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1188 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1189 SSEPackedDouble>, OpSize, VEX_4V;
1190 let Constraints = "$src1 = $dst" in {
1191 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1192 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1193 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1194 SSEPackedSingle>, TB;
1195 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1196 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1197 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1198 SSEPackedDouble>, TB, OpSize;
1201 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1202 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1203 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1204 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1205 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1206 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1207 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1208 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1210 //===----------------------------------------------------------------------===//
1211 // SSE 1 & 2 - Shuffle Instructions
1212 //===----------------------------------------------------------------------===//
1214 /// sse12_shuffle - sse 1 & 2 shuffle instructions
1215 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
1216 ValueType vt, string asm, PatFrag mem_frag,
1217 Domain d, bit IsConvertibleToThreeAddress = 0> {
1218 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
1219 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
1220 [(set RC:$dst, (vt (shufp:$src3
1221 RC:$src1, (mem_frag addr:$src2))))], d>;
1222 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
1223 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
1224 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
1226 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
1229 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1230 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1231 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
1232 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
1233 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1234 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
1235 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1236 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1237 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1238 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
1239 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1240 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1242 let Constraints = "$src1 = $dst" in {
1243 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1244 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1245 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
1247 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1248 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1249 memopv2f64, SSEPackedDouble>, TB, OpSize;
1252 //===----------------------------------------------------------------------===//
1253 // SSE 1 & 2 - Unpack Instructions
1254 //===----------------------------------------------------------------------===//
1256 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
1257 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
1258 PatFrag mem_frag, RegisterClass RC,
1259 X86MemOperand x86memop, string asm,
1261 def rr : PI<opc, MRMSrcReg,
1262 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1264 (vt (OpNode RC:$src1, RC:$src2)))], d>;
1265 def rm : PI<opc, MRMSrcMem,
1266 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1268 (vt (OpNode RC:$src1,
1269 (mem_frag addr:$src2))))], d>;
1272 let AddedComplexity = 10 in {
1273 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1274 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1275 SSEPackedSingle>, VEX_4V;
1276 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1277 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1278 SSEPackedDouble>, OpSize, VEX_4V;
1279 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1280 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1281 SSEPackedSingle>, VEX_4V;
1282 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1283 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1284 SSEPackedDouble>, OpSize, VEX_4V;
1286 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
1287 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1288 SSEPackedSingle>, VEX_4V;
1289 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
1290 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1291 SSEPackedDouble>, OpSize, VEX_4V;
1292 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
1293 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1294 SSEPackedSingle>, VEX_4V;
1295 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
1296 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1297 SSEPackedDouble>, OpSize, VEX_4V;
1299 let Constraints = "$src1 = $dst" in {
1300 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1301 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1302 SSEPackedSingle>, TB;
1303 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1304 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1305 SSEPackedDouble>, TB, OpSize;
1306 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1307 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1308 SSEPackedSingle>, TB;
1309 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1310 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1311 SSEPackedDouble>, TB, OpSize;
1312 } // Constraints = "$src1 = $dst"
1313 } // AddedComplexity
1315 //===----------------------------------------------------------------------===//
1316 // SSE 1 & 2 - Extract Floating-Point Sign mask
1317 //===----------------------------------------------------------------------===//
1319 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
1320 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
1322 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
1323 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1324 [(set GR32:$dst, (Int RC:$src))], d>;
1325 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
1326 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
1330 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
1331 "movmskps", SSEPackedSingle>, VEX;
1332 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
1333 "movmskpd", SSEPackedDouble>, OpSize,
1335 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
1336 "movmskps", SSEPackedSingle>, VEX;
1337 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
1338 "movmskpd", SSEPackedDouble>, OpSize,
1340 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
1341 SSEPackedSingle>, TB;
1342 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
1343 SSEPackedDouble>, TB, OpSize;
1346 def MOVMSKPDrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1347 "movmskpd\t{$src, $dst|$dst, $src}",
1348 [(set GR32:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB, OpSize;
1349 def MOVMSKPDrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1350 "movmskpd\t{$src, $dst|$dst, $src}",
1351 [(set GR64:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB, OpSize;
1352 def MOVMSKPSrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
1353 "movmskps\t{$src, $dst|$dst, $src}",
1354 [(set GR32:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
1355 def MOVMSKPSrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1356 "movmskps\t{$src, $dst|$dst, $src}",
1357 [(set GR64:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
1360 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1361 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1362 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1363 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1365 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1366 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1367 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1368 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1371 //===----------------------------------------------------------------------===//
1372 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
1373 //===----------------------------------------------------------------------===//
1375 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
1376 // names that start with 'Fs'.
1378 // Alias instructions that map fld0 to pxor for sse.
1379 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1380 canFoldAsLoad = 1 in {
1381 // FIXME: Set encoding to pseudo!
1382 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1383 [(set FR32:$dst, fp32imm0)]>,
1384 Requires<[HasSSE1]>, TB, OpSize;
1385 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1386 [(set FR64:$dst, fpimm0)]>,
1387 Requires<[HasSSE2]>, TB, OpSize;
1388 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1389 [(set FR32:$dst, fp32imm0)]>,
1390 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1391 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1392 [(set FR64:$dst, fpimm0)]>,
1393 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1396 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1397 // bits are disregarded.
1398 let neverHasSideEffects = 1 in {
1399 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1400 "movaps\t{$src, $dst|$dst, $src}", []>;
1401 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1402 "movapd\t{$src, $dst|$dst, $src}", []>;
1405 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1406 // bits are disregarded.
1407 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1408 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1409 "movaps\t{$src, $dst|$dst, $src}",
1410 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
1411 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1412 "movapd\t{$src, $dst|$dst, $src}",
1413 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1416 //===----------------------------------------------------------------------===//
1417 // SSE 1 & 2 - Logical Instructions
1418 //===----------------------------------------------------------------------===//
1420 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
1422 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
1424 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
1425 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, VEX_4V;
1427 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
1428 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, OpSize, VEX_4V;
1430 let Constraints = "$src1 = $dst" in {
1431 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
1432 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
1434 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
1435 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
1439 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1440 let mayLoad = 0 in {
1441 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
1442 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
1443 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
1446 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
1447 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
1449 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
1451 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
1452 SDNode OpNode, int HasPat = 0,
1453 list<list<dag>> Pattern = []> {
1454 let Pattern = []<dag> in {
1455 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1456 !strconcat(OpcodeStr, "ps"), f128mem,
1457 !if(HasPat, Pattern[0], // rr
1458 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1460 !if(HasPat, Pattern[2], // rm
1461 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1462 (memopv2i64 addr:$src2)))]), 0>,
1465 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1466 !strconcat(OpcodeStr, "pd"), f128mem,
1467 !if(HasPat, Pattern[1], // rr
1468 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1471 !if(HasPat, Pattern[3], // rm
1472 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1473 (memopv2i64 addr:$src2)))]), 0>,
1476 let Constraints = "$src1 = $dst" in {
1477 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1478 !strconcat(OpcodeStr, "ps"), f128mem,
1479 !if(HasPat, Pattern[0], // rr
1480 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1482 !if(HasPat, Pattern[2], // rm
1483 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1484 (memopv2i64 addr:$src2)))])>, TB;
1486 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1487 !strconcat(OpcodeStr, "pd"), f128mem,
1488 !if(HasPat, Pattern[1], // rr
1489 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1492 !if(HasPat, Pattern[3], // rm
1493 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1494 (memopv2i64 addr:$src2)))])>,
1499 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
1501 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr> {
1502 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
1503 !strconcat(OpcodeStr, "ps"), f256mem, [], [], 0>, VEX_4V;
1505 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
1506 !strconcat(OpcodeStr, "pd"), f256mem, [], [], 0>, OpSize, VEX_4V;
1509 // AVX 256-bit packed logical ops forms
1510 defm VAND : sse12_fp_packed_logical_y<0x54, "and">;
1511 defm VOR : sse12_fp_packed_logical_y<0x56, "or">;
1512 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor">;
1513 let isCommutable = 0 in
1514 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn">;
1516 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
1517 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
1518 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
1519 let isCommutable = 0 in
1520 defm ANDN : sse12_fp_packed_logical<0x55, "andn", undef /* dummy */, 1, [
1522 [(set VR128:$dst, (X86pandn VR128:$src1, VR128:$src2))],
1526 [(set VR128:$dst, (X86pandn VR128:$src1, (memopv2i64 addr:$src2)))],
1530 //===----------------------------------------------------------------------===//
1531 // SSE 1 & 2 - Arithmetic Instructions
1532 //===----------------------------------------------------------------------===//
1534 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
1537 /// In addition, we also have a special variant of the scalar form here to
1538 /// represent the associated intrinsic operation. This form is unlike the
1539 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1540 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1542 /// These three forms can each be reg+reg or reg+mem.
1545 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
1547 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1549 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
1550 OpNode, FR32, f32mem, Is2Addr>, XS;
1551 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
1552 OpNode, FR64, f64mem, Is2Addr>, XD;
1555 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
1557 let mayLoad = 0 in {
1558 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
1559 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
1560 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
1561 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
1565 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
1567 let mayLoad = 0 in {
1568 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
1569 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
1570 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
1571 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
1575 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
1577 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1578 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
1579 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1580 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
1583 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
1585 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1586 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
1587 SSEPackedSingle, Is2Addr>, TB;
1589 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1590 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
1591 SSEPackedDouble, Is2Addr>, TB, OpSize;
1594 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
1595 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1596 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
1597 SSEPackedSingle, 0>, TB;
1599 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1600 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
1601 SSEPackedDouble, 0>, TB, OpSize;
1604 // Binary Arithmetic instructions
1605 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
1606 basic_sse12_fp_binop_s_int<0x58, "add", 0>,
1607 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
1608 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
1609 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
1610 basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
1611 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
1612 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
1614 let isCommutable = 0 in {
1615 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
1616 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
1617 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
1618 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
1619 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
1620 basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
1621 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
1622 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
1623 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
1624 basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
1625 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
1626 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
1627 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
1628 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
1629 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
1630 basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
1631 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
1632 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
1633 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
1634 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
1637 let Constraints = "$src1 = $dst" in {
1638 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
1639 basic_sse12_fp_binop_p<0x58, "add", fadd>,
1640 basic_sse12_fp_binop_s_int<0x58, "add">;
1641 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
1642 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
1643 basic_sse12_fp_binop_s_int<0x59, "mul">;
1645 let isCommutable = 0 in {
1646 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
1647 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
1648 basic_sse12_fp_binop_s_int<0x5C, "sub">;
1649 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
1650 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
1651 basic_sse12_fp_binop_s_int<0x5E, "div">;
1652 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
1653 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
1654 basic_sse12_fp_binop_s_int<0x5F, "max">,
1655 basic_sse12_fp_binop_p_int<0x5F, "max">;
1656 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
1657 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
1658 basic_sse12_fp_binop_s_int<0x5D, "min">,
1659 basic_sse12_fp_binop_p_int<0x5D, "min">;
1664 /// In addition, we also have a special variant of the scalar form here to
1665 /// represent the associated intrinsic operation. This form is unlike the
1666 /// plain scalar form, in that it takes an entire vector (instead of a
1667 /// scalar) and leaves the top elements undefined.
1669 /// And, we have a special variant form for a full-vector intrinsic form.
1671 /// sse1_fp_unop_s - SSE1 unops in scalar form.
1672 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
1673 SDNode OpNode, Intrinsic F32Int> {
1674 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1675 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1676 [(set FR32:$dst, (OpNode FR32:$src))]>;
1677 // For scalar unary operations, fold a load into the operation
1678 // only in OptForSize mode. It eliminates an instruction, but it also
1679 // eliminates a whole-register clobber (the load), so it introduces a
1680 // partial register update condition.
1681 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1682 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1683 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1684 Requires<[HasSSE1, OptForSize]>;
1685 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1686 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1687 [(set VR128:$dst, (F32Int VR128:$src))]>;
1688 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1689 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1690 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1693 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
1694 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1695 SDNode OpNode, Intrinsic F32Int> {
1696 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
1697 !strconcat(OpcodeStr,
1698 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1699 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
1700 !strconcat(OpcodeStr,
1701 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1702 []>, XS, Requires<[HasAVX, OptForSize]>;
1703 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1704 !strconcat(OpcodeStr,
1705 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1706 [(set VR128:$dst, (F32Int VR128:$src))]>;
1707 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1708 !strconcat(OpcodeStr,
1709 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1710 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1713 /// sse1_fp_unop_p - SSE1 unops in packed form.
1714 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1715 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1716 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1717 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
1718 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1719 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1720 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1723 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
1724 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1725 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1726 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1727 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
1728 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1729 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1730 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
1733 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
1734 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1735 Intrinsic V4F32Int> {
1736 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1737 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1738 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
1739 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1740 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1741 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1744 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
1745 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1746 Intrinsic V4F32Int> {
1747 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1748 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1749 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
1750 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1751 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1752 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
1755 /// sse2_fp_unop_s - SSE2 unops in scalar form.
1756 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
1757 SDNode OpNode, Intrinsic F64Int> {
1758 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1759 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1760 [(set FR64:$dst, (OpNode FR64:$src))]>;
1761 // See the comments in sse1_fp_unop_s for why this is OptForSize.
1762 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1763 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1764 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
1765 Requires<[HasSSE2, OptForSize]>;
1766 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1767 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1768 [(set VR128:$dst, (F64Int VR128:$src))]>;
1769 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1770 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1771 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1774 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
1775 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1776 SDNode OpNode, Intrinsic F64Int> {
1777 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1778 !strconcat(OpcodeStr,
1779 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1780 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1781 (ins FR64:$src1, f64mem:$src2),
1782 !strconcat(OpcodeStr,
1783 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1784 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1785 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1786 [(set VR128:$dst, (F64Int VR128:$src))]>;
1787 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1788 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1789 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1792 /// sse2_fp_unop_p - SSE2 unops in vector forms.
1793 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
1795 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1796 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1797 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
1798 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1799 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1800 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1803 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
1804 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1805 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1806 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1807 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
1808 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1809 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1810 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
1813 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
1814 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1815 Intrinsic V2F64Int> {
1816 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1817 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1818 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
1819 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1820 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1821 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1824 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
1825 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1826 Intrinsic V2F64Int> {
1827 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1828 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1829 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
1830 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1831 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1832 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
1835 let Predicates = [HasAVX] in {
1837 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ss>,
1838 sse2_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1841 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
1842 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
1843 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1844 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1845 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
1846 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
1847 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
1848 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
1851 // Reciprocal approximations. Note that these typically require refinement
1852 // in order to obtain suitable precision.
1853 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt", X86frsqrt,
1854 int_x86_sse_rsqrt_ss>, VEX_4V;
1855 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
1856 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
1857 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
1858 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
1860 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ss>,
1862 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
1863 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
1864 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
1865 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
1869 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
1870 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
1871 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
1872 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1873 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
1874 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
1876 // Reciprocal approximations. Note that these typically require refinement
1877 // in order to obtain suitable precision.
1878 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
1879 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
1880 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
1881 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
1882 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
1883 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
1885 // There is no f64 version of the reciprocal approximation instructions.
1887 //===----------------------------------------------------------------------===//
1888 // SSE 1 & 2 - Non-temporal stores
1889 //===----------------------------------------------------------------------===//
1891 let AddedComplexity = 400 in { // Prefer non-temporal versions
1892 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
1893 (ins f128mem:$dst, VR128:$src),
1894 "movntps\t{$src, $dst|$dst, $src}",
1895 [(alignednontemporalstore (v4f32 VR128:$src),
1897 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
1898 (ins f128mem:$dst, VR128:$src),
1899 "movntpd\t{$src, $dst|$dst, $src}",
1900 [(alignednontemporalstore (v2f64 VR128:$src),
1902 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
1903 (ins f128mem:$dst, VR128:$src),
1904 "movntdq\t{$src, $dst|$dst, $src}",
1905 [(alignednontemporalstore (v2f64 VR128:$src),
1908 let ExeDomain = SSEPackedInt in
1909 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
1910 (ins f128mem:$dst, VR128:$src),
1911 "movntdq\t{$src, $dst|$dst, $src}",
1912 [(alignednontemporalstore (v4f32 VR128:$src),
1915 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
1916 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
1918 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
1919 (ins f256mem:$dst, VR256:$src),
1920 "movntps\t{$src, $dst|$dst, $src}",
1921 [(alignednontemporalstore (v8f32 VR256:$src),
1923 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
1924 (ins f256mem:$dst, VR256:$src),
1925 "movntpd\t{$src, $dst|$dst, $src}",
1926 [(alignednontemporalstore (v4f64 VR256:$src),
1928 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
1929 (ins f256mem:$dst, VR256:$src),
1930 "movntdq\t{$src, $dst|$dst, $src}",
1931 [(alignednontemporalstore (v4f64 VR256:$src),
1933 let ExeDomain = SSEPackedInt in
1934 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
1935 (ins f256mem:$dst, VR256:$src),
1936 "movntdq\t{$src, $dst|$dst, $src}",
1937 [(alignednontemporalstore (v8f32 VR256:$src),
1941 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
1942 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
1943 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
1944 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
1945 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
1946 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
1948 let AddedComplexity = 400 in { // Prefer non-temporal versions
1949 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1950 "movntps\t{$src, $dst|$dst, $src}",
1951 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1952 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1953 "movntpd\t{$src, $dst|$dst, $src}",
1954 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
1956 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1957 "movntdq\t{$src, $dst|$dst, $src}",
1958 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
1960 let ExeDomain = SSEPackedInt in
1961 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1962 "movntdq\t{$src, $dst|$dst, $src}",
1963 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1965 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
1966 (MOVNTDQmr addr:$dst, VR128:$src)>;
1968 // There is no AVX form for instructions below this point
1969 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1970 "movnti\t{$src, $dst|$dst, $src}",
1971 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
1972 TB, Requires<[HasSSE2]>;
1973 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1974 "movnti\t{$src, $dst|$dst, $src}",
1975 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
1976 TB, Requires<[HasSSE2]>;
1979 //===----------------------------------------------------------------------===//
1980 // SSE 1 & 2 - Misc Instructions (No AVX form)
1981 //===----------------------------------------------------------------------===//
1983 // Prefetch intrinsic.
1984 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
1985 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
1986 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
1987 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
1988 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
1989 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
1990 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
1991 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
1993 // Load, store, and memory fence
1994 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
1995 TB, Requires<[HasSSE1]>;
1996 def : Pat<(X86SFence), (SFENCE)>;
1998 // Alias instructions that map zero vector to pxor / xorp* for sse.
1999 // We set canFoldAsLoad because this can be converted to a constant-pool
2000 // load of an all-zeros value if folding it would be beneficial.
2001 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
2002 // JIT implementation, it does not expand the instructions below like
2003 // X86MCInstLower does.
2004 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2005 isCodeGenOnly = 1 in {
2006 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2007 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2008 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2009 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
2010 let ExeDomain = SSEPackedInt in
2011 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2012 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2015 // The same as done above but for AVX. The 128-bit versions are the
2016 // same, but re-encoded. The 256-bit does not support PI version.
2017 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
2018 // JIT implementatioan, it does not expand the instructions below like
2019 // X86MCInstLower does.
2020 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2021 isCodeGenOnly = 1, Predicates = [HasAVX] in {
2022 def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2023 [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V;
2024 def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2025 [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V;
2026 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2027 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
2028 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2029 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
2030 let ExeDomain = SSEPackedInt in
2031 def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2032 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2035 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
2036 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
2037 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
2039 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2040 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
2042 //===----------------------------------------------------------------------===//
2043 // SSE 1 & 2 - Load/Store XCSR register
2044 //===----------------------------------------------------------------------===//
2046 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2047 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
2048 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2049 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
2051 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2052 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
2053 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2054 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
2056 //===---------------------------------------------------------------------===//
2057 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
2058 //===---------------------------------------------------------------------===//
2060 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2062 let neverHasSideEffects = 1 in {
2063 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2064 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2065 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2066 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2068 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2069 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2070 def VMOVDQUYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2071 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2073 let canFoldAsLoad = 1, mayLoad = 1 in {
2074 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2075 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2076 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2077 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2078 let Predicates = [HasAVX] in {
2079 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2080 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2081 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2082 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2086 let mayStore = 1 in {
2087 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
2088 (ins i128mem:$dst, VR128:$src),
2089 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2090 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
2091 (ins i256mem:$dst, VR256:$src),
2092 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2093 let Predicates = [HasAVX] in {
2094 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2095 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2096 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
2097 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2101 let neverHasSideEffects = 1 in
2102 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2103 "movdqa\t{$src, $dst|$dst, $src}", []>;
2105 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2106 "movdqu\t{$src, $dst|$dst, $src}",
2107 []>, XS, Requires<[HasSSE2]>;
2109 let canFoldAsLoad = 1, mayLoad = 1 in {
2110 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2111 "movdqa\t{$src, $dst|$dst, $src}",
2112 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
2113 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2114 "movdqu\t{$src, $dst|$dst, $src}",
2115 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2116 XS, Requires<[HasSSE2]>;
2119 let mayStore = 1 in {
2120 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2121 "movdqa\t{$src, $dst|$dst, $src}",
2122 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
2123 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2124 "movdqu\t{$src, $dst|$dst, $src}",
2125 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2126 XS, Requires<[HasSSE2]>;
2129 // Intrinsic forms of MOVDQU load and store
2130 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2131 "vmovdqu\t{$src, $dst|$dst, $src}",
2132 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2133 XS, VEX, Requires<[HasAVX]>;
2135 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2136 "movdqu\t{$src, $dst|$dst, $src}",
2137 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2138 XS, Requires<[HasSSE2]>;
2140 } // ExeDomain = SSEPackedInt
2142 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
2143 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
2144 (VMOVDQUYmr addr:$dst, VR256:$src)>;
2146 //===---------------------------------------------------------------------===//
2147 // SSE2 - Packed Integer Arithmetic Instructions
2148 //===---------------------------------------------------------------------===//
2150 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2152 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2153 bit IsCommutable = 0, bit Is2Addr = 1> {
2154 let isCommutable = IsCommutable in
2155 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2156 (ins VR128:$src1, VR128:$src2),
2158 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2159 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2160 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2161 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2162 (ins VR128:$src1, i128mem:$src2),
2164 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2165 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2166 [(set VR128:$dst, (IntId VR128:$src1,
2167 (bitconvert (memopv2i64 addr:$src2))))]>;
2170 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2171 string OpcodeStr, Intrinsic IntId,
2172 Intrinsic IntId2, bit Is2Addr = 1> {
2173 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2174 (ins VR128:$src1, VR128:$src2),
2176 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2177 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2178 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2179 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2180 (ins VR128:$src1, i128mem:$src2),
2182 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2183 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2184 [(set VR128:$dst, (IntId VR128:$src1,
2185 (bitconvert (memopv2i64 addr:$src2))))]>;
2186 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2187 (ins VR128:$src1, i32i8imm:$src2),
2189 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2190 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2191 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2194 /// PDI_binop_rm - Simple SSE2 binary operator.
2195 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2196 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
2197 let isCommutable = IsCommutable in
2198 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2199 (ins VR128:$src1, VR128:$src2),
2201 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2202 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2203 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2204 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2205 (ins VR128:$src1, i128mem:$src2),
2207 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2208 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2209 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2210 (bitconvert (memopv2i64 addr:$src2)))))]>;
2213 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2215 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2216 /// to collapse (bitconvert VT to VT) into its operand.
2218 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2219 bit IsCommutable = 0, bit Is2Addr = 1> {
2220 let isCommutable = IsCommutable in
2221 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2222 (ins VR128:$src1, VR128:$src2),
2224 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2225 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2226 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
2227 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2228 (ins VR128:$src1, i128mem:$src2),
2230 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2231 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2232 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
2235 } // ExeDomain = SSEPackedInt
2237 // 128-bit Integer Arithmetic
2239 let Predicates = [HasAVX] in {
2240 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
2241 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
2242 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
2243 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
2244 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
2245 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
2246 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
2247 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
2248 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
2251 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
2253 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
2255 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
2257 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
2259 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
2261 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
2263 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
2265 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
2267 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
2269 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
2271 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
2273 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
2275 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
2277 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
2279 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
2281 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
2283 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
2285 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
2287 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
2291 let Constraints = "$src1 = $dst" in {
2292 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2293 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2294 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2295 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2296 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2297 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2298 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2299 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2300 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2303 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2304 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2305 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2306 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2307 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2308 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2309 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2310 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2311 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2312 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
2313 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2314 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2315 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2316 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2317 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2318 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2319 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2320 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2321 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2323 } // Constraints = "$src1 = $dst"
2325 //===---------------------------------------------------------------------===//
2326 // SSE2 - Packed Integer Logical Instructions
2327 //===---------------------------------------------------------------------===//
2329 let Predicates = [HasAVX] in {
2330 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
2331 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
2333 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
2334 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
2336 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
2337 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
2340 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
2341 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
2343 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
2344 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
2346 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
2347 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
2350 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
2351 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
2353 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
2354 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
2357 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
2358 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
2359 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
2361 let ExeDomain = SSEPackedInt in {
2362 let neverHasSideEffects = 1 in {
2363 // 128-bit logical shifts.
2364 def VPSLLDQri : PDIi8<0x73, MRM7r,
2365 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2366 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2368 def VPSRLDQri : PDIi8<0x73, MRM3r,
2369 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2370 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2372 // PSRADQri doesn't exist in SSE[1-3].
2374 def VPANDNrr : PDI<0xDF, MRMSrcReg,
2375 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2376 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2377 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2378 VR128:$src2)))]>, VEX_4V;
2380 def VPANDNrm : PDI<0xDF, MRMSrcMem,
2381 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2382 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2383 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2384 (memopv2i64 addr:$src2))))]>,
2389 let Constraints = "$src1 = $dst" in {
2390 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2391 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2392 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2393 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2394 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2395 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2397 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2398 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2399 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2400 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2401 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2402 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2404 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2405 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2406 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2407 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2409 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2410 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
2411 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2413 let ExeDomain = SSEPackedInt in {
2414 let neverHasSideEffects = 1 in {
2415 // 128-bit logical shifts.
2416 def PSLLDQri : PDIi8<0x73, MRM7r,
2417 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2418 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2419 def PSRLDQri : PDIi8<0x73, MRM3r,
2420 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2421 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2422 // PSRADQri doesn't exist in SSE[1-3].
2424 def PANDNrr : PDI<0xDF, MRMSrcReg,
2425 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2426 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2428 def PANDNrm : PDI<0xDF, MRMSrcMem,
2429 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2430 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2432 } // Constraints = "$src1 = $dst"
2434 let Predicates = [HasAVX] in {
2435 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2436 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2437 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2438 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2439 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2440 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
2441 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2442 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
2443 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2444 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2446 // Shift up / down and insert zero's.
2447 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2448 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2449 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2450 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2453 let Predicates = [HasSSE2] in {
2454 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2455 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2456 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2457 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2458 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2459 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2460 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2461 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2462 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2463 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2465 // Shift up / down and insert zero's.
2466 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2467 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2468 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2469 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2472 //===---------------------------------------------------------------------===//
2473 // SSE2 - Packed Integer Comparison Instructions
2474 //===---------------------------------------------------------------------===//
2476 let Predicates = [HasAVX] in {
2477 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
2479 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
2481 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
2483 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
2485 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
2487 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
2491 let Constraints = "$src1 = $dst" in {
2492 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
2493 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
2494 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
2495 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2496 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2497 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2498 } // Constraints = "$src1 = $dst"
2500 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2501 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2502 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2503 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2504 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2505 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2506 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2507 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2508 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2509 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2510 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2511 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2513 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2514 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2515 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2516 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2517 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2518 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2519 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2520 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2521 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2522 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2523 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2524 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2526 //===---------------------------------------------------------------------===//
2527 // SSE2 - Packed Integer Pack Instructions
2528 //===---------------------------------------------------------------------===//
2530 let Predicates = [HasAVX] in {
2531 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
2533 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
2535 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
2539 let Constraints = "$src1 = $dst" in {
2540 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2541 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2542 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2543 } // Constraints = "$src1 = $dst"
2545 //===---------------------------------------------------------------------===//
2546 // SSE2 - Packed Integer Shuffle Instructions
2547 //===---------------------------------------------------------------------===//
2549 let ExeDomain = SSEPackedInt in {
2550 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
2552 def ri : Ii8<0x70, MRMSrcReg,
2553 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2554 !strconcat(OpcodeStr,
2555 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2556 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
2558 def mi : Ii8<0x70, MRMSrcMem,
2559 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2560 !strconcat(OpcodeStr,
2561 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2562 [(set VR128:$dst, (vt (pshuf_frag:$src2
2563 (bc_frag (memopv2i64 addr:$src1)),
2566 } // ExeDomain = SSEPackedInt
2568 let Predicates = [HasAVX] in {
2569 let AddedComplexity = 5 in
2570 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize,
2573 // SSE2 with ImmT == Imm8 and XS prefix.
2574 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
2577 // SSE2 with ImmT == Imm8 and XD prefix.
2578 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
2582 let Predicates = [HasSSE2] in {
2583 let AddedComplexity = 5 in
2584 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
2586 // SSE2 with ImmT == Imm8 and XS prefix.
2587 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
2589 // SSE2 with ImmT == Imm8 and XD prefix.
2590 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
2593 //===---------------------------------------------------------------------===//
2594 // SSE2 - Packed Integer Unpack Instructions
2595 //===---------------------------------------------------------------------===//
2597 let ExeDomain = SSEPackedInt in {
2598 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2599 PatFrag unp_frag, PatFrag bc_frag, bit Is2Addr = 1> {
2600 def rr : PDI<opc, MRMSrcReg,
2601 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2603 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2604 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2605 [(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
2606 def rm : PDI<opc, MRMSrcMem,
2607 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2609 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2610 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2611 [(set VR128:$dst, (unp_frag VR128:$src1,
2612 (bc_frag (memopv2i64
2616 let Predicates = [HasAVX] in {
2617 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, unpckl, bc_v16i8,
2619 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, unpckl, bc_v8i16,
2621 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, unpckl, bc_v4i32,
2624 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2625 /// knew to collapse (bitconvert VT to VT) into its operand.
2626 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2627 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2628 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2630 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>, VEX_4V;
2631 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2632 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2633 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2635 (v2i64 (unpckl VR128:$src1,
2636 (memopv2i64 addr:$src2))))]>, VEX_4V;
2638 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, unpckh, bc_v16i8,
2640 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, unpckh, bc_v8i16,
2642 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, unpckh, bc_v4i32,
2645 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2646 /// knew to collapse (bitconvert VT to VT) into its operand.
2647 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2648 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2649 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2651 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>, VEX_4V;
2652 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2653 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2654 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2656 (v2i64 (unpckh VR128:$src1,
2657 (memopv2i64 addr:$src2))))]>, VEX_4V;
2660 let Constraints = "$src1 = $dst" in {
2661 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, unpckl, bc_v16i8>;
2662 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, unpckl, bc_v8i16>;
2663 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, unpckl, bc_v4i32>;
2665 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2666 /// knew to collapse (bitconvert VT to VT) into its operand.
2667 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2668 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2669 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2671 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2672 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2673 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2674 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2676 (v2i64 (unpckl VR128:$src1,
2677 (memopv2i64 addr:$src2))))]>;
2679 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, unpckh, bc_v16i8>;
2680 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, unpckh, bc_v8i16>;
2681 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, unpckh, bc_v4i32>;
2683 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2684 /// knew to collapse (bitconvert VT to VT) into its operand.
2685 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2686 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2687 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2689 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2690 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2691 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2692 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2694 (v2i64 (unpckh VR128:$src1,
2695 (memopv2i64 addr:$src2))))]>;
2698 } // ExeDomain = SSEPackedInt
2700 //===---------------------------------------------------------------------===//
2701 // SSE2 - Packed Integer Extract and Insert
2702 //===---------------------------------------------------------------------===//
2704 let ExeDomain = SSEPackedInt in {
2705 multiclass sse2_pinsrw<bit Is2Addr = 1> {
2706 def rri : Ii8<0xC4, MRMSrcReg,
2707 (outs VR128:$dst), (ins VR128:$src1,
2708 GR32:$src2, i32i8imm:$src3),
2710 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2711 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2713 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2714 def rmi : Ii8<0xC4, MRMSrcMem,
2715 (outs VR128:$dst), (ins VR128:$src1,
2716 i16mem:$src2, i32i8imm:$src3),
2718 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2719 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2721 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2726 let Predicates = [HasAVX] in
2727 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
2728 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2729 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2730 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2731 imm:$src2))]>, OpSize, VEX;
2732 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2733 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2734 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2735 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2739 let Predicates = [HasAVX] in {
2740 defm VPINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
2741 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
2742 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2743 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2744 []>, OpSize, VEX_4V;
2747 let Constraints = "$src1 = $dst" in
2748 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
2750 } // ExeDomain = SSEPackedInt
2752 //===---------------------------------------------------------------------===//
2753 // SSE2 - Packed Mask Creation
2754 //===---------------------------------------------------------------------===//
2756 let ExeDomain = SSEPackedInt in {
2758 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2759 "pmovmskb\t{$src, $dst|$dst, $src}",
2760 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
2761 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2762 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
2763 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2764 "pmovmskb\t{$src, $dst|$dst, $src}",
2765 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2767 } // ExeDomain = SSEPackedInt
2769 //===---------------------------------------------------------------------===//
2770 // SSE2 - Conditional Store
2771 //===---------------------------------------------------------------------===//
2773 let ExeDomain = SSEPackedInt in {
2776 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
2777 (ins VR128:$src, VR128:$mask),
2778 "maskmovdqu\t{$mask, $src|$src, $mask}",
2779 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
2781 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
2782 (ins VR128:$src, VR128:$mask),
2783 "maskmovdqu\t{$mask, $src|$src, $mask}",
2784 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
2787 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2788 "maskmovdqu\t{$mask, $src|$src, $mask}",
2789 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2791 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2792 "maskmovdqu\t{$mask, $src|$src, $mask}",
2793 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2795 } // ExeDomain = SSEPackedInt
2797 //===---------------------------------------------------------------------===//
2798 // SSE2 - Move Doubleword
2799 //===---------------------------------------------------------------------===//
2801 // Move Int Doubleword to Packed Double Int
2802 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2803 "movd\t{$src, $dst|$dst, $src}",
2805 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
2806 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2807 "movd\t{$src, $dst|$dst, $src}",
2809 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
2811 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2812 "movd\t{$src, $dst|$dst, $src}",
2814 (v4i32 (scalar_to_vector GR32:$src)))]>;
2815 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2816 "movd\t{$src, $dst|$dst, $src}",
2818 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2819 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2820 "mov{d|q}\t{$src, $dst|$dst, $src}",
2822 (v2i64 (scalar_to_vector GR64:$src)))]>;
2823 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2824 "mov{d|q}\t{$src, $dst|$dst, $src}",
2825 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2828 // Move Int Doubleword to Single Scalar
2829 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2830 "movd\t{$src, $dst|$dst, $src}",
2831 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
2833 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2834 "movd\t{$src, $dst|$dst, $src}",
2835 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
2837 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2838 "movd\t{$src, $dst|$dst, $src}",
2839 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2841 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2842 "movd\t{$src, $dst|$dst, $src}",
2843 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2845 // Move Packed Doubleword Int to Packed Double Int
2846 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2847 "movd\t{$src, $dst|$dst, $src}",
2848 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2850 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
2851 (ins i32mem:$dst, VR128:$src),
2852 "movd\t{$src, $dst|$dst, $src}",
2853 [(store (i32 (vector_extract (v4i32 VR128:$src),
2854 (iPTR 0))), addr:$dst)]>, VEX;
2855 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2856 "movd\t{$src, $dst|$dst, $src}",
2857 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2859 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2860 "movd\t{$src, $dst|$dst, $src}",
2861 [(store (i32 (vector_extract (v4i32 VR128:$src),
2862 (iPTR 0))), addr:$dst)]>;
2864 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2865 "mov{d|q}\t{$src, $dst|$dst, $src}",
2866 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
2868 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2869 "movq\t{$src, $dst|$dst, $src}",
2870 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2872 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2873 "mov{d|q}\t{$src, $dst|$dst, $src}",
2874 [(set GR64:$dst, (bitconvert FR64:$src))]>;
2875 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2876 "movq\t{$src, $dst|$dst, $src}",
2877 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
2879 // Move Scalar Single to Double Int
2880 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2881 "movd\t{$src, $dst|$dst, $src}",
2882 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
2883 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2884 "movd\t{$src, $dst|$dst, $src}",
2885 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
2886 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2887 "movd\t{$src, $dst|$dst, $src}",
2888 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2889 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2890 "movd\t{$src, $dst|$dst, $src}",
2891 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2893 // movd / movq to XMM register zero-extends
2894 let AddedComplexity = 15 in {
2895 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2896 "movd\t{$src, $dst|$dst, $src}",
2897 [(set VR128:$dst, (v4i32 (X86vzmovl
2898 (v4i32 (scalar_to_vector GR32:$src)))))]>,
2900 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2901 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
2902 [(set VR128:$dst, (v2i64 (X86vzmovl
2903 (v2i64 (scalar_to_vector GR64:$src)))))]>,
2906 let AddedComplexity = 15 in {
2907 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2908 "movd\t{$src, $dst|$dst, $src}",
2909 [(set VR128:$dst, (v4i32 (X86vzmovl
2910 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2911 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2912 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
2913 [(set VR128:$dst, (v2i64 (X86vzmovl
2914 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2917 let AddedComplexity = 20 in {
2918 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2919 "movd\t{$src, $dst|$dst, $src}",
2921 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2922 (loadi32 addr:$src))))))]>,
2924 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2925 "movd\t{$src, $dst|$dst, $src}",
2927 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2928 (loadi32 addr:$src))))))]>;
2930 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2931 (MOVZDI2PDIrm addr:$src)>;
2932 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2933 (MOVZDI2PDIrm addr:$src)>;
2934 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2935 (MOVZDI2PDIrm addr:$src)>;
2938 //===---------------------------------------------------------------------===//
2939 // SSE2 - Move Quadword
2940 //===---------------------------------------------------------------------===//
2942 // Move Quadword Int to Packed Quadword Int
2943 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2944 "vmovq\t{$src, $dst|$dst, $src}",
2946 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2947 VEX, Requires<[HasAVX]>;
2948 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2949 "movq\t{$src, $dst|$dst, $src}",
2951 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2952 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
2954 // Move Packed Quadword Int to Quadword Int
2955 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2956 "movq\t{$src, $dst|$dst, $src}",
2957 [(store (i64 (vector_extract (v2i64 VR128:$src),
2958 (iPTR 0))), addr:$dst)]>, VEX;
2959 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2960 "movq\t{$src, $dst|$dst, $src}",
2961 [(store (i64 (vector_extract (v2i64 VR128:$src),
2962 (iPTR 0))), addr:$dst)]>;
2964 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
2965 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
2967 // Store / copy lower 64-bits of a XMM register.
2968 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2969 "movq\t{$src, $dst|$dst, $src}",
2970 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
2971 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2972 "movq\t{$src, $dst|$dst, $src}",
2973 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2975 let AddedComplexity = 20 in
2976 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2977 "vmovq\t{$src, $dst|$dst, $src}",
2979 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2980 (loadi64 addr:$src))))))]>,
2981 XS, VEX, Requires<[HasAVX]>;
2983 let AddedComplexity = 20 in {
2984 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2985 "movq\t{$src, $dst|$dst, $src}",
2987 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2988 (loadi64 addr:$src))))))]>,
2989 XS, Requires<[HasSSE2]>;
2991 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2992 (MOVZQI2PQIrm addr:$src)>;
2993 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2994 (MOVZQI2PQIrm addr:$src)>;
2995 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2998 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2999 // IA32 document. movq xmm1, xmm2 does clear the high bits.
3000 let AddedComplexity = 15 in
3001 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3002 "vmovq\t{$src, $dst|$dst, $src}",
3003 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3004 XS, VEX, Requires<[HasAVX]>;
3005 let AddedComplexity = 15 in
3006 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3007 "movq\t{$src, $dst|$dst, $src}",
3008 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3009 XS, Requires<[HasSSE2]>;
3011 let AddedComplexity = 20 in
3012 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3013 "vmovq\t{$src, $dst|$dst, $src}",
3014 [(set VR128:$dst, (v2i64 (X86vzmovl
3015 (loadv2i64 addr:$src))))]>,
3016 XS, VEX, Requires<[HasAVX]>;
3017 let AddedComplexity = 20 in {
3018 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3019 "movq\t{$src, $dst|$dst, $src}",
3020 [(set VR128:$dst, (v2i64 (X86vzmovl
3021 (loadv2i64 addr:$src))))]>,
3022 XS, Requires<[HasSSE2]>;
3024 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
3025 (MOVZPQILo2PQIrm addr:$src)>;
3028 // Instructions to match in the assembler
3029 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3030 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3031 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3032 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3033 // Recognize "movd" with GR64 destination, but encode as a "movq"
3034 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3035 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3037 // Instructions for the disassembler
3038 // xr = XMM register
3041 let Predicates = [HasAVX] in
3042 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3043 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
3044 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3045 "movq\t{$src, $dst|$dst, $src}", []>, XS;
3047 //===---------------------------------------------------------------------===//
3048 // SSE2 - Misc Instructions
3049 //===---------------------------------------------------------------------===//
3052 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3053 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3054 TB, Requires<[HasSSE2]>;
3056 // Load, store, and memory fence
3057 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3058 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3059 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3060 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3061 def : Pat<(X86LFence), (LFENCE)>;
3062 def : Pat<(X86MFence), (MFENCE)>;
3065 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3066 // was introduced with SSE2, it's backward compatible.
3067 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3069 // Alias instructions that map zero vector to pxor / xorp* for sse.
3070 // We set canFoldAsLoad because this can be converted to a constant-pool
3071 // load of an all-ones value if folding it would be beneficial.
3072 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3073 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
3074 // FIXME: Change encoding to pseudo.
3075 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3076 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
3078 //===---------------------------------------------------------------------===//
3079 // SSE3 - Conversion Instructions
3080 //===---------------------------------------------------------------------===//
3082 // Convert Packed Double FP to Packed DW Integers
3083 let Predicates = [HasAVX] in {
3084 // The assembler can recognize rr 256-bit instructions by seeing a ymm
3085 // register, but the same isn't true when using memory operands instead.
3086 // Provide other assembly rr and rm forms to address this explicitly.
3087 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3088 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3089 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3090 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3093 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3094 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3095 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3096 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3099 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3100 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
3101 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
3102 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
3105 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3106 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3107 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3108 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3110 // Convert Packed DW Integers to Packed Double FP
3111 let Predicates = [HasAVX] in {
3112 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3113 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3114 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3115 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3116 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
3117 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3118 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
3119 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3122 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3123 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3124 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3125 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3127 // AVX 256-bit register conversion intrinsics
3128 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
3129 (VCVTDQ2PDYrr VR128:$src)>;
3130 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
3131 (VCVTDQ2PDYrm addr:$src)>;
3133 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
3134 (VCVTPD2DQYrr VR256:$src)>;
3135 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
3136 (VCVTPD2DQYrm addr:$src)>;
3138 //===---------------------------------------------------------------------===//
3139 // SSE3 - Move Instructions
3140 //===---------------------------------------------------------------------===//
3142 // Replicate Single FP
3143 multiclass sse3_replicate_sfp<bits<8> op, PatFrag rep_frag, string OpcodeStr> {
3144 def rr : S3SI<op, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3145 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3146 [(set VR128:$dst, (v4f32 (rep_frag
3147 VR128:$src, (undef))))]>;
3148 def rm : S3SI<op, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3149 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3150 [(set VR128:$dst, (rep_frag
3151 (memopv4f32 addr:$src), (undef)))]>;
3154 multiclass sse3_replicate_sfp_y<bits<8> op, PatFrag rep_frag,
3156 def rr : S3SI<op, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3157 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
3158 def rm : S3SI<op, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3159 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
3162 let Predicates = [HasAVX] in {
3163 // FIXME: Merge above classes when we have patterns for the ymm version
3164 defm VMOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "vmovshdup">, VEX;
3165 defm VMOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "vmovsldup">, VEX;
3166 defm VMOVSHDUPY : sse3_replicate_sfp_y<0x16, movshdup, "vmovshdup">, VEX;
3167 defm VMOVSLDUPY : sse3_replicate_sfp_y<0x12, movsldup, "vmovsldup">, VEX;
3169 defm MOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "movshdup">;
3170 defm MOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "movsldup">;
3172 // Replicate Double FP
3173 multiclass sse3_replicate_dfp<string OpcodeStr> {
3174 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3175 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3176 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
3177 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
3178 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3180 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
3184 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
3185 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3186 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3188 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3189 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3193 let Predicates = [HasAVX] in {
3194 // FIXME: Merge above classes when we have patterns for the ymm version
3195 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
3196 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
3198 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
3200 // Move Unaligned Integer
3201 let Predicates = [HasAVX] in {
3202 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3203 "vlddqu\t{$src, $dst|$dst, $src}",
3204 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
3205 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3206 "vlddqu\t{$src, $dst|$dst, $src}",
3207 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
3209 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3210 "lddqu\t{$src, $dst|$dst, $src}",
3211 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
3213 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
3215 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3217 // Several Move patterns
3218 let AddedComplexity = 5 in {
3219 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
3220 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3221 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
3222 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3223 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
3224 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3225 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
3226 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3229 // vector_shuffle v1, <undef> <1, 1, 3, 3>
3230 let AddedComplexity = 15 in
3231 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
3232 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3233 let AddedComplexity = 20 in
3234 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3235 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
3237 // vector_shuffle v1, <undef> <0, 0, 2, 2>
3238 let AddedComplexity = 15 in
3239 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
3240 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3241 let AddedComplexity = 20 in
3242 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3243 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
3245 //===---------------------------------------------------------------------===//
3246 // SSE3 - Arithmetic
3247 //===---------------------------------------------------------------------===//
3249 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
3250 X86MemOperand x86memop, bit Is2Addr = 1> {
3251 def rr : I<0xD0, MRMSrcReg,
3252 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3254 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3255 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3256 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
3257 def rm : I<0xD0, MRMSrcMem,
3258 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3260 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3261 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3262 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
3265 let Predicates = [HasAVX],
3266 ExeDomain = SSEPackedDouble in {
3267 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
3268 f128mem, 0>, TB, XD, VEX_4V;
3269 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
3270 f128mem, 0>, TB, OpSize, VEX_4V;
3271 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
3272 f256mem, 0>, TB, XD, VEX_4V;
3273 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
3274 f256mem, 0>, TB, OpSize, VEX_4V;
3276 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
3277 ExeDomain = SSEPackedDouble in {
3278 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
3280 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
3281 f128mem>, TB, OpSize;
3284 //===---------------------------------------------------------------------===//
3285 // SSE3 Instructions
3286 //===---------------------------------------------------------------------===//
3289 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3290 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3291 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3293 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3294 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3295 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3297 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3299 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3300 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3301 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3303 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3304 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3305 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3307 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3308 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3309 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3311 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3313 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3314 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3315 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3318 let Predicates = [HasAVX] in {
3319 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
3320 int_x86_sse3_hadd_ps, 0>, VEX_4V;
3321 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
3322 int_x86_sse3_hadd_pd, 0>, VEX_4V;
3323 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
3324 int_x86_sse3_hsub_ps, 0>, VEX_4V;
3325 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
3326 int_x86_sse3_hsub_pd, 0>, VEX_4V;
3327 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
3328 int_x86_avx_hadd_ps_256, 0>, VEX_4V;
3329 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
3330 int_x86_avx_hadd_pd_256, 0>, VEX_4V;
3331 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
3332 int_x86_avx_hsub_ps_256, 0>, VEX_4V;
3333 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
3334 int_x86_avx_hsub_pd_256, 0>, VEX_4V;
3337 let Constraints = "$src1 = $dst" in {
3338 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
3339 int_x86_sse3_hadd_ps>;
3340 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
3341 int_x86_sse3_hadd_pd>;
3342 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
3343 int_x86_sse3_hsub_ps>;
3344 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
3345 int_x86_sse3_hsub_pd>;
3348 //===---------------------------------------------------------------------===//
3349 // SSSE3 - Packed Absolute Instructions
3350 //===---------------------------------------------------------------------===//
3353 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
3354 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
3355 PatFrag mem_frag128, Intrinsic IntId128> {
3356 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3358 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3359 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3362 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3364 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3367 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
3370 let Predicates = [HasAVX] in {
3371 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
3372 int_x86_ssse3_pabs_b_128>, VEX;
3373 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
3374 int_x86_ssse3_pabs_w_128>, VEX;
3375 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
3376 int_x86_ssse3_pabs_d_128>, VEX;
3379 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
3380 int_x86_ssse3_pabs_b_128>;
3381 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
3382 int_x86_ssse3_pabs_w_128>;
3383 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
3384 int_x86_ssse3_pabs_d_128>;
3386 //===---------------------------------------------------------------------===//
3387 // SSSE3 - Packed Binary Operator Instructions
3388 //===---------------------------------------------------------------------===//
3390 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
3391 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
3392 PatFrag mem_frag128, Intrinsic IntId128,
3394 let isCommutable = 1 in
3395 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3396 (ins VR128:$src1, VR128:$src2),
3398 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3399 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3400 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3402 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3403 (ins VR128:$src1, i128mem:$src2),
3405 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3406 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3408 (IntId128 VR128:$src1,
3409 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3412 let Predicates = [HasAVX] in {
3413 let isCommutable = 0 in {
3414 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
3415 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
3416 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
3417 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
3418 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
3419 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
3420 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
3421 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
3422 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
3423 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
3424 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
3425 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
3426 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
3427 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
3428 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
3429 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
3430 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
3431 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
3432 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
3433 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
3434 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
3435 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
3437 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
3438 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
3441 // None of these have i8 immediate fields.
3442 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
3443 let isCommutable = 0 in {
3444 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
3445 int_x86_ssse3_phadd_w_128>;
3446 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
3447 int_x86_ssse3_phadd_d_128>;
3448 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
3449 int_x86_ssse3_phadd_sw_128>;
3450 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
3451 int_x86_ssse3_phsub_w_128>;
3452 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
3453 int_x86_ssse3_phsub_d_128>;
3454 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
3455 int_x86_ssse3_phsub_sw_128>;
3456 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
3457 int_x86_ssse3_pmadd_ub_sw_128>;
3458 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
3459 int_x86_ssse3_pshuf_b_128>;
3460 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
3461 int_x86_ssse3_psign_b_128>;
3462 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
3463 int_x86_ssse3_psign_w_128>;
3464 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
3465 int_x86_ssse3_psign_d_128>;
3467 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
3468 int_x86_ssse3_pmul_hr_sw_128>;
3471 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
3472 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
3473 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
3474 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
3476 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
3477 (PSIGNBrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3478 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
3479 (PSIGNWrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3480 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
3481 (PSIGNDrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3483 //===---------------------------------------------------------------------===//
3484 // SSSE3 - Packed Align Instruction Patterns
3485 //===---------------------------------------------------------------------===//
3487 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
3488 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
3489 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3491 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3493 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3495 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
3496 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3498 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3500 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3504 let Predicates = [HasAVX] in
3505 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
3506 let Constraints = "$src1 = $dst" in
3507 defm PALIGN : ssse3_palign<"palignr">;
3509 let AddedComplexity = 5 in {
3510 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
3511 (PALIGNR128rr VR128:$src2, VR128:$src1,
3512 (SHUFFLE_get_palign_imm VR128:$src3))>,
3513 Requires<[HasSSSE3]>;
3514 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
3515 (PALIGNR128rr VR128:$src2, VR128:$src1,
3516 (SHUFFLE_get_palign_imm VR128:$src3))>,
3517 Requires<[HasSSSE3]>;
3518 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
3519 (PALIGNR128rr VR128:$src2, VR128:$src1,
3520 (SHUFFLE_get_palign_imm VR128:$src3))>,
3521 Requires<[HasSSSE3]>;
3522 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
3523 (PALIGNR128rr VR128:$src2, VR128:$src1,
3524 (SHUFFLE_get_palign_imm VR128:$src3))>,
3525 Requires<[HasSSSE3]>;
3528 //===---------------------------------------------------------------------===//
3529 // SSSE3 Misc Instructions
3530 //===---------------------------------------------------------------------===//
3532 // Thread synchronization
3533 let usesCustomInserter = 1 in {
3534 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
3535 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
3536 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
3537 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
3540 let Uses = [EAX, ECX, EDX] in
3541 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
3542 Requires<[HasSSE3]>;
3543 let Uses = [ECX, EAX] in
3544 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
3545 Requires<[HasSSE3]>;
3547 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
3548 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
3550 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
3551 Requires<[In32BitMode]>;
3552 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
3553 Requires<[In64BitMode]>;
3555 //===---------------------------------------------------------------------===//
3556 // Non-Instruction Patterns
3557 //===---------------------------------------------------------------------===//
3559 // extload f32 -> f64. This matches load+fextend because we have a hack in
3560 // the isel (PreprocessForFPConvert) that can introduce loads after dag
3562 // Since these loads aren't folded into the fextend, we have to match it
3564 let Predicates = [HasSSE2] in
3565 def : Pat<(fextend (loadf32 addr:$src)),
3566 (CVTSS2SDrm addr:$src)>;
3569 let Predicates = [HasXMMInt] in {
3570 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
3571 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
3572 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
3573 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
3574 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
3575 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
3576 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
3577 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3578 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3579 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3580 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3581 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3582 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3583 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3584 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3585 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3586 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3587 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3588 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3589 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3590 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3591 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3592 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3593 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3594 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3595 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3596 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3597 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3598 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3599 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3602 let Predicates = [HasAVX] in {
3603 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
3606 // Move scalar to XMM zero-extended
3607 // movd to XMM register zero-extends
3608 let AddedComplexity = 15 in {
3609 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3610 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3611 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
3612 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3613 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
3614 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3615 (MOVSSrr (v4f32 (V_SET0PS)),
3616 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
3617 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3618 (MOVSSrr (v4i32 (V_SET0PI)),
3619 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
3622 // Splat v2f64 / v2i64
3623 let AddedComplexity = 10 in {
3624 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3625 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3626 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
3627 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3628 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3629 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3630 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
3631 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3634 // Special unary SHUFPSrri case.
3635 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3636 (SHUFPSrri VR128:$src1, VR128:$src1,
3637 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3638 let AddedComplexity = 5 in
3639 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3640 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3641 Requires<[HasSSE2]>;
3642 // Special unary SHUFPDrri case.
3643 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3644 (SHUFPDrri VR128:$src1, VR128:$src1,
3645 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3646 Requires<[HasSSE2]>;
3647 // Special unary SHUFPDrri case.
3648 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3649 (SHUFPDrri VR128:$src1, VR128:$src1,
3650 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3651 Requires<[HasSSE2]>;
3652 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3653 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3654 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3655 Requires<[HasSSE2]>;
3657 // Special binary v4i32 shuffle cases with SHUFPS.
3658 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3659 (SHUFPSrri VR128:$src1, VR128:$src2,
3660 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3661 Requires<[HasSSE2]>;
3662 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3663 (SHUFPSrmi VR128:$src1, addr:$src2,
3664 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3665 Requires<[HasSSE2]>;
3666 // Special binary v2i64 shuffle cases using SHUFPDrri.
3667 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3668 (SHUFPDrri VR128:$src1, VR128:$src2,
3669 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3670 Requires<[HasSSE2]>;
3672 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3673 let AddedComplexity = 15 in {
3674 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3675 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3676 Requires<[OptForSpeed, HasSSE2]>;
3677 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3678 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3679 Requires<[OptForSpeed, HasSSE2]>;
3681 let AddedComplexity = 10 in {
3682 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3683 (UNPCKLPSrr VR128:$src, VR128:$src)>;
3684 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3685 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
3686 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3687 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
3688 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3689 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3692 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3693 let AddedComplexity = 15 in {
3694 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3695 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3696 Requires<[OptForSpeed, HasSSE2]>;
3697 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3698 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3699 Requires<[OptForSpeed, HasSSE2]>;
3701 let AddedComplexity = 10 in {
3702 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3703 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3704 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3705 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3706 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3707 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3708 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3709 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3712 let AddedComplexity = 20 in {
3713 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3714 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3715 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3717 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3718 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3719 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3721 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3722 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3723 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3724 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3725 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3728 let AddedComplexity = 20 in {
3729 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3730 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3731 (MOVLPSrm VR128:$src1, addr:$src2)>;
3732 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3733 (MOVLPDrm VR128:$src1, addr:$src2)>;
3734 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3735 (MOVLPSrm VR128:$src1, addr:$src2)>;
3736 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3737 (MOVLPDrm VR128:$src1, addr:$src2)>;
3740 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3741 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3742 (MOVLPSmr addr:$src1, VR128:$src2)>;
3743 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3744 (MOVLPDmr addr:$src1, VR128:$src2)>;
3745 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3747 (MOVLPSmr addr:$src1, VR128:$src2)>;
3748 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3749 (MOVLPDmr addr:$src1, VR128:$src2)>;
3751 let AddedComplexity = 15 in {
3752 // Setting the lowest element in the vector.
3753 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3754 (MOVSSrr (v4i32 VR128:$src1),
3755 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3756 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3757 (MOVSDrr (v2i64 VR128:$src1),
3758 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
3760 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3761 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3762 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3763 Requires<[HasSSE2]>;
3764 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3765 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3766 Requires<[HasSSE2]>;
3769 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3770 // fall back to this for SSE1)
3771 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3772 (SHUFPSrri VR128:$src2, VR128:$src1,
3773 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3775 // Set lowest element and zero upper elements.
3776 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3777 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3779 // vector -> vector casts
3780 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3781 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3782 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3783 (CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3785 // Use movaps / movups for SSE integer load / store (one byte shorter).
3786 let Predicates = [HasSSE1] in {
3787 def : Pat<(alignedloadv4i32 addr:$src),
3788 (MOVAPSrm addr:$src)>;
3789 def : Pat<(loadv4i32 addr:$src),
3790 (MOVUPSrm addr:$src)>;
3791 def : Pat<(alignedloadv2i64 addr:$src),
3792 (MOVAPSrm addr:$src)>;
3793 def : Pat<(loadv2i64 addr:$src),
3794 (MOVUPSrm addr:$src)>;
3796 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3797 (MOVAPSmr addr:$dst, VR128:$src)>;
3798 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3799 (MOVAPSmr addr:$dst, VR128:$src)>;
3800 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3801 (MOVAPSmr addr:$dst, VR128:$src)>;
3802 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3803 (MOVAPSmr addr:$dst, VR128:$src)>;
3804 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3805 (MOVUPSmr addr:$dst, VR128:$src)>;
3806 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3807 (MOVUPSmr addr:$dst, VR128:$src)>;
3808 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3809 (MOVUPSmr addr:$dst, VR128:$src)>;
3810 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3811 (MOVUPSmr addr:$dst, VR128:$src)>;
3814 // Use vmovaps/vmovups for AVX 128-bit integer load/store (one byte shorter).
3815 let Predicates = [HasAVX] in {
3816 def : Pat<(alignedloadv4i32 addr:$src),
3817 (VMOVAPSrm addr:$src)>;
3818 def : Pat<(loadv4i32 addr:$src),
3819 (VMOVUPSrm addr:$src)>;
3820 def : Pat<(alignedloadv2i64 addr:$src),
3821 (VMOVAPSrm addr:$src)>;
3822 def : Pat<(loadv2i64 addr:$src),
3823 (VMOVUPSrm addr:$src)>;
3825 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3826 (VMOVAPSmr addr:$dst, VR128:$src)>;
3827 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3828 (VMOVAPSmr addr:$dst, VR128:$src)>;
3829 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3830 (VMOVAPSmr addr:$dst, VR128:$src)>;
3831 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3832 (VMOVAPSmr addr:$dst, VR128:$src)>;
3833 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3834 (VMOVUPSmr addr:$dst, VR128:$src)>;
3835 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3836 (VMOVUPSmr addr:$dst, VR128:$src)>;
3837 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3838 (VMOVUPSmr addr:$dst, VR128:$src)>;
3839 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3840 (VMOVUPSmr addr:$dst, VR128:$src)>;
3843 //===----------------------------------------------------------------------===//
3844 // SSE4.1 - Packed Move with Sign/Zero Extend
3845 //===----------------------------------------------------------------------===//
3847 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3848 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3849 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3850 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3852 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3853 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3855 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3859 let Predicates = [HasAVX] in {
3860 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
3862 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
3864 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
3866 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
3868 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
3870 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
3874 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3875 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3876 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3877 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3878 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3879 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3881 // Common patterns involving scalar load.
3882 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3883 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3884 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3885 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3887 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3888 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3889 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3890 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3892 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3893 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3894 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3895 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3897 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3898 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3899 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3900 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3902 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3903 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3904 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3905 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3907 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3908 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3909 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3910 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3913 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3914 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3915 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3916 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3918 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3919 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3921 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3925 let Predicates = [HasAVX] in {
3926 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
3928 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
3930 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
3932 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
3936 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3937 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3938 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3939 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3941 // Common patterns involving scalar load
3942 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3943 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3944 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3945 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3947 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3948 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3949 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3950 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3953 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3954 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3955 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3956 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3958 // Expecting a i16 load any extended to i32 value.
3959 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3960 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3961 [(set VR128:$dst, (IntId (bitconvert
3962 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3966 let Predicates = [HasAVX] in {
3967 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
3969 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
3972 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3973 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
3975 // Common patterns involving scalar load
3976 def : Pat<(int_x86_sse41_pmovsxbq
3977 (bitconvert (v4i32 (X86vzmovl
3978 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3979 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3981 def : Pat<(int_x86_sse41_pmovzxbq
3982 (bitconvert (v4i32 (X86vzmovl
3983 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3984 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3986 //===----------------------------------------------------------------------===//
3987 // SSE4.1 - Extract Instructions
3988 //===----------------------------------------------------------------------===//
3990 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3991 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3992 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3993 (ins VR128:$src1, i32i8imm:$src2),
3994 !strconcat(OpcodeStr,
3995 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3996 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3998 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3999 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
4000 !strconcat(OpcodeStr,
4001 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4004 // There's an AssertZext in the way of writing the store pattern
4005 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4008 let Predicates = [HasAVX] in {
4009 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
4010 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
4011 (ins VR128:$src1, i32i8imm:$src2),
4012 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
4015 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
4018 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
4019 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
4020 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4021 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
4022 !strconcat(OpcodeStr,
4023 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4026 // There's an AssertZext in the way of writing the store pattern
4027 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4030 let Predicates = [HasAVX] in
4031 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
4033 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
4036 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4037 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
4038 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4039 (ins VR128:$src1, i32i8imm:$src2),
4040 !strconcat(OpcodeStr,
4041 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4043 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
4044 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4045 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
4046 !strconcat(OpcodeStr,
4047 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4048 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
4049 addr:$dst)]>, OpSize;
4052 let Predicates = [HasAVX] in
4053 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
4055 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
4057 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4058 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
4059 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
4060 (ins VR128:$src1, i32i8imm:$src2),
4061 !strconcat(OpcodeStr,
4062 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4064 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
4065 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4066 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
4067 !strconcat(OpcodeStr,
4068 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4069 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
4070 addr:$dst)]>, OpSize, REX_W;
4073 let Predicates = [HasAVX] in
4074 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
4076 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
4078 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
4080 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
4081 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4082 (ins VR128:$src1, i32i8imm:$src2),
4083 !strconcat(OpcodeStr,
4084 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4086 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
4088 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4089 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
4090 !strconcat(OpcodeStr,
4091 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4092 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
4093 addr:$dst)]>, OpSize;
4096 let Predicates = [HasAVX] in {
4097 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
4098 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
4099 (ins VR128:$src1, i32i8imm:$src2),
4100 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
4103 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
4105 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
4106 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
4109 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
4110 Requires<[HasSSE41]>;
4112 //===----------------------------------------------------------------------===//
4113 // SSE4.1 - Insert Instructions
4114 //===----------------------------------------------------------------------===//
4116 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
4117 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4118 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4120 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4122 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4124 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
4125 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4126 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
4128 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4130 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4132 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
4133 imm:$src3))]>, OpSize;
4136 let Predicates = [HasAVX] in
4137 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
4138 let Constraints = "$src1 = $dst" in
4139 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
4141 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
4142 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4143 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4145 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4147 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4149 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
4151 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4152 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
4154 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4156 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4158 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
4159 imm:$src3)))]>, OpSize;
4162 let Predicates = [HasAVX] in
4163 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
4164 let Constraints = "$src1 = $dst" in
4165 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
4167 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
4168 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4169 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4171 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4173 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4175 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
4177 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4178 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
4180 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4182 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4184 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
4185 imm:$src3)))]>, OpSize;
4188 let Predicates = [HasAVX] in
4189 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
4190 let Constraints = "$src1 = $dst" in
4191 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
4193 // insertps has a few different modes, there's the first two here below which
4194 // are optimized inserts that won't zero arbitrary elements in the destination
4195 // vector. The next one matches the intrinsic and could zero arbitrary elements
4196 // in the target vector.
4197 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
4198 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4199 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4201 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4203 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4205 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
4207 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4208 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
4210 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4212 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4214 (X86insrtps VR128:$src1,
4215 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
4216 imm:$src3))]>, OpSize;
4219 let Constraints = "$src1 = $dst" in
4220 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
4221 let Predicates = [HasAVX] in
4222 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
4224 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4225 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4227 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4228 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4229 Requires<[HasSSE41]>;
4231 //===----------------------------------------------------------------------===//
4232 // SSE4.1 - Round Instructions
4233 //===----------------------------------------------------------------------===//
4235 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4236 X86MemOperand x86memop, RegisterClass RC,
4237 PatFrag mem_frag32, PatFrag mem_frag64,
4238 Intrinsic V4F32Int, Intrinsic V2F64Int> {
4239 // Intrinsic operation, reg.
4240 // Vector intrinsic operation, reg
4241 def PSr : SS4AIi8<opcps, MRMSrcReg,
4242 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4243 !strconcat(OpcodeStr,
4244 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4245 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
4248 // Vector intrinsic operation, mem
4249 def PSm : Ii8<opcps, MRMSrcMem,
4250 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4251 !strconcat(OpcodeStr,
4252 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4254 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4256 Requires<[HasSSE41]>;
4258 // Vector intrinsic operation, reg
4259 def PDr : SS4AIi8<opcpd, MRMSrcReg,
4260 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4261 !strconcat(OpcodeStr,
4262 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4263 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
4266 // Vector intrinsic operation, mem
4267 def PDm : SS4AIi8<opcpd, MRMSrcMem,
4268 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4269 !strconcat(OpcodeStr,
4270 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4272 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4276 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
4277 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
4278 // Intrinsic operation, reg.
4279 // Vector intrinsic operation, reg
4280 def PSr_AVX : SS4AIi8<opcps, MRMSrcReg,
4281 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4282 !strconcat(OpcodeStr,
4283 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4286 // Vector intrinsic operation, mem
4287 def PSm_AVX : Ii8<opcps, MRMSrcMem,
4288 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4289 !strconcat(OpcodeStr,
4290 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4291 []>, TA, OpSize, Requires<[HasSSE41]>;
4293 // Vector intrinsic operation, reg
4294 def PDr_AVX : SS4AIi8<opcpd, MRMSrcReg,
4295 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4296 !strconcat(OpcodeStr,
4297 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4300 // Vector intrinsic operation, mem
4301 def PDm_AVX : SS4AIi8<opcpd, MRMSrcMem,
4302 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4303 !strconcat(OpcodeStr,
4304 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4308 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4311 Intrinsic F64Int, bit Is2Addr = 1> {
4312 // Intrinsic operation, reg.
4313 def SSr : SS4AIi8<opcss, MRMSrcReg,
4314 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4316 !strconcat(OpcodeStr,
4317 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4318 !strconcat(OpcodeStr,
4319 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4320 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4323 // Intrinsic operation, mem.
4324 def SSm : SS4AIi8<opcss, MRMSrcMem,
4325 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4327 !strconcat(OpcodeStr,
4328 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4329 !strconcat(OpcodeStr,
4330 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4332 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
4335 // Intrinsic operation, reg.
4336 def SDr : SS4AIi8<opcsd, MRMSrcReg,
4337 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4339 !strconcat(OpcodeStr,
4340 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4341 !strconcat(OpcodeStr,
4342 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4343 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4346 // Intrinsic operation, mem.
4347 def SDm : SS4AIi8<opcsd, MRMSrcMem,
4348 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4350 !strconcat(OpcodeStr,
4351 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4352 !strconcat(OpcodeStr,
4353 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4355 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
4359 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
4361 // Intrinsic operation, reg.
4362 def SSr_AVX : SS4AIi8<opcss, MRMSrcReg,
4363 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4364 !strconcat(OpcodeStr,
4365 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4368 // Intrinsic operation, mem.
4369 def SSm_AVX : SS4AIi8<opcss, MRMSrcMem,
4370 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4371 !strconcat(OpcodeStr,
4372 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4375 // Intrinsic operation, reg.
4376 def SDr_AVX : SS4AIi8<opcsd, MRMSrcReg,
4377 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4378 !strconcat(OpcodeStr,
4379 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4382 // Intrinsic operation, mem.
4383 def SDm_AVX : SS4AIi8<opcsd, MRMSrcMem,
4384 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4385 !strconcat(OpcodeStr,
4386 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4390 // FP round - roundss, roundps, roundsd, roundpd
4391 let Predicates = [HasAVX] in {
4393 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
4394 memopv4f32, memopv2f64,
4395 int_x86_sse41_round_ps,
4396 int_x86_sse41_round_pd>, VEX;
4397 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
4398 memopv8f32, memopv4f64,
4399 int_x86_avx_round_ps_256,
4400 int_x86_avx_round_pd_256>, VEX;
4401 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
4402 int_x86_sse41_round_ss,
4403 int_x86_sse41_round_sd, 0>, VEX_4V;
4405 // Instructions for the assembler
4406 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
4408 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
4410 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
4413 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
4414 memopv4f32, memopv2f64,
4415 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
4416 let Constraints = "$src1 = $dst" in
4417 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
4418 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
4420 //===----------------------------------------------------------------------===//
4421 // SSE4.1 - Packed Bit Test
4422 //===----------------------------------------------------------------------===//
4424 // ptest instruction we'll lower to this in X86ISelLowering primarily from
4425 // the intel intrinsic that corresponds to this.
4426 let Defs = [EFLAGS], Predicates = [HasAVX] in {
4427 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4428 "vptest\t{$src2, $src1|$src1, $src2}",
4429 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4431 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4432 "vptest\t{$src2, $src1|$src1, $src2}",
4433 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4436 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
4437 "vptest\t{$src2, $src1|$src1, $src2}",
4438 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
4440 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
4441 "vptest\t{$src2, $src1|$src1, $src2}",
4442 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
4446 let Defs = [EFLAGS] in {
4447 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4448 "ptest \t{$src2, $src1|$src1, $src2}",
4449 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4451 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4452 "ptest \t{$src2, $src1|$src1, $src2}",
4453 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4457 // The bit test instructions below are AVX only
4458 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
4459 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
4460 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
4461 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4462 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
4463 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
4464 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4465 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
4469 let Defs = [EFLAGS], Predicates = [HasAVX] in {
4470 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
4471 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
4472 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
4473 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
4476 //===----------------------------------------------------------------------===//
4477 // SSE4.1 - Misc Instructions
4478 //===----------------------------------------------------------------------===//
4480 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4481 "popcnt{w}\t{$src, $dst|$dst, $src}",
4482 [(set GR16:$dst, (ctpop GR16:$src))]>, OpSize, XS;
4483 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4484 "popcnt{w}\t{$src, $dst|$dst, $src}",
4485 [(set GR16:$dst, (ctpop (loadi16 addr:$src)))]>, OpSize, XS;
4487 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4488 "popcnt{l}\t{$src, $dst|$dst, $src}",
4489 [(set GR32:$dst, (ctpop GR32:$src))]>, XS;
4490 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4491 "popcnt{l}\t{$src, $dst|$dst, $src}",
4492 [(set GR32:$dst, (ctpop (loadi32 addr:$src)))]>, XS;
4494 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4495 "popcnt{q}\t{$src, $dst|$dst, $src}",
4496 [(set GR64:$dst, (ctpop GR64:$src))]>, XS;
4497 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4498 "popcnt{q}\t{$src, $dst|$dst, $src}",
4499 [(set GR64:$dst, (ctpop (loadi64 addr:$src)))]>, XS;
4503 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
4504 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
4505 Intrinsic IntId128> {
4506 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4508 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4509 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
4510 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4512 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4515 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
4518 let Predicates = [HasAVX] in
4519 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
4520 int_x86_sse41_phminposuw>, VEX;
4521 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
4522 int_x86_sse41_phminposuw>;
4524 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
4525 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
4526 Intrinsic IntId128, bit Is2Addr = 1> {
4527 let isCommutable = 1 in
4528 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4529 (ins VR128:$src1, VR128:$src2),
4531 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4532 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4533 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
4534 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4535 (ins VR128:$src1, i128mem:$src2),
4537 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4538 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4540 (IntId128 VR128:$src1,
4541 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4544 let Predicates = [HasAVX] in {
4545 let isCommutable = 0 in
4546 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
4548 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
4550 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
4552 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
4554 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
4556 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
4558 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
4560 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
4562 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
4564 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
4566 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
4570 let Constraints = "$src1 = $dst" in {
4571 let isCommutable = 0 in
4572 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
4573 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
4574 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
4575 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
4576 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
4577 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
4578 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
4579 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
4580 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
4581 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
4582 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
4585 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
4586 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
4587 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
4588 (PCMPEQQrm VR128:$src1, addr:$src2)>;
4590 /// SS48I_binop_rm - Simple SSE41 binary operator.
4591 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4592 ValueType OpVT, bit Is2Addr = 1> {
4593 let isCommutable = 1 in
4594 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4595 (ins VR128:$src1, VR128:$src2),
4597 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4598 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4599 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
4601 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4602 (ins VR128:$src1, i128mem:$src2),
4604 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4605 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4606 [(set VR128:$dst, (OpNode VR128:$src1,
4607 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
4611 let Predicates = [HasAVX] in
4612 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
4613 let Constraints = "$src1 = $dst" in
4614 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
4616 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
4617 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
4618 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
4619 X86MemOperand x86memop, bit Is2Addr = 1> {
4620 let isCommutable = 1 in
4621 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
4622 (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4624 !strconcat(OpcodeStr,
4625 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4626 !strconcat(OpcodeStr,
4627 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4628 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
4630 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
4631 (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4633 !strconcat(OpcodeStr,
4634 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4635 !strconcat(OpcodeStr,
4636 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4639 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
4643 let Predicates = [HasAVX] in {
4644 let isCommutable = 0 in {
4645 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
4646 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4647 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
4648 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4649 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
4650 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4651 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
4652 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4653 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
4654 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4655 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
4656 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4658 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
4659 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4660 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
4661 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4662 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
4663 VR256, memopv32i8, i256mem, 0>, VEX_4V;
4666 let Constraints = "$src1 = $dst" in {
4667 let isCommutable = 0 in {
4668 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
4669 VR128, memopv16i8, i128mem>;
4670 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
4671 VR128, memopv16i8, i128mem>;
4672 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
4673 VR128, memopv16i8, i128mem>;
4674 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
4675 VR128, memopv16i8, i128mem>;
4677 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
4678 VR128, memopv16i8, i128mem>;
4679 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
4680 VR128, memopv16i8, i128mem>;
4683 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
4684 let Predicates = [HasAVX] in {
4685 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
4686 RegisterClass RC, X86MemOperand x86memop,
4687 PatFrag mem_frag, Intrinsic IntId> {
4688 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
4689 (ins RC:$src1, RC:$src2, RC:$src3),
4690 !strconcat(OpcodeStr,
4691 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4692 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
4693 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4695 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
4696 (ins RC:$src1, x86memop:$src2, RC:$src3),
4697 !strconcat(OpcodeStr,
4698 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4700 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
4702 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4706 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
4707 memopv16i8, int_x86_sse41_blendvpd>;
4708 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
4709 memopv16i8, int_x86_sse41_blendvps>;
4710 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
4711 memopv16i8, int_x86_sse41_pblendvb>;
4712 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
4713 memopv32i8, int_x86_avx_blendv_pd_256>;
4714 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
4715 memopv32i8, int_x86_avx_blendv_ps_256>;
4717 /// SS41I_ternary_int - SSE 4.1 ternary operator
4718 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
4719 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4720 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4721 (ins VR128:$src1, VR128:$src2),
4722 !strconcat(OpcodeStr,
4723 "\t{$src2, $dst|$dst, $src2}"),
4724 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
4727 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4728 (ins VR128:$src1, i128mem:$src2),
4729 !strconcat(OpcodeStr,
4730 "\t{$src2, $dst|$dst, $src2}"),
4733 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
4737 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
4738 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
4739 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
4741 def : Pat<(X86pblendv VR128:$src1, VR128:$src2, XMM0),
4742 (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
4744 let Predicates = [HasAVX] in
4745 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4746 "vmovntdqa\t{$src, $dst|$dst, $src}",
4747 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4749 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4750 "movntdqa\t{$src, $dst|$dst, $src}",
4751 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4754 //===----------------------------------------------------------------------===//
4755 // SSE4.2 - Compare Instructions
4756 //===----------------------------------------------------------------------===//
4758 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
4759 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
4760 Intrinsic IntId128, bit Is2Addr = 1> {
4761 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
4762 (ins VR128:$src1, VR128:$src2),
4764 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4765 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4766 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4768 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
4769 (ins VR128:$src1, i128mem:$src2),
4771 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4772 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4774 (IntId128 VR128:$src1,
4775 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4778 let Predicates = [HasAVX] in
4779 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
4781 let Constraints = "$src1 = $dst" in
4782 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
4784 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
4785 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
4786 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
4787 (PCMPGTQrm VR128:$src1, addr:$src2)>;
4789 //===----------------------------------------------------------------------===//
4790 // SSE4.2 - String/text Processing Instructions
4791 //===----------------------------------------------------------------------===//
4793 // Packed Compare Implicit Length Strings, Return Mask
4794 multiclass pseudo_pcmpistrm<string asm> {
4795 def REG : PseudoI<(outs VR128:$dst),
4796 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4797 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
4799 def MEM : PseudoI<(outs VR128:$dst),
4800 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4801 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
4802 VR128:$src1, (load addr:$src2), imm:$src3))]>;
4805 let Defs = [EFLAGS], usesCustomInserter = 1 in {
4806 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
4807 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
4810 let Defs = [XMM0, EFLAGS], Predicates = [HasAVX] in {
4811 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4812 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4813 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
4814 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4815 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4816 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
4819 let Defs = [XMM0, EFLAGS] in {
4820 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4821 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4822 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4823 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4824 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4825 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4828 // Packed Compare Explicit Length Strings, Return Mask
4829 multiclass pseudo_pcmpestrm<string asm> {
4830 def REG : PseudoI<(outs VR128:$dst),
4831 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4832 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4833 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
4834 def MEM : PseudoI<(outs VR128:$dst),
4835 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4836 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4837 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
4840 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
4841 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
4842 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
4845 let Predicates = [HasAVX],
4846 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4847 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4848 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4849 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
4850 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4851 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4852 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
4855 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4856 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4857 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4858 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4859 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4860 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4861 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4864 // Packed Compare Implicit Length Strings, Return Index
4865 let Defs = [ECX, EFLAGS] in {
4866 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
4867 def rr : SS42AI<0x63, MRMSrcReg, (outs),
4868 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4869 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
4870 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
4871 (implicit EFLAGS)]>, OpSize;
4872 def rm : SS42AI<0x63, MRMSrcMem, (outs),
4873 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4874 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
4875 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
4876 (implicit EFLAGS)]>, OpSize;
4880 let Predicates = [HasAVX] in {
4881 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
4883 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
4885 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
4887 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
4889 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
4891 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
4895 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
4896 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
4897 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
4898 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
4899 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
4900 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
4902 // Packed Compare Explicit Length Strings, Return Index
4903 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
4904 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
4905 def rr : SS42AI<0x61, MRMSrcReg, (outs),
4906 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4907 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
4908 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
4909 (implicit EFLAGS)]>, OpSize;
4910 def rm : SS42AI<0x61, MRMSrcMem, (outs),
4911 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4912 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
4914 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
4915 (implicit EFLAGS)]>, OpSize;
4919 let Predicates = [HasAVX] in {
4920 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
4922 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
4924 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
4926 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
4928 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
4930 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
4934 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
4935 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
4936 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
4937 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
4938 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
4939 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
4941 //===----------------------------------------------------------------------===//
4942 // SSE4.2 - CRC Instructions
4943 //===----------------------------------------------------------------------===//
4945 // No CRC instructions have AVX equivalents
4947 // crc intrinsic instruction
4948 // This set of instructions are only rm, the only difference is the size
4950 let Constraints = "$src1 = $dst" in {
4951 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
4952 (ins GR32:$src1, i8mem:$src2),
4953 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4955 (int_x86_sse42_crc32_32_8 GR32:$src1,
4956 (load addr:$src2)))]>;
4957 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
4958 (ins GR32:$src1, GR8:$src2),
4959 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4961 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
4962 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
4963 (ins GR32:$src1, i16mem:$src2),
4964 "crc32{w} \t{$src2, $src1|$src1, $src2}",
4966 (int_x86_sse42_crc32_32_16 GR32:$src1,
4967 (load addr:$src2)))]>,
4969 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
4970 (ins GR32:$src1, GR16:$src2),
4971 "crc32{w} \t{$src2, $src1|$src1, $src2}",
4973 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
4975 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
4976 (ins GR32:$src1, i32mem:$src2),
4977 "crc32{l} \t{$src2, $src1|$src1, $src2}",
4979 (int_x86_sse42_crc32_32_32 GR32:$src1,
4980 (load addr:$src2)))]>;
4981 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
4982 (ins GR32:$src1, GR32:$src2),
4983 "crc32{l} \t{$src2, $src1|$src1, $src2}",
4985 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
4986 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
4987 (ins GR64:$src1, i8mem:$src2),
4988 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4990 (int_x86_sse42_crc32_64_8 GR64:$src1,
4991 (load addr:$src2)))]>,
4993 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
4994 (ins GR64:$src1, GR8:$src2),
4995 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4997 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
4999 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
5000 (ins GR64:$src1, i64mem:$src2),
5001 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5003 (int_x86_sse42_crc32_64_64 GR64:$src1,
5004 (load addr:$src2)))]>,
5006 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
5007 (ins GR64:$src1, GR64:$src2),
5008 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5010 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
5014 //===----------------------------------------------------------------------===//
5015 // AES-NI Instructions
5016 //===----------------------------------------------------------------------===//
5018 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
5019 Intrinsic IntId128, bit Is2Addr = 1> {
5020 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
5021 (ins VR128:$src1, VR128:$src2),
5023 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5024 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5025 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5027 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
5028 (ins VR128:$src1, i128mem:$src2),
5030 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5031 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5033 (IntId128 VR128:$src1,
5034 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5037 // Perform One Round of an AES Encryption/Decryption Flow
5038 let Predicates = [HasAVX, HasAES] in {
5039 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
5040 int_x86_aesni_aesenc, 0>, VEX_4V;
5041 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
5042 int_x86_aesni_aesenclast, 0>, VEX_4V;
5043 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
5044 int_x86_aesni_aesdec, 0>, VEX_4V;
5045 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
5046 int_x86_aesni_aesdeclast, 0>, VEX_4V;
5049 let Constraints = "$src1 = $dst" in {
5050 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
5051 int_x86_aesni_aesenc>;
5052 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
5053 int_x86_aesni_aesenclast>;
5054 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
5055 int_x86_aesni_aesdec>;
5056 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
5057 int_x86_aesni_aesdeclast>;
5060 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
5061 (AESENCrr VR128:$src1, VR128:$src2)>;
5062 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
5063 (AESENCrm VR128:$src1, addr:$src2)>;
5064 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
5065 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
5066 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
5067 (AESENCLASTrm VR128:$src1, addr:$src2)>;
5068 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
5069 (AESDECrr VR128:$src1, VR128:$src2)>;
5070 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
5071 (AESDECrm VR128:$src1, addr:$src2)>;
5072 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
5073 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
5074 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
5075 (AESDECLASTrm VR128:$src1, addr:$src2)>;
5077 // Perform the AES InvMixColumn Transformation
5078 let Predicates = [HasAVX, HasAES] in {
5079 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5081 "vaesimc\t{$src1, $dst|$dst, $src1}",
5083 (int_x86_aesni_aesimc VR128:$src1))]>,
5085 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5086 (ins i128mem:$src1),
5087 "vaesimc\t{$src1, $dst|$dst, $src1}",
5089 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5092 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5094 "aesimc\t{$src1, $dst|$dst, $src1}",
5096 (int_x86_aesni_aesimc VR128:$src1))]>,
5098 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5099 (ins i128mem:$src1),
5100 "aesimc\t{$src1, $dst|$dst, $src1}",
5102 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5105 // AES Round Key Generation Assist
5106 let Predicates = [HasAVX, HasAES] in {
5107 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5108 (ins VR128:$src1, i8imm:$src2),
5109 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5111 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5113 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5114 (ins i128mem:$src1, i8imm:$src2),
5115 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5117 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5121 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5122 (ins VR128:$src1, i8imm:$src2),
5123 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5125 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5127 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5128 (ins i128mem:$src1, i8imm:$src2),
5129 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5131 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5135 //===----------------------------------------------------------------------===//
5136 // CLMUL Instructions
5137 //===----------------------------------------------------------------------===//
5139 // Only the AVX version of CLMUL instructions are described here.
5141 // Carry-less Multiplication instructions
5142 def VPCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5143 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5144 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5147 def VPCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5148 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5149 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5153 multiclass avx_vpclmul<string asm> {
5154 def rr : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
5155 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5158 def rm : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
5159 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5162 defm VPCLMULHQHQDQ : avx_vpclmul<"vpclmulhqhqdq">;
5163 defm VPCLMULHQLQDQ : avx_vpclmul<"vpclmulhqlqdq">;
5164 defm VPCLMULLQHQDQ : avx_vpclmul<"vpclmullqhqdq">;
5165 defm VPCLMULLQLQDQ : avx_vpclmul<"vpclmullqlqdq">;
5167 //===----------------------------------------------------------------------===//
5169 //===----------------------------------------------------------------------===//
5172 // Load from memory and broadcast to all elements of the destination operand
5173 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
5174 X86MemOperand x86memop, Intrinsic Int> :
5175 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5176 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5177 [(set RC:$dst, (Int addr:$src))]>, VEX;
5179 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
5180 int_x86_avx_vbroadcastss>;
5181 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
5182 int_x86_avx_vbroadcastss_256>;
5183 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
5184 int_x86_avx_vbroadcast_sd_256>;
5185 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
5186 int_x86_avx_vbroadcastf128_pd_256>;
5188 // Insert packed floating-point values
5189 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
5190 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
5191 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5193 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
5194 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
5195 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5198 // Extract packed floating-point values
5199 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
5200 (ins VR256:$src1, i8imm:$src2),
5201 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5203 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
5204 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
5205 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5208 // Conditional SIMD Packed Loads and Stores
5209 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
5210 Intrinsic IntLd, Intrinsic IntLd256,
5211 Intrinsic IntSt, Intrinsic IntSt256,
5212 PatFrag pf128, PatFrag pf256> {
5213 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
5214 (ins VR128:$src1, f128mem:$src2),
5215 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5216 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
5218 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
5219 (ins VR256:$src1, f256mem:$src2),
5220 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5221 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
5223 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
5224 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
5225 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5226 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
5227 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
5228 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
5229 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5230 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
5233 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
5234 int_x86_avx_maskload_ps,
5235 int_x86_avx_maskload_ps_256,
5236 int_x86_avx_maskstore_ps,
5237 int_x86_avx_maskstore_ps_256,
5238 memopv4f32, memopv8f32>;
5239 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
5240 int_x86_avx_maskload_pd,
5241 int_x86_avx_maskload_pd_256,
5242 int_x86_avx_maskstore_pd,
5243 int_x86_avx_maskstore_pd_256,
5244 memopv2f64, memopv4f64>;
5246 // Permute Floating-Point Values
5247 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
5248 RegisterClass RC, X86MemOperand x86memop_f,
5249 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
5250 Intrinsic IntVar, Intrinsic IntImm> {
5251 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
5252 (ins RC:$src1, RC:$src2),
5253 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5254 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
5255 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
5256 (ins RC:$src1, x86memop_i:$src2),
5257 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5258 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
5260 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
5261 (ins RC:$src1, i8imm:$src2),
5262 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5263 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
5264 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
5265 (ins x86memop_f:$src1, i8imm:$src2),
5266 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5267 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
5270 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
5271 memopv4f32, memopv4i32,
5272 int_x86_avx_vpermilvar_ps,
5273 int_x86_avx_vpermil_ps>;
5274 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
5275 memopv8f32, memopv8i32,
5276 int_x86_avx_vpermilvar_ps_256,
5277 int_x86_avx_vpermil_ps_256>;
5278 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
5279 memopv2f64, memopv2i64,
5280 int_x86_avx_vpermilvar_pd,
5281 int_x86_avx_vpermil_pd>;
5282 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
5283 memopv4f64, memopv4i64,
5284 int_x86_avx_vpermilvar_pd_256,
5285 int_x86_avx_vpermil_pd_256>;
5287 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
5288 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5289 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5291 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
5292 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
5293 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5296 // Zero All YMM registers
5297 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
5298 [(int_x86_avx_vzeroall)]>, VEX, VEX_L, Requires<[HasAVX]>;
5300 // Zero Upper bits of YMM registers
5301 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
5302 [(int_x86_avx_vzeroupper)]>, VEX, Requires<[HasAVX]>;
5304 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
5305 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5306 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
5307 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5308 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
5309 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5311 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
5313 (VINSERTF128rr VR256:$src1, VR128:$src2,
5314 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5315 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
5317 (VINSERTF128rr VR256:$src1, VR128:$src2,
5318 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5319 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
5321 (VINSERTF128rr VR256:$src1, VR128:$src2,
5322 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5323 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
5325 (VINSERTF128rr VR256:$src1, VR128:$src2,
5326 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5328 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
5329 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5330 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
5331 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5332 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
5333 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5335 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5336 (v4f32 (VEXTRACTF128rr
5337 (v8f32 VR256:$src1),
5338 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5339 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5340 (v2f64 (VEXTRACTF128rr
5341 (v4f64 VR256:$src1),
5342 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5343 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5344 (v4i32 (VEXTRACTF128rr
5345 (v8i32 VR256:$src1),
5346 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5347 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5348 (v2i64 (VEXTRACTF128rr
5349 (v4i64 VR256:$src1),
5350 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5352 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
5353 (VBROADCASTF128 addr:$src)>;
5355 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
5356 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5357 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
5358 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5359 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
5360 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5362 def : Pat<(int_x86_avx_vperm2f128_ps_256
5363 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
5364 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5365 def : Pat<(int_x86_avx_vperm2f128_pd_256
5366 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
5367 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5368 def : Pat<(int_x86_avx_vperm2f128_si_256
5369 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
5370 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5372 //===----------------------------------------------------------------------===//
5373 // SSE Shuffle pattern fragments
5374 //===----------------------------------------------------------------------===//
5376 // This is part of a "work in progress" refactoring. The idea is that all
5377 // vector shuffles are going to be translated into target specific nodes and
5378 // directly matched by the patterns below (which can be changed along the way)
5379 // The AVX version of some but not all of them are described here, and more
5380 // should come in a near future.
5382 // Shuffle with PSHUFD instruction folding loads. The first two patterns match
5383 // SSE2 loads, which are always promoted to v2i64. The last one should match
5384 // the SSE1 case, where the only legal load is v4f32, but there is no PSHUFD
5385 // in SSE2, how does it ever worked? Anyway, the pattern will remain here until
5386 // we investigate further.
5387 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5389 (VPSHUFDmi addr:$src1, imm:$imm)>, Requires<[HasAVX]>;
5390 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5392 (PSHUFDmi addr:$src1, imm:$imm)>;
5393 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
5395 (PSHUFDmi addr:$src1, imm:$imm)>; // FIXME: has this ever worked?
5397 // Shuffle with PSHUFD instruction.
5398 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5399 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5400 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5401 (PSHUFDri VR128:$src1, imm:$imm)>;
5403 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5404 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5405 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5406 (PSHUFDri VR128:$src1, imm:$imm)>;
5408 // Shuffle with SHUFPD instruction.
5409 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5410 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5411 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5412 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5413 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5414 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
5416 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5417 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5418 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5419 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5421 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5422 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5423 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5424 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5426 // Shuffle with SHUFPS instruction.
5427 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5428 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5429 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5430 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5431 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5432 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5434 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5435 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5436 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5437 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5439 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5440 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5441 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5442 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5443 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5444 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5446 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5447 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5448 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5449 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5451 // Shuffle with MOVHLPS instruction
5452 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
5453 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5454 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
5455 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5457 // Shuffle with MOVDDUP instruction
5458 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5459 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5460 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5461 (MOVDDUPrm addr:$src)>;
5463 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5464 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5465 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5466 (MOVDDUPrm addr:$src)>;
5468 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5469 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5470 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5471 (MOVDDUPrm addr:$src)>;
5473 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5474 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5475 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5476 (MOVDDUPrm addr:$src)>;
5478 def : Pat<(X86Movddup (bc_v2f64
5479 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5480 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5481 def : Pat<(X86Movddup (bc_v2f64
5482 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5483 (MOVDDUPrm addr:$src)>;
5486 // Shuffle with UNPCKLPS
5487 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
5488 (VUNPCKLPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5489 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
5490 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5491 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
5492 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
5494 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
5495 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5496 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
5497 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5498 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
5499 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
5501 // Shuffle with UNPCKHPS
5502 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
5503 (VUNPCKHPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5504 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
5505 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
5507 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
5508 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5509 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
5510 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
5512 // Shuffle with UNPCKLPD
5513 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
5514 (VUNPCKLPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5515 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
5516 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5517 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
5518 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
5520 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
5521 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5522 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
5523 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5524 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
5525 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
5527 // Shuffle with UNPCKHPD
5528 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
5529 (VUNPCKHPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5530 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
5531 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
5533 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
5534 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5535 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
5536 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
5538 // Shuffle with PUNPCKLBW
5539 def : Pat<(v16i8 (X86Punpcklbw VR128:$src1,
5540 (bc_v16i8 (memopv2i64 addr:$src2)))),
5541 (PUNPCKLBWrm VR128:$src1, addr:$src2)>;
5542 def : Pat<(v16i8 (X86Punpcklbw VR128:$src1, VR128:$src2)),
5543 (PUNPCKLBWrr VR128:$src1, VR128:$src2)>;
5545 // Shuffle with PUNPCKLWD
5546 def : Pat<(v8i16 (X86Punpcklwd VR128:$src1,
5547 (bc_v8i16 (memopv2i64 addr:$src2)))),
5548 (PUNPCKLWDrm VR128:$src1, addr:$src2)>;
5549 def : Pat<(v8i16 (X86Punpcklwd VR128:$src1, VR128:$src2)),
5550 (PUNPCKLWDrr VR128:$src1, VR128:$src2)>;
5552 // Shuffle with PUNPCKLDQ
5553 def : Pat<(v4i32 (X86Punpckldq VR128:$src1,
5554 (bc_v4i32 (memopv2i64 addr:$src2)))),
5555 (PUNPCKLDQrm VR128:$src1, addr:$src2)>;
5556 def : Pat<(v4i32 (X86Punpckldq VR128:$src1, VR128:$src2)),
5557 (PUNPCKLDQrr VR128:$src1, VR128:$src2)>;
5559 // Shuffle with PUNPCKLQDQ
5560 def : Pat<(v2i64 (X86Punpcklqdq VR128:$src1, (memopv2i64 addr:$src2))),
5561 (PUNPCKLQDQrm VR128:$src1, addr:$src2)>;
5562 def : Pat<(v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)),
5563 (PUNPCKLQDQrr VR128:$src1, VR128:$src2)>;
5565 // Shuffle with PUNPCKHBW
5566 def : Pat<(v16i8 (X86Punpckhbw VR128:$src1,
5567 (bc_v16i8 (memopv2i64 addr:$src2)))),
5568 (PUNPCKHBWrm VR128:$src1, addr:$src2)>;
5569 def : Pat<(v16i8 (X86Punpckhbw VR128:$src1, VR128:$src2)),
5570 (PUNPCKHBWrr VR128:$src1, VR128:$src2)>;
5572 // Shuffle with PUNPCKHWD
5573 def : Pat<(v8i16 (X86Punpckhwd VR128:$src1,
5574 (bc_v8i16 (memopv2i64 addr:$src2)))),
5575 (PUNPCKHWDrm VR128:$src1, addr:$src2)>;
5576 def : Pat<(v8i16 (X86Punpckhwd VR128:$src1, VR128:$src2)),
5577 (PUNPCKHWDrr VR128:$src1, VR128:$src2)>;
5579 // Shuffle with PUNPCKHDQ
5580 def : Pat<(v4i32 (X86Punpckhdq VR128:$src1,
5581 (bc_v4i32 (memopv2i64 addr:$src2)))),
5582 (PUNPCKHDQrm VR128:$src1, addr:$src2)>;
5583 def : Pat<(v4i32 (X86Punpckhdq VR128:$src1, VR128:$src2)),
5584 (PUNPCKHDQrr VR128:$src1, VR128:$src2)>;
5586 // Shuffle with PUNPCKHQDQ
5587 def : Pat<(v2i64 (X86Punpckhqdq VR128:$src1, (memopv2i64 addr:$src2))),
5588 (PUNPCKHQDQrm VR128:$src1, addr:$src2)>;
5589 def : Pat<(v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)),
5590 (PUNPCKHQDQrr VR128:$src1, VR128:$src2)>;
5592 // Shuffle with MOVLHPS
5593 def : Pat<(X86Movlhps VR128:$src1,
5594 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
5595 (MOVHPSrm VR128:$src1, addr:$src2)>;
5596 def : Pat<(X86Movlhps VR128:$src1,
5597 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
5598 (MOVHPSrm VR128:$src1, addr:$src2)>;
5599 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
5600 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
5601 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
5602 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
5603 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
5604 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
5606 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the problem
5607 // is during lowering, where it's not possible to recognize the load fold cause
5608 // it has two uses through a bitcast. One use disappears at isel time and the
5609 // fold opportunity reappears.
5610 def : Pat<(v2f64 (X86Movddup VR128:$src)),
5611 (UNPCKLPDrr VR128:$src, VR128:$src)>;
5613 // Shuffle with MOVLHPD
5614 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
5615 (scalar_to_vector (loadf64 addr:$src2)))),
5616 (MOVHPDrm VR128:$src1, addr:$src2)>;
5618 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
5619 // is during lowering, where it's not possible to recognize the load fold cause
5620 // it has two uses through a bitcast. One use disappears at isel time and the
5621 // fold opportunity reappears.
5622 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
5623 (scalar_to_vector (loadf64 addr:$src2)))),
5624 (MOVHPDrm VR128:$src1, addr:$src2)>;
5626 // Shuffle with MOVSS
5627 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
5628 (MOVSSrr VR128:$src1, FR32:$src2)>;
5629 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
5630 (MOVSSrr (v4i32 VR128:$src1),
5631 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
5632 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
5633 (MOVSSrr (v4f32 VR128:$src1),
5634 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
5635 // FIXME: Instead of a X86Movss there should be a X86Movlps here, the problem
5636 // is during lowering, where it's not possible to recognize the load fold cause
5637 // it has two uses through a bitcast. One use disappears at isel time and the
5638 // fold opportunity reappears.
5639 def : Pat<(X86Movss VR128:$src1,
5640 (bc_v4i32 (v2i64 (load addr:$src2)))),
5641 (MOVLPSrm VR128:$src1, addr:$src2)>;
5643 // Shuffle with MOVSD
5644 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
5645 (MOVSDrr VR128:$src1, FR64:$src2)>;
5646 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
5647 (MOVSDrr (v2i64 VR128:$src1),
5648 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
5649 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
5650 (MOVSDrr (v2f64 VR128:$src1),
5651 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
5652 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
5653 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
5654 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
5655 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
5657 // Shuffle with MOVSHDUP
5658 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5659 (MOVSHDUPrr VR128:$src)>;
5660 def : Pat<(X86Movshdup (bc_v4i32 (memopv2i64 addr:$src))),
5661 (MOVSHDUPrm addr:$src)>;
5663 def : Pat<(v4f32 (X86Movshdup VR128:$src)),
5664 (MOVSHDUPrr VR128:$src)>;
5665 def : Pat<(X86Movshdup (memopv4f32 addr:$src)),
5666 (MOVSHDUPrm addr:$src)>;
5668 // Shuffle with MOVSLDUP
5669 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5670 (MOVSLDUPrr VR128:$src)>;
5671 def : Pat<(X86Movsldup (bc_v4i32 (memopv2i64 addr:$src))),
5672 (MOVSLDUPrm addr:$src)>;
5674 def : Pat<(v4f32 (X86Movsldup VR128:$src)),
5675 (MOVSLDUPrr VR128:$src)>;
5676 def : Pat<(X86Movsldup (memopv4f32 addr:$src)),
5677 (MOVSLDUPrm addr:$src)>;
5679 // Shuffle with PSHUFHW
5680 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
5681 (PSHUFHWri VR128:$src, imm:$imm)>;
5682 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
5683 (PSHUFHWmi addr:$src, imm:$imm)>;
5685 // Shuffle with PSHUFLW
5686 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
5687 (PSHUFLWri VR128:$src, imm:$imm)>;
5688 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
5689 (PSHUFLWmi addr:$src, imm:$imm)>;
5691 // Shuffle with PALIGN
5692 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5693 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5694 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5695 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5696 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5697 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5698 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5699 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5701 // Shuffle with MOVLPS
5702 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
5703 (MOVLPSrm VR128:$src1, addr:$src2)>;
5704 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
5705 (MOVLPSrm VR128:$src1, addr:$src2)>;
5706 def : Pat<(X86Movlps VR128:$src1,
5707 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
5708 (MOVLPSrm VR128:$src1, addr:$src2)>;
5709 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
5710 // is during lowering, where it's not possible to recognize the load fold cause
5711 // it has two uses through a bitcast. One use disappears at isel time and the
5712 // fold opportunity reappears.
5713 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
5714 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
5716 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
5717 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
5719 // Shuffle with MOVLPD
5720 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
5721 (MOVLPDrm VR128:$src1, addr:$src2)>;
5722 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
5723 (MOVLPDrm VR128:$src1, addr:$src2)>;
5724 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
5725 (scalar_to_vector (loadf64 addr:$src2)))),
5726 (MOVLPDrm VR128:$src1, addr:$src2)>;
5728 // Extra patterns to match stores with MOVHPS/PD and MOVLPS/PD
5729 def : Pat<(store (f64 (vector_extract
5730 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))),addr:$dst),
5731 (MOVHPSmr addr:$dst, VR128:$src)>;
5732 def : Pat<(store (f64 (vector_extract
5733 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
5734 (MOVHPDmr addr:$dst, VR128:$src)>;
5736 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),addr:$src1),
5737 (MOVLPSmr addr:$src1, VR128:$src2)>;
5738 def : Pat<(store (v4i32 (X86Movlps
5739 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
5740 (MOVLPSmr addr:$src1, VR128:$src2)>;
5742 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
5743 (MOVLPDmr addr:$src1, VR128:$src2)>;
5744 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
5745 (MOVLPDmr addr:$src1, VR128:$src2)>;