1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 let isCommutable = 1 in
85 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
90 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
97 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
98 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
99 string asm, string SSEVer, string FPSizeStr,
100 X86MemOperand x86memop, PatFrag mem_frag,
101 Domain d, bit Is2Addr = 1> {
102 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
104 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
105 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
106 [(set RC:$dst, (!cast<Intrinsic>(
107 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
108 RC:$src1, RC:$src2))], d>;
109 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
111 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
113 [(set RC:$dst, (!cast<Intrinsic>(
114 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
115 RC:$src1, (mem_frag addr:$src2)))], d>;
118 //===----------------------------------------------------------------------===//
119 // Non-instruction patterns
120 //===----------------------------------------------------------------------===//
122 // A vector extract of the first f32/f64 position is a subregister copy
123 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
124 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
125 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
126 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
128 // A 128-bit subvector extract from the first 256-bit vector position
129 // is a subregister copy that needs no instruction.
130 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
131 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
132 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
133 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
135 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
136 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
137 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
138 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
140 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
141 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
142 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
143 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
145 // A 128-bit subvector insert to the first 256-bit vector position
146 // is a subregister copy that needs no instruction.
147 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
148 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
149 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
150 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
151 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
152 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
153 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
154 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
155 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
156 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
157 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
158 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
160 // Implicitly promote a 32-bit scalar to a vector.
161 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
162 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
163 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
164 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
165 // Implicitly promote a 64-bit scalar to a vector.
166 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
167 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
168 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
169 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
171 // Bitcasts between 128-bit vector types. Return the original type since
172 // no instruction is needed for the conversion
173 let Predicates = [HasXMMInt] in {
174 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
175 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
176 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
177 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
178 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
179 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
180 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
181 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
182 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
183 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
184 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
185 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
186 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
187 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
188 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
189 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
190 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
191 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
192 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
193 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
194 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
195 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
196 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
197 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
198 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
199 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
200 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
201 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
202 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
203 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
206 // Bitcasts between 256-bit vector types. Return the original type since
207 // no instruction is needed for the conversion
208 let Predicates = [HasAVX] in {
209 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
210 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
211 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
212 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
213 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
214 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
215 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
216 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
217 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
218 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
219 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
220 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
221 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
222 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
223 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
224 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
225 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
226 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
227 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
228 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
229 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
230 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
231 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
232 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
233 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
234 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
235 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
236 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
237 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
238 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
241 // Alias instructions that map fld0 to pxor for sse.
242 // FIXME: Set encoding to pseudo!
243 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
244 canFoldAsLoad = 1 in {
245 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
246 [(set FR32:$dst, fp32imm0)]>,
247 Requires<[HasSSE1]>, TB, OpSize;
248 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
249 [(set FR64:$dst, fpimm0)]>,
250 Requires<[HasSSE2]>, TB, OpSize;
251 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
252 [(set FR32:$dst, fp32imm0)]>,
253 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
254 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
255 [(set FR64:$dst, fpimm0)]>,
256 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
259 //===----------------------------------------------------------------------===//
260 // AVX & SSE - Zero/One Vectors
261 //===----------------------------------------------------------------------===//
263 // Alias instruction that maps zero vector to pxor / xorp* for sse.
264 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
265 // swizzled by ExecutionDepsFix to pxor.
266 // We set canFoldAsLoad because this can be converted to a constant-pool
267 // load of an all-zeros value if folding it would be beneficial.
268 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
270 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "", []>;
273 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
274 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
275 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
276 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
277 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
278 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
281 // The same as done above but for AVX. The 256-bit ISA does not support PI,
282 // and doesn't need it because on sandy bridge the register is set to zero
283 // at the rename stage without using any execution unit, so SET0PSY
284 // and SET0PDY can be used for vector int instructions without penalty
285 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
286 // JIT implementatioan, it does not expand the instructions below like
287 // X86MCInstLower does.
288 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
289 isCodeGenOnly = 1, Predicates = [HasAVX] in {
290 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
291 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
292 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
293 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
297 // AVX has no support for 256-bit integer instructions, but since the 128-bit
298 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
299 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
300 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
301 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
303 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
304 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
305 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
307 // We set canFoldAsLoad because this can be converted to a constant-pool
308 // load of an all-ones value if folding it would be beneficial.
309 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
310 // JIT implementation, it does not expand the instructions below like
311 // X86MCInstLower does.
312 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
313 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
314 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
315 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
316 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
317 isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in
318 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
319 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
322 //===----------------------------------------------------------------------===//
323 // SSE 1 & 2 - Move FP Scalar Instructions
325 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
326 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
327 // is used instead. Register-to-register movss/movsd is not modeled as an
328 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
329 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
330 //===----------------------------------------------------------------------===//
332 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
333 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
334 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
336 // Loading from memory automatically zeroing upper bits.
337 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
338 PatFrag mem_pat, string OpcodeStr> :
339 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
340 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
341 [(set RC:$dst, (mem_pat addr:$src))]>;
344 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
345 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
347 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
348 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
351 // For the disassembler
352 let isCodeGenOnly = 1 in {
353 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
354 (ins VR128:$src1, FR32:$src2),
355 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
357 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
358 (ins VR128:$src1, FR64:$src2),
359 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
363 let canFoldAsLoad = 1, isReMaterializable = 1 in {
364 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
366 let AddedComplexity = 20 in
367 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
371 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
372 "movss\t{$src, $dst|$dst, $src}",
373 [(store FR32:$src, addr:$dst)]>, XS, VEX, VEX_LIG;
374 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
375 "movsd\t{$src, $dst|$dst, $src}",
376 [(store FR64:$src, addr:$dst)]>, XD, VEX, VEX_LIG;
379 let Constraints = "$src1 = $dst" in {
380 def MOVSSrr : sse12_move_rr<FR32, v4f32,
381 "movss\t{$src2, $dst|$dst, $src2}">, XS;
382 def MOVSDrr : sse12_move_rr<FR64, v2f64,
383 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
385 // For the disassembler
386 let isCodeGenOnly = 1 in {
387 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
388 (ins VR128:$src1, FR32:$src2),
389 "movss\t{$src2, $dst|$dst, $src2}", []>, XS;
390 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
391 (ins VR128:$src1, FR64:$src2),
392 "movsd\t{$src2, $dst|$dst, $src2}", []>, XD;
396 let canFoldAsLoad = 1, isReMaterializable = 1 in {
397 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
399 let AddedComplexity = 20 in
400 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
403 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
404 "movss\t{$src, $dst|$dst, $src}",
405 [(store FR32:$src, addr:$dst)]>;
406 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
407 "movsd\t{$src, $dst|$dst, $src}",
408 [(store FR64:$src, addr:$dst)]>;
411 let Predicates = [HasSSE1] in {
412 let AddedComplexity = 15 in {
413 // Extract the low 32-bit value from one vector and insert it into another.
414 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
415 (MOVSSrr (v4f32 VR128:$src1),
416 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
417 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
418 (MOVSSrr (v4i32 VR128:$src1),
419 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
421 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
422 // MOVSS to the lower bits.
423 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
424 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
425 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
426 (MOVSSrr (v4f32 (V_SET0)),
427 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
428 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
429 (MOVSSrr (v4i32 (V_SET0)),
430 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
433 let AddedComplexity = 20 in {
434 // MOVSSrm zeros the high parts of the register; represent this
435 // with SUBREG_TO_REG.
436 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
437 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
438 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
439 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
440 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
441 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
444 // Extract and store.
445 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
448 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
450 // Shuffle with MOVSS
451 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
452 (MOVSSrr VR128:$src1, FR32:$src2)>;
453 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
454 (MOVSSrr (v4i32 VR128:$src1),
455 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
456 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
457 (MOVSSrr (v4f32 VR128:$src1),
458 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
461 let Predicates = [HasSSE2] in {
462 let AddedComplexity = 15 in {
463 // Extract the low 64-bit value from one vector and insert it into another.
464 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
465 (MOVSDrr (v2f64 VR128:$src1),
466 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
467 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
468 (MOVSDrr (v2i64 VR128:$src1),
469 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
471 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
472 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
473 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
474 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
475 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
477 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
478 // MOVSD to the lower bits.
479 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
480 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
483 let AddedComplexity = 20 in {
484 // MOVSDrm zeros the high parts of the register; represent this
485 // with SUBREG_TO_REG.
486 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
487 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
488 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
489 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
490 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
491 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
492 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
493 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
494 def : Pat<(v2f64 (X86vzload addr:$src)),
495 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
498 // Extract and store.
499 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
502 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
504 // Shuffle with MOVSD
505 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
506 (MOVSDrr VR128:$src1, FR64:$src2)>;
507 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
508 (MOVSDrr (v2i64 VR128:$src1),
509 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
510 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
511 (MOVSDrr (v2f64 VR128:$src1),
512 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
513 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
514 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
515 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
516 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
518 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
519 // is during lowering, where it's not possible to recognize the fold cause
520 // it has two uses through a bitcast. One use disappears at isel time and the
521 // fold opportunity reappears.
522 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
523 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
524 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
525 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
528 let Predicates = [HasAVX] in {
529 let AddedComplexity = 15 in {
530 // Extract the low 32-bit value from one vector and insert it into another.
531 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
532 (VMOVSSrr (v4f32 VR128:$src1),
533 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
534 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
535 (VMOVSSrr (v4i32 VR128:$src1),
536 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
538 // Extract the low 64-bit value from one vector and insert it into another.
539 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
540 (VMOVSDrr (v2f64 VR128:$src1),
541 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
542 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
543 (VMOVSDrr (v2i64 VR128:$src1),
544 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
546 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
547 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
548 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
549 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
550 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
552 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
553 // MOVS{S,D} to the lower bits.
554 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
555 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
556 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
557 (VMOVSSrr (v4f32 (V_SET0)),
558 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
559 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
560 (VMOVSSrr (v4i32 (V_SET0)),
561 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
562 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
563 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
566 let AddedComplexity = 20 in {
567 // MOVSSrm zeros the high parts of the register; represent this
568 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
569 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
570 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
571 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
572 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
573 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
574 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
576 // MOVSDrm zeros the high parts of the register; represent this
577 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
578 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
579 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
580 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
581 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
582 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
583 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
584 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
585 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
586 def : Pat<(v2f64 (X86vzload addr:$src)),
587 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
589 // Represent the same patterns above but in the form they appear for
591 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
592 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
593 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
594 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
595 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
596 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
598 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
599 (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
600 (SUBREG_TO_REG (i32 0),
601 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
603 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
604 (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
605 (SUBREG_TO_REG (i64 0),
606 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
609 // Extract and store.
610 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
613 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
614 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
617 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
619 // Shuffle with VMOVSS
620 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
621 (VMOVSSrr VR128:$src1, FR32:$src2)>;
622 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
623 (VMOVSSrr (v4i32 VR128:$src1),
624 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
625 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
626 (VMOVSSrr (v4f32 VR128:$src1),
627 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
629 // Shuffle with VMOVSD
630 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
631 (VMOVSDrr VR128:$src1, FR64:$src2)>;
632 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
633 (VMOVSDrr (v2i64 VR128:$src1),
634 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
635 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
636 (VMOVSDrr (v2f64 VR128:$src1),
637 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
638 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
639 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
641 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
642 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
645 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
646 // is during lowering, where it's not possible to recognize the fold cause
647 // it has two uses through a bitcast. One use disappears at isel time and the
648 // fold opportunity reappears.
649 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
650 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
652 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
653 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
657 //===----------------------------------------------------------------------===//
658 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
659 //===----------------------------------------------------------------------===//
661 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
662 X86MemOperand x86memop, PatFrag ld_frag,
663 string asm, Domain d,
664 bit IsReMaterializable = 1> {
665 let neverHasSideEffects = 1 in
666 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
667 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
668 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
669 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
670 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
671 [(set RC:$dst, (ld_frag addr:$src))], d>;
674 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
675 "movaps", SSEPackedSingle>, TB, VEX;
676 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
677 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
678 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
679 "movups", SSEPackedSingle>, TB, VEX;
680 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
681 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
683 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
684 "movaps", SSEPackedSingle>, TB, VEX;
685 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
686 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
687 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
688 "movups", SSEPackedSingle>, TB, VEX;
689 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
690 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
691 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
692 "movaps", SSEPackedSingle>, TB;
693 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
694 "movapd", SSEPackedDouble>, TB, OpSize;
695 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
696 "movups", SSEPackedSingle>, TB;
697 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
698 "movupd", SSEPackedDouble, 0>, TB, OpSize;
700 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
701 "movaps\t{$src, $dst|$dst, $src}",
702 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
703 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
704 "movapd\t{$src, $dst|$dst, $src}",
705 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
706 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
707 "movups\t{$src, $dst|$dst, $src}",
708 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
709 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
710 "movupd\t{$src, $dst|$dst, $src}",
711 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
712 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
713 "movaps\t{$src, $dst|$dst, $src}",
714 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)]>, VEX;
715 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
716 "movapd\t{$src, $dst|$dst, $src}",
717 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)]>, VEX;
718 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
719 "movups\t{$src, $dst|$dst, $src}",
720 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
721 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
722 "movupd\t{$src, $dst|$dst, $src}",
723 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
726 let isCodeGenOnly = 1 in {
727 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
729 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
730 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
732 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
733 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
735 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
736 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
738 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
739 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
741 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
742 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
744 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
745 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
747 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
748 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
750 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
753 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
754 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
755 (VMOVUPSYmr addr:$dst, VR256:$src)>;
757 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
758 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
759 (VMOVUPDYmr addr:$dst, VR256:$src)>;
761 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
762 "movaps\t{$src, $dst|$dst, $src}",
763 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
764 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
765 "movapd\t{$src, $dst|$dst, $src}",
766 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
767 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
768 "movups\t{$src, $dst|$dst, $src}",
769 [(store (v4f32 VR128:$src), addr:$dst)]>;
770 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
771 "movupd\t{$src, $dst|$dst, $src}",
772 [(store (v2f64 VR128:$src), addr:$dst)]>;
775 let isCodeGenOnly = 1 in {
776 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
777 "movaps\t{$src, $dst|$dst, $src}", []>;
778 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
779 "movapd\t{$src, $dst|$dst, $src}", []>;
780 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
781 "movups\t{$src, $dst|$dst, $src}", []>;
782 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
783 "movupd\t{$src, $dst|$dst, $src}", []>;
786 let Predicates = [HasAVX] in {
787 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
788 (VMOVUPSmr addr:$dst, VR128:$src)>;
789 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
790 (VMOVUPDmr addr:$dst, VR128:$src)>;
793 let Predicates = [HasSSE1] in
794 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
795 (MOVUPSmr addr:$dst, VR128:$src)>;
796 let Predicates = [HasSSE2] in
797 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
798 (MOVUPDmr addr:$dst, VR128:$src)>;
800 // Use movaps / movups for SSE integer load / store (one byte shorter).
801 // The instructions selected below are then converted to MOVDQA/MOVDQU
802 // during the SSE domain pass.
803 let Predicates = [HasSSE1] in {
804 def : Pat<(alignedloadv4i32 addr:$src),
805 (MOVAPSrm addr:$src)>;
806 def : Pat<(loadv4i32 addr:$src),
807 (MOVUPSrm addr:$src)>;
808 def : Pat<(alignedloadv2i64 addr:$src),
809 (MOVAPSrm addr:$src)>;
810 def : Pat<(loadv2i64 addr:$src),
811 (MOVUPSrm addr:$src)>;
813 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
814 (MOVAPSmr addr:$dst, VR128:$src)>;
815 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
816 (MOVAPSmr addr:$dst, VR128:$src)>;
817 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
818 (MOVAPSmr addr:$dst, VR128:$src)>;
819 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
820 (MOVAPSmr addr:$dst, VR128:$src)>;
821 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
822 (MOVUPSmr addr:$dst, VR128:$src)>;
823 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
824 (MOVUPSmr addr:$dst, VR128:$src)>;
825 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
826 (MOVUPSmr addr:$dst, VR128:$src)>;
827 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
828 (MOVUPSmr addr:$dst, VR128:$src)>;
831 // Use vmovaps/vmovups for AVX integer load/store.
832 let Predicates = [HasAVX] in {
833 // 128-bit load/store
834 def : Pat<(alignedloadv4i32 addr:$src),
835 (VMOVAPSrm addr:$src)>;
836 def : Pat<(loadv4i32 addr:$src),
837 (VMOVUPSrm addr:$src)>;
838 def : Pat<(alignedloadv2i64 addr:$src),
839 (VMOVAPSrm addr:$src)>;
840 def : Pat<(loadv2i64 addr:$src),
841 (VMOVUPSrm addr:$src)>;
843 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
844 (VMOVAPSmr addr:$dst, VR128:$src)>;
845 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
846 (VMOVAPSmr addr:$dst, VR128:$src)>;
847 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
848 (VMOVAPSmr addr:$dst, VR128:$src)>;
849 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
850 (VMOVAPSmr addr:$dst, VR128:$src)>;
851 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
852 (VMOVUPSmr addr:$dst, VR128:$src)>;
853 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
854 (VMOVUPSmr addr:$dst, VR128:$src)>;
855 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
856 (VMOVUPSmr addr:$dst, VR128:$src)>;
857 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
858 (VMOVUPSmr addr:$dst, VR128:$src)>;
860 // 256-bit load/store
861 def : Pat<(alignedloadv4i64 addr:$src),
862 (VMOVAPSYrm addr:$src)>;
863 def : Pat<(loadv4i64 addr:$src),
864 (VMOVUPSYrm addr:$src)>;
865 def : Pat<(alignedloadv8i32 addr:$src),
866 (VMOVAPSYrm addr:$src)>;
867 def : Pat<(loadv8i32 addr:$src),
868 (VMOVUPSYrm addr:$src)>;
869 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
870 (VMOVAPSYmr addr:$dst, VR256:$src)>;
871 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
872 (VMOVAPSYmr addr:$dst, VR256:$src)>;
873 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
874 (VMOVAPSYmr addr:$dst, VR256:$src)>;
875 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
876 (VMOVAPSYmr addr:$dst, VR256:$src)>;
877 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
878 (VMOVUPSYmr addr:$dst, VR256:$src)>;
879 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
880 (VMOVUPSYmr addr:$dst, VR256:$src)>;
881 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
882 (VMOVUPSYmr addr:$dst, VR256:$src)>;
883 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
884 (VMOVUPSYmr addr:$dst, VR256:$src)>;
887 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
888 // bits are disregarded. FIXME: Set encoding to pseudo!
889 let neverHasSideEffects = 1 in {
890 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
891 "movaps\t{$src, $dst|$dst, $src}", []>;
892 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
893 "movapd\t{$src, $dst|$dst, $src}", []>;
894 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
895 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
896 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
897 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
900 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
901 // bits are disregarded. FIXME: Set encoding to pseudo!
902 let canFoldAsLoad = 1, isReMaterializable = 1 in {
903 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
904 "movaps\t{$src, $dst|$dst, $src}",
905 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
906 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
907 "movapd\t{$src, $dst|$dst, $src}",
908 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
909 let isCodeGenOnly = 1 in {
910 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
911 "movaps\t{$src, $dst|$dst, $src}",
912 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>, VEX;
913 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
914 "movapd\t{$src, $dst|$dst, $src}",
915 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>, VEX;
919 //===----------------------------------------------------------------------===//
920 // SSE 1 & 2 - Move Low packed FP Instructions
921 //===----------------------------------------------------------------------===//
923 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
924 PatFrag mov_frag, string base_opc,
926 def PSrm : PI<opc, MRMSrcMem,
927 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
928 !strconcat(base_opc, "s", asm_opr),
931 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
932 SSEPackedSingle>, TB;
934 def PDrm : PI<opc, MRMSrcMem,
935 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
936 !strconcat(base_opc, "d", asm_opr),
937 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
938 (scalar_to_vector (loadf64 addr:$src2)))))],
939 SSEPackedDouble>, TB, OpSize;
942 let AddedComplexity = 20 in {
943 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
944 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
946 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
947 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
948 "\t{$src2, $dst|$dst, $src2}">;
951 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
952 "movlps\t{$src, $dst|$dst, $src}",
953 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
954 (iPTR 0))), addr:$dst)]>, VEX;
955 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
956 "movlpd\t{$src, $dst|$dst, $src}",
957 [(store (f64 (vector_extract (v2f64 VR128:$src),
958 (iPTR 0))), addr:$dst)]>, VEX;
959 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
960 "movlps\t{$src, $dst|$dst, $src}",
961 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
962 (iPTR 0))), addr:$dst)]>;
963 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
964 "movlpd\t{$src, $dst|$dst, $src}",
965 [(store (f64 (vector_extract (v2f64 VR128:$src),
966 (iPTR 0))), addr:$dst)]>;
968 let Predicates = [HasAVX] in {
969 let AddedComplexity = 20 in {
970 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
971 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
972 (VMOVLPSrm VR128:$src1, addr:$src2)>;
973 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
974 (VMOVLPSrm VR128:$src1, addr:$src2)>;
975 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
976 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
977 (VMOVLPDrm VR128:$src1, addr:$src2)>;
978 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
979 (VMOVLPDrm VR128:$src1, addr:$src2)>;
982 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
983 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
984 (VMOVLPSmr addr:$src1, VR128:$src2)>;
985 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
986 VR128:$src2)), addr:$src1),
987 (VMOVLPSmr addr:$src1, VR128:$src2)>;
989 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
990 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
991 (VMOVLPDmr addr:$src1, VR128:$src2)>;
992 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
993 (VMOVLPDmr addr:$src1, VR128:$src2)>;
995 // Shuffle with VMOVLPS
996 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
997 (VMOVLPSrm VR128:$src1, addr:$src2)>;
998 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
999 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1000 def : Pat<(X86Movlps VR128:$src1,
1001 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1002 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1004 // Shuffle with VMOVLPD
1005 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1006 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1007 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1008 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1009 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1010 (scalar_to_vector (loadf64 addr:$src2)))),
1011 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1014 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1016 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1017 def : Pat<(store (v4i32 (X86Movlps
1018 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1019 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1020 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1022 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1023 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1025 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1028 let Predicates = [HasSSE1] in {
1029 let AddedComplexity = 20 in {
1030 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
1031 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
1032 (MOVLPSrm VR128:$src1, addr:$src2)>;
1033 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
1034 (MOVLPSrm VR128:$src1, addr:$src2)>;
1037 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1038 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1039 (MOVLPSmr addr:$src1, VR128:$src2)>;
1040 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
1041 VR128:$src2)), addr:$src1),
1042 (MOVLPSmr addr:$src1, VR128:$src2)>;
1044 // Shuffle with MOVLPS
1045 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1046 (MOVLPSrm VR128:$src1, addr:$src2)>;
1047 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1048 (MOVLPSrm VR128:$src1, addr:$src2)>;
1049 def : Pat<(X86Movlps VR128:$src1,
1050 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1051 (MOVLPSrm VR128:$src1, addr:$src2)>;
1054 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1056 (MOVLPSmr addr:$src1, VR128:$src2)>;
1057 def : Pat<(store (v4i32 (X86Movlps
1058 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1060 (MOVLPSmr addr:$src1, VR128:$src2)>;
1063 let Predicates = [HasSSE2] in {
1064 let AddedComplexity = 20 in {
1065 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
1066 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
1067 (MOVLPDrm VR128:$src1, addr:$src2)>;
1068 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
1069 (MOVLPDrm VR128:$src1, addr:$src2)>;
1072 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
1073 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1074 (MOVLPDmr addr:$src1, VR128:$src2)>;
1075 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1076 (MOVLPDmr addr:$src1, VR128:$src2)>;
1078 // Shuffle with MOVLPD
1079 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1080 (MOVLPDrm VR128:$src1, addr:$src2)>;
1081 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1082 (MOVLPDrm VR128:$src1, addr:$src2)>;
1083 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1084 (scalar_to_vector (loadf64 addr:$src2)))),
1085 (MOVLPDrm VR128:$src1, addr:$src2)>;
1088 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1090 (MOVLPDmr addr:$src1, VR128:$src2)>;
1091 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1093 (MOVLPDmr addr:$src1, VR128:$src2)>;
1096 //===----------------------------------------------------------------------===//
1097 // SSE 1 & 2 - Move Hi packed FP Instructions
1098 //===----------------------------------------------------------------------===//
1100 let AddedComplexity = 20 in {
1101 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1102 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
1104 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1105 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1106 "\t{$src2, $dst|$dst, $src2}">;
1109 // v2f64 extract element 1 is always custom lowered to unpack high to low
1110 // and extract element 0 so the non-store version isn't too horrible.
1111 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1112 "movhps\t{$src, $dst|$dst, $src}",
1113 [(store (f64 (vector_extract
1114 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1115 (undef)), (iPTR 0))), addr:$dst)]>,
1117 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1118 "movhpd\t{$src, $dst|$dst, $src}",
1119 [(store (f64 (vector_extract
1120 (v2f64 (unpckh VR128:$src, (undef))),
1121 (iPTR 0))), addr:$dst)]>,
1123 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1124 "movhps\t{$src, $dst|$dst, $src}",
1125 [(store (f64 (vector_extract
1126 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1127 (undef)), (iPTR 0))), addr:$dst)]>;
1128 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1129 "movhpd\t{$src, $dst|$dst, $src}",
1130 [(store (f64 (vector_extract
1131 (v2f64 (unpckh VR128:$src, (undef))),
1132 (iPTR 0))), addr:$dst)]>;
1134 let Predicates = [HasAVX] in {
1136 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1137 (VMOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1138 def : Pat<(X86Movlhps VR128:$src1,
1139 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1140 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1141 def : Pat<(X86Movlhps VR128:$src1,
1142 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1143 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1145 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
1146 // is during lowering, where it's not possible to recognize the load fold cause
1147 // it has two uses through a bitcast. One use disappears at isel time and the
1148 // fold opportunity reappears.
1149 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
1150 (scalar_to_vector (loadf64 addr:$src2)))),
1151 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1153 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1154 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1155 (scalar_to_vector (loadf64 addr:$src2)))),
1156 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1159 def : Pat<(store (f64 (vector_extract
1160 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1161 (VMOVHPSmr addr:$dst, VR128:$src)>;
1162 def : Pat<(store (f64 (vector_extract
1163 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1164 (VMOVHPDmr addr:$dst, VR128:$src)>;
1167 let Predicates = [HasSSE1] in {
1169 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1170 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1171 def : Pat<(X86Movlhps VR128:$src1,
1172 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1173 (MOVHPSrm VR128:$src1, addr:$src2)>;
1174 def : Pat<(X86Movlhps VR128:$src1,
1175 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1176 (MOVHPSrm VR128:$src1, addr:$src2)>;
1179 def : Pat<(store (f64 (vector_extract
1180 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1181 (MOVHPSmr addr:$dst, VR128:$src)>;
1184 let Predicates = [HasSSE2] in {
1185 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
1186 // is during lowering, where it's not possible to recognize the load fold cause
1187 // it has two uses through a bitcast. One use disappears at isel time and the
1188 // fold opportunity reappears.
1189 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
1190 (scalar_to_vector (loadf64 addr:$src2)))),
1191 (MOVHPDrm VR128:$src1, addr:$src2)>;
1193 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1194 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1195 (scalar_to_vector (loadf64 addr:$src2)))),
1196 (MOVHPDrm VR128:$src1, addr:$src2)>;
1199 def : Pat<(store (f64 (vector_extract
1200 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
1201 (MOVHPDmr addr:$dst, VR128:$src)>;
1204 //===----------------------------------------------------------------------===//
1205 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1206 //===----------------------------------------------------------------------===//
1208 let AddedComplexity = 20 in {
1209 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1210 (ins VR128:$src1, VR128:$src2),
1211 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1213 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
1215 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1216 (ins VR128:$src1, VR128:$src2),
1217 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1219 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
1222 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1223 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1224 (ins VR128:$src1, VR128:$src2),
1225 "movlhps\t{$src2, $dst|$dst, $src2}",
1227 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
1228 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1229 (ins VR128:$src1, VR128:$src2),
1230 "movhlps\t{$src2, $dst|$dst, $src2}",
1232 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
1235 let Predicates = [HasAVX] in {
1237 let AddedComplexity = 20 in {
1238 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1239 (VMOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1240 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1241 (VMOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1243 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
1244 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
1245 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1247 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
1248 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1249 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1250 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1251 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1252 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1255 let AddedComplexity = 20 in {
1256 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
1257 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
1258 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1260 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
1261 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
1262 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
1263 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
1264 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
1267 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
1268 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1269 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1270 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1273 let Predicates = [HasSSE1] in {
1275 let AddedComplexity = 20 in {
1276 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1277 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1278 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1279 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1281 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
1282 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
1283 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1285 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
1286 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1287 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1288 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1289 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1290 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1293 let AddedComplexity = 20 in {
1294 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
1295 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
1296 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1298 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
1299 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
1300 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
1301 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
1302 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
1305 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
1306 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1307 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1308 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1311 //===----------------------------------------------------------------------===//
1312 // SSE 1 & 2 - Conversion Instructions
1313 //===----------------------------------------------------------------------===//
1315 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1316 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1318 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1319 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
1320 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1321 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
1324 multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1325 X86MemOperand x86memop, string asm> {
1326 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm, []>;
1328 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm, []>;
1331 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1332 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1333 string asm, Domain d> {
1334 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1335 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
1336 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1337 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
1340 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1341 X86MemOperand x86memop, string asm> {
1342 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1343 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1345 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1346 (ins DstRC:$src1, x86memop:$src),
1347 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1350 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1351 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1353 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1354 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1356 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1357 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX,
1359 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1360 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
1361 VEX, VEX_W, VEX_LIG;
1363 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1364 // register, but the same isn't true when only using memory operands,
1365 // provide other assembly "l" and "q" forms to address this explicitly
1366 // where appropriate to do so.
1367 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
1369 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
1370 VEX_4V, VEX_W, VEX_LIG;
1371 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
1373 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
1375 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
1376 VEX_4V, VEX_W, VEX_LIG;
1378 let Predicates = [HasAVX] in {
1379 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1380 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1381 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1382 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1383 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1384 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1385 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1386 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1388 def : Pat<(f32 (sint_to_fp GR32:$src)),
1389 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1390 def : Pat<(f32 (sint_to_fp GR64:$src)),
1391 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1392 def : Pat<(f64 (sint_to_fp GR32:$src)),
1393 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1394 def : Pat<(f64 (sint_to_fp GR64:$src)),
1395 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1398 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1399 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
1400 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1401 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1402 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1403 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
1404 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1405 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1406 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1407 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
1408 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1409 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1410 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1411 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
1412 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1413 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1415 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1416 // and/or XMM operand(s).
1418 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1419 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
1421 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1422 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1423 [(set DstRC:$dst, (Int SrcRC:$src))]>;
1424 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
1425 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1426 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
1429 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1430 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1431 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
1432 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1434 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1435 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1436 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
1437 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1438 (ins DstRC:$src1, x86memop:$src2),
1440 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1441 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1442 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
1445 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1446 f128mem, load, "cvtsd2si">, XD, VEX;
1447 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1448 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
1451 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
1452 // Get rid of this hack or rename the intrinsics, there are several
1453 // intructions that only match with the intrinsic form, why create duplicates
1454 // to let them be recognized by the assembler?
1455 defm VCVTSD2SI : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
1456 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_LIG;
1457 defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
1458 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W,
1461 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1462 f128mem, load, "cvtsd2si{l}">, XD;
1463 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1464 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
1467 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1468 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
1469 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1470 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
1472 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1473 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
1474 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1475 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
1478 let Constraints = "$src1 = $dst" in {
1479 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1480 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1482 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1483 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1484 "cvtsi2ss{q}">, XS, REX_W;
1485 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1486 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1488 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1489 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1490 "cvtsi2sd">, XD, REX_W;
1495 // Aliases for intrinsics
1496 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1497 f32mem, load, "cvttss2si">, XS, VEX;
1498 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1499 int_x86_sse_cvttss2si64, f32mem, load,
1500 "cvttss2si">, XS, VEX, VEX_W;
1501 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1502 f128mem, load, "cvttsd2si">, XD, VEX;
1503 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1504 int_x86_sse2_cvttsd2si64, f128mem, load,
1505 "cvttsd2si">, XD, VEX, VEX_W;
1506 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1507 f32mem, load, "cvttss2si">, XS;
1508 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1509 int_x86_sse_cvttss2si64, f32mem, load,
1510 "cvttss2si{q}">, XS, REX_W;
1511 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1512 f128mem, load, "cvttsd2si">, XD;
1513 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1514 int_x86_sse2_cvttsd2si64, f128mem, load,
1515 "cvttsd2si{q}">, XD, REX_W;
1517 let Pattern = []<dag> in {
1518 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
1519 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS,
1521 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
1522 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1524 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
1525 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1526 SSEPackedSingle>, TB, VEX;
1527 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
1528 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1529 SSEPackedSingle>, TB, VEX;
1532 let Pattern = []<dag> in {
1533 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
1534 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
1535 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
1536 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1537 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
1538 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1539 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
1542 let Predicates = [HasSSE1] in {
1543 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1544 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1545 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1546 (CVTSS2SIrm addr:$src)>;
1547 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1548 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1549 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1550 (CVTSS2SI64rm addr:$src)>;
1553 let Predicates = [HasAVX] in {
1554 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1555 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1556 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1557 (VCVTSS2SIrm addr:$src)>;
1558 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1559 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1560 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1561 (VCVTSS2SI64rm addr:$src)>;
1566 // Convert scalar double to scalar single
1567 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1568 (ins FR64:$src1, FR64:$src2),
1569 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
1572 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1573 (ins FR64:$src1, f64mem:$src2),
1574 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1575 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1577 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1580 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1581 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1582 [(set FR32:$dst, (fround FR64:$src))]>;
1583 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1584 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1585 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1586 Requires<[HasSSE2, OptForSize]>;
1588 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1589 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
1591 let Constraints = "$src1 = $dst" in
1592 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1593 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
1595 // Convert scalar single to scalar double
1596 // SSE2 instructions with XS prefix
1597 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1598 (ins FR32:$src1, FR32:$src2),
1599 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1600 []>, XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1602 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1603 (ins FR32:$src1, f32mem:$src2),
1604 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1605 []>, XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1607 let Predicates = [HasAVX] in {
1608 def : Pat<(f64 (fextend FR32:$src)),
1609 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
1610 def : Pat<(fextend (loadf32 addr:$src)),
1611 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1612 def : Pat<(extloadf32 addr:$src),
1613 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1616 def : Pat<(extloadf32 addr:$src),
1617 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (MOVSSrm addr:$src))>,
1618 Requires<[HasAVX, OptForSpeed]>;
1620 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1621 "cvtss2sd\t{$src, $dst|$dst, $src}",
1622 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1623 Requires<[HasSSE2]>;
1624 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1625 "cvtss2sd\t{$src, $dst|$dst, $src}",
1626 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1627 Requires<[HasSSE2, OptForSize]>;
1629 // extload f32 -> f64. This matches load+fextend because we have a hack in
1630 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1632 // Since these loads aren't folded into the fextend, we have to match it
1634 def : Pat<(fextend (loadf32 addr:$src)),
1635 (CVTSS2SDrm addr:$src)>, Requires<[HasSSE2]>;
1636 def : Pat<(extloadf32 addr:$src),
1637 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1639 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1640 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1641 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1642 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1643 VR128:$src2))]>, XS, VEX_4V,
1645 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1646 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1647 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1648 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1649 (load addr:$src2)))]>, XS, VEX_4V,
1651 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1652 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1653 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1654 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1655 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1656 VR128:$src2))]>, XS,
1657 Requires<[HasSSE2]>;
1658 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1659 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1660 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1661 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1662 (load addr:$src2)))]>, XS,
1663 Requires<[HasSSE2]>;
1666 // Convert doubleword to packed single/double fp
1667 // SSE2 instructions without OpSize prefix
1668 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1669 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1670 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1671 TB, VEX, Requires<[HasAVX]>;
1672 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1673 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1674 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1675 (bitconvert (memopv2i64 addr:$src))))]>,
1676 TB, VEX, Requires<[HasAVX]>;
1677 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1678 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1679 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1680 TB, Requires<[HasSSE2]>;
1681 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1682 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1683 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1684 (bitconvert (memopv2i64 addr:$src))))]>,
1685 TB, Requires<[HasSSE2]>;
1687 // FIXME: why the non-intrinsic version is described as SSE3?
1688 // SSE2 instructions with XS prefix
1689 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1690 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1691 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1692 XS, VEX, Requires<[HasAVX]>;
1693 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1694 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1695 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1696 (bitconvert (memopv2i64 addr:$src))))]>,
1697 XS, VEX, Requires<[HasAVX]>;
1698 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1699 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1700 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1701 XS, Requires<[HasSSE2]>;
1702 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1703 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1704 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1705 (bitconvert (memopv2i64 addr:$src))))]>,
1706 XS, Requires<[HasSSE2]>;
1709 // Convert packed single/double fp to doubleword
1710 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1711 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1712 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1713 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1714 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1715 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1716 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1717 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1718 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1719 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1720 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1721 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1723 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1724 "cvtps2dq\t{$src, $dst|$dst, $src}",
1725 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
1727 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1729 "cvtps2dq\t{$src, $dst|$dst, $src}",
1730 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1731 (memop addr:$src)))]>, VEX;
1732 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1733 "cvtps2dq\t{$src, $dst|$dst, $src}",
1734 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1735 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1736 "cvtps2dq\t{$src, $dst|$dst, $src}",
1737 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1738 (memop addr:$src)))]>;
1740 // SSE2 packed instructions with XD prefix
1741 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1742 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1743 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1744 XD, VEX, Requires<[HasAVX]>;
1745 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1746 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1747 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1748 (memop addr:$src)))]>,
1749 XD, VEX, Requires<[HasAVX]>;
1750 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1751 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1752 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1753 XD, Requires<[HasSSE2]>;
1754 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1755 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1756 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1757 (memop addr:$src)))]>,
1758 XD, Requires<[HasSSE2]>;
1761 // Convert with truncation packed single/double fp to doubleword
1762 // SSE2 packed instructions with XS prefix
1763 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1764 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1766 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1767 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1768 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1769 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1771 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1772 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1773 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1774 "cvttps2dq\t{$src, $dst|$dst, $src}",
1776 (int_x86_sse2_cvttps2dq VR128:$src))]>;
1777 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1778 "cvttps2dq\t{$src, $dst|$dst, $src}",
1780 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
1782 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1783 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1785 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1786 XS, VEX, Requires<[HasAVX]>;
1787 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1788 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1789 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1790 (memop addr:$src)))]>,
1791 XS, VEX, Requires<[HasAVX]>;
1793 let Predicates = [HasSSE2] in {
1794 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1795 (Int_CVTDQ2PSrr VR128:$src)>;
1796 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1797 (CVTTPS2DQrr VR128:$src)>;
1800 let Predicates = [HasAVX] in {
1801 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1802 (Int_VCVTDQ2PSrr VR128:$src)>;
1803 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1804 (VCVTTPS2DQrr VR128:$src)>;
1805 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1806 (VCVTDQ2PSYrr VR256:$src)>;
1807 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1808 (VCVTTPS2DQYrr VR256:$src)>;
1811 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1812 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1814 (int_x86_sse2_cvttpd2dq VR128:$src))]>, VEX;
1815 let isCodeGenOnly = 1 in
1816 def VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1817 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1818 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1819 (memop addr:$src)))]>, VEX;
1820 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1821 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1822 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1823 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1824 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1825 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1826 (memop addr:$src)))]>;
1828 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1829 // register, but the same isn't true when using memory operands instead.
1830 // Provide other assembly rr and rm forms to address this explicitly.
1831 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1832 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1835 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1836 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1837 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1838 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1841 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1842 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
1843 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1844 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1846 // Convert packed single to packed double
1847 let Predicates = [HasAVX] in {
1848 // SSE2 instructions without OpSize prefix
1849 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1850 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1851 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1852 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1853 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1854 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1855 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1856 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1858 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1859 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1860 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1861 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1863 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1864 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1865 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1866 TB, VEX, Requires<[HasAVX]>;
1867 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1868 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1869 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1870 (load addr:$src)))]>,
1871 TB, VEX, Requires<[HasAVX]>;
1872 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1873 "cvtps2pd\t{$src, $dst|$dst, $src}",
1874 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1875 TB, Requires<[HasSSE2]>;
1876 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1877 "cvtps2pd\t{$src, $dst|$dst, $src}",
1878 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1879 (load addr:$src)))]>,
1880 TB, Requires<[HasSSE2]>;
1882 // Convert packed double to packed single
1883 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1884 // register, but the same isn't true when using memory operands instead.
1885 // Provide other assembly rr and rm forms to address this explicitly.
1886 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1887 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1888 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1889 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1892 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1893 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1894 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1895 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1898 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1899 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1900 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1901 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1902 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1903 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1904 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1905 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1908 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1909 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1910 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1911 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1913 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1914 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1915 (memop addr:$src)))]>;
1916 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1917 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1918 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1919 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1920 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1921 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1922 (memop addr:$src)))]>;
1924 // AVX 256-bit register conversion intrinsics
1925 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1926 // whenever possible to avoid declaring two versions of each one.
1927 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1928 (VCVTDQ2PSYrr VR256:$src)>;
1929 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
1930 (VCVTDQ2PSYrm addr:$src)>;
1932 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1933 (VCVTPD2PSYrr VR256:$src)>;
1934 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1935 (VCVTPD2PSYrm addr:$src)>;
1937 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1938 (VCVTPS2DQYrr VR256:$src)>;
1939 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1940 (VCVTPS2DQYrm addr:$src)>;
1942 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1943 (VCVTPS2PDYrr VR128:$src)>;
1944 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1945 (VCVTPS2PDYrm addr:$src)>;
1947 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1948 (VCVTTPD2DQYrr VR256:$src)>;
1949 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1950 (VCVTTPD2DQYrm addr:$src)>;
1952 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1953 (VCVTTPS2DQYrr VR256:$src)>;
1954 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1955 (VCVTTPS2DQYrm addr:$src)>;
1957 // Match fround and fextend for 128/256-bit conversions
1958 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
1959 (VCVTPD2PSYrr VR256:$src)>;
1960 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
1961 (VCVTPD2PSYrm addr:$src)>;
1963 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
1964 (VCVTPS2PDYrr VR128:$src)>;
1965 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
1966 (VCVTPS2PDYrm addr:$src)>;
1968 //===----------------------------------------------------------------------===//
1969 // SSE 1 & 2 - Compare Instructions
1970 //===----------------------------------------------------------------------===//
1972 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1973 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1974 SDNode OpNode, ValueType VT, PatFrag ld_frag,
1975 string asm, string asm_alt> {
1976 def rr : SIi8<0xC2, MRMSrcReg,
1977 (outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
1978 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))]>;
1979 def rm : SIi8<0xC2, MRMSrcMem,
1980 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, SSECC:$cc), asm,
1981 [(set RC:$dst, (OpNode (VT RC:$src1),
1982 (ld_frag addr:$src2), imm:$cc))]>;
1984 // Accept explicit immediate argument form instead of comparison code.
1985 let neverHasSideEffects = 1 in {
1986 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
1987 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, []>;
1989 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
1990 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, []>;
1994 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, X86cmpss, f32, loadf32,
1995 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1996 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1997 XS, VEX_4V, VEX_LIG;
1998 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, X86cmpsd, f64, loadf64,
1999 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2000 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
2001 XD, VEX_4V, VEX_LIG;
2003 let Constraints = "$src1 = $dst" in {
2004 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, X86cmpss, f32, loadf32,
2005 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2006 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}">,
2008 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, X86cmpsd, f64, loadf64,
2009 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2010 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}">,
2014 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
2015 Intrinsic Int, string asm> {
2016 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2017 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
2018 [(set VR128:$dst, (Int VR128:$src1,
2019 VR128:$src, imm:$cc))]>;
2020 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2021 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
2022 [(set VR128:$dst, (Int VR128:$src1,
2023 (load addr:$src), imm:$cc))]>;
2026 // Aliases to match intrinsics which expect XMM operand(s).
2027 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2028 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
2030 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2031 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
2033 let Constraints = "$src1 = $dst" in {
2034 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2035 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
2036 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2037 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
2041 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2042 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2043 ValueType vt, X86MemOperand x86memop,
2044 PatFrag ld_frag, string OpcodeStr, Domain d> {
2045 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2046 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2047 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
2048 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2049 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2050 [(set EFLAGS, (OpNode (vt RC:$src1),
2051 (ld_frag addr:$src2)))], d>;
2054 let Defs = [EFLAGS] in {
2055 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2056 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2057 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2058 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2060 let Pattern = []<dag> in {
2061 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2062 "comiss", SSEPackedSingle>, TB, VEX,
2064 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2065 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2069 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2070 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2071 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2072 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2074 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2075 load, "comiss", SSEPackedSingle>, TB, VEX;
2076 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2077 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2078 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2079 "ucomiss", SSEPackedSingle>, TB;
2080 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2081 "ucomisd", SSEPackedDouble>, TB, OpSize;
2083 let Pattern = []<dag> in {
2084 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2085 "comiss", SSEPackedSingle>, TB;
2086 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2087 "comisd", SSEPackedDouble>, TB, OpSize;
2090 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2091 load, "ucomiss", SSEPackedSingle>, TB;
2092 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2093 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2095 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2096 "comiss", SSEPackedSingle>, TB;
2097 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2098 "comisd", SSEPackedDouble>, TB, OpSize;
2099 } // Defs = [EFLAGS]
2101 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
2102 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2103 Intrinsic Int, string asm, string asm_alt,
2105 let isAsmParserOnly = 1 in {
2106 def rri : PIi8<0xC2, MRMSrcReg,
2107 (outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
2108 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))], d>;
2109 def rmi : PIi8<0xC2, MRMSrcMem,
2110 (outs RC:$dst), (ins RC:$src1, f128mem:$src2, SSECC:$cc), asm,
2111 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))], d>;
2114 // Accept explicit immediate argument form instead of comparison code.
2115 def rri_alt : PIi8<0xC2, MRMSrcReg,
2116 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2118 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2119 (outs RC:$dst), (ins RC:$src1, f128mem:$src2, i8imm:$cc),
2123 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2124 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2125 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2126 SSEPackedSingle>, TB, VEX_4V;
2127 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2128 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2129 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2130 SSEPackedDouble>, TB, OpSize, VEX_4V;
2131 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
2132 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2133 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2134 SSEPackedSingle>, TB, VEX_4V;
2135 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
2136 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2137 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2138 SSEPackedDouble>, TB, OpSize, VEX_4V;
2139 let Constraints = "$src1 = $dst" in {
2140 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2141 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2142 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2143 SSEPackedSingle>, TB;
2144 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2145 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2146 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2147 SSEPackedDouble>, TB, OpSize;
2150 let Predicates = [HasSSE1] in {
2151 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2152 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2153 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2154 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2157 let Predicates = [HasSSE2] in {
2158 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2159 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2160 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2161 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2164 let Predicates = [HasAVX] in {
2165 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2166 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2167 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2168 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2169 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2170 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2171 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2172 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2174 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2175 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2176 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2177 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2178 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2179 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2180 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2181 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2184 //===----------------------------------------------------------------------===//
2185 // SSE 1 & 2 - Shuffle Instructions
2186 //===----------------------------------------------------------------------===//
2188 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2189 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2190 ValueType vt, string asm, PatFrag mem_frag,
2191 Domain d, bit IsConvertibleToThreeAddress = 0> {
2192 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2193 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
2194 [(set RC:$dst, (vt (shufp:$src3
2195 RC:$src1, (mem_frag addr:$src2))))], d>;
2196 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2197 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2198 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2200 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
2203 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2204 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2205 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2206 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2207 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2208 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2209 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2210 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2211 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2212 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2213 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2214 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2216 let Constraints = "$src1 = $dst" in {
2217 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2218 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2219 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2221 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2222 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2223 memopv2f64, SSEPackedDouble>, TB, OpSize;
2226 let Predicates = [HasSSE1] in {
2227 def : Pat<(v4f32 (X86Shufps VR128:$src1,
2228 (memopv4f32 addr:$src2), (i8 imm:$imm))),
2229 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2230 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2231 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2232 def : Pat<(v4i32 (X86Shufps VR128:$src1,
2233 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2234 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2235 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2236 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2237 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2238 // fall back to this for SSE1)
2239 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2240 (SHUFPSrri VR128:$src2, VR128:$src1,
2241 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2242 // Special unary SHUFPSrri case.
2243 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2244 (SHUFPSrri VR128:$src1, VR128:$src1,
2245 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2248 let Predicates = [HasSSE2] in {
2249 // Special binary v4i32 shuffle cases with SHUFPS.
2250 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2251 (SHUFPSrri VR128:$src1, VR128:$src2,
2252 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2253 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
2254 (bc_v4i32 (memopv2i64 addr:$src2)))),
2255 (SHUFPSrmi VR128:$src1, addr:$src2,
2256 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2257 // Special unary SHUFPDrri cases.
2258 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2259 (SHUFPDrri VR128:$src1, VR128:$src1,
2260 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2261 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2262 (SHUFPDrri VR128:$src1, VR128:$src1,
2263 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2264 // Special binary v2i64 shuffle cases using SHUFPDrri.
2265 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2266 (SHUFPDrri VR128:$src1, VR128:$src2,
2267 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2268 // Generic SHUFPD patterns
2269 def : Pat<(v2f64 (X86Shufps VR128:$src1,
2270 (memopv2f64 addr:$src2), (i8 imm:$imm))),
2271 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2272 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2273 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2274 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2275 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2278 let Predicates = [HasAVX] in {
2279 def : Pat<(v4f32 (X86Shufps VR128:$src1,
2280 (memopv4f32 addr:$src2), (i8 imm:$imm))),
2281 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2282 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2283 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2284 def : Pat<(v4i32 (X86Shufps VR128:$src1,
2285 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2286 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2287 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2288 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2289 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2290 // fall back to this for SSE1)
2291 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2292 (VSHUFPSrri VR128:$src2, VR128:$src1,
2293 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2294 // Special unary SHUFPSrri case.
2295 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2296 (VSHUFPSrri VR128:$src1, VR128:$src1,
2297 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2298 // Special binary v4i32 shuffle cases with SHUFPS.
2299 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2300 (VSHUFPSrri VR128:$src1, VR128:$src2,
2301 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2302 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
2303 (bc_v4i32 (memopv2i64 addr:$src2)))),
2304 (VSHUFPSrmi VR128:$src1, addr:$src2,
2305 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2306 // Special unary SHUFPDrri cases.
2307 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2308 (VSHUFPDrri VR128:$src1, VR128:$src1,
2309 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2310 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2311 (VSHUFPDrri VR128:$src1, VR128:$src1,
2312 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2313 // Special binary v2i64 shuffle cases using SHUFPDrri.
2314 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2315 (VSHUFPDrri VR128:$src1, VR128:$src2,
2316 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2318 def : Pat<(v2f64 (X86Shufps VR128:$src1,
2319 (memopv2f64 addr:$src2), (i8 imm:$imm))),
2320 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2321 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2322 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2323 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2324 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2327 def : Pat<(v8i32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2328 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2329 def : Pat<(v8i32 (X86Shufps VR256:$src1,
2330 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2331 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2333 def : Pat<(v8f32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2334 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2335 def : Pat<(v8f32 (X86Shufps VR256:$src1,
2336 (memopv8f32 addr:$src2), (i8 imm:$imm))),
2337 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2339 def : Pat<(v4i64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2340 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2341 def : Pat<(v4i64 (X86Shufpd VR256:$src1,
2342 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2343 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2345 def : Pat<(v4f64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2346 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2347 def : Pat<(v4f64 (X86Shufpd VR256:$src1,
2348 (memopv4f64 addr:$src2), (i8 imm:$imm))),
2349 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2352 //===----------------------------------------------------------------------===//
2353 // SSE 1 & 2 - Unpack Instructions
2354 //===----------------------------------------------------------------------===//
2356 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2357 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
2358 PatFrag mem_frag, RegisterClass RC,
2359 X86MemOperand x86memop, string asm,
2361 def rr : PI<opc, MRMSrcReg,
2362 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2364 (vt (OpNode RC:$src1, RC:$src2)))], d>;
2365 def rm : PI<opc, MRMSrcMem,
2366 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2368 (vt (OpNode RC:$src1,
2369 (mem_frag addr:$src2))))], d>;
2372 let AddedComplexity = 10 in {
2373 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2374 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2375 SSEPackedSingle>, TB, VEX_4V;
2376 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2377 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2378 SSEPackedDouble>, TB, OpSize, VEX_4V;
2379 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2380 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2381 SSEPackedSingle>, TB, VEX_4V;
2382 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2383 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2384 SSEPackedDouble>, TB, OpSize, VEX_4V;
2386 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
2387 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2388 SSEPackedSingle>, TB, VEX_4V;
2389 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
2390 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2391 SSEPackedDouble>, TB, OpSize, VEX_4V;
2392 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
2393 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2394 SSEPackedSingle>, TB, VEX_4V;
2395 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
2396 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2397 SSEPackedDouble>, TB, OpSize, VEX_4V;
2399 let Constraints = "$src1 = $dst" in {
2400 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2401 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2402 SSEPackedSingle>, TB;
2403 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2404 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2405 SSEPackedDouble>, TB, OpSize;
2406 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2407 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2408 SSEPackedSingle>, TB;
2409 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2410 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2411 SSEPackedDouble>, TB, OpSize;
2412 } // Constraints = "$src1 = $dst"
2413 } // AddedComplexity
2415 let Predicates = [HasSSE1] in {
2416 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
2417 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
2418 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
2419 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
2420 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
2421 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
2422 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
2423 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
2426 let Predicates = [HasSSE2] in {
2427 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
2428 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
2429 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
2430 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
2431 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
2432 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
2433 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
2434 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
2436 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
2437 // problem is during lowering, where it's not possible to recognize the load
2438 // fold cause it has two uses through a bitcast. One use disappears at isel
2439 // time and the fold opportunity reappears.
2440 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2441 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2443 let AddedComplexity = 10 in
2444 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2445 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2448 let Predicates = [HasAVX] in {
2449 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
2450 (VUNPCKLPSrm VR128:$src1, addr:$src2)>;
2451 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
2452 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>;
2453 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
2454 (VUNPCKHPSrm VR128:$src1, addr:$src2)>;
2455 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
2456 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>;
2458 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
2459 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2460 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
2461 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2462 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
2463 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2464 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, (memopv8i32 addr:$src2))),
2465 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2466 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, (memopv8f32 addr:$src2))),
2467 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2468 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
2469 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2470 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, (memopv8i32 addr:$src2))),
2471 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2472 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
2473 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2475 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
2476 (VUNPCKLPDrm VR128:$src1, addr:$src2)>;
2477 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
2478 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>;
2479 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
2480 (VUNPCKHPDrm VR128:$src1, addr:$src2)>;
2481 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
2482 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>;
2484 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
2485 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2486 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
2487 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2488 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, (memopv4i64 addr:$src2))),
2489 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2490 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
2491 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2492 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, (memopv4f64 addr:$src2))),
2493 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2494 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
2495 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2496 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, (memopv4i64 addr:$src2))),
2497 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2498 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
2499 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2501 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
2502 // problem is during lowering, where it's not possible to recognize the load
2503 // fold cause it has two uses through a bitcast. One use disappears at isel
2504 // time and the fold opportunity reappears.
2505 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2506 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2507 let AddedComplexity = 10 in
2508 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2509 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2512 //===----------------------------------------------------------------------===//
2513 // SSE 1 & 2 - Extract Floating-Point Sign mask
2514 //===----------------------------------------------------------------------===//
2516 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2517 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2519 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2520 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2521 [(set GR32:$dst, (Int RC:$src))], d>;
2522 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2523 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
2526 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2527 SSEPackedSingle>, TB;
2528 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2529 SSEPackedDouble>, TB, OpSize;
2531 def : Pat<(i32 (X86fgetsign FR32:$src)),
2532 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2533 sub_ss))>, Requires<[HasSSE1]>;
2534 def : Pat<(i64 (X86fgetsign FR32:$src)),
2535 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2536 sub_ss))>, Requires<[HasSSE1]>;
2537 def : Pat<(i32 (X86fgetsign FR64:$src)),
2538 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2539 sub_sd))>, Requires<[HasSSE2]>;
2540 def : Pat<(i64 (X86fgetsign FR64:$src)),
2541 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2542 sub_sd))>, Requires<[HasSSE2]>;
2544 let Predicates = [HasAVX] in {
2545 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2546 "movmskps", SSEPackedSingle>, TB, VEX;
2547 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2548 "movmskpd", SSEPackedDouble>, TB,
2550 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2551 "movmskps", SSEPackedSingle>, TB, VEX;
2552 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2553 "movmskpd", SSEPackedDouble>, TB,
2556 def : Pat<(i32 (X86fgetsign FR32:$src)),
2557 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2559 def : Pat<(i64 (X86fgetsign FR32:$src)),
2560 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2562 def : Pat<(i32 (X86fgetsign FR64:$src)),
2563 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2565 def : Pat<(i64 (X86fgetsign FR64:$src)),
2566 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2570 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2571 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2572 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2573 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
2575 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2576 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2577 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2578 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
2582 //===----------------------------------------------------------------------===//
2583 // SSE 1 & 2 - Logical Instructions
2584 //===----------------------------------------------------------------------===//
2586 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2588 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2590 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2591 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, TB, VEX_4V;
2593 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2594 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, TB, OpSize, VEX_4V;
2596 let Constraints = "$src1 = $dst" in {
2597 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2598 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
2600 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2601 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
2605 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2606 let mayLoad = 0 in {
2607 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
2608 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
2609 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
2612 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2613 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
2615 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2617 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2619 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2620 // are all promoted to v2i64, and the patterns are covered by the int
2621 // version. This is needed in SSE only, because v2i64 isn't supported on
2622 // SSE1, but only on SSE2.
2623 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2624 !strconcat(OpcodeStr, "ps"), f128mem, [],
2625 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2626 (memopv2i64 addr:$src2)))], 0>, TB, VEX_4V;
2628 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2629 !strconcat(OpcodeStr, "pd"), f128mem,
2630 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2631 (bc_v2i64 (v2f64 VR128:$src2))))],
2632 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2633 (memopv2i64 addr:$src2)))], 0>,
2635 let Constraints = "$src1 = $dst" in {
2636 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2637 !strconcat(OpcodeStr, "ps"), f128mem,
2638 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2639 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2640 (memopv2i64 addr:$src2)))]>, TB;
2642 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2643 !strconcat(OpcodeStr, "pd"), f128mem,
2644 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2645 (bc_v2i64 (v2f64 VR128:$src2))))],
2646 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2647 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2651 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2653 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2655 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2656 !strconcat(OpcodeStr, "ps"), f256mem,
2657 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2658 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2659 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2661 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2662 !strconcat(OpcodeStr, "pd"), f256mem,
2663 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2664 (bc_v4i64 (v4f64 VR256:$src2))))],
2665 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2666 (memopv4i64 addr:$src2)))], 0>,
2670 // AVX 256-bit packed logical ops forms
2671 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2672 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2673 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2674 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2676 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2677 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2678 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2679 let isCommutable = 0 in
2680 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2682 //===----------------------------------------------------------------------===//
2683 // SSE 1 & 2 - Arithmetic Instructions
2684 //===----------------------------------------------------------------------===//
2686 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2689 /// In addition, we also have a special variant of the scalar form here to
2690 /// represent the associated intrinsic operation. This form is unlike the
2691 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2692 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2694 /// These three forms can each be reg+reg or reg+mem.
2697 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2699 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2701 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2702 OpNode, FR32, f32mem, Is2Addr>, XS;
2703 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2704 OpNode, FR64, f64mem, Is2Addr>, XD;
2707 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2709 let mayLoad = 0 in {
2710 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2711 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
2712 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2713 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
2717 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2719 let mayLoad = 0 in {
2720 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2721 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
2722 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2723 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
2727 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2729 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2730 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
2731 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2732 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
2735 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2737 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2738 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2739 SSEPackedSingle, Is2Addr>, TB;
2741 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2742 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2743 SSEPackedDouble, Is2Addr>, TB, OpSize;
2746 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
2747 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2748 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2749 SSEPackedSingle, 0>, TB;
2751 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2752 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2753 SSEPackedDouble, 0>, TB, OpSize;
2756 // Binary Arithmetic instructions
2757 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
2758 basic_sse12_fp_binop_s_int<0x58, "add", 0>, VEX_4V, VEX_LIG;
2759 defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
2760 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
2761 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
2762 basic_sse12_fp_binop_s_int<0x59, "mul", 0>, VEX_4V, VEX_LIG;
2763 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
2764 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
2766 let isCommutable = 0 in {
2767 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
2768 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>, VEX_4V, VEX_LIG;
2769 defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
2770 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
2771 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
2772 basic_sse12_fp_binop_s_int<0x5E, "div", 0>, VEX_4V, VEX_LIG;
2773 defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
2774 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
2775 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
2776 basic_sse12_fp_binop_s_int<0x5F, "max", 0>, VEX_4V, VEX_LIG;
2777 defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
2778 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
2779 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
2780 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
2781 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
2782 basic_sse12_fp_binop_s_int<0x5D, "min", 0>, VEX_4V, VEX_LIG;
2783 defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
2784 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
2785 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
2786 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
2789 let Constraints = "$src1 = $dst" in {
2790 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
2791 basic_sse12_fp_binop_p<0x58, "add", fadd>,
2792 basic_sse12_fp_binop_s_int<0x58, "add">;
2793 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
2794 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
2795 basic_sse12_fp_binop_s_int<0x59, "mul">;
2797 let isCommutable = 0 in {
2798 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
2799 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
2800 basic_sse12_fp_binop_s_int<0x5C, "sub">;
2801 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
2802 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
2803 basic_sse12_fp_binop_s_int<0x5E, "div">;
2804 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
2805 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
2806 basic_sse12_fp_binop_s_int<0x5F, "max">,
2807 basic_sse12_fp_binop_p_int<0x5F, "max">;
2808 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
2809 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
2810 basic_sse12_fp_binop_s_int<0x5D, "min">,
2811 basic_sse12_fp_binop_p_int<0x5D, "min">;
2816 /// In addition, we also have a special variant of the scalar form here to
2817 /// represent the associated intrinsic operation. This form is unlike the
2818 /// plain scalar form, in that it takes an entire vector (instead of a
2819 /// scalar) and leaves the top elements undefined.
2821 /// And, we have a special variant form for a full-vector intrinsic form.
2823 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2824 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2825 SDNode OpNode, Intrinsic F32Int> {
2826 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2827 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2828 [(set FR32:$dst, (OpNode FR32:$src))]>;
2829 // For scalar unary operations, fold a load into the operation
2830 // only in OptForSize mode. It eliminates an instruction, but it also
2831 // eliminates a whole-register clobber (the load), so it introduces a
2832 // partial register update condition.
2833 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
2834 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2835 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
2836 Requires<[HasSSE1, OptForSize]>;
2837 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2838 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2839 [(set VR128:$dst, (F32Int VR128:$src))]>;
2840 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
2841 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2842 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
2845 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
2846 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2847 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
2848 !strconcat(OpcodeStr,
2849 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2851 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
2852 !strconcat(OpcodeStr,
2853 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2854 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
2855 (ins ssmem:$src1, VR128:$src2),
2856 !strconcat(OpcodeStr,
2857 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2860 /// sse1_fp_unop_p - SSE1 unops in packed form.
2861 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2862 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2863 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2864 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
2865 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2866 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2867 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
2870 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
2871 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2872 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2873 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2874 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
2875 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2876 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2877 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
2880 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
2881 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2882 Intrinsic V4F32Int> {
2883 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2884 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2885 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
2886 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2887 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2888 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
2891 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
2892 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2893 Intrinsic V4F32Int> {
2894 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2895 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2896 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
2897 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2898 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2899 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
2902 /// sse2_fp_unop_s - SSE2 unops in scalar form.
2903 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
2904 SDNode OpNode, Intrinsic F64Int> {
2905 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
2906 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2907 [(set FR64:$dst, (OpNode FR64:$src))]>;
2908 // See the comments in sse1_fp_unop_s for why this is OptForSize.
2909 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
2910 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2911 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
2912 Requires<[HasSSE2, OptForSize]>;
2913 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2914 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2915 [(set VR128:$dst, (F64Int VR128:$src))]>;
2916 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
2917 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2918 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
2921 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
2922 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2923 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
2924 !strconcat(OpcodeStr,
2925 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2926 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
2927 !strconcat(OpcodeStr,
2928 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2929 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
2930 (ins VR128:$src1, sdmem:$src2),
2931 !strconcat(OpcodeStr,
2932 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2935 /// sse2_fp_unop_p - SSE2 unops in vector forms.
2936 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
2938 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2939 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2940 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
2941 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2942 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2943 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
2946 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
2947 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2948 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2949 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2950 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
2951 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2952 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2953 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
2956 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
2957 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2958 Intrinsic V2F64Int> {
2959 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2960 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2961 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
2962 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2963 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2964 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
2967 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
2968 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2969 Intrinsic V2F64Int> {
2970 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2971 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2972 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
2973 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2974 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2975 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
2978 let Predicates = [HasAVX] in {
2980 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
2981 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
2983 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
2984 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
2985 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
2986 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
2987 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
2988 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
2989 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
2990 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
2993 // Reciprocal approximations. Note that these typically require refinement
2994 // in order to obtain suitable precision.
2995 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
2996 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
2997 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
2998 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
2999 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
3001 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
3002 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
3003 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
3004 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
3005 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
3008 def : Pat<(f32 (fsqrt FR32:$src)),
3009 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3010 def : Pat<(f32 (fsqrt (load addr:$src))),
3011 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3012 Requires<[HasAVX, OptForSize]>;
3013 def : Pat<(f64 (fsqrt FR64:$src)),
3014 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3015 def : Pat<(f64 (fsqrt (load addr:$src))),
3016 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3017 Requires<[HasAVX, OptForSize]>;
3019 def : Pat<(f32 (X86frsqrt FR32:$src)),
3020 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3021 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3022 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3023 Requires<[HasAVX, OptForSize]>;
3025 def : Pat<(f32 (X86frcp FR32:$src)),
3026 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3027 def : Pat<(f32 (X86frcp (load addr:$src))),
3028 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3029 Requires<[HasAVX, OptForSize]>;
3031 let Predicates = [HasAVX] in {
3032 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3033 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3034 (VSQRTSSr (f32 (IMPLICIT_DEF)),
3035 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3037 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3038 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3040 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3041 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
3042 (VSQRTSDr (f64 (IMPLICIT_DEF)),
3043 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
3045 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3046 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3048 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3049 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3050 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3051 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3053 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3054 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3056 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3057 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3058 (VRCPSSr (f32 (IMPLICIT_DEF)),
3059 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3061 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3062 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3066 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
3067 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
3068 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
3069 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
3070 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
3071 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
3073 // Reciprocal approximations. Note that these typically require refinement
3074 // in order to obtain suitable precision.
3075 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
3076 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
3077 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
3078 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
3079 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
3080 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
3082 // There is no f64 version of the reciprocal approximation instructions.
3084 //===----------------------------------------------------------------------===//
3085 // SSE 1 & 2 - Non-temporal stores
3086 //===----------------------------------------------------------------------===//
3088 let AddedComplexity = 400 in { // Prefer non-temporal versions
3089 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3090 (ins f128mem:$dst, VR128:$src),
3091 "movntps\t{$src, $dst|$dst, $src}",
3092 [(alignednontemporalstore (v4f32 VR128:$src),
3094 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3095 (ins f128mem:$dst, VR128:$src),
3096 "movntpd\t{$src, $dst|$dst, $src}",
3097 [(alignednontemporalstore (v2f64 VR128:$src),
3099 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
3100 (ins f128mem:$dst, VR128:$src),
3101 "movntdq\t{$src, $dst|$dst, $src}",
3102 [(alignednontemporalstore (v2f64 VR128:$src),
3105 let ExeDomain = SSEPackedInt in
3106 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3107 (ins f128mem:$dst, VR128:$src),
3108 "movntdq\t{$src, $dst|$dst, $src}",
3109 [(alignednontemporalstore (v4f32 VR128:$src),
3112 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3113 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3115 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3116 (ins f256mem:$dst, VR256:$src),
3117 "movntps\t{$src, $dst|$dst, $src}",
3118 [(alignednontemporalstore (v8f32 VR256:$src),
3120 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3121 (ins f256mem:$dst, VR256:$src),
3122 "movntpd\t{$src, $dst|$dst, $src}",
3123 [(alignednontemporalstore (v4f64 VR256:$src),
3125 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
3126 (ins f256mem:$dst, VR256:$src),
3127 "movntdq\t{$src, $dst|$dst, $src}",
3128 [(alignednontemporalstore (v4f64 VR256:$src),
3130 let ExeDomain = SSEPackedInt in
3131 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3132 (ins f256mem:$dst, VR256:$src),
3133 "movntdq\t{$src, $dst|$dst, $src}",
3134 [(alignednontemporalstore (v8f32 VR256:$src),
3138 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
3139 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3140 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
3141 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
3142 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
3143 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
3145 let AddedComplexity = 400 in { // Prefer non-temporal versions
3146 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3147 "movntps\t{$src, $dst|$dst, $src}",
3148 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
3149 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3150 "movntpd\t{$src, $dst|$dst, $src}",
3151 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
3153 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3154 "movntdq\t{$src, $dst|$dst, $src}",
3155 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
3157 let ExeDomain = SSEPackedInt in
3158 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3159 "movntdq\t{$src, $dst|$dst, $src}",
3160 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
3162 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3163 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3165 // There is no AVX form for instructions below this point
3166 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3167 "movnti{l}\t{$src, $dst|$dst, $src}",
3168 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
3169 TB, Requires<[HasSSE2]>;
3170 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3171 "movnti{q}\t{$src, $dst|$dst, $src}",
3172 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
3173 TB, Requires<[HasSSE2]>;
3176 //===----------------------------------------------------------------------===//
3177 // SSE 1 & 2 - Prefetch and memory fence
3178 //===----------------------------------------------------------------------===//
3180 // Prefetch intrinsic.
3181 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
3182 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
3183 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
3184 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
3185 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
3186 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
3187 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
3188 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
3191 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3192 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3193 TB, Requires<[HasSSE2]>;
3195 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3196 // was introduced with SSE2, it's backward compatible.
3197 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3199 // Load, store, and memory fence
3200 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3201 "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
3202 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3203 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3204 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3205 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3207 def : Pat<(X86SFence), (SFENCE)>;
3208 def : Pat<(X86LFence), (LFENCE)>;
3209 def : Pat<(X86MFence), (MFENCE)>;
3211 //===----------------------------------------------------------------------===//
3212 // SSE 1 & 2 - Load/Store XCSR register
3213 //===----------------------------------------------------------------------===//
3215 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3216 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
3217 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3218 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
3220 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3221 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
3222 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3223 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
3225 //===---------------------------------------------------------------------===//
3226 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3227 //===---------------------------------------------------------------------===//
3229 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3231 let neverHasSideEffects = 1 in {
3232 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3233 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3234 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3235 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3237 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3238 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3239 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3240 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3243 let isCodeGenOnly = 1 in {
3244 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3245 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3246 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3247 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3248 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3249 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3250 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3251 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3254 let canFoldAsLoad = 1, mayLoad = 1 in {
3255 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3256 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3257 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3258 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3259 let Predicates = [HasAVX] in {
3260 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3261 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3262 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3263 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3267 let mayStore = 1 in {
3268 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3269 (ins i128mem:$dst, VR128:$src),
3270 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3271 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3272 (ins i256mem:$dst, VR256:$src),
3273 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3274 let Predicates = [HasAVX] in {
3275 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3276 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3277 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3278 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3282 let neverHasSideEffects = 1 in
3283 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3284 "movdqa\t{$src, $dst|$dst, $src}", []>;
3286 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3287 "movdqu\t{$src, $dst|$dst, $src}",
3288 []>, XS, Requires<[HasSSE2]>;
3291 let isCodeGenOnly = 1 in {
3292 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3293 "movdqa\t{$src, $dst|$dst, $src}", []>;
3295 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3296 "movdqu\t{$src, $dst|$dst, $src}",
3297 []>, XS, Requires<[HasSSE2]>;
3300 let canFoldAsLoad = 1, mayLoad = 1 in {
3301 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3302 "movdqa\t{$src, $dst|$dst, $src}",
3303 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
3304 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3305 "movdqu\t{$src, $dst|$dst, $src}",
3306 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
3307 XS, Requires<[HasSSE2]>;
3310 let mayStore = 1 in {
3311 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3312 "movdqa\t{$src, $dst|$dst, $src}",
3313 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
3314 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3315 "movdqu\t{$src, $dst|$dst, $src}",
3316 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
3317 XS, Requires<[HasSSE2]>;
3320 // Intrinsic forms of MOVDQU load and store
3321 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3322 "vmovdqu\t{$src, $dst|$dst, $src}",
3323 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3324 XS, VEX, Requires<[HasAVX]>;
3326 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3327 "movdqu\t{$src, $dst|$dst, $src}",
3328 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3329 XS, Requires<[HasSSE2]>;
3331 } // ExeDomain = SSEPackedInt
3333 let Predicates = [HasAVX] in {
3334 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
3335 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3336 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3339 //===---------------------------------------------------------------------===//
3340 // SSE2 - Packed Integer Arithmetic Instructions
3341 //===---------------------------------------------------------------------===//
3343 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3345 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3346 bit IsCommutable = 0, bit Is2Addr = 1> {
3347 let isCommutable = IsCommutable in
3348 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3349 (ins VR128:$src1, VR128:$src2),
3351 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3352 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3353 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
3354 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3355 (ins VR128:$src1, i128mem:$src2),
3357 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3358 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3359 [(set VR128:$dst, (IntId VR128:$src1,
3360 (bitconvert (memopv2i64 addr:$src2))))]>;
3363 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
3364 string OpcodeStr, Intrinsic IntId,
3365 Intrinsic IntId2, bit Is2Addr = 1> {
3366 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3367 (ins VR128:$src1, VR128:$src2),
3369 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3370 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3371 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
3372 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3373 (ins VR128:$src1, i128mem:$src2),
3375 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3376 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3377 [(set VR128:$dst, (IntId VR128:$src1,
3378 (bitconvert (memopv2i64 addr:$src2))))]>;
3379 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
3380 (ins VR128:$src1, i32i8imm:$src2),
3382 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3383 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3384 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
3387 /// PDI_binop_rm - Simple SSE2 binary operator.
3388 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3389 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
3390 let isCommutable = IsCommutable in
3391 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3392 (ins VR128:$src1, VR128:$src2),
3394 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3395 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3396 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
3397 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3398 (ins VR128:$src1, i128mem:$src2),
3400 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3401 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3402 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
3403 (bitconvert (memopv2i64 addr:$src2)))))]>;
3406 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
3408 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
3409 /// to collapse (bitconvert VT to VT) into its operand.
3411 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
3412 bit IsCommutable = 0, bit Is2Addr = 1> {
3413 let isCommutable = IsCommutable in
3414 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3415 (ins VR128:$src1, VR128:$src2),
3417 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3418 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3419 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
3420 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3421 (ins VR128:$src1, i128mem:$src2),
3423 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3424 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3425 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
3428 } // ExeDomain = SSEPackedInt
3430 // 128-bit Integer Arithmetic
3432 let Predicates = [HasAVX] in {
3433 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
3434 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
3435 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
3436 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
3437 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
3438 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
3439 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
3440 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
3441 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
3444 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
3446 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
3448 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
3450 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
3452 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
3454 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
3456 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
3458 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
3460 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
3462 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
3464 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
3466 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
3468 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
3470 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
3472 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
3474 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
3476 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
3478 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
3480 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
3484 let Constraints = "$src1 = $dst" in {
3485 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
3486 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
3487 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
3488 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
3489 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
3490 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
3491 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
3492 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
3493 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
3496 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
3497 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
3498 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
3499 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
3500 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
3501 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
3502 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
3503 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
3504 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
3505 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
3506 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
3507 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
3508 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
3509 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
3510 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
3511 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
3512 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
3513 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
3514 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
3516 } // Constraints = "$src1 = $dst"
3518 //===---------------------------------------------------------------------===//
3519 // SSE2 - Packed Integer Logical Instructions
3520 //===---------------------------------------------------------------------===//
3522 let Predicates = [HasAVX] in {
3523 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
3524 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
3526 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
3527 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
3529 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
3530 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
3533 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
3534 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
3536 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
3537 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
3539 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
3540 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
3543 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
3544 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
3546 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
3547 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
3550 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
3551 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
3552 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
3554 let ExeDomain = SSEPackedInt in {
3555 let neverHasSideEffects = 1 in {
3556 // 128-bit logical shifts.
3557 def VPSLLDQri : PDIi8<0x73, MRM7r,
3558 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3559 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3561 def VPSRLDQri : PDIi8<0x73, MRM3r,
3562 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3563 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3565 // PSRADQri doesn't exist in SSE[1-3].
3567 def VPANDNrr : PDI<0xDF, MRMSrcReg,
3568 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3569 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3571 (v2i64 (X86andnp VR128:$src1, VR128:$src2)))]>,VEX_4V;
3573 def VPANDNrm : PDI<0xDF, MRMSrcMem,
3574 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3575 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3576 [(set VR128:$dst, (X86andnp VR128:$src1,
3577 (memopv2i64 addr:$src2)))]>, VEX_4V;
3581 let Constraints = "$src1 = $dst" in {
3582 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
3583 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
3584 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
3585 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
3586 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
3587 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
3589 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
3590 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
3591 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
3592 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
3593 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
3594 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
3596 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
3597 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
3598 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
3599 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
3601 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
3602 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
3603 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
3605 let ExeDomain = SSEPackedInt in {
3606 let neverHasSideEffects = 1 in {
3607 // 128-bit logical shifts.
3608 def PSLLDQri : PDIi8<0x73, MRM7r,
3609 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3610 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
3611 def PSRLDQri : PDIi8<0x73, MRM3r,
3612 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3613 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
3614 // PSRADQri doesn't exist in SSE[1-3].
3616 def PANDNrr : PDI<0xDF, MRMSrcReg,
3617 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3618 "pandn\t{$src2, $dst|$dst, $src2}", []>;
3620 def PANDNrm : PDI<0xDF, MRMSrcMem,
3621 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3622 "pandn\t{$src2, $dst|$dst, $src2}", []>;
3624 } // Constraints = "$src1 = $dst"
3626 let Predicates = [HasAVX] in {
3627 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3628 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3629 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3630 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3631 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3632 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
3633 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3634 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
3635 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3636 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3638 // Shift up / down and insert zero's.
3639 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3640 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3641 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3642 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3645 let Predicates = [HasSSE2] in {
3646 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3647 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3648 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3649 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3650 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3651 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
3652 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3653 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
3654 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3655 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3657 // Shift up / down and insert zero's.
3658 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3659 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3660 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3661 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3664 //===---------------------------------------------------------------------===//
3665 // SSE2 - Packed Integer Comparison Instructions
3666 //===---------------------------------------------------------------------===//
3668 let Predicates = [HasAVX] in {
3669 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
3671 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
3673 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
3675 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
3677 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
3679 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
3682 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3683 (VPCMPEQBrr VR128:$src1, VR128:$src2)>;
3684 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
3685 (VPCMPEQBrm VR128:$src1, addr:$src2)>;
3686 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3687 (VPCMPEQWrr VR128:$src1, VR128:$src2)>;
3688 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
3689 (VPCMPEQWrm VR128:$src1, addr:$src2)>;
3690 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3691 (VPCMPEQDrr VR128:$src1, VR128:$src2)>;
3692 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
3693 (VPCMPEQDrm VR128:$src1, addr:$src2)>;
3695 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3696 (VPCMPGTBrr VR128:$src1, VR128:$src2)>;
3697 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
3698 (VPCMPGTBrm VR128:$src1, addr:$src2)>;
3699 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3700 (VPCMPGTWrr VR128:$src1, VR128:$src2)>;
3701 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
3702 (VPCMPGTWrm VR128:$src1, addr:$src2)>;
3703 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3704 (VPCMPGTDrr VR128:$src1, VR128:$src2)>;
3705 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
3706 (VPCMPGTDrm VR128:$src1, addr:$src2)>;
3709 let Constraints = "$src1 = $dst" in {
3710 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
3711 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
3712 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
3713 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
3714 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
3715 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
3716 } // Constraints = "$src1 = $dst"
3718 let Predicates = [HasSSE2] in {
3719 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3720 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
3721 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
3722 (PCMPEQBrm VR128:$src1, addr:$src2)>;
3723 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3724 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
3725 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
3726 (PCMPEQWrm VR128:$src1, addr:$src2)>;
3727 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3728 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
3729 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
3730 (PCMPEQDrm VR128:$src1, addr:$src2)>;
3732 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3733 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
3734 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
3735 (PCMPGTBrm VR128:$src1, addr:$src2)>;
3736 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3737 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
3738 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
3739 (PCMPGTWrm VR128:$src1, addr:$src2)>;
3740 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3741 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
3742 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
3743 (PCMPGTDrm VR128:$src1, addr:$src2)>;
3746 //===---------------------------------------------------------------------===//
3747 // SSE2 - Packed Integer Pack Instructions
3748 //===---------------------------------------------------------------------===//
3750 let Predicates = [HasAVX] in {
3751 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
3753 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
3755 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
3759 let Constraints = "$src1 = $dst" in {
3760 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
3761 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
3762 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
3763 } // Constraints = "$src1 = $dst"
3765 //===---------------------------------------------------------------------===//
3766 // SSE2 - Packed Integer Shuffle Instructions
3767 //===---------------------------------------------------------------------===//
3769 let ExeDomain = SSEPackedInt in {
3770 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
3772 def ri : Ii8<0x70, MRMSrcReg,
3773 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
3774 !strconcat(OpcodeStr,
3775 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3776 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
3778 def mi : Ii8<0x70, MRMSrcMem,
3779 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
3780 !strconcat(OpcodeStr,
3781 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3782 [(set VR128:$dst, (vt (pshuf_frag:$src2
3783 (bc_frag (memopv2i64 addr:$src1)),
3786 } // ExeDomain = SSEPackedInt
3788 let Predicates = [HasAVX] in {
3789 let AddedComplexity = 5 in
3790 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize,
3793 // SSE2 with ImmT == Imm8 and XS prefix.
3794 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
3797 // SSE2 with ImmT == Imm8 and XD prefix.
3798 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
3801 let AddedComplexity = 5 in
3802 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3803 (VPSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3804 // Unary v4f32 shuffle with VPSHUF* in order to fold a load.
3805 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3806 (VPSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3808 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
3810 (VPSHUFDmi addr:$src1, imm:$imm)>;
3811 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
3813 (VPSHUFDmi addr:$src1, imm:$imm)>;
3814 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3815 (VPSHUFDri VR128:$src1, imm:$imm)>;
3816 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3817 (VPSHUFDri VR128:$src1, imm:$imm)>;
3818 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
3819 (VPSHUFHWri VR128:$src, imm:$imm)>;
3820 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
3822 (VPSHUFHWmi addr:$src, imm:$imm)>;
3823 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
3824 (VPSHUFLWri VR128:$src, imm:$imm)>;
3825 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
3827 (VPSHUFLWmi addr:$src, imm:$imm)>;
3830 let Predicates = [HasSSE2] in {
3831 let AddedComplexity = 5 in
3832 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
3834 // SSE2 with ImmT == Imm8 and XS prefix.
3835 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
3837 // SSE2 with ImmT == Imm8 and XD prefix.
3838 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
3840 let AddedComplexity = 5 in
3841 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3842 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3843 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3844 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3845 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3847 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
3849 (PSHUFDmi addr:$src1, imm:$imm)>;
3850 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
3852 (PSHUFDmi addr:$src1, imm:$imm)>;
3853 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3854 (PSHUFDri VR128:$src1, imm:$imm)>;
3855 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3856 (PSHUFDri VR128:$src1, imm:$imm)>;
3857 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
3858 (PSHUFHWri VR128:$src, imm:$imm)>;
3859 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
3861 (PSHUFHWmi addr:$src, imm:$imm)>;
3862 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
3863 (PSHUFLWri VR128:$src, imm:$imm)>;
3864 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
3866 (PSHUFLWmi addr:$src, imm:$imm)>;
3869 //===---------------------------------------------------------------------===//
3870 // SSE2 - Packed Integer Unpack Instructions
3871 //===---------------------------------------------------------------------===//
3873 let ExeDomain = SSEPackedInt in {
3874 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
3875 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
3876 def rr : PDI<opc, MRMSrcReg,
3877 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3879 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3880 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3881 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))]>;
3882 def rm : PDI<opc, MRMSrcMem,
3883 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3885 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3886 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3887 [(set VR128:$dst, (OpNode VR128:$src1,
3888 (bc_frag (memopv2i64
3892 let Predicates = [HasAVX] in {
3893 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Punpcklbw,
3894 bc_v16i8, 0>, VEX_4V;
3895 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Punpcklwd,
3896 bc_v8i16, 0>, VEX_4V;
3897 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Punpckldq,
3898 bc_v4i32, 0>, VEX_4V;
3900 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3901 /// knew to collapse (bitconvert VT to VT) into its operand.
3902 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
3903 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3904 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3905 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
3906 VR128:$src2)))]>, VEX_4V;
3907 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
3908 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3909 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3910 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
3911 (memopv2i64 addr:$src2))))]>, VEX_4V;
3913 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Punpckhbw,
3914 bc_v16i8, 0>, VEX_4V;
3915 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Punpckhwd,
3916 bc_v8i16, 0>, VEX_4V;
3917 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Punpckhdq,
3918 bc_v4i32, 0>, VEX_4V;
3920 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3921 /// knew to collapse (bitconvert VT to VT) into its operand.
3922 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
3923 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3924 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3925 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
3926 VR128:$src2)))]>, VEX_4V;
3927 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
3928 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3929 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3930 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
3931 (memopv2i64 addr:$src2))))]>, VEX_4V;
3934 let Constraints = "$src1 = $dst" in {
3935 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Punpcklbw, bc_v16i8>;
3936 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Punpcklwd, bc_v8i16>;
3937 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Punpckldq, bc_v4i32>;
3939 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3940 /// knew to collapse (bitconvert VT to VT) into its operand.
3941 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
3942 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3943 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
3945 (v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)))]>;
3946 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
3947 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3948 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
3950 (v2i64 (X86Punpcklqdq VR128:$src1,
3951 (memopv2i64 addr:$src2))))]>;
3953 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Punpckhbw, bc_v16i8>;
3954 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Punpckhwd, bc_v8i16>;
3955 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Punpckhdq, bc_v4i32>;
3957 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3958 /// knew to collapse (bitconvert VT to VT) into its operand.
3959 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
3960 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3961 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
3963 (v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)))]>;
3964 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
3965 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3966 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
3968 (v2i64 (X86Punpckhqdq VR128:$src1,
3969 (memopv2i64 addr:$src2))))]>;
3971 } // ExeDomain = SSEPackedInt
3973 // Splat v2f64 / v2i64
3974 let AddedComplexity = 10 in {
3975 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3976 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3977 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3978 (VPUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasAVX]>;
3981 //===---------------------------------------------------------------------===//
3982 // SSE2 - Packed Integer Extract and Insert
3983 //===---------------------------------------------------------------------===//
3985 let ExeDomain = SSEPackedInt in {
3986 multiclass sse2_pinsrw<bit Is2Addr = 1> {
3987 def rri : Ii8<0xC4, MRMSrcReg,
3988 (outs VR128:$dst), (ins VR128:$src1,
3989 GR32:$src2, i32i8imm:$src3),
3991 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3992 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3994 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
3995 def rmi : Ii8<0xC4, MRMSrcMem,
3996 (outs VR128:$dst), (ins VR128:$src1,
3997 i16mem:$src2, i32i8imm:$src3),
3999 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4000 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4002 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4007 let Predicates = [HasAVX] in
4008 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4009 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4010 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4011 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4012 imm:$src2))]>, TB, OpSize, VEX;
4013 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4014 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4015 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4016 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4020 let Predicates = [HasAVX] in {
4021 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4022 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4023 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4024 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4025 []>, TB, OpSize, VEX_4V;
4028 let Constraints = "$src1 = $dst" in
4029 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
4031 } // ExeDomain = SSEPackedInt
4033 //===---------------------------------------------------------------------===//
4034 // SSE2 - Packed Mask Creation
4035 //===---------------------------------------------------------------------===//
4037 let ExeDomain = SSEPackedInt in {
4039 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4040 "pmovmskb\t{$src, $dst|$dst, $src}",
4041 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
4042 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4043 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4044 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4045 "pmovmskb\t{$src, $dst|$dst, $src}",
4046 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
4048 } // ExeDomain = SSEPackedInt
4050 //===---------------------------------------------------------------------===//
4051 // SSE2 - Conditional Store
4052 //===---------------------------------------------------------------------===//
4054 let ExeDomain = SSEPackedInt in {
4057 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4058 (ins VR128:$src, VR128:$mask),
4059 "maskmovdqu\t{$mask, $src|$src, $mask}",
4060 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
4062 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4063 (ins VR128:$src, VR128:$mask),
4064 "maskmovdqu\t{$mask, $src|$src, $mask}",
4065 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
4068 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4069 "maskmovdqu\t{$mask, $src|$src, $mask}",
4070 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
4072 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4073 "maskmovdqu\t{$mask, $src|$src, $mask}",
4074 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
4076 } // ExeDomain = SSEPackedInt
4078 //===---------------------------------------------------------------------===//
4079 // SSE2 - Move Doubleword
4080 //===---------------------------------------------------------------------===//
4082 //===---------------------------------------------------------------------===//
4083 // Move Int Doubleword to Packed Double Int
4085 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4086 "movd\t{$src, $dst|$dst, $src}",
4088 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
4089 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4090 "movd\t{$src, $dst|$dst, $src}",
4092 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
4094 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4095 "mov{d|q}\t{$src, $dst|$dst, $src}",
4097 (v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
4098 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4099 "mov{d|q}\t{$src, $dst|$dst, $src}",
4100 [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
4102 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4103 "movd\t{$src, $dst|$dst, $src}",
4105 (v4i32 (scalar_to_vector GR32:$src)))]>;
4106 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4107 "movd\t{$src, $dst|$dst, $src}",
4109 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
4110 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4111 "mov{d|q}\t{$src, $dst|$dst, $src}",
4113 (v2i64 (scalar_to_vector GR64:$src)))]>;
4114 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4115 "mov{d|q}\t{$src, $dst|$dst, $src}",
4116 [(set FR64:$dst, (bitconvert GR64:$src))]>;
4118 //===---------------------------------------------------------------------===//
4119 // Move Int Doubleword to Single Scalar
4121 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4122 "movd\t{$src, $dst|$dst, $src}",
4123 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
4125 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4126 "movd\t{$src, $dst|$dst, $src}",
4127 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
4129 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4130 "movd\t{$src, $dst|$dst, $src}",
4131 [(set FR32:$dst, (bitconvert GR32:$src))]>;
4133 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4134 "movd\t{$src, $dst|$dst, $src}",
4135 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
4137 //===---------------------------------------------------------------------===//
4138 // Move Packed Doubleword Int to Packed Double Int
4140 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4141 "movd\t{$src, $dst|$dst, $src}",
4142 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4144 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4145 (ins i32mem:$dst, VR128:$src),
4146 "movd\t{$src, $dst|$dst, $src}",
4147 [(store (i32 (vector_extract (v4i32 VR128:$src),
4148 (iPTR 0))), addr:$dst)]>, VEX;
4149 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4150 "movd\t{$src, $dst|$dst, $src}",
4151 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4153 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4154 "movd\t{$src, $dst|$dst, $src}",
4155 [(store (i32 (vector_extract (v4i32 VR128:$src),
4156 (iPTR 0))), addr:$dst)]>;
4158 //===---------------------------------------------------------------------===//
4159 // Move Packed Doubleword Int first element to Doubleword Int
4161 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4162 "mov{d|q}\t{$src, $dst|$dst, $src}",
4163 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4165 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4167 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4168 "mov{d|q}\t{$src, $dst|$dst, $src}",
4169 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4172 //===---------------------------------------------------------------------===//
4173 // Bitcast FR64 <-> GR64
4175 let Predicates = [HasAVX] in
4176 def VMOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4177 "vmovq\t{$src, $dst|$dst, $src}",
4178 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4180 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4181 "mov{d|q}\t{$src, $dst|$dst, $src}",
4182 [(set GR64:$dst, (bitconvert FR64:$src))]>;
4183 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4184 "movq\t{$src, $dst|$dst, $src}",
4185 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
4187 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4188 "movq\t{$src, $dst|$dst, $src}",
4189 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
4190 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4191 "mov{d|q}\t{$src, $dst|$dst, $src}",
4192 [(set GR64:$dst, (bitconvert FR64:$src))]>;
4193 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4194 "movq\t{$src, $dst|$dst, $src}",
4195 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
4197 //===---------------------------------------------------------------------===//
4198 // Move Scalar Single to Double Int
4200 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4201 "movd\t{$src, $dst|$dst, $src}",
4202 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
4203 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4204 "movd\t{$src, $dst|$dst, $src}",
4205 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
4206 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4207 "movd\t{$src, $dst|$dst, $src}",
4208 [(set GR32:$dst, (bitconvert FR32:$src))]>;
4209 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4210 "movd\t{$src, $dst|$dst, $src}",
4211 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
4213 //===---------------------------------------------------------------------===//
4214 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4216 let AddedComplexity = 15 in {
4217 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4218 "movd\t{$src, $dst|$dst, $src}",
4219 [(set VR128:$dst, (v4i32 (X86vzmovl
4220 (v4i32 (scalar_to_vector GR32:$src)))))]>,
4222 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4223 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4224 [(set VR128:$dst, (v2i64 (X86vzmovl
4225 (v2i64 (scalar_to_vector GR64:$src)))))]>,
4228 let AddedComplexity = 15 in {
4229 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4230 "movd\t{$src, $dst|$dst, $src}",
4231 [(set VR128:$dst, (v4i32 (X86vzmovl
4232 (v4i32 (scalar_to_vector GR32:$src)))))]>;
4233 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4234 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4235 [(set VR128:$dst, (v2i64 (X86vzmovl
4236 (v2i64 (scalar_to_vector GR64:$src)))))]>;
4239 let AddedComplexity = 20 in {
4240 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4241 "movd\t{$src, $dst|$dst, $src}",
4243 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4244 (loadi32 addr:$src))))))]>,
4246 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4247 "movd\t{$src, $dst|$dst, $src}",
4249 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4250 (loadi32 addr:$src))))))]>;
4253 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4254 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
4255 (MOVZDI2PDIrm addr:$src)>;
4256 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4257 (MOVZDI2PDIrm addr:$src)>;
4258 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4259 (MOVZDI2PDIrm addr:$src)>;
4262 let Predicates = [HasAVX] in {
4263 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4264 let AddedComplexity = 20 in {
4265 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
4266 (VMOVZDI2PDIrm addr:$src)>;
4267 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4268 (VMOVZDI2PDIrm addr:$src)>;
4269 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4270 (VMOVZDI2PDIrm addr:$src)>;
4272 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4273 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4274 (v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
4275 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4276 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4277 (v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
4278 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4281 // These are the correct encodings of the instructions so that we know how to
4282 // read correct assembly, even though we continue to emit the wrong ones for
4283 // compatibility with Darwin's buggy assembler.
4284 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4285 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4286 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4287 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4288 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4289 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4290 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4291 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4292 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4293 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4294 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4295 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4297 //===---------------------------------------------------------------------===//
4298 // SSE2 - Move Quadword
4299 //===---------------------------------------------------------------------===//
4301 //===---------------------------------------------------------------------===//
4302 // Move Quadword Int to Packed Quadword Int
4304 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4305 "vmovq\t{$src, $dst|$dst, $src}",
4307 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4308 VEX, Requires<[HasAVX]>;
4309 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4310 "movq\t{$src, $dst|$dst, $src}",
4312 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4313 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
4315 //===---------------------------------------------------------------------===//
4316 // Move Packed Quadword Int to Quadword Int
4318 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4319 "movq\t{$src, $dst|$dst, $src}",
4320 [(store (i64 (vector_extract (v2i64 VR128:$src),
4321 (iPTR 0))), addr:$dst)]>, VEX;
4322 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4323 "movq\t{$src, $dst|$dst, $src}",
4324 [(store (i64 (vector_extract (v2i64 VR128:$src),
4325 (iPTR 0))), addr:$dst)]>;
4327 //===---------------------------------------------------------------------===//
4328 // Store / copy lower 64-bits of a XMM register.
4330 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4331 "movq\t{$src, $dst|$dst, $src}",
4332 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4333 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4334 "movq\t{$src, $dst|$dst, $src}",
4335 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
4337 let AddedComplexity = 20 in
4338 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4339 "vmovq\t{$src, $dst|$dst, $src}",
4341 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4342 (loadi64 addr:$src))))))]>,
4343 XS, VEX, Requires<[HasAVX]>;
4345 let AddedComplexity = 20 in
4346 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4347 "movq\t{$src, $dst|$dst, $src}",
4349 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4350 (loadi64 addr:$src))))))]>,
4351 XS, Requires<[HasSSE2]>;
4353 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4354 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4355 (MOVZQI2PQIrm addr:$src)>;
4356 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4357 (MOVZQI2PQIrm addr:$src)>;
4358 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4361 let Predicates = [HasAVX], AddedComplexity = 20 in {
4362 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4363 (VMOVZQI2PQIrm addr:$src)>;
4364 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4365 (VMOVZQI2PQIrm addr:$src)>;
4366 def : Pat<(v2i64 (X86vzload addr:$src)),
4367 (VMOVZQI2PQIrm addr:$src)>;
4370 //===---------------------------------------------------------------------===//
4371 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4372 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4374 let AddedComplexity = 15 in
4375 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4376 "vmovq\t{$src, $dst|$dst, $src}",
4377 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4378 XS, VEX, Requires<[HasAVX]>;
4379 let AddedComplexity = 15 in
4380 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4381 "movq\t{$src, $dst|$dst, $src}",
4382 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4383 XS, Requires<[HasSSE2]>;
4385 let AddedComplexity = 20 in
4386 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4387 "vmovq\t{$src, $dst|$dst, $src}",
4388 [(set VR128:$dst, (v2i64 (X86vzmovl
4389 (loadv2i64 addr:$src))))]>,
4390 XS, VEX, Requires<[HasAVX]>;
4391 let AddedComplexity = 20 in {
4392 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4393 "movq\t{$src, $dst|$dst, $src}",
4394 [(set VR128:$dst, (v2i64 (X86vzmovl
4395 (loadv2i64 addr:$src))))]>,
4396 XS, Requires<[HasSSE2]>;
4399 let AddedComplexity = 20 in {
4400 let Predicates = [HasSSE2] in {
4401 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
4402 (MOVZPQILo2PQIrm addr:$src)>;
4403 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4404 (MOVZPQILo2PQIrr VR128:$src)>;
4406 let Predicates = [HasAVX] in {
4407 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
4408 (VMOVZPQILo2PQIrm addr:$src)>;
4409 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4410 (VMOVZPQILo2PQIrr VR128:$src)>;
4414 // Instructions to match in the assembler
4415 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4416 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4417 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4418 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4419 // Recognize "movd" with GR64 destination, but encode as a "movq"
4420 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4421 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4423 // Instructions for the disassembler
4424 // xr = XMM register
4427 let Predicates = [HasAVX] in
4428 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4429 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4430 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4431 "movq\t{$src, $dst|$dst, $src}", []>, XS;
4433 //===---------------------------------------------------------------------===//
4434 // SSE3 - Conversion Instructions
4435 //===---------------------------------------------------------------------===//
4437 // Convert Packed Double FP to Packed DW Integers
4438 let Predicates = [HasAVX] in {
4439 // The assembler can recognize rr 256-bit instructions by seeing a ymm
4440 // register, but the same isn't true when using memory operands instead.
4441 // Provide other assembly rr and rm forms to address this explicitly.
4442 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4443 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4444 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4445 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4448 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4449 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4450 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4451 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4454 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4455 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
4456 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
4457 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4460 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4461 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4462 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4463 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4465 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
4466 (VCVTPD2DQYrr VR256:$src)>;
4467 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
4468 (VCVTPD2DQYrm addr:$src)>;
4470 // Convert Packed DW Integers to Packed Double FP
4471 let Predicates = [HasAVX] in {
4472 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4473 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4474 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4475 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4476 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
4477 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4478 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
4479 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4482 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4483 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4484 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4485 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4487 // AVX 256-bit register conversion intrinsics
4488 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
4489 (VCVTDQ2PDYrr VR128:$src)>;
4490 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
4491 (VCVTDQ2PDYrm addr:$src)>;
4493 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
4494 (VCVTPD2DQYrr VR256:$src)>;
4495 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
4496 (VCVTPD2DQYrm addr:$src)>;
4498 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
4499 (VCVTDQ2PDYrr VR128:$src)>;
4500 def : Pat<(v4f64 (sint_to_fp (memopv4i32 addr:$src))),
4501 (VCVTDQ2PDYrm addr:$src)>;
4503 //===---------------------------------------------------------------------===//
4504 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4505 //===---------------------------------------------------------------------===//
4506 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4507 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4508 X86MemOperand x86memop> {
4509 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4510 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4511 [(set RC:$dst, (vt (OpNode RC:$src)))]>;
4512 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4513 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4514 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>;
4517 let Predicates = [HasAVX] in {
4518 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4519 v4f32, VR128, memopv4f32, f128mem>, VEX;
4520 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4521 v4f32, VR128, memopv4f32, f128mem>, VEX;
4522 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4523 v8f32, VR256, memopv8f32, f256mem>, VEX;
4524 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4525 v8f32, VR256, memopv8f32, f256mem>, VEX;
4527 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4528 memopv4f32, f128mem>;
4529 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4530 memopv4f32, f128mem>;
4532 let Predicates = [HasSSE3] in {
4533 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4534 (MOVSHDUPrr VR128:$src)>;
4535 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4536 (MOVSHDUPrm addr:$src)>;
4537 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4538 (MOVSLDUPrr VR128:$src)>;
4539 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4540 (MOVSLDUPrm addr:$src)>;
4543 let Predicates = [HasAVX] in {
4544 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4545 (VMOVSHDUPrr VR128:$src)>;
4546 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4547 (VMOVSHDUPrm addr:$src)>;
4548 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4549 (VMOVSLDUPrr VR128:$src)>;
4550 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4551 (VMOVSLDUPrm addr:$src)>;
4552 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4553 (VMOVSHDUPYrr VR256:$src)>;
4554 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4555 (VMOVSHDUPYrm addr:$src)>;
4556 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4557 (VMOVSLDUPYrr VR256:$src)>;
4558 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4559 (VMOVSLDUPYrm addr:$src)>;
4562 //===---------------------------------------------------------------------===//
4563 // SSE3 - Replicate Double FP - MOVDDUP
4564 //===---------------------------------------------------------------------===//
4566 multiclass sse3_replicate_dfp<string OpcodeStr> {
4567 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4568 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4569 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
4570 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4571 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4573 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
4577 // FIXME: Merge with above classe when there're patterns for the ymm version
4578 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4579 let Predicates = [HasAVX] in {
4580 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4581 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4583 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4584 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4589 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4590 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4591 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
4593 let Predicates = [HasSSE3] in {
4594 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
4596 (MOVDDUPrm addr:$src)>;
4597 let AddedComplexity = 5 in {
4598 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
4599 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
4600 (MOVDDUPrm addr:$src)>;
4601 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
4602 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
4603 (MOVDDUPrm addr:$src)>;
4605 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4606 (MOVDDUPrm addr:$src)>;
4607 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4608 (MOVDDUPrm addr:$src)>;
4609 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4610 (MOVDDUPrm addr:$src)>;
4611 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
4612 (MOVDDUPrm addr:$src)>;
4613 def : Pat<(X86Movddup (bc_v2f64
4614 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4615 (MOVDDUPrm addr:$src)>;
4618 let Predicates = [HasAVX] in {
4619 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
4621 (VMOVDDUPrm addr:$src)>;
4622 let AddedComplexity = 5 in {
4623 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
4624 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
4625 (VMOVDDUPrm addr:$src)>;
4626 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
4627 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
4628 (VMOVDDUPrm addr:$src)>;
4630 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4631 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4632 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4633 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4634 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4635 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4636 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
4637 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4638 def : Pat<(X86Movddup (bc_v2f64
4639 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4640 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4643 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4644 (VMOVDDUPYrm addr:$src)>;
4645 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4646 (VMOVDDUPYrm addr:$src)>;
4647 def : Pat<(X86Movddup (v4f64 (scalar_to_vector (loadf64 addr:$src)))),
4648 (VMOVDDUPYrm addr:$src)>;
4649 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4650 (VMOVDDUPYrm addr:$src)>;
4651 def : Pat<(X86Movddup (v4f64 VR256:$src)),
4652 (VMOVDDUPYrr VR256:$src)>;
4653 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4654 (VMOVDDUPYrr VR256:$src)>;
4657 //===---------------------------------------------------------------------===//
4658 // SSE3 - Move Unaligned Integer
4659 //===---------------------------------------------------------------------===//
4661 let Predicates = [HasAVX] in {
4662 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4663 "vlddqu\t{$src, $dst|$dst, $src}",
4664 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4665 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4666 "vlddqu\t{$src, $dst|$dst, $src}",
4667 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
4669 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4670 "lddqu\t{$src, $dst|$dst, $src}",
4671 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
4673 //===---------------------------------------------------------------------===//
4674 // SSE3 - Arithmetic
4675 //===---------------------------------------------------------------------===//
4677 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4678 X86MemOperand x86memop, bit Is2Addr = 1> {
4679 def rr : I<0xD0, MRMSrcReg,
4680 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4682 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4683 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4684 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
4685 def rm : I<0xD0, MRMSrcMem,
4686 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4688 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4689 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4690 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
4693 let Predicates = [HasAVX],
4694 ExeDomain = SSEPackedDouble in {
4695 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4696 f128mem, 0>, TB, XD, VEX_4V;
4697 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4698 f128mem, 0>, TB, OpSize, VEX_4V;
4699 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4700 f256mem, 0>, TB, XD, VEX_4V;
4701 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
4702 f256mem, 0>, TB, OpSize, VEX_4V;
4704 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
4705 ExeDomain = SSEPackedDouble in {
4706 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
4708 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
4709 f128mem>, TB, OpSize;
4712 //===---------------------------------------------------------------------===//
4713 // SSE3 Instructions
4714 //===---------------------------------------------------------------------===//
4717 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4718 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4719 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4721 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4722 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4723 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))]>;
4725 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4727 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4728 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4729 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))]>;
4731 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4732 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4733 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4735 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4736 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4737 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))]>;
4739 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4741 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4742 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4743 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))]>;
4746 let Predicates = [HasAVX] in {
4747 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
4748 X86fhadd, 0>, VEX_4V;
4749 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
4750 X86fhadd, 0>, VEX_4V;
4751 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
4752 X86fhsub, 0>, VEX_4V;
4753 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
4754 X86fhsub, 0>, VEX_4V;
4755 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
4756 X86fhadd, 0>, VEX_4V;
4757 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
4758 X86fhadd, 0>, VEX_4V;
4759 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
4760 X86fhsub, 0>, VEX_4V;
4761 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
4762 X86fhsub, 0>, VEX_4V;
4765 let Constraints = "$src1 = $dst" in {
4766 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
4767 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
4768 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
4769 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
4772 //===---------------------------------------------------------------------===//
4773 // SSSE3 - Packed Absolute Instructions
4774 //===---------------------------------------------------------------------===//
4777 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
4778 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
4779 PatFrag mem_frag128, Intrinsic IntId128> {
4780 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4782 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4783 [(set VR128:$dst, (IntId128 VR128:$src))]>,
4786 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4788 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4791 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
4794 let Predicates = [HasAVX] in {
4795 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
4796 int_x86_ssse3_pabs_b_128>, VEX;
4797 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
4798 int_x86_ssse3_pabs_w_128>, VEX;
4799 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
4800 int_x86_ssse3_pabs_d_128>, VEX;
4803 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
4804 int_x86_ssse3_pabs_b_128>;
4805 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
4806 int_x86_ssse3_pabs_w_128>;
4807 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
4808 int_x86_ssse3_pabs_d_128>;
4810 //===---------------------------------------------------------------------===//
4811 // SSSE3 - Packed Binary Operator Instructions
4812 //===---------------------------------------------------------------------===//
4814 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
4815 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
4816 PatFrag mem_frag128, Intrinsic IntId128,
4818 let isCommutable = 1 in
4819 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4820 (ins VR128:$src1, VR128:$src2),
4822 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4823 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4824 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4826 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4827 (ins VR128:$src1, i128mem:$src2),
4829 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4830 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4832 (IntId128 VR128:$src1,
4833 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4836 let ImmT = NoImm, Predicates = [HasAVX] in {
4837 let isCommutable = 0 in {
4838 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
4839 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
4840 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
4841 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
4842 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
4843 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
4844 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
4845 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
4846 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
4847 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
4848 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
4849 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
4850 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
4851 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
4852 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
4853 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
4854 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
4855 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
4856 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
4857 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
4858 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
4859 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
4861 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
4862 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
4865 // None of these have i8 immediate fields.
4866 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
4867 let isCommutable = 0 in {
4868 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
4869 int_x86_ssse3_phadd_w_128>;
4870 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
4871 int_x86_ssse3_phadd_d_128>;
4872 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
4873 int_x86_ssse3_phadd_sw_128>;
4874 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
4875 int_x86_ssse3_phsub_w_128>;
4876 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
4877 int_x86_ssse3_phsub_d_128>;
4878 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
4879 int_x86_ssse3_phsub_sw_128>;
4880 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
4881 int_x86_ssse3_pmadd_ub_sw_128>;
4882 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
4883 int_x86_ssse3_pshuf_b_128>;
4884 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
4885 int_x86_ssse3_psign_b_128>;
4886 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
4887 int_x86_ssse3_psign_w_128>;
4888 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
4889 int_x86_ssse3_psign_d_128>;
4891 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
4892 int_x86_ssse3_pmul_hr_sw_128>;
4895 let Predicates = [HasSSSE3] in {
4896 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
4897 (PSHUFBrr128 VR128:$src, VR128:$mask)>;
4898 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
4899 (PSHUFBrm128 VR128:$src, addr:$mask)>;
4901 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
4902 (PSIGNBrr128 VR128:$src1, VR128:$src2)>;
4903 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
4904 (PSIGNWrr128 VR128:$src1, VR128:$src2)>;
4905 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
4906 (PSIGNDrr128 VR128:$src1, VR128:$src2)>;
4909 let Predicates = [HasAVX] in {
4910 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
4911 (VPSHUFBrr128 VR128:$src, VR128:$mask)>;
4912 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
4913 (VPSHUFBrm128 VR128:$src, addr:$mask)>;
4915 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
4916 (VPSIGNBrr128 VR128:$src1, VR128:$src2)>;
4917 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
4918 (VPSIGNWrr128 VR128:$src1, VR128:$src2)>;
4919 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
4920 (VPSIGNDrr128 VR128:$src1, VR128:$src2)>;
4923 //===---------------------------------------------------------------------===//
4924 // SSSE3 - Packed Align Instruction Patterns
4925 //===---------------------------------------------------------------------===//
4927 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
4928 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
4929 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4931 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4933 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4935 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
4936 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4938 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4940 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4944 let Predicates = [HasAVX] in
4945 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
4946 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
4947 defm PALIGN : ssse3_palign<"palignr">;
4949 let Predicates = [HasSSSE3] in {
4950 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4951 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4952 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4953 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4954 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4955 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4956 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4957 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4960 let Predicates = [HasAVX] in {
4961 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4962 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4963 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4964 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4965 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4966 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4967 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4968 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4971 //===---------------------------------------------------------------------===//
4972 // SSSE3 - Thread synchronization
4973 //===---------------------------------------------------------------------===//
4975 let usesCustomInserter = 1 in {
4976 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
4977 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
4978 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
4979 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
4982 let Uses = [EAX, ECX, EDX] in
4983 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
4984 Requires<[HasSSE3]>;
4985 let Uses = [ECX, EAX] in
4986 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
4987 Requires<[HasSSE3]>;
4989 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
4990 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
4992 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
4993 Requires<[In32BitMode]>;
4994 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
4995 Requires<[In64BitMode]>;
4997 //===----------------------------------------------------------------------===//
4998 // SSE4.1 - Packed Move with Sign/Zero Extend
4999 //===----------------------------------------------------------------------===//
5001 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5002 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5003 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5004 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5006 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5007 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5009 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5013 let Predicates = [HasAVX] in {
5014 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5016 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5018 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5020 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5022 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5024 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5028 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5029 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5030 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5031 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5032 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5033 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5035 let Predicates = [HasSSE41] in {
5036 // Common patterns involving scalar load.
5037 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5038 (PMOVSXBWrm addr:$src)>;
5039 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5040 (PMOVSXBWrm addr:$src)>;
5042 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5043 (PMOVSXWDrm addr:$src)>;
5044 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5045 (PMOVSXWDrm addr:$src)>;
5047 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5048 (PMOVSXDQrm addr:$src)>;
5049 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5050 (PMOVSXDQrm addr:$src)>;
5052 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5053 (PMOVZXBWrm addr:$src)>;
5054 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5055 (PMOVZXBWrm addr:$src)>;
5057 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5058 (PMOVZXWDrm addr:$src)>;
5059 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5060 (PMOVZXWDrm addr:$src)>;
5062 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5063 (PMOVZXDQrm addr:$src)>;
5064 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5065 (PMOVZXDQrm addr:$src)>;
5068 let Predicates = [HasAVX] in {
5069 // Common patterns involving scalar load.
5070 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5071 (VPMOVSXBWrm addr:$src)>;
5072 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5073 (VPMOVSXBWrm addr:$src)>;
5075 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5076 (VPMOVSXWDrm addr:$src)>;
5077 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5078 (VPMOVSXWDrm addr:$src)>;
5080 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5081 (VPMOVSXDQrm addr:$src)>;
5082 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5083 (VPMOVSXDQrm addr:$src)>;
5085 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5086 (VPMOVZXBWrm addr:$src)>;
5087 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5088 (VPMOVZXBWrm addr:$src)>;
5090 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5091 (VPMOVZXWDrm addr:$src)>;
5092 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5093 (VPMOVZXWDrm addr:$src)>;
5095 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5096 (VPMOVZXDQrm addr:$src)>;
5097 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5098 (VPMOVZXDQrm addr:$src)>;
5102 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5103 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5104 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5105 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5107 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5108 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5110 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5114 let Predicates = [HasAVX] in {
5115 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5117 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5119 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5121 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5125 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5126 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5127 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5128 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5130 let Predicates = [HasSSE41] in {
5131 // Common patterns involving scalar load
5132 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5133 (PMOVSXBDrm addr:$src)>;
5134 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5135 (PMOVSXWQrm addr:$src)>;
5137 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5138 (PMOVZXBDrm addr:$src)>;
5139 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5140 (PMOVZXWQrm addr:$src)>;
5143 let Predicates = [HasAVX] in {
5144 // Common patterns involving scalar load
5145 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5146 (VPMOVSXBDrm addr:$src)>;
5147 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5148 (VPMOVSXWQrm addr:$src)>;
5150 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5151 (VPMOVZXBDrm addr:$src)>;
5152 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5153 (VPMOVZXWQrm addr:$src)>;
5156 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5157 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5158 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5159 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5161 // Expecting a i16 load any extended to i32 value.
5162 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5163 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5164 [(set VR128:$dst, (IntId (bitconvert
5165 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5169 let Predicates = [HasAVX] in {
5170 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5172 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5175 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5176 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5178 let Predicates = [HasSSE41] in {
5179 // Common patterns involving scalar load
5180 def : Pat<(int_x86_sse41_pmovsxbq
5181 (bitconvert (v4i32 (X86vzmovl
5182 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5183 (PMOVSXBQrm addr:$src)>;
5185 def : Pat<(int_x86_sse41_pmovzxbq
5186 (bitconvert (v4i32 (X86vzmovl
5187 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5188 (PMOVZXBQrm addr:$src)>;
5191 let Predicates = [HasAVX] in {
5192 // Common patterns involving scalar load
5193 def : Pat<(int_x86_sse41_pmovsxbq
5194 (bitconvert (v4i32 (X86vzmovl
5195 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5196 (VPMOVSXBQrm addr:$src)>;
5198 def : Pat<(int_x86_sse41_pmovzxbq
5199 (bitconvert (v4i32 (X86vzmovl
5200 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5201 (VPMOVZXBQrm addr:$src)>;
5204 //===----------------------------------------------------------------------===//
5205 // SSE4.1 - Extract Instructions
5206 //===----------------------------------------------------------------------===//
5208 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5209 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5210 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5211 (ins VR128:$src1, i32i8imm:$src2),
5212 !strconcat(OpcodeStr,
5213 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5214 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5216 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5217 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5218 !strconcat(OpcodeStr,
5219 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5222 // There's an AssertZext in the way of writing the store pattern
5223 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5226 let Predicates = [HasAVX] in {
5227 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5228 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5229 (ins VR128:$src1, i32i8imm:$src2),
5230 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5233 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5236 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5237 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5238 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5239 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5240 !strconcat(OpcodeStr,
5241 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5244 // There's an AssertZext in the way of writing the store pattern
5245 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5248 let Predicates = [HasAVX] in
5249 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5251 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5254 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5255 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5256 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5257 (ins VR128:$src1, i32i8imm:$src2),
5258 !strconcat(OpcodeStr,
5259 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5261 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5262 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5263 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5264 !strconcat(OpcodeStr,
5265 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5266 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5267 addr:$dst)]>, OpSize;
5270 let Predicates = [HasAVX] in
5271 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5273 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5275 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5276 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5277 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5278 (ins VR128:$src1, i32i8imm:$src2),
5279 !strconcat(OpcodeStr,
5280 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5282 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5283 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5284 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5285 !strconcat(OpcodeStr,
5286 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5287 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5288 addr:$dst)]>, OpSize, REX_W;
5291 let Predicates = [HasAVX] in
5292 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5294 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5296 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5298 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5299 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5300 (ins VR128:$src1, i32i8imm:$src2),
5301 !strconcat(OpcodeStr,
5302 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5304 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5306 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5307 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5308 !strconcat(OpcodeStr,
5309 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5310 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5311 addr:$dst)]>, OpSize;
5314 let Predicates = [HasAVX] in {
5315 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5316 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5317 (ins VR128:$src1, i32i8imm:$src2),
5318 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
5321 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
5323 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
5324 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5327 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5328 Requires<[HasSSE41]>;
5329 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5332 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5335 //===----------------------------------------------------------------------===//
5336 // SSE4.1 - Insert Instructions
5337 //===----------------------------------------------------------------------===//
5339 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5340 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5341 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5343 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5345 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5347 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5348 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5349 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
5351 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5353 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5355 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
5356 imm:$src3))]>, OpSize;
5359 let Predicates = [HasAVX] in
5360 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
5361 let Constraints = "$src1 = $dst" in
5362 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
5364 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
5365 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5366 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5368 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5370 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5372 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
5374 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5375 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
5377 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5379 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5381 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
5382 imm:$src3)))]>, OpSize;
5385 let Predicates = [HasAVX] in
5386 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
5387 let Constraints = "$src1 = $dst" in
5388 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
5390 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
5391 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5392 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
5394 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5396 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5398 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
5400 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5401 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
5403 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5405 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5407 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
5408 imm:$src3)))]>, OpSize;
5411 let Predicates = [HasAVX] in
5412 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
5413 let Constraints = "$src1 = $dst" in
5414 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
5416 // insertps has a few different modes, there's the first two here below which
5417 // are optimized inserts that won't zero arbitrary elements in the destination
5418 // vector. The next one matches the intrinsic and could zero arbitrary elements
5419 // in the target vector.
5420 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
5421 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5422 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
5424 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5426 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5428 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
5430 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5431 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
5433 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5435 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5437 (X86insrtps VR128:$src1,
5438 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
5439 imm:$src3))]>, OpSize;
5442 let Constraints = "$src1 = $dst" in
5443 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
5444 let Predicates = [HasAVX] in
5445 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
5447 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
5448 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
5450 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
5451 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
5452 Requires<[HasSSE41]>;
5454 //===----------------------------------------------------------------------===//
5455 // SSE4.1 - Round Instructions
5456 //===----------------------------------------------------------------------===//
5458 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
5459 X86MemOperand x86memop, RegisterClass RC,
5460 PatFrag mem_frag32, PatFrag mem_frag64,
5461 Intrinsic V4F32Int, Intrinsic V2F64Int> {
5462 // Intrinsic operation, reg.
5463 // Vector intrinsic operation, reg
5464 def PSr : SS4AIi8<opcps, MRMSrcReg,
5465 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5466 !strconcat(OpcodeStr,
5467 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5468 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
5471 // Vector intrinsic operation, mem
5472 def PSm : Ii8<opcps, MRMSrcMem,
5473 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5474 !strconcat(OpcodeStr,
5475 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5477 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
5479 Requires<[HasSSE41]>;
5481 // Vector intrinsic operation, reg
5482 def PDr : SS4AIi8<opcpd, MRMSrcReg,
5483 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5484 !strconcat(OpcodeStr,
5485 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5486 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
5489 // Vector intrinsic operation, mem
5490 def PDm : SS4AIi8<opcpd, MRMSrcMem,
5491 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5492 !strconcat(OpcodeStr,
5493 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5495 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
5499 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
5500 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
5501 // Intrinsic operation, reg.
5502 // Vector intrinsic operation, reg
5503 def PSr_AVX : SS4AIi8<opcps, MRMSrcReg,
5504 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5505 !strconcat(OpcodeStr,
5506 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5509 // Vector intrinsic operation, mem
5510 def PSm_AVX : Ii8<opcps, MRMSrcMem,
5511 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5512 !strconcat(OpcodeStr,
5513 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5514 []>, TA, OpSize, Requires<[HasSSE41]>;
5516 // Vector intrinsic operation, reg
5517 def PDr_AVX : SS4AIi8<opcpd, MRMSrcReg,
5518 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5519 !strconcat(OpcodeStr,
5520 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5523 // Vector intrinsic operation, mem
5524 def PDm_AVX : SS4AIi8<opcpd, MRMSrcMem,
5525 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5526 !strconcat(OpcodeStr,
5527 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5531 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
5534 Intrinsic F64Int, bit Is2Addr = 1> {
5535 // Intrinsic operation, reg.
5536 def SSr : SS4AIi8<opcss, MRMSrcReg,
5537 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5539 !strconcat(OpcodeStr,
5540 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5541 !strconcat(OpcodeStr,
5542 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5543 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
5546 // Intrinsic operation, mem.
5547 def SSm : SS4AIi8<opcss, MRMSrcMem,
5548 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
5550 !strconcat(OpcodeStr,
5551 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5552 !strconcat(OpcodeStr,
5553 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5555 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
5558 // Intrinsic operation, reg.
5559 def SDr : SS4AIi8<opcsd, MRMSrcReg,
5560 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5562 !strconcat(OpcodeStr,
5563 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5564 !strconcat(OpcodeStr,
5565 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5566 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
5569 // Intrinsic operation, mem.
5570 def SDm : SS4AIi8<opcsd, MRMSrcMem,
5571 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
5573 !strconcat(OpcodeStr,
5574 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5575 !strconcat(OpcodeStr,
5576 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5578 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
5582 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
5584 // Intrinsic operation, reg.
5585 def SSr_AVX : SS4AIi8<opcss, MRMSrcReg,
5586 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5587 !strconcat(OpcodeStr,
5588 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5591 // Intrinsic operation, mem.
5592 def SSm_AVX : SS4AIi8<opcss, MRMSrcMem,
5593 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
5594 !strconcat(OpcodeStr,
5595 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5598 // Intrinsic operation, reg.
5599 def SDr_AVX : SS4AIi8<opcsd, MRMSrcReg,
5600 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5601 !strconcat(OpcodeStr,
5602 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5605 // Intrinsic operation, mem.
5606 def SDm_AVX : SS4AIi8<opcsd, MRMSrcMem,
5607 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
5608 !strconcat(OpcodeStr,
5609 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5613 // FP round - roundss, roundps, roundsd, roundpd
5614 let Predicates = [HasAVX] in {
5616 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
5617 memopv4f32, memopv2f64,
5618 int_x86_sse41_round_ps,
5619 int_x86_sse41_round_pd>, VEX;
5620 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
5621 memopv8f32, memopv4f64,
5622 int_x86_avx_round_ps_256,
5623 int_x86_avx_round_pd_256>, VEX;
5624 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
5625 int_x86_sse41_round_ss,
5626 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
5628 // Instructions for the assembler
5629 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
5631 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
5633 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V, VEX_LIG;
5636 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
5637 memopv4f32, memopv2f64,
5638 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
5639 let Constraints = "$src1 = $dst" in
5640 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
5641 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
5643 //===----------------------------------------------------------------------===//
5644 // SSE4.1 - Packed Bit Test
5645 //===----------------------------------------------------------------------===//
5647 // ptest instruction we'll lower to this in X86ISelLowering primarily from
5648 // the intel intrinsic that corresponds to this.
5649 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5650 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5651 "vptest\t{$src2, $src1|$src1, $src2}",
5652 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5654 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5655 "vptest\t{$src2, $src1|$src1, $src2}",
5656 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5659 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
5660 "vptest\t{$src2, $src1|$src1, $src2}",
5661 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
5663 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
5664 "vptest\t{$src2, $src1|$src1, $src2}",
5665 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
5669 let Defs = [EFLAGS] in {
5670 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5671 "ptest \t{$src2, $src1|$src1, $src2}",
5672 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5674 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5675 "ptest \t{$src2, $src1|$src1, $src2}",
5676 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5680 // The bit test instructions below are AVX only
5681 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
5682 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
5683 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
5684 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5685 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
5686 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
5687 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5688 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
5692 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5693 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
5694 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
5695 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
5696 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
5699 //===----------------------------------------------------------------------===//
5700 // SSE4.1 - Misc Instructions
5701 //===----------------------------------------------------------------------===//
5703 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
5704 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
5705 "popcnt{w}\t{$src, $dst|$dst, $src}",
5706 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
5708 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
5709 "popcnt{w}\t{$src, $dst|$dst, $src}",
5710 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
5711 (implicit EFLAGS)]>, OpSize, XS;
5713 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
5714 "popcnt{l}\t{$src, $dst|$dst, $src}",
5715 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
5717 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
5718 "popcnt{l}\t{$src, $dst|$dst, $src}",
5719 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
5720 (implicit EFLAGS)]>, XS;
5722 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
5723 "popcnt{q}\t{$src, $dst|$dst, $src}",
5724 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
5726 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
5727 "popcnt{q}\t{$src, $dst|$dst, $src}",
5728 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
5729 (implicit EFLAGS)]>, XS;
5734 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
5735 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
5736 Intrinsic IntId128> {
5737 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5739 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5740 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
5741 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5743 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5746 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
5749 let Predicates = [HasAVX] in
5750 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
5751 int_x86_sse41_phminposuw>, VEX;
5752 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
5753 int_x86_sse41_phminposuw>;
5755 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
5756 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
5757 Intrinsic IntId128, bit Is2Addr = 1> {
5758 let isCommutable = 1 in
5759 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5760 (ins VR128:$src1, VR128:$src2),
5762 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5763 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5764 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
5765 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5766 (ins VR128:$src1, i128mem:$src2),
5768 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5769 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5771 (IntId128 VR128:$src1,
5772 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5775 let Predicates = [HasAVX] in {
5776 let isCommutable = 0 in
5777 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
5779 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
5781 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
5783 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
5785 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
5787 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
5789 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
5791 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
5793 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
5795 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
5797 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
5800 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
5801 (VPCMPEQQrr VR128:$src1, VR128:$src2)>;
5802 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
5803 (VPCMPEQQrm VR128:$src1, addr:$src2)>;
5806 let Constraints = "$src1 = $dst" in {
5807 let isCommutable = 0 in
5808 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
5809 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
5810 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
5811 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
5812 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
5813 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
5814 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
5815 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
5816 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
5817 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
5818 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
5821 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
5822 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
5823 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
5824 (PCMPEQQrm VR128:$src1, addr:$src2)>;
5826 /// SS48I_binop_rm - Simple SSE41 binary operator.
5827 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5828 ValueType OpVT, bit Is2Addr = 1> {
5829 let isCommutable = 1 in
5830 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5831 (ins VR128:$src1, VR128:$src2),
5833 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5834 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5835 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
5837 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5838 (ins VR128:$src1, i128mem:$src2),
5840 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5841 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5842 [(set VR128:$dst, (OpNode VR128:$src1,
5843 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
5847 let Predicates = [HasAVX] in
5848 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
5849 let Constraints = "$src1 = $dst" in
5850 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
5852 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
5853 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
5854 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
5855 X86MemOperand x86memop, bit Is2Addr = 1> {
5856 let isCommutable = 1 in
5857 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
5858 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
5860 !strconcat(OpcodeStr,
5861 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5862 !strconcat(OpcodeStr,
5863 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5864 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
5866 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
5867 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
5869 !strconcat(OpcodeStr,
5870 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5871 !strconcat(OpcodeStr,
5872 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5875 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
5879 let Predicates = [HasAVX] in {
5880 let isCommutable = 0 in {
5881 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
5882 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5883 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
5884 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5885 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
5886 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
5887 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
5888 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
5889 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
5890 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5891 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
5892 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5894 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
5895 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5896 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
5897 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5898 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
5899 VR256, memopv32i8, i256mem, 0>, VEX_4V;
5902 let Constraints = "$src1 = $dst" in {
5903 let isCommutable = 0 in {
5904 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
5905 VR128, memopv16i8, i128mem>;
5906 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
5907 VR128, memopv16i8, i128mem>;
5908 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
5909 VR128, memopv16i8, i128mem>;
5910 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
5911 VR128, memopv16i8, i128mem>;
5913 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
5914 VR128, memopv16i8, i128mem>;
5915 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
5916 VR128, memopv16i8, i128mem>;
5919 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
5920 let Predicates = [HasAVX] in {
5921 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
5922 RegisterClass RC, X86MemOperand x86memop,
5923 PatFrag mem_frag, Intrinsic IntId> {
5924 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
5925 (ins RC:$src1, RC:$src2, RC:$src3),
5926 !strconcat(OpcodeStr,
5927 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5928 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
5929 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
5931 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
5932 (ins RC:$src1, x86memop:$src2, RC:$src3),
5933 !strconcat(OpcodeStr,
5934 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5936 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
5938 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
5942 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
5943 memopv16i8, int_x86_sse41_blendvpd>;
5944 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
5945 memopv16i8, int_x86_sse41_blendvps>;
5946 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
5947 memopv16i8, int_x86_sse41_pblendvb>;
5948 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
5949 memopv32i8, int_x86_avx_blendv_pd_256>;
5950 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
5951 memopv32i8, int_x86_avx_blendv_ps_256>;
5953 let Predicates = [HasAVX] in {
5954 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
5955 (v16i8 VR128:$src2))),
5956 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
5957 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
5958 (v4i32 VR128:$src2))),
5959 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
5960 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
5961 (v4f32 VR128:$src2))),
5962 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
5963 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
5964 (v2i64 VR128:$src2))),
5965 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
5966 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
5967 (v2f64 VR128:$src2))),
5968 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
5969 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
5970 (v8i32 VR256:$src2))),
5971 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
5972 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
5973 (v8f32 VR256:$src2))),
5974 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
5975 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
5976 (v4i64 VR256:$src2))),
5977 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
5978 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
5979 (v4f64 VR256:$src2))),
5980 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
5983 /// SS41I_ternary_int - SSE 4.1 ternary operator
5984 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
5985 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5986 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5987 (ins VR128:$src1, VR128:$src2),
5988 !strconcat(OpcodeStr,
5989 "\t{$src2, $dst|$dst, $src2}"),
5990 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
5993 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5994 (ins VR128:$src1, i128mem:$src2),
5995 !strconcat(OpcodeStr,
5996 "\t{$src2, $dst|$dst, $src2}"),
5999 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
6003 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
6004 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
6005 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
6007 let Predicates = [HasSSE41] in {
6008 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6009 (v16i8 VR128:$src2))),
6010 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6011 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6012 (v4i32 VR128:$src2))),
6013 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6014 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6015 (v4f32 VR128:$src2))),
6016 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6017 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6018 (v2i64 VR128:$src2))),
6019 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6020 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6021 (v2f64 VR128:$src2))),
6022 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6025 let Predicates = [HasAVX] in
6026 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6027 "vmovntdqa\t{$src, $dst|$dst, $src}",
6028 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6030 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6031 "movntdqa\t{$src, $dst|$dst, $src}",
6032 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6035 //===----------------------------------------------------------------------===//
6036 // SSE4.2 - Compare Instructions
6037 //===----------------------------------------------------------------------===//
6039 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
6040 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
6041 Intrinsic IntId128, bit Is2Addr = 1> {
6042 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
6043 (ins VR128:$src1, VR128:$src2),
6045 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6046 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6047 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
6049 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
6050 (ins VR128:$src1, i128mem:$src2),
6052 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6053 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6055 (IntId128 VR128:$src1,
6056 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
6059 let Predicates = [HasAVX] in {
6060 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
6063 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
6064 (VPCMPGTQrr VR128:$src1, VR128:$src2)>;
6065 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
6066 (VPCMPGTQrm VR128:$src1, addr:$src2)>;
6069 let Constraints = "$src1 = $dst" in
6070 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
6072 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
6073 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
6074 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
6075 (PCMPGTQrm VR128:$src1, addr:$src2)>;
6077 //===----------------------------------------------------------------------===//
6078 // SSE4.2 - String/text Processing Instructions
6079 //===----------------------------------------------------------------------===//
6081 // Packed Compare Implicit Length Strings, Return Mask
6082 multiclass pseudo_pcmpistrm<string asm> {
6083 def REG : PseudoI<(outs VR128:$dst),
6084 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6085 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6087 def MEM : PseudoI<(outs VR128:$dst),
6088 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6089 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6090 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6093 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6094 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
6095 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6098 let Defs = [XMM0, EFLAGS], Predicates = [HasAVX] in {
6099 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6100 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6101 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6102 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6103 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6104 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6107 let Defs = [XMM0, EFLAGS] in {
6108 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6109 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6110 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6111 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6112 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6113 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6116 // Packed Compare Explicit Length Strings, Return Mask
6117 multiclass pseudo_pcmpestrm<string asm> {
6118 def REG : PseudoI<(outs VR128:$dst),
6119 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6120 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6121 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6122 def MEM : PseudoI<(outs VR128:$dst),
6123 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6124 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6125 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6128 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6129 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
6130 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6133 let Predicates = [HasAVX],
6134 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
6135 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6136 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6137 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6138 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6139 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6140 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6143 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
6144 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6145 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6146 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6147 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6148 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6149 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6152 // Packed Compare Implicit Length Strings, Return Index
6153 let Defs = [ECX, EFLAGS] in {
6154 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
6155 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6156 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6157 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6158 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
6159 (implicit EFLAGS)]>, OpSize;
6160 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6161 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6162 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6163 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
6164 (implicit EFLAGS)]>, OpSize;
6168 let Predicates = [HasAVX] in {
6169 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
6171 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
6173 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
6175 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
6177 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
6179 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
6183 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
6184 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
6185 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
6186 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
6187 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
6188 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
6190 // Packed Compare Explicit Length Strings, Return Index
6191 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
6192 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
6193 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6194 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6195 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6196 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
6197 (implicit EFLAGS)]>, OpSize;
6198 def rm : SS42AI<0x61, MRMSrcMem, (outs),
6199 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6200 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6202 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
6203 (implicit EFLAGS)]>, OpSize;
6207 let Predicates = [HasAVX] in {
6208 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
6210 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
6212 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
6214 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
6216 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
6218 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
6222 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
6223 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
6224 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
6225 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
6226 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
6227 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
6229 //===----------------------------------------------------------------------===//
6230 // SSE4.2 - CRC Instructions
6231 //===----------------------------------------------------------------------===//
6233 // No CRC instructions have AVX equivalents
6235 // crc intrinsic instruction
6236 // This set of instructions are only rm, the only difference is the size
6238 let Constraints = "$src1 = $dst" in {
6239 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
6240 (ins GR32:$src1, i8mem:$src2),
6241 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6243 (int_x86_sse42_crc32_32_8 GR32:$src1,
6244 (load addr:$src2)))]>;
6245 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
6246 (ins GR32:$src1, GR8:$src2),
6247 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6249 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
6250 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6251 (ins GR32:$src1, i16mem:$src2),
6252 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6254 (int_x86_sse42_crc32_32_16 GR32:$src1,
6255 (load addr:$src2)))]>,
6257 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6258 (ins GR32:$src1, GR16:$src2),
6259 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6261 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
6263 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6264 (ins GR32:$src1, i32mem:$src2),
6265 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6267 (int_x86_sse42_crc32_32_32 GR32:$src1,
6268 (load addr:$src2)))]>;
6269 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6270 (ins GR32:$src1, GR32:$src2),
6271 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6273 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
6274 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
6275 (ins GR64:$src1, i8mem:$src2),
6276 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6278 (int_x86_sse42_crc32_64_8 GR64:$src1,
6279 (load addr:$src2)))]>,
6281 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
6282 (ins GR64:$src1, GR8:$src2),
6283 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6285 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
6287 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
6288 (ins GR64:$src1, i64mem:$src2),
6289 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6291 (int_x86_sse42_crc32_64_64 GR64:$src1,
6292 (load addr:$src2)))]>,
6294 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
6295 (ins GR64:$src1, GR64:$src2),
6296 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6298 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
6302 //===----------------------------------------------------------------------===//
6303 // AES-NI Instructions
6304 //===----------------------------------------------------------------------===//
6306 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
6307 Intrinsic IntId128, bit Is2Addr = 1> {
6308 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
6309 (ins VR128:$src1, VR128:$src2),
6311 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6312 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6313 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
6315 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
6316 (ins VR128:$src1, i128mem:$src2),
6318 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6319 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6321 (IntId128 VR128:$src1,
6322 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
6325 // Perform One Round of an AES Encryption/Decryption Flow
6326 let Predicates = [HasAVX, HasAES] in {
6327 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
6328 int_x86_aesni_aesenc, 0>, VEX_4V;
6329 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
6330 int_x86_aesni_aesenclast, 0>, VEX_4V;
6331 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
6332 int_x86_aesni_aesdec, 0>, VEX_4V;
6333 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
6334 int_x86_aesni_aesdeclast, 0>, VEX_4V;
6337 let Constraints = "$src1 = $dst" in {
6338 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
6339 int_x86_aesni_aesenc>;
6340 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
6341 int_x86_aesni_aesenclast>;
6342 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
6343 int_x86_aesni_aesdec>;
6344 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
6345 int_x86_aesni_aesdeclast>;
6348 let Predicates = [HasAES] in {
6349 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
6350 (AESENCrr VR128:$src1, VR128:$src2)>;
6351 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
6352 (AESENCrm VR128:$src1, addr:$src2)>;
6353 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
6354 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
6355 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
6356 (AESENCLASTrm VR128:$src1, addr:$src2)>;
6357 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
6358 (AESDECrr VR128:$src1, VR128:$src2)>;
6359 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
6360 (AESDECrm VR128:$src1, addr:$src2)>;
6361 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
6362 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
6363 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
6364 (AESDECLASTrm VR128:$src1, addr:$src2)>;
6367 let Predicates = [HasAVX, HasAES], AddedComplexity = 20 in {
6368 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
6369 (VAESENCrr VR128:$src1, VR128:$src2)>;
6370 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
6371 (VAESENCrm VR128:$src1, addr:$src2)>;
6372 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
6373 (VAESENCLASTrr VR128:$src1, VR128:$src2)>;
6374 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
6375 (VAESENCLASTrm VR128:$src1, addr:$src2)>;
6376 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
6377 (VAESDECrr VR128:$src1, VR128:$src2)>;
6378 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
6379 (VAESDECrm VR128:$src1, addr:$src2)>;
6380 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
6381 (VAESDECLASTrr VR128:$src1, VR128:$src2)>;
6382 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
6383 (VAESDECLASTrm VR128:$src1, addr:$src2)>;
6386 // Perform the AES InvMixColumn Transformation
6387 let Predicates = [HasAVX, HasAES] in {
6388 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6390 "vaesimc\t{$src1, $dst|$dst, $src1}",
6392 (int_x86_aesni_aesimc VR128:$src1))]>,
6394 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
6395 (ins i128mem:$src1),
6396 "vaesimc\t{$src1, $dst|$dst, $src1}",
6398 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
6401 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6403 "aesimc\t{$src1, $dst|$dst, $src1}",
6405 (int_x86_aesni_aesimc VR128:$src1))]>,
6407 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
6408 (ins i128mem:$src1),
6409 "aesimc\t{$src1, $dst|$dst, $src1}",
6411 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
6414 // AES Round Key Generation Assist
6415 let Predicates = [HasAVX, HasAES] in {
6416 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
6417 (ins VR128:$src1, i8imm:$src2),
6418 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6420 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
6422 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
6423 (ins i128mem:$src1, i8imm:$src2),
6424 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6426 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
6430 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
6431 (ins VR128:$src1, i8imm:$src2),
6432 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6434 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
6436 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
6437 (ins i128mem:$src1, i8imm:$src2),
6438 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6440 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
6444 //===----------------------------------------------------------------------===//
6445 // CLMUL Instructions
6446 //===----------------------------------------------------------------------===//
6448 // Carry-less Multiplication instructions
6449 let Constraints = "$src1 = $dst" in {
6450 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
6451 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6452 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
6455 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
6456 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6457 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
6461 // AVX carry-less Multiplication instructions
6462 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
6463 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6464 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6467 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
6468 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6469 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6473 multiclass pclmul_alias<string asm, int immop> {
6474 def : InstAlias<!strconcat("pclmul", asm,
6475 "dq {$src, $dst|$dst, $src}"),
6476 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
6478 def : InstAlias<!strconcat("pclmul", asm,
6479 "dq {$src, $dst|$dst, $src}"),
6480 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
6482 def : InstAlias<!strconcat("vpclmul", asm,
6483 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
6484 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
6486 def : InstAlias<!strconcat("vpclmul", asm,
6487 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
6488 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
6490 defm : pclmul_alias<"hqhq", 0x11>;
6491 defm : pclmul_alias<"hqlq", 0x01>;
6492 defm : pclmul_alias<"lqhq", 0x10>;
6493 defm : pclmul_alias<"lqlq", 0x00>;
6495 //===----------------------------------------------------------------------===//
6497 //===----------------------------------------------------------------------===//
6499 //===----------------------------------------------------------------------===//
6500 // VBROADCAST - Load from memory and broadcast to all elements of the
6501 // destination operand
6503 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
6504 X86MemOperand x86memop, Intrinsic Int> :
6505 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
6506 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6507 [(set RC:$dst, (Int addr:$src))]>, VEX;
6509 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
6510 int_x86_avx_vbroadcastss>;
6511 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
6512 int_x86_avx_vbroadcastss_256>;
6513 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
6514 int_x86_avx_vbroadcast_sd_256>;
6515 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
6516 int_x86_avx_vbroadcastf128_pd_256>;
6518 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
6519 (VBROADCASTF128 addr:$src)>;
6521 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
6522 (VBROADCASTSSY addr:$src)>;
6523 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
6524 (VBROADCASTSD addr:$src)>;
6525 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
6526 (VBROADCASTSSY addr:$src)>;
6527 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
6528 (VBROADCASTSD addr:$src)>;
6530 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
6531 (VBROADCASTSS addr:$src)>;
6532 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
6533 (VBROADCASTSS addr:$src)>;
6535 //===----------------------------------------------------------------------===//
6536 // VINSERTF128 - Insert packed floating-point values
6538 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
6539 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
6540 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6542 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
6543 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
6544 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6547 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
6548 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6549 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
6550 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6551 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
6552 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6554 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
6556 (VINSERTF128rr VR256:$src1, VR128:$src2,
6557 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6558 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
6560 (VINSERTF128rr VR256:$src1, VR128:$src2,
6561 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6562 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
6564 (VINSERTF128rr VR256:$src1, VR128:$src2,
6565 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6566 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
6568 (VINSERTF128rr VR256:$src1, VR128:$src2,
6569 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6570 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
6572 (VINSERTF128rr VR256:$src1, VR128:$src2,
6573 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6574 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
6576 (VINSERTF128rr VR256:$src1, VR128:$src2,
6577 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6579 //===----------------------------------------------------------------------===//
6580 // VEXTRACTF128 - Extract packed floating-point values
6582 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
6583 (ins VR256:$src1, i8imm:$src2),
6584 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6586 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
6587 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
6588 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6591 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
6592 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6593 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
6594 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6595 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
6596 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6598 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6599 (v4f32 (VEXTRACTF128rr
6600 (v8f32 VR256:$src1),
6601 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6602 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6603 (v2f64 (VEXTRACTF128rr
6604 (v4f64 VR256:$src1),
6605 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6606 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6607 (v4i32 (VEXTRACTF128rr
6608 (v8i32 VR256:$src1),
6609 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6610 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6611 (v2i64 (VEXTRACTF128rr
6612 (v4i64 VR256:$src1),
6613 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6614 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6615 (v8i16 (VEXTRACTF128rr
6616 (v16i16 VR256:$src1),
6617 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6618 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6619 (v16i8 (VEXTRACTF128rr
6620 (v32i8 VR256:$src1),
6621 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6623 //===----------------------------------------------------------------------===//
6624 // VMASKMOV - Conditional SIMD Packed Loads and Stores
6626 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
6627 Intrinsic IntLd, Intrinsic IntLd256,
6628 Intrinsic IntSt, Intrinsic IntSt256,
6629 PatFrag pf128, PatFrag pf256> {
6630 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
6631 (ins VR128:$src1, f128mem:$src2),
6632 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6633 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
6635 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
6636 (ins VR256:$src1, f256mem:$src2),
6637 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6638 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
6640 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
6641 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
6642 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6643 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
6644 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
6645 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
6646 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6647 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
6650 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
6651 int_x86_avx_maskload_ps,
6652 int_x86_avx_maskload_ps_256,
6653 int_x86_avx_maskstore_ps,
6654 int_x86_avx_maskstore_ps_256,
6655 memopv4f32, memopv8f32>;
6656 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
6657 int_x86_avx_maskload_pd,
6658 int_x86_avx_maskload_pd_256,
6659 int_x86_avx_maskstore_pd,
6660 int_x86_avx_maskstore_pd_256,
6661 memopv2f64, memopv4f64>;
6663 //===----------------------------------------------------------------------===//
6664 // VPERMIL - Permute Single and Double Floating-Point Values
6666 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
6667 RegisterClass RC, X86MemOperand x86memop_f,
6668 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
6669 Intrinsic IntVar, Intrinsic IntImm> {
6670 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
6671 (ins RC:$src1, RC:$src2),
6672 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6673 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
6674 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
6675 (ins RC:$src1, x86memop_i:$src2),
6676 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6677 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
6679 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
6680 (ins RC:$src1, i8imm:$src2),
6681 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6682 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
6683 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
6684 (ins x86memop_f:$src1, i8imm:$src2),
6685 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6686 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
6689 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
6690 memopv4f32, memopv4i32,
6691 int_x86_avx_vpermilvar_ps,
6692 int_x86_avx_vpermil_ps>;
6693 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
6694 memopv8f32, memopv8i32,
6695 int_x86_avx_vpermilvar_ps_256,
6696 int_x86_avx_vpermil_ps_256>;
6697 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
6698 memopv2f64, memopv2i64,
6699 int_x86_avx_vpermilvar_pd,
6700 int_x86_avx_vpermil_pd>;
6701 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
6702 memopv4f64, memopv4i64,
6703 int_x86_avx_vpermilvar_pd_256,
6704 int_x86_avx_vpermil_pd_256>;
6706 def : Pat<(v8f32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
6707 (VPERMILPSYri VR256:$src1, imm:$imm)>;
6708 def : Pat<(v4f64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
6709 (VPERMILPDYri VR256:$src1, imm:$imm)>;
6710 def : Pat<(v8i32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
6711 (VPERMILPSYri VR256:$src1, imm:$imm)>;
6712 def : Pat<(v4i64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
6713 (VPERMILPDYri VR256:$src1, imm:$imm)>;
6715 //===----------------------------------------------------------------------===//
6716 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
6718 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
6719 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
6720 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6722 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
6723 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
6724 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6727 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
6728 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6729 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
6730 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6731 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
6732 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6734 def : Pat<(int_x86_avx_vperm2f128_ps_256
6735 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
6736 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6737 def : Pat<(int_x86_avx_vperm2f128_pd_256
6738 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
6739 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6740 def : Pat<(int_x86_avx_vperm2f128_si_256
6741 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
6742 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6744 def : Pat<(v8f32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6745 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6746 def : Pat<(v8i32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6747 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6748 def : Pat<(v4i64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6749 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6750 def : Pat<(v4f64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6751 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6752 def : Pat<(v32i8 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6753 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6754 def : Pat<(v16i16 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6755 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6757 //===----------------------------------------------------------------------===//
6758 // VZERO - Zero YMM registers
6760 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
6761 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
6762 // Zero All YMM registers
6763 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
6764 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
6766 // Zero Upper bits of YMM registers
6767 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
6768 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
6771 //===----------------------------------------------------------------------===//
6772 // Half precision conversion instructions
6774 let Predicates = [HasAVX, HasF16C] in {
6775 def VCVTPH2PSrm : I<0x13, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
6776 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
6777 def VCVTPH2PSrr : I<0x13, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
6778 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
6779 def VCVTPH2PSYrm : I<0x13, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
6780 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
6781 def VCVTPH2PSYrr : I<0x13, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
6782 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
6783 def VCVTPS2PHmr : Ii8<0x1D, MRMDestMem, (outs f64mem:$dst),
6784 (ins VR128:$src1, i32i8imm:$src2),
6785 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
6787 def VCVTPS2PHrr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
6788 (ins VR128:$src1, i32i8imm:$src2),
6789 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
6791 def VCVTPS2PHYmr : Ii8<0x1D, MRMDestMem, (outs f128mem:$dst),
6792 (ins VR256:$src1, i32i8imm:$src2),
6793 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
6795 def VCVTPS2PHYrr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
6796 (ins VR256:$src1, i32i8imm:$src2),
6797 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,