1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 let Sched = WriteVecLogic in
124 def SSE_VEC_BIT_ITINS_P : OpndItins<
125 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
128 def SSE_BIT_ITINS_P : OpndItins<
129 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
132 let Sched = WriteVecALU in {
133 def SSE_INTALU_ITINS_P : OpndItins<
134 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
137 def SSE_INTALUQ_ITINS_P : OpndItins<
138 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
142 let Sched = WriteVecIMul in
143 def SSE_INTMUL_ITINS_P : OpndItins<
144 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
147 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
148 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
151 def SSE_MOVA_ITINS : OpndItins<
152 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
155 def SSE_MOVU_ITINS : OpndItins<
156 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
159 def SSE_DPPD_ITINS : OpndItins<
160 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
163 def SSE_DPPS_ITINS : OpndItins<
164 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
167 def DEFAULT_ITINS : OpndItins<
168 IIC_ALU_NONMEM, IIC_ALU_MEM
171 def SSE_EXTRACT_ITINS : OpndItins<
172 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
175 def SSE_INSERT_ITINS : OpndItins<
176 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
179 let Sched = WriteMPSAD in
180 def SSE_MPSADBW_ITINS : OpndItins<
181 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
184 let Sched = WriteVecIMul in
185 def SSE_PMULLD_ITINS : OpndItins<
186 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
189 // Definitions for backward compatibility.
190 // The instructions mapped on these definitions uses a different itinerary
191 // than the actual scheduling model.
192 let Sched = WriteShuffle in
193 def DEFAULT_ITINS_SHUFFLESCHED : OpndItins<
194 IIC_ALU_NONMEM, IIC_ALU_MEM
197 let Sched = WriteVecIMul in
198 def DEFAULT_ITINS_VECIMULSCHED : OpndItins<
199 IIC_ALU_NONMEM, IIC_ALU_MEM
202 let Sched = WriteShuffle in
203 def SSE_INTALU_ITINS_SHUFF_P : OpndItins<
204 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
207 let Sched = WriteMPSAD in
208 def DEFAULT_ITINS_MPSADSCHED : OpndItins<
209 IIC_ALU_NONMEM, IIC_ALU_MEM
212 let Sched = WriteFBlend in
213 def DEFAULT_ITINS_FBLENDSCHED : OpndItins<
214 IIC_ALU_NONMEM, IIC_ALU_MEM
217 let Sched = WriteBlend in
218 def DEFAULT_ITINS_BLENDSCHED : OpndItins<
219 IIC_ALU_NONMEM, IIC_ALU_MEM
222 let Sched = WriteVarBlend in
223 def DEFAULT_ITINS_VARBLENDSCHED : OpndItins<
224 IIC_ALU_NONMEM, IIC_ALU_MEM
227 let Sched = WriteFBlend in
228 def SSE_INTALU_ITINS_FBLEND_P : OpndItins<
229 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
232 let Sched = WriteBlend in
233 def SSE_INTALU_ITINS_BLEND_P : OpndItins<
234 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
237 //===----------------------------------------------------------------------===//
238 // SSE 1 & 2 Instructions Classes
239 //===----------------------------------------------------------------------===//
241 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
242 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
243 RegisterClass RC, X86MemOperand x86memop,
246 let isCommutable = 1 in {
247 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
249 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
250 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
251 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
252 Sched<[itins.Sched]>;
254 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
256 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
257 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
258 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
259 Sched<[itins.Sched.Folded, ReadAfterLd]>;
262 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
263 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
264 string asm, string SSEVer, string FPSizeStr,
265 Operand memopr, ComplexPattern mem_cpat,
268 let isCodeGenOnly = 1 in {
269 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
271 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
272 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
273 [(set RC:$dst, (!cast<Intrinsic>(
274 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
275 RC:$src1, RC:$src2))], itins.rr>,
276 Sched<[itins.Sched]>;
277 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
279 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
280 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
281 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
282 SSEVer, "_", OpcodeStr, FPSizeStr))
283 RC:$src1, mem_cpat:$src2))], itins.rm>,
284 Sched<[itins.Sched.Folded, ReadAfterLd]>;
288 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
289 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
290 RegisterClass RC, ValueType vt,
291 X86MemOperand x86memop, PatFrag mem_frag,
292 Domain d, OpndItins itins, bit Is2Addr = 1> {
293 let isCommutable = 1 in
294 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
296 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
297 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
298 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
299 Sched<[itins.Sched]>;
301 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
303 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
304 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
305 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
307 Sched<[itins.Sched.Folded, ReadAfterLd]>;
310 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
311 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
312 string OpcodeStr, X86MemOperand x86memop,
313 list<dag> pat_rr, list<dag> pat_rm,
315 let isCommutable = 1, hasSideEffects = 0 in
316 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
318 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
319 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
320 pat_rr, NoItinerary, d>,
321 Sched<[WriteVecLogic]>;
322 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
324 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
325 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
326 pat_rm, NoItinerary, d>,
327 Sched<[WriteVecLogicLd, ReadAfterLd]>;
330 //===----------------------------------------------------------------------===//
331 // Non-instruction patterns
332 //===----------------------------------------------------------------------===//
334 // A vector extract of the first f32/f64 position is a subregister copy
335 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
336 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
337 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
338 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
340 // A 128-bit subvector extract from the first 256-bit vector position
341 // is a subregister copy that needs no instruction.
342 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
343 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
344 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
345 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
347 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
348 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
349 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
350 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
352 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
353 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
354 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
355 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
357 // A 128-bit subvector insert to the first 256-bit vector position
358 // is a subregister copy that needs no instruction.
359 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
360 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
361 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
362 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
363 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
364 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
365 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
366 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
367 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
368 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
369 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
370 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
371 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
374 // Implicitly promote a 32-bit scalar to a vector.
375 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
376 (COPY_TO_REGCLASS FR32:$src, VR128)>;
377 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
378 (COPY_TO_REGCLASS FR32:$src, VR128)>;
379 // Implicitly promote a 64-bit scalar to a vector.
380 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
381 (COPY_TO_REGCLASS FR64:$src, VR128)>;
382 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
383 (COPY_TO_REGCLASS FR64:$src, VR128)>;
385 // Bitcasts between 128-bit vector types. Return the original type since
386 // no instruction is needed for the conversion
387 let Predicates = [HasSSE2] in {
388 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
389 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
390 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
391 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
392 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
393 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
394 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
395 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
396 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
397 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
398 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
399 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
400 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
401 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
402 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
403 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
404 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
405 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
406 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
407 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
408 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
409 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
410 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
411 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
412 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
413 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
414 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
415 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
416 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
417 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
420 // Bitcasts between 256-bit vector types. Return the original type since
421 // no instruction is needed for the conversion
422 let Predicates = [HasAVX] in {
423 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
424 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
425 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
426 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
427 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
428 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
429 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
430 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
431 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
432 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
433 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
434 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
435 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
436 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
437 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
438 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
439 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
440 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
441 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
442 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
443 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
444 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
445 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
446 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
447 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
448 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
449 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
450 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
451 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
452 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
455 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
456 // This is expanded by ExpandPostRAPseudos.
457 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
458 isPseudo = 1, SchedRW = [WriteZero] in {
459 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
460 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
461 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
462 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
465 //===----------------------------------------------------------------------===//
466 // AVX & SSE - Zero/One Vectors
467 //===----------------------------------------------------------------------===//
469 // Alias instruction that maps zero vector to pxor / xorp* for sse.
470 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
471 // swizzled by ExecutionDepsFix to pxor.
472 // We set canFoldAsLoad because this can be converted to a constant-pool
473 // load of an all-zeros value if folding it would be beneficial.
474 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
475 isPseudo = 1, SchedRW = [WriteZero] in {
476 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
477 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
480 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
481 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
482 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
483 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
484 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
487 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
488 // and doesn't need it because on sandy bridge the register is set to zero
489 // at the rename stage without using any execution unit, so SET0PSY
490 // and SET0PDY can be used for vector int instructions without penalty
491 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
492 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
493 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
494 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
497 let Predicates = [HasAVX] in
498 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
500 let Predicates = [HasAVX2] in {
501 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
502 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
503 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
504 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
507 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
508 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
509 let Predicates = [HasAVX1Only] in {
510 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
511 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
512 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
514 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
515 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
516 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
518 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
519 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
520 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
522 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
523 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
524 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
527 // We set canFoldAsLoad because this can be converted to a constant-pool
528 // load of an all-ones value if folding it would be beneficial.
529 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
530 isPseudo = 1, SchedRW = [WriteZero] in {
531 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
532 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
533 let Predicates = [HasAVX2] in
534 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
535 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
539 //===----------------------------------------------------------------------===//
540 // SSE 1 & 2 - Move FP Scalar Instructions
542 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
543 // register copies because it's a partial register update; Register-to-register
544 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
545 // that the insert be implementable in terms of a copy, and just mentioned, we
546 // don't use movss/movsd for copies.
547 //===----------------------------------------------------------------------===//
549 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
550 X86MemOperand x86memop, string base_opc,
552 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
553 (ins VR128:$src1, RC:$src2),
554 !strconcat(base_opc, asm_opr),
555 [(set VR128:$dst, (vt (OpNode VR128:$src1,
556 (scalar_to_vector RC:$src2))))],
557 IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
559 // For the disassembler
560 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
561 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
562 (ins VR128:$src1, RC:$src2),
563 !strconcat(base_opc, asm_opr),
564 [], IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
567 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
568 X86MemOperand x86memop, string OpcodeStr> {
570 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
571 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
574 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
575 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
576 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
577 VEX, VEX_LIG, Sched<[WriteStore]>;
579 let Constraints = "$src1 = $dst" in {
580 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
581 "\t{$src2, $dst|$dst, $src2}">;
584 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
585 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
586 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
590 // Loading from memory automatically zeroing upper bits.
591 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
592 PatFrag mem_pat, string OpcodeStr> {
593 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
595 [(set RC:$dst, (mem_pat addr:$src))],
596 IIC_SSE_MOV_S_RM>, VEX, VEX_LIG, Sched<[WriteLoad]>;
597 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
598 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
599 [(set RC:$dst, (mem_pat addr:$src))],
600 IIC_SSE_MOV_S_RM>, Sched<[WriteLoad]>;
603 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss">, XS;
604 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd">, XD;
606 let canFoldAsLoad = 1, isReMaterializable = 1 in {
607 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
609 let AddedComplexity = 20 in
610 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
614 let Predicates = [UseAVX] in {
615 let AddedComplexity = 15 in {
616 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
617 // MOVS{S,D} to the lower bits.
618 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
619 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
620 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
621 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
622 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
623 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
624 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
625 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
627 // Move low f32 and clear high bits.
628 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
629 (SUBREG_TO_REG (i32 0),
630 (VMOVSSrr (v4f32 (V_SET0)),
631 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
632 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
633 (SUBREG_TO_REG (i32 0),
634 (VMOVSSrr (v4i32 (V_SET0)),
635 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
638 let AddedComplexity = 20 in {
639 // MOVSSrm zeros the high parts of the register; represent this
640 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
641 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
642 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
643 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
644 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
645 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
646 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
648 // MOVSDrm zeros the high parts of the register; represent this
649 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
650 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
651 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
652 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
653 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
654 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
655 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
656 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
657 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
658 def : Pat<(v2f64 (X86vzload addr:$src)),
659 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
661 // Represent the same patterns above but in the form they appear for
663 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
664 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
665 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
666 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
667 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
668 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
669 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
670 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
671 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
673 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
674 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
675 (SUBREG_TO_REG (i32 0),
676 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
678 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
679 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
680 (SUBREG_TO_REG (i64 0),
681 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
683 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
684 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
685 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
687 // Move low f64 and clear high bits.
688 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
689 (SUBREG_TO_REG (i32 0),
690 (VMOVSDrr (v2f64 (V_SET0)),
691 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
693 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
694 (SUBREG_TO_REG (i32 0),
695 (VMOVSDrr (v2i64 (V_SET0)),
696 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
698 // Extract and store.
699 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
701 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
702 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
704 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
706 // Shuffle with VMOVSS
707 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
708 (VMOVSSrr (v4i32 VR128:$src1),
709 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
710 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
711 (VMOVSSrr (v4f32 VR128:$src1),
712 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
715 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
716 (SUBREG_TO_REG (i32 0),
717 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
718 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
720 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
721 (SUBREG_TO_REG (i32 0),
722 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
723 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
726 // Shuffle with VMOVSD
727 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
728 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
729 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
730 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
731 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
732 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
733 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
734 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
737 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
738 (SUBREG_TO_REG (i32 0),
739 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
740 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
742 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
743 (SUBREG_TO_REG (i32 0),
744 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
745 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
749 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
750 // is during lowering, where it's not possible to recognize the fold cause
751 // it has two uses through a bitcast. One use disappears at isel time and the
752 // fold opportunity reappears.
753 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
754 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
755 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
756 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
757 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
758 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
759 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
760 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
763 let Predicates = [UseSSE1] in {
764 let AddedComplexity = 15 in {
765 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
766 // MOVSS to the lower bits.
767 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
768 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
769 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
770 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
771 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
772 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
775 let AddedComplexity = 20 in {
776 // MOVSSrm already zeros the high parts of the register.
777 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
778 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
779 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
780 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
781 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
782 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
785 // Extract and store.
786 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
788 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
790 // Shuffle with MOVSS
791 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
792 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
793 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
794 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
797 let Predicates = [UseSSE2] in {
798 let AddedComplexity = 15 in {
799 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
800 // MOVSD to the lower bits.
801 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
802 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
805 let AddedComplexity = 20 in {
806 // MOVSDrm already zeros the high parts of the register.
807 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
808 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
809 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
810 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
811 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
812 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
813 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
814 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
815 def : Pat<(v2f64 (X86vzload addr:$src)),
816 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
819 // Extract and store.
820 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
822 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
824 // Shuffle with MOVSD
825 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
826 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
827 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
828 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
829 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
830 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
831 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
832 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
834 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
835 // is during lowering, where it's not possible to recognize the fold cause
836 // it has two uses through a bitcast. One use disappears at isel time and the
837 // fold opportunity reappears.
838 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
839 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
840 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
841 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
842 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
843 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
844 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
845 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
848 //===----------------------------------------------------------------------===//
849 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
850 //===----------------------------------------------------------------------===//
852 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
853 X86MemOperand x86memop, PatFrag ld_frag,
854 string asm, Domain d,
856 bit IsReMaterializable = 1> {
857 let neverHasSideEffects = 1 in
858 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
859 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
860 Sched<[WriteFShuffle]>;
861 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
862 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
863 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
864 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
868 let Predicates = [HasAVX, NoVLX] in {
869 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
870 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
872 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
873 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
875 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
876 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
878 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
879 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
882 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
883 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
885 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
886 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
888 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
889 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
891 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
892 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
896 let Predicates = [UseSSE1] in {
897 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
898 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
900 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
901 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
904 let Predicates = [UseSSE2] in {
905 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
906 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
908 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
909 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
913 let SchedRW = [WriteStore], Predicates = [HasAVX, NoVLX] in {
914 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
915 "movaps\t{$src, $dst|$dst, $src}",
916 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
917 IIC_SSE_MOVA_P_MR>, VEX;
918 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
919 "movapd\t{$src, $dst|$dst, $src}",
920 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
921 IIC_SSE_MOVA_P_MR>, VEX;
922 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
923 "movups\t{$src, $dst|$dst, $src}",
924 [(store (v4f32 VR128:$src), addr:$dst)],
925 IIC_SSE_MOVU_P_MR>, VEX;
926 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
927 "movupd\t{$src, $dst|$dst, $src}",
928 [(store (v2f64 VR128:$src), addr:$dst)],
929 IIC_SSE_MOVU_P_MR>, VEX;
930 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
931 "movaps\t{$src, $dst|$dst, $src}",
932 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
933 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
934 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
935 "movapd\t{$src, $dst|$dst, $src}",
936 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
937 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
938 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
939 "movups\t{$src, $dst|$dst, $src}",
940 [(store (v8f32 VR256:$src), addr:$dst)],
941 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
942 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
943 "movupd\t{$src, $dst|$dst, $src}",
944 [(store (v4f64 VR256:$src), addr:$dst)],
945 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
949 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
950 SchedRW = [WriteFShuffle] in {
951 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
953 "movaps\t{$src, $dst|$dst, $src}", [],
954 IIC_SSE_MOVA_P_RR>, VEX;
955 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
957 "movapd\t{$src, $dst|$dst, $src}", [],
958 IIC_SSE_MOVA_P_RR>, VEX;
959 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
961 "movups\t{$src, $dst|$dst, $src}", [],
962 IIC_SSE_MOVU_P_RR>, VEX;
963 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
965 "movupd\t{$src, $dst|$dst, $src}", [],
966 IIC_SSE_MOVU_P_RR>, VEX;
967 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
969 "movaps\t{$src, $dst|$dst, $src}", [],
970 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
971 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
973 "movapd\t{$src, $dst|$dst, $src}", [],
974 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
975 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
977 "movups\t{$src, $dst|$dst, $src}", [],
978 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
979 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
981 "movupd\t{$src, $dst|$dst, $src}", [],
982 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
985 let Predicates = [HasAVX] in {
986 def : Pat<(v8i32 (X86vzmovl
987 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
988 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
989 def : Pat<(v4i64 (X86vzmovl
990 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
991 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
992 def : Pat<(v8f32 (X86vzmovl
993 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
994 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
995 def : Pat<(v4f64 (X86vzmovl
996 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
997 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
1001 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
1002 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1003 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
1004 (VMOVUPDYmr addr:$dst, VR256:$src)>;
1006 let SchedRW = [WriteStore] in {
1007 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1008 "movaps\t{$src, $dst|$dst, $src}",
1009 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
1011 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1012 "movapd\t{$src, $dst|$dst, $src}",
1013 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
1015 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1016 "movups\t{$src, $dst|$dst, $src}",
1017 [(store (v4f32 VR128:$src), addr:$dst)],
1019 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1020 "movupd\t{$src, $dst|$dst, $src}",
1021 [(store (v2f64 VR128:$src), addr:$dst)],
1026 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1027 SchedRW = [WriteFShuffle] in {
1028 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
1029 "movaps\t{$src, $dst|$dst, $src}", [],
1031 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
1032 "movapd\t{$src, $dst|$dst, $src}", [],
1034 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
1035 "movups\t{$src, $dst|$dst, $src}", [],
1037 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
1038 "movupd\t{$src, $dst|$dst, $src}", [],
1042 let Predicates = [HasAVX] in {
1043 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1044 (VMOVUPSmr addr:$dst, VR128:$src)>;
1045 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1046 (VMOVUPDmr addr:$dst, VR128:$src)>;
1049 let Predicates = [UseSSE1] in
1050 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1051 (MOVUPSmr addr:$dst, VR128:$src)>;
1052 let Predicates = [UseSSE2] in
1053 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1054 (MOVUPDmr addr:$dst, VR128:$src)>;
1056 // Use vmovaps/vmovups for AVX integer load/store.
1057 let Predicates = [HasAVX, NoVLX] in {
1058 // 128-bit load/store
1059 def : Pat<(alignedloadv2i64 addr:$src),
1060 (VMOVAPSrm addr:$src)>;
1061 def : Pat<(loadv2i64 addr:$src),
1062 (VMOVUPSrm addr:$src)>;
1064 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1065 (VMOVAPSmr addr:$dst, VR128:$src)>;
1066 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1067 (VMOVAPSmr addr:$dst, VR128:$src)>;
1068 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1069 (VMOVAPSmr addr:$dst, VR128:$src)>;
1070 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1071 (VMOVAPSmr addr:$dst, VR128:$src)>;
1072 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1073 (VMOVUPSmr addr:$dst, VR128:$src)>;
1074 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1075 (VMOVUPSmr addr:$dst, VR128:$src)>;
1076 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1077 (VMOVUPSmr addr:$dst, VR128:$src)>;
1078 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1079 (VMOVUPSmr addr:$dst, VR128:$src)>;
1081 // 256-bit load/store
1082 def : Pat<(alignedloadv4i64 addr:$src),
1083 (VMOVAPSYrm addr:$src)>;
1084 def : Pat<(loadv4i64 addr:$src),
1085 (VMOVUPSYrm addr:$src)>;
1086 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1087 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1088 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1089 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1090 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1091 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1092 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1093 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1094 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1095 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1096 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1097 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1098 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1099 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1100 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1101 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1103 // Special patterns for storing subvector extracts of lower 128-bits
1104 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1105 def : Pat<(alignedstore (v2f64 (extract_subvector
1106 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1107 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1108 def : Pat<(alignedstore (v4f32 (extract_subvector
1109 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1110 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1111 def : Pat<(alignedstore (v2i64 (extract_subvector
1112 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1113 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1114 def : Pat<(alignedstore (v4i32 (extract_subvector
1115 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1116 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1117 def : Pat<(alignedstore (v8i16 (extract_subvector
1118 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1119 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1120 def : Pat<(alignedstore (v16i8 (extract_subvector
1121 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1122 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1124 def : Pat<(store (v2f64 (extract_subvector
1125 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1126 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1127 def : Pat<(store (v4f32 (extract_subvector
1128 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1129 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1130 def : Pat<(store (v2i64 (extract_subvector
1131 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1132 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1133 def : Pat<(store (v4i32 (extract_subvector
1134 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1135 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1136 def : Pat<(store (v8i16 (extract_subvector
1137 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1138 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1139 def : Pat<(store (v16i8 (extract_subvector
1140 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1141 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1144 // Use movaps / movups for SSE integer load / store (one byte shorter).
1145 // The instructions selected below are then converted to MOVDQA/MOVDQU
1146 // during the SSE domain pass.
1147 let Predicates = [UseSSE1] in {
1148 def : Pat<(alignedloadv2i64 addr:$src),
1149 (MOVAPSrm addr:$src)>;
1150 def : Pat<(loadv2i64 addr:$src),
1151 (MOVUPSrm addr:$src)>;
1153 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1154 (MOVAPSmr addr:$dst, VR128:$src)>;
1155 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1156 (MOVAPSmr addr:$dst, VR128:$src)>;
1157 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1158 (MOVAPSmr addr:$dst, VR128:$src)>;
1159 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1160 (MOVAPSmr addr:$dst, VR128:$src)>;
1161 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1162 (MOVUPSmr addr:$dst, VR128:$src)>;
1163 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1164 (MOVUPSmr addr:$dst, VR128:$src)>;
1165 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1166 (MOVUPSmr addr:$dst, VR128:$src)>;
1167 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1168 (MOVUPSmr addr:$dst, VR128:$src)>;
1171 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1172 // bits are disregarded. FIXME: Set encoding to pseudo!
1173 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1174 let isCodeGenOnly = 1 in {
1175 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1176 "movaps\t{$src, $dst|$dst, $src}",
1177 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1178 IIC_SSE_MOVA_P_RM>, VEX;
1179 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1180 "movapd\t{$src, $dst|$dst, $src}",
1181 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1182 IIC_SSE_MOVA_P_RM>, VEX;
1183 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1184 "movaps\t{$src, $dst|$dst, $src}",
1185 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1187 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1188 "movapd\t{$src, $dst|$dst, $src}",
1189 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1194 //===----------------------------------------------------------------------===//
1195 // SSE 1 & 2 - Move Low packed FP Instructions
1196 //===----------------------------------------------------------------------===//
1198 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1199 string base_opc, string asm_opr,
1200 InstrItinClass itin> {
1201 def PSrm : PI<opc, MRMSrcMem,
1202 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1203 !strconcat(base_opc, "s", asm_opr),
1205 (psnode VR128:$src1,
1206 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1207 itin, SSEPackedSingle>, PS,
1208 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1210 def PDrm : PI<opc, MRMSrcMem,
1211 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1212 !strconcat(base_opc, "d", asm_opr),
1213 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1214 (scalar_to_vector (loadf64 addr:$src2)))))],
1215 itin, SSEPackedDouble>, PD,
1216 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1220 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1221 string base_opc, InstrItinClass itin> {
1222 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1223 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1226 let Constraints = "$src1 = $dst" in
1227 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1228 "\t{$src2, $dst|$dst, $src2}",
1232 let AddedComplexity = 20 in {
1233 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1237 let SchedRW = [WriteStore] in {
1238 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1239 "movlps\t{$src, $dst|$dst, $src}",
1240 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1241 (iPTR 0))), addr:$dst)],
1242 IIC_SSE_MOV_LH>, VEX;
1243 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1244 "movlpd\t{$src, $dst|$dst, $src}",
1245 [(store (f64 (vector_extract (v2f64 VR128:$src),
1246 (iPTR 0))), addr:$dst)],
1247 IIC_SSE_MOV_LH>, VEX;
1248 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1249 "movlps\t{$src, $dst|$dst, $src}",
1250 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1251 (iPTR 0))), addr:$dst)],
1253 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1254 "movlpd\t{$src, $dst|$dst, $src}",
1255 [(store (f64 (vector_extract (v2f64 VR128:$src),
1256 (iPTR 0))), addr:$dst)],
1260 let Predicates = [HasAVX] in {
1261 // Shuffle with VMOVLPS
1262 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1263 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1264 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1265 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1267 // Shuffle with VMOVLPD
1268 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1269 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1270 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1271 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1274 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1276 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1277 def : Pat<(store (v4i32 (X86Movlps
1278 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1279 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1280 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1282 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1283 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1285 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1288 let Predicates = [UseSSE1] in {
1289 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1290 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1291 (iPTR 0))), addr:$src1),
1292 (MOVLPSmr addr:$src1, VR128:$src2)>;
1294 // Shuffle with MOVLPS
1295 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1296 (MOVLPSrm VR128:$src1, addr:$src2)>;
1297 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1298 (MOVLPSrm VR128:$src1, addr:$src2)>;
1299 def : Pat<(X86Movlps VR128:$src1,
1300 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1301 (MOVLPSrm VR128:$src1, addr:$src2)>;
1304 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1306 (MOVLPSmr addr:$src1, VR128:$src2)>;
1307 def : Pat<(store (v4i32 (X86Movlps
1308 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1310 (MOVLPSmr addr:$src1, VR128:$src2)>;
1313 let Predicates = [UseSSE2] in {
1314 // Shuffle with MOVLPD
1315 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1316 (MOVLPDrm VR128:$src1, addr:$src2)>;
1317 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1318 (MOVLPDrm VR128:$src1, addr:$src2)>;
1321 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1323 (MOVLPDmr addr:$src1, VR128:$src2)>;
1324 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1326 (MOVLPDmr addr:$src1, VR128:$src2)>;
1329 //===----------------------------------------------------------------------===//
1330 // SSE 1 & 2 - Move Hi packed FP Instructions
1331 //===----------------------------------------------------------------------===//
1333 let AddedComplexity = 20 in {
1334 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1338 let SchedRW = [WriteStore] in {
1339 // v2f64 extract element 1 is always custom lowered to unpack high to low
1340 // and extract element 0 so the non-store version isn't too horrible.
1341 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1342 "movhps\t{$src, $dst|$dst, $src}",
1343 [(store (f64 (vector_extract
1344 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1345 (bc_v2f64 (v4f32 VR128:$src))),
1346 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1347 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1348 "movhpd\t{$src, $dst|$dst, $src}",
1349 [(store (f64 (vector_extract
1350 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1351 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1352 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1353 "movhps\t{$src, $dst|$dst, $src}",
1354 [(store (f64 (vector_extract
1355 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1356 (bc_v2f64 (v4f32 VR128:$src))),
1357 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1358 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1359 "movhpd\t{$src, $dst|$dst, $src}",
1360 [(store (f64 (vector_extract
1361 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1362 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1365 let Predicates = [HasAVX] in {
1367 def : Pat<(X86Movlhps VR128:$src1,
1368 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1369 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1370 def : Pat<(X86Movlhps VR128:$src1,
1371 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1372 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1374 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1375 // is during lowering, where it's not possible to recognize the load fold
1376 // cause it has two uses through a bitcast. One use disappears at isel time
1377 // and the fold opportunity reappears.
1378 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1379 (scalar_to_vector (loadf64 addr:$src2)))),
1380 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1383 let Predicates = [UseSSE1] in {
1385 def : Pat<(X86Movlhps VR128:$src1,
1386 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1387 (MOVHPSrm VR128:$src1, addr:$src2)>;
1388 def : Pat<(X86Movlhps VR128:$src1,
1389 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1390 (MOVHPSrm VR128:$src1, addr:$src2)>;
1393 let Predicates = [UseSSE2] in {
1394 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1395 // is during lowering, where it's not possible to recognize the load fold
1396 // cause it has two uses through a bitcast. One use disappears at isel time
1397 // and the fold opportunity reappears.
1398 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1399 (scalar_to_vector (loadf64 addr:$src2)))),
1400 (MOVHPDrm VR128:$src1, addr:$src2)>;
1403 //===----------------------------------------------------------------------===//
1404 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1405 //===----------------------------------------------------------------------===//
1407 let AddedComplexity = 20, Predicates = [UseAVX] in {
1408 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1409 (ins VR128:$src1, VR128:$src2),
1410 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1412 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1414 VEX_4V, Sched<[WriteFShuffle]>;
1415 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1416 (ins VR128:$src1, VR128:$src2),
1417 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1419 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1421 VEX_4V, Sched<[WriteFShuffle]>;
1423 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1424 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1425 (ins VR128:$src1, VR128:$src2),
1426 "movlhps\t{$src2, $dst|$dst, $src2}",
1428 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1429 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1430 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1431 (ins VR128:$src1, VR128:$src2),
1432 "movhlps\t{$src2, $dst|$dst, $src2}",
1434 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1435 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1438 let Predicates = [UseAVX] in {
1440 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1441 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1442 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1443 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1446 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1447 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1450 let Predicates = [UseSSE1] in {
1452 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1453 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1454 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1455 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1458 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1459 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1462 //===----------------------------------------------------------------------===//
1463 // SSE 1 & 2 - Conversion Instructions
1464 //===----------------------------------------------------------------------===//
1466 def SSE_CVT_PD : OpndItins<
1467 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1470 let Sched = WriteCvtI2F in
1471 def SSE_CVT_PS : OpndItins<
1472 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1475 let Sched = WriteCvtI2F in
1476 def SSE_CVT_Scalar : OpndItins<
1477 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1480 let Sched = WriteCvtF2I in
1481 def SSE_CVT_SS2SI_32 : OpndItins<
1482 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1485 let Sched = WriteCvtF2I in
1486 def SSE_CVT_SS2SI_64 : OpndItins<
1487 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1490 let Sched = WriteCvtF2I in
1491 def SSE_CVT_SD2SI : OpndItins<
1492 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1495 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1496 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1497 string asm, OpndItins itins> {
1498 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1499 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1500 itins.rr>, Sched<[itins.Sched]>;
1501 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1502 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1503 itins.rm>, Sched<[itins.Sched.Folded]>;
1506 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1507 X86MemOperand x86memop, string asm, Domain d,
1509 let neverHasSideEffects = 1 in {
1510 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1511 [], itins.rr, d>, Sched<[itins.Sched]>;
1513 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1514 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1518 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1519 X86MemOperand x86memop, string asm> {
1520 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1521 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1522 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1523 Sched<[WriteCvtI2F]>;
1525 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1526 (ins DstRC:$src1, x86memop:$src),
1527 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1528 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1529 } // neverHasSideEffects = 1
1532 let Predicates = [UseAVX] in {
1533 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1534 "cvttss2si\t{$src, $dst|$dst, $src}",
1537 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1538 "cvttss2si\t{$src, $dst|$dst, $src}",
1540 XS, VEX, VEX_W, VEX_LIG;
1541 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1542 "cvttsd2si\t{$src, $dst|$dst, $src}",
1545 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1546 "cvttsd2si\t{$src, $dst|$dst, $src}",
1548 XD, VEX, VEX_W, VEX_LIG;
1550 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1551 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1552 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1553 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1554 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1555 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1556 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1557 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1558 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1559 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1560 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1561 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1562 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1563 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1564 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1565 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1567 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1568 // register, but the same isn't true when only using memory operands,
1569 // provide other assembly "l" and "q" forms to address this explicitly
1570 // where appropriate to do so.
1571 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1572 XS, VEX_4V, VEX_LIG;
1573 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1574 XS, VEX_4V, VEX_W, VEX_LIG;
1575 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1576 XD, VEX_4V, VEX_LIG;
1577 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1578 XD, VEX_4V, VEX_W, VEX_LIG;
1580 let Predicates = [UseAVX] in {
1581 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1582 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1583 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1584 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1586 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1587 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1588 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1589 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1590 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1591 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1592 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1593 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1595 def : Pat<(f32 (sint_to_fp GR32:$src)),
1596 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1597 def : Pat<(f32 (sint_to_fp GR64:$src)),
1598 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1599 def : Pat<(f64 (sint_to_fp GR32:$src)),
1600 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1601 def : Pat<(f64 (sint_to_fp GR64:$src)),
1602 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1605 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1606 "cvttss2si\t{$src, $dst|$dst, $src}",
1607 SSE_CVT_SS2SI_32>, XS;
1608 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1609 "cvttss2si\t{$src, $dst|$dst, $src}",
1610 SSE_CVT_SS2SI_64>, XS, REX_W;
1611 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1612 "cvttsd2si\t{$src, $dst|$dst, $src}",
1614 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1615 "cvttsd2si\t{$src, $dst|$dst, $src}",
1616 SSE_CVT_SD2SI>, XD, REX_W;
1617 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1618 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1619 SSE_CVT_Scalar>, XS;
1620 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1621 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1622 SSE_CVT_Scalar>, XS, REX_W;
1623 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1624 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1625 SSE_CVT_Scalar>, XD;
1626 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1627 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1628 SSE_CVT_Scalar>, XD, REX_W;
1630 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1631 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1632 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1633 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1634 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1635 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1636 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1637 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1638 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1639 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1640 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1641 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1642 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1643 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1644 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1645 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1647 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1648 (CVTSI2SSrm FR64:$dst, i32mem:$src), 0>;
1649 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1650 (CVTSI2SDrm FR64:$dst, i32mem:$src), 0>;
1652 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1653 // and/or XMM operand(s).
1655 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1656 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1657 string asm, OpndItins itins> {
1658 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1659 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1660 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1661 Sched<[itins.Sched]>;
1662 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1663 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1664 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1665 Sched<[itins.Sched.Folded]>;
1668 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1669 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1670 PatFrag ld_frag, string asm, OpndItins itins,
1672 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1674 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1675 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1676 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1677 itins.rr>, Sched<[itins.Sched]>;
1678 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1679 (ins DstRC:$src1, x86memop:$src2),
1681 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1682 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1683 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1684 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1687 let Predicates = [UseAVX] in {
1688 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1689 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1690 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1691 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1692 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1693 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1695 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1696 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1697 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1698 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1701 let isCodeGenOnly = 1 in {
1702 let Predicates = [UseAVX] in {
1703 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1704 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1705 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1706 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1707 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1708 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1710 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1711 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1712 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1713 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1714 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1715 SSE_CVT_Scalar, 0>, XD,
1718 let Constraints = "$src1 = $dst" in {
1719 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1720 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1721 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1722 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1723 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1724 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1725 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1726 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1727 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1728 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1729 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1730 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1732 } // isCodeGenOnly = 1
1736 // Aliases for intrinsics
1737 let isCodeGenOnly = 1 in {
1738 let Predicates = [UseAVX] in {
1739 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1740 ssmem, sse_load_f32, "cvttss2si",
1741 SSE_CVT_SS2SI_32>, XS, VEX;
1742 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1743 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1744 "cvttss2si", SSE_CVT_SS2SI_64>,
1746 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1747 sdmem, sse_load_f64, "cvttsd2si",
1748 SSE_CVT_SD2SI>, XD, VEX;
1749 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1750 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1751 "cvttsd2si", SSE_CVT_SD2SI>,
1754 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1755 ssmem, sse_load_f32, "cvttss2si",
1756 SSE_CVT_SS2SI_32>, XS;
1757 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1758 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1759 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1760 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1761 sdmem, sse_load_f64, "cvttsd2si",
1763 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1764 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1765 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1766 } // isCodeGenOnly = 1
1768 let Predicates = [UseAVX] in {
1769 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1770 ssmem, sse_load_f32, "cvtss2si",
1771 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1772 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1773 ssmem, sse_load_f32, "cvtss2si",
1774 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1776 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1777 ssmem, sse_load_f32, "cvtss2si",
1778 SSE_CVT_SS2SI_32>, XS;
1779 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1780 ssmem, sse_load_f32, "cvtss2si",
1781 SSE_CVT_SS2SI_64>, XS, REX_W;
1783 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1784 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1785 SSEPackedSingle, SSE_CVT_PS>,
1786 PS, VEX, Requires<[HasAVX]>;
1787 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1788 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1789 SSEPackedSingle, SSE_CVT_PS>,
1790 PS, VEX, VEX_L, Requires<[HasAVX]>;
1792 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1793 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1794 SSEPackedSingle, SSE_CVT_PS>,
1795 PS, Requires<[UseSSE2]>;
1797 let Predicates = [UseAVX] in {
1798 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1799 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1800 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1801 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1802 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1803 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1804 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1805 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1806 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1807 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1808 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1809 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1810 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1811 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1812 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1813 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1816 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1817 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1818 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1819 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1820 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1821 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1822 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1823 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1824 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1825 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1826 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1827 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1828 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1829 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1830 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1831 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1835 // Convert scalar double to scalar single
1836 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1837 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1838 (ins FR64:$src1, FR64:$src2),
1839 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1840 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1841 Sched<[WriteCvtF2F]>;
1843 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1844 (ins FR64:$src1, f64mem:$src2),
1845 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1846 [], IIC_SSE_CVT_Scalar_RM>,
1847 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1848 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1851 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1854 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1855 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1856 [(set FR32:$dst, (fround FR64:$src))],
1857 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1858 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1859 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1860 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1861 IIC_SSE_CVT_Scalar_RM>,
1863 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1865 let isCodeGenOnly = 1 in {
1866 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1867 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1868 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1870 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1871 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[UseAVX]>,
1872 Sched<[WriteCvtF2F]>;
1873 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1874 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1875 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1876 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1877 VR128:$src1, sse_load_f64:$src2))],
1878 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[UseAVX]>,
1879 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1881 let Constraints = "$src1 = $dst" in {
1882 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1883 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1884 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1886 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1887 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1888 Sched<[WriteCvtF2F]>;
1889 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1890 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1891 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1892 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1893 VR128:$src1, sse_load_f64:$src2))],
1894 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1895 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1897 } // isCodeGenOnly = 1
1899 // Convert scalar single to scalar double
1900 // SSE2 instructions with XS prefix
1901 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1902 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1903 (ins FR32:$src1, FR32:$src2),
1904 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1905 [], IIC_SSE_CVT_Scalar_RR>,
1906 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1907 Sched<[WriteCvtF2F]>;
1909 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1910 (ins FR32:$src1, f32mem:$src2),
1911 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1912 [], IIC_SSE_CVT_Scalar_RM>,
1913 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1914 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1917 def : Pat<(f64 (fextend FR32:$src)),
1918 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1919 def : Pat<(fextend (loadf32 addr:$src)),
1920 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1922 def : Pat<(extloadf32 addr:$src),
1923 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1924 Requires<[UseAVX, OptForSize]>;
1925 def : Pat<(extloadf32 addr:$src),
1926 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1927 Requires<[UseAVX, OptForSpeed]>;
1929 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1930 "cvtss2sd\t{$src, $dst|$dst, $src}",
1931 [(set FR64:$dst, (fextend FR32:$src))],
1932 IIC_SSE_CVT_Scalar_RR>, XS,
1933 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1934 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1935 "cvtss2sd\t{$src, $dst|$dst, $src}",
1936 [(set FR64:$dst, (extloadf32 addr:$src))],
1937 IIC_SSE_CVT_Scalar_RM>, XS,
1938 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1940 // extload f32 -> f64. This matches load+fextend because we have a hack in
1941 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1943 // Since these loads aren't folded into the fextend, we have to match it
1945 def : Pat<(fextend (loadf32 addr:$src)),
1946 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1947 def : Pat<(extloadf32 addr:$src),
1948 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1950 let isCodeGenOnly = 1 in {
1951 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1952 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1953 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1955 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1956 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[UseAVX]>,
1957 Sched<[WriteCvtF2F]>;
1958 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1959 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1960 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1962 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1963 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[UseAVX]>,
1964 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1965 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1966 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1967 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1968 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1970 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1971 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1972 Sched<[WriteCvtF2F]>;
1973 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1974 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1975 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1977 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1978 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1979 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1981 } // isCodeGenOnly = 1
1983 // Convert packed single/double fp to doubleword
1984 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1985 "cvtps2dq\t{$src, $dst|$dst, $src}",
1986 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1987 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1988 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1989 "cvtps2dq\t{$src, $dst|$dst, $src}",
1991 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1992 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1993 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1994 "cvtps2dq\t{$src, $dst|$dst, $src}",
1996 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1997 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1998 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1999 "cvtps2dq\t{$src, $dst|$dst, $src}",
2001 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
2002 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2003 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2004 "cvtps2dq\t{$src, $dst|$dst, $src}",
2005 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
2006 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2007 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2008 "cvtps2dq\t{$src, $dst|$dst, $src}",
2010 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
2011 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2014 // Convert Packed Double FP to Packed DW Integers
2015 let Predicates = [HasAVX] in {
2016 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2017 // register, but the same isn't true when using memory operands instead.
2018 // Provide other assembly rr and rm forms to address this explicitly.
2019 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2020 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
2021 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
2022 VEX, Sched<[WriteCvtF2I]>;
2025 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2026 (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>;
2027 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2028 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2030 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
2031 Sched<[WriteCvtF2ILd]>;
2034 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2035 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2037 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
2038 Sched<[WriteCvtF2I]>;
2039 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2040 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2042 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
2043 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2044 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
2045 (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2048 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2049 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2051 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
2052 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
2053 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2054 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2055 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
2056 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2058 // Convert with truncation packed single/double fp to doubleword
2059 // SSE2 packed instructions with XS prefix
2060 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2061 "cvttps2dq\t{$src, $dst|$dst, $src}",
2063 (int_x86_sse2_cvttps2dq VR128:$src))],
2064 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2065 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2066 "cvttps2dq\t{$src, $dst|$dst, $src}",
2067 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2068 (loadv4f32 addr:$src)))],
2069 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2070 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2071 "cvttps2dq\t{$src, $dst|$dst, $src}",
2073 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2074 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2075 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2076 "cvttps2dq\t{$src, $dst|$dst, $src}",
2077 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2078 (loadv8f32 addr:$src)))],
2079 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2080 Sched<[WriteCvtF2ILd]>;
2082 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2083 "cvttps2dq\t{$src, $dst|$dst, $src}",
2084 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2085 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2086 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2087 "cvttps2dq\t{$src, $dst|$dst, $src}",
2089 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2090 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2092 let Predicates = [HasAVX] in {
2093 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2094 (VCVTDQ2PSrr VR128:$src)>;
2095 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2096 (VCVTDQ2PSrm addr:$src)>;
2098 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2099 (VCVTDQ2PSrr VR128:$src)>;
2100 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2101 (VCVTDQ2PSrm addr:$src)>;
2103 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2104 (VCVTTPS2DQrr VR128:$src)>;
2105 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2106 (VCVTTPS2DQrm addr:$src)>;
2108 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2109 (VCVTDQ2PSYrr VR256:$src)>;
2110 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2111 (VCVTDQ2PSYrm addr:$src)>;
2113 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2114 (VCVTTPS2DQYrr VR256:$src)>;
2115 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2116 (VCVTTPS2DQYrm addr:$src)>;
2119 let Predicates = [UseSSE2] in {
2120 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2121 (CVTDQ2PSrr VR128:$src)>;
2122 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2123 (CVTDQ2PSrm addr:$src)>;
2125 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2126 (CVTDQ2PSrr VR128:$src)>;
2127 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2128 (CVTDQ2PSrm addr:$src)>;
2130 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2131 (CVTTPS2DQrr VR128:$src)>;
2132 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2133 (CVTTPS2DQrm addr:$src)>;
2136 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2137 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2139 (int_x86_sse2_cvttpd2dq VR128:$src))],
2140 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2142 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2143 // register, but the same isn't true when using memory operands instead.
2144 // Provide other assembly rr and rm forms to address this explicitly.
2147 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2148 (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>;
2149 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2150 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2151 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2152 (loadv2f64 addr:$src)))],
2153 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2156 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2157 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2159 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2160 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2161 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2162 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2164 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2165 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2166 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2167 (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2169 let Predicates = [HasAVX] in {
2170 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2171 (VCVTTPD2DQYrr VR256:$src)>;
2172 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2173 (VCVTTPD2DQYrm addr:$src)>;
2174 } // Predicates = [HasAVX]
2176 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2177 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2178 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2179 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2180 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2181 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2182 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2183 (memopv2f64 addr:$src)))],
2185 Sched<[WriteCvtF2ILd]>;
2187 // Convert packed single to packed double
2188 let Predicates = [HasAVX] in {
2189 // SSE2 instructions without OpSize prefix
2190 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2191 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2192 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2193 IIC_SSE_CVT_PD_RR>, PS, VEX, Sched<[WriteCvtF2F]>;
2194 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2195 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2196 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2197 IIC_SSE_CVT_PD_RM>, PS, VEX, Sched<[WriteCvtF2FLd]>;
2198 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2199 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2201 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2202 IIC_SSE_CVT_PD_RR>, PS, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2203 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2204 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2206 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2207 IIC_SSE_CVT_PD_RM>, PS, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2210 let Predicates = [UseSSE2] in {
2211 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2212 "cvtps2pd\t{$src, $dst|$dst, $src}",
2213 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2214 IIC_SSE_CVT_PD_RR>, PS, Sched<[WriteCvtF2F]>;
2215 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2216 "cvtps2pd\t{$src, $dst|$dst, $src}",
2217 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2218 IIC_SSE_CVT_PD_RM>, PS, Sched<[WriteCvtF2FLd]>;
2221 // Convert Packed DW Integers to Packed Double FP
2222 let Predicates = [HasAVX] in {
2223 let neverHasSideEffects = 1, mayLoad = 1 in
2224 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2225 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2226 []>, VEX, Sched<[WriteCvtI2FLd]>;
2227 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2228 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2230 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2231 Sched<[WriteCvtI2F]>;
2232 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2233 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2235 (int_x86_avx_cvtdq2_pd_256
2236 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2237 Sched<[WriteCvtI2FLd]>;
2238 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2239 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2241 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2242 Sched<[WriteCvtI2F]>;
2245 let neverHasSideEffects = 1, mayLoad = 1 in
2246 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2247 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2248 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2249 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2250 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2251 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2252 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2254 // AVX 256-bit register conversion intrinsics
2255 let Predicates = [HasAVX] in {
2256 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2257 (VCVTDQ2PDYrr VR128:$src)>;
2258 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2259 (VCVTDQ2PDYrm addr:$src)>;
2260 } // Predicates = [HasAVX]
2262 // Convert packed double to packed single
2263 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2264 // register, but the same isn't true when using memory operands instead.
2265 // Provide other assembly rr and rm forms to address this explicitly.
2266 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2267 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2268 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2269 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2272 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2273 (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>;
2274 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2275 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2277 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2278 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2281 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2282 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2284 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2285 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2286 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2287 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2289 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2290 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2291 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2292 (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>;
2294 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2295 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2296 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2297 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2298 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2299 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2301 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2302 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2305 // AVX 256-bit register conversion intrinsics
2306 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2307 // whenever possible to avoid declaring two versions of each one.
2308 let Predicates = [HasAVX] in {
2309 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2310 (VCVTDQ2PSYrr VR256:$src)>;
2311 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2312 (VCVTDQ2PSYrm addr:$src)>;
2314 // Match fround and fextend for 128/256-bit conversions
2315 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2316 (VCVTPD2PSrr VR128:$src)>;
2317 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2318 (VCVTPD2PSXrm addr:$src)>;
2319 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2320 (VCVTPD2PSYrr VR256:$src)>;
2321 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2322 (VCVTPD2PSYrm addr:$src)>;
2324 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2325 (VCVTPS2PDrr VR128:$src)>;
2326 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2327 (VCVTPS2PDYrr VR128:$src)>;
2328 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2329 (VCVTPS2PDYrm addr:$src)>;
2332 let Predicates = [UseSSE2] in {
2333 // Match fround and fextend for 128 conversions
2334 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2335 (CVTPD2PSrr VR128:$src)>;
2336 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2337 (CVTPD2PSrm addr:$src)>;
2339 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2340 (CVTPS2PDrr VR128:$src)>;
2343 //===----------------------------------------------------------------------===//
2344 // SSE 1 & 2 - Compare Instructions
2345 //===----------------------------------------------------------------------===//
2347 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2348 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2349 Operand CC, SDNode OpNode, ValueType VT,
2350 PatFrag ld_frag, string asm, string asm_alt,
2352 def rr : SIi8<0xC2, MRMSrcReg,
2353 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2354 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2355 itins.rr>, Sched<[itins.Sched]>;
2356 def rm : SIi8<0xC2, MRMSrcMem,
2357 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2358 [(set RC:$dst, (OpNode (VT RC:$src1),
2359 (ld_frag addr:$src2), imm:$cc))],
2361 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2363 // Accept explicit immediate argument form instead of comparison code.
2364 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2365 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2366 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2367 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2369 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2370 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2371 IIC_SSE_ALU_F32S_RM>,
2372 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2376 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2377 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2378 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2380 XS, VEX_4V, VEX_LIG;
2381 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2382 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2383 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2384 SSE_ALU_F32S>, // same latency as 32 bit compare
2385 XD, VEX_4V, VEX_LIG;
2387 let Constraints = "$src1 = $dst" in {
2388 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2389 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2390 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2392 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2393 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2394 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2399 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2400 Intrinsic Int, string asm, OpndItins itins> {
2401 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2402 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2403 [(set VR128:$dst, (Int VR128:$src1,
2404 VR128:$src, imm:$cc))],
2406 Sched<[itins.Sched]>;
2407 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2408 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2409 [(set VR128:$dst, (Int VR128:$src1,
2410 (load addr:$src), imm:$cc))],
2412 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2415 let isCodeGenOnly = 1 in {
2416 // Aliases to match intrinsics which expect XMM operand(s).
2417 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2418 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2421 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2422 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2423 SSE_ALU_F32S>, // same latency as f32
2425 let Constraints = "$src1 = $dst" in {
2426 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2427 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2429 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2430 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2437 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2438 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2439 ValueType vt, X86MemOperand x86memop,
2440 PatFrag ld_frag, string OpcodeStr> {
2441 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2442 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2443 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2446 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2447 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2448 [(set EFLAGS, (OpNode (vt RC:$src1),
2449 (ld_frag addr:$src2)))],
2451 Sched<[WriteFAddLd, ReadAfterLd]>;
2454 let Defs = [EFLAGS] in {
2455 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2456 "ucomiss">, PS, VEX, VEX_LIG;
2457 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2458 "ucomisd">, PD, VEX, VEX_LIG;
2459 let Pattern = []<dag> in {
2460 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2461 "comiss">, PS, VEX, VEX_LIG;
2462 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2463 "comisd">, PD, VEX, VEX_LIG;
2466 let isCodeGenOnly = 1 in {
2467 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2468 load, "ucomiss">, PS, VEX;
2469 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2470 load, "ucomisd">, PD, VEX;
2472 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2473 load, "comiss">, PS, VEX;
2474 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2475 load, "comisd">, PD, VEX;
2477 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2479 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2482 let Pattern = []<dag> in {
2483 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2485 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2489 let isCodeGenOnly = 1 in {
2490 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2491 load, "ucomiss">, PS;
2492 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2493 load, "ucomisd">, PD;
2495 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2497 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2500 } // Defs = [EFLAGS]
2502 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2503 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2504 Operand CC, Intrinsic Int, string asm,
2505 string asm_alt, Domain d,
2506 OpndItins itins = SSE_ALU_F32P> {
2507 def rri : PIi8<0xC2, MRMSrcReg,
2508 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2509 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2512 def rmi : PIi8<0xC2, MRMSrcMem,
2513 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2514 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2516 Sched<[WriteFAddLd, ReadAfterLd]>;
2518 // Accept explicit immediate argument form instead of comparison code.
2519 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2520 def rri_alt : PIi8<0xC2, MRMSrcReg,
2521 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2522 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2523 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2524 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2525 asm_alt, [], itins.rm, d>,
2526 Sched<[WriteFAddLd, ReadAfterLd]>;
2530 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2531 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2532 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2533 SSEPackedSingle>, PS, VEX_4V;
2534 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2535 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2536 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2537 SSEPackedDouble>, PD, VEX_4V;
2538 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2539 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2540 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2541 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2542 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2543 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2544 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2545 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2546 let Constraints = "$src1 = $dst" in {
2547 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2548 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2549 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2550 SSEPackedSingle, SSE_ALU_F32P>, PS;
2551 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2552 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2553 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2554 SSEPackedDouble, SSE_ALU_F64P>, PD;
2557 let Predicates = [HasAVX] in {
2558 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2559 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2560 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2561 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2562 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2563 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2564 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2565 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2567 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2568 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2569 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2570 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2571 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2572 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2573 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2574 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2577 let Predicates = [UseSSE1] in {
2578 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2579 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2580 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2581 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2584 let Predicates = [UseSSE2] in {
2585 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2586 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2587 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2588 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2591 //===----------------------------------------------------------------------===//
2592 // SSE 1 & 2 - Shuffle Instructions
2593 //===----------------------------------------------------------------------===//
2595 /// sse12_shuffle - sse 1 & 2 fp shuffle instructions
2596 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2597 ValueType vt, string asm, PatFrag mem_frag,
2598 Domain d, bit IsConvertibleToThreeAddress = 0> {
2599 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2600 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2601 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2602 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2603 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2604 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2605 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2606 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2607 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2608 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2609 Sched<[WriteFShuffle]>;
2612 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2613 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2614 loadv4f32, SSEPackedSingle>, PS, VEX_4V;
2615 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2616 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2617 loadv8f32, SSEPackedSingle>, PS, VEX_4V, VEX_L;
2618 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2619 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2620 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
2621 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2622 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2623 loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L;
2625 let Constraints = "$src1 = $dst" in {
2626 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2627 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2628 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>, PS;
2629 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2630 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2631 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>, PD;
2634 let Predicates = [HasAVX] in {
2635 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2636 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2637 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2638 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2639 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2641 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2642 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2643 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2644 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2645 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2648 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2649 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2650 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2651 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2652 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2654 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2655 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2656 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2657 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2658 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2661 let Predicates = [UseSSE1] in {
2662 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2663 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2664 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2665 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2666 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2669 let Predicates = [UseSSE2] in {
2670 // Generic SHUFPD patterns
2671 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2672 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2673 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2674 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2675 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2678 //===----------------------------------------------------------------------===//
2679 // SSE 1 & 2 - Unpack FP Instructions
2680 //===----------------------------------------------------------------------===//
2682 /// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave
2683 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2684 PatFrag mem_frag, RegisterClass RC,
2685 X86MemOperand x86memop, string asm,
2687 def rr : PI<opc, MRMSrcReg,
2688 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2690 (vt (OpNode RC:$src1, RC:$src2)))],
2691 IIC_SSE_UNPCK, d>, Sched<[WriteFShuffle]>;
2692 def rm : PI<opc, MRMSrcMem,
2693 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2695 (vt (OpNode RC:$src1,
2696 (mem_frag addr:$src2))))],
2698 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2701 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2702 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2703 SSEPackedSingle>, PS, VEX_4V;
2704 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2705 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2706 SSEPackedDouble>, PD, VEX_4V;
2707 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2708 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2709 SSEPackedSingle>, PS, VEX_4V;
2710 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2711 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2712 SSEPackedDouble>, PD, VEX_4V;
2714 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2715 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2716 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2717 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2718 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2719 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2720 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2721 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2722 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2723 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2724 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2725 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2727 let Constraints = "$src1 = $dst" in {
2728 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2729 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2730 SSEPackedSingle>, PS;
2731 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2732 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2733 SSEPackedDouble>, PD;
2734 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2735 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2736 SSEPackedSingle>, PS;
2737 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2738 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2739 SSEPackedDouble>, PD;
2740 } // Constraints = "$src1 = $dst"
2742 let Predicates = [HasAVX1Only] in {
2743 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2744 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2745 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2746 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2747 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2748 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2749 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2750 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2752 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2753 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2754 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2755 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2756 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2757 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2758 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2759 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2762 let Predicates = [HasAVX] in {
2763 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2764 // problem is during lowering, where it's not possible to recognize the load
2765 // fold cause it has two uses through a bitcast. One use disappears at isel
2766 // time and the fold opportunity reappears.
2767 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2768 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2771 let Predicates = [UseSSE2] in {
2772 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2773 // problem is during lowering, where it's not possible to recognize the load
2774 // fold cause it has two uses through a bitcast. One use disappears at isel
2775 // time and the fold opportunity reappears.
2776 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2777 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2780 //===----------------------------------------------------------------------===//
2781 // SSE 1 & 2 - Extract Floating-Point Sign mask
2782 //===----------------------------------------------------------------------===//
2784 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2785 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2787 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2788 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2789 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2790 Sched<[WriteVecLogic]>;
2793 let Predicates = [HasAVX] in {
2794 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2795 "movmskps", SSEPackedSingle>, PS, VEX;
2796 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2797 "movmskpd", SSEPackedDouble>, PD, VEX;
2798 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2799 "movmskps", SSEPackedSingle>, PS,
2801 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2802 "movmskpd", SSEPackedDouble>, PD,
2805 def : Pat<(i32 (X86fgetsign FR32:$src)),
2806 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2807 def : Pat<(i64 (X86fgetsign FR32:$src)),
2808 (SUBREG_TO_REG (i64 0),
2809 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2810 def : Pat<(i32 (X86fgetsign FR64:$src)),
2811 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2812 def : Pat<(i64 (X86fgetsign FR64:$src)),
2813 (SUBREG_TO_REG (i64 0),
2814 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2817 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2818 SSEPackedSingle>, PS;
2819 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2820 SSEPackedDouble>, PD;
2822 def : Pat<(i32 (X86fgetsign FR32:$src)),
2823 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2824 Requires<[UseSSE1]>;
2825 def : Pat<(i64 (X86fgetsign FR32:$src)),
2826 (SUBREG_TO_REG (i64 0),
2827 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2828 Requires<[UseSSE1]>;
2829 def : Pat<(i32 (X86fgetsign FR64:$src)),
2830 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2831 Requires<[UseSSE2]>;
2832 def : Pat<(i64 (X86fgetsign FR64:$src)),
2833 (SUBREG_TO_REG (i64 0),
2834 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2835 Requires<[UseSSE2]>;
2837 //===---------------------------------------------------------------------===//
2838 // SSE2 - Packed Integer Logical Instructions
2839 //===---------------------------------------------------------------------===//
2841 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2843 /// PDI_binop_rm - Simple SSE2 binary operator.
2844 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2845 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2846 X86MemOperand x86memop, OpndItins itins,
2847 bit IsCommutable, bit Is2Addr> {
2848 let isCommutable = IsCommutable in
2849 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2850 (ins RC:$src1, RC:$src2),
2852 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2853 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2854 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2855 Sched<[itins.Sched]>;
2856 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2857 (ins RC:$src1, x86memop:$src2),
2859 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2860 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2861 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2862 (bitconvert (memop_frag addr:$src2)))))],
2864 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2866 } // ExeDomain = SSEPackedInt
2868 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2869 ValueType OpVT128, ValueType OpVT256,
2870 OpndItins itins, bit IsCommutable = 0> {
2871 let Predicates = [HasAVX] in
2872 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2873 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2875 let Constraints = "$src1 = $dst" in
2876 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2877 memopv2i64, i128mem, itins, IsCommutable, 1>;
2879 let Predicates = [HasAVX2] in
2880 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2881 OpVT256, VR256, loadv4i64, i256mem, itins,
2882 IsCommutable, 0>, VEX_4V, VEX_L;
2885 // These are ordered here for pattern ordering requirements with the fp versions
2887 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64,
2888 SSE_VEC_BIT_ITINS_P, 1>;
2889 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64,
2890 SSE_VEC_BIT_ITINS_P, 1>;
2891 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64,
2892 SSE_VEC_BIT_ITINS_P, 1>;
2893 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2894 SSE_VEC_BIT_ITINS_P, 0>;
2896 //===----------------------------------------------------------------------===//
2897 // SSE 1 & 2 - Logical Instructions
2898 //===----------------------------------------------------------------------===//
2900 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2902 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2903 SDNode OpNode, OpndItins itins> {
2904 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2905 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2908 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2909 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2912 let Constraints = "$src1 = $dst" in {
2913 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2914 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2917 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2918 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2923 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2924 let isCodeGenOnly = 1 in {
2925 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2927 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2929 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2932 let isCommutable = 0 in
2933 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", X86fandn,
2937 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2939 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2941 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2942 !strconcat(OpcodeStr, "ps"), f256mem,
2943 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2944 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2945 (loadv4i64 addr:$src2)))], 0>, PS, VEX_4V, VEX_L;
2947 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2948 !strconcat(OpcodeStr, "pd"), f256mem,
2949 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2950 (bc_v4i64 (v4f64 VR256:$src2))))],
2951 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2952 (loadv4i64 addr:$src2)))], 0>,
2955 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2956 // are all promoted to v2i64, and the patterns are covered by the int
2957 // version. This is needed in SSE only, because v2i64 isn't supported on
2958 // SSE1, but only on SSE2.
2959 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2960 !strconcat(OpcodeStr, "ps"), f128mem, [],
2961 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2962 (loadv2i64 addr:$src2)))], 0>, PS, VEX_4V;
2964 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2965 !strconcat(OpcodeStr, "pd"), f128mem,
2966 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2967 (bc_v2i64 (v2f64 VR128:$src2))))],
2968 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2969 (loadv2i64 addr:$src2)))], 0>,
2972 let Constraints = "$src1 = $dst" in {
2973 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2974 !strconcat(OpcodeStr, "ps"), f128mem,
2975 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2976 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2977 (memopv2i64 addr:$src2)))]>, PS;
2979 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2980 !strconcat(OpcodeStr, "pd"), f128mem,
2981 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2982 (bc_v2i64 (v2f64 VR128:$src2))))],
2983 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2984 (memopv2i64 addr:$src2)))]>, PD;
2988 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2989 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2990 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2991 let isCommutable = 0 in
2992 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2994 // AVX1 requires type coercions in order to fold loads directly into logical
2996 let Predicates = [HasAVX1Only] in {
2997 def : Pat<(bc_v8f32 (and VR256:$src1, (loadv4i64 addr:$src2))),
2998 (VANDPSYrm VR256:$src1, addr:$src2)>;
2999 def : Pat<(bc_v8f32 (or VR256:$src1, (loadv4i64 addr:$src2))),
3000 (VORPSYrm VR256:$src1, addr:$src2)>;
3001 def : Pat<(bc_v8f32 (xor VR256:$src1, (loadv4i64 addr:$src2))),
3002 (VXORPSYrm VR256:$src1, addr:$src2)>;
3003 def : Pat<(bc_v8f32 (X86andnp VR256:$src1, (loadv4i64 addr:$src2))),
3004 (VANDNPSYrm VR256:$src1, addr:$src2)>;
3007 //===----------------------------------------------------------------------===//
3008 // SSE 1 & 2 - Arithmetic Instructions
3009 //===----------------------------------------------------------------------===//
3011 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
3014 /// In addition, we also have a special variant of the scalar form here to
3015 /// represent the associated intrinsic operation. This form is unlike the
3016 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
3017 /// and leaves the top elements unmodified (therefore these cannot be commuted).
3019 /// These three forms can each be reg+reg or reg+mem.
3022 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
3024 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
3025 SDNode OpNode, SizeItins itins> {
3026 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
3027 VR128, v4f32, f128mem, loadv4f32,
3028 SSEPackedSingle, itins.s, 0>, PS, VEX_4V;
3029 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
3030 VR128, v2f64, f128mem, loadv2f64,
3031 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
3033 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
3034 OpNode, VR256, v8f32, f256mem, loadv8f32,
3035 SSEPackedSingle, itins.s, 0>, PS, VEX_4V, VEX_L;
3036 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
3037 OpNode, VR256, v4f64, f256mem, loadv4f64,
3038 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
3040 let Constraints = "$src1 = $dst" in {
3041 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
3042 v4f32, f128mem, memopv4f32, SSEPackedSingle,
3044 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
3045 v2f64, f128mem, memopv2f64, SSEPackedDouble,
3050 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3052 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3053 OpNode, FR32, f32mem, itins.s, 0>, XS, VEX_4V, VEX_LIG;
3054 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3055 OpNode, FR64, f64mem, itins.d, 0>, XD, VEX_4V, VEX_LIG;
3057 let Constraints = "$src1 = $dst" in {
3058 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3059 OpNode, FR32, f32mem, itins.s>, XS;
3060 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3061 OpNode, FR64, f64mem, itins.d>, XD;
3065 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
3067 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3068 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3069 itins.s, 0>, XS, VEX_4V, VEX_LIG;
3070 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3071 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3072 itins.d, 0>, XD, VEX_4V, VEX_LIG;
3074 let Constraints = "$src1 = $dst" in {
3075 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3076 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3078 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3079 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3084 // Binary Arithmetic instructions
3085 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3086 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3087 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3088 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3089 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3090 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3091 let isCommutable = 0 in {
3092 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3093 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3094 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3095 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3096 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3097 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3098 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3099 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3100 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3101 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3102 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3103 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3106 let isCodeGenOnly = 1 in {
3107 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3108 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3109 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3110 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3113 // Patterns used to select SSE scalar fp arithmetic instructions from
3114 // a scalar fp operation followed by a blend.
3116 // These patterns know, for example, how to select an ADDSS from a
3117 // float add plus vector insert.
3119 // The effect is that the backend no longer emits unnecessary vector
3120 // insert instructions immediately after SSE scalar fp instructions
3121 // like addss or mulss.
3123 // For example, given the following code:
3124 // __m128 foo(__m128 A, __m128 B) {
3129 // previously we generated:
3130 // addss %xmm0, %xmm1
3131 // movss %xmm1, %xmm0
3134 // addss %xmm1, %xmm0
3136 let Predicates = [UseSSE1] in {
3137 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3138 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3140 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3141 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3142 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3144 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3145 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3146 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3148 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3149 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3150 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3152 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3155 let Predicates = [UseSSE2] in {
3156 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3158 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3159 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3161 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3162 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3163 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3165 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3166 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3167 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3169 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3170 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3171 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3173 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3176 let Predicates = [UseSSE41] in {
3177 // If the subtarget has SSE4.1 but not AVX, the vector insert
3178 // instruction is lowered into a X86insertps rather than a X86Movss.
3179 // When selecting SSE scalar single-precision fp arithmetic instructions,
3180 // make sure that we correctly match the X86insertps.
3182 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3183 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3184 FR32:$src))), (iPTR 0))),
3185 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3186 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3187 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3188 FR32:$src))), (iPTR 0))),
3189 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3190 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3191 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3192 FR32:$src))), (iPTR 0))),
3193 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3194 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3195 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3196 FR32:$src))), (iPTR 0))),
3197 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3200 let Predicates = [HasAVX] in {
3201 // The following patterns select AVX Scalar single/double precision fp
3202 // arithmetic instructions.
3204 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3205 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3207 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3208 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3209 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3211 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3212 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3213 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3215 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3216 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3217 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3219 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3220 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3221 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3222 FR32:$src))), (iPTR 0))),
3223 (VADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3224 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3225 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3226 FR32:$src))), (iPTR 0))),
3227 (VSUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3228 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3229 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3230 FR32:$src))), (iPTR 0))),
3231 (VMULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3232 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3233 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3234 FR32:$src))), (iPTR 0))),
3235 (VDIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3238 // Patterns used to select SSE scalar fp arithmetic instructions from
3239 // a vector packed single/double fp operation followed by a vector insert.
3241 // The effect is that the backend converts the packed fp instruction
3242 // followed by a vector insert into a single SSE scalar fp instruction.
3244 // For example, given the following code:
3245 // __m128 foo(__m128 A, __m128 B) {
3246 // __m128 C = A + B;
3247 // return (__m128) {c[0], a[1], a[2], a[3]};
3250 // previously we generated:
3251 // addps %xmm0, %xmm1
3252 // movss %xmm1, %xmm0
3255 // addss %xmm1, %xmm0
3257 let Predicates = [UseSSE1] in {
3258 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3259 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3260 (ADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3261 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3262 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3263 (SUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3264 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3265 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3266 (MULSSrr_Int v4f32:$dst, v4f32:$src)>;
3267 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3268 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3269 (DIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3272 let Predicates = [UseSSE2] in {
3273 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3274 // from a packed double-precision fp instruction plus movsd.
3276 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3277 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3278 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3279 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3280 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3281 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3282 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3283 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3284 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3285 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3286 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3287 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3290 let Predicates = [HasAVX] in {
3291 // The following patterns select AVX Scalar single/double precision fp
3292 // arithmetic instructions from a packed single precision fp instruction
3293 // plus movss/movsd.
3295 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3296 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3297 (VADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3298 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3299 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3300 (VSUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3301 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3302 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3303 (VMULSSrr_Int v4f32:$dst, v4f32:$src)>;
3304 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3305 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3306 (VDIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3307 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3308 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3309 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3310 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3311 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3312 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3313 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3314 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3315 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3316 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3317 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3318 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3322 /// In addition, we also have a special variant of the scalar form here to
3323 /// represent the associated intrinsic operation. This form is unlike the
3324 /// plain scalar form, in that it takes an entire vector (instead of a
3325 /// scalar) and leaves the top elements undefined.
3327 /// And, we have a special variant form for a full-vector intrinsic form.
3329 let Sched = WriteFSqrt in {
3330 def SSE_SQRTPS : OpndItins<
3331 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3334 def SSE_SQRTSS : OpndItins<
3335 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3338 def SSE_SQRTPD : OpndItins<
3339 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3342 def SSE_SQRTSD : OpndItins<
3343 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3347 let Sched = WriteFRsqrt in {
3348 def SSE_RSQRTPS : OpndItins<
3349 IIC_SSE_RSQRTPS_RR, IIC_SSE_RSQRTPS_RM
3352 def SSE_RSQRTSS : OpndItins<
3353 IIC_SSE_RSQRTSS_RR, IIC_SSE_RSQRTSS_RM
3357 let Sched = WriteFRcp in {
3358 def SSE_RCPP : OpndItins<
3359 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3362 def SSE_RCPS : OpndItins<
3363 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3367 /// sse1_fp_unop_s - SSE1 unops in scalar form.
3368 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3369 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3370 let Predicates = [HasAVX], hasSideEffects = 0 in {
3371 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3372 (ins FR32:$src1, FR32:$src2),
3373 !strconcat("v", OpcodeStr,
3374 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3375 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3376 let mayLoad = 1 in {
3377 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3378 (ins FR32:$src1,f32mem:$src2),
3379 !strconcat("v", OpcodeStr,
3380 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3381 []>, VEX_4V, VEX_LIG,
3382 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3383 let isCodeGenOnly = 1 in
3384 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3385 (ins VR128:$src1, ssmem:$src2),
3386 !strconcat("v", OpcodeStr,
3387 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3388 []>, VEX_4V, VEX_LIG,
3389 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3393 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3394 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3395 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3396 // For scalar unary operations, fold a load into the operation
3397 // only in OptForSize mode. It eliminates an instruction, but it also
3398 // eliminates a whole-register clobber (the load), so it introduces a
3399 // partial register update condition.
3400 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3401 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3402 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3403 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3404 let isCodeGenOnly = 1 in {
3405 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3406 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3407 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>,
3408 Sched<[itins.Sched]>;
3409 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3410 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3411 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>,
3412 Sched<[itins.Sched.Folded]>;
3416 /// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.
3417 multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,
3419 let Predicates = [HasAVX], hasSideEffects = 0 in {
3420 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3421 (ins FR32:$src1, FR32:$src2),
3422 !strconcat("v", OpcodeStr,
3423 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3424 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3425 let mayLoad = 1 in {
3426 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3427 (ins FR32:$src1,f32mem:$src2),
3428 !strconcat("v", OpcodeStr,
3429 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3430 []>, VEX_4V, VEX_LIG,
3431 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3432 let isCodeGenOnly = 1 in
3433 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3434 (ins VR128:$src1, ssmem:$src2),
3435 !strconcat("v", OpcodeStr,
3436 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3437 []>, VEX_4V, VEX_LIG,
3438 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3442 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3443 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3444 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3445 // For scalar unary operations, fold a load into the operation
3446 // only in OptForSize mode. It eliminates an instruction, but it also
3447 // eliminates a whole-register clobber (the load), so it introduces a
3448 // partial register update condition.
3449 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3450 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3451 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3452 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3453 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3454 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3455 (ins VR128:$src1, VR128:$src2),
3456 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3457 [], itins.rr>, Sched<[itins.Sched]>;
3458 let mayLoad = 1, hasSideEffects = 0 in
3459 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3460 (ins VR128:$src1, ssmem:$src2),
3461 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3462 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3466 /// sse1_fp_unop_p - SSE1 unops in packed form.
3467 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3469 let Predicates = [HasAVX] in {
3470 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3471 !strconcat("v", OpcodeStr,
3472 "ps\t{$src, $dst|$dst, $src}"),
3473 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3474 itins.rr>, VEX, Sched<[itins.Sched]>;
3475 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3476 !strconcat("v", OpcodeStr,
3477 "ps\t{$src, $dst|$dst, $src}"),
3478 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3479 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3480 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3481 !strconcat("v", OpcodeStr,
3482 "ps\t{$src, $dst|$dst, $src}"),
3483 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3484 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3485 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3486 !strconcat("v", OpcodeStr,
3487 "ps\t{$src, $dst|$dst, $src}"),
3488 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3489 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3492 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3493 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3494 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3495 Sched<[itins.Sched]>;
3496 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3497 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3498 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3499 Sched<[itins.Sched.Folded]>;
3502 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3503 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3504 Intrinsic V4F32Int, Intrinsic V8F32Int,
3506 let isCodeGenOnly = 1 in {
3507 let Predicates = [HasAVX] in {
3508 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3509 !strconcat("v", OpcodeStr,
3510 "ps\t{$src, $dst|$dst, $src}"),
3511 [(set VR128:$dst, (V4F32Int VR128:$src))],
3512 itins.rr>, VEX, Sched<[itins.Sched]>;
3513 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3514 !strconcat("v", OpcodeStr,
3515 "ps\t{$src, $dst|$dst, $src}"),
3516 [(set VR128:$dst, (V4F32Int (loadv4f32 addr:$src)))],
3517 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3518 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3519 !strconcat("v", OpcodeStr,
3520 "ps\t{$src, $dst|$dst, $src}"),
3521 [(set VR256:$dst, (V8F32Int VR256:$src))],
3522 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3523 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3525 !strconcat("v", OpcodeStr,
3526 "ps\t{$src, $dst|$dst, $src}"),
3527 [(set VR256:$dst, (V8F32Int (loadv8f32 addr:$src)))],
3528 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3531 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3532 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3533 [(set VR128:$dst, (V4F32Int VR128:$src))],
3534 itins.rr>, Sched<[itins.Sched]>;
3535 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3536 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3537 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3538 itins.rm>, Sched<[itins.Sched.Folded]>;
3539 } // isCodeGenOnly = 1
3542 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3543 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3544 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3545 let Predicates = [HasAVX], hasSideEffects = 0 in {
3546 def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),
3547 (ins FR64:$src1, FR64:$src2),
3548 !strconcat("v", OpcodeStr,
3549 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3550 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3551 let mayLoad = 1 in {
3552 def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
3553 (ins FR64:$src1,f64mem:$src2),
3554 !strconcat("v", OpcodeStr,
3555 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3556 []>, VEX_4V, VEX_LIG,
3557 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3558 let isCodeGenOnly = 1 in
3559 def V#NAME#SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3560 (ins VR128:$src1, sdmem:$src2),
3561 !strconcat("v", OpcodeStr,
3562 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3563 []>, VEX_4V, VEX_LIG,
3564 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3568 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3569 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3570 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>,
3571 Sched<[itins.Sched]>;
3572 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3573 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3574 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3575 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3576 Requires<[UseSSE2, OptForSize]>, Sched<[itins.Sched.Folded]>;
3577 let isCodeGenOnly = 1 in {
3578 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3579 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3580 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>,
3581 Sched<[itins.Sched]>;
3582 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3583 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3584 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>,
3585 Sched<[itins.Sched.Folded]>;
3589 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3590 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3591 SDNode OpNode, OpndItins itins> {
3592 let Predicates = [HasAVX] in {
3593 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3594 !strconcat("v", OpcodeStr,
3595 "pd\t{$src, $dst|$dst, $src}"),
3596 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3597 itins.rr>, VEX, Sched<[itins.Sched]>;
3598 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3599 !strconcat("v", OpcodeStr,
3600 "pd\t{$src, $dst|$dst, $src}"),
3601 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3602 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3603 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3604 !strconcat("v", OpcodeStr,
3605 "pd\t{$src, $dst|$dst, $src}"),
3606 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3607 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3608 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3609 !strconcat("v", OpcodeStr,
3610 "pd\t{$src, $dst|$dst, $src}"),
3611 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3612 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3615 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3616 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3617 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3618 Sched<[itins.Sched]>;
3619 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3620 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3621 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3622 Sched<[itins.Sched.Folded]>;
3626 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3628 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3629 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3631 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3633 // Reciprocal approximations. Note that these typically require refinement
3634 // in order to obtain suitable precision.
3635 defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_RSQRTSS>,
3636 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_RSQRTPS>,
3637 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3638 int_x86_avx_rsqrt_ps_256, SSE_RSQRTPS>;
3639 defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>,
3640 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3641 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3642 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3644 let Predicates = [UseAVX] in {
3645 def : Pat<(f32 (fsqrt FR32:$src)),
3646 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3647 def : Pat<(f32 (fsqrt (load addr:$src))),
3648 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3649 Requires<[HasAVX, OptForSize]>;
3650 def : Pat<(f64 (fsqrt FR64:$src)),
3651 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3652 def : Pat<(f64 (fsqrt (load addr:$src))),
3653 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3654 Requires<[HasAVX, OptForSize]>;
3656 def : Pat<(f32 (X86frsqrt FR32:$src)),
3657 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3658 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3659 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3660 Requires<[HasAVX, OptForSize]>;
3662 def : Pat<(f32 (X86frcp FR32:$src)),
3663 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3664 def : Pat<(f32 (X86frcp (load addr:$src))),
3665 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3666 Requires<[HasAVX, OptForSize]>;
3668 let Predicates = [UseAVX] in {
3669 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3670 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3671 (COPY_TO_REGCLASS VR128:$src, FR32)),
3673 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3674 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3676 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3677 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3678 (COPY_TO_REGCLASS VR128:$src, FR64)),
3680 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3681 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3684 let Predicates = [HasAVX] in {
3685 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3686 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3687 (COPY_TO_REGCLASS VR128:$src, FR32)),
3689 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3690 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3692 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3693 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3694 (COPY_TO_REGCLASS VR128:$src, FR32)),
3696 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3697 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3700 // Reciprocal approximations. Note that these typically require refinement
3701 // in order to obtain suitable precision.
3702 let Predicates = [UseSSE1] in {
3703 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3704 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3705 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3706 (RCPSSr_Int VR128:$src, VR128:$src)>;
3709 // There is no f64 version of the reciprocal approximation instructions.
3711 //===----------------------------------------------------------------------===//
3712 // SSE 1 & 2 - Non-temporal stores
3713 //===----------------------------------------------------------------------===//
3715 let AddedComplexity = 400 in { // Prefer non-temporal versions
3716 let SchedRW = [WriteStore] in {
3717 let Predicates = [HasAVX, NoVLX] in {
3718 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3719 (ins f128mem:$dst, VR128:$src),
3720 "movntps\t{$src, $dst|$dst, $src}",
3721 [(alignednontemporalstore (v4f32 VR128:$src),
3723 IIC_SSE_MOVNT>, VEX;
3724 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3725 (ins f128mem:$dst, VR128:$src),
3726 "movntpd\t{$src, $dst|$dst, $src}",
3727 [(alignednontemporalstore (v2f64 VR128:$src),
3729 IIC_SSE_MOVNT>, VEX;
3731 let ExeDomain = SSEPackedInt in
3732 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3733 (ins f128mem:$dst, VR128:$src),
3734 "movntdq\t{$src, $dst|$dst, $src}",
3735 [(alignednontemporalstore (v2i64 VR128:$src),
3737 IIC_SSE_MOVNT>, VEX;
3739 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3740 (ins f256mem:$dst, VR256:$src),
3741 "movntps\t{$src, $dst|$dst, $src}",
3742 [(alignednontemporalstore (v8f32 VR256:$src),
3744 IIC_SSE_MOVNT>, VEX, VEX_L;
3745 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3746 (ins f256mem:$dst, VR256:$src),
3747 "movntpd\t{$src, $dst|$dst, $src}",
3748 [(alignednontemporalstore (v4f64 VR256:$src),
3750 IIC_SSE_MOVNT>, VEX, VEX_L;
3751 let ExeDomain = SSEPackedInt in
3752 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3753 (ins f256mem:$dst, VR256:$src),
3754 "movntdq\t{$src, $dst|$dst, $src}",
3755 [(alignednontemporalstore (v4i64 VR256:$src),
3757 IIC_SSE_MOVNT>, VEX, VEX_L;
3760 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3761 "movntps\t{$src, $dst|$dst, $src}",
3762 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3764 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3765 "movntpd\t{$src, $dst|$dst, $src}",
3766 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3769 let ExeDomain = SSEPackedInt in
3770 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3771 "movntdq\t{$src, $dst|$dst, $src}",
3772 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3775 // There is no AVX form for instructions below this point
3776 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3777 "movnti{l}\t{$src, $dst|$dst, $src}",
3778 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3780 PS, Requires<[HasSSE2]>;
3781 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3782 "movnti{q}\t{$src, $dst|$dst, $src}",
3783 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3785 PS, Requires<[HasSSE2]>;
3786 } // SchedRW = [WriteStore]
3788 } // AddedComplexity
3790 //===----------------------------------------------------------------------===//
3791 // SSE 1 & 2 - Prefetch and memory fence
3792 //===----------------------------------------------------------------------===//
3794 // Prefetch intrinsic.
3795 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3796 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3797 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3798 IIC_SSE_PREFETCH>, TB;
3799 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3800 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3801 IIC_SSE_PREFETCH>, TB;
3802 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3803 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3804 IIC_SSE_PREFETCH>, TB;
3805 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3806 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3807 IIC_SSE_PREFETCH>, TB;
3810 // FIXME: How should flush instruction be modeled?
3811 let SchedRW = [WriteLoad] in {
3813 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3814 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3815 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3818 let SchedRW = [WriteNop] in {
3819 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3820 // was introduced with SSE2, it's backward compatible.
3821 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3822 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3823 OBXS, Requires<[HasSSE2]>;
3826 let SchedRW = [WriteFence] in {
3827 // Load, store, and memory fence
3828 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3829 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3830 TB, Requires<[HasSSE1]>;
3831 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3832 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3833 TB, Requires<[HasSSE2]>;
3834 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3835 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3836 TB, Requires<[HasSSE2]>;
3839 def : Pat<(X86SFence), (SFENCE)>;
3840 def : Pat<(X86LFence), (LFENCE)>;
3841 def : Pat<(X86MFence), (MFENCE)>;
3843 //===----------------------------------------------------------------------===//
3844 // SSE 1 & 2 - Load/Store XCSR register
3845 //===----------------------------------------------------------------------===//
3847 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3848 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3849 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3850 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3851 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3852 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3854 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3855 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3856 IIC_SSE_LDMXCSR>, Sched<[WriteLoad]>;
3857 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3858 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3859 IIC_SSE_STMXCSR>, Sched<[WriteStore]>;
3861 //===---------------------------------------------------------------------===//
3862 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3863 //===---------------------------------------------------------------------===//
3865 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3867 let neverHasSideEffects = 1, SchedRW = [WriteMove] in {
3868 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3869 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3871 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3872 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3874 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3875 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3877 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3878 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3883 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
3884 SchedRW = [WriteMove] in {
3885 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3886 "movdqa\t{$src, $dst|$dst, $src}", [],
3889 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3890 "movdqa\t{$src, $dst|$dst, $src}", [],
3891 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3892 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3893 "movdqu\t{$src, $dst|$dst, $src}", [],
3896 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3897 "movdqu\t{$src, $dst|$dst, $src}", [],
3898 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3901 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3902 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3903 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3904 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3906 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3907 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3909 let Predicates = [HasAVX] in {
3910 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3911 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3913 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3914 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3919 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3920 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3921 (ins i128mem:$dst, VR128:$src),
3922 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3924 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3925 (ins i256mem:$dst, VR256:$src),
3926 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3928 let Predicates = [HasAVX] in {
3929 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3930 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3932 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3933 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3938 let SchedRW = [WriteMove] in {
3939 let neverHasSideEffects = 1 in
3940 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3941 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3943 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3944 "movdqu\t{$src, $dst|$dst, $src}",
3945 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3948 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
3949 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3950 "movdqa\t{$src, $dst|$dst, $src}", [],
3953 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3954 "movdqu\t{$src, $dst|$dst, $src}",
3955 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3959 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3960 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3961 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3962 "movdqa\t{$src, $dst|$dst, $src}",
3963 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3965 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3966 "movdqu\t{$src, $dst|$dst, $src}",
3967 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3969 XS, Requires<[UseSSE2]>;
3972 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3973 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3974 "movdqa\t{$src, $dst|$dst, $src}",
3975 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3977 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3978 "movdqu\t{$src, $dst|$dst, $src}",
3979 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3981 XS, Requires<[UseSSE2]>;
3984 } // ExeDomain = SSEPackedInt
3986 let Predicates = [HasAVX] in {
3987 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3988 (VMOVDQUmr addr:$dst, VR128:$src)>;
3989 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3990 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3992 let Predicates = [UseSSE2] in
3993 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3994 (MOVDQUmr addr:$dst, VR128:$src)>;
3996 //===---------------------------------------------------------------------===//
3997 // SSE2 - Packed Integer Arithmetic Instructions
3998 //===---------------------------------------------------------------------===//
4000 let Sched = WriteVecIMul in
4001 def SSE_PMADD : OpndItins<
4002 IIC_SSE_PMADD, IIC_SSE_PMADD
4005 let ExeDomain = SSEPackedInt in { // SSE integer instructions
4007 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
4008 RegisterClass RC, PatFrag memop_frag,
4009 X86MemOperand x86memop,
4011 bit IsCommutable = 0,
4013 let isCommutable = IsCommutable in
4014 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4015 (ins RC:$src1, RC:$src2),
4017 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4018 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4019 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
4020 Sched<[itins.Sched]>;
4021 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4022 (ins RC:$src1, x86memop:$src2),
4024 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4025 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4026 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
4027 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
4030 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
4031 Intrinsic IntId256, OpndItins itins,
4032 bit IsCommutable = 0> {
4033 let Predicates = [HasAVX] in
4034 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
4035 VR128, loadv2i64, i128mem, itins,
4036 IsCommutable, 0>, VEX_4V;
4038 let Constraints = "$src1 = $dst" in
4039 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
4040 i128mem, itins, IsCommutable, 1>;
4042 let Predicates = [HasAVX2] in
4043 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
4044 VR256, loadv4i64, i256mem, itins,
4045 IsCommutable, 0>, VEX_4V, VEX_L;
4048 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
4049 string OpcodeStr, SDNode OpNode,
4050 SDNode OpNode2, RegisterClass RC,
4051 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
4052 ShiftOpndItins itins,
4054 // src2 is always 128-bit
4055 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4056 (ins RC:$src1, VR128:$src2),
4058 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4059 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4060 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
4061 itins.rr>, Sched<[WriteVecShift]>;
4062 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4063 (ins RC:$src1, i128mem:$src2),
4065 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4066 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4067 [(set RC:$dst, (DstVT (OpNode RC:$src1,
4068 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>,
4069 Sched<[WriteVecShiftLd, ReadAfterLd]>;
4070 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
4071 (ins RC:$src1, i8imm:$src2),
4073 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4074 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4075 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
4076 Sched<[WriteVecShift]>;
4079 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
4080 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
4081 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
4082 PatFrag memop_frag, X86MemOperand x86memop,
4084 bit IsCommutable = 0, bit Is2Addr = 1> {
4085 let isCommutable = IsCommutable in
4086 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4087 (ins RC:$src1, RC:$src2),
4089 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4090 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4091 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
4092 Sched<[itins.Sched]>;
4093 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4094 (ins RC:$src1, x86memop:$src2),
4096 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4097 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4098 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
4099 (bitconvert (memop_frag addr:$src2)))))]>,
4100 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4102 } // ExeDomain = SSEPackedInt
4104 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
4105 SSE_INTALU_ITINS_P, 1>;
4106 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
4107 SSE_INTALU_ITINS_P, 1>;
4108 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
4109 SSE_INTALU_ITINS_P, 1>;
4110 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
4111 SSE_INTALUQ_ITINS_P, 1>;
4112 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
4113 SSE_INTMUL_ITINS_P, 1>;
4114 defm PMULHUW : PDI_binop_all<0xE4, "pmulhuw", mulhu, v8i16, v16i16,
4115 SSE_INTMUL_ITINS_P, 1>;
4116 defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16,
4117 SSE_INTMUL_ITINS_P, 1>;
4118 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
4119 SSE_INTALU_ITINS_P, 0>;
4120 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
4121 SSE_INTALU_ITINS_P, 0>;
4122 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
4123 SSE_INTALU_ITINS_P, 0>;
4124 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
4125 SSE_INTALUQ_ITINS_P, 0>;
4126 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
4127 SSE_INTALU_ITINS_P, 0>;
4128 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
4129 SSE_INTALU_ITINS_P, 0>;
4130 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
4131 SSE_INTALU_ITINS_P, 1>;
4132 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
4133 SSE_INTALU_ITINS_P, 1>;
4134 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
4135 SSE_INTALU_ITINS_P, 1>;
4136 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
4137 SSE_INTALU_ITINS_P, 1>;
4140 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4141 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4142 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4143 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4144 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4145 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4146 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4147 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4148 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4149 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4150 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4151 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4152 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4153 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4154 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
4155 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
4156 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
4157 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
4158 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
4159 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
4161 let Predicates = [HasAVX] in
4162 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4163 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4165 let Predicates = [HasAVX2] in
4166 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4167 VR256, loadv4i64, i256mem,
4168 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4169 let Constraints = "$src1 = $dst" in
4170 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4171 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4173 //===---------------------------------------------------------------------===//
4174 // SSE2 - Packed Integer Logical Instructions
4175 //===---------------------------------------------------------------------===//
4177 let Predicates = [HasAVX] in {
4178 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4179 VR128, v8i16, v8i16, bc_v8i16,
4180 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4181 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4182 VR128, v4i32, v4i32, bc_v4i32,
4183 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4184 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4185 VR128, v2i64, v2i64, bc_v2i64,
4186 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4188 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4189 VR128, v8i16, v8i16, bc_v8i16,
4190 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4191 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4192 VR128, v4i32, v4i32, bc_v4i32,
4193 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4194 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4195 VR128, v2i64, v2i64, bc_v2i64,
4196 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4198 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4199 VR128, v8i16, v8i16, bc_v8i16,
4200 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4201 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4202 VR128, v4i32, v4i32, bc_v4i32,
4203 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4205 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4206 // 128-bit logical shifts.
4207 def VPSLLDQri : PDIi8<0x73, MRM7r,
4208 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4209 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4211 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
4213 def VPSRLDQri : PDIi8<0x73, MRM3r,
4214 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4215 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4217 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
4219 // PSRADQri doesn't exist in SSE[1-3].
4221 } // Predicates = [HasAVX]
4223 let Predicates = [HasAVX2] in {
4224 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4225 VR256, v16i16, v8i16, bc_v8i16,
4226 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4227 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4228 VR256, v8i32, v4i32, bc_v4i32,
4229 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4230 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4231 VR256, v4i64, v2i64, bc_v2i64,
4232 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4234 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4235 VR256, v16i16, v8i16, bc_v8i16,
4236 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4237 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4238 VR256, v8i32, v4i32, bc_v4i32,
4239 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4240 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4241 VR256, v4i64, v2i64, bc_v2i64,
4242 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4244 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4245 VR256, v16i16, v8i16, bc_v8i16,
4246 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4247 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4248 VR256, v8i32, v4i32, bc_v4i32,
4249 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4251 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4252 // 256-bit logical shifts.
4253 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4254 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4255 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4257 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
4259 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4260 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4261 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4263 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
4265 // PSRADQYri doesn't exist in SSE[1-3].
4267 } // Predicates = [HasAVX2]
4269 let Constraints = "$src1 = $dst" in {
4270 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4271 VR128, v8i16, v8i16, bc_v8i16,
4272 SSE_INTSHIFT_ITINS_P>;
4273 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4274 VR128, v4i32, v4i32, bc_v4i32,
4275 SSE_INTSHIFT_ITINS_P>;
4276 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4277 VR128, v2i64, v2i64, bc_v2i64,
4278 SSE_INTSHIFT_ITINS_P>;
4280 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4281 VR128, v8i16, v8i16, bc_v8i16,
4282 SSE_INTSHIFT_ITINS_P>;
4283 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4284 VR128, v4i32, v4i32, bc_v4i32,
4285 SSE_INTSHIFT_ITINS_P>;
4286 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4287 VR128, v2i64, v2i64, bc_v2i64,
4288 SSE_INTSHIFT_ITINS_P>;
4290 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4291 VR128, v8i16, v8i16, bc_v8i16,
4292 SSE_INTSHIFT_ITINS_P>;
4293 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4294 VR128, v4i32, v4i32, bc_v4i32,
4295 SSE_INTSHIFT_ITINS_P>;
4297 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4298 // 128-bit logical shifts.
4299 def PSLLDQri : PDIi8<0x73, MRM7r,
4300 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4301 "pslldq\t{$src2, $dst|$dst, $src2}",
4303 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))],
4304 IIC_SSE_INTSHDQ_P_RI>;
4305 def PSRLDQri : PDIi8<0x73, MRM3r,
4306 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4307 "psrldq\t{$src2, $dst|$dst, $src2}",
4309 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))],
4310 IIC_SSE_INTSHDQ_P_RI>;
4311 // PSRADQri doesn't exist in SSE[1-3].
4313 } // Constraints = "$src1 = $dst"
4315 let Predicates = [HasAVX] in {
4316 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4317 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4318 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4319 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4320 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4321 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4323 // Shift up / down and insert zero's.
4324 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4325 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4326 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4327 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4330 let Predicates = [HasAVX2] in {
4331 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4332 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4333 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4334 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4337 let Predicates = [UseSSE2] in {
4338 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4339 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4340 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4341 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4342 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4343 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4345 // Shift up / down and insert zero's.
4346 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4347 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4348 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4349 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4352 //===---------------------------------------------------------------------===//
4353 // SSE2 - Packed Integer Comparison Instructions
4354 //===---------------------------------------------------------------------===//
4356 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4357 SSE_INTALU_ITINS_P, 1>;
4358 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4359 SSE_INTALU_ITINS_P, 1>;
4360 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4361 SSE_INTALU_ITINS_P, 1>;
4362 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4363 SSE_INTALU_ITINS_P, 0>;
4364 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4365 SSE_INTALU_ITINS_P, 0>;
4366 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4367 SSE_INTALU_ITINS_P, 0>;
4369 //===---------------------------------------------------------------------===//
4370 // SSE2 - Packed Integer Shuffle Instructions
4371 //===---------------------------------------------------------------------===//
4373 let ExeDomain = SSEPackedInt in {
4374 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4376 let Predicates = [HasAVX] in {
4377 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4378 (ins VR128:$src1, i8imm:$src2),
4379 !strconcat("v", OpcodeStr,
4380 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4382 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4383 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4384 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4385 (ins i128mem:$src1, i8imm:$src2),
4386 !strconcat("v", OpcodeStr,
4387 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4389 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4390 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4391 Sched<[WriteShuffleLd]>;
4394 let Predicates = [HasAVX2] in {
4395 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4396 (ins VR256:$src1, i8imm:$src2),
4397 !strconcat("v", OpcodeStr,
4398 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4400 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4401 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4402 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4403 (ins i256mem:$src1, i8imm:$src2),
4404 !strconcat("v", OpcodeStr,
4405 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4407 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4408 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4409 Sched<[WriteShuffleLd]>;
4412 let Predicates = [UseSSE2] in {
4413 def ri : Ii8<0x70, MRMSrcReg,
4414 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4415 !strconcat(OpcodeStr,
4416 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4418 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4419 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4420 def mi : Ii8<0x70, MRMSrcMem,
4421 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4422 !strconcat(OpcodeStr,
4423 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4425 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4426 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4427 Sched<[WriteShuffleLd, ReadAfterLd]>;
4430 } // ExeDomain = SSEPackedInt
4432 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
4433 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4434 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4436 let Predicates = [HasAVX] in {
4437 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4438 (VPSHUFDmi addr:$src1, imm:$imm)>;
4439 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4440 (VPSHUFDri VR128:$src1, imm:$imm)>;
4443 let Predicates = [UseSSE2] in {
4444 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4445 (PSHUFDmi addr:$src1, imm:$imm)>;
4446 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4447 (PSHUFDri VR128:$src1, imm:$imm)>;
4450 //===---------------------------------------------------------------------===//
4451 // Packed Integer Pack Instructions (SSE & AVX)
4452 //===---------------------------------------------------------------------===//
4454 let ExeDomain = SSEPackedInt in {
4455 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4456 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4458 def rr : PDI<opc, MRMSrcReg,
4459 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4461 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4462 !strconcat(OpcodeStr,
4463 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4465 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4466 Sched<[WriteShuffle]>;
4467 def rm : PDI<opc, MRMSrcMem,
4468 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4470 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4471 !strconcat(OpcodeStr,
4472 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4474 (OutVT (OpNode VR128:$src1,
4475 (bc_frag (memopv2i64 addr:$src2)))))]>,
4476 Sched<[WriteShuffleLd, ReadAfterLd]>;
4479 multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4480 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4481 def Yrr : PDI<opc, MRMSrcReg,
4482 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4483 !strconcat(OpcodeStr,
4484 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4486 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4487 Sched<[WriteShuffle]>;
4488 def Yrm : PDI<opc, MRMSrcMem,
4489 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4490 !strconcat(OpcodeStr,
4491 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4493 (OutVT (OpNode VR256:$src1,
4494 (bc_frag (memopv4i64 addr:$src2)))))]>,
4495 Sched<[WriteShuffleLd, ReadAfterLd]>;
4498 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4499 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4501 def rr : SS48I<opc, MRMSrcReg,
4502 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4504 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4505 !strconcat(OpcodeStr,
4506 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4508 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4509 Sched<[WriteShuffle]>;
4510 def rm : SS48I<opc, MRMSrcMem,
4511 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4513 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4514 !strconcat(OpcodeStr,
4515 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4517 (OutVT (OpNode VR128:$src1,
4518 (bc_frag (memopv2i64 addr:$src2)))))]>,
4519 Sched<[WriteShuffleLd, ReadAfterLd]>;
4522 multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4523 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4524 def Yrr : SS48I<opc, MRMSrcReg,
4525 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4526 !strconcat(OpcodeStr,
4527 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4529 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4530 Sched<[WriteShuffle]>;
4531 def Yrm : SS48I<opc, MRMSrcMem,
4532 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4533 !strconcat(OpcodeStr,
4534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4536 (OutVT (OpNode VR256:$src1,
4537 (bc_frag (memopv4i64 addr:$src2)))))]>,
4538 Sched<[WriteShuffleLd, ReadAfterLd]>;
4541 let Predicates = [HasAVX] in {
4542 defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
4543 bc_v8i16, 0>, VEX_4V;
4544 defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
4545 bc_v4i32, 0>, VEX_4V;
4547 defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
4548 bc_v8i16, 0>, VEX_4V;
4549 defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
4550 bc_v4i32, 0>, VEX_4V;
4553 let Predicates = [HasAVX2] in {
4554 defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
4555 bc_v16i16>, VEX_4V, VEX_L;
4556 defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
4557 bc_v8i32>, VEX_4V, VEX_L;
4559 defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
4560 bc_v16i16>, VEX_4V, VEX_L;
4561 defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
4562 bc_v8i32>, VEX_4V, VEX_L;
4565 let Constraints = "$src1 = $dst" in {
4566 defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss,
4568 defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss,
4571 defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus,
4574 let Predicates = [HasSSE41] in
4575 defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus,
4578 } // ExeDomain = SSEPackedInt
4580 //===---------------------------------------------------------------------===//
4581 // SSE2 - Packed Integer Unpack Instructions
4582 //===---------------------------------------------------------------------===//
4584 let ExeDomain = SSEPackedInt in {
4585 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4586 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4587 def rr : PDI<opc, MRMSrcReg,
4588 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4590 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4591 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4592 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4593 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4594 def rm : PDI<opc, MRMSrcMem,
4595 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4597 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4598 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4599 [(set VR128:$dst, (OpNode VR128:$src1,
4600 (bc_frag (memopv2i64
4603 Sched<[WriteShuffleLd, ReadAfterLd]>;
4606 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4607 SDNode OpNode, PatFrag bc_frag> {
4608 def Yrr : PDI<opc, MRMSrcReg,
4609 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4610 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4611 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4612 Sched<[WriteShuffle]>;
4613 def Yrm : PDI<opc, MRMSrcMem,
4614 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4615 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4616 [(set VR256:$dst, (OpNode VR256:$src1,
4617 (bc_frag (memopv4i64 addr:$src2))))]>,
4618 Sched<[WriteShuffleLd, ReadAfterLd]>;
4621 let Predicates = [HasAVX] in {
4622 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4623 bc_v16i8, 0>, VEX_4V;
4624 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4625 bc_v8i16, 0>, VEX_4V;
4626 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4627 bc_v4i32, 0>, VEX_4V;
4628 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4629 bc_v2i64, 0>, VEX_4V;
4631 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4632 bc_v16i8, 0>, VEX_4V;
4633 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4634 bc_v8i16, 0>, VEX_4V;
4635 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4636 bc_v4i32, 0>, VEX_4V;
4637 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4638 bc_v2i64, 0>, VEX_4V;
4641 let Predicates = [HasAVX2] in {
4642 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4643 bc_v32i8>, VEX_4V, VEX_L;
4644 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4645 bc_v16i16>, VEX_4V, VEX_L;
4646 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4647 bc_v8i32>, VEX_4V, VEX_L;
4648 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4649 bc_v4i64>, VEX_4V, VEX_L;
4651 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4652 bc_v32i8>, VEX_4V, VEX_L;
4653 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4654 bc_v16i16>, VEX_4V, VEX_L;
4655 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4656 bc_v8i32>, VEX_4V, VEX_L;
4657 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4658 bc_v4i64>, VEX_4V, VEX_L;
4661 let Constraints = "$src1 = $dst" in {
4662 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4664 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4666 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4668 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4671 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4673 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4675 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4677 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4680 } // ExeDomain = SSEPackedInt
4682 //===---------------------------------------------------------------------===//
4683 // SSE2 - Packed Integer Extract and Insert
4684 //===---------------------------------------------------------------------===//
4686 let ExeDomain = SSEPackedInt in {
4687 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4688 def rri : Ii8<0xC4, MRMSrcReg,
4689 (outs VR128:$dst), (ins VR128:$src1,
4690 GR32orGR64:$src2, i32i8imm:$src3),
4692 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4693 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4695 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4696 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4697 def rmi : Ii8<0xC4, MRMSrcMem,
4698 (outs VR128:$dst), (ins VR128:$src1,
4699 i16mem:$src2, i32i8imm:$src3),
4701 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4702 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4704 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4705 imm:$src3))], IIC_SSE_PINSRW>,
4706 Sched<[WriteShuffleLd, ReadAfterLd]>;
4710 let Predicates = [HasAVX] in
4711 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4712 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
4713 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4714 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4715 imm:$src2))]>, PD, VEX,
4716 Sched<[WriteShuffle]>;
4717 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4718 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
4719 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4720 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4721 imm:$src2))], IIC_SSE_PEXTRW>,
4722 Sched<[WriteShuffleLd, ReadAfterLd]>;
4725 let Predicates = [HasAVX] in
4726 defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V;
4728 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4729 defm PINSRW : sse2_pinsrw, PD;
4731 } // ExeDomain = SSEPackedInt
4733 //===---------------------------------------------------------------------===//
4734 // SSE2 - Packed Mask Creation
4735 //===---------------------------------------------------------------------===//
4737 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4739 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4741 "pmovmskb\t{$src, $dst|$dst, $src}",
4742 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4743 IIC_SSE_MOVMSK>, VEX;
4745 let Predicates = [HasAVX2] in {
4746 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4748 "pmovmskb\t{$src, $dst|$dst, $src}",
4749 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4753 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4754 "pmovmskb\t{$src, $dst|$dst, $src}",
4755 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4758 } // ExeDomain = SSEPackedInt
4760 //===---------------------------------------------------------------------===//
4761 // SSE2 - Conditional Store
4762 //===---------------------------------------------------------------------===//
4764 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4766 let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
4767 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4768 (ins VR128:$src, VR128:$mask),
4769 "maskmovdqu\t{$mask, $src|$src, $mask}",
4770 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4771 IIC_SSE_MASKMOV>, VEX;
4772 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4773 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4774 (ins VR128:$src, VR128:$mask),
4775 "maskmovdqu\t{$mask, $src|$src, $mask}",
4776 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4777 IIC_SSE_MASKMOV>, VEX;
4779 let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
4780 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4781 "maskmovdqu\t{$mask, $src|$src, $mask}",
4782 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4784 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4785 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4786 "maskmovdqu\t{$mask, $src|$src, $mask}",
4787 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4790 } // ExeDomain = SSEPackedInt
4792 //===---------------------------------------------------------------------===//
4793 // SSE2 - Move Doubleword
4794 //===---------------------------------------------------------------------===//
4796 //===---------------------------------------------------------------------===//
4797 // Move Int Doubleword to Packed Double Int
4799 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4800 "movd\t{$src, $dst|$dst, $src}",
4802 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4803 VEX, Sched<[WriteMove]>;
4804 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4805 "movd\t{$src, $dst|$dst, $src}",
4807 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4809 VEX, Sched<[WriteLoad]>;
4810 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4811 "movq\t{$src, $dst|$dst, $src}",
4813 (v2i64 (scalar_to_vector GR64:$src)))],
4814 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4815 let isCodeGenOnly = 1 in
4816 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4817 "movq\t{$src, $dst|$dst, $src}",
4818 [(set FR64:$dst, (bitconvert GR64:$src))],
4819 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4821 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4822 "movd\t{$src, $dst|$dst, $src}",
4824 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4826 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4827 "movd\t{$src, $dst|$dst, $src}",
4829 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4830 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4831 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4832 "mov{d|q}\t{$src, $dst|$dst, $src}",
4834 (v2i64 (scalar_to_vector GR64:$src)))],
4835 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4836 let isCodeGenOnly = 1 in
4837 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4838 "mov{d|q}\t{$src, $dst|$dst, $src}",
4839 [(set FR64:$dst, (bitconvert GR64:$src))],
4840 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4842 //===---------------------------------------------------------------------===//
4843 // Move Int Doubleword to Single Scalar
4845 let isCodeGenOnly = 1 in {
4846 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4847 "movd\t{$src, $dst|$dst, $src}",
4848 [(set FR32:$dst, (bitconvert GR32:$src))],
4849 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4851 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4852 "movd\t{$src, $dst|$dst, $src}",
4853 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4855 VEX, Sched<[WriteLoad]>;
4856 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4857 "movd\t{$src, $dst|$dst, $src}",
4858 [(set FR32:$dst, (bitconvert GR32:$src))],
4859 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4861 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4862 "movd\t{$src, $dst|$dst, $src}",
4863 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4864 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4867 //===---------------------------------------------------------------------===//
4868 // Move Packed Doubleword Int to Packed Double Int
4870 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4871 "movd\t{$src, $dst|$dst, $src}",
4872 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4873 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4875 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4876 (ins i32mem:$dst, VR128:$src),
4877 "movd\t{$src, $dst|$dst, $src}",
4878 [(store (i32 (vector_extract (v4i32 VR128:$src),
4879 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4880 VEX, Sched<[WriteStore]>;
4881 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4882 "movd\t{$src, $dst|$dst, $src}",
4883 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4884 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4886 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4887 "movd\t{$src, $dst|$dst, $src}",
4888 [(store (i32 (vector_extract (v4i32 VR128:$src),
4889 (iPTR 0))), addr:$dst)],
4890 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4892 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
4893 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4895 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
4896 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4898 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
4899 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4901 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
4902 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4904 //===---------------------------------------------------------------------===//
4905 // Move Packed Doubleword Int first element to Doubleword Int
4907 let SchedRW = [WriteMove] in {
4908 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4909 "movq\t{$src, $dst|$dst, $src}",
4910 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4915 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4916 "mov{d|q}\t{$src, $dst|$dst, $src}",
4917 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4922 //===---------------------------------------------------------------------===//
4923 // Bitcast FR64 <-> GR64
4925 let isCodeGenOnly = 1 in {
4926 let Predicates = [UseAVX] in
4927 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4928 "movq\t{$src, $dst|$dst, $src}",
4929 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4930 VEX, Sched<[WriteLoad]>;
4931 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4932 "movq\t{$src, $dst|$dst, $src}",
4933 [(set GR64:$dst, (bitconvert FR64:$src))],
4934 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4935 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4936 "movq\t{$src, $dst|$dst, $src}",
4937 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4938 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4940 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4941 "movq\t{$src, $dst|$dst, $src}",
4942 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4943 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4944 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4945 "mov{d|q}\t{$src, $dst|$dst, $src}",
4946 [(set GR64:$dst, (bitconvert FR64:$src))],
4947 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4948 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4949 "movq\t{$src, $dst|$dst, $src}",
4950 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4951 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4954 //===---------------------------------------------------------------------===//
4955 // Move Scalar Single to Double Int
4957 let isCodeGenOnly = 1 in {
4958 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4959 "movd\t{$src, $dst|$dst, $src}",
4960 [(set GR32:$dst, (bitconvert FR32:$src))],
4961 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4962 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4963 "movd\t{$src, $dst|$dst, $src}",
4964 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4965 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4966 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4967 "movd\t{$src, $dst|$dst, $src}",
4968 [(set GR32:$dst, (bitconvert FR32:$src))],
4969 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4970 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4971 "movd\t{$src, $dst|$dst, $src}",
4972 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4973 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4976 //===---------------------------------------------------------------------===//
4977 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4979 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
4980 let AddedComplexity = 15 in {
4981 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4982 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
4983 [(set VR128:$dst, (v2i64 (X86vzmovl
4984 (v2i64 (scalar_to_vector GR64:$src)))))],
4987 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4988 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4989 [(set VR128:$dst, (v2i64 (X86vzmovl
4990 (v2i64 (scalar_to_vector GR64:$src)))))],
4993 } // isCodeGenOnly, SchedRW
4995 let Predicates = [UseAVX] in {
4996 let AddedComplexity = 15 in
4997 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4998 (VMOVDI2PDIrr GR32:$src)>;
5000 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
5001 let AddedComplexity = 20 in {
5002 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
5003 (VMOVDI2PDIrm addr:$src)>;
5004 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
5005 (VMOVDI2PDIrm addr:$src)>;
5006 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
5007 (VMOVDI2PDIrm addr:$src)>;
5009 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
5010 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
5011 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
5012 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
5013 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
5014 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
5015 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
5018 let Predicates = [UseSSE2] in {
5019 let AddedComplexity = 15 in
5020 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
5021 (MOVDI2PDIrr GR32:$src)>;
5023 let AddedComplexity = 20 in {
5024 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
5025 (MOVDI2PDIrm addr:$src)>;
5026 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
5027 (MOVDI2PDIrm addr:$src)>;
5028 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
5029 (MOVDI2PDIrm addr:$src)>;
5033 // These are the correct encodings of the instructions so that we know how to
5034 // read correct assembly, even though we continue to emit the wrong ones for
5035 // compatibility with Darwin's buggy assembler.
5036 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
5037 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
5038 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
5039 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
5040 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
5041 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
5042 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
5043 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
5044 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
5046 //===---------------------------------------------------------------------===//
5047 // SSE2 - Move Quadword
5048 //===---------------------------------------------------------------------===//
5050 //===---------------------------------------------------------------------===//
5051 // Move Quadword Int to Packed Quadword Int
5054 let SchedRW = [WriteLoad] in {
5055 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5056 "vmovq\t{$src, $dst|$dst, $src}",
5058 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
5059 VEX, Requires<[UseAVX]>;
5060 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5061 "movq\t{$src, $dst|$dst, $src}",
5063 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
5065 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
5068 //===---------------------------------------------------------------------===//
5069 // Move Packed Quadword Int to Quadword Int
5071 let SchedRW = [WriteStore] in {
5072 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
5073 "movq\t{$src, $dst|$dst, $src}",
5074 [(store (i64 (vector_extract (v2i64 VR128:$src),
5075 (iPTR 0))), addr:$dst)],
5076 IIC_SSE_MOVDQ>, VEX;
5077 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
5078 "movq\t{$src, $dst|$dst, $src}",
5079 [(store (i64 (vector_extract (v2i64 VR128:$src),
5080 (iPTR 0))), addr:$dst)],
5084 // For disassembler only
5085 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
5086 SchedRW = [WriteVecLogic] in {
5087 def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5088 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, VEX;
5089 def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5090 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>;
5093 //===---------------------------------------------------------------------===//
5094 // Store / copy lower 64-bits of a XMM register.
5096 let Predicates = [UseAVX] in
5097 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5098 (VMOVPQI2QImr addr:$dst, VR128:$src)>;
5099 let Predicates = [UseSSE2] in
5100 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5101 (MOVPQI2QImr addr:$dst, VR128:$src)>;
5103 let isCodeGenOnly = 1, AddedComplexity = 20 in {
5104 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5105 "vmovq\t{$src, $dst|$dst, $src}",
5107 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5108 (loadi64 addr:$src))))))],
5110 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
5112 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5113 "movq\t{$src, $dst|$dst, $src}",
5115 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5116 (loadi64 addr:$src))))))],
5118 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
5121 let Predicates = [UseAVX], AddedComplexity = 20 in {
5122 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5123 (VMOVZQI2PQIrm addr:$src)>;
5124 def : Pat<(v2i64 (X86vzload addr:$src)),
5125 (VMOVZQI2PQIrm addr:$src)>;
5128 let Predicates = [UseSSE2], AddedComplexity = 20 in {
5129 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5130 (MOVZQI2PQIrm addr:$src)>;
5131 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
5134 let Predicates = [HasAVX] in {
5135 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
5136 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
5137 def : Pat<(v4i64 (X86vzload addr:$src)),
5138 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
5141 //===---------------------------------------------------------------------===//
5142 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
5143 // IA32 document. movq xmm1, xmm2 does clear the high bits.
5145 let SchedRW = [WriteVecLogic] in {
5146 let AddedComplexity = 15 in
5147 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5148 "vmovq\t{$src, $dst|$dst, $src}",
5149 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5151 XS, VEX, Requires<[UseAVX]>;
5152 let AddedComplexity = 15 in
5153 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5154 "movq\t{$src, $dst|$dst, $src}",
5155 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5157 XS, Requires<[UseSSE2]>;
5160 let isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
5161 let AddedComplexity = 20 in
5162 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5163 "vmovq\t{$src, $dst|$dst, $src}",
5164 [(set VR128:$dst, (v2i64 (X86vzmovl
5165 (loadv2i64 addr:$src))))],
5167 XS, VEX, Requires<[UseAVX]>;
5168 let AddedComplexity = 20 in {
5169 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5170 "movq\t{$src, $dst|$dst, $src}",
5171 [(set VR128:$dst, (v2i64 (X86vzmovl
5172 (loadv2i64 addr:$src))))],
5174 XS, Requires<[UseSSE2]>;
5176 } // isCodeGenOnly, SchedRW
5178 let AddedComplexity = 20 in {
5179 let Predicates = [UseAVX] in {
5180 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5181 (VMOVZPQILo2PQIrr VR128:$src)>;
5183 let Predicates = [UseSSE2] in {
5184 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5185 (MOVZPQILo2PQIrr VR128:$src)>;
5189 //===---------------------------------------------------------------------===//
5190 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
5191 //===---------------------------------------------------------------------===//
5192 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
5193 ValueType vt, RegisterClass RC, PatFrag mem_frag,
5194 X86MemOperand x86memop> {
5195 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5196 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5197 [(set RC:$dst, (vt (OpNode RC:$src)))],
5198 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5199 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5200 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5201 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
5202 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5205 let Predicates = [HasAVX] in {
5206 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5207 v4f32, VR128, loadv4f32, f128mem>, VEX;
5208 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5209 v4f32, VR128, loadv4f32, f128mem>, VEX;
5210 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5211 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5212 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5213 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5215 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
5216 memopv4f32, f128mem>;
5217 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5218 memopv4f32, f128mem>;
5220 let Predicates = [HasAVX] in {
5221 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5222 (VMOVSHDUPrr VR128:$src)>;
5223 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
5224 (VMOVSHDUPrm addr:$src)>;
5225 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5226 (VMOVSLDUPrr VR128:$src)>;
5227 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
5228 (VMOVSLDUPrm addr:$src)>;
5229 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5230 (VMOVSHDUPYrr VR256:$src)>;
5231 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
5232 (VMOVSHDUPYrm addr:$src)>;
5233 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5234 (VMOVSLDUPYrr VR256:$src)>;
5235 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
5236 (VMOVSLDUPYrm addr:$src)>;
5239 let Predicates = [UseSSE3] in {
5240 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5241 (MOVSHDUPrr VR128:$src)>;
5242 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5243 (MOVSHDUPrm addr:$src)>;
5244 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5245 (MOVSLDUPrr VR128:$src)>;
5246 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5247 (MOVSLDUPrm addr:$src)>;
5250 //===---------------------------------------------------------------------===//
5251 // SSE3 - Replicate Double FP - MOVDDUP
5252 //===---------------------------------------------------------------------===//
5254 multiclass sse3_replicate_dfp<string OpcodeStr> {
5255 let neverHasSideEffects = 1 in
5256 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5257 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5258 [], IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5259 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5260 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5263 (scalar_to_vector (loadf64 addr:$src)))))],
5264 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5267 // FIXME: Merge with above classe when there're patterns for the ymm version
5268 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5269 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5270 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5271 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5272 Sched<[WriteFShuffle]>;
5273 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5274 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5277 (scalar_to_vector (loadf64 addr:$src)))))]>,
5281 let Predicates = [HasAVX] in {
5282 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5283 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5286 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5288 let Predicates = [HasAVX] in {
5289 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5290 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5291 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5292 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5293 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5294 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5295 def : Pat<(X86Movddup (bc_v2f64
5296 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5297 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5300 def : Pat<(X86Movddup (loadv4f64 addr:$src)),
5301 (VMOVDDUPYrm addr:$src)>;
5302 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5303 (VMOVDDUPYrm addr:$src)>;
5304 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5305 (VMOVDDUPYrm addr:$src)>;
5306 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5307 (VMOVDDUPYrr VR256:$src)>;
5310 let Predicates = [UseAVX, OptForSize] in {
5311 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
5312 (VMOVDDUPrm addr:$src)>;
5313 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
5314 (VMOVDDUPrm addr:$src)>;
5317 let Predicates = [UseSSE3] in {
5318 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5319 (MOVDDUPrm addr:$src)>;
5320 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5321 (MOVDDUPrm addr:$src)>;
5322 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5323 (MOVDDUPrm addr:$src)>;
5324 def : Pat<(X86Movddup (bc_v2f64
5325 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5326 (MOVDDUPrm addr:$src)>;
5329 //===---------------------------------------------------------------------===//
5330 // SSE3 - Move Unaligned Integer
5331 //===---------------------------------------------------------------------===//
5333 let SchedRW = [WriteLoad] in {
5334 let Predicates = [HasAVX] in {
5335 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5336 "vlddqu\t{$src, $dst|$dst, $src}",
5337 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5338 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5339 "vlddqu\t{$src, $dst|$dst, $src}",
5340 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5343 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5344 "lddqu\t{$src, $dst|$dst, $src}",
5345 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5349 //===---------------------------------------------------------------------===//
5350 // SSE3 - Arithmetic
5351 //===---------------------------------------------------------------------===//
5353 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5354 X86MemOperand x86memop, OpndItins itins,
5356 def rr : I<0xD0, MRMSrcReg,
5357 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5359 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5360 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5361 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5362 Sched<[itins.Sched]>;
5363 def rm : I<0xD0, MRMSrcMem,
5364 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5366 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5367 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5368 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>,
5369 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5372 let Predicates = [HasAVX] in {
5373 let ExeDomain = SSEPackedSingle in {
5374 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5375 f128mem, SSE_ALU_F32P, 0>, XD, VEX_4V;
5376 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5377 f256mem, SSE_ALU_F32P, 0>, XD, VEX_4V, VEX_L;
5379 let ExeDomain = SSEPackedDouble in {
5380 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5381 f128mem, SSE_ALU_F64P, 0>, PD, VEX_4V;
5382 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5383 f256mem, SSE_ALU_F64P, 0>, PD, VEX_4V, VEX_L;
5386 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5387 let ExeDomain = SSEPackedSingle in
5388 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5389 f128mem, SSE_ALU_F32P>, XD;
5390 let ExeDomain = SSEPackedDouble in
5391 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5392 f128mem, SSE_ALU_F64P>, PD;
5395 // Patterns used to select 'addsub' instructions.
5396 let Predicates = [HasAVX] in {
5397 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5398 (VADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5399 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 (memop addr:$rhs)))),
5400 (VADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5401 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5402 (VADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5403 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 (memop addr:$rhs)))),
5404 (VADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5406 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 VR256:$rhs))),
5407 (VADDSUBPSYrr VR256:$lhs, VR256:$rhs)>;
5408 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 (memop addr:$rhs)))),
5409 (VADDSUBPSYrm VR256:$lhs, f256mem:$rhs)>;
5410 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 VR256:$rhs))),
5411 (VADDSUBPDYrr VR256:$lhs, VR256:$rhs)>;
5412 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 (memop addr:$rhs)))),
5413 (VADDSUBPDYrm VR256:$lhs, f256mem:$rhs)>;
5416 let Predicates = [UseSSE3] in {
5417 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5418 (ADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5419 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 (memop addr:$rhs)))),
5420 (ADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5421 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5422 (ADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5423 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 (memop addr:$rhs)))),
5424 (ADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5427 //===---------------------------------------------------------------------===//
5428 // SSE3 Instructions
5429 //===---------------------------------------------------------------------===//
5432 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5433 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5434 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5436 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5437 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5438 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5441 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5443 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5444 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5445 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5446 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5448 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5449 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5450 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5452 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5453 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5454 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5457 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5459 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5460 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5461 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5462 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5465 let Predicates = [HasAVX] in {
5466 let ExeDomain = SSEPackedSingle in {
5467 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5468 X86fhadd, 0>, VEX_4V;
5469 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5470 X86fhsub, 0>, VEX_4V;
5471 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5472 X86fhadd, 0>, VEX_4V, VEX_L;
5473 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5474 X86fhsub, 0>, VEX_4V, VEX_L;
5476 let ExeDomain = SSEPackedDouble in {
5477 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5478 X86fhadd, 0>, VEX_4V;
5479 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5480 X86fhsub, 0>, VEX_4V;
5481 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5482 X86fhadd, 0>, VEX_4V, VEX_L;
5483 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5484 X86fhsub, 0>, VEX_4V, VEX_L;
5488 let Constraints = "$src1 = $dst" in {
5489 let ExeDomain = SSEPackedSingle in {
5490 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5491 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5493 let ExeDomain = SSEPackedDouble in {
5494 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5495 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5499 //===---------------------------------------------------------------------===//
5500 // SSSE3 - Packed Absolute Instructions
5501 //===---------------------------------------------------------------------===//
5504 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5505 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5506 Intrinsic IntId128> {
5507 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5509 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5510 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5511 Sched<[WriteVecALU]>;
5513 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5515 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5518 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5519 Sched<[WriteVecALULd]>;
5522 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5523 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5524 Intrinsic IntId256> {
5525 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5527 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5528 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5529 Sched<[WriteVecALU]>;
5531 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5533 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5536 (bitconvert (memopv4i64 addr:$src))))]>,
5537 Sched<[WriteVecALULd]>;
5540 // Helper fragments to match sext vXi1 to vXiY.
5541 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5543 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5544 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5545 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5547 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5548 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5550 let Predicates = [HasAVX] in {
5551 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5552 int_x86_ssse3_pabs_b_128>, VEX;
5553 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5554 int_x86_ssse3_pabs_w_128>, VEX;
5555 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5556 int_x86_ssse3_pabs_d_128>, VEX;
5559 (bc_v2i64 (v16i1sextv16i8)),
5560 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5561 (VPABSBrr128 VR128:$src)>;
5563 (bc_v2i64 (v8i1sextv8i16)),
5564 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5565 (VPABSWrr128 VR128:$src)>;
5567 (bc_v2i64 (v4i1sextv4i32)),
5568 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5569 (VPABSDrr128 VR128:$src)>;
5572 let Predicates = [HasAVX2] in {
5573 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5574 int_x86_avx2_pabs_b>, VEX, VEX_L;
5575 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5576 int_x86_avx2_pabs_w>, VEX, VEX_L;
5577 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5578 int_x86_avx2_pabs_d>, VEX, VEX_L;
5581 (bc_v4i64 (v32i1sextv32i8)),
5582 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5583 (VPABSBrr256 VR256:$src)>;
5585 (bc_v4i64 (v16i1sextv16i16)),
5586 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5587 (VPABSWrr256 VR256:$src)>;
5589 (bc_v4i64 (v8i1sextv8i32)),
5590 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5591 (VPABSDrr256 VR256:$src)>;
5594 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5595 int_x86_ssse3_pabs_b_128>;
5596 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5597 int_x86_ssse3_pabs_w_128>;
5598 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5599 int_x86_ssse3_pabs_d_128>;
5601 let Predicates = [HasSSSE3] in {
5603 (bc_v2i64 (v16i1sextv16i8)),
5604 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5605 (PABSBrr128 VR128:$src)>;
5607 (bc_v2i64 (v8i1sextv8i16)),
5608 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5609 (PABSWrr128 VR128:$src)>;
5611 (bc_v2i64 (v4i1sextv4i32)),
5612 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5613 (PABSDrr128 VR128:$src)>;
5616 //===---------------------------------------------------------------------===//
5617 // SSSE3 - Packed Binary Operator Instructions
5618 //===---------------------------------------------------------------------===//
5620 let Sched = WriteVecALU in {
5621 def SSE_PHADDSUBD : OpndItins<
5622 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5624 def SSE_PHADDSUBSW : OpndItins<
5625 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5627 def SSE_PHADDSUBW : OpndItins<
5628 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5631 let Sched = WriteShuffle in
5632 def SSE_PSHUFB : OpndItins<
5633 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5635 let Sched = WriteVecALU in
5636 def SSE_PSIGN : OpndItins<
5637 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5639 let Sched = WriteVecIMul in
5640 def SSE_PMULHRSW : OpndItins<
5641 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5644 /// SS3I_binop_rm - Simple SSSE3 bin op
5645 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5646 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5647 X86MemOperand x86memop, OpndItins itins,
5649 let isCommutable = 1 in
5650 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5651 (ins RC:$src1, RC:$src2),
5653 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5654 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5655 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5656 Sched<[itins.Sched]>;
5657 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5658 (ins RC:$src1, x86memop:$src2),
5660 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5661 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5663 (OpVT (OpNode RC:$src1,
5664 (bitconvert (memop_frag addr:$src2)))))], itins.rm>,
5665 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5668 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5669 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5670 Intrinsic IntId128, OpndItins itins,
5672 let isCommutable = 1 in
5673 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5674 (ins VR128:$src1, VR128:$src2),
5676 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5677 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5678 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5679 Sched<[itins.Sched]>;
5680 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5681 (ins VR128:$src1, i128mem:$src2),
5683 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5684 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5686 (IntId128 VR128:$src1,
5687 (bitconvert (memopv2i64 addr:$src2))))]>,
5688 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5691 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5693 X86FoldableSchedWrite Sched> {
5694 let isCommutable = 1 in
5695 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5696 (ins VR256:$src1, VR256:$src2),
5697 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5698 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5700 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5701 (ins VR256:$src1, i256mem:$src2),
5702 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5704 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
5705 Sched<[Sched.Folded, ReadAfterLd]>;
5708 let ImmT = NoImm, Predicates = [HasAVX] in {
5709 let isCommutable = 0 in {
5710 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5712 SSE_PHADDSUBW, 0>, VEX_4V;
5713 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5715 SSE_PHADDSUBD, 0>, VEX_4V;
5716 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5718 SSE_PHADDSUBW, 0>, VEX_4V;
5719 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5721 SSE_PHADDSUBD, 0>, VEX_4V;
5722 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5724 SSE_PSIGN, 0>, VEX_4V;
5725 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5727 SSE_PSIGN, 0>, VEX_4V;
5728 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5730 SSE_PSIGN, 0>, VEX_4V;
5731 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5733 SSE_PSHUFB, 0>, VEX_4V;
5734 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5735 int_x86_ssse3_phadd_sw_128,
5736 SSE_PHADDSUBSW, 0>, VEX_4V;
5737 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5738 int_x86_ssse3_phsub_sw_128,
5739 SSE_PHADDSUBSW, 0>, VEX_4V;
5740 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5741 int_x86_ssse3_pmadd_ub_sw_128,
5742 SSE_PMADD, 0>, VEX_4V;
5744 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5745 int_x86_ssse3_pmul_hr_sw_128,
5746 SSE_PMULHRSW, 0>, VEX_4V;
5749 let ImmT = NoImm, Predicates = [HasAVX2] in {
5750 let isCommutable = 0 in {
5751 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5753 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5754 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5756 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5757 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5759 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5760 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5762 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5763 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5765 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5766 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5768 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5769 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5771 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5772 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5774 SSE_PSHUFB, 0>, VEX_4V, VEX_L;
5775 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5776 int_x86_avx2_phadd_sw,
5777 WriteVecALU>, VEX_4V, VEX_L;
5778 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5779 int_x86_avx2_phsub_sw,
5780 WriteVecALU>, VEX_4V, VEX_L;
5781 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5782 int_x86_avx2_pmadd_ub_sw,
5783 WriteVecIMul>, VEX_4V, VEX_L;
5785 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5786 int_x86_avx2_pmul_hr_sw,
5787 WriteVecIMul>, VEX_4V, VEX_L;
5790 // None of these have i8 immediate fields.
5791 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5792 let isCommutable = 0 in {
5793 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5794 memopv2i64, i128mem, SSE_PHADDSUBW>;
5795 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5796 memopv2i64, i128mem, SSE_PHADDSUBD>;
5797 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5798 memopv2i64, i128mem, SSE_PHADDSUBW>;
5799 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5800 memopv2i64, i128mem, SSE_PHADDSUBD>;
5801 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5802 memopv2i64, i128mem, SSE_PSIGN>;
5803 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5804 memopv2i64, i128mem, SSE_PSIGN>;
5805 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5806 memopv2i64, i128mem, SSE_PSIGN>;
5807 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5808 memopv2i64, i128mem, SSE_PSHUFB>;
5809 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5810 int_x86_ssse3_phadd_sw_128,
5812 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5813 int_x86_ssse3_phsub_sw_128,
5815 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5816 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5818 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5819 int_x86_ssse3_pmul_hr_sw_128,
5823 //===---------------------------------------------------------------------===//
5824 // SSSE3 - Packed Align Instruction Patterns
5825 //===---------------------------------------------------------------------===//
5827 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5828 let neverHasSideEffects = 1 in {
5829 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5830 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5832 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5834 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5835 [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
5837 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5838 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5840 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5842 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5843 [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5847 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5848 let neverHasSideEffects = 1 in {
5849 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5850 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5852 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5853 []>, Sched<[WriteShuffle]>;
5855 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5856 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5858 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5859 []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5863 let Predicates = [HasAVX] in
5864 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5865 let Predicates = [HasAVX2] in
5866 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5867 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5868 defm PALIGN : ssse3_palignr<"palignr">;
5870 let Predicates = [HasAVX2] in {
5871 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5872 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5873 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5874 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5875 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5876 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5877 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5878 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5881 let Predicates = [HasAVX] in {
5882 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5883 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5884 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5885 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5886 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5887 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5888 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5889 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5892 let Predicates = [UseSSSE3] in {
5893 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5894 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5895 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5896 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5897 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5898 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5899 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5900 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5903 //===---------------------------------------------------------------------===//
5904 // SSSE3 - Thread synchronization
5905 //===---------------------------------------------------------------------===//
5907 let SchedRW = [WriteSystem] in {
5908 let usesCustomInserter = 1 in {
5909 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5910 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5911 Requires<[HasSSE3]>;
5914 let Uses = [EAX, ECX, EDX] in
5915 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5916 TB, Requires<[HasSSE3]>;
5917 let Uses = [ECX, EAX] in
5918 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5919 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5920 TB, Requires<[HasSSE3]>;
5923 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
5924 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5926 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
5927 Requires<[Not64BitMode]>;
5928 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
5929 Requires<[In64BitMode]>;
5931 //===----------------------------------------------------------------------===//
5932 // SSE4.1 - Packed Move with Sign/Zero Extend
5933 //===----------------------------------------------------------------------===//
5935 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5936 OpndItins itins = DEFAULT_ITINS> {
5937 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5938 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5939 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>,
5940 Sched<[itins.Sched]>;
5942 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5943 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5945 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))],
5946 itins.rm>, Sched<[itins.Sched.Folded]>;
5949 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5950 Intrinsic IntId, X86FoldableSchedWrite Sched> {
5951 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5952 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5953 [(set VR256:$dst, (IntId VR128:$src))]>, Sched<[Sched]>;
5955 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5956 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5957 [(set VR256:$dst, (IntId (load addr:$src)))]>,
5958 Sched<[Sched.Folded]>;
5961 let Predicates = [HasAVX] in {
5962 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw",
5963 int_x86_sse41_pmovsxbw,
5964 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5965 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd",
5966 int_x86_sse41_pmovsxwd,
5967 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5968 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq",
5969 int_x86_sse41_pmovsxdq,
5970 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5971 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw",
5972 int_x86_sse41_pmovzxbw,
5973 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5974 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd",
5975 int_x86_sse41_pmovzxwd,
5976 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5977 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq",
5978 int_x86_sse41_pmovzxdq,
5979 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5982 let Predicates = [HasAVX2] in {
5983 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5984 int_x86_avx2_pmovsxbw,
5985 WriteShuffle>, VEX, VEX_L;
5986 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5987 int_x86_avx2_pmovsxwd,
5988 WriteShuffle>, VEX, VEX_L;
5989 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5990 int_x86_avx2_pmovsxdq,
5991 WriteShuffle>, VEX, VEX_L;
5992 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5993 int_x86_avx2_pmovzxbw,
5994 WriteShuffle>, VEX, VEX_L;
5995 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5996 int_x86_avx2_pmovzxwd,
5997 WriteShuffle>, VEX, VEX_L;
5998 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5999 int_x86_avx2_pmovzxdq,
6000 WriteShuffle>, VEX, VEX_L;
6003 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw,
6004 SSE_INTALU_ITINS_SHUFF_P>;
6005 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd,
6006 SSE_INTALU_ITINS_SHUFF_P>;
6007 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq,
6008 SSE_INTALU_ITINS_SHUFF_P>;
6009 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw,
6010 SSE_INTALU_ITINS_SHUFF_P>;
6011 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd,
6012 SSE_INTALU_ITINS_SHUFF_P>;
6013 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq,
6014 SSE_INTALU_ITINS_SHUFF_P>;
6016 let Predicates = [HasAVX] in {
6017 // Common patterns involving scalar load.
6018 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
6019 (VPMOVSXBWrm addr:$src)>;
6020 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
6021 (VPMOVSXBWrm addr:$src)>;
6022 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
6023 (VPMOVSXBWrm addr:$src)>;
6025 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
6026 (VPMOVSXWDrm addr:$src)>;
6027 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
6028 (VPMOVSXWDrm addr:$src)>;
6029 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
6030 (VPMOVSXWDrm addr:$src)>;
6032 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
6033 (VPMOVSXDQrm addr:$src)>;
6034 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
6035 (VPMOVSXDQrm addr:$src)>;
6036 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
6037 (VPMOVSXDQrm addr:$src)>;
6039 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
6040 (VPMOVZXBWrm addr:$src)>;
6041 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
6042 (VPMOVZXBWrm addr:$src)>;
6043 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
6044 (VPMOVZXBWrm addr:$src)>;
6046 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
6047 (VPMOVZXWDrm addr:$src)>;
6048 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
6049 (VPMOVZXWDrm addr:$src)>;
6050 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
6051 (VPMOVZXWDrm addr:$src)>;
6053 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
6054 (VPMOVZXDQrm addr:$src)>;
6055 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
6056 (VPMOVZXDQrm addr:$src)>;
6057 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
6058 (VPMOVZXDQrm addr:$src)>;
6061 let Predicates = [UseSSE41] in {
6062 // Common patterns involving scalar load.
6063 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
6064 (PMOVSXBWrm addr:$src)>;
6065 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
6066 (PMOVSXBWrm addr:$src)>;
6067 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
6068 (PMOVSXBWrm addr:$src)>;
6070 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
6071 (PMOVSXWDrm addr:$src)>;
6072 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
6073 (PMOVSXWDrm addr:$src)>;
6074 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
6075 (PMOVSXWDrm addr:$src)>;
6077 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
6078 (PMOVSXDQrm addr:$src)>;
6079 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
6080 (PMOVSXDQrm addr:$src)>;
6081 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
6082 (PMOVSXDQrm addr:$src)>;
6084 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
6085 (PMOVZXBWrm addr:$src)>;
6086 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
6087 (PMOVZXBWrm addr:$src)>;
6088 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
6089 (PMOVZXBWrm addr:$src)>;
6091 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
6092 (PMOVZXWDrm addr:$src)>;
6093 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
6094 (PMOVZXWDrm addr:$src)>;
6095 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
6096 (PMOVZXWDrm addr:$src)>;
6098 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
6099 (PMOVZXDQrm addr:$src)>;
6100 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
6101 (PMOVZXDQrm addr:$src)>;
6102 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
6103 (PMOVZXDQrm addr:$src)>;
6106 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId,
6107 OpndItins itins = DEFAULT_ITINS> {
6108 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
6109 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6110 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>,
6111 Sched<[itins.Sched]>;
6113 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
6114 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6116 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))],
6117 itins.rm>, Sched<[itins.Sched.Folded]>;
6120 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
6121 Intrinsic IntId, X86FoldableSchedWrite Sched> {
6122 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
6123 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6124 [(set VR256:$dst, (IntId VR128:$src))]>, Sched<[Sched]>;
6126 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
6127 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6129 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
6130 Sched<[Sched.Folded]>;
6133 let Predicates = [HasAVX] in {
6134 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd,
6135 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6136 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq,
6137 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6138 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd,
6139 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6140 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq,
6141 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6144 let Predicates = [HasAVX2] in {
6145 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
6146 int_x86_avx2_pmovsxbd, WriteShuffle>,
6148 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
6149 int_x86_avx2_pmovsxwq, WriteShuffle>,
6151 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
6152 int_x86_avx2_pmovzxbd, WriteShuffle>,
6154 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
6155 int_x86_avx2_pmovzxwq, WriteShuffle>,
6159 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd,
6160 SSE_INTALU_ITINS_SHUFF_P>;
6161 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq,
6162 SSE_INTALU_ITINS_SHUFF_P>;
6163 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd,
6164 SSE_INTALU_ITINS_SHUFF_P>;
6165 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq,
6166 SSE_INTALU_ITINS_SHUFF_P>;
6168 let Predicates = [HasAVX] in {
6169 // Common patterns involving scalar load
6170 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
6171 (VPMOVSXBDrm addr:$src)>;
6172 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
6173 (VPMOVSXWQrm addr:$src)>;
6175 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
6176 (VPMOVZXBDrm addr:$src)>;
6177 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
6178 (VPMOVZXWQrm addr:$src)>;
6181 let Predicates = [UseSSE41] in {
6182 // Common patterns involving scalar load
6183 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
6184 (PMOVSXBDrm addr:$src)>;
6185 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
6186 (PMOVSXWQrm addr:$src)>;
6188 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
6189 (PMOVZXBDrm addr:$src)>;
6190 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
6191 (PMOVZXWQrm addr:$src)>;
6194 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId,
6195 X86FoldableSchedWrite Sched> {
6196 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
6197 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6198 [(set VR128:$dst, (IntId VR128:$src))]>, Sched<[Sched]>;
6200 // Expecting a i16 load any extended to i32 value.
6201 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
6202 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6203 [(set VR128:$dst, (IntId (bitconvert
6204 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
6205 Sched<[Sched.Folded]>;
6208 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
6209 Intrinsic IntId, X86FoldableSchedWrite Sched> {
6210 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
6211 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6212 [(set VR256:$dst, (IntId VR128:$src))]>, Sched<[Sched]>;
6214 // Expecting a i16 load any extended to i32 value.
6215 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
6216 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6217 [(set VR256:$dst, (IntId (bitconvert
6218 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
6219 Sched<[Sched.Folded]>;
6222 let Predicates = [HasAVX] in {
6223 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq,
6225 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq,
6228 let Predicates = [HasAVX2] in {
6229 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq", int_x86_avx2_pmovsxbq,
6230 WriteShuffle>, VEX, VEX_L;
6231 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq", int_x86_avx2_pmovzxbq,
6232 WriteShuffle>, VEX, VEX_L;
6234 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq,
6236 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq,
6239 let Predicates = [HasAVX2] in {
6240 def : Pat<(v16i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWYrr VR128:$src)>;
6241 def : Pat<(v8i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDYrr VR128:$src)>;
6242 def : Pat<(v4i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQYrr VR128:$src)>;
6244 def : Pat<(v8i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
6245 def : Pat<(v4i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQYrr VR128:$src)>;
6247 def : Pat<(v4i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
6249 def : Pat<(v16i16 (X86vsext (v32i8 VR256:$src))),
6250 (VPMOVSXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6251 def : Pat<(v8i32 (X86vsext (v32i8 VR256:$src))),
6252 (VPMOVSXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6253 def : Pat<(v4i64 (X86vsext (v32i8 VR256:$src))),
6254 (VPMOVSXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6256 def : Pat<(v8i32 (X86vsext (v16i16 VR256:$src))),
6257 (VPMOVSXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6258 def : Pat<(v4i64 (X86vsext (v16i16 VR256:$src))),
6259 (VPMOVSXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6261 def : Pat<(v4i64 (X86vsext (v8i32 VR256:$src))),
6262 (VPMOVSXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6264 def : Pat<(v8i32 (X86vsext (v8i16 (bitconvert (v2i64 (load addr:$src)))))),
6265 (VPMOVSXWDYrm addr:$src)>;
6266 def : Pat<(v4i64 (X86vsext (v4i32 (bitconvert (v2i64 (load addr:$src)))))),
6267 (VPMOVSXDQYrm addr:$src)>;
6269 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2i64
6270 (scalar_to_vector (loadi64 addr:$src))))))),
6271 (VPMOVSXBDYrm addr:$src)>;
6272 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2f64
6273 (scalar_to_vector (loadf64 addr:$src))))))),
6274 (VPMOVSXBDYrm addr:$src)>;
6276 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2i64
6277 (scalar_to_vector (loadi64 addr:$src))))))),
6278 (VPMOVSXWQYrm addr:$src)>;
6279 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2f64
6280 (scalar_to_vector (loadf64 addr:$src))))))),
6281 (VPMOVSXWQYrm addr:$src)>;
6283 def : Pat<(v4i64 (X86vsext (v16i8 (bitconvert (v4i32
6284 (scalar_to_vector (loadi32 addr:$src))))))),
6285 (VPMOVSXBQYrm addr:$src)>;
6288 let Predicates = [HasAVX] in {
6289 // Common patterns involving scalar load
6290 def : Pat<(int_x86_sse41_pmovsxbq
6291 (bitconvert (v4i32 (X86vzmovl
6292 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6293 (VPMOVSXBQrm addr:$src)>;
6295 def : Pat<(int_x86_sse41_pmovzxbq
6296 (bitconvert (v4i32 (X86vzmovl
6297 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6298 (VPMOVZXBQrm addr:$src)>;
6301 let Predicates = [UseSSE41] in {
6302 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (PMOVSXBWrr VR128:$src)>;
6303 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (PMOVSXBDrr VR128:$src)>;
6304 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (PMOVSXBQrr VR128:$src)>;
6306 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
6307 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (PMOVSXWQrr VR128:$src)>;
6309 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
6311 // Common patterns involving scalar load
6312 def : Pat<(int_x86_sse41_pmovsxbq
6313 (bitconvert (v4i32 (X86vzmovl
6314 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6315 (PMOVSXBQrm addr:$src)>;
6317 def : Pat<(int_x86_sse41_pmovzxbq
6318 (bitconvert (v4i32 (X86vzmovl
6319 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6320 (PMOVZXBQrm addr:$src)>;
6322 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
6323 (scalar_to_vector (loadi64 addr:$src))))))),
6324 (PMOVSXWDrm addr:$src)>;
6325 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
6326 (scalar_to_vector (loadf64 addr:$src))))))),
6327 (PMOVSXWDrm addr:$src)>;
6328 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
6329 (scalar_to_vector (loadi32 addr:$src))))))),
6330 (PMOVSXBDrm addr:$src)>;
6331 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
6332 (scalar_to_vector (loadi32 addr:$src))))))),
6333 (PMOVSXWQrm addr:$src)>;
6334 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
6335 (scalar_to_vector (extloadi32i16 addr:$src))))))),
6336 (PMOVSXBQrm addr:$src)>;
6337 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
6338 (scalar_to_vector (loadi64 addr:$src))))))),
6339 (PMOVSXDQrm addr:$src)>;
6340 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
6341 (scalar_to_vector (loadf64 addr:$src))))))),
6342 (PMOVSXDQrm addr:$src)>;
6343 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
6344 (scalar_to_vector (loadi64 addr:$src))))))),
6345 (PMOVSXBWrm addr:$src)>;
6346 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
6347 (scalar_to_vector (loadf64 addr:$src))))))),
6348 (PMOVSXBWrm addr:$src)>;
6351 let Predicates = [HasAVX2] in {
6352 def : Pat<(v16i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWYrr VR128:$src)>;
6353 def : Pat<(v8i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDYrr VR128:$src)>;
6354 def : Pat<(v4i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQYrr VR128:$src)>;
6356 def : Pat<(v8i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDYrr VR128:$src)>;
6357 def : Pat<(v4i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQYrr VR128:$src)>;
6359 def : Pat<(v4i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQYrr VR128:$src)>;
6361 def : Pat<(v16i16 (X86vzext (v32i8 VR256:$src))),
6362 (VPMOVZXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6363 def : Pat<(v8i32 (X86vzext (v32i8 VR256:$src))),
6364 (VPMOVZXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6365 def : Pat<(v4i64 (X86vzext (v32i8 VR256:$src))),
6366 (VPMOVZXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6368 def : Pat<(v8i32 (X86vzext (v16i16 VR256:$src))),
6369 (VPMOVZXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6370 def : Pat<(v4i64 (X86vzext (v16i16 VR256:$src))),
6371 (VPMOVZXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6373 def : Pat<(v4i64 (X86vzext (v8i32 VR256:$src))),
6374 (VPMOVZXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6377 let Predicates = [HasAVX] in {
6378 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWrr VR128:$src)>;
6379 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDrr VR128:$src)>;
6380 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQrr VR128:$src)>;
6382 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDrr VR128:$src)>;
6383 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQrr VR128:$src)>;
6385 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQrr VR128:$src)>;
6387 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6388 (VPMOVZXBWrm addr:$src)>;
6389 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6390 (VPMOVZXBWrm addr:$src)>;
6391 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6392 (VPMOVZXBDrm addr:$src)>;
6393 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
6394 (VPMOVZXBQrm addr:$src)>;
6396 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6397 (VPMOVZXWDrm addr:$src)>;
6398 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6399 (VPMOVZXWDrm addr:$src)>;
6400 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6401 (VPMOVZXWQrm addr:$src)>;
6403 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6404 (VPMOVZXDQrm addr:$src)>;
6405 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6406 (VPMOVZXDQrm addr:$src)>;
6407 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
6408 (VPMOVZXDQrm addr:$src)>;
6410 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWrr VR128:$src)>;
6411 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDrr VR128:$src)>;
6412 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQrr VR128:$src)>;
6414 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
6415 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQrr VR128:$src)>;
6417 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
6419 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
6420 (scalar_to_vector (loadi64 addr:$src))))))),
6421 (VPMOVSXWDrm addr:$src)>;
6422 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
6423 (scalar_to_vector (loadi64 addr:$src))))))),
6424 (VPMOVSXDQrm addr:$src)>;
6425 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
6426 (scalar_to_vector (loadf64 addr:$src))))))),
6427 (VPMOVSXWDrm addr:$src)>;
6428 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
6429 (scalar_to_vector (loadf64 addr:$src))))))),
6430 (VPMOVSXDQrm addr:$src)>;
6431 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
6432 (scalar_to_vector (loadi64 addr:$src))))))),
6433 (VPMOVSXBWrm addr:$src)>;
6434 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
6435 (scalar_to_vector (loadf64 addr:$src))))))),
6436 (VPMOVSXBWrm addr:$src)>;
6438 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
6439 (scalar_to_vector (loadi32 addr:$src))))))),
6440 (VPMOVSXBDrm addr:$src)>;
6441 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
6442 (scalar_to_vector (loadi32 addr:$src))))))),
6443 (VPMOVSXWQrm addr:$src)>;
6444 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
6445 (scalar_to_vector (extloadi32i16 addr:$src))))))),
6446 (VPMOVSXBQrm addr:$src)>;
6449 let Predicates = [UseSSE41] in {
6450 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (PMOVZXBWrr VR128:$src)>;
6451 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (PMOVZXBDrr VR128:$src)>;
6452 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (PMOVZXBQrr VR128:$src)>;
6454 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (PMOVZXWDrr VR128:$src)>;
6455 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (PMOVZXWQrr VR128:$src)>;
6457 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (PMOVZXDQrr VR128:$src)>;
6459 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6460 (PMOVZXBWrm addr:$src)>;
6461 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6462 (PMOVZXBWrm addr:$src)>;
6463 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6464 (PMOVZXBDrm addr:$src)>;
6465 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
6466 (PMOVZXBQrm addr:$src)>;
6468 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6469 (PMOVZXWDrm addr:$src)>;
6470 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6471 (PMOVZXWDrm addr:$src)>;
6472 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6473 (PMOVZXWQrm addr:$src)>;
6475 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6476 (PMOVZXDQrm addr:$src)>;
6477 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6478 (PMOVZXDQrm addr:$src)>;
6479 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
6480 (PMOVZXDQrm addr:$src)>;
6483 //===----------------------------------------------------------------------===//
6484 // SSE4.1 - Extract Instructions
6485 //===----------------------------------------------------------------------===//
6487 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6488 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6489 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6490 (ins VR128:$src1, i32i8imm:$src2),
6491 !strconcat(OpcodeStr,
6492 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6493 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6495 Sched<[WriteShuffle]>;
6496 let neverHasSideEffects = 1, mayStore = 1,
6497 SchedRW = [WriteShuffleLd, WriteRMW] in
6498 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6499 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
6500 !strconcat(OpcodeStr,
6501 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6502 [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
6503 imm:$src2)))), addr:$dst)]>;
6506 let Predicates = [HasAVX] in
6507 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6509 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6512 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6513 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6514 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
6515 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6516 (ins VR128:$src1, i32i8imm:$src2),
6517 !strconcat(OpcodeStr,
6518 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6519 []>, Sched<[WriteShuffle]>;
6521 let neverHasSideEffects = 1, mayStore = 1,
6522 SchedRW = [WriteShuffleLd, WriteRMW] in
6523 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6524 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
6525 !strconcat(OpcodeStr,
6526 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6527 [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
6528 imm:$src2)))), addr:$dst)]>;
6531 let Predicates = [HasAVX] in
6532 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6534 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6537 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6538 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6539 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6540 (ins VR128:$src1, i32i8imm:$src2),
6541 !strconcat(OpcodeStr,
6542 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6544 (extractelt (v4i32 VR128:$src1), imm:$src2))]>,
6545 Sched<[WriteShuffle]>;
6546 let SchedRW = [WriteShuffleLd, WriteRMW] in
6547 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6548 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
6549 !strconcat(OpcodeStr,
6550 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6551 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6555 let Predicates = [HasAVX] in
6556 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6558 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6560 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6561 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6562 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6563 (ins VR128:$src1, i32i8imm:$src2),
6564 !strconcat(OpcodeStr,
6565 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6567 (extractelt (v2i64 VR128:$src1), imm:$src2))]>,
6568 Sched<[WriteShuffle]>, REX_W;
6569 let SchedRW = [WriteShuffleLd, WriteRMW] in
6570 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6571 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
6572 !strconcat(OpcodeStr,
6573 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6574 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6575 addr:$dst)]>, REX_W;
6578 let Predicates = [HasAVX] in
6579 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6581 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6583 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6585 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6586 OpndItins itins = DEFAULT_ITINS> {
6587 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6588 (ins VR128:$src1, i32i8imm:$src2),
6589 !strconcat(OpcodeStr,
6590 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6591 [(set GR32orGR64:$dst,
6592 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6593 itins.rr>, Sched<[WriteFBlend]>;
6594 let SchedRW = [WriteFBlendLd, WriteRMW] in
6595 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6596 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
6597 !strconcat(OpcodeStr,
6598 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6599 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6600 addr:$dst)], itins.rm>;
6603 let ExeDomain = SSEPackedSingle in {
6604 let Predicates = [UseAVX] in
6605 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6606 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6609 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6610 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6613 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6615 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6618 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6619 Requires<[UseSSE41]>;
6621 //===----------------------------------------------------------------------===//
6622 // SSE4.1 - Insert Instructions
6623 //===----------------------------------------------------------------------===//
6625 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6626 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6627 (ins VR128:$src1, GR32orGR64:$src2, i32i8imm:$src3),
6629 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6631 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6633 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>,
6634 Sched<[WriteShuffle]>;
6635 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6636 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6638 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6640 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6642 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6643 imm:$src3))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6646 let Predicates = [HasAVX] in
6647 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6648 let Constraints = "$src1 = $dst" in
6649 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6651 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6652 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6653 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6655 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6657 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6659 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6660 Sched<[WriteShuffle]>;
6661 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6662 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6664 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6666 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6668 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6669 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6672 let Predicates = [HasAVX] in
6673 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6674 let Constraints = "$src1 = $dst" in
6675 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6677 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6678 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6679 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6681 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6683 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6685 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6686 Sched<[WriteShuffle]>;
6687 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6688 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6690 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6692 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6694 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6695 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6698 let Predicates = [HasAVX] in
6699 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6700 let Constraints = "$src1 = $dst" in
6701 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6703 // insertps has a few different modes, there's the first two here below which
6704 // are optimized inserts that won't zero arbitrary elements in the destination
6705 // vector. The next one matches the intrinsic and could zero arbitrary elements
6706 // in the target vector.
6707 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6708 OpndItins itins = DEFAULT_ITINS> {
6709 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6710 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6712 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6714 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6716 (X86insertps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6717 Sched<[WriteFShuffle]>;
6718 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6719 (ins VR128:$src1, f32mem:$src2, i8imm:$src3),
6721 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6723 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6725 (X86insertps VR128:$src1,
6726 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6727 imm:$src3))], itins.rm>,
6728 Sched<[WriteFShuffleLd, ReadAfterLd]>;
6731 let ExeDomain = SSEPackedSingle in {
6732 let Predicates = [UseAVX] in
6733 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6734 let Constraints = "$src1 = $dst" in
6735 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6738 let Predicates = [UseSSE41] in {
6739 // If we're inserting an element from a load or a null pshuf of a load,
6740 // fold the load into the insertps instruction.
6741 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd (v4f32
6742 (scalar_to_vector (loadf32 addr:$src2))), (i8 0)),
6744 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6745 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd
6746 (loadv4f32 addr:$src2), (i8 0)), imm:$src3)),
6747 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6750 let Predicates = [UseAVX] in {
6751 // If we're inserting an element from a vbroadcast of a load, fold the
6752 // load into the X86insertps instruction.
6753 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6754 (X86VBroadcast (loadf32 addr:$src2)), imm:$src3)),
6755 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6756 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6757 (X86VBroadcast (loadv4f32 addr:$src2)), imm:$src3)),
6758 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6761 //===----------------------------------------------------------------------===//
6762 // SSE4.1 - Round Instructions
6763 //===----------------------------------------------------------------------===//
6765 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6766 X86MemOperand x86memop, RegisterClass RC,
6767 PatFrag mem_frag32, PatFrag mem_frag64,
6768 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6769 let ExeDomain = SSEPackedSingle in {
6770 // Intrinsic operation, reg.
6771 // Vector intrinsic operation, reg
6772 def PSr : SS4AIi8<opcps, MRMSrcReg,
6773 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6774 !strconcat(OpcodeStr,
6775 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6776 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6777 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6779 // Vector intrinsic operation, mem
6780 def PSm : SS4AIi8<opcps, MRMSrcMem,
6781 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6782 !strconcat(OpcodeStr,
6783 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6785 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6786 IIC_SSE_ROUNDPS_MEM>, Sched<[WriteFAddLd]>;
6787 } // ExeDomain = SSEPackedSingle
6789 let ExeDomain = SSEPackedDouble in {
6790 // Vector intrinsic operation, reg
6791 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6792 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6793 !strconcat(OpcodeStr,
6794 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6795 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6796 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6798 // Vector intrinsic operation, mem
6799 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6800 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6801 !strconcat(OpcodeStr,
6802 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6804 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6805 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAddLd]>;
6806 } // ExeDomain = SSEPackedDouble
6809 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6812 Intrinsic F64Int, bit Is2Addr = 1> {
6813 let ExeDomain = GenericDomain in {
6815 let hasSideEffects = 0 in
6816 def SSr : SS4AIi8<opcss, MRMSrcReg,
6817 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6819 !strconcat(OpcodeStr,
6820 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6821 !strconcat(OpcodeStr,
6822 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6823 []>, Sched<[WriteFAdd]>;
6825 // Intrinsic operation, reg.
6826 let isCodeGenOnly = 1 in
6827 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6828 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6830 !strconcat(OpcodeStr,
6831 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6832 !strconcat(OpcodeStr,
6833 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6834 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6837 // Intrinsic operation, mem.
6838 def SSm : SS4AIi8<opcss, MRMSrcMem,
6839 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6841 !strconcat(OpcodeStr,
6842 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6843 !strconcat(OpcodeStr,
6844 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6846 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6847 Sched<[WriteFAddLd, ReadAfterLd]>;
6850 let hasSideEffects = 0 in
6851 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6852 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6854 !strconcat(OpcodeStr,
6855 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6856 !strconcat(OpcodeStr,
6857 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6858 []>, Sched<[WriteFAdd]>;
6860 // Intrinsic operation, reg.
6861 let isCodeGenOnly = 1 in
6862 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6863 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6865 !strconcat(OpcodeStr,
6866 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6867 !strconcat(OpcodeStr,
6868 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6869 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6872 // Intrinsic operation, mem.
6873 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6874 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6876 !strconcat(OpcodeStr,
6877 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6878 !strconcat(OpcodeStr,
6879 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6881 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6882 Sched<[WriteFAddLd, ReadAfterLd]>;
6883 } // ExeDomain = GenericDomain
6886 // FP round - roundss, roundps, roundsd, roundpd
6887 let Predicates = [HasAVX] in {
6889 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6890 loadv4f32, loadv2f64,
6891 int_x86_sse41_round_ps,
6892 int_x86_sse41_round_pd>, VEX;
6893 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6894 loadv8f32, loadv4f64,
6895 int_x86_avx_round_ps_256,
6896 int_x86_avx_round_pd_256>, VEX, VEX_L;
6897 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6898 int_x86_sse41_round_ss,
6899 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6901 def : Pat<(ffloor FR32:$src),
6902 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6903 def : Pat<(f64 (ffloor FR64:$src)),
6904 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6905 def : Pat<(f32 (fnearbyint FR32:$src)),
6906 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6907 def : Pat<(f64 (fnearbyint FR64:$src)),
6908 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6909 def : Pat<(f32 (fceil FR32:$src)),
6910 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6911 def : Pat<(f64 (fceil FR64:$src)),
6912 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6913 def : Pat<(f32 (frint FR32:$src)),
6914 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6915 def : Pat<(f64 (frint FR64:$src)),
6916 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6917 def : Pat<(f32 (ftrunc FR32:$src)),
6918 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6919 def : Pat<(f64 (ftrunc FR64:$src)),
6920 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6922 def : Pat<(v4f32 (ffloor VR128:$src)),
6923 (VROUNDPSr VR128:$src, (i32 0x1))>;
6924 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6925 (VROUNDPSr VR128:$src, (i32 0xC))>;
6926 def : Pat<(v4f32 (fceil VR128:$src)),
6927 (VROUNDPSr VR128:$src, (i32 0x2))>;
6928 def : Pat<(v4f32 (frint VR128:$src)),
6929 (VROUNDPSr VR128:$src, (i32 0x4))>;
6930 def : Pat<(v4f32 (ftrunc VR128:$src)),
6931 (VROUNDPSr VR128:$src, (i32 0x3))>;
6933 def : Pat<(v2f64 (ffloor VR128:$src)),
6934 (VROUNDPDr VR128:$src, (i32 0x1))>;
6935 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6936 (VROUNDPDr VR128:$src, (i32 0xC))>;
6937 def : Pat<(v2f64 (fceil VR128:$src)),
6938 (VROUNDPDr VR128:$src, (i32 0x2))>;
6939 def : Pat<(v2f64 (frint VR128:$src)),
6940 (VROUNDPDr VR128:$src, (i32 0x4))>;
6941 def : Pat<(v2f64 (ftrunc VR128:$src)),
6942 (VROUNDPDr VR128:$src, (i32 0x3))>;
6944 def : Pat<(v8f32 (ffloor VR256:$src)),
6945 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6946 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6947 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6948 def : Pat<(v8f32 (fceil VR256:$src)),
6949 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6950 def : Pat<(v8f32 (frint VR256:$src)),
6951 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6952 def : Pat<(v8f32 (ftrunc VR256:$src)),
6953 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6955 def : Pat<(v4f64 (ffloor VR256:$src)),
6956 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6957 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6958 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6959 def : Pat<(v4f64 (fceil VR256:$src)),
6960 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6961 def : Pat<(v4f64 (frint VR256:$src)),
6962 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6963 def : Pat<(v4f64 (ftrunc VR256:$src)),
6964 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6967 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6968 memopv4f32, memopv2f64,
6969 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6970 let Constraints = "$src1 = $dst" in
6971 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6972 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6974 let Predicates = [UseSSE41] in {
6975 def : Pat<(ffloor FR32:$src),
6976 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6977 def : Pat<(f64 (ffloor FR64:$src)),
6978 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6979 def : Pat<(f32 (fnearbyint FR32:$src)),
6980 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6981 def : Pat<(f64 (fnearbyint FR64:$src)),
6982 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6983 def : Pat<(f32 (fceil FR32:$src)),
6984 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6985 def : Pat<(f64 (fceil FR64:$src)),
6986 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6987 def : Pat<(f32 (frint FR32:$src)),
6988 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6989 def : Pat<(f64 (frint FR64:$src)),
6990 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6991 def : Pat<(f32 (ftrunc FR32:$src)),
6992 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6993 def : Pat<(f64 (ftrunc FR64:$src)),
6994 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6996 def : Pat<(v4f32 (ffloor VR128:$src)),
6997 (ROUNDPSr VR128:$src, (i32 0x1))>;
6998 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6999 (ROUNDPSr VR128:$src, (i32 0xC))>;
7000 def : Pat<(v4f32 (fceil VR128:$src)),
7001 (ROUNDPSr VR128:$src, (i32 0x2))>;
7002 def : Pat<(v4f32 (frint VR128:$src)),
7003 (ROUNDPSr VR128:$src, (i32 0x4))>;
7004 def : Pat<(v4f32 (ftrunc VR128:$src)),
7005 (ROUNDPSr VR128:$src, (i32 0x3))>;
7007 def : Pat<(v2f64 (ffloor VR128:$src)),
7008 (ROUNDPDr VR128:$src, (i32 0x1))>;
7009 def : Pat<(v2f64 (fnearbyint VR128:$src)),
7010 (ROUNDPDr VR128:$src, (i32 0xC))>;
7011 def : Pat<(v2f64 (fceil VR128:$src)),
7012 (ROUNDPDr VR128:$src, (i32 0x2))>;
7013 def : Pat<(v2f64 (frint VR128:$src)),
7014 (ROUNDPDr VR128:$src, (i32 0x4))>;
7015 def : Pat<(v2f64 (ftrunc VR128:$src)),
7016 (ROUNDPDr VR128:$src, (i32 0x3))>;
7019 //===----------------------------------------------------------------------===//
7020 // SSE4.1 - Packed Bit Test
7021 //===----------------------------------------------------------------------===//
7023 // ptest instruction we'll lower to this in X86ISelLowering primarily from
7024 // the intel intrinsic that corresponds to this.
7025 let Defs = [EFLAGS], Predicates = [HasAVX] in {
7026 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
7027 "vptest\t{$src2, $src1|$src1, $src2}",
7028 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
7029 Sched<[WriteVecLogic]>, VEX;
7030 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
7031 "vptest\t{$src2, $src1|$src1, $src2}",
7032 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
7033 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
7035 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
7036 "vptest\t{$src2, $src1|$src1, $src2}",
7037 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
7038 Sched<[WriteVecLogic]>, VEX, VEX_L;
7039 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
7040 "vptest\t{$src2, $src1|$src1, $src2}",
7041 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
7042 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX, VEX_L;
7045 let Defs = [EFLAGS] in {
7046 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
7047 "ptest\t{$src2, $src1|$src1, $src2}",
7048 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
7049 Sched<[WriteVecLogic]>;
7050 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
7051 "ptest\t{$src2, $src1|$src1, $src2}",
7052 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
7053 Sched<[WriteVecLogicLd, ReadAfterLd]>;
7056 // The bit test instructions below are AVX only
7057 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
7058 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
7059 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
7060 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
7061 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>,
7062 Sched<[WriteVecLogic]>, VEX;
7063 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
7064 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
7065 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
7066 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
7069 let Defs = [EFLAGS], Predicates = [HasAVX] in {
7070 let ExeDomain = SSEPackedSingle in {
7071 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
7072 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
7075 let ExeDomain = SSEPackedDouble in {
7076 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
7077 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
7082 //===----------------------------------------------------------------------===//
7083 // SSE4.1 - Misc Instructions
7084 //===----------------------------------------------------------------------===//
7086 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
7087 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
7088 "popcnt{w}\t{$src, $dst|$dst, $src}",
7089 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
7090 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
7092 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
7093 "popcnt{w}\t{$src, $dst|$dst, $src}",
7094 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
7095 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
7096 Sched<[WriteFAddLd]>, OpSize16, XS;
7098 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
7099 "popcnt{l}\t{$src, $dst|$dst, $src}",
7100 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
7101 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
7104 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
7105 "popcnt{l}\t{$src, $dst|$dst, $src}",
7106 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
7107 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
7108 Sched<[WriteFAddLd]>, OpSize32, XS;
7110 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
7111 "popcnt{q}\t{$src, $dst|$dst, $src}",
7112 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
7113 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>, XS;
7114 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
7115 "popcnt{q}\t{$src, $dst|$dst, $src}",
7116 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
7117 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
7118 Sched<[WriteFAddLd]>, XS;
7123 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
7124 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
7126 X86FoldableSchedWrite Sched> {
7127 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7129 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7130 [(set VR128:$dst, (IntId128 VR128:$src))]>,
7132 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7134 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7136 (IntId128 (bitconvert (memopv2i64 addr:$src))))]>,
7137 Sched<[Sched.Folded]>;
7140 // PHMIN has the same profile as PSAD, thus we use the same scheduling
7141 // model, although the naming is misleading.
7142 let Predicates = [HasAVX] in
7143 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
7144 int_x86_sse41_phminposuw,
7146 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
7147 int_x86_sse41_phminposuw,
7150 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
7151 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
7152 Intrinsic IntId128, bit Is2Addr = 1,
7153 OpndItins itins = DEFAULT_ITINS> {
7154 let isCommutable = 1 in
7155 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7156 (ins VR128:$src1, VR128:$src2),
7158 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7159 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7160 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))],
7161 itins.rr>, Sched<[itins.Sched]>;
7162 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7163 (ins VR128:$src1, i128mem:$src2),
7165 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7166 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7168 (IntId128 VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))],
7169 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7172 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
7173 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
7175 X86FoldableSchedWrite Sched> {
7176 let isCommutable = 1 in
7177 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
7178 (ins VR256:$src1, VR256:$src2),
7179 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7180 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
7182 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
7183 (ins VR256:$src1, i256mem:$src2),
7184 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7186 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
7187 Sched<[Sched.Folded, ReadAfterLd]>;
7191 /// SS48I_binop_rm - Simple SSE41 binary operator.
7192 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7193 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7194 X86MemOperand x86memop, bit Is2Addr = 1,
7195 OpndItins itins = SSE_INTALU_ITINS_P> {
7196 let isCommutable = 1 in
7197 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
7198 (ins RC:$src1, RC:$src2),
7200 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7201 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7202 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
7203 Sched<[itins.Sched]>;
7204 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
7205 (ins RC:$src1, x86memop:$src2),
7207 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7208 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7210 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>,
7211 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7214 /// SS48I_binop_rm2 - Simple SSE41 binary operator with different src and dst
7216 multiclass SS48I_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
7217 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
7218 PatFrag memop_frag, X86MemOperand x86memop,
7220 bit IsCommutable = 0, bit Is2Addr = 1> {
7221 let isCommutable = IsCommutable in
7222 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
7223 (ins RC:$src1, RC:$src2),
7225 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7226 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7227 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
7228 Sched<[itins.Sched]>;
7229 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
7230 (ins RC:$src1, x86memop:$src2),
7232 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7233 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7234 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
7235 (bitconvert (memop_frag addr:$src2)))))]>,
7236 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7239 let Predicates = [HasAVX] in {
7240 let isCommutable = 0 in
7241 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
7242 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7244 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
7245 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7247 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
7248 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7250 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
7251 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7253 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
7254 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7256 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
7257 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7259 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
7260 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7262 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
7263 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7265 defm VPMULDQ : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v2i64, v4i32,
7266 VR128, loadv2i64, i128mem,
7267 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
7270 let Predicates = [HasAVX2] in {
7271 let isCommutable = 0 in
7272 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
7273 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7275 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
7276 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7278 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
7279 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7281 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
7282 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7284 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
7285 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7287 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
7288 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7290 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
7291 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7293 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
7294 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7296 defm VPMULDQY : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v4i64, v8i32,
7297 VR256, loadv4i64, i256mem,
7298 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
7301 let Constraints = "$src1 = $dst" in {
7302 let isCommutable = 0 in
7303 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
7304 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7305 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
7306 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7307 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
7308 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7309 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
7310 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7311 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
7312 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7313 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
7314 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7315 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
7316 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7317 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
7318 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7319 defm PMULDQ : SS48I_binop_rm2<0x28, "pmuldq", X86pmuldq, v2i64, v4i32,
7320 VR128, memopv2i64, i128mem,
7321 SSE_INTMUL_ITINS_P, 1>;
7324 let Predicates = [HasAVX] in {
7325 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
7326 memopv2i64, i128mem, 0, SSE_PMULLD_ITINS>,
7328 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
7329 memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7332 let Predicates = [HasAVX2] in {
7333 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
7334 memopv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
7336 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
7337 memopv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7341 let Constraints = "$src1 = $dst" in {
7342 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
7343 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
7344 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
7345 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
7348 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
7349 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
7350 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7351 X86MemOperand x86memop, bit Is2Addr = 1,
7352 OpndItins itins = DEFAULT_ITINS> {
7353 let isCommutable = 1 in
7354 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
7355 (ins RC:$src1, RC:$src2, i8imm:$src3),
7357 !strconcat(OpcodeStr,
7358 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7359 !strconcat(OpcodeStr,
7360 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7361 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
7362 Sched<[itins.Sched]>;
7363 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
7364 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
7366 !strconcat(OpcodeStr,
7367 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7368 !strconcat(OpcodeStr,
7369 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7372 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
7373 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7376 let Predicates = [HasAVX] in {
7377 let isCommutable = 0 in {
7378 let ExeDomain = SSEPackedSingle in {
7379 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
7380 VR128, loadv4f32, f128mem, 0,
7381 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7382 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
7383 int_x86_avx_blend_ps_256, VR256, loadv8f32,
7384 f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,
7387 let ExeDomain = SSEPackedDouble in {
7388 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
7389 VR128, loadv2f64, f128mem, 0,
7390 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7391 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
7392 int_x86_avx_blend_pd_256,VR256, loadv4f64,
7393 f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,
7396 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
7397 VR128, loadv2i64, i128mem, 0,
7398 DEFAULT_ITINS_BLENDSCHED>, VEX_4V;
7399 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
7400 VR128, loadv2i64, i128mem, 0,
7401 DEFAULT_ITINS_MPSADSCHED>, VEX_4V;
7403 let ExeDomain = SSEPackedSingle in
7404 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
7405 VR128, loadv4f32, f128mem, 0,
7406 SSE_DPPS_ITINS>, VEX_4V;
7407 let ExeDomain = SSEPackedDouble in
7408 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
7409 VR128, loadv2f64, f128mem, 0,
7410 SSE_DPPS_ITINS>, VEX_4V;
7411 let ExeDomain = SSEPackedSingle in
7412 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
7413 VR256, loadv8f32, i256mem, 0,
7414 SSE_DPPS_ITINS>, VEX_4V, VEX_L;
7417 let Predicates = [HasAVX2] in {
7418 let isCommutable = 0 in {
7419 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
7420 VR256, loadv4i64, i256mem, 0,
7421 DEFAULT_ITINS_BLENDSCHED>, VEX_4V, VEX_L;
7422 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
7423 VR256, loadv4i64, i256mem, 0,
7424 DEFAULT_ITINS_MPSADSCHED>, VEX_4V, VEX_L;
7428 let Constraints = "$src1 = $dst" in {
7429 let isCommutable = 0 in {
7430 let ExeDomain = SSEPackedSingle in
7431 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
7432 VR128, memopv4f32, f128mem,
7433 1, SSE_INTALU_ITINS_FBLEND_P>;
7434 let ExeDomain = SSEPackedDouble in
7435 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
7436 VR128, memopv2f64, f128mem,
7437 1, SSE_INTALU_ITINS_FBLEND_P>;
7438 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
7439 VR128, memopv2i64, i128mem,
7440 1, SSE_INTALU_ITINS_BLEND_P>;
7441 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7442 VR128, memopv2i64, i128mem,
7443 1, SSE_MPSADBW_ITINS>;
7445 let ExeDomain = SSEPackedSingle in
7446 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7447 VR128, memopv4f32, f128mem, 1,
7449 let ExeDomain = SSEPackedDouble in
7450 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7451 VR128, memopv2f64, f128mem, 1,
7455 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7456 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7457 RegisterClass RC, X86MemOperand x86memop,
7458 PatFrag mem_frag, Intrinsic IntId,
7459 X86FoldableSchedWrite Sched> {
7460 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7461 (ins RC:$src1, RC:$src2, RC:$src3),
7462 !strconcat(OpcodeStr,
7463 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7464 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7465 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7468 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7469 (ins RC:$src1, x86memop:$src2, RC:$src3),
7470 !strconcat(OpcodeStr,
7471 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7473 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7475 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7476 Sched<[Sched.Folded, ReadAfterLd]>;
7479 let Predicates = [HasAVX] in {
7480 let ExeDomain = SSEPackedDouble in {
7481 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7482 loadv2f64, int_x86_sse41_blendvpd,
7484 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7485 loadv4f64, int_x86_avx_blendv_pd_256,
7486 WriteFVarBlend>, VEX_L;
7487 } // ExeDomain = SSEPackedDouble
7488 let ExeDomain = SSEPackedSingle in {
7489 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7490 loadv4f32, int_x86_sse41_blendvps,
7492 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7493 loadv8f32, int_x86_avx_blendv_ps_256,
7494 WriteFVarBlend>, VEX_L;
7495 } // ExeDomain = SSEPackedSingle
7496 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7497 loadv2i64, int_x86_sse41_pblendvb,
7501 let Predicates = [HasAVX2] in {
7502 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7503 loadv4i64, int_x86_avx2_pblendvb,
7504 WriteVarBlend>, VEX_L;
7507 let Predicates = [HasAVX] in {
7508 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7509 (v16i8 VR128:$src2))),
7510 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7511 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7512 (v4i32 VR128:$src2))),
7513 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7514 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7515 (v4f32 VR128:$src2))),
7516 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7517 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7518 (v2i64 VR128:$src2))),
7519 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7520 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7521 (v2f64 VR128:$src2))),
7522 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7523 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7524 (v8i32 VR256:$src2))),
7525 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7526 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7527 (v8f32 VR256:$src2))),
7528 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7529 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7530 (v4i64 VR256:$src2))),
7531 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7532 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7533 (v4f64 VR256:$src2))),
7534 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7536 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
7538 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7539 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
7541 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7543 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7545 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7546 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7548 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7549 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7551 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7554 let Predicates = [HasAVX2] in {
7555 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7556 (v32i8 VR256:$src2))),
7557 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7558 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
7560 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7563 /// SS41I_ternary_int - SSE 4.1 ternary operator
7564 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7565 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7566 X86MemOperand x86memop, Intrinsic IntId,
7567 OpndItins itins = DEFAULT_ITINS> {
7568 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7569 (ins VR128:$src1, VR128:$src2),
7570 !strconcat(OpcodeStr,
7571 "\t{$src2, $dst|$dst, $src2}"),
7572 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7573 itins.rr>, Sched<[itins.Sched]>;
7575 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7576 (ins VR128:$src1, x86memop:$src2),
7577 !strconcat(OpcodeStr,
7578 "\t{$src2, $dst|$dst, $src2}"),
7581 (bitconvert (mem_frag addr:$src2)), XMM0))],
7582 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7586 let ExeDomain = SSEPackedDouble in
7587 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7588 int_x86_sse41_blendvpd,
7589 DEFAULT_ITINS_FBLENDSCHED>;
7590 let ExeDomain = SSEPackedSingle in
7591 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7592 int_x86_sse41_blendvps,
7593 DEFAULT_ITINS_FBLENDSCHED>;
7594 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7595 int_x86_sse41_pblendvb,
7596 DEFAULT_ITINS_VARBLENDSCHED>;
7598 // Aliases with the implicit xmm0 argument
7599 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7600 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7601 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7602 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7603 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7604 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7605 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7606 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7607 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7608 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7609 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7610 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7612 let Predicates = [UseSSE41] in {
7613 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7614 (v16i8 VR128:$src2))),
7615 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7616 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7617 (v4i32 VR128:$src2))),
7618 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7619 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7620 (v4f32 VR128:$src2))),
7621 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7622 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7623 (v2i64 VR128:$src2))),
7624 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7625 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7626 (v2f64 VR128:$src2))),
7627 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7629 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7631 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7632 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7634 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7635 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7637 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7641 let SchedRW = [WriteLoad] in {
7642 let Predicates = [HasAVX] in
7643 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7644 "vmovntdqa\t{$src, $dst|$dst, $src}",
7645 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7647 let Predicates = [HasAVX2] in
7648 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7649 "vmovntdqa\t{$src, $dst|$dst, $src}",
7650 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7652 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7653 "movntdqa\t{$src, $dst|$dst, $src}",
7654 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
7657 //===----------------------------------------------------------------------===//
7658 // SSE4.2 - Compare Instructions
7659 //===----------------------------------------------------------------------===//
7661 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7662 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7663 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7664 X86MemOperand x86memop, bit Is2Addr = 1> {
7665 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7666 (ins RC:$src1, RC:$src2),
7668 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7669 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7670 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
7671 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7672 (ins RC:$src1, x86memop:$src2),
7674 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7675 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7677 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>;
7680 let Predicates = [HasAVX] in
7681 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7682 loadv2i64, i128mem, 0>, VEX_4V;
7684 let Predicates = [HasAVX2] in
7685 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7686 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7688 let Constraints = "$src1 = $dst" in
7689 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7690 memopv2i64, i128mem>;
7692 //===----------------------------------------------------------------------===//
7693 // SSE4.2 - String/text Processing Instructions
7694 //===----------------------------------------------------------------------===//
7696 // Packed Compare Implicit Length Strings, Return Mask
7697 multiclass pseudo_pcmpistrm<string asm> {
7698 def REG : PseudoI<(outs VR128:$dst),
7699 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7700 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7702 def MEM : PseudoI<(outs VR128:$dst),
7703 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7704 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7705 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7708 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7709 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
7710 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
7713 multiclass pcmpistrm_SS42AI<string asm> {
7714 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7715 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7716 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7717 []>, Sched<[WritePCmpIStrM]>;
7719 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7720 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7721 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7722 []>, Sched<[WritePCmpIStrMLd, ReadAfterLd]>;
7725 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
7726 let Predicates = [HasAVX] in
7727 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7728 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7731 // Packed Compare Explicit Length Strings, Return Mask
7732 multiclass pseudo_pcmpestrm<string asm> {
7733 def REG : PseudoI<(outs VR128:$dst),
7734 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7735 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7736 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7737 def MEM : PseudoI<(outs VR128:$dst),
7738 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7739 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7740 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
7743 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7744 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
7745 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
7748 multiclass SS42AI_pcmpestrm<string asm> {
7749 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7750 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7751 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7752 []>, Sched<[WritePCmpEStrM]>;
7754 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7755 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7756 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7757 []>, Sched<[WritePCmpEStrMLd, ReadAfterLd]>;
7760 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7761 let Predicates = [HasAVX] in
7762 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7763 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7766 // Packed Compare Implicit Length Strings, Return Index
7767 multiclass pseudo_pcmpistri<string asm> {
7768 def REG : PseudoI<(outs GR32:$dst),
7769 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7770 [(set GR32:$dst, EFLAGS,
7771 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7772 def MEM : PseudoI<(outs GR32:$dst),
7773 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7774 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7775 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7778 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7779 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
7780 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
7783 multiclass SS42AI_pcmpistri<string asm> {
7784 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7785 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7786 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7787 []>, Sched<[WritePCmpIStrI]>;
7789 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7790 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7791 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7792 []>, Sched<[WritePCmpIStrILd, ReadAfterLd]>;
7795 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
7796 let Predicates = [HasAVX] in
7797 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7798 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7801 // Packed Compare Explicit Length Strings, Return Index
7802 multiclass pseudo_pcmpestri<string asm> {
7803 def REG : PseudoI<(outs GR32:$dst),
7804 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7805 [(set GR32:$dst, EFLAGS,
7806 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7807 def MEM : PseudoI<(outs GR32:$dst),
7808 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7809 [(set GR32:$dst, EFLAGS,
7810 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
7814 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7815 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
7816 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
7819 multiclass SS42AI_pcmpestri<string asm> {
7820 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7821 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7822 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7823 []>, Sched<[WritePCmpEStrI]>;
7825 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7826 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7827 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7828 []>, Sched<[WritePCmpEStrILd, ReadAfterLd]>;
7831 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7832 let Predicates = [HasAVX] in
7833 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7834 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7837 //===----------------------------------------------------------------------===//
7838 // SSE4.2 - CRC Instructions
7839 //===----------------------------------------------------------------------===//
7841 // No CRC instructions have AVX equivalents
7843 // crc intrinsic instruction
7844 // This set of instructions are only rm, the only difference is the size
7846 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7847 RegisterClass RCIn, SDPatternOperator Int> :
7848 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7849 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7850 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>,
7853 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7854 X86MemOperand x86memop, SDPatternOperator Int> :
7855 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7856 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7857 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7858 IIC_CRC32_MEM>, Sched<[WriteFAddLd, ReadAfterLd]>;
7860 let Constraints = "$src1 = $dst" in {
7861 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7862 int_x86_sse42_crc32_32_8>;
7863 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7864 int_x86_sse42_crc32_32_8>;
7865 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7866 int_x86_sse42_crc32_32_16>, OpSize16;
7867 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7868 int_x86_sse42_crc32_32_16>, OpSize16;
7869 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7870 int_x86_sse42_crc32_32_32>, OpSize32;
7871 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7872 int_x86_sse42_crc32_32_32>, OpSize32;
7873 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7874 int_x86_sse42_crc32_64_64>, REX_W;
7875 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7876 int_x86_sse42_crc32_64_64>, REX_W;
7877 let hasSideEffects = 0 in {
7879 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7881 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7886 //===----------------------------------------------------------------------===//
7887 // SHA-NI Instructions
7888 //===----------------------------------------------------------------------===//
7890 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7892 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7893 (ins VR128:$src1, VR128:$src2),
7894 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7896 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7897 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7899 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7900 (ins VR128:$src1, i128mem:$src2),
7901 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7903 (set VR128:$dst, (IntId VR128:$src1,
7904 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7905 (set VR128:$dst, (IntId VR128:$src1,
7906 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7909 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7910 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7911 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7912 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7914 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7915 (i8 imm:$src3)))]>, TA;
7916 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7917 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7918 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7920 (int_x86_sha1rnds4 VR128:$src1,
7921 (bc_v4i32 (memopv2i64 addr:$src2)),
7922 (i8 imm:$src3)))]>, TA;
7924 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7925 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7926 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7929 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7931 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7932 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7935 // Aliases with explicit %xmm0
7936 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7937 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7938 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7939 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7941 //===----------------------------------------------------------------------===//
7942 // AES-NI Instructions
7943 //===----------------------------------------------------------------------===//
7945 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7946 Intrinsic IntId128, bit Is2Addr = 1> {
7947 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7948 (ins VR128:$src1, VR128:$src2),
7950 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7951 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7952 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7953 Sched<[WriteAESDecEnc]>;
7954 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7955 (ins VR128:$src1, i128mem:$src2),
7957 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7958 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7960 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>,
7961 Sched<[WriteAESDecEncLd, ReadAfterLd]>;
7964 // Perform One Round of an AES Encryption/Decryption Flow
7965 let Predicates = [HasAVX, HasAES] in {
7966 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7967 int_x86_aesni_aesenc, 0>, VEX_4V;
7968 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7969 int_x86_aesni_aesenclast, 0>, VEX_4V;
7970 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7971 int_x86_aesni_aesdec, 0>, VEX_4V;
7972 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7973 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7976 let Constraints = "$src1 = $dst" in {
7977 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7978 int_x86_aesni_aesenc>;
7979 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7980 int_x86_aesni_aesenclast>;
7981 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7982 int_x86_aesni_aesdec>;
7983 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7984 int_x86_aesni_aesdeclast>;
7987 // Perform the AES InvMixColumn Transformation
7988 let Predicates = [HasAVX, HasAES] in {
7989 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7991 "vaesimc\t{$src1, $dst|$dst, $src1}",
7993 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>,
7995 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7996 (ins i128mem:$src1),
7997 "vaesimc\t{$src1, $dst|$dst, $src1}",
7998 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7999 Sched<[WriteAESIMCLd]>, VEX;
8001 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
8003 "aesimc\t{$src1, $dst|$dst, $src1}",
8005 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>;
8006 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
8007 (ins i128mem:$src1),
8008 "aesimc\t{$src1, $dst|$dst, $src1}",
8009 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
8010 Sched<[WriteAESIMCLd]>;
8012 // AES Round Key Generation Assist
8013 let Predicates = [HasAVX, HasAES] in {
8014 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
8015 (ins VR128:$src1, i8imm:$src2),
8016 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8018 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
8019 Sched<[WriteAESKeyGen]>, VEX;
8020 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
8021 (ins i128mem:$src1, i8imm:$src2),
8022 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8024 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
8025 Sched<[WriteAESKeyGenLd]>, VEX;
8027 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
8028 (ins VR128:$src1, i8imm:$src2),
8029 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8031 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
8032 Sched<[WriteAESKeyGen]>;
8033 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
8034 (ins i128mem:$src1, i8imm:$src2),
8035 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8037 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
8038 Sched<[WriteAESKeyGenLd]>;
8040 //===----------------------------------------------------------------------===//
8041 // PCLMUL Instructions
8042 //===----------------------------------------------------------------------===//
8044 // AVX carry-less Multiplication instructions
8045 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
8046 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
8047 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8049 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>,
8050 Sched<[WriteCLMul]>;
8052 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
8053 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
8054 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8055 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
8056 (loadv2i64 addr:$src2), imm:$src3))]>,
8057 Sched<[WriteCLMulLd, ReadAfterLd]>;
8059 // Carry-less Multiplication instructions
8060 let Constraints = "$src1 = $dst" in {
8061 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
8062 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
8063 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
8065 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
8066 IIC_SSE_PCLMULQDQ_RR>, Sched<[WriteCLMul]>;
8068 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
8069 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
8070 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
8071 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
8072 (memopv2i64 addr:$src2), imm:$src3))],
8073 IIC_SSE_PCLMULQDQ_RM>,
8074 Sched<[WriteCLMulLd, ReadAfterLd]>;
8075 } // Constraints = "$src1 = $dst"
8078 multiclass pclmul_alias<string asm, int immop> {
8079 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
8080 (PCLMULQDQrr VR128:$dst, VR128:$src, immop), 0>;
8082 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
8083 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop), 0>;
8085 def : InstAlias<!strconcat("vpclmul", asm,
8086 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
8087 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop),
8090 def : InstAlias<!strconcat("vpclmul", asm,
8091 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
8092 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop),
8095 defm : pclmul_alias<"hqhq", 0x11>;
8096 defm : pclmul_alias<"hqlq", 0x01>;
8097 defm : pclmul_alias<"lqhq", 0x10>;
8098 defm : pclmul_alias<"lqlq", 0x00>;
8100 //===----------------------------------------------------------------------===//
8101 // SSE4A Instructions
8102 //===----------------------------------------------------------------------===//
8104 let Predicates = [HasSSE4A] in {
8106 let Constraints = "$src = $dst" in {
8107 def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst),
8108 (ins VR128:$src, i8imm:$len, i8imm:$idx),
8109 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
8110 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
8112 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
8113 (ins VR128:$src, VR128:$mask),
8114 "extrq\t{$mask, $src|$src, $mask}",
8115 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
8116 VR128:$mask))]>, PD;
8118 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
8119 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
8120 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
8121 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
8122 VR128:$src2, imm:$len, imm:$idx))]>, XD;
8123 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
8124 (ins VR128:$src, VR128:$mask),
8125 "insertq\t{$mask, $src|$src, $mask}",
8126 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
8127 VR128:$mask))]>, XD;
8130 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
8131 "movntss\t{$src, $dst|$dst, $src}",
8132 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
8134 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
8135 "movntsd\t{$src, $dst|$dst, $src}",
8136 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
8139 //===----------------------------------------------------------------------===//
8141 //===----------------------------------------------------------------------===//
8143 //===----------------------------------------------------------------------===//
8144 // VBROADCAST - Load from memory and broadcast to all elements of the
8145 // destination operand
8147 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
8148 X86MemOperand x86memop, Intrinsic Int, SchedWrite Sched> :
8149 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8150 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8151 [(set RC:$dst, (Int addr:$src))]>, Sched<[Sched]>, VEX;
8153 class avx_broadcast_no_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
8154 X86MemOperand x86memop, ValueType VT,
8155 PatFrag ld_frag, SchedWrite Sched> :
8156 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8157 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8158 [(set RC:$dst, (VT (X86VBroadcast (ld_frag addr:$src))))]>,
8159 Sched<[Sched]>, VEX {
8163 // AVX2 adds register forms
8164 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
8165 Intrinsic Int, SchedWrite Sched> :
8166 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8167 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8168 [(set RC:$dst, (Int VR128:$src))]>, Sched<[Sched]>, VEX;
8170 let ExeDomain = SSEPackedSingle in {
8171 def VBROADCASTSSrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR128,
8172 f32mem, v4f32, loadf32, WriteLoad>;
8173 def VBROADCASTSSYrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR256,
8174 f32mem, v8f32, loadf32,
8175 WriteFShuffleLd>, VEX_L;
8177 let ExeDomain = SSEPackedDouble in
8178 def VBROADCASTSDYrm : avx_broadcast_no_int<0x19, "vbroadcastsd", VR256, f64mem,
8179 v4f64, loadf64, WriteFShuffleLd>, VEX_L;
8180 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
8181 int_x86_avx_vbroadcastf128_pd_256,
8182 WriteFShuffleLd>, VEX_L;
8184 let ExeDomain = SSEPackedSingle in {
8185 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
8186 int_x86_avx2_vbroadcast_ss_ps,
8188 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
8189 int_x86_avx2_vbroadcast_ss_ps_256,
8190 WriteFShuffle256>, VEX_L;
8192 let ExeDomain = SSEPackedDouble in
8193 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
8194 int_x86_avx2_vbroadcast_sd_pd_256,
8195 WriteFShuffle256>, VEX_L;
8197 let Predicates = [HasAVX2] in
8198 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
8199 int_x86_avx2_vbroadcasti128, WriteLoad>,
8202 let Predicates = [HasAVX] in
8203 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
8204 (VBROADCASTF128 addr:$src)>;
8207 //===----------------------------------------------------------------------===//
8208 // VINSERTF128 - Insert packed floating-point values
8210 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
8211 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
8212 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8213 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8214 []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
8216 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
8217 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
8218 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8219 []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
8222 let Predicates = [HasAVX] in {
8223 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
8225 (VINSERTF128rr VR256:$src1, VR128:$src2,
8226 (INSERT_get_vinsert128_imm VR256:$ins))>;
8227 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
8229 (VINSERTF128rr VR256:$src1, VR128:$src2,
8230 (INSERT_get_vinsert128_imm VR256:$ins))>;
8232 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
8234 (VINSERTF128rm VR256:$src1, addr:$src2,
8235 (INSERT_get_vinsert128_imm VR256:$ins))>;
8236 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
8238 (VINSERTF128rm VR256:$src1, addr:$src2,
8239 (INSERT_get_vinsert128_imm VR256:$ins))>;
8242 let Predicates = [HasAVX1Only] in {
8243 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8245 (VINSERTF128rr VR256:$src1, VR128:$src2,
8246 (INSERT_get_vinsert128_imm VR256:$ins))>;
8247 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8249 (VINSERTF128rr VR256:$src1, VR128:$src2,
8250 (INSERT_get_vinsert128_imm VR256:$ins))>;
8251 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8253 (VINSERTF128rr VR256:$src1, VR128:$src2,
8254 (INSERT_get_vinsert128_imm VR256:$ins))>;
8255 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8257 (VINSERTF128rr VR256:$src1, VR128:$src2,
8258 (INSERT_get_vinsert128_imm VR256:$ins))>;
8260 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8262 (VINSERTF128rm VR256:$src1, addr:$src2,
8263 (INSERT_get_vinsert128_imm VR256:$ins))>;
8264 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8265 (bc_v4i32 (loadv2i64 addr:$src2)),
8267 (VINSERTF128rm VR256:$src1, addr:$src2,
8268 (INSERT_get_vinsert128_imm VR256:$ins))>;
8269 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8270 (bc_v16i8 (loadv2i64 addr:$src2)),
8272 (VINSERTF128rm VR256:$src1, addr:$src2,
8273 (INSERT_get_vinsert128_imm VR256:$ins))>;
8274 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8275 (bc_v8i16 (loadv2i64 addr:$src2)),
8277 (VINSERTF128rm VR256:$src1, addr:$src2,
8278 (INSERT_get_vinsert128_imm VR256:$ins))>;
8281 //===----------------------------------------------------------------------===//
8282 // VEXTRACTF128 - Extract packed floating-point values
8284 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
8285 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
8286 (ins VR256:$src1, i8imm:$src2),
8287 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8288 []>, Sched<[WriteFShuffle]>, VEX, VEX_L;
8290 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
8291 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
8292 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8293 []>, Sched<[WriteStore]>, VEX, VEX_L;
8297 let Predicates = [HasAVX] in {
8298 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8299 (v4f32 (VEXTRACTF128rr
8300 (v8f32 VR256:$src1),
8301 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8302 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8303 (v2f64 (VEXTRACTF128rr
8304 (v4f64 VR256:$src1),
8305 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8307 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
8308 (iPTR imm))), addr:$dst),
8309 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8310 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8311 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
8312 (iPTR imm))), addr:$dst),
8313 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8314 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8317 let Predicates = [HasAVX1Only] in {
8318 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8319 (v2i64 (VEXTRACTF128rr
8320 (v4i64 VR256:$src1),
8321 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8322 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8323 (v4i32 (VEXTRACTF128rr
8324 (v8i32 VR256:$src1),
8325 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8326 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8327 (v8i16 (VEXTRACTF128rr
8328 (v16i16 VR256:$src1),
8329 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8330 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8331 (v16i8 (VEXTRACTF128rr
8332 (v32i8 VR256:$src1),
8333 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8335 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8336 (iPTR imm))), addr:$dst),
8337 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8338 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8339 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8340 (iPTR imm))), addr:$dst),
8341 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8342 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8343 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8344 (iPTR imm))), addr:$dst),
8345 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8346 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8347 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8348 (iPTR imm))), addr:$dst),
8349 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8350 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8353 //===----------------------------------------------------------------------===//
8354 // VMASKMOV - Conditional SIMD Packed Loads and Stores
8356 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
8357 Intrinsic IntLd, Intrinsic IntLd256,
8358 Intrinsic IntSt, Intrinsic IntSt256> {
8359 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
8360 (ins VR128:$src1, f128mem:$src2),
8361 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8362 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
8364 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
8365 (ins VR256:$src1, f256mem:$src2),
8366 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8367 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8369 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
8370 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
8371 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8372 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8373 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
8374 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
8375 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8376 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8379 let ExeDomain = SSEPackedSingle in
8380 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
8381 int_x86_avx_maskload_ps,
8382 int_x86_avx_maskload_ps_256,
8383 int_x86_avx_maskstore_ps,
8384 int_x86_avx_maskstore_ps_256>;
8385 let ExeDomain = SSEPackedDouble in
8386 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
8387 int_x86_avx_maskload_pd,
8388 int_x86_avx_maskload_pd_256,
8389 int_x86_avx_maskstore_pd,
8390 int_x86_avx_maskstore_pd_256>;
8392 //===----------------------------------------------------------------------===//
8393 // VPERMIL - Permute Single and Double Floating-Point Values
8395 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
8396 RegisterClass RC, X86MemOperand x86memop_f,
8397 X86MemOperand x86memop_i, PatFrag i_frag,
8398 Intrinsic IntVar, ValueType vt> {
8399 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
8400 (ins RC:$src1, RC:$src2),
8401 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8402 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V,
8403 Sched<[WriteFShuffle]>;
8404 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
8405 (ins RC:$src1, x86memop_i:$src2),
8406 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8407 [(set RC:$dst, (IntVar RC:$src1,
8408 (bitconvert (i_frag addr:$src2))))]>, VEX_4V,
8409 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8411 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8412 (ins RC:$src1, i8imm:$src2),
8413 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8414 [(set RC:$dst, (vt (X86VPermilpi RC:$src1, (i8 imm:$src2))))]>, VEX,
8415 Sched<[WriteFShuffle]>;
8416 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
8417 (ins x86memop_f:$src1, i8imm:$src2),
8418 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8420 (vt (X86VPermilpi (memop addr:$src1), (i8 imm:$src2))))]>, VEX,
8421 Sched<[WriteFShuffleLd]>;
8424 let ExeDomain = SSEPackedSingle in {
8425 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
8426 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
8427 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
8428 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
8430 let ExeDomain = SSEPackedDouble in {
8431 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
8432 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
8433 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
8434 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
8437 let Predicates = [HasAVX] in {
8438 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (v8i32 VR256:$src2))),
8439 (VPERMILPSYrr VR256:$src1, VR256:$src2)>;
8440 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
8441 (VPERMILPSYrm VR256:$src1, addr:$src2)>;
8442 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (v4i64 VR256:$src2))),
8443 (VPERMILPDYrr VR256:$src1, VR256:$src2)>;
8444 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (loadv4i64 addr:$src2))),
8445 (VPERMILPDYrm VR256:$src1, addr:$src2)>;
8447 def : Pat<(v8i32 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8448 (VPERMILPSYri VR256:$src1, imm:$imm)>;
8449 def : Pat<(v4i64 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8450 (VPERMILPDYri VR256:$src1, imm:$imm)>;
8451 def : Pat<(v8i32 (X86VPermilpi (bc_v8i32 (loadv4i64 addr:$src1)),
8453 (VPERMILPSYmi addr:$src1, imm:$imm)>;
8454 def : Pat<(v4i64 (X86VPermilpi (loadv4i64 addr:$src1), (i8 imm:$imm))),
8455 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8457 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (v4i32 VR128:$src2))),
8458 (VPERMILPSrr VR128:$src1, VR128:$src2)>;
8459 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)))),
8460 (VPERMILPSrm VR128:$src1, addr:$src2)>;
8461 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (v2i64 VR128:$src2))),
8462 (VPERMILPDrr VR128:$src1, VR128:$src2)>;
8463 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (loadv2i64 addr:$src2))),
8464 (VPERMILPDrm VR128:$src1, addr:$src2)>;
8466 def : Pat<(v2i64 (X86VPermilpi VR128:$src1, (i8 imm:$imm))),
8467 (VPERMILPDri VR128:$src1, imm:$imm)>;
8468 def : Pat<(v2i64 (X86VPermilpi (loadv2i64 addr:$src1), (i8 imm:$imm))),
8469 (VPERMILPDmi addr:$src1, imm:$imm)>;
8472 //===----------------------------------------------------------------------===//
8473 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8475 let ExeDomain = SSEPackedSingle in {
8476 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8477 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8478 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8479 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8480 (i8 imm:$src3))))]>, VEX_4V, VEX_L,
8481 Sched<[WriteFShuffle]>;
8482 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8483 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8484 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8485 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8486 (i8 imm:$src3)))]>, VEX_4V, VEX_L,
8487 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8490 let Predicates = [HasAVX] in {
8491 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8492 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8493 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8494 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8495 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8498 let Predicates = [HasAVX1Only] in {
8499 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8500 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8501 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8502 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8503 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8504 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8505 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8506 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8508 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8509 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8510 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8511 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8512 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8513 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8514 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8515 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8516 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8517 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8518 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8519 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8522 //===----------------------------------------------------------------------===//
8523 // VZERO - Zero YMM registers
8525 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8526 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8527 // Zero All YMM registers
8528 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8529 [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, Requires<[HasAVX]>;
8531 // Zero Upper bits of YMM registers
8532 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8533 [(int_x86_avx_vzeroupper)]>, PS, VEX, Requires<[HasAVX]>;
8536 //===----------------------------------------------------------------------===//
8537 // Half precision conversion instructions
8538 //===----------------------------------------------------------------------===//
8539 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8540 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8541 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8542 [(set RC:$dst, (Int VR128:$src))]>,
8543 T8PD, VEX, Sched<[WriteCvtF2F]>;
8544 let neverHasSideEffects = 1, mayLoad = 1 in
8545 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8546 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX,
8547 Sched<[WriteCvtF2FLd]>;
8550 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8551 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8552 (ins RC:$src1, i32i8imm:$src2),
8553 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8554 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8555 TAPD, VEX, Sched<[WriteCvtF2F]>;
8556 let neverHasSideEffects = 1, mayStore = 1,
8557 SchedRW = [WriteCvtF2FLd, WriteRMW] in
8558 def mr : Ii8<0x1D, MRMDestMem, (outs),
8559 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
8560 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8564 let Predicates = [HasF16C] in {
8565 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8566 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8567 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8568 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8570 // Pattern match vcvtph2ps of a scalar i64 load.
8571 def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)),
8572 (VCVTPH2PSrm addr:$src)>;
8573 def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),
8574 (VCVTPH2PSrm addr:$src)>;
8577 // Patterns for matching conversions from float to half-float and vice versa.
8578 let Predicates = [HasF16C] in {
8579 def : Pat<(fp_to_f16 FR32:$src),
8580 (i16 (EXTRACT_SUBREG (VMOVPDI2DIrr (VCVTPS2PHrr
8581 (COPY_TO_REGCLASS FR32:$src, VR128), 0)), sub_16bit))>;
8583 def : Pat<(f16_to_fp GR16:$src),
8584 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8585 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128)), FR32)) >;
8587 def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32:$src))),
8588 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8589 (VCVTPS2PHrr (COPY_TO_REGCLASS FR32:$src, VR128), 0)), FR32)) >;
8592 //===----------------------------------------------------------------------===//
8593 // AVX2 Instructions
8594 //===----------------------------------------------------------------------===//
8596 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
8597 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
8598 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
8599 X86MemOperand x86memop> {
8600 let isCommutable = 1 in
8601 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8602 (ins RC:$src1, RC:$src2, i8imm:$src3),
8603 !strconcat(OpcodeStr,
8604 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8605 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
8606 Sched<[WriteBlend]>, VEX_4V;
8607 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8608 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
8609 !strconcat(OpcodeStr,
8610 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8613 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
8614 Sched<[WriteBlendLd, ReadAfterLd]>, VEX_4V;
8617 let isCommutable = 0 in {
8618 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
8619 VR128, loadv2i64, i128mem>;
8620 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
8621 VR256, loadv4i64, i256mem>, VEX_L;
8624 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
8626 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
8627 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
8629 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
8631 //===----------------------------------------------------------------------===//
8632 // VPBROADCAST - Load from memory and broadcast to all elements of the
8633 // destination operand
8635 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8636 X86MemOperand x86memop, PatFrag ld_frag,
8637 Intrinsic Int128, Intrinsic Int256> {
8638 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8639 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8640 [(set VR128:$dst, (Int128 VR128:$src))]>,
8641 Sched<[WriteShuffle]>, VEX;
8642 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8643 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8645 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>,
8646 Sched<[WriteLoad]>, VEX;
8647 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8648 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8649 [(set VR256:$dst, (Int256 VR128:$src))]>,
8650 Sched<[WriteShuffle256]>, VEX, VEX_L;
8651 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8652 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8654 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8655 Sched<[WriteLoad]>, VEX, VEX_L;
8658 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8659 int_x86_avx2_pbroadcastb_128,
8660 int_x86_avx2_pbroadcastb_256>;
8661 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8662 int_x86_avx2_pbroadcastw_128,
8663 int_x86_avx2_pbroadcastw_256>;
8664 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8665 int_x86_avx2_pbroadcastd_128,
8666 int_x86_avx2_pbroadcastd_256>;
8667 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8668 int_x86_avx2_pbroadcastq_128,
8669 int_x86_avx2_pbroadcastq_256>;
8671 let Predicates = [HasAVX2] in {
8672 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8673 (VPBROADCASTBrm addr:$src)>;
8674 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8675 (VPBROADCASTBYrm addr:$src)>;
8676 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8677 (VPBROADCASTWrm addr:$src)>;
8678 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8679 (VPBROADCASTWYrm addr:$src)>;
8680 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8681 (VPBROADCASTDrm addr:$src)>;
8682 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8683 (VPBROADCASTDYrm addr:$src)>;
8684 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8685 (VPBROADCASTQrm addr:$src)>;
8686 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8687 (VPBROADCASTQYrm addr:$src)>;
8689 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8690 (VPBROADCASTBrr VR128:$src)>;
8691 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8692 (VPBROADCASTBYrr VR128:$src)>;
8693 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8694 (VPBROADCASTWrr VR128:$src)>;
8695 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8696 (VPBROADCASTWYrr VR128:$src)>;
8697 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8698 (VPBROADCASTDrr VR128:$src)>;
8699 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8700 (VPBROADCASTDYrr VR128:$src)>;
8701 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8702 (VPBROADCASTQrr VR128:$src)>;
8703 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8704 (VPBROADCASTQYrr VR128:$src)>;
8705 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8706 (VBROADCASTSSrr VR128:$src)>;
8707 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8708 (VBROADCASTSSYrr VR128:$src)>;
8709 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8710 (VPBROADCASTQrr VR128:$src)>;
8711 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8712 (VBROADCASTSDYrr VR128:$src)>;
8714 // Provide aliases for broadcast from the same regitser class that
8715 // automatically does the extract.
8716 def : Pat<(v32i8 (X86VBroadcast (v32i8 VR256:$src))),
8717 (VPBROADCASTBYrr (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src),
8719 def : Pat<(v16i16 (X86VBroadcast (v16i16 VR256:$src))),
8720 (VPBROADCASTWYrr (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src),
8722 def : Pat<(v8i32 (X86VBroadcast (v8i32 VR256:$src))),
8723 (VPBROADCASTDYrr (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src),
8725 def : Pat<(v4i64 (X86VBroadcast (v4i64 VR256:$src))),
8726 (VPBROADCASTQYrr (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src),
8728 def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256:$src))),
8729 (VBROADCASTSSYrr (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src),
8731 def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256:$src))),
8732 (VBROADCASTSDYrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src),
8735 // Provide fallback in case the load node that is used in the patterns above
8736 // is used by additional users, which prevents the pattern selection.
8737 let AddedComplexity = 20 in {
8738 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8739 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8740 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8741 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8742 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8743 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8745 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8746 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8747 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8748 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8749 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8750 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8752 def : Pat<(v16i8 (X86VBroadcast GR8:$src)),
8753 (VPBROADCASTBrr (COPY_TO_REGCLASS
8754 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8756 def : Pat<(v32i8 (X86VBroadcast GR8:$src)),
8757 (VPBROADCASTBYrr (COPY_TO_REGCLASS
8758 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8761 def : Pat<(v8i16 (X86VBroadcast GR16:$src)),
8762 (VPBROADCASTWrr (COPY_TO_REGCLASS
8763 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8765 def : Pat<(v16i16 (X86VBroadcast GR16:$src)),
8766 (VPBROADCASTWYrr (COPY_TO_REGCLASS
8767 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8770 // The patterns for VPBROADCASTD are not needed because they would match
8771 // the exact same thing as VBROADCASTSS patterns.
8773 def : Pat<(v2i64 (X86VBroadcast GR64:$src)),
8774 (VPBROADCASTQrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8775 // The v4i64 pattern is not needed because VBROADCASTSDYrr already match.
8779 // AVX1 broadcast patterns
8780 let Predicates = [HasAVX1Only] in {
8781 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8782 (VBROADCASTSSYrm addr:$src)>;
8783 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8784 (VBROADCASTSDYrm addr:$src)>;
8785 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8786 (VBROADCASTSSrm addr:$src)>;
8789 let Predicates = [HasAVX] in {
8790 // Provide fallback in case the load node that is used in the patterns above
8791 // is used by additional users, which prevents the pattern selection.
8792 let AddedComplexity = 20 in {
8793 // 128bit broadcasts:
8794 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8795 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8796 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8797 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8798 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8799 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8800 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8801 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8802 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8803 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8805 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8806 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8807 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8808 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8809 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8810 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8811 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8812 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8813 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8814 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8817 def : Pat<(v2f64 (X86VBroadcast f64:$src)),
8818 (VMOVDDUPrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8821 //===----------------------------------------------------------------------===//
8822 // VPERM - Permute instructions
8825 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8826 ValueType OpVT, X86FoldableSchedWrite Sched> {
8827 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8828 (ins VR256:$src1, VR256:$src2),
8829 !strconcat(OpcodeStr,
8830 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8832 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8833 Sched<[Sched]>, VEX_4V, VEX_L;
8834 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8835 (ins VR256:$src1, i256mem:$src2),
8836 !strconcat(OpcodeStr,
8837 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8839 (OpVT (X86VPermv VR256:$src1,
8840 (bitconvert (mem_frag addr:$src2)))))]>,
8841 Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
8844 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteShuffle256>;
8845 let ExeDomain = SSEPackedSingle in
8846 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFShuffle256>;
8848 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8849 ValueType OpVT, X86FoldableSchedWrite Sched> {
8850 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8851 (ins VR256:$src1, i8imm:$src2),
8852 !strconcat(OpcodeStr,
8853 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8855 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8856 Sched<[Sched]>, VEX, VEX_L;
8857 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8858 (ins i256mem:$src1, i8imm:$src2),
8859 !strconcat(OpcodeStr,
8860 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8862 (OpVT (X86VPermi (mem_frag addr:$src1),
8863 (i8 imm:$src2))))]>,
8864 Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L;
8867 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64,
8868 WriteShuffle256>, VEX_W;
8869 let ExeDomain = SSEPackedDouble in
8870 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64,
8871 WriteFShuffle256>, VEX_W;
8873 //===----------------------------------------------------------------------===//
8874 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8876 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8877 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8878 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8879 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8880 (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>,
8882 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8883 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8884 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8885 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8887 Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8889 let Predicates = [HasAVX2] in {
8890 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8891 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8892 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8893 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8894 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8895 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8897 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8899 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8900 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8901 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8902 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8903 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8905 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8909 //===----------------------------------------------------------------------===//
8910 // VINSERTI128 - Insert packed integer values
8912 let neverHasSideEffects = 1 in {
8913 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8914 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8915 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8916 []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L;
8918 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8919 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
8920 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8921 []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8924 let Predicates = [HasAVX2] in {
8925 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8927 (VINSERTI128rr VR256:$src1, VR128:$src2,
8928 (INSERT_get_vinsert128_imm VR256:$ins))>;
8929 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8931 (VINSERTI128rr VR256:$src1, VR128:$src2,
8932 (INSERT_get_vinsert128_imm VR256:$ins))>;
8933 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8935 (VINSERTI128rr VR256:$src1, VR128:$src2,
8936 (INSERT_get_vinsert128_imm VR256:$ins))>;
8937 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8939 (VINSERTI128rr VR256:$src1, VR128:$src2,
8940 (INSERT_get_vinsert128_imm VR256:$ins))>;
8942 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8944 (VINSERTI128rm VR256:$src1, addr:$src2,
8945 (INSERT_get_vinsert128_imm VR256:$ins))>;
8946 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8947 (bc_v4i32 (loadv2i64 addr:$src2)),
8949 (VINSERTI128rm VR256:$src1, addr:$src2,
8950 (INSERT_get_vinsert128_imm VR256:$ins))>;
8951 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8952 (bc_v16i8 (loadv2i64 addr:$src2)),
8954 (VINSERTI128rm VR256:$src1, addr:$src2,
8955 (INSERT_get_vinsert128_imm VR256:$ins))>;
8956 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8957 (bc_v8i16 (loadv2i64 addr:$src2)),
8959 (VINSERTI128rm VR256:$src1, addr:$src2,
8960 (INSERT_get_vinsert128_imm VR256:$ins))>;
8963 //===----------------------------------------------------------------------===//
8964 // VEXTRACTI128 - Extract packed integer values
8966 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8967 (ins VR256:$src1, i8imm:$src2),
8968 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8970 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8971 Sched<[WriteShuffle256]>, VEX, VEX_L;
8972 let neverHasSideEffects = 1, mayStore = 1 in
8973 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8974 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
8975 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8976 Sched<[WriteStore]>, VEX, VEX_L;
8978 let Predicates = [HasAVX2] in {
8979 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8980 (v2i64 (VEXTRACTI128rr
8981 (v4i64 VR256:$src1),
8982 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8983 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8984 (v4i32 (VEXTRACTI128rr
8985 (v8i32 VR256:$src1),
8986 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8987 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8988 (v8i16 (VEXTRACTI128rr
8989 (v16i16 VR256:$src1),
8990 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8991 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8992 (v16i8 (VEXTRACTI128rr
8993 (v32i8 VR256:$src1),
8994 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8996 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8997 (iPTR imm))), addr:$dst),
8998 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8999 (EXTRACT_get_vextract128_imm VR128:$ext))>;
9000 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
9001 (iPTR imm))), addr:$dst),
9002 (VEXTRACTI128mr addr:$dst, VR256:$src1,
9003 (EXTRACT_get_vextract128_imm VR128:$ext))>;
9004 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
9005 (iPTR imm))), addr:$dst),
9006 (VEXTRACTI128mr addr:$dst, VR256:$src1,
9007 (EXTRACT_get_vextract128_imm VR128:$ext))>;
9008 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
9009 (iPTR imm))), addr:$dst),
9010 (VEXTRACTI128mr addr:$dst, VR256:$src1,
9011 (EXTRACT_get_vextract128_imm VR128:$ext))>;
9014 //===----------------------------------------------------------------------===//
9015 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
9017 multiclass avx2_pmovmask<string OpcodeStr,
9018 Intrinsic IntLd128, Intrinsic IntLd256,
9019 Intrinsic IntSt128, Intrinsic IntSt256> {
9020 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
9021 (ins VR128:$src1, i128mem:$src2),
9022 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9023 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
9024 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
9025 (ins VR256:$src1, i256mem:$src2),
9026 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9027 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
9029 def mr : AVX28I<0x8e, MRMDestMem, (outs),
9030 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
9031 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9032 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
9033 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
9034 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
9035 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9036 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
9039 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
9040 int_x86_avx2_maskload_d,
9041 int_x86_avx2_maskload_d_256,
9042 int_x86_avx2_maskstore_d,
9043 int_x86_avx2_maskstore_d_256>;
9044 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
9045 int_x86_avx2_maskload_q,
9046 int_x86_avx2_maskload_q_256,
9047 int_x86_avx2_maskstore_q,
9048 int_x86_avx2_maskstore_q_256>, VEX_W;
9051 //===----------------------------------------------------------------------===//
9052 // Variable Bit Shifts
9054 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
9055 ValueType vt128, ValueType vt256> {
9056 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
9057 (ins VR128:$src1, VR128:$src2),
9058 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9060 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
9061 VEX_4V, Sched<[WriteVarVecShift]>;
9062 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
9063 (ins VR128:$src1, i128mem:$src2),
9064 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9066 (vt128 (OpNode VR128:$src1,
9067 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
9068 VEX_4V, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
9069 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
9070 (ins VR256:$src1, VR256:$src2),
9071 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9073 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
9074 VEX_4V, VEX_L, Sched<[WriteVarVecShift]>;
9075 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
9076 (ins VR256:$src1, i256mem:$src2),
9077 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9079 (vt256 (OpNode VR256:$src1,
9080 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
9081 VEX_4V, VEX_L, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
9084 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
9085 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
9086 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
9087 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
9088 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
9090 //===----------------------------------------------------------------------===//
9091 // VGATHER - GATHER Operations
9092 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
9093 X86MemOperand memop128, X86MemOperand memop256> {
9094 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
9095 (ins VR128:$src1, memop128:$src2, VR128:$mask),
9096 !strconcat(OpcodeStr,
9097 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
9099 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
9100 (ins RC256:$src1, memop256:$src2, RC256:$mask),
9101 !strconcat(OpcodeStr,
9102 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
9103 []>, VEX_4VOp3, VEX_L;
9106 let mayLoad = 1, Constraints
9107 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
9109 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
9110 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
9111 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
9112 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;
9114 let ExeDomain = SSEPackedDouble in {
9115 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
9116 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
9119 let ExeDomain = SSEPackedSingle in {
9120 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
9121 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;