1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 let Sched = WriteVecLogic in
124 def SSE_VEC_BIT_ITINS_P : OpndItins<
125 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
128 def SSE_BIT_ITINS_P : OpndItins<
129 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
132 let Sched = WriteVecALU in {
133 def SSE_INTALU_ITINS_P : OpndItins<
134 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
137 def SSE_INTALUQ_ITINS_P : OpndItins<
138 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
142 let Sched = WriteVecIMul in
143 def SSE_INTMUL_ITINS_P : OpndItins<
144 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
147 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
148 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
151 def SSE_MOVA_ITINS : OpndItins<
152 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
155 def SSE_MOVU_ITINS : OpndItins<
156 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
159 def SSE_DPPD_ITINS : OpndItins<
160 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
163 def SSE_DPPS_ITINS : OpndItins<
164 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
167 def DEFAULT_ITINS : OpndItins<
168 IIC_ALU_NONMEM, IIC_ALU_MEM
171 def SSE_EXTRACT_ITINS : OpndItins<
172 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
175 def SSE_INSERT_ITINS : OpndItins<
176 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
179 let Sched = WriteMPSAD in
180 def SSE_MPSADBW_ITINS : OpndItins<
181 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
184 let Sched = WriteVecIMul in
185 def SSE_PMULLD_ITINS : OpndItins<
186 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
189 // Definitions for backward compatibility.
190 // The instructions mapped on these definitions uses a different itinerary
191 // than the actual scheduling model.
192 let Sched = WriteShuffle in
193 def DEFAULT_ITINS_SHUFFLESCHED : OpndItins<
194 IIC_ALU_NONMEM, IIC_ALU_MEM
197 let Sched = WriteVecIMul in
198 def DEFAULT_ITINS_VECIMULSCHED : OpndItins<
199 IIC_ALU_NONMEM, IIC_ALU_MEM
202 let Sched = WriteShuffle in
203 def SSE_INTALU_ITINS_SHUFF_P : OpndItins<
204 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
207 let Sched = WriteMPSAD in
208 def DEFAULT_ITINS_MPSADSCHED : OpndItins<
209 IIC_ALU_NONMEM, IIC_ALU_MEM
212 let Sched = WriteFBlend in
213 def DEFAULT_ITINS_FBLENDSCHED : OpndItins<
214 IIC_ALU_NONMEM, IIC_ALU_MEM
217 let Sched = WriteBlend in
218 def DEFAULT_ITINS_BLENDSCHED : OpndItins<
219 IIC_ALU_NONMEM, IIC_ALU_MEM
222 let Sched = WriteVarBlend in
223 def DEFAULT_ITINS_VARBLENDSCHED : OpndItins<
224 IIC_ALU_NONMEM, IIC_ALU_MEM
227 let Sched = WriteFBlend in
228 def SSE_INTALU_ITINS_FBLEND_P : OpndItins<
229 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
232 let Sched = WriteBlend in
233 def SSE_INTALU_ITINS_BLEND_P : OpndItins<
234 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
237 //===----------------------------------------------------------------------===//
238 // SSE 1 & 2 Instructions Classes
239 //===----------------------------------------------------------------------===//
241 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
242 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
243 RegisterClass RC, X86MemOperand x86memop,
244 Domain d, OpndItins itins, bit Is2Addr = 1> {
245 let isCommutable = 1 in {
246 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
248 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
249 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
250 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr, d>,
251 Sched<[itins.Sched]>;
253 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
255 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
256 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
257 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm, d>,
258 Sched<[itins.Sched.Folded, ReadAfterLd]>;
261 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
262 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
263 string asm, string SSEVer, string FPSizeStr,
264 Operand memopr, ComplexPattern mem_cpat,
265 Domain d, OpndItins itins, bit Is2Addr = 1> {
266 let isCodeGenOnly = 1 in {
267 def rr_Int : SI_Int<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
269 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
270 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
271 [(set RC:$dst, (!cast<Intrinsic>(
272 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
273 RC:$src1, RC:$src2))], itins.rr, d>,
274 Sched<[itins.Sched]>;
275 def rm_Int : SI_Int<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
277 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
278 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
279 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
280 SSEVer, "_", OpcodeStr, FPSizeStr))
281 RC:$src1, mem_cpat:$src2))], itins.rm, d>,
282 Sched<[itins.Sched.Folded, ReadAfterLd]>;
286 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
287 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
288 RegisterClass RC, ValueType vt,
289 X86MemOperand x86memop, PatFrag mem_frag,
290 Domain d, OpndItins itins, bit Is2Addr = 1> {
291 let isCommutable = 1 in
292 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
294 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
295 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
296 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
297 Sched<[itins.Sched]>;
299 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
301 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
302 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
303 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
305 Sched<[itins.Sched.Folded, ReadAfterLd]>;
308 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
309 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
310 string OpcodeStr, X86MemOperand x86memop,
311 list<dag> pat_rr, list<dag> pat_rm,
313 let isCommutable = 1, hasSideEffects = 0 in
314 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
316 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
317 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
318 pat_rr, NoItinerary, d>,
319 Sched<[WriteVecLogic]>;
320 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
322 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
323 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
324 pat_rm, NoItinerary, d>,
325 Sched<[WriteVecLogicLd, ReadAfterLd]>;
328 //===----------------------------------------------------------------------===//
329 // Non-instruction patterns
330 //===----------------------------------------------------------------------===//
332 // A vector extract of the first f32/f64 position is a subregister copy
333 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
334 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
335 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
336 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
338 // A 128-bit subvector extract from the first 256-bit vector position
339 // is a subregister copy that needs no instruction.
340 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
341 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
342 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
343 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
345 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
346 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
347 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
348 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
350 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
351 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
352 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
353 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
355 // A 128-bit subvector insert to the first 256-bit vector position
356 // is a subregister copy that needs no instruction.
357 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
358 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
359 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
360 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
361 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
362 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
363 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
364 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
365 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
366 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
367 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
368 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
369 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
372 // Implicitly promote a 32-bit scalar to a vector.
373 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
374 (COPY_TO_REGCLASS FR32:$src, VR128)>;
375 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
376 (COPY_TO_REGCLASS FR32:$src, VR128)>;
377 // Implicitly promote a 64-bit scalar to a vector.
378 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
379 (COPY_TO_REGCLASS FR64:$src, VR128)>;
380 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
381 (COPY_TO_REGCLASS FR64:$src, VR128)>;
383 // Bitcasts between 128-bit vector types. Return the original type since
384 // no instruction is needed for the conversion
385 let Predicates = [HasSSE2] in {
386 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
387 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
388 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
389 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
390 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
391 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
392 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
393 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
394 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
395 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
396 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
397 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
398 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
399 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
400 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
401 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
402 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
403 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
404 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
405 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
406 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
407 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
408 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
409 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
410 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
411 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
412 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
413 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
414 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
415 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
418 // Bitcasts between 256-bit vector types. Return the original type since
419 // no instruction is needed for the conversion
420 let Predicates = [HasAVX] in {
421 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
422 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
423 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
424 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
425 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
426 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
427 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
428 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
429 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
430 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
431 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
432 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
433 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
434 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
435 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
436 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
437 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
438 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
439 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
440 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
441 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
442 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
443 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
444 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
445 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
446 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
447 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
448 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
449 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
450 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
453 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
454 // This is expanded by ExpandPostRAPseudos.
455 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
456 isPseudo = 1, SchedRW = [WriteZero] in {
457 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
458 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
459 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
460 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
463 //===----------------------------------------------------------------------===//
464 // AVX & SSE - Zero/One Vectors
465 //===----------------------------------------------------------------------===//
467 // Alias instruction that maps zero vector to pxor / xorp* for sse.
468 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
469 // swizzled by ExecutionDepsFix to pxor.
470 // We set canFoldAsLoad because this can be converted to a constant-pool
471 // load of an all-zeros value if folding it would be beneficial.
472 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
473 isPseudo = 1, SchedRW = [WriteZero] in {
474 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
475 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
478 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
479 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
480 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
481 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
482 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
485 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
486 // and doesn't need it because on sandy bridge the register is set to zero
487 // at the rename stage without using any execution unit, so SET0PSY
488 // and SET0PDY can be used for vector int instructions without penalty
489 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
490 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
491 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
492 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
495 let Predicates = [HasAVX] in
496 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
498 let Predicates = [HasAVX2] in {
499 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
500 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
501 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
502 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
505 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
506 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
507 let Predicates = [HasAVX1Only] in {
508 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
509 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
510 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
512 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
513 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
514 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
516 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
517 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
518 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
520 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
521 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
522 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
525 // We set canFoldAsLoad because this can be converted to a constant-pool
526 // load of an all-ones value if folding it would be beneficial.
527 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
528 isPseudo = 1, SchedRW = [WriteZero] in {
529 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
530 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
531 let Predicates = [HasAVX2] in
532 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
533 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
537 //===----------------------------------------------------------------------===//
538 // SSE 1 & 2 - Move FP Scalar Instructions
540 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
541 // register copies because it's a partial register update; Register-to-register
542 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
543 // that the insert be implementable in terms of a copy, and just mentioned, we
544 // don't use movss/movsd for copies.
545 //===----------------------------------------------------------------------===//
547 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
548 X86MemOperand x86memop, string base_opc,
549 string asm_opr, Domain d = GenericDomain> {
550 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
551 (ins VR128:$src1, RC:$src2),
552 !strconcat(base_opc, asm_opr),
553 [(set VR128:$dst, (vt (OpNode VR128:$src1,
554 (scalar_to_vector RC:$src2))))],
555 IIC_SSE_MOV_S_RR, d>, Sched<[WriteFShuffle]>;
557 // For the disassembler
558 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
559 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
560 (ins VR128:$src1, RC:$src2),
561 !strconcat(base_opc, asm_opr),
562 [], IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
565 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
566 X86MemOperand x86memop, string OpcodeStr,
567 Domain d = GenericDomain> {
569 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
570 "\t{$src2, $src1, $dst|$dst, $src1, $src2}", d>,
573 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
574 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
575 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
576 VEX, VEX_LIG, Sched<[WriteStore]>;
578 let Constraints = "$src1 = $dst" in {
579 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
580 "\t{$src2, $dst|$dst, $src2}", d>;
583 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
584 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
585 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
589 // Loading from memory automatically zeroing upper bits.
590 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
591 PatFrag mem_pat, string OpcodeStr,
592 Domain d = GenericDomain> {
593 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
595 [(set RC:$dst, (mem_pat addr:$src))],
596 IIC_SSE_MOV_S_RM, d>, VEX, VEX_LIG, Sched<[WriteLoad]>;
597 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
598 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
599 [(set RC:$dst, (mem_pat addr:$src))],
600 IIC_SSE_MOV_S_RM, d>, Sched<[WriteLoad]>;
603 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss",
604 SSEPackedSingle>, XS;
605 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd",
606 SSEPackedDouble>, XD;
608 let canFoldAsLoad = 1, isReMaterializable = 1 in {
609 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss",
610 SSEPackedSingle>, XS;
612 let AddedComplexity = 20 in
613 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd",
614 SSEPackedDouble>, XD;
618 let Predicates = [UseAVX] in {
619 let AddedComplexity = 20 in {
620 // MOVSSrm zeros the high parts of the register; represent this
621 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
622 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
623 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
624 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
625 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
626 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
627 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
629 // MOVSDrm zeros the high parts of the register; represent this
630 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
631 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
632 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
633 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
634 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
635 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
636 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
637 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
638 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
639 def : Pat<(v2f64 (X86vzload addr:$src)),
640 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
642 // Represent the same patterns above but in the form they appear for
644 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
645 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
646 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
647 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
648 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
649 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
652 // Extract and store.
653 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
655 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
656 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
658 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
660 // Shuffle with VMOVSS
661 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
662 (VMOVSSrr (v4i32 VR128:$src1),
663 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
664 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
665 (VMOVSSrr (v4f32 VR128:$src1),
666 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
669 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
670 (SUBREG_TO_REG (i32 0),
671 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
672 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
674 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
675 (SUBREG_TO_REG (i32 0),
676 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
677 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
680 // Shuffle with VMOVSD
681 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
682 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
683 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
684 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
685 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
686 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
687 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
688 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
691 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
692 (SUBREG_TO_REG (i32 0),
693 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
694 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
696 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
697 (SUBREG_TO_REG (i32 0),
698 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
699 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
702 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
703 // is during lowering, where it's not possible to recognize the fold cause
704 // it has two uses through a bitcast. One use disappears at isel time and the
705 // fold opportunity reappears.
706 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
707 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
708 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
709 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
710 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
711 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
712 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
713 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
716 let Predicates = [UseSSE1] in {
717 let Predicates = [NoSSE41], AddedComplexity = 15 in {
718 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
719 // MOVSS to the lower bits.
720 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
721 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
722 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
723 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
724 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
725 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
728 let AddedComplexity = 20 in {
729 // MOVSSrm already zeros the high parts of the register.
730 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
731 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
732 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
733 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
734 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
735 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
738 // Extract and store.
739 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
741 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
743 // Shuffle with MOVSS
744 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
745 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
746 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
747 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
750 let Predicates = [UseSSE2] in {
751 let Predicates = [NoSSE41], AddedComplexity = 15 in {
752 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
753 // MOVSD to the lower bits.
754 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
755 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
758 let AddedComplexity = 20 in {
759 // MOVSDrm already zeros the high parts of the register.
760 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
761 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
762 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
763 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
764 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
765 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
766 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
767 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
768 def : Pat<(v2f64 (X86vzload addr:$src)),
769 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
772 // Extract and store.
773 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
775 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
777 // Shuffle with MOVSD
778 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
779 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
780 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
781 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
782 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
783 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
784 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
785 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
787 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
788 // is during lowering, where it's not possible to recognize the fold because
789 // it has two uses through a bitcast. One use disappears at isel time and the
790 // fold opportunity reappears.
791 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
792 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
793 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
794 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
795 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
796 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
797 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
798 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
801 //===----------------------------------------------------------------------===//
802 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
803 //===----------------------------------------------------------------------===//
805 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
806 X86MemOperand x86memop, PatFrag ld_frag,
807 string asm, Domain d,
809 bit IsReMaterializable = 1> {
810 let hasSideEffects = 0 in
811 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
812 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
813 Sched<[WriteFShuffle]>;
814 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
815 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
816 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
817 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
821 let Predicates = [HasAVX, NoVLX] in {
822 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
823 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
825 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
826 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
828 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
829 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
831 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
832 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
835 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
836 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
838 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
839 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
841 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
842 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
844 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
845 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
849 let Predicates = [UseSSE1] in {
850 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
851 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
853 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
854 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
857 let Predicates = [UseSSE2] in {
858 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
859 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
861 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
862 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
866 let SchedRW = [WriteStore], Predicates = [HasAVX, NoVLX] in {
867 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
868 "movaps\t{$src, $dst|$dst, $src}",
869 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
870 IIC_SSE_MOVA_P_MR>, VEX;
871 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
872 "movapd\t{$src, $dst|$dst, $src}",
873 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
874 IIC_SSE_MOVA_P_MR>, VEX;
875 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
876 "movups\t{$src, $dst|$dst, $src}",
877 [(store (v4f32 VR128:$src), addr:$dst)],
878 IIC_SSE_MOVU_P_MR>, VEX;
879 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
880 "movupd\t{$src, $dst|$dst, $src}",
881 [(store (v2f64 VR128:$src), addr:$dst)],
882 IIC_SSE_MOVU_P_MR>, VEX;
883 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
884 "movaps\t{$src, $dst|$dst, $src}",
885 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
886 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
887 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
888 "movapd\t{$src, $dst|$dst, $src}",
889 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
890 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
891 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
892 "movups\t{$src, $dst|$dst, $src}",
893 [(store (v8f32 VR256:$src), addr:$dst)],
894 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
895 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
896 "movupd\t{$src, $dst|$dst, $src}",
897 [(store (v4f64 VR256:$src), addr:$dst)],
898 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
902 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
903 SchedRW = [WriteFShuffle] in {
904 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
906 "movaps\t{$src, $dst|$dst, $src}", [],
907 IIC_SSE_MOVA_P_RR>, VEX;
908 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
910 "movapd\t{$src, $dst|$dst, $src}", [],
911 IIC_SSE_MOVA_P_RR>, VEX;
912 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
914 "movups\t{$src, $dst|$dst, $src}", [],
915 IIC_SSE_MOVU_P_RR>, VEX;
916 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
918 "movupd\t{$src, $dst|$dst, $src}", [],
919 IIC_SSE_MOVU_P_RR>, VEX;
920 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
922 "movaps\t{$src, $dst|$dst, $src}", [],
923 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
924 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
926 "movapd\t{$src, $dst|$dst, $src}", [],
927 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
928 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
930 "movups\t{$src, $dst|$dst, $src}", [],
931 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
932 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
934 "movupd\t{$src, $dst|$dst, $src}", [],
935 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
938 let Predicates = [HasAVX] in {
939 def : Pat<(v8i32 (X86vzmovl
940 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
941 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
942 def : Pat<(v4i64 (X86vzmovl
943 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
944 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
945 def : Pat<(v8f32 (X86vzmovl
946 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
947 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
948 def : Pat<(v4f64 (X86vzmovl
949 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
950 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
954 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
955 (VMOVUPSYmr addr:$dst, VR256:$src)>;
956 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
957 (VMOVUPDYmr addr:$dst, VR256:$src)>;
959 let SchedRW = [WriteStore] in {
960 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
961 "movaps\t{$src, $dst|$dst, $src}",
962 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
964 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
965 "movapd\t{$src, $dst|$dst, $src}",
966 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
968 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
969 "movups\t{$src, $dst|$dst, $src}",
970 [(store (v4f32 VR128:$src), addr:$dst)],
972 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
973 "movupd\t{$src, $dst|$dst, $src}",
974 [(store (v2f64 VR128:$src), addr:$dst)],
979 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
980 SchedRW = [WriteFShuffle] in {
981 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
982 "movaps\t{$src, $dst|$dst, $src}", [],
984 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
985 "movapd\t{$src, $dst|$dst, $src}", [],
987 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
988 "movups\t{$src, $dst|$dst, $src}", [],
990 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
991 "movupd\t{$src, $dst|$dst, $src}", [],
995 let Predicates = [HasAVX] in {
996 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
997 (VMOVUPSmr addr:$dst, VR128:$src)>;
998 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
999 (VMOVUPDmr addr:$dst, VR128:$src)>;
1002 let Predicates = [UseSSE1] in
1003 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1004 (MOVUPSmr addr:$dst, VR128:$src)>;
1005 let Predicates = [UseSSE2] in
1006 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1007 (MOVUPDmr addr:$dst, VR128:$src)>;
1009 // Use vmovaps/vmovups for AVX integer load/store.
1010 let Predicates = [HasAVX, NoVLX] in {
1011 // 128-bit load/store
1012 def : Pat<(alignedloadv2i64 addr:$src),
1013 (VMOVAPSrm addr:$src)>;
1014 def : Pat<(loadv2i64 addr:$src),
1015 (VMOVUPSrm addr:$src)>;
1017 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1018 (VMOVAPSmr addr:$dst, VR128:$src)>;
1019 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1020 (VMOVAPSmr addr:$dst, VR128:$src)>;
1021 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1022 (VMOVAPSmr addr:$dst, VR128:$src)>;
1023 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1024 (VMOVAPSmr addr:$dst, VR128:$src)>;
1025 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1026 (VMOVUPSmr addr:$dst, VR128:$src)>;
1027 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1028 (VMOVUPSmr addr:$dst, VR128:$src)>;
1029 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1030 (VMOVUPSmr addr:$dst, VR128:$src)>;
1031 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1032 (VMOVUPSmr addr:$dst, VR128:$src)>;
1034 // 256-bit load/store
1035 def : Pat<(alignedloadv4i64 addr:$src),
1036 (VMOVAPSYrm addr:$src)>;
1037 def : Pat<(loadv4i64 addr:$src),
1038 (VMOVUPSYrm addr:$src)>;
1039 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1040 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1041 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1042 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1043 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1044 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1045 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1046 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1047 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1048 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1049 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1050 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1051 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1052 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1053 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1054 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1056 // Special patterns for storing subvector extracts of lower 128-bits
1057 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1058 def : Pat<(alignedstore (v2f64 (extract_subvector
1059 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1060 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1061 def : Pat<(alignedstore (v4f32 (extract_subvector
1062 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1063 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1064 def : Pat<(alignedstore (v2i64 (extract_subvector
1065 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1066 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1067 def : Pat<(alignedstore (v4i32 (extract_subvector
1068 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1069 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1070 def : Pat<(alignedstore (v8i16 (extract_subvector
1071 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1072 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1073 def : Pat<(alignedstore (v16i8 (extract_subvector
1074 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1075 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1077 def : Pat<(store (v2f64 (extract_subvector
1078 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1079 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1080 def : Pat<(store (v4f32 (extract_subvector
1081 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1082 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1083 def : Pat<(store (v2i64 (extract_subvector
1084 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1085 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1086 def : Pat<(store (v4i32 (extract_subvector
1087 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1088 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1089 def : Pat<(store (v8i16 (extract_subvector
1090 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1091 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1092 def : Pat<(store (v16i8 (extract_subvector
1093 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1094 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1097 // Use movaps / movups for SSE integer load / store (one byte shorter).
1098 // The instructions selected below are then converted to MOVDQA/MOVDQU
1099 // during the SSE domain pass.
1100 let Predicates = [UseSSE1] in {
1101 def : Pat<(alignedloadv2i64 addr:$src),
1102 (MOVAPSrm addr:$src)>;
1103 def : Pat<(loadv2i64 addr:$src),
1104 (MOVUPSrm addr:$src)>;
1106 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1107 (MOVAPSmr addr:$dst, VR128:$src)>;
1108 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1109 (MOVAPSmr addr:$dst, VR128:$src)>;
1110 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1111 (MOVAPSmr addr:$dst, VR128:$src)>;
1112 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1113 (MOVAPSmr addr:$dst, VR128:$src)>;
1114 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1115 (MOVUPSmr addr:$dst, VR128:$src)>;
1116 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1117 (MOVUPSmr addr:$dst, VR128:$src)>;
1118 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1119 (MOVUPSmr addr:$dst, VR128:$src)>;
1120 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1121 (MOVUPSmr addr:$dst, VR128:$src)>;
1124 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1125 // bits are disregarded. FIXME: Set encoding to pseudo!
1126 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1127 let isCodeGenOnly = 1 in {
1128 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1129 "movaps\t{$src, $dst|$dst, $src}",
1130 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1131 IIC_SSE_MOVA_P_RM>, VEX;
1132 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1133 "movapd\t{$src, $dst|$dst, $src}",
1134 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1135 IIC_SSE_MOVA_P_RM>, VEX;
1136 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1137 "movaps\t{$src, $dst|$dst, $src}",
1138 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1140 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1141 "movapd\t{$src, $dst|$dst, $src}",
1142 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1147 //===----------------------------------------------------------------------===//
1148 // SSE 1 & 2 - Move Low packed FP Instructions
1149 //===----------------------------------------------------------------------===//
1151 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1152 string base_opc, string asm_opr,
1153 InstrItinClass itin> {
1154 def PSrm : PI<opc, MRMSrcMem,
1155 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1156 !strconcat(base_opc, "s", asm_opr),
1158 (psnode VR128:$src1,
1159 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1160 itin, SSEPackedSingle>, PS,
1161 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1163 def PDrm : PI<opc, MRMSrcMem,
1164 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1165 !strconcat(base_opc, "d", asm_opr),
1166 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1167 (scalar_to_vector (loadf64 addr:$src2)))))],
1168 itin, SSEPackedDouble>, PD,
1169 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1173 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1174 string base_opc, InstrItinClass itin> {
1175 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1176 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1179 let Constraints = "$src1 = $dst" in
1180 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1181 "\t{$src2, $dst|$dst, $src2}",
1185 let AddedComplexity = 20 in {
1186 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1190 let SchedRW = [WriteStore] in {
1191 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1192 "movlps\t{$src, $dst|$dst, $src}",
1193 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1194 (iPTR 0))), addr:$dst)],
1195 IIC_SSE_MOV_LH>, VEX;
1196 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1197 "movlpd\t{$src, $dst|$dst, $src}",
1198 [(store (f64 (vector_extract (v2f64 VR128:$src),
1199 (iPTR 0))), addr:$dst)],
1200 IIC_SSE_MOV_LH>, VEX;
1201 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1202 "movlps\t{$src, $dst|$dst, $src}",
1203 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1204 (iPTR 0))), addr:$dst)],
1206 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1207 "movlpd\t{$src, $dst|$dst, $src}",
1208 [(store (f64 (vector_extract (v2f64 VR128:$src),
1209 (iPTR 0))), addr:$dst)],
1213 let Predicates = [HasAVX] in {
1214 // Shuffle with VMOVLPS
1215 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1216 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1217 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1218 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1220 // Shuffle with VMOVLPD
1221 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1222 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1223 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1224 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1226 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1227 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1230 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1232 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1233 def : Pat<(store (v4i32 (X86Movlps
1234 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1235 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1236 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1238 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1239 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1241 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1244 let Predicates = [UseSSE1] in {
1245 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1246 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1247 (iPTR 0))), addr:$src1),
1248 (MOVLPSmr addr:$src1, VR128:$src2)>;
1250 // Shuffle with MOVLPS
1251 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1252 (MOVLPSrm VR128:$src1, addr:$src2)>;
1253 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1254 (MOVLPSrm VR128:$src1, addr:$src2)>;
1255 def : Pat<(X86Movlps VR128:$src1,
1256 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1257 (MOVLPSrm VR128:$src1, addr:$src2)>;
1260 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1262 (MOVLPSmr addr:$src1, VR128:$src2)>;
1263 def : Pat<(store (v4i32 (X86Movlps
1264 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1266 (MOVLPSmr addr:$src1, VR128:$src2)>;
1269 let Predicates = [UseSSE2] in {
1270 // Shuffle with MOVLPD
1271 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1272 (MOVLPDrm VR128:$src1, addr:$src2)>;
1273 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1274 (MOVLPDrm VR128:$src1, addr:$src2)>;
1275 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1276 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1277 (MOVLPDrm VR128:$src1, addr:$src2)>;
1280 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1282 (MOVLPDmr addr:$src1, VR128:$src2)>;
1283 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1285 (MOVLPDmr addr:$src1, VR128:$src2)>;
1288 //===----------------------------------------------------------------------===//
1289 // SSE 1 & 2 - Move Hi packed FP Instructions
1290 //===----------------------------------------------------------------------===//
1292 let AddedComplexity = 20 in {
1293 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1297 let SchedRW = [WriteStore] in {
1298 // v2f64 extract element 1 is always custom lowered to unpack high to low
1299 // and extract element 0 so the non-store version isn't too horrible.
1300 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1301 "movhps\t{$src, $dst|$dst, $src}",
1302 [(store (f64 (vector_extract
1303 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1304 (bc_v2f64 (v4f32 VR128:$src))),
1305 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1306 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1307 "movhpd\t{$src, $dst|$dst, $src}",
1308 [(store (f64 (vector_extract
1309 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1310 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1311 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1312 "movhps\t{$src, $dst|$dst, $src}",
1313 [(store (f64 (vector_extract
1314 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1315 (bc_v2f64 (v4f32 VR128:$src))),
1316 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1317 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1318 "movhpd\t{$src, $dst|$dst, $src}",
1319 [(store (f64 (vector_extract
1320 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1321 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1324 let Predicates = [HasAVX] in {
1326 def : Pat<(X86Movlhps VR128:$src1,
1327 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1328 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1329 def : Pat<(X86Movlhps VR128:$src1,
1330 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1331 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1335 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1336 // is during lowering, where it's not possible to recognize the load fold
1337 // cause it has two uses through a bitcast. One use disappears at isel time
1338 // and the fold opportunity reappears.
1339 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1340 (scalar_to_vector (loadf64 addr:$src2)))),
1341 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1342 // Also handle an i64 load because that may get selected as a faster way to
1344 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1345 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1346 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1348 def : Pat<(store (f64 (vector_extract
1349 (v2f64 (X86VPermilpi VR128:$src, (i8 1))),
1350 (iPTR 0))), addr:$dst),
1351 (VMOVHPDmr addr:$dst, VR128:$src)>;
1354 let Predicates = [UseSSE1] in {
1356 def : Pat<(X86Movlhps VR128:$src1,
1357 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1358 (MOVHPSrm VR128:$src1, addr:$src2)>;
1359 def : Pat<(X86Movlhps VR128:$src1,
1360 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1361 (MOVHPSrm VR128:$src1, addr:$src2)>;
1364 let Predicates = [UseSSE2] in {
1367 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1368 // is during lowering, where it's not possible to recognize the load fold
1369 // cause it has two uses through a bitcast. One use disappears at isel time
1370 // and the fold opportunity reappears.
1371 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1372 (scalar_to_vector (loadf64 addr:$src2)))),
1373 (MOVHPDrm VR128:$src1, addr:$src2)>;
1374 // Also handle an i64 load because that may get selected as a faster way to
1376 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1377 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1378 (MOVHPDrm VR128:$src1, addr:$src2)>;
1380 def : Pat<(store (f64 (vector_extract
1381 (v2f64 (X86Shufp VR128:$src, VR128:$src, (i8 1))),
1382 (iPTR 0))), addr:$dst),
1383 (MOVHPDmr addr:$dst, VR128:$src)>;
1386 //===----------------------------------------------------------------------===//
1387 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1388 //===----------------------------------------------------------------------===//
1390 let AddedComplexity = 20, Predicates = [UseAVX] in {
1391 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1392 (ins VR128:$src1, VR128:$src2),
1393 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1395 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1397 VEX_4V, Sched<[WriteFShuffle]>;
1398 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1399 (ins VR128:$src1, VR128:$src2),
1400 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1402 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1404 VEX_4V, Sched<[WriteFShuffle]>;
1406 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1407 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1408 (ins VR128:$src1, VR128:$src2),
1409 "movlhps\t{$src2, $dst|$dst, $src2}",
1411 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1412 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1413 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1414 (ins VR128:$src1, VR128:$src2),
1415 "movhlps\t{$src2, $dst|$dst, $src2}",
1417 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1418 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1421 let Predicates = [UseAVX] in {
1423 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1424 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1425 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1426 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1429 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1430 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1433 let Predicates = [UseSSE1] in {
1435 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1436 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1437 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1438 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1441 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1442 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1445 //===----------------------------------------------------------------------===//
1446 // SSE 1 & 2 - Conversion Instructions
1447 //===----------------------------------------------------------------------===//
1449 def SSE_CVT_PD : OpndItins<
1450 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1453 let Sched = WriteCvtI2F in
1454 def SSE_CVT_PS : OpndItins<
1455 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1458 let Sched = WriteCvtI2F in
1459 def SSE_CVT_Scalar : OpndItins<
1460 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1463 let Sched = WriteCvtF2I in
1464 def SSE_CVT_SS2SI_32 : OpndItins<
1465 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1468 let Sched = WriteCvtF2I in
1469 def SSE_CVT_SS2SI_64 : OpndItins<
1470 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1473 let Sched = WriteCvtF2I in
1474 def SSE_CVT_SD2SI : OpndItins<
1475 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1478 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1479 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1480 string asm, OpndItins itins> {
1481 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1482 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1483 itins.rr>, Sched<[itins.Sched]>;
1484 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1485 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1486 itins.rm>, Sched<[itins.Sched.Folded]>;
1489 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1490 X86MemOperand x86memop, string asm, Domain d,
1492 let hasSideEffects = 0 in {
1493 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1494 [], itins.rr, d>, Sched<[itins.Sched]>;
1496 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1497 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1501 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1502 X86MemOperand x86memop, string asm> {
1503 let hasSideEffects = 0, Predicates = [UseAVX] in {
1504 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1505 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1506 Sched<[WriteCvtI2F]>;
1508 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1509 (ins DstRC:$src1, x86memop:$src),
1510 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1511 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1512 } // hasSideEffects = 0
1515 let Predicates = [UseAVX] in {
1516 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1517 "cvttss2si\t{$src, $dst|$dst, $src}",
1520 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1521 "cvttss2si\t{$src, $dst|$dst, $src}",
1523 XS, VEX, VEX_W, VEX_LIG;
1524 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1525 "cvttsd2si\t{$src, $dst|$dst, $src}",
1528 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1529 "cvttsd2si\t{$src, $dst|$dst, $src}",
1531 XD, VEX, VEX_W, VEX_LIG;
1533 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1534 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1535 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1536 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1537 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1538 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1539 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1540 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1541 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1542 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1543 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1544 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1545 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1546 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1547 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1548 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1550 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1551 // register, but the same isn't true when only using memory operands,
1552 // provide other assembly "l" and "q" forms to address this explicitly
1553 // where appropriate to do so.
1554 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1555 XS, VEX_4V, VEX_LIG;
1556 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1557 XS, VEX_4V, VEX_W, VEX_LIG;
1558 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1559 XD, VEX_4V, VEX_LIG;
1560 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1561 XD, VEX_4V, VEX_W, VEX_LIG;
1563 let Predicates = [UseAVX] in {
1564 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1565 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1566 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1567 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1569 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1570 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1571 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1572 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1573 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1574 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1575 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1576 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1578 def : Pat<(f32 (sint_to_fp GR32:$src)),
1579 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1580 def : Pat<(f32 (sint_to_fp GR64:$src)),
1581 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1582 def : Pat<(f64 (sint_to_fp GR32:$src)),
1583 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1584 def : Pat<(f64 (sint_to_fp GR64:$src)),
1585 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1588 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1589 "cvttss2si\t{$src, $dst|$dst, $src}",
1590 SSE_CVT_SS2SI_32>, XS;
1591 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1592 "cvttss2si\t{$src, $dst|$dst, $src}",
1593 SSE_CVT_SS2SI_64>, XS, REX_W;
1594 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1595 "cvttsd2si\t{$src, $dst|$dst, $src}",
1597 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1598 "cvttsd2si\t{$src, $dst|$dst, $src}",
1599 SSE_CVT_SD2SI>, XD, REX_W;
1600 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1601 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1602 SSE_CVT_Scalar>, XS;
1603 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1604 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1605 SSE_CVT_Scalar>, XS, REX_W;
1606 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1607 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1608 SSE_CVT_Scalar>, XD;
1609 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1610 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1611 SSE_CVT_Scalar>, XD, REX_W;
1613 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1614 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1615 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1616 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1617 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1618 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1619 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1620 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1621 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1622 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1623 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1624 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1625 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1626 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1627 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1628 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1630 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1631 (CVTSI2SSrm FR64:$dst, i32mem:$src), 0>;
1632 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1633 (CVTSI2SDrm FR64:$dst, i32mem:$src), 0>;
1635 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1636 // and/or XMM operand(s).
1638 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1639 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1640 string asm, OpndItins itins> {
1641 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1642 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1643 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1644 Sched<[itins.Sched]>;
1645 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1646 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1647 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1648 Sched<[itins.Sched.Folded]>;
1651 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1652 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1653 PatFrag ld_frag, string asm, OpndItins itins,
1655 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1657 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1658 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1659 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1660 itins.rr>, Sched<[itins.Sched]>;
1661 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1662 (ins DstRC:$src1, x86memop:$src2),
1664 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1665 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1666 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1667 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1670 let Predicates = [UseAVX] in {
1671 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1672 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1673 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1674 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1675 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1676 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1678 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1679 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1680 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1681 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1684 let isCodeGenOnly = 1 in {
1685 let Predicates = [UseAVX] in {
1686 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1687 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1688 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1689 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1690 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1691 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1693 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1694 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1695 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1696 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1697 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1698 SSE_CVT_Scalar, 0>, XD,
1701 let Constraints = "$src1 = $dst" in {
1702 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1703 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1704 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1705 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1706 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1707 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1708 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1709 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1710 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1711 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1712 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1713 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1715 } // isCodeGenOnly = 1
1719 // Aliases for intrinsics
1720 let isCodeGenOnly = 1 in {
1721 let Predicates = [UseAVX] in {
1722 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1723 ssmem, sse_load_f32, "cvttss2si",
1724 SSE_CVT_SS2SI_32>, XS, VEX;
1725 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1726 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1727 "cvttss2si", SSE_CVT_SS2SI_64>,
1729 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1730 sdmem, sse_load_f64, "cvttsd2si",
1731 SSE_CVT_SD2SI>, XD, VEX;
1732 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1733 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1734 "cvttsd2si", SSE_CVT_SD2SI>,
1737 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1738 ssmem, sse_load_f32, "cvttss2si",
1739 SSE_CVT_SS2SI_32>, XS;
1740 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1741 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1742 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1743 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1744 sdmem, sse_load_f64, "cvttsd2si",
1746 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1747 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1748 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1749 } // isCodeGenOnly = 1
1751 let Predicates = [UseAVX] in {
1752 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1753 ssmem, sse_load_f32, "cvtss2si",
1754 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1755 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1756 ssmem, sse_load_f32, "cvtss2si",
1757 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1759 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1760 ssmem, sse_load_f32, "cvtss2si",
1761 SSE_CVT_SS2SI_32>, XS;
1762 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1763 ssmem, sse_load_f32, "cvtss2si",
1764 SSE_CVT_SS2SI_64>, XS, REX_W;
1766 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1767 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1768 SSEPackedSingle, SSE_CVT_PS>,
1769 PS, VEX, Requires<[HasAVX]>;
1770 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1771 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1772 SSEPackedSingle, SSE_CVT_PS>,
1773 PS, VEX, VEX_L, Requires<[HasAVX]>;
1775 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1776 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1777 SSEPackedSingle, SSE_CVT_PS>,
1778 PS, Requires<[UseSSE2]>;
1780 let Predicates = [UseAVX] in {
1781 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1782 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1783 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1784 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1785 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1786 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1787 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1788 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1789 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1790 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1791 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1792 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1793 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1794 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1795 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1796 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1799 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1800 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1801 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1802 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1803 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1804 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1805 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1806 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1807 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1808 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1809 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1810 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1811 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1812 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1813 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1814 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1818 // Convert scalar double to scalar single
1819 let hasSideEffects = 0, Predicates = [UseAVX] in {
1820 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1821 (ins FR64:$src1, FR64:$src2),
1822 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1823 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1824 Sched<[WriteCvtF2F]>;
1826 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1827 (ins FR64:$src1, f64mem:$src2),
1828 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1829 [], IIC_SSE_CVT_Scalar_RM>,
1830 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1831 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1834 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1837 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1838 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1839 [(set FR32:$dst, (fround FR64:$src))],
1840 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1841 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1842 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1843 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1844 IIC_SSE_CVT_Scalar_RM>,
1846 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1848 let isCodeGenOnly = 1 in {
1849 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1850 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1851 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1853 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1854 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>,
1855 Sched<[WriteCvtF2F]>;
1856 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1857 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1858 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1859 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1860 VR128:$src1, sse_load_f64:$src2))],
1861 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>,
1862 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1864 let Constraints = "$src1 = $dst" in {
1865 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1866 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1867 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1869 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1870 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1871 Sched<[WriteCvtF2F]>;
1872 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1873 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1874 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1875 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1876 VR128:$src1, sse_load_f64:$src2))],
1877 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1878 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1880 } // isCodeGenOnly = 1
1882 // Convert scalar single to scalar double
1883 // SSE2 instructions with XS prefix
1884 let hasSideEffects = 0, Predicates = [UseAVX] in {
1885 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1886 (ins FR32:$src1, FR32:$src2),
1887 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1888 [], IIC_SSE_CVT_Scalar_RR>,
1889 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1890 Sched<[WriteCvtF2F]>;
1892 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1893 (ins FR32:$src1, f32mem:$src2),
1894 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1895 [], IIC_SSE_CVT_Scalar_RM>,
1896 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1897 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1900 def : Pat<(f64 (fextend FR32:$src)),
1901 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1902 def : Pat<(fextend (loadf32 addr:$src)),
1903 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1905 def : Pat<(extloadf32 addr:$src),
1906 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1907 Requires<[UseAVX, OptForSize]>;
1908 def : Pat<(extloadf32 addr:$src),
1909 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1910 Requires<[UseAVX, OptForSpeed]>;
1912 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1913 "cvtss2sd\t{$src, $dst|$dst, $src}",
1914 [(set FR64:$dst, (fextend FR32:$src))],
1915 IIC_SSE_CVT_Scalar_RR>, XS,
1916 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1917 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1918 "cvtss2sd\t{$src, $dst|$dst, $src}",
1919 [(set FR64:$dst, (extloadf32 addr:$src))],
1920 IIC_SSE_CVT_Scalar_RM>, XS,
1921 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1923 // extload f32 -> f64. This matches load+fextend because we have a hack in
1924 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1926 // Since these loads aren't folded into the fextend, we have to match it
1928 def : Pat<(fextend (loadf32 addr:$src)),
1929 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1930 def : Pat<(extloadf32 addr:$src),
1931 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1933 let isCodeGenOnly = 1 in {
1934 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1935 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1936 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1938 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1939 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[HasAVX]>,
1940 Sched<[WriteCvtF2F]>;
1941 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1942 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1943 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1945 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1946 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[HasAVX]>,
1947 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1948 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1949 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1950 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1951 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1953 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1954 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1955 Sched<[WriteCvtF2F]>;
1956 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1957 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1958 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1960 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1961 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1962 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1964 } // isCodeGenOnly = 1
1966 // Convert packed single/double fp to doubleword
1967 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1968 "cvtps2dq\t{$src, $dst|$dst, $src}",
1969 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1970 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1971 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1972 "cvtps2dq\t{$src, $dst|$dst, $src}",
1974 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1975 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1976 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1977 "cvtps2dq\t{$src, $dst|$dst, $src}",
1979 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1980 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1981 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1982 "cvtps2dq\t{$src, $dst|$dst, $src}",
1984 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
1985 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1986 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1987 "cvtps2dq\t{$src, $dst|$dst, $src}",
1988 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1989 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1990 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1991 "cvtps2dq\t{$src, $dst|$dst, $src}",
1993 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1994 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1997 // Convert Packed Double FP to Packed DW Integers
1998 let Predicates = [HasAVX] in {
1999 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2000 // register, but the same isn't true when using memory operands instead.
2001 // Provide other assembly rr and rm forms to address this explicitly.
2002 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2003 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
2004 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
2005 VEX, Sched<[WriteCvtF2I]>;
2008 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2009 (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>;
2010 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2011 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2013 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
2014 Sched<[WriteCvtF2ILd]>;
2017 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2018 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2020 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
2021 Sched<[WriteCvtF2I]>;
2022 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2023 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2025 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
2026 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2027 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
2028 (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2031 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2032 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2034 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
2035 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
2036 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2037 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2038 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
2039 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2041 // Convert with truncation packed single/double fp to doubleword
2042 // SSE2 packed instructions with XS prefix
2043 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2044 "cvttps2dq\t{$src, $dst|$dst, $src}",
2046 (int_x86_sse2_cvttps2dq VR128:$src))],
2047 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2048 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2049 "cvttps2dq\t{$src, $dst|$dst, $src}",
2050 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2051 (loadv4f32 addr:$src)))],
2052 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2053 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2054 "cvttps2dq\t{$src, $dst|$dst, $src}",
2056 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2057 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2058 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2059 "cvttps2dq\t{$src, $dst|$dst, $src}",
2060 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2061 (loadv8f32 addr:$src)))],
2062 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2063 Sched<[WriteCvtF2ILd]>;
2065 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2066 "cvttps2dq\t{$src, $dst|$dst, $src}",
2067 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2068 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2069 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2070 "cvttps2dq\t{$src, $dst|$dst, $src}",
2072 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2073 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2075 let Predicates = [HasAVX] in {
2076 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2077 (VCVTDQ2PSrr VR128:$src)>;
2078 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2079 (VCVTDQ2PSrm addr:$src)>;
2082 let Predicates = [HasAVX, NoVLX] in {
2083 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2084 (VCVTDQ2PSrr VR128:$src)>;
2085 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2086 (VCVTDQ2PSrm addr:$src)>;
2088 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2089 (VCVTTPS2DQrr VR128:$src)>;
2090 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2091 (VCVTTPS2DQrm addr:$src)>;
2093 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2094 (VCVTDQ2PSYrr VR256:$src)>;
2095 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2096 (VCVTDQ2PSYrm addr:$src)>;
2098 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2099 (VCVTTPS2DQYrr VR256:$src)>;
2100 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2101 (VCVTTPS2DQYrm addr:$src)>;
2104 let Predicates = [UseSSE2] in {
2105 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2106 (CVTDQ2PSrr VR128:$src)>;
2107 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2108 (CVTDQ2PSrm addr:$src)>;
2110 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2111 (CVTDQ2PSrr VR128:$src)>;
2112 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2113 (CVTDQ2PSrm addr:$src)>;
2115 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2116 (CVTTPS2DQrr VR128:$src)>;
2117 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2118 (CVTTPS2DQrm addr:$src)>;
2121 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2122 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2124 (int_x86_sse2_cvttpd2dq VR128:$src))],
2125 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2127 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2128 // register, but the same isn't true when using memory operands instead.
2129 // Provide other assembly rr and rm forms to address this explicitly.
2132 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2133 (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>;
2134 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2135 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2136 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2137 (loadv2f64 addr:$src)))],
2138 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2141 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2142 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2144 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2145 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2146 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2147 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2149 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2150 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2151 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2152 (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2154 let Predicates = [HasAVX, NoVLX] in {
2155 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2156 (VCVTTPD2DQYrr VR256:$src)>;
2157 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2158 (VCVTTPD2DQYrm addr:$src)>;
2159 } // Predicates = [HasAVX]
2161 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2162 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2163 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2164 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2165 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2166 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2167 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2168 (memopv2f64 addr:$src)))],
2170 Sched<[WriteCvtF2ILd]>;
2172 // Convert packed single to packed double
2173 let Predicates = [HasAVX] in {
2174 // SSE2 instructions without OpSize prefix
2175 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2176 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2177 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2178 IIC_SSE_CVT_PD_RR>, PS, VEX, Sched<[WriteCvtF2F]>;
2179 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2180 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2181 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2182 IIC_SSE_CVT_PD_RM>, PS, VEX, Sched<[WriteCvtF2FLd]>;
2183 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2184 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2186 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2187 IIC_SSE_CVT_PD_RR>, PS, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2188 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2189 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2191 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2192 IIC_SSE_CVT_PD_RM>, PS, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2195 let Predicates = [UseSSE2] in {
2196 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2197 "cvtps2pd\t{$src, $dst|$dst, $src}",
2198 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2199 IIC_SSE_CVT_PD_RR>, PS, Sched<[WriteCvtF2F]>;
2200 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2201 "cvtps2pd\t{$src, $dst|$dst, $src}",
2202 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2203 IIC_SSE_CVT_PD_RM>, PS, Sched<[WriteCvtF2FLd]>;
2206 // Convert Packed DW Integers to Packed Double FP
2207 let Predicates = [HasAVX] in {
2208 let hasSideEffects = 0, mayLoad = 1 in
2209 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2210 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2211 []>, VEX, Sched<[WriteCvtI2FLd]>;
2212 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2213 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2215 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2216 Sched<[WriteCvtI2F]>;
2217 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2218 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2220 (int_x86_avx_cvtdq2_pd_256
2221 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2222 Sched<[WriteCvtI2FLd]>;
2223 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2224 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2226 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2227 Sched<[WriteCvtI2F]>;
2230 let hasSideEffects = 0, mayLoad = 1 in
2231 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2232 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2233 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2234 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2235 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2236 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2237 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2239 // AVX register conversion intrinsics
2240 let Predicates = [HasAVX] in {
2241 def : Pat<(v2f64 (X86cvtdq2pd (v4i32 VR128:$src))),
2242 (VCVTDQ2PDrr VR128:$src)>;
2243 def : Pat<(v2f64 (X86cvtdq2pd (bc_v4i32 (loadv2i64 addr:$src)))),
2244 (VCVTDQ2PDrm addr:$src)>;
2246 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2247 (VCVTDQ2PDYrr VR128:$src)>;
2248 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2249 (VCVTDQ2PDYrm addr:$src)>;
2250 } // Predicates = [HasAVX]
2252 // SSE2 register conversion intrinsics
2253 let Predicates = [HasSSE2] in {
2254 def : Pat<(v2f64 (X86cvtdq2pd (v4i32 VR128:$src))),
2255 (CVTDQ2PDrr VR128:$src)>;
2256 def : Pat<(v2f64 (X86cvtdq2pd (bc_v4i32 (loadv2i64 addr:$src)))),
2257 (CVTDQ2PDrm addr:$src)>;
2258 } // Predicates = [HasSSE2]
2260 // Convert packed double to packed single
2261 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2262 // register, but the same isn't true when using memory operands instead.
2263 // Provide other assembly rr and rm forms to address this explicitly.
2264 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2265 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2266 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2267 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2270 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2271 (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>;
2272 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2273 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2275 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2276 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2279 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2280 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2282 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2283 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2284 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2285 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2287 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2288 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2289 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2290 (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>;
2292 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2293 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2294 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2295 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2296 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2297 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2299 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2300 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2303 // AVX 256-bit register conversion intrinsics
2304 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2305 // whenever possible to avoid declaring two versions of each one.
2306 let Predicates = [HasAVX] in {
2307 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2308 (VCVTDQ2PSYrr VR256:$src)>;
2309 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2310 (VCVTDQ2PSYrm addr:$src)>;
2313 let Predicates = [HasAVX, NoVLX] in {
2314 // Match fround and fextend for 128/256-bit conversions
2315 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2316 (VCVTPD2PSrr VR128:$src)>;
2317 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2318 (VCVTPD2PSXrm addr:$src)>;
2319 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2320 (VCVTPD2PSYrr VR256:$src)>;
2321 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2322 (VCVTPD2PSYrm addr:$src)>;
2324 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2325 (VCVTPS2PDrr VR128:$src)>;
2326 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2327 (VCVTPS2PDYrr VR128:$src)>;
2328 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2329 (VCVTPS2PDYrm addr:$src)>;
2332 let Predicates = [UseSSE2] in {
2333 // Match fround and fextend for 128 conversions
2334 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2335 (CVTPD2PSrr VR128:$src)>;
2336 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2337 (CVTPD2PSrm addr:$src)>;
2339 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2340 (CVTPS2PDrr VR128:$src)>;
2343 //===----------------------------------------------------------------------===//
2344 // SSE 1 & 2 - Compare Instructions
2345 //===----------------------------------------------------------------------===//
2347 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2348 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2349 Operand CC, SDNode OpNode, ValueType VT,
2350 PatFrag ld_frag, string asm, string asm_alt,
2351 OpndItins itins, ImmLeaf immLeaf> {
2352 def rr : SIi8<0xC2, MRMSrcReg,
2353 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2354 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, immLeaf:$cc))],
2355 itins.rr>, Sched<[itins.Sched]>;
2356 def rm : SIi8<0xC2, MRMSrcMem,
2357 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2358 [(set RC:$dst, (OpNode (VT RC:$src1),
2359 (ld_frag addr:$src2), immLeaf:$cc))],
2361 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2363 // Accept explicit immediate argument form instead of comparison code.
2364 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2365 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2366 (ins RC:$src1, RC:$src2, u8imm:$cc), asm_alt, [],
2367 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2369 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2370 (ins RC:$src1, x86memop:$src2, u8imm:$cc), asm_alt, [],
2371 IIC_SSE_ALU_F32S_RM>,
2372 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2376 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2377 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2378 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2379 SSE_ALU_F32S, i8immZExt5>, XS, VEX_4V, VEX_LIG;
2380 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2381 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2382 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2383 SSE_ALU_F32S, i8immZExt5>, // same latency as 32 bit compare
2384 XD, VEX_4V, VEX_LIG;
2386 let Constraints = "$src1 = $dst" in {
2387 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2388 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2389 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S,
2391 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2392 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2393 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2394 SSE_ALU_F64S, i8immZExt3>, XD;
2397 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2398 Intrinsic Int, string asm, OpndItins itins,
2400 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2401 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2402 [(set VR128:$dst, (Int VR128:$src1,
2403 VR128:$src, immLeaf:$cc))],
2405 Sched<[itins.Sched]>;
2406 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2407 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2408 [(set VR128:$dst, (Int VR128:$src1,
2409 (load addr:$src), immLeaf:$cc))],
2411 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2414 let isCodeGenOnly = 1 in {
2415 // Aliases to match intrinsics which expect XMM operand(s).
2416 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2417 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2418 SSE_ALU_F32S, i8immZExt5>,
2420 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2421 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2422 SSE_ALU_F32S, i8immZExt5>, // same latency as f32
2424 let Constraints = "$src1 = $dst" in {
2425 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2426 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2427 SSE_ALU_F32S, i8immZExt3>, XS;
2428 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2429 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2430 SSE_ALU_F64S, i8immZExt3>,
2436 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2437 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2438 ValueType vt, X86MemOperand x86memop,
2439 PatFrag ld_frag, string OpcodeStr> {
2440 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2441 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2442 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2445 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2446 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2447 [(set EFLAGS, (OpNode (vt RC:$src1),
2448 (ld_frag addr:$src2)))],
2450 Sched<[WriteFAddLd, ReadAfterLd]>;
2453 let Defs = [EFLAGS] in {
2454 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2455 "ucomiss">, PS, VEX, VEX_LIG;
2456 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2457 "ucomisd">, PD, VEX, VEX_LIG;
2458 let Pattern = []<dag> in {
2459 defm VCOMISS : sse12_ord_cmp<0x2F, FR32, undef, f32, f32mem, loadf32,
2460 "comiss">, PS, VEX, VEX_LIG;
2461 defm VCOMISD : sse12_ord_cmp<0x2F, FR64, undef, f64, f64mem, loadf64,
2462 "comisd">, PD, VEX, VEX_LIG;
2465 let isCodeGenOnly = 1 in {
2466 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2467 load, "ucomiss">, PS, VEX;
2468 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2469 load, "ucomisd">, PD, VEX;
2471 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2472 load, "comiss">, PS, VEX;
2473 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2474 load, "comisd">, PD, VEX;
2476 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2478 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2481 let Pattern = []<dag> in {
2482 defm COMISS : sse12_ord_cmp<0x2F, FR32, undef, f32, f32mem, loadf32,
2484 defm COMISD : sse12_ord_cmp<0x2F, FR64, undef, f64, f64mem, loadf64,
2488 let isCodeGenOnly = 1 in {
2489 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2490 load, "ucomiss">, PS;
2491 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2492 load, "ucomisd">, PD;
2494 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2496 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2499 } // Defs = [EFLAGS]
2501 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2502 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2503 Operand CC, Intrinsic Int, string asm,
2504 string asm_alt, Domain d, ImmLeaf immLeaf,
2505 PatFrag ld_frag, OpndItins itins = SSE_ALU_F32P> {
2506 let isCommutable = 1 in
2507 def rri : PIi8<0xC2, MRMSrcReg,
2508 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2509 [(set RC:$dst, (Int RC:$src1, RC:$src2, immLeaf:$cc))],
2512 def rmi : PIi8<0xC2, MRMSrcMem,
2513 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2514 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2), immLeaf:$cc))],
2516 Sched<[WriteFAddLd, ReadAfterLd]>;
2518 // Accept explicit immediate argument form instead of comparison code.
2519 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2520 def rri_alt : PIi8<0xC2, MRMSrcReg,
2521 (outs RC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
2522 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2524 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2525 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
2526 asm_alt, [], itins.rm, d>,
2527 Sched<[WriteFAddLd, ReadAfterLd]>;
2531 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2532 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2533 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2534 SSEPackedSingle, i8immZExt5, loadv4f32>, PS, VEX_4V;
2535 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2536 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2537 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2538 SSEPackedDouble, i8immZExt5, loadv2f64>, PD, VEX_4V;
2539 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2540 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2541 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2542 SSEPackedSingle, i8immZExt5, loadv8f32>, PS, VEX_4V, VEX_L;
2543 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2544 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2545 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2546 SSEPackedDouble, i8immZExt5, loadv4f64>, PD, VEX_4V, VEX_L;
2547 let Constraints = "$src1 = $dst" in {
2548 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2549 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2550 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2551 SSEPackedSingle, i8immZExt5, memopv4f32, SSE_ALU_F32P>, PS;
2552 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2553 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2554 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2555 SSEPackedDouble, i8immZExt5, memopv2f64, SSE_ALU_F64P>, PD;
2558 let Predicates = [HasAVX] in {
2559 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2560 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2561 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (loadv4f32 addr:$src2), imm:$cc)),
2562 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2563 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2564 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2565 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (loadv2f64 addr:$src2), imm:$cc)),
2566 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2568 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2569 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2570 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (loadv8f32 addr:$src2), imm:$cc)),
2571 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2572 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2573 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2574 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (loadv4f64 addr:$src2), imm:$cc)),
2575 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2578 let Predicates = [UseSSE1] in {
2579 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2580 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2581 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memopv4f32 addr:$src2), imm:$cc)),
2582 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2585 let Predicates = [UseSSE2] in {
2586 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2587 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2588 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memopv2f64 addr:$src2), imm:$cc)),
2589 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2592 //===----------------------------------------------------------------------===//
2593 // SSE 1 & 2 - Shuffle Instructions
2594 //===----------------------------------------------------------------------===//
2596 /// sse12_shuffle - sse 1 & 2 fp shuffle instructions
2597 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2598 ValueType vt, string asm, PatFrag mem_frag,
2600 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2601 (ins RC:$src1, x86memop:$src2, u8imm:$src3), asm,
2602 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2603 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2604 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2605 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2606 (ins RC:$src1, RC:$src2, u8imm:$src3), asm,
2607 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2608 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2609 Sched<[WriteFShuffle]>;
2612 let Predicates = [HasAVX, NoVLX] in {
2613 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2614 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2615 loadv4f32, SSEPackedSingle>, PS, VEX_4V;
2616 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2617 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2618 loadv8f32, SSEPackedSingle>, PS, VEX_4V, VEX_L;
2619 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2620 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2621 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
2622 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2623 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2624 loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L;
2626 let Constraints = "$src1 = $dst" in {
2627 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2628 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2629 memopv4f32, SSEPackedSingle>, PS;
2630 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2631 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2632 memopv2f64, SSEPackedDouble>, PD;
2635 let Predicates = [HasAVX, NoVLX] in {
2636 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2637 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2638 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2639 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2640 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2642 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2643 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2644 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2645 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2646 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2649 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2650 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2651 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2652 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2653 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2655 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2656 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2657 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2658 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2659 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2662 let Predicates = [UseSSE1] in {
2663 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2664 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2665 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2666 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2667 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2670 let Predicates = [UseSSE2] in {
2671 // Generic SHUFPD patterns
2672 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2673 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2674 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2675 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2676 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2679 //===----------------------------------------------------------------------===//
2680 // SSE 1 & 2 - Unpack FP Instructions
2681 //===----------------------------------------------------------------------===//
2683 /// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave
2684 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2685 PatFrag mem_frag, RegisterClass RC,
2686 X86MemOperand x86memop, string asm,
2688 def rr : PI<opc, MRMSrcReg,
2689 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2691 (vt (OpNode RC:$src1, RC:$src2)))],
2692 IIC_SSE_UNPCK, d>, Sched<[WriteFShuffle]>;
2693 def rm : PI<opc, MRMSrcMem,
2694 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2696 (vt (OpNode RC:$src1,
2697 (mem_frag addr:$src2))))],
2699 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2702 let Predicates = [HasAVX, NoVLX] in {
2703 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2704 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2705 SSEPackedSingle>, PS, VEX_4V;
2706 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2707 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2708 SSEPackedDouble>, PD, VEX_4V;
2709 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2710 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2711 SSEPackedSingle>, PS, VEX_4V;
2712 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2713 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2714 SSEPackedDouble>, PD, VEX_4V;
2716 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2717 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2718 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2719 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2720 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2721 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2722 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2723 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2724 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2725 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2726 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2727 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2728 }// Predicates = [HasAVX, NoVLX]
2729 let Constraints = "$src1 = $dst" in {
2730 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2731 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2732 SSEPackedSingle>, PS;
2733 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2734 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2735 SSEPackedDouble>, PD;
2736 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2737 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2738 SSEPackedSingle>, PS;
2739 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2740 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2741 SSEPackedDouble>, PD;
2742 } // Constraints = "$src1 = $dst"
2744 let Predicates = [HasAVX1Only] in {
2745 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2746 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2747 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2748 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2749 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2750 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2751 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2752 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2754 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2755 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2756 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2757 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2758 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2759 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2760 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2761 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2764 //===----------------------------------------------------------------------===//
2765 // SSE 1 & 2 - Extract Floating-Point Sign mask
2766 //===----------------------------------------------------------------------===//
2768 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2769 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2771 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2772 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2773 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2774 Sched<[WriteVecLogic]>;
2777 let Predicates = [HasAVX] in {
2778 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2779 "movmskps", SSEPackedSingle>, PS, VEX;
2780 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2781 "movmskpd", SSEPackedDouble>, PD, VEX;
2782 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2783 "movmskps", SSEPackedSingle>, PS,
2785 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2786 "movmskpd", SSEPackedDouble>, PD,
2789 def : Pat<(i32 (X86fgetsign FR32:$src)),
2790 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2791 def : Pat<(i64 (X86fgetsign FR32:$src)),
2792 (SUBREG_TO_REG (i64 0),
2793 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2794 def : Pat<(i32 (X86fgetsign FR64:$src)),
2795 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2796 def : Pat<(i64 (X86fgetsign FR64:$src)),
2797 (SUBREG_TO_REG (i64 0),
2798 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2801 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2802 SSEPackedSingle>, PS;
2803 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2804 SSEPackedDouble>, PD;
2806 def : Pat<(i32 (X86fgetsign FR32:$src)),
2807 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2808 Requires<[UseSSE1]>;
2809 def : Pat<(i64 (X86fgetsign FR32:$src)),
2810 (SUBREG_TO_REG (i64 0),
2811 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2812 Requires<[UseSSE1]>;
2813 def : Pat<(i32 (X86fgetsign FR64:$src)),
2814 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2815 Requires<[UseSSE2]>;
2816 def : Pat<(i64 (X86fgetsign FR64:$src)),
2817 (SUBREG_TO_REG (i64 0),
2818 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2819 Requires<[UseSSE2]>;
2821 //===---------------------------------------------------------------------===//
2822 // SSE2 - Packed Integer Logical Instructions
2823 //===---------------------------------------------------------------------===//
2825 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2827 /// PDI_binop_rm - Simple SSE2 binary operator.
2828 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2829 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2830 X86MemOperand x86memop, OpndItins itins,
2831 bit IsCommutable, bit Is2Addr> {
2832 let isCommutable = IsCommutable in
2833 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2834 (ins RC:$src1, RC:$src2),
2836 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2837 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2838 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2839 Sched<[itins.Sched]>;
2840 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2841 (ins RC:$src1, x86memop:$src2),
2843 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2844 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2845 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2846 (bitconvert (memop_frag addr:$src2)))))],
2848 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2850 } // ExeDomain = SSEPackedInt
2852 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2853 ValueType OpVT128, ValueType OpVT256,
2854 OpndItins itins, bit IsCommutable = 0, Predicate prd> {
2855 let Predicates = [HasAVX, prd] in
2856 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2857 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2859 let Constraints = "$src1 = $dst" in
2860 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2861 memopv2i64, i128mem, itins, IsCommutable, 1>;
2863 let Predicates = [HasAVX2, prd] in
2864 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2865 OpVT256, VR256, loadv4i64, i256mem, itins,
2866 IsCommutable, 0>, VEX_4V, VEX_L;
2869 // These are ordered here for pattern ordering requirements with the fp versions
2871 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64,
2872 SSE_VEC_BIT_ITINS_P, 1, NoVLX>;
2873 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64,
2874 SSE_VEC_BIT_ITINS_P, 1, NoVLX>;
2875 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64,
2876 SSE_VEC_BIT_ITINS_P, 1, NoVLX>;
2877 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2878 SSE_VEC_BIT_ITINS_P, 0, NoVLX>;
2880 //===----------------------------------------------------------------------===//
2881 // SSE 1 & 2 - Logical Instructions
2882 //===----------------------------------------------------------------------===//
2884 // Multiclass for scalars using the X86 logical operation aliases for FP.
2885 multiclass sse12_fp_packed_scalar_logical_alias<
2886 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2887 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2888 FR32, f32, f128mem, loadf32_128, SSEPackedSingle, itins, 0>,
2891 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2892 FR64, f64, f128mem, loadf64_128, SSEPackedDouble, itins, 0>,
2895 let Constraints = "$src1 = $dst" in {
2896 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2897 f32, f128mem, memopfsf32_128, SSEPackedSingle, itins>, PS;
2899 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2900 f64, f128mem, memopfsf64_128, SSEPackedDouble, itins>, PD;
2904 let isCodeGenOnly = 1 in {
2905 defm FsAND : sse12_fp_packed_scalar_logical_alias<0x54, "and", X86fand,
2907 defm FsOR : sse12_fp_packed_scalar_logical_alias<0x56, "or", X86for,
2909 defm FsXOR : sse12_fp_packed_scalar_logical_alias<0x57, "xor", X86fxor,
2912 let isCommutable = 0 in
2913 defm FsANDN : sse12_fp_packed_scalar_logical_alias<0x55, "andn", X86fandn,
2917 // Multiclass for vectors using the X86 logical operation aliases for FP.
2918 multiclass sse12_fp_packed_vector_logical_alias<
2919 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2920 let Predicates = [HasAVX, NoVLX] in {
2921 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2922 VR128, v4f32, f128mem, loadv4f32, SSEPackedSingle, itins, 0>,
2925 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2926 VR128, v2f64, f128mem, loadv2f64, SSEPackedDouble, itins, 0>,
2929 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2930 VR256, v8f32, f256mem, loadv8f32, SSEPackedSingle, itins, 0>,
2933 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2934 VR256, v4f64, f256mem, loadv4f64, SSEPackedDouble, itins, 0>,
2938 let Constraints = "$src1 = $dst" in {
2939 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2940 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins>,
2943 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2944 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins>,
2949 let isCodeGenOnly = 1 in {
2950 defm FvAND : sse12_fp_packed_vector_logical_alias<0x54, "and", X86fand,
2952 defm FvOR : sse12_fp_packed_vector_logical_alias<0x56, "or", X86for,
2954 defm FvXOR : sse12_fp_packed_vector_logical_alias<0x57, "xor", X86fxor,
2957 let isCommutable = 0 in
2958 defm FvANDN : sse12_fp_packed_vector_logical_alias<0x55, "andn", X86fandn,
2962 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2964 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2966 let Predicates = [HasAVX, NoVLX] in {
2967 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2968 !strconcat(OpcodeStr, "ps"), f256mem,
2969 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2970 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2971 (loadv4i64 addr:$src2)))], 0>, PS, VEX_4V, VEX_L;
2973 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2974 !strconcat(OpcodeStr, "pd"), f256mem,
2975 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2976 (bc_v4i64 (v4f64 VR256:$src2))))],
2977 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2978 (loadv4i64 addr:$src2)))], 0>,
2981 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2982 // are all promoted to v2i64, and the patterns are covered by the int
2983 // version. This is needed in SSE only, because v2i64 isn't supported on
2984 // SSE1, but only on SSE2.
2985 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2986 !strconcat(OpcodeStr, "ps"), f128mem, [],
2987 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2988 (loadv2i64 addr:$src2)))], 0>, PS, VEX_4V;
2990 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2991 !strconcat(OpcodeStr, "pd"), f128mem,
2992 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2993 (bc_v2i64 (v2f64 VR128:$src2))))],
2994 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2995 (loadv2i64 addr:$src2)))], 0>,
2999 let Constraints = "$src1 = $dst" in {
3000 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
3001 !strconcat(OpcodeStr, "ps"), f128mem,
3002 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
3003 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
3004 (memopv2i64 addr:$src2)))]>, PS;
3006 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
3007 !strconcat(OpcodeStr, "pd"), f128mem,
3008 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
3009 (bc_v2i64 (v2f64 VR128:$src2))))],
3010 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
3011 (memopv2i64 addr:$src2)))]>, PD;
3015 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
3016 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
3017 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
3018 let isCommutable = 0 in
3019 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
3021 // AVX1 requires type coercions in order to fold loads directly into logical
3023 let Predicates = [HasAVX1Only] in {
3024 def : Pat<(bc_v8f32 (and VR256:$src1, (loadv4i64 addr:$src2))),
3025 (VANDPSYrm VR256:$src1, addr:$src2)>;
3026 def : Pat<(bc_v8f32 (or VR256:$src1, (loadv4i64 addr:$src2))),
3027 (VORPSYrm VR256:$src1, addr:$src2)>;
3028 def : Pat<(bc_v8f32 (xor VR256:$src1, (loadv4i64 addr:$src2))),
3029 (VXORPSYrm VR256:$src1, addr:$src2)>;
3030 def : Pat<(bc_v8f32 (X86andnp VR256:$src1, (loadv4i64 addr:$src2))),
3031 (VANDNPSYrm VR256:$src1, addr:$src2)>;
3034 //===----------------------------------------------------------------------===//
3035 // SSE 1 & 2 - Arithmetic Instructions
3036 //===----------------------------------------------------------------------===//
3038 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
3041 /// In addition, we also have a special variant of the scalar form here to
3042 /// represent the associated intrinsic operation. This form is unlike the
3043 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
3044 /// and leaves the top elements unmodified (therefore these cannot be commuted).
3046 /// These three forms can each be reg+reg or reg+mem.
3049 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
3051 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
3052 SDNode OpNode, SizeItins itins> {
3053 let Predicates = [HasAVX, NoVLX] in {
3054 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
3055 VR128, v4f32, f128mem, loadv4f32,
3056 SSEPackedSingle, itins.s, 0>, PS, VEX_4V;
3057 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
3058 VR128, v2f64, f128mem, loadv2f64,
3059 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
3061 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
3062 OpNode, VR256, v8f32, f256mem, loadv8f32,
3063 SSEPackedSingle, itins.s, 0>, PS, VEX_4V, VEX_L;
3064 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
3065 OpNode, VR256, v4f64, f256mem, loadv4f64,
3066 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
3069 let Constraints = "$src1 = $dst" in {
3070 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
3071 v4f32, f128mem, memopv4f32, SSEPackedSingle,
3073 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
3074 v2f64, f128mem, memopv2f64, SSEPackedDouble,
3079 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3081 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3082 OpNode, FR32, f32mem, SSEPackedSingle, itins.s, 0>,
3083 XS, VEX_4V, VEX_LIG;
3084 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3085 OpNode, FR64, f64mem, SSEPackedDouble, itins.d, 0>,
3086 XD, VEX_4V, VEX_LIG;
3088 let Constraints = "$src1 = $dst" in {
3089 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3090 OpNode, FR32, f32mem, SSEPackedSingle,
3092 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3093 OpNode, FR64, f64mem, SSEPackedDouble,
3098 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
3100 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3101 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3102 SSEPackedSingle, itins.s, 0>, XS, VEX_4V, VEX_LIG;
3103 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3104 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3105 SSEPackedDouble, itins.d, 0>, XD, VEX_4V, VEX_LIG;
3107 let Constraints = "$src1 = $dst" in {
3108 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3109 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3110 SSEPackedSingle, itins.s>, XS;
3111 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3112 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3113 SSEPackedDouble, itins.d>, XD;
3117 // Binary Arithmetic instructions
3118 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3119 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3120 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3121 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3122 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3123 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3124 let isCommutable = 0 in {
3125 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3126 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3127 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3128 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3129 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3130 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3131 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3132 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3133 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3134 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3135 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3136 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3139 let isCodeGenOnly = 1 in {
3140 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3141 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3142 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3143 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3146 // Patterns used to select SSE scalar fp arithmetic instructions from
3149 // (1) a scalar fp operation followed by a blend
3151 // The effect is that the backend no longer emits unnecessary vector
3152 // insert instructions immediately after SSE scalar fp instructions
3153 // like addss or mulss.
3155 // For example, given the following code:
3156 // __m128 foo(__m128 A, __m128 B) {
3161 // Previously we generated:
3162 // addss %xmm0, %xmm1
3163 // movss %xmm1, %xmm0
3166 // addss %xmm1, %xmm0
3168 // (2) a vector packed single/double fp operation followed by a vector insert
3170 // The effect is that the backend converts the packed fp instruction
3171 // followed by a vector insert into a single SSE scalar fp instruction.
3173 // For example, given the following code:
3174 // __m128 foo(__m128 A, __m128 B) {
3175 // __m128 C = A + B;
3176 // return (__m128) {c[0], a[1], a[2], a[3]};
3179 // Previously we generated:
3180 // addps %xmm0, %xmm1
3181 // movss %xmm1, %xmm0
3184 // addss %xmm1, %xmm0
3186 // TODO: Some canonicalization in lowering would simplify the number of
3187 // patterns we have to try to match.
3188 multiclass scalar_math_f32_patterns<SDNode Op, string OpcPrefix> {
3189 let Predicates = [UseSSE1] in {
3190 // extracted scalar math op with insert via movss
3191 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3192 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3194 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
3195 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3197 // vector math op with insert via movss
3198 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3199 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3200 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3203 // With SSE 4.1, blendi is preferred to movsd, so match that too.
3204 let Predicates = [UseSSE41] in {
3205 // extracted scalar math op with insert via blend
3206 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3207 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3208 FR32:$src))), (i8 1))),
3209 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
3210 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3212 // vector math op with insert via blend
3213 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3214 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3215 (!cast<I>(OpcPrefix#SSrr_Int)v4f32:$dst, v4f32:$src)>;
3219 // Repeat everything for AVX, except for the movss + scalar combo...
3220 // because that one shouldn't occur with AVX codegen?
3221 let Predicates = [HasAVX] in {
3222 // extracted scalar math op with insert via blend
3223 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3224 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3225 FR32:$src))), (i8 1))),
3226 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst,
3227 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3229 // vector math op with insert via movss
3230 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3231 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3232 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3234 // vector math op with insert via blend
3235 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3236 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3237 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3241 defm : scalar_math_f32_patterns<fadd, "ADD">;
3242 defm : scalar_math_f32_patterns<fsub, "SUB">;
3243 defm : scalar_math_f32_patterns<fmul, "MUL">;
3244 defm : scalar_math_f32_patterns<fdiv, "DIV">;
3246 multiclass scalar_math_f64_patterns<SDNode Op, string OpcPrefix> {
3247 let Predicates = [UseSSE2] in {
3248 // extracted scalar math op with insert via movsd
3249 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3250 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3252 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
3253 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3255 // vector math op with insert via movsd
3256 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3257 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3258 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3261 // With SSE 4.1, blendi is preferred to movsd, so match those too.
3262 let Predicates = [UseSSE41] in {
3263 // extracted scalar math op with insert via blend
3264 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3265 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3266 FR64:$src))), (i8 1))),
3267 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
3268 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3270 // vector math op with insert via blend
3271 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3272 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3273 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3276 // Repeat everything for AVX.
3277 let Predicates = [HasAVX] in {
3278 // extracted scalar math op with insert via movsd
3279 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3280 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3282 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
3283 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3285 // extracted scalar math op with insert via blend
3286 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3287 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3288 FR64:$src))), (i8 1))),
3289 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
3290 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3292 // vector math op with insert via movsd
3293 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3294 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3295 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3297 // vector math op with insert via blend
3298 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3299 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3300 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3304 defm : scalar_math_f64_patterns<fadd, "ADD">;
3305 defm : scalar_math_f64_patterns<fsub, "SUB">;
3306 defm : scalar_math_f64_patterns<fmul, "MUL">;
3307 defm : scalar_math_f64_patterns<fdiv, "DIV">;
3311 /// In addition, we also have a special variant of the scalar form here to
3312 /// represent the associated intrinsic operation. This form is unlike the
3313 /// plain scalar form, in that it takes an entire vector (instead of a
3314 /// scalar) and leaves the top elements undefined.
3316 /// And, we have a special variant form for a full-vector intrinsic form.
3318 let Sched = WriteFSqrt in {
3319 def SSE_SQRTPS : OpndItins<
3320 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3323 def SSE_SQRTSS : OpndItins<
3324 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3327 def SSE_SQRTPD : OpndItins<
3328 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3331 def SSE_SQRTSD : OpndItins<
3332 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3336 let Sched = WriteFRsqrt in {
3337 def SSE_RSQRTPS : OpndItins<
3338 IIC_SSE_RSQRTPS_RR, IIC_SSE_RSQRTPS_RM
3341 def SSE_RSQRTSS : OpndItins<
3342 IIC_SSE_RSQRTSS_RR, IIC_SSE_RSQRTSS_RM
3346 let Sched = WriteFRcp in {
3347 def SSE_RCPP : OpndItins<
3348 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3351 def SSE_RCPS : OpndItins<
3352 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3356 /// sse_fp_unop_s - SSE1 unops in scalar form
3357 /// For the non-AVX defs, we need $src1 to be tied to $dst because
3358 /// the HW instructions are 2 operand / destructive.
3359 multiclass sse_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3360 ValueType vt, ValueType ScalarVT,
3361 X86MemOperand x86memop, Operand vec_memop,
3362 ComplexPattern mem_cpat, Intrinsic Intr,
3363 SDNode OpNode, Domain d, OpndItins itins,
3364 Predicate target, string Suffix> {
3365 let hasSideEffects = 0 in {
3366 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1),
3367 !strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
3368 [(set RC:$dst, (OpNode RC:$src1))], itins.rr, d>, Sched<[itins.Sched]>,
3371 def m : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1),
3372 !strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
3373 [(set RC:$dst, (OpNode (load addr:$src1)))], itins.rm, d>,
3374 Sched<[itins.Sched.Folded, ReadAfterLd]>,
3375 Requires<[target, OptForSize]>;
3377 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3378 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3379 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3380 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3382 def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, vec_memop:$src2),
3383 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3384 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3388 let Predicates = [target] in {
3389 def : Pat<(vt (OpNode mem_cpat:$src)),
3390 (vt (COPY_TO_REGCLASS (vt (!cast<Instruction>(NAME#Suffix##m_Int)
3391 (vt (IMPLICIT_DEF)), mem_cpat:$src)), RC))>;
3392 // These are unary operations, but they are modeled as having 2 source operands
3393 // because the high elements of the destination are unchanged in SSE.
3394 def : Pat<(Intr VR128:$src),
3395 (!cast<Instruction>(NAME#Suffix##r_Int) VR128:$src, VR128:$src)>;
3396 def : Pat<(Intr (load addr:$src)),
3397 (vt (COPY_TO_REGCLASS(!cast<Instruction>(NAME#Suffix##m)
3398 addr:$src), VR128))>;
3399 def : Pat<(Intr mem_cpat:$src),
3400 (!cast<Instruction>(NAME#Suffix##m_Int)
3401 (vt (IMPLICIT_DEF)), mem_cpat:$src)>;
3405 multiclass avx_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3406 ValueType vt, ValueType ScalarVT,
3407 X86MemOperand x86memop, Operand vec_memop,
3408 ComplexPattern mem_cpat,
3409 Intrinsic Intr, SDNode OpNode, Domain d,
3410 OpndItins itins, string Suffix> {
3411 let hasSideEffects = 0 in {
3412 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3413 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3414 [], itins.rr, d>, Sched<[itins.Sched]>;
3416 def m : I<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3417 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3418 [], itins.rm, d>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3419 let isCodeGenOnly = 1 in {
3420 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst),
3421 (ins VR128:$src1, VR128:$src2),
3422 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3423 []>, Sched<[itins.Sched.Folded]>;
3425 def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst),
3426 (ins VR128:$src1, vec_memop:$src2),
3427 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3428 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3432 let Predicates = [UseAVX] in {
3433 def : Pat<(OpNode RC:$src), (!cast<Instruction>("V"#NAME#Suffix##r)
3434 (ScalarVT (IMPLICIT_DEF)), RC:$src)>;
3436 def : Pat<(vt (OpNode mem_cpat:$src)),
3437 (!cast<Instruction>("V"#NAME#Suffix##m_Int) (vt (IMPLICIT_DEF)),
3441 let Predicates = [HasAVX] in {
3442 def : Pat<(Intr VR128:$src),
3443 (!cast<Instruction>("V"#NAME#Suffix##r_Int) (vt (IMPLICIT_DEF)),
3446 def : Pat<(Intr mem_cpat:$src),
3447 (!cast<Instruction>("V"#NAME#Suffix##m_Int)
3448 (vt (IMPLICIT_DEF)), mem_cpat:$src)>;
3450 let Predicates = [UseAVX, OptForSize] in
3451 def : Pat<(ScalarVT (OpNode (load addr:$src))),
3452 (!cast<Instruction>("V"#NAME#Suffix##m) (ScalarVT (IMPLICIT_DEF)),
3456 /// sse1_fp_unop_p - SSE1 unops in packed form.
3457 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3459 let Predicates = [HasAVX] in {
3460 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3461 !strconcat("v", OpcodeStr,
3462 "ps\t{$src, $dst|$dst, $src}"),
3463 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3464 itins.rr>, VEX, Sched<[itins.Sched]>;
3465 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3466 !strconcat("v", OpcodeStr,
3467 "ps\t{$src, $dst|$dst, $src}"),
3468 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3469 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3470 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3471 !strconcat("v", OpcodeStr,
3472 "ps\t{$src, $dst|$dst, $src}"),
3473 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3474 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3475 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3476 !strconcat("v", OpcodeStr,
3477 "ps\t{$src, $dst|$dst, $src}"),
3478 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3479 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3482 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3483 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3484 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3485 Sched<[itins.Sched]>;
3486 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3487 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3488 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3489 Sched<[itins.Sched.Folded]>;
3492 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3493 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3494 SDNode OpNode, OpndItins itins> {
3495 let Predicates = [HasAVX] in {
3496 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3497 !strconcat("v", OpcodeStr,
3498 "pd\t{$src, $dst|$dst, $src}"),
3499 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3500 itins.rr>, VEX, Sched<[itins.Sched]>;
3501 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3502 !strconcat("v", OpcodeStr,
3503 "pd\t{$src, $dst|$dst, $src}"),
3504 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3505 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3506 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3507 !strconcat("v", OpcodeStr,
3508 "pd\t{$src, $dst|$dst, $src}"),
3509 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3510 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3511 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3512 !strconcat("v", OpcodeStr,
3513 "pd\t{$src, $dst|$dst, $src}"),
3514 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3515 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3518 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3519 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3520 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3521 Sched<[itins.Sched]>;
3522 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3523 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3524 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3525 Sched<[itins.Sched.Folded]>;
3528 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3530 defm SS : sse_fp_unop_s<opc, OpcodeStr##ss, FR32, v4f32, f32, f32mem,
3531 ssmem, sse_load_f32,
3532 !cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
3533 SSEPackedSingle, itins, UseSSE1, "SS">, XS;
3534 defm V#NAME#SS : avx_fp_unop_s<opc, "v"#OpcodeStr##ss, FR32, v4f32, f32,
3535 f32mem, ssmem, sse_load_f32,
3536 !cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
3537 SSEPackedSingle, itins, "SS">, XS, VEX_4V, VEX_LIG;
3540 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3542 defm SD : sse_fp_unop_s<opc, OpcodeStr##sd, FR64, v2f64, f64, f64mem,
3543 sdmem, sse_load_f64,
3544 !cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
3545 OpNode, SSEPackedDouble, itins, UseSSE2, "SD">, XD;
3546 defm V#NAME#SD : avx_fp_unop_s<opc, "v"#OpcodeStr##sd, FR64, v2f64, f64,
3547 f64mem, sdmem, sse_load_f64,
3548 !cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
3549 OpNode, SSEPackedDouble, itins, "SD">,
3550 XD, VEX_4V, VEX_LIG;
3554 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSS>,
3555 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3556 sse2_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSD>,
3557 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3559 // Reciprocal approximations. Note that these typically require refinement
3560 // in order to obtain suitable precision.
3561 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, SSE_RSQRTSS>,
3562 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_RSQRTPS>;
3563 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, SSE_RCPS>,
3564 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>;
3566 // There is no f64 version of the reciprocal approximation instructions.
3568 // TODO: We should add *scalar* op patterns for these just like we have for
3569 // the binops above. If the binop and unop patterns could all be unified
3570 // that would be even better.
3572 multiclass scalar_unary_math_patterns<Intrinsic Intr, string OpcPrefix,
3573 SDNode Move, ValueType VT,
3574 Predicate BasePredicate> {
3575 let Predicates = [BasePredicate] in {
3576 def : Pat<(VT (Move VT:$dst, (Intr VT:$src))),
3577 (!cast<I>(OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3580 // With SSE 4.1, blendi is preferred to movs*, so match that too.
3581 let Predicates = [UseSSE41] in {
3582 def : Pat<(VT (X86Blendi VT:$dst, (Intr VT:$src), (i8 1))),
3583 (!cast<I>(OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3586 // Repeat for AVX versions of the instructions.
3587 let Predicates = [HasAVX] in {
3588 def : Pat<(VT (Move VT:$dst, (Intr VT:$src))),
3589 (!cast<I>("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3591 def : Pat<(VT (X86Blendi VT:$dst, (Intr VT:$src), (i8 1))),
3592 (!cast<I>("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3596 defm : scalar_unary_math_patterns<int_x86_sse_rcp_ss, "RCPSS", X86Movss,
3598 defm : scalar_unary_math_patterns<int_x86_sse_rsqrt_ss, "RSQRTSS", X86Movss,
3600 defm : scalar_unary_math_patterns<int_x86_sse_sqrt_ss, "SQRTSS", X86Movss,
3602 defm : scalar_unary_math_patterns<int_x86_sse2_sqrt_sd, "SQRTSD", X86Movsd,
3606 //===----------------------------------------------------------------------===//
3607 // SSE 1 & 2 - Non-temporal stores
3608 //===----------------------------------------------------------------------===//
3610 let AddedComplexity = 400 in { // Prefer non-temporal versions
3611 let SchedRW = [WriteStore] in {
3612 let Predicates = [HasAVX, NoVLX] in {
3613 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3614 (ins f128mem:$dst, VR128:$src),
3615 "movntps\t{$src, $dst|$dst, $src}",
3616 [(alignednontemporalstore (v4f32 VR128:$src),
3618 IIC_SSE_MOVNT>, VEX;
3619 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3620 (ins f128mem:$dst, VR128:$src),
3621 "movntpd\t{$src, $dst|$dst, $src}",
3622 [(alignednontemporalstore (v2f64 VR128:$src),
3624 IIC_SSE_MOVNT>, VEX;
3626 let ExeDomain = SSEPackedInt in
3627 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3628 (ins f128mem:$dst, VR128:$src),
3629 "movntdq\t{$src, $dst|$dst, $src}",
3630 [(alignednontemporalstore (v2i64 VR128:$src),
3632 IIC_SSE_MOVNT>, VEX;
3634 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3635 (ins f256mem:$dst, VR256:$src),
3636 "movntps\t{$src, $dst|$dst, $src}",
3637 [(alignednontemporalstore (v8f32 VR256:$src),
3639 IIC_SSE_MOVNT>, VEX, VEX_L;
3640 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3641 (ins f256mem:$dst, VR256:$src),
3642 "movntpd\t{$src, $dst|$dst, $src}",
3643 [(alignednontemporalstore (v4f64 VR256:$src),
3645 IIC_SSE_MOVNT>, VEX, VEX_L;
3646 let ExeDomain = SSEPackedInt in
3647 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3648 (ins f256mem:$dst, VR256:$src),
3649 "movntdq\t{$src, $dst|$dst, $src}",
3650 [(alignednontemporalstore (v4i64 VR256:$src),
3652 IIC_SSE_MOVNT>, VEX, VEX_L;
3655 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3656 "movntps\t{$src, $dst|$dst, $src}",
3657 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3659 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3660 "movntpd\t{$src, $dst|$dst, $src}",
3661 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3664 let ExeDomain = SSEPackedInt in
3665 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3666 "movntdq\t{$src, $dst|$dst, $src}",
3667 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3670 // There is no AVX form for instructions below this point
3671 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3672 "movnti{l}\t{$src, $dst|$dst, $src}",
3673 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3675 PS, Requires<[HasSSE2]>;
3676 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3677 "movnti{q}\t{$src, $dst|$dst, $src}",
3678 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3680 PS, Requires<[HasSSE2]>;
3681 } // SchedRW = [WriteStore]
3683 let Predicates = [HasAVX2, NoVLX] in {
3684 def : Pat<(alignednontemporalstore (v8i32 VR256:$src), addr:$dst),
3685 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3686 def : Pat<(alignednontemporalstore (v16i16 VR256:$src), addr:$dst),
3687 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3688 def : Pat<(alignednontemporalstore (v32i8 VR256:$src), addr:$dst),
3689 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3692 let Predicates = [HasAVX, NoVLX] in {
3693 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3694 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3695 def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst),
3696 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3697 def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst),
3698 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3701 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3702 (MOVNTDQmr addr:$dst, VR128:$src)>;
3703 def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst),
3704 (MOVNTDQmr addr:$dst, VR128:$src)>;
3705 def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst),
3706 (MOVNTDQmr addr:$dst, VR128:$src)>;
3708 } // AddedComplexity
3710 //===----------------------------------------------------------------------===//
3711 // SSE 1 & 2 - Prefetch and memory fence
3712 //===----------------------------------------------------------------------===//
3714 // Prefetch intrinsic.
3715 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3716 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3717 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3718 IIC_SSE_PREFETCH>, TB;
3719 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3720 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3721 IIC_SSE_PREFETCH>, TB;
3722 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3723 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3724 IIC_SSE_PREFETCH>, TB;
3725 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3726 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3727 IIC_SSE_PREFETCH>, TB;
3730 // FIXME: How should flush instruction be modeled?
3731 let SchedRW = [WriteLoad] in {
3733 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3734 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3735 IIC_SSE_PREFETCH>, PS, Requires<[HasSSE2]>;
3738 let SchedRW = [WriteNop] in {
3739 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3740 // was introduced with SSE2, it's backward compatible.
3741 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3742 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3743 OBXS, Requires<[HasSSE2]>;
3746 let SchedRW = [WriteFence] in {
3747 // Load, store, and memory fence
3748 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3749 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3750 PS, Requires<[HasSSE1]>;
3751 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3752 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3753 TB, Requires<[HasSSE2]>;
3754 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3755 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3756 TB, Requires<[HasSSE2]>;
3759 def : Pat<(X86SFence), (SFENCE)>;
3760 def : Pat<(X86LFence), (LFENCE)>;
3761 def : Pat<(X86MFence), (MFENCE)>;
3763 //===----------------------------------------------------------------------===//
3764 // SSE 1 & 2 - Load/Store XCSR register
3765 //===----------------------------------------------------------------------===//
3767 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3768 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3769 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3770 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3771 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3772 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3774 let Predicates = [UseSSE1] in {
3775 def LDMXCSR : I<0xAE, MRM2m, (outs), (ins i32mem:$src),
3776 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3777 IIC_SSE_LDMXCSR>, TB, Sched<[WriteLoad]>;
3778 def STMXCSR : I<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3779 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3780 IIC_SSE_STMXCSR>, TB, Sched<[WriteStore]>;
3783 //===---------------------------------------------------------------------===//
3784 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3785 //===---------------------------------------------------------------------===//
3787 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3789 let hasSideEffects = 0, SchedRW = [WriteMove] in {
3790 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3791 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3793 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3794 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3796 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3797 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3799 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3800 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3805 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
3806 SchedRW = [WriteMove] in {
3807 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3808 "movdqa\t{$src, $dst|$dst, $src}", [],
3811 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3812 "movdqa\t{$src, $dst|$dst, $src}", [],
3813 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3814 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3815 "movdqu\t{$src, $dst|$dst, $src}", [],
3818 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3819 "movdqu\t{$src, $dst|$dst, $src}", [],
3820 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3823 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3824 hasSideEffects = 0, SchedRW = [WriteLoad] in {
3825 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3826 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3828 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3829 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3831 let Predicates = [HasAVX] in {
3832 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3833 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3835 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3836 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3841 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
3842 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3843 (ins i128mem:$dst, VR128:$src),
3844 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3846 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3847 (ins i256mem:$dst, VR256:$src),
3848 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3850 let Predicates = [HasAVX] in {
3851 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3852 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3854 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3855 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3860 let SchedRW = [WriteMove] in {
3861 let hasSideEffects = 0 in
3862 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3863 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3865 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3866 "movdqu\t{$src, $dst|$dst, $src}",
3867 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3870 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
3871 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3872 "movdqa\t{$src, $dst|$dst, $src}", [],
3875 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3876 "movdqu\t{$src, $dst|$dst, $src}",
3877 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3881 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3882 hasSideEffects = 0, SchedRW = [WriteLoad] in {
3883 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3884 "movdqa\t{$src, $dst|$dst, $src}",
3885 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3887 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3888 "movdqu\t{$src, $dst|$dst, $src}",
3889 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3891 XS, Requires<[UseSSE2]>;
3894 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
3895 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3896 "movdqa\t{$src, $dst|$dst, $src}",
3897 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3899 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3900 "movdqu\t{$src, $dst|$dst, $src}",
3901 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3903 XS, Requires<[UseSSE2]>;
3906 } // ExeDomain = SSEPackedInt
3908 let Predicates = [HasAVX] in {
3909 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3910 (VMOVDQUmr addr:$dst, VR128:$src)>;
3911 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3912 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3914 let Predicates = [UseSSE2] in
3915 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3916 (MOVDQUmr addr:$dst, VR128:$src)>;
3918 //===---------------------------------------------------------------------===//
3919 // SSE2 - Packed Integer Arithmetic Instructions
3920 //===---------------------------------------------------------------------===//
3922 let Sched = WriteVecIMul in
3923 def SSE_PMADD : OpndItins<
3924 IIC_SSE_PMADD, IIC_SSE_PMADD
3927 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3929 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3930 RegisterClass RC, PatFrag memop_frag,
3931 X86MemOperand x86memop,
3933 bit IsCommutable = 0,
3935 let isCommutable = IsCommutable in
3936 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3937 (ins RC:$src1, RC:$src2),
3939 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3940 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3941 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
3942 Sched<[itins.Sched]>;
3943 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3944 (ins RC:$src1, x86memop:$src2),
3946 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3947 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3948 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3949 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3952 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3953 Intrinsic IntId256, OpndItins itins,
3954 bit IsCommutable = 0> {
3955 let Predicates = [HasAVX] in
3956 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3957 VR128, loadv2i64, i128mem, itins,
3958 IsCommutable, 0>, VEX_4V;
3960 let Constraints = "$src1 = $dst" in
3961 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3962 i128mem, itins, IsCommutable, 1>;
3964 let Predicates = [HasAVX2] in
3965 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3966 VR256, loadv4i64, i256mem, itins,
3967 IsCommutable, 0>, VEX_4V, VEX_L;
3970 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3971 string OpcodeStr, SDNode OpNode,
3972 SDNode OpNode2, RegisterClass RC,
3973 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3974 PatFrag ld_frag, ShiftOpndItins itins,
3976 // src2 is always 128-bit
3977 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3978 (ins RC:$src1, VR128:$src2),
3980 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3981 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3982 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3983 itins.rr>, Sched<[WriteVecShift]>;
3984 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3985 (ins RC:$src1, i128mem:$src2),
3987 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3988 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3989 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3990 (bc_frag (ld_frag addr:$src2)))))], itins.rm>,
3991 Sched<[WriteVecShiftLd, ReadAfterLd]>;
3992 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3993 (ins RC:$src1, u8imm:$src2),
3995 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3996 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3997 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
3998 Sched<[WriteVecShift]>;
4001 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
4002 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
4003 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
4004 PatFrag memop_frag, X86MemOperand x86memop,
4006 bit IsCommutable = 0, bit Is2Addr = 1> {
4007 let isCommutable = IsCommutable in
4008 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4009 (ins RC:$src1, RC:$src2),
4011 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4012 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4013 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
4014 Sched<[itins.Sched]>;
4015 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4016 (ins RC:$src1, x86memop:$src2),
4018 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4019 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4020 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
4021 (bitconvert (memop_frag addr:$src2)))))]>,
4022 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4024 } // ExeDomain = SSEPackedInt
4026 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
4027 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4028 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
4029 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4030 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
4031 SSE_INTALU_ITINS_P, 1, NoVLX>;
4032 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
4033 SSE_INTALUQ_ITINS_P, 1, NoVLX>;
4034 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
4035 SSE_INTMUL_ITINS_P, 1, NoVLX_Or_NoBWI>;
4036 defm PMULHUW : PDI_binop_all<0xE4, "pmulhuw", mulhu, v8i16, v16i16,
4037 SSE_INTMUL_ITINS_P, 1, NoVLX_Or_NoBWI>;
4038 defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16,
4039 SSE_INTMUL_ITINS_P, 1, NoVLX_Or_NoBWI>;
4040 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
4041 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4042 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
4043 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4044 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
4045 SSE_INTALU_ITINS_P, 0, NoVLX>;
4046 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
4047 SSE_INTALUQ_ITINS_P, 0, NoVLX>;
4048 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
4049 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4050 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
4051 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4052 defm PMINUB : PDI_binop_all<0xDA, "pminub", umin, v16i8, v32i8,
4053 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4054 defm PMINSW : PDI_binop_all<0xEA, "pminsw", smin, v8i16, v16i16,
4055 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4056 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", umax, v16i8, v32i8,
4057 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4058 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", smax, v8i16, v16i16,
4059 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4062 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4063 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4064 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4065 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4066 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4067 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4068 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4069 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4070 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4071 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4072 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4073 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4074 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4075 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4076 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
4077 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
4078 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
4079 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
4080 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
4081 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
4083 let Predicates = [HasAVX2] in
4084 def : Pat<(v32i8 (X86psadbw (v32i8 VR256:$src1),
4085 (v32i8 VR256:$src2))),
4086 (VPSADBWYrr VR256:$src2, VR256:$src1)>;
4088 let Predicates = [HasAVX] in
4089 def : Pat<(v16i8 (X86psadbw (v16i8 VR128:$src1),
4090 (v16i8 VR128:$src2))),
4091 (VPSADBWrr VR128:$src2, VR128:$src1)>;
4093 def : Pat<(v16i8 (X86psadbw (v16i8 VR128:$src1),
4094 (v16i8 VR128:$src2))),
4095 (PSADBWrr VR128:$src2, VR128:$src1)>;
4097 let Predicates = [HasAVX] in
4098 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4099 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4101 let Predicates = [HasAVX2] in
4102 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4103 VR256, loadv4i64, i256mem,
4104 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4105 let Constraints = "$src1 = $dst" in
4106 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4107 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4109 //===---------------------------------------------------------------------===//
4110 // SSE2 - Packed Integer Logical Instructions
4111 //===---------------------------------------------------------------------===//
4113 let Predicates = [HasAVX, NoVLX] in {
4114 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4115 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4116 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4117 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4118 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4119 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4120 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4121 VR128, v2i64, v2i64, bc_v2i64, loadv2i64,
4122 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4124 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4125 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4126 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4127 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4128 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4129 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4130 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4131 VR128, v2i64, v2i64, bc_v2i64, loadv2i64,
4132 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4134 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4135 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4136 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4137 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4138 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4139 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4140 } // Predicates = [HasAVX]
4142 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] ,
4143 Predicates = [HasAVX, NoVLX_Or_NoBWI]in {
4144 // 128-bit logical shifts.
4145 def VPSLLDQri : PDIi8<0x73, MRM7r,
4146 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4147 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4149 (v2i64 (X86vshldq VR128:$src1, (i8 imm:$src2))))]>,
4151 def VPSRLDQri : PDIi8<0x73, MRM3r,
4152 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4153 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4155 (v2i64 (X86vshrdq VR128:$src1, (i8 imm:$src2))))]>,
4157 // PSRADQri doesn't exist in SSE[1-3].
4158 } // Predicates = [HasAVX, NoVLX_Or_NoBWI]
4160 let Predicates = [HasAVX2, NoVLX] in {
4161 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4162 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4163 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4164 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4165 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4166 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4167 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4168 VR256, v4i64, v2i64, bc_v2i64, loadv2i64,
4169 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4171 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4172 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4173 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4174 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4175 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4176 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4177 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4178 VR256, v4i64, v2i64, bc_v2i64, loadv2i64,
4179 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4181 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4182 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4183 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4184 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4185 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4186 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4187 }// Predicates = [HasAVX2]
4189 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 ,
4190 Predicates = [HasAVX2, NoVLX_Or_NoBWI] in {
4191 // 256-bit logical shifts.
4192 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4193 (outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
4194 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4196 (v4i64 (X86vshldq VR256:$src1, (i8 imm:$src2))))]>,
4198 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4199 (outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
4200 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4202 (v4i64 (X86vshrdq VR256:$src1, (i8 imm:$src2))))]>,
4204 // PSRADQYri doesn't exist in SSE[1-3].
4205 } // Predicates = [HasAVX2, NoVLX_Or_NoBWI]
4207 let Constraints = "$src1 = $dst" in {
4208 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4209 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4210 SSE_INTSHIFT_ITINS_P>;
4211 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4212 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4213 SSE_INTSHIFT_ITINS_P>;
4214 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4215 VR128, v2i64, v2i64, bc_v2i64, memopv2i64,
4216 SSE_INTSHIFT_ITINS_P>;
4218 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4219 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4220 SSE_INTSHIFT_ITINS_P>;
4221 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4222 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4223 SSE_INTSHIFT_ITINS_P>;
4224 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4225 VR128, v2i64, v2i64, bc_v2i64, memopv2i64,
4226 SSE_INTSHIFT_ITINS_P>;
4228 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4229 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4230 SSE_INTSHIFT_ITINS_P>;
4231 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4232 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4233 SSE_INTSHIFT_ITINS_P>;
4235 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 in {
4236 // 128-bit logical shifts.
4237 def PSLLDQri : PDIi8<0x73, MRM7r,
4238 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4239 "pslldq\t{$src2, $dst|$dst, $src2}",
4241 (v2i64 (X86vshldq VR128:$src1, (i8 imm:$src2))))],
4242 IIC_SSE_INTSHDQ_P_RI>;
4243 def PSRLDQri : PDIi8<0x73, MRM3r,
4244 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4245 "psrldq\t{$src2, $dst|$dst, $src2}",
4247 (v2i64 (X86vshrdq VR128:$src1, (i8 imm:$src2))))],
4248 IIC_SSE_INTSHDQ_P_RI>;
4249 // PSRADQri doesn't exist in SSE[1-3].
4251 } // Constraints = "$src1 = $dst"
4253 //===---------------------------------------------------------------------===//
4254 // SSE2 - Packed Integer Comparison Instructions
4255 //===---------------------------------------------------------------------===//
4257 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4258 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4259 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4260 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4261 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4262 SSE_INTALU_ITINS_P, 1, NoVLX>;
4263 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4264 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4265 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4266 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4267 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4268 SSE_INTALU_ITINS_P, 0, NoVLX>;
4270 //===---------------------------------------------------------------------===//
4271 // SSE2 - Packed Integer Shuffle Instructions
4272 //===---------------------------------------------------------------------===//
4274 let ExeDomain = SSEPackedInt in {
4275 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4277 let Predicates = [HasAVX] in {
4278 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4279 (ins VR128:$src1, u8imm:$src2),
4280 !strconcat("v", OpcodeStr,
4281 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4283 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4284 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4285 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4286 (ins i128mem:$src1, u8imm:$src2),
4287 !strconcat("v", OpcodeStr,
4288 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4290 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4291 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4292 Sched<[WriteShuffleLd]>;
4295 let Predicates = [HasAVX2] in {
4296 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4297 (ins VR256:$src1, u8imm:$src2),
4298 !strconcat("v", OpcodeStr,
4299 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4301 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4302 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4303 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4304 (ins i256mem:$src1, u8imm:$src2),
4305 !strconcat("v", OpcodeStr,
4306 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4308 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4309 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4310 Sched<[WriteShuffleLd]>;
4313 let Predicates = [UseSSE2] in {
4314 def ri : Ii8<0x70, MRMSrcReg,
4315 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4316 !strconcat(OpcodeStr,
4317 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4319 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4320 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4321 def mi : Ii8<0x70, MRMSrcMem,
4322 (outs VR128:$dst), (ins i128mem:$src1, u8imm:$src2),
4323 !strconcat(OpcodeStr,
4324 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4326 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4327 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4328 Sched<[WriteShuffleLd, ReadAfterLd]>;
4331 } // ExeDomain = SSEPackedInt
4333 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
4334 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4335 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4337 let Predicates = [HasAVX] in {
4338 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4339 (VPSHUFDmi addr:$src1, imm:$imm)>;
4340 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4341 (VPSHUFDri VR128:$src1, imm:$imm)>;
4344 let Predicates = [UseSSE2] in {
4345 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4346 (PSHUFDmi addr:$src1, imm:$imm)>;
4347 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4348 (PSHUFDri VR128:$src1, imm:$imm)>;
4351 //===---------------------------------------------------------------------===//
4352 // Packed Integer Pack Instructions (SSE & AVX)
4353 //===---------------------------------------------------------------------===//
4355 let ExeDomain = SSEPackedInt in {
4356 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4357 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4358 PatFrag ld_frag, bit Is2Addr = 1> {
4359 def rr : PDI<opc, MRMSrcReg,
4360 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4362 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4363 !strconcat(OpcodeStr,
4364 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4366 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4367 Sched<[WriteShuffle]>;
4368 def rm : PDI<opc, MRMSrcMem,
4369 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4371 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4372 !strconcat(OpcodeStr,
4373 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4375 (OutVT (OpNode VR128:$src1,
4376 (bc_frag (ld_frag addr:$src2)))))]>,
4377 Sched<[WriteShuffleLd, ReadAfterLd]>;
4380 multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4381 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4382 def Yrr : PDI<opc, MRMSrcReg,
4383 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4384 !strconcat(OpcodeStr,
4385 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4387 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4388 Sched<[WriteShuffle]>;
4389 def Yrm : PDI<opc, MRMSrcMem,
4390 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4391 !strconcat(OpcodeStr,
4392 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4394 (OutVT (OpNode VR256:$src1,
4395 (bc_frag (loadv4i64 addr:$src2)))))]>,
4396 Sched<[WriteShuffleLd, ReadAfterLd]>;
4399 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4400 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4401 PatFrag ld_frag, bit Is2Addr = 1> {
4402 def rr : SS48I<opc, MRMSrcReg,
4403 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4405 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4406 !strconcat(OpcodeStr,
4407 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4409 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4410 Sched<[WriteShuffle]>;
4411 def rm : SS48I<opc, MRMSrcMem,
4412 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4414 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4415 !strconcat(OpcodeStr,
4416 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4418 (OutVT (OpNode VR128:$src1,
4419 (bc_frag (ld_frag addr:$src2)))))]>,
4420 Sched<[WriteShuffleLd, ReadAfterLd]>;
4423 multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4424 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4425 def Yrr : SS48I<opc, MRMSrcReg,
4426 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4427 !strconcat(OpcodeStr,
4428 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4430 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4431 Sched<[WriteShuffle]>;
4432 def Yrm : SS48I<opc, MRMSrcMem,
4433 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4434 !strconcat(OpcodeStr,
4435 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4437 (OutVT (OpNode VR256:$src1,
4438 (bc_frag (loadv4i64 addr:$src2)))))]>,
4439 Sched<[WriteShuffleLd, ReadAfterLd]>;
4442 let Predicates = [HasAVX] in {
4443 defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
4444 bc_v8i16, loadv2i64, 0>, VEX_4V;
4445 defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
4446 bc_v4i32, loadv2i64, 0>, VEX_4V;
4448 defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
4449 bc_v8i16, loadv2i64, 0>, VEX_4V;
4450 defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
4451 bc_v4i32, loadv2i64, 0>, VEX_4V;
4454 let Predicates = [HasAVX2] in {
4455 defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
4456 bc_v16i16>, VEX_4V, VEX_L;
4457 defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
4458 bc_v8i32>, VEX_4V, VEX_L;
4460 defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
4461 bc_v16i16>, VEX_4V, VEX_L;
4462 defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
4463 bc_v8i32>, VEX_4V, VEX_L;
4466 let Constraints = "$src1 = $dst" in {
4467 defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss,
4468 bc_v8i16, memopv2i64>;
4469 defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss,
4470 bc_v4i32, memopv2i64>;
4472 defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus,
4473 bc_v8i16, memopv2i64>;
4475 let Predicates = [HasSSE41] in
4476 defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus,
4477 bc_v4i32, memopv2i64>;
4479 } // ExeDomain = SSEPackedInt
4481 //===---------------------------------------------------------------------===//
4482 // SSE2 - Packed Integer Unpack Instructions
4483 //===---------------------------------------------------------------------===//
4485 let ExeDomain = SSEPackedInt in {
4486 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4487 SDNode OpNode, PatFrag bc_frag, PatFrag ld_frag,
4489 def rr : PDI<opc, MRMSrcReg,
4490 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4492 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4493 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4494 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4495 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4496 def rm : PDI<opc, MRMSrcMem,
4497 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4499 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4500 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4501 [(set VR128:$dst, (OpNode VR128:$src1,
4502 (bc_frag (ld_frag addr:$src2))))],
4504 Sched<[WriteShuffleLd, ReadAfterLd]>;
4507 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4508 SDNode OpNode, PatFrag bc_frag> {
4509 def Yrr : PDI<opc, MRMSrcReg,
4510 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4511 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4512 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4513 Sched<[WriteShuffle]>;
4514 def Yrm : PDI<opc, MRMSrcMem,
4515 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4516 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4517 [(set VR256:$dst, (OpNode VR256:$src1,
4518 (bc_frag (loadv4i64 addr:$src2))))]>,
4519 Sched<[WriteShuffleLd, ReadAfterLd]>;
4523 let Predicates = [HasAVX, NoVLX_Or_NoBWI] in {
4524 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4525 bc_v16i8, loadv2i64, 0>, VEX_4V;
4526 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4527 bc_v8i16, loadv2i64, 0>, VEX_4V;
4528 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4529 bc_v16i8, loadv2i64, 0>, VEX_4V;
4530 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4531 bc_v8i16, loadv2i64, 0>, VEX_4V;
4533 let Predicates = [HasAVX, NoVLX] in {
4534 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4535 bc_v4i32, loadv2i64, 0>, VEX_4V;
4536 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4537 bc_v2i64, loadv2i64, 0>, VEX_4V;
4538 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4539 bc_v4i32, loadv2i64, 0>, VEX_4V;
4540 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4541 bc_v2i64, loadv2i64, 0>, VEX_4V;
4544 let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in {
4545 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4546 bc_v32i8>, VEX_4V, VEX_L;
4547 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4548 bc_v16i16>, VEX_4V, VEX_L;
4549 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4550 bc_v32i8>, VEX_4V, VEX_L;
4551 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4552 bc_v16i16>, VEX_4V, VEX_L;
4554 let Predicates = [HasAVX2, NoVLX] in {
4555 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4556 bc_v8i32>, VEX_4V, VEX_L;
4557 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4558 bc_v4i64>, VEX_4V, VEX_L;
4559 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4560 bc_v8i32>, VEX_4V, VEX_L;
4561 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4562 bc_v4i64>, VEX_4V, VEX_L;
4565 let Constraints = "$src1 = $dst" in {
4566 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4567 bc_v16i8, memopv2i64>;
4568 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4569 bc_v8i16, memopv2i64>;
4570 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4571 bc_v4i32, memopv2i64>;
4572 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4573 bc_v2i64, memopv2i64>;
4575 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4576 bc_v16i8, memopv2i64>;
4577 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4578 bc_v8i16, memopv2i64>;
4579 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4580 bc_v4i32, memopv2i64>;
4581 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4582 bc_v2i64, memopv2i64>;
4584 } // ExeDomain = SSEPackedInt
4586 //===---------------------------------------------------------------------===//
4587 // SSE2 - Packed Integer Extract and Insert
4588 //===---------------------------------------------------------------------===//
4590 let ExeDomain = SSEPackedInt in {
4591 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4592 def rri : Ii8<0xC4, MRMSrcReg,
4593 (outs VR128:$dst), (ins VR128:$src1,
4594 GR32orGR64:$src2, u8imm:$src3),
4596 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4597 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4599 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4600 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4601 def rmi : Ii8<0xC4, MRMSrcMem,
4602 (outs VR128:$dst), (ins VR128:$src1,
4603 i16mem:$src2, u8imm:$src3),
4605 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4606 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4608 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4609 imm:$src3))], IIC_SSE_PINSRW>,
4610 Sched<[WriteShuffleLd, ReadAfterLd]>;
4614 let Predicates = [HasAVX, NoBWI] in
4615 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4616 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4617 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4618 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4619 imm:$src2))]>, PD, VEX,
4620 Sched<[WriteShuffle]>;
4621 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4622 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4623 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4624 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4625 imm:$src2))], IIC_SSE_PEXTRW>,
4626 Sched<[WriteShuffleLd, ReadAfterLd]>;
4629 let Predicates = [HasAVX, NoBWI] in
4630 defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V;
4632 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4633 defm PINSRW : sse2_pinsrw, PD;
4635 } // ExeDomain = SSEPackedInt
4637 //===---------------------------------------------------------------------===//
4638 // SSE2 - Packed Mask Creation
4639 //===---------------------------------------------------------------------===//
4641 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4643 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4645 "pmovmskb\t{$src, $dst|$dst, $src}",
4646 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4647 IIC_SSE_MOVMSK>, VEX;
4649 let Predicates = [HasAVX2] in {
4650 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4652 "pmovmskb\t{$src, $dst|$dst, $src}",
4653 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4657 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4658 "pmovmskb\t{$src, $dst|$dst, $src}",
4659 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4662 } // ExeDomain = SSEPackedInt
4664 //===---------------------------------------------------------------------===//
4665 // SSE2 - Conditional Store
4666 //===---------------------------------------------------------------------===//
4668 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4670 let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
4671 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4672 (ins VR128:$src, VR128:$mask),
4673 "maskmovdqu\t{$mask, $src|$src, $mask}",
4674 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4675 IIC_SSE_MASKMOV>, VEX;
4676 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4677 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4678 (ins VR128:$src, VR128:$mask),
4679 "maskmovdqu\t{$mask, $src|$src, $mask}",
4680 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4681 IIC_SSE_MASKMOV>, VEX;
4683 let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
4684 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4685 "maskmovdqu\t{$mask, $src|$src, $mask}",
4686 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4688 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4689 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4690 "maskmovdqu\t{$mask, $src|$src, $mask}",
4691 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4694 } // ExeDomain = SSEPackedInt
4696 //===---------------------------------------------------------------------===//
4697 // SSE2 - Move Doubleword
4698 //===---------------------------------------------------------------------===//
4700 //===---------------------------------------------------------------------===//
4701 // Move Int Doubleword to Packed Double Int
4703 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4704 "movd\t{$src, $dst|$dst, $src}",
4706 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4707 VEX, Sched<[WriteMove]>;
4708 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4709 "movd\t{$src, $dst|$dst, $src}",
4711 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4713 VEX, Sched<[WriteLoad]>;
4714 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4715 "movq\t{$src, $dst|$dst, $src}",
4717 (v2i64 (scalar_to_vector GR64:$src)))],
4718 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4719 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
4720 def VMOV64toPQIrm : VRS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4721 "movq\t{$src, $dst|$dst, $src}",
4722 [], IIC_SSE_MOVDQ>, VEX, Sched<[WriteLoad]>;
4723 let isCodeGenOnly = 1 in
4724 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4725 "movq\t{$src, $dst|$dst, $src}",
4726 [(set FR64:$dst, (bitconvert GR64:$src))],
4727 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4729 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4730 "movd\t{$src, $dst|$dst, $src}",
4732 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4734 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4735 "movd\t{$src, $dst|$dst, $src}",
4737 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4738 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4739 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4740 "mov{d|q}\t{$src, $dst|$dst, $src}",
4742 (v2i64 (scalar_to_vector GR64:$src)))],
4743 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4744 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
4745 def MOV64toPQIrm : RS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4746 "mov{d|q}\t{$src, $dst|$dst, $src}",
4747 [], IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4748 let isCodeGenOnly = 1 in
4749 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4750 "mov{d|q}\t{$src, $dst|$dst, $src}",
4751 [(set FR64:$dst, (bitconvert GR64:$src))],
4752 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4754 //===---------------------------------------------------------------------===//
4755 // Move Int Doubleword to Single Scalar
4757 let isCodeGenOnly = 1 in {
4758 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4759 "movd\t{$src, $dst|$dst, $src}",
4760 [(set FR32:$dst, (bitconvert GR32:$src))],
4761 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4763 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4764 "movd\t{$src, $dst|$dst, $src}",
4765 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4767 VEX, Sched<[WriteLoad]>;
4768 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4769 "movd\t{$src, $dst|$dst, $src}",
4770 [(set FR32:$dst, (bitconvert GR32:$src))],
4771 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4773 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4774 "movd\t{$src, $dst|$dst, $src}",
4775 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4776 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4779 //===---------------------------------------------------------------------===//
4780 // Move Packed Doubleword Int to Packed Double Int
4782 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4783 "movd\t{$src, $dst|$dst, $src}",
4784 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4785 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4787 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4788 (ins i32mem:$dst, VR128:$src),
4789 "movd\t{$src, $dst|$dst, $src}",
4790 [(store (i32 (vector_extract (v4i32 VR128:$src),
4791 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4792 VEX, Sched<[WriteStore]>;
4793 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4794 "movd\t{$src, $dst|$dst, $src}",
4795 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4796 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4798 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4799 "movd\t{$src, $dst|$dst, $src}",
4800 [(store (i32 (vector_extract (v4i32 VR128:$src),
4801 (iPTR 0))), addr:$dst)],
4802 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4804 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
4805 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4807 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
4808 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4810 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
4811 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4813 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
4814 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4816 //===---------------------------------------------------------------------===//
4817 // Move Packed Doubleword Int first element to Doubleword Int
4819 let SchedRW = [WriteMove] in {
4820 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4821 "movq\t{$src, $dst|$dst, $src}",
4822 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4827 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4828 "mov{d|q}\t{$src, $dst|$dst, $src}",
4829 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4834 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
4835 def VMOVPQIto64rm : VRS2I<0x7E, MRMDestMem, (outs i64mem:$dst),
4836 (ins VR128:$src), "movq\t{$src, $dst|$dst, $src}",
4837 [], IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4838 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
4839 def MOVPQIto64rm : RS2I<0x7E, MRMDestMem, (outs i64mem:$dst), (ins VR128:$src),
4840 "mov{d|q}\t{$src, $dst|$dst, $src}",
4841 [], IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4843 //===---------------------------------------------------------------------===//
4844 // Bitcast FR64 <-> GR64
4846 let isCodeGenOnly = 1 in {
4847 let Predicates = [UseAVX] in
4848 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4849 "movq\t{$src, $dst|$dst, $src}",
4850 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4851 VEX, Sched<[WriteLoad]>;
4852 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4853 "movq\t{$src, $dst|$dst, $src}",
4854 [(set GR64:$dst, (bitconvert FR64:$src))],
4855 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4856 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4857 "movq\t{$src, $dst|$dst, $src}",
4858 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4859 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4861 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4862 "movq\t{$src, $dst|$dst, $src}",
4863 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4864 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4865 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4866 "mov{d|q}\t{$src, $dst|$dst, $src}",
4867 [(set GR64:$dst, (bitconvert FR64:$src))],
4868 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4869 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4870 "movq\t{$src, $dst|$dst, $src}",
4871 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4872 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4875 //===---------------------------------------------------------------------===//
4876 // Move Scalar Single to Double Int
4878 let isCodeGenOnly = 1 in {
4879 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4880 "movd\t{$src, $dst|$dst, $src}",
4881 [(set GR32:$dst, (bitconvert FR32:$src))],
4882 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4883 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4884 "movd\t{$src, $dst|$dst, $src}",
4885 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4886 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4887 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4888 "movd\t{$src, $dst|$dst, $src}",
4889 [(set GR32:$dst, (bitconvert FR32:$src))],
4890 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4891 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4892 "movd\t{$src, $dst|$dst, $src}",
4893 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4894 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4897 //===---------------------------------------------------------------------===//
4898 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4900 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
4901 let AddedComplexity = 15 in {
4902 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4903 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
4904 [(set VR128:$dst, (v2i64 (X86vzmovl
4905 (v2i64 (scalar_to_vector GR64:$src)))))],
4908 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4909 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4910 [(set VR128:$dst, (v2i64 (X86vzmovl
4911 (v2i64 (scalar_to_vector GR64:$src)))))],
4914 } // isCodeGenOnly, SchedRW
4916 let Predicates = [UseAVX] in {
4917 let AddedComplexity = 15 in
4918 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4919 (VMOVDI2PDIrr GR32:$src)>;
4921 // AVX 128-bit movd/movq instructions write zeros in the high 128-bit part.
4922 // These instructions also write zeros in the high part of a 256-bit register.
4923 let AddedComplexity = 20 in {
4924 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4925 (VMOVDI2PDIrm addr:$src)>;
4926 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4927 (VMOVDI2PDIrm addr:$src)>;
4928 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4929 (VMOVDI2PDIrm addr:$src)>;
4930 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4931 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
4932 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrm addr:$src), sub_xmm)>;
4934 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4935 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4936 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4937 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
4938 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4939 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4940 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4943 let Predicates = [UseSSE2] in {
4944 let AddedComplexity = 15 in
4945 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4946 (MOVDI2PDIrr GR32:$src)>;
4948 let AddedComplexity = 20 in {
4949 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4950 (MOVDI2PDIrm addr:$src)>;
4951 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4952 (MOVDI2PDIrm addr:$src)>;
4953 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4954 (MOVDI2PDIrm addr:$src)>;
4958 // These are the correct encodings of the instructions so that we know how to
4959 // read correct assembly, even though we continue to emit the wrong ones for
4960 // compatibility with Darwin's buggy assembler.
4961 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4962 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4963 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4964 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4965 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
4966 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4967 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4968 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4969 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4971 //===---------------------------------------------------------------------===//
4972 // SSE2 - Move Quadword
4973 //===---------------------------------------------------------------------===//
4975 //===---------------------------------------------------------------------===//
4976 // Move Quadword Int to Packed Quadword Int
4979 let ExeDomain = SSEPackedInt, SchedRW = [WriteLoad] in {
4980 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4981 "vmovq\t{$src, $dst|$dst, $src}",
4983 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4984 VEX, Requires<[UseAVX]>;
4985 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4986 "movq\t{$src, $dst|$dst, $src}",
4988 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4990 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4991 } // ExeDomain, SchedRW
4993 //===---------------------------------------------------------------------===//
4994 // Move Packed Quadword Int to Quadword Int
4996 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4997 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4998 "movq\t{$src, $dst|$dst, $src}",
4999 [(store (i64 (vector_extract (v2i64 VR128:$src),
5000 (iPTR 0))), addr:$dst)],
5001 IIC_SSE_MOVDQ>, VEX;
5002 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
5003 "movq\t{$src, $dst|$dst, $src}",
5004 [(store (i64 (vector_extract (v2i64 VR128:$src),
5005 (iPTR 0))), addr:$dst)],
5007 } // ExeDomain, SchedRW
5009 // For disassembler only
5010 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
5011 SchedRW = [WriteVecLogic] in {
5012 def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5013 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, VEX;
5014 def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5015 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>;
5018 //===---------------------------------------------------------------------===//
5019 // Store / copy lower 64-bits of a XMM register.
5021 let Predicates = [HasAVX] in
5022 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5023 (VMOVPQI2QImr addr:$dst, VR128:$src)>;
5024 let Predicates = [UseSSE2] in
5025 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5026 (MOVPQI2QImr addr:$dst, VR128:$src)>;
5028 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1, AddedComplexity = 20 in {
5029 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5030 "vmovq\t{$src, $dst|$dst, $src}",
5032 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5033 (loadi64 addr:$src))))))],
5035 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
5037 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5038 "movq\t{$src, $dst|$dst, $src}",
5040 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5041 (loadi64 addr:$src))))))],
5043 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
5044 } // ExeDomain, isCodeGenOnly, AddedComplexity
5046 let Predicates = [UseAVX], AddedComplexity = 20 in {
5047 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5048 (VMOVZQI2PQIrm addr:$src)>;
5049 def : Pat<(v2i64 (X86vzload addr:$src)),
5050 (VMOVZQI2PQIrm addr:$src)>;
5051 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
5052 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
5053 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>;
5056 let Predicates = [UseSSE2], AddedComplexity = 20 in {
5057 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5058 (MOVZQI2PQIrm addr:$src)>;
5059 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
5062 let Predicates = [HasAVX] in {
5063 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
5064 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
5065 def : Pat<(v4i64 (X86vzload addr:$src)),
5066 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
5069 //===---------------------------------------------------------------------===//
5070 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
5071 // IA32 document. movq xmm1, xmm2 does clear the high bits.
5073 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
5074 let AddedComplexity = 15 in
5075 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5076 "vmovq\t{$src, $dst|$dst, $src}",
5077 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5079 XS, VEX, Requires<[UseAVX]>;
5080 let AddedComplexity = 15 in
5081 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5082 "movq\t{$src, $dst|$dst, $src}",
5083 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5085 XS, Requires<[UseSSE2]>;
5086 } // ExeDomain, SchedRW
5088 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
5089 let AddedComplexity = 20 in
5090 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5091 "vmovq\t{$src, $dst|$dst, $src}",
5092 [(set VR128:$dst, (v2i64 (X86vzmovl
5093 (loadv2i64 addr:$src))))],
5095 XS, VEX, Requires<[UseAVX]>;
5096 let AddedComplexity = 20 in {
5097 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5098 "movq\t{$src, $dst|$dst, $src}",
5099 [(set VR128:$dst, (v2i64 (X86vzmovl
5100 (loadv2i64 addr:$src))))],
5102 XS, Requires<[UseSSE2]>;
5104 } // ExeDomain, isCodeGenOnly, SchedRW
5106 let AddedComplexity = 20 in {
5107 let Predicates = [UseAVX] in {
5108 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5109 (VMOVZPQILo2PQIrr VR128:$src)>;
5111 let Predicates = [UseSSE2] in {
5112 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5113 (MOVZPQILo2PQIrr VR128:$src)>;
5117 //===---------------------------------------------------------------------===//
5118 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
5119 //===---------------------------------------------------------------------===//
5120 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
5121 ValueType vt, RegisterClass RC, PatFrag mem_frag,
5122 X86MemOperand x86memop> {
5123 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5124 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5125 [(set RC:$dst, (vt (OpNode RC:$src)))],
5126 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5127 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5128 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5129 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
5130 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5133 let Predicates = [HasAVX] in {
5134 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5135 v4f32, VR128, loadv4f32, f128mem>, VEX;
5136 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5137 v4f32, VR128, loadv4f32, f128mem>, VEX;
5138 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5139 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5140 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5141 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5143 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
5144 memopv4f32, f128mem>;
5145 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5146 memopv4f32, f128mem>;
5148 let Predicates = [HasAVX] in {
5149 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5150 (VMOVSHDUPrr VR128:$src)>;
5151 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
5152 (VMOVSHDUPrm addr:$src)>;
5153 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5154 (VMOVSLDUPrr VR128:$src)>;
5155 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
5156 (VMOVSLDUPrm addr:$src)>;
5157 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5158 (VMOVSHDUPYrr VR256:$src)>;
5159 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
5160 (VMOVSHDUPYrm addr:$src)>;
5161 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5162 (VMOVSLDUPYrr VR256:$src)>;
5163 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
5164 (VMOVSLDUPYrm addr:$src)>;
5167 let Predicates = [UseSSE3] in {
5168 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5169 (MOVSHDUPrr VR128:$src)>;
5170 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5171 (MOVSHDUPrm addr:$src)>;
5172 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5173 (MOVSLDUPrr VR128:$src)>;
5174 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5175 (MOVSLDUPrm addr:$src)>;
5178 //===---------------------------------------------------------------------===//
5179 // SSE3 - Replicate Double FP - MOVDDUP
5180 //===---------------------------------------------------------------------===//
5182 multiclass sse3_replicate_dfp<string OpcodeStr> {
5183 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5184 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5185 [(set VR128:$dst, (v2f64 (X86Movddup VR128:$src)))],
5186 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5187 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5188 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5191 (scalar_to_vector (loadf64 addr:$src)))))],
5192 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5195 // FIXME: Merge with above classe when there're patterns for the ymm version
5196 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5197 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5198 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5199 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5200 Sched<[WriteFShuffle]>;
5201 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5202 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5205 (scalar_to_vector (loadf64 addr:$src)))))]>,
5209 let Predicates = [HasAVX] in {
5210 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5211 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5214 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5216 let Predicates = [HasAVX] in {
5217 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5218 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5219 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5220 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5221 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5222 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5223 def : Pat<(X86Movddup (bc_v2f64
5224 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5225 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5228 def : Pat<(X86Movddup (loadv4f64 addr:$src)),
5229 (VMOVDDUPYrm addr:$src)>;
5230 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5231 (VMOVDDUPYrm addr:$src)>;
5232 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5233 (VMOVDDUPYrm addr:$src)>;
5234 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5235 (VMOVDDUPYrr VR256:$src)>;
5238 let Predicates = [UseAVX, OptForSize] in {
5239 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
5240 (VMOVDDUPrm addr:$src)>;
5241 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
5242 (VMOVDDUPrm addr:$src)>;
5245 let Predicates = [UseSSE3] in {
5246 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5247 (MOVDDUPrm addr:$src)>;
5248 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5249 (MOVDDUPrm addr:$src)>;
5250 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5251 (MOVDDUPrm addr:$src)>;
5252 def : Pat<(X86Movddup (bc_v2f64
5253 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5254 (MOVDDUPrm addr:$src)>;
5257 //===---------------------------------------------------------------------===//
5258 // SSE3 - Move Unaligned Integer
5259 //===---------------------------------------------------------------------===//
5261 let SchedRW = [WriteLoad] in {
5262 let Predicates = [HasAVX] in {
5263 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5264 "vlddqu\t{$src, $dst|$dst, $src}",
5265 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5266 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5267 "vlddqu\t{$src, $dst|$dst, $src}",
5268 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5271 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5272 "lddqu\t{$src, $dst|$dst, $src}",
5273 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5277 //===---------------------------------------------------------------------===//
5278 // SSE3 - Arithmetic
5279 //===---------------------------------------------------------------------===//
5281 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5282 X86MemOperand x86memop, OpndItins itins,
5283 PatFrag ld_frag, bit Is2Addr = 1> {
5284 def rr : I<0xD0, MRMSrcReg,
5285 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5287 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5288 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5289 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5290 Sched<[itins.Sched]>;
5291 def rm : I<0xD0, MRMSrcMem,
5292 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5294 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5295 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5296 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))], itins.rr>,
5297 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5300 let Predicates = [HasAVX] in {
5301 let ExeDomain = SSEPackedSingle in {
5302 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5303 f128mem, SSE_ALU_F32P, loadv4f32, 0>, XD, VEX_4V;
5304 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5305 f256mem, SSE_ALU_F32P, loadv8f32, 0>, XD, VEX_4V, VEX_L;
5307 let ExeDomain = SSEPackedDouble in {
5308 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5309 f128mem, SSE_ALU_F64P, loadv2f64, 0>, PD, VEX_4V;
5310 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5311 f256mem, SSE_ALU_F64P, loadv4f64, 0>, PD, VEX_4V, VEX_L;
5314 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5315 let ExeDomain = SSEPackedSingle in
5316 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5317 f128mem, SSE_ALU_F32P, memopv4f32>, XD;
5318 let ExeDomain = SSEPackedDouble in
5319 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5320 f128mem, SSE_ALU_F64P, memopv2f64>, PD;
5323 // Patterns used to select 'addsub' instructions.
5324 let Predicates = [HasAVX] in {
5325 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5326 (VADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5327 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (loadv4f32 addr:$rhs))),
5328 (VADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5329 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5330 (VADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5331 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (loadv2f64 addr:$rhs))),
5332 (VADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5334 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 VR256:$rhs))),
5335 (VADDSUBPSYrr VR256:$lhs, VR256:$rhs)>;
5336 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (loadv8f32 addr:$rhs))),
5337 (VADDSUBPSYrm VR256:$lhs, f256mem:$rhs)>;
5338 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 VR256:$rhs))),
5339 (VADDSUBPDYrr VR256:$lhs, VR256:$rhs)>;
5340 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (loadv4f64 addr:$rhs))),
5341 (VADDSUBPDYrm VR256:$lhs, f256mem:$rhs)>;
5344 let Predicates = [UseSSE3] in {
5345 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5346 (ADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5347 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (memopv4f32 addr:$rhs))),
5348 (ADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5349 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5350 (ADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5351 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (memopv2f64 addr:$rhs))),
5352 (ADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5355 //===---------------------------------------------------------------------===//
5356 // SSE3 Instructions
5357 //===---------------------------------------------------------------------===//
5360 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5361 X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
5363 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5365 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5366 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5367 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5370 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5372 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5373 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5374 [(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
5375 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5377 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5378 X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
5380 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5382 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5383 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5384 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5387 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5389 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5390 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5391 [(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
5392 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5395 let Predicates = [HasAVX] in {
5396 let ExeDomain = SSEPackedSingle in {
5397 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5398 X86fhadd, loadv4f32, 0>, VEX_4V;
5399 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5400 X86fhsub, loadv4f32, 0>, VEX_4V;
5401 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5402 X86fhadd, loadv8f32, 0>, VEX_4V, VEX_L;
5403 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5404 X86fhsub, loadv8f32, 0>, VEX_4V, VEX_L;
5406 let ExeDomain = SSEPackedDouble in {
5407 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5408 X86fhadd, loadv2f64, 0>, VEX_4V;
5409 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5410 X86fhsub, loadv2f64, 0>, VEX_4V;
5411 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5412 X86fhadd, loadv4f64, 0>, VEX_4V, VEX_L;
5413 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5414 X86fhsub, loadv4f64, 0>, VEX_4V, VEX_L;
5418 let Constraints = "$src1 = $dst" in {
5419 let ExeDomain = SSEPackedSingle in {
5420 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd,
5422 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub,
5425 let ExeDomain = SSEPackedDouble in {
5426 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd,
5428 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub,
5433 //===---------------------------------------------------------------------===//
5434 // SSSE3 - Packed Absolute Instructions
5435 //===---------------------------------------------------------------------===//
5438 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5439 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
5441 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5443 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5444 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5445 Sched<[WriteVecALU]>;
5447 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5449 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5452 (bitconvert (ld_frag addr:$src))))], IIC_SSE_PABS_RM>,
5453 Sched<[WriteVecALULd]>;
5456 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5457 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5458 Intrinsic IntId256> {
5459 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5461 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5462 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5463 Sched<[WriteVecALU]>;
5465 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5467 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5470 (bitconvert (loadv4i64 addr:$src))))]>,
5471 Sched<[WriteVecALULd]>;
5474 // Helper fragments to match sext vXi1 to vXiY.
5475 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5477 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5478 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5479 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5481 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5482 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5484 let Predicates = [HasAVX] in {
5485 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", int_x86_ssse3_pabs_b_128,
5487 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", int_x86_ssse3_pabs_w_128,
5489 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", int_x86_ssse3_pabs_d_128,
5493 (bc_v2i64 (v16i1sextv16i8)),
5494 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5495 (VPABSBrr128 VR128:$src)>;
5497 (bc_v2i64 (v8i1sextv8i16)),
5498 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5499 (VPABSWrr128 VR128:$src)>;
5501 (bc_v2i64 (v4i1sextv4i32)),
5502 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5503 (VPABSDrr128 VR128:$src)>;
5506 let Predicates = [HasAVX2] in {
5507 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5508 int_x86_avx2_pabs_b>, VEX, VEX_L;
5509 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5510 int_x86_avx2_pabs_w>, VEX, VEX_L;
5511 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5512 int_x86_avx2_pabs_d>, VEX, VEX_L;
5515 (bc_v4i64 (v32i1sextv32i8)),
5516 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5517 (VPABSBrr256 VR256:$src)>;
5519 (bc_v4i64 (v16i1sextv16i16)),
5520 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5521 (VPABSWrr256 VR256:$src)>;
5523 (bc_v4i64 (v8i1sextv8i32)),
5524 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5525 (VPABSDrr256 VR256:$src)>;
5528 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", int_x86_ssse3_pabs_b_128,
5530 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", int_x86_ssse3_pabs_w_128,
5532 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", int_x86_ssse3_pabs_d_128,
5535 let Predicates = [HasSSSE3] in {
5537 (bc_v2i64 (v16i1sextv16i8)),
5538 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5539 (PABSBrr128 VR128:$src)>;
5541 (bc_v2i64 (v8i1sextv8i16)),
5542 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5543 (PABSWrr128 VR128:$src)>;
5545 (bc_v2i64 (v4i1sextv4i32)),
5546 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5547 (PABSDrr128 VR128:$src)>;
5550 //===---------------------------------------------------------------------===//
5551 // SSSE3 - Packed Binary Operator Instructions
5552 //===---------------------------------------------------------------------===//
5554 let Sched = WriteVecALU in {
5555 def SSE_PHADDSUBD : OpndItins<
5556 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5558 def SSE_PHADDSUBSW : OpndItins<
5559 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5561 def SSE_PHADDSUBW : OpndItins<
5562 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5565 let Sched = WriteShuffle in
5566 def SSE_PSHUFB : OpndItins<
5567 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5569 let Sched = WriteVecALU in
5570 def SSE_PSIGN : OpndItins<
5571 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5573 let Sched = WriteVecIMul in
5574 def SSE_PMULHRSW : OpndItins<
5575 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5578 /// SS3I_binop_rm - Simple SSSE3 bin op
5579 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5580 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5581 X86MemOperand x86memop, OpndItins itins,
5583 let isCommutable = 1 in
5584 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5585 (ins RC:$src1, RC:$src2),
5587 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5588 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5589 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5590 Sched<[itins.Sched]>;
5591 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5592 (ins RC:$src1, x86memop:$src2),
5594 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5595 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5597 (OpVT (OpNode RC:$src1,
5598 (bitconvert (memop_frag addr:$src2)))))], itins.rm>,
5599 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5602 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5603 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5604 Intrinsic IntId128, OpndItins itins,
5605 PatFrag ld_frag, bit Is2Addr = 1> {
5606 let isCommutable = 1 in
5607 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5608 (ins VR128:$src1, VR128:$src2),
5610 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5611 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5612 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5613 Sched<[itins.Sched]>;
5614 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5615 (ins VR128:$src1, i128mem:$src2),
5617 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5618 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5620 (IntId128 VR128:$src1,
5621 (bitconvert (ld_frag addr:$src2))))]>,
5622 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5625 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5627 X86FoldableSchedWrite Sched> {
5628 let isCommutable = 1 in
5629 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5630 (ins VR256:$src1, VR256:$src2),
5631 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5632 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5634 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5635 (ins VR256:$src1, i256mem:$src2),
5636 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5638 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
5639 Sched<[Sched.Folded, ReadAfterLd]>;
5642 let ImmT = NoImm, Predicates = [HasAVX] in {
5643 let isCommutable = 0 in {
5644 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5646 SSE_PHADDSUBW, 0>, VEX_4V;
5647 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5649 SSE_PHADDSUBD, 0>, VEX_4V;
5650 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5652 SSE_PHADDSUBW, 0>, VEX_4V;
5653 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5655 SSE_PHADDSUBD, 0>, VEX_4V;
5656 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5658 SSE_PSIGN, 0>, VEX_4V;
5659 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5661 SSE_PSIGN, 0>, VEX_4V;
5662 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5664 SSE_PSIGN, 0>, VEX_4V;
5665 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5667 SSE_PSHUFB, 0>, VEX_4V;
5668 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5669 int_x86_ssse3_phadd_sw_128,
5670 SSE_PHADDSUBSW, loadv2i64, 0>, VEX_4V;
5671 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5672 int_x86_ssse3_phsub_sw_128,
5673 SSE_PHADDSUBSW, loadv2i64, 0>, VEX_4V;
5674 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5675 int_x86_ssse3_pmadd_ub_sw_128,
5676 SSE_PMADD, loadv2i64, 0>, VEX_4V;
5678 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5679 int_x86_ssse3_pmul_hr_sw_128,
5680 SSE_PMULHRSW, loadv2i64, 0>, VEX_4V;
5683 let ImmT = NoImm, Predicates = [HasAVX2] in {
5684 let isCommutable = 0 in {
5685 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5687 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5688 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5690 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5691 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5693 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5694 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5696 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5697 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5699 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5700 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5702 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5703 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5705 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5706 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5708 SSE_PSHUFB, 0>, VEX_4V, VEX_L;
5709 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5710 int_x86_avx2_phadd_sw,
5711 WriteVecALU>, VEX_4V, VEX_L;
5712 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5713 int_x86_avx2_phsub_sw,
5714 WriteVecALU>, VEX_4V, VEX_L;
5715 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5716 int_x86_avx2_pmadd_ub_sw,
5717 WriteVecIMul>, VEX_4V, VEX_L;
5719 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5720 int_x86_avx2_pmul_hr_sw,
5721 WriteVecIMul>, VEX_4V, VEX_L;
5724 // None of these have i8 immediate fields.
5725 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5726 let isCommutable = 0 in {
5727 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5728 memopv2i64, i128mem, SSE_PHADDSUBW>;
5729 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5730 memopv2i64, i128mem, SSE_PHADDSUBD>;
5731 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5732 memopv2i64, i128mem, SSE_PHADDSUBW>;
5733 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5734 memopv2i64, i128mem, SSE_PHADDSUBD>;
5735 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5736 memopv2i64, i128mem, SSE_PSIGN>;
5737 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5738 memopv2i64, i128mem, SSE_PSIGN>;
5739 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5740 memopv2i64, i128mem, SSE_PSIGN>;
5741 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5742 memopv2i64, i128mem, SSE_PSHUFB>;
5743 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5744 int_x86_ssse3_phadd_sw_128,
5745 SSE_PHADDSUBSW, memopv2i64>;
5746 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5747 int_x86_ssse3_phsub_sw_128,
5748 SSE_PHADDSUBSW, memopv2i64>;
5749 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5750 int_x86_ssse3_pmadd_ub_sw_128,
5751 SSE_PMADD, memopv2i64>;
5753 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5754 int_x86_ssse3_pmul_hr_sw_128,
5755 SSE_PMULHRSW, memopv2i64>;
5758 //===---------------------------------------------------------------------===//
5759 // SSSE3 - Packed Align Instruction Patterns
5760 //===---------------------------------------------------------------------===//
5762 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5763 let hasSideEffects = 0 in {
5764 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5765 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
5767 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5769 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5770 [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
5772 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5773 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
5775 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5777 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5778 [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5782 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5783 let hasSideEffects = 0 in {
5784 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5785 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
5787 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5788 []>, Sched<[WriteShuffle]>;
5790 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5791 (ins VR256:$src1, i256mem:$src2, u8imm:$src3),
5793 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5794 []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5798 let Predicates = [HasAVX] in
5799 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5800 let Predicates = [HasAVX2] in
5801 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5802 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5803 defm PALIGN : ssse3_palignr<"palignr">;
5805 let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in {
5806 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5807 (VPALIGNR256rr VR256:$src1, VR256:$src2, imm:$imm)>;
5808 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5809 (VPALIGNR256rr VR256:$src1, VR256:$src2, imm:$imm)>;
5810 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5811 (VPALIGNR256rr VR256:$src1, VR256:$src2, imm:$imm)>;
5812 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5813 (VPALIGNR256rr VR256:$src1, VR256:$src2, imm:$imm)>;
5816 let Predicates = [HasAVX, NoVLX_Or_NoBWI] in {
5817 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5818 (VPALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5819 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5820 (VPALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5821 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5822 (VPALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5823 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5824 (VPALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5827 let Predicates = [UseSSSE3] in {
5828 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5829 (PALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5830 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5831 (PALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5832 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5833 (PALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5834 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5835 (PALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5838 //===---------------------------------------------------------------------===//
5839 // SSSE3 - Thread synchronization
5840 //===---------------------------------------------------------------------===//
5842 let SchedRW = [WriteSystem] in {
5843 let usesCustomInserter = 1 in {
5844 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5845 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5846 Requires<[HasSSE3]>;
5849 let Uses = [EAX, ECX, EDX] in
5850 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5851 TB, Requires<[HasSSE3]>;
5852 let Uses = [ECX, EAX] in
5853 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5854 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5855 TB, Requires<[HasSSE3]>;
5858 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
5859 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5861 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
5862 Requires<[Not64BitMode]>;
5863 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
5864 Requires<[In64BitMode]>;
5866 //===----------------------------------------------------------------------===//
5867 // SSE4.1 - Packed Move with Sign/Zero Extend
5868 //===----------------------------------------------------------------------===//
5870 multiclass SS41I_pmovx_rrrm<bits<8> opc, string OpcodeStr, X86MemOperand MemOp,
5871 RegisterClass OutRC, RegisterClass InRC,
5873 def rr : SS48I<opc, MRMSrcReg, (outs OutRC:$dst), (ins InRC:$src),
5874 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5876 Sched<[itins.Sched]>;
5878 def rm : SS48I<opc, MRMSrcMem, (outs OutRC:$dst), (ins MemOp:$src),
5879 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5881 itins.rm>, Sched<[itins.Sched.Folded]>;
5884 multiclass SS41I_pmovx_rm_all<bits<8> opc, string OpcodeStr,
5885 X86MemOperand MemOp, X86MemOperand MemYOp,
5886 OpndItins SSEItins, OpndItins AVXItins,
5887 OpndItins AVX2Itins> {
5888 defm NAME : SS41I_pmovx_rrrm<opc, OpcodeStr, MemOp, VR128, VR128, SSEItins>;
5889 let Predicates = [HasAVX, NoVLX] in
5890 defm V#NAME : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemOp,
5891 VR128, VR128, AVXItins>, VEX;
5892 let Predicates = [HasAVX2, NoVLX] in
5893 defm V#NAME#Y : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemYOp,
5894 VR256, VR128, AVX2Itins>, VEX, VEX_L;
5897 multiclass SS41I_pmovx_rm<bits<8> opc, string OpcodeStr,
5898 X86MemOperand MemOp, X86MemOperand MemYOp> {
5899 defm PMOVSX#NAME : SS41I_pmovx_rm_all<opc, !strconcat("pmovsx", OpcodeStr),
5901 SSE_INTALU_ITINS_SHUFF_P,
5902 DEFAULT_ITINS_SHUFFLESCHED,
5903 DEFAULT_ITINS_SHUFFLESCHED>;
5904 defm PMOVZX#NAME : SS41I_pmovx_rm_all<!add(opc, 0x10),
5905 !strconcat("pmovzx", OpcodeStr),
5907 SSE_INTALU_ITINS_SHUFF_P,
5908 DEFAULT_ITINS_SHUFFLESCHED,
5909 DEFAULT_ITINS_SHUFFLESCHED>;
5912 defm BW : SS41I_pmovx_rm<0x20, "bw", i64mem, i128mem>;
5913 defm WD : SS41I_pmovx_rm<0x23, "wd", i64mem, i128mem>;
5914 defm DQ : SS41I_pmovx_rm<0x25, "dq", i64mem, i128mem>;
5916 defm BD : SS41I_pmovx_rm<0x21, "bd", i32mem, i64mem>;
5917 defm WQ : SS41I_pmovx_rm<0x24, "wq", i32mem, i64mem>;
5919 defm BQ : SS41I_pmovx_rm<0x22, "bq", i16mem, i32mem>;
5922 multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy, SDNode ExtOp> {
5923 // Register-Register patterns
5924 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
5925 (!cast<I>(OpcPrefix#BWYrr) VR128:$src)>;
5926 def : Pat<(v8i32 (ExtOp (v16i8 VR128:$src))),
5927 (!cast<I>(OpcPrefix#BDYrr) VR128:$src)>;
5928 def : Pat<(v4i64 (ExtOp (v16i8 VR128:$src))),
5929 (!cast<I>(OpcPrefix#BQYrr) VR128:$src)>;
5931 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
5932 (!cast<I>(OpcPrefix#WDYrr) VR128:$src)>;
5933 def : Pat<(v4i64 (ExtOp (v8i16 VR128:$src))),
5934 (!cast<I>(OpcPrefix#WQYrr) VR128:$src)>;
5936 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
5937 (!cast<I>(OpcPrefix#DQYrr) VR128:$src)>;
5939 // On AVX2, we also support 256bit inputs.
5940 def : Pat<(v16i16 (ExtOp (v32i8 VR256:$src))),
5941 (!cast<I>(OpcPrefix#BWYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5942 def : Pat<(v8i32 (ExtOp (v32i8 VR256:$src))),
5943 (!cast<I>(OpcPrefix#BDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5944 def : Pat<(v4i64 (ExtOp (v32i8 VR256:$src))),
5945 (!cast<I>(OpcPrefix#BQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5947 def : Pat<(v8i32 (ExtOp (v16i16 VR256:$src))),
5948 (!cast<I>(OpcPrefix#WDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5949 def : Pat<(v4i64 (ExtOp (v16i16 VR256:$src))),
5950 (!cast<I>(OpcPrefix#WQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5952 def : Pat<(v4i64 (ExtOp (v8i32 VR256:$src))),
5953 (!cast<I>(OpcPrefix#DQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5955 // Simple Register-Memory patterns
5956 def : Pat<(v16i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5957 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5958 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5959 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5960 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5961 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5963 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5964 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5965 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5966 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5968 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
5969 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5971 // AVX2 Register-Memory patterns
5972 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5973 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5974 def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5975 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5976 def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5977 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5978 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5979 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5981 def : Pat<(v8i32 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
5982 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5983 def : Pat<(v8i32 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5984 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5985 def : Pat<(v8i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5986 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5987 def : Pat<(v8i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5988 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5990 def : Pat<(v4i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
5991 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5992 def : Pat<(v4i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
5993 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5994 def : Pat<(v4i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5995 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5996 def : Pat<(v4i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5997 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5999 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6000 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6001 def : Pat<(v8i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6002 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6003 def : Pat<(v8i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6004 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6005 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6006 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6008 def : Pat<(v4i64 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6009 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6010 def : Pat<(v4i64 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6011 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6012 def : Pat<(v4i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6013 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6014 def : Pat<(v4i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6015 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6017 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6018 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6019 def : Pat<(v4i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6020 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6021 def : Pat<(v4i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6022 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6023 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6024 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6027 let Predicates = [HasAVX2, NoVLX] in {
6028 defm : SS41I_pmovx_avx2_patterns<"VPMOVSX", "s", X86vsext>;
6029 defm : SS41I_pmovx_avx2_patterns<"VPMOVZX", "z", X86vzext>;
6032 // SSE4.1/AVX patterns.
6033 multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy,
6034 SDNode ExtOp, PatFrag ExtLoad16> {
6035 def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))),
6036 (!cast<I>(OpcPrefix#BWrr) VR128:$src)>;
6037 def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))),
6038 (!cast<I>(OpcPrefix#BDrr) VR128:$src)>;
6039 def : Pat<(v2i64 (ExtOp (v16i8 VR128:$src))),
6040 (!cast<I>(OpcPrefix#BQrr) VR128:$src)>;
6042 def : Pat<(v4i32 (ExtOp (v8i16 VR128:$src))),
6043 (!cast<I>(OpcPrefix#WDrr) VR128:$src)>;
6044 def : Pat<(v2i64 (ExtOp (v8i16 VR128:$src))),
6045 (!cast<I>(OpcPrefix#WQrr) VR128:$src)>;
6047 def : Pat<(v2i64 (ExtOp (v4i32 VR128:$src))),
6048 (!cast<I>(OpcPrefix#DQrr) VR128:$src)>;
6050 def : Pat<(v8i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6051 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6052 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6053 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6054 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6055 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6057 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6058 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6059 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6060 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6062 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
6063 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6065 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6066 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6067 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6068 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6069 def : Pat<(v8i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6070 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6071 def : Pat<(v8i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6072 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6073 def : Pat<(v8i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6074 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6076 def : Pat<(v4i32 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6077 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6078 def : Pat<(v4i32 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6079 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6080 def : Pat<(v4i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6081 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6082 def : Pat<(v4i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6083 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6085 def : Pat<(v2i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (ExtLoad16 addr:$src)))))),
6086 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6087 def : Pat<(v2i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6088 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6089 def : Pat<(v2i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6090 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6091 def : Pat<(v2i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6092 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6094 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6095 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6096 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6097 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6098 def : Pat<(v4i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6099 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6100 def : Pat<(v4i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6101 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6102 def : Pat<(v4i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6103 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6105 def : Pat<(v2i64 (ExtOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6106 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6107 def : Pat<(v2i64 (ExtOp (v8i16 (vzmovl_v4i32 addr:$src)))),
6108 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6109 def : Pat<(v2i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6110 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6111 def : Pat<(v2i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6112 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6114 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6115 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6116 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6117 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6118 def : Pat<(v2i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6119 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6120 def : Pat<(v2i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6121 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6122 def : Pat<(v2i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6123 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6126 let Predicates = [HasAVX, NoVLX] in {
6127 defm : SS41I_pmovx_patterns<"VPMOVSX", "s", X86vsext, extloadi32i16>;
6128 defm : SS41I_pmovx_patterns<"VPMOVZX", "z", X86vzext, loadi16_anyext>;
6131 let Predicates = [UseSSE41] in {
6132 defm : SS41I_pmovx_patterns<"PMOVSX", "s", X86vsext, extloadi32i16>;
6133 defm : SS41I_pmovx_patterns<"PMOVZX", "z", X86vzext, loadi16_anyext>;
6136 //===----------------------------------------------------------------------===//
6137 // SSE4.1 - Extract Instructions
6138 //===----------------------------------------------------------------------===//
6140 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6141 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6142 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6143 (ins VR128:$src1, u8imm:$src2),
6144 !strconcat(OpcodeStr,
6145 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6146 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6148 Sched<[WriteShuffle]>;
6149 let hasSideEffects = 0, mayStore = 1,
6150 SchedRW = [WriteShuffleLd, WriteRMW] in
6151 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6152 (ins i8mem:$dst, VR128:$src1, u8imm:$src2),
6153 !strconcat(OpcodeStr,
6154 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6155 [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
6156 imm:$src2)))), addr:$dst)]>;
6159 let Predicates = [HasAVX, NoBWI] in
6160 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6162 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6165 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6166 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6167 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
6168 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6169 (ins VR128:$src1, u8imm:$src2),
6170 !strconcat(OpcodeStr,
6171 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6172 []>, Sched<[WriteShuffle]>;
6174 let hasSideEffects = 0, mayStore = 1,
6175 SchedRW = [WriteShuffleLd, WriteRMW] in
6176 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6177 (ins i16mem:$dst, VR128:$src1, u8imm:$src2),
6178 !strconcat(OpcodeStr,
6179 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6180 [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
6181 imm:$src2)))), addr:$dst)]>;
6184 let Predicates = [HasAVX, NoBWI] in
6185 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6187 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6190 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6191 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6192 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6193 (ins VR128:$src1, u8imm:$src2),
6194 !strconcat(OpcodeStr,
6195 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6197 (extractelt (v4i32 VR128:$src1), imm:$src2))]>,
6198 Sched<[WriteShuffle]>;
6199 let SchedRW = [WriteShuffleLd, WriteRMW] in
6200 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6201 (ins i32mem:$dst, VR128:$src1, u8imm:$src2),
6202 !strconcat(OpcodeStr,
6203 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6204 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6208 let Predicates = [HasAVX, NoDQI] in
6209 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6211 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6213 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6214 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6215 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6216 (ins VR128:$src1, u8imm:$src2),
6217 !strconcat(OpcodeStr,
6218 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6220 (extractelt (v2i64 VR128:$src1), imm:$src2))]>,
6221 Sched<[WriteShuffle]>, REX_W;
6222 let SchedRW = [WriteShuffleLd, WriteRMW] in
6223 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6224 (ins i64mem:$dst, VR128:$src1, u8imm:$src2),
6225 !strconcat(OpcodeStr,
6226 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6227 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6228 addr:$dst)]>, REX_W;
6231 let Predicates = [HasAVX, NoDQI] in
6232 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6234 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6236 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6238 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6239 OpndItins itins = DEFAULT_ITINS> {
6240 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6241 (ins VR128:$src1, u8imm:$src2),
6242 !strconcat(OpcodeStr,
6243 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6244 [(set GR32orGR64:$dst,
6245 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6246 itins.rr>, Sched<[WriteFBlend]>;
6247 let SchedRW = [WriteFBlendLd, WriteRMW] in
6248 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6249 (ins f32mem:$dst, VR128:$src1, u8imm:$src2),
6250 !strconcat(OpcodeStr,
6251 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6252 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6253 addr:$dst)], itins.rm>;
6256 let ExeDomain = SSEPackedSingle in {
6257 let Predicates = [UseAVX] in
6258 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6259 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6262 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6263 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6266 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6268 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6271 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6272 Requires<[UseSSE41]>;
6274 //===----------------------------------------------------------------------===//
6275 // SSE4.1 - Insert Instructions
6276 //===----------------------------------------------------------------------===//
6278 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6279 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6280 (ins VR128:$src1, GR32orGR64:$src2, u8imm:$src3),
6282 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6284 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6286 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>,
6287 Sched<[WriteShuffle]>;
6288 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6289 (ins VR128:$src1, i8mem:$src2, u8imm:$src3),
6291 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6293 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6295 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6296 imm:$src3))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6299 let Predicates = [HasAVX, NoBWI] in
6300 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6301 let Constraints = "$src1 = $dst" in
6302 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6304 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6305 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6306 (ins VR128:$src1, GR32:$src2, u8imm:$src3),
6308 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6310 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6312 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6313 Sched<[WriteShuffle]>;
6314 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6315 (ins VR128:$src1, i32mem:$src2, u8imm:$src3),
6317 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6319 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6321 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6322 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6325 let Predicates = [HasAVX, NoDQI] in
6326 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6327 let Constraints = "$src1 = $dst" in
6328 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6330 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6331 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6332 (ins VR128:$src1, GR64:$src2, u8imm:$src3),
6334 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6336 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6338 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6339 Sched<[WriteShuffle]>;
6340 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6341 (ins VR128:$src1, i64mem:$src2, u8imm:$src3),
6343 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6345 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6347 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6348 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6351 let Predicates = [HasAVX, NoDQI] in
6352 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6353 let Constraints = "$src1 = $dst" in
6354 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6356 // insertps has a few different modes, there's the first two here below which
6357 // are optimized inserts that won't zero arbitrary elements in the destination
6358 // vector. The next one matches the intrinsic and could zero arbitrary elements
6359 // in the target vector.
6360 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6361 OpndItins itins = DEFAULT_ITINS> {
6362 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6363 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
6365 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6367 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6369 (X86insertps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6370 Sched<[WriteFShuffle]>;
6371 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6372 (ins VR128:$src1, f32mem:$src2, u8imm:$src3),
6374 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6376 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6378 (X86insertps VR128:$src1,
6379 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6380 imm:$src3))], itins.rm>,
6381 Sched<[WriteFShuffleLd, ReadAfterLd]>;
6384 let ExeDomain = SSEPackedSingle in {
6385 let Predicates = [UseAVX] in
6386 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6387 let Constraints = "$src1 = $dst" in
6388 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6391 let Predicates = [UseSSE41] in {
6392 // If we're inserting an element from a load or a null pshuf of a load,
6393 // fold the load into the insertps instruction.
6394 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd (v4f32
6395 (scalar_to_vector (loadf32 addr:$src2))), (i8 0)),
6397 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6398 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd
6399 (loadv4f32 addr:$src2), (i8 0)), imm:$src3)),
6400 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6403 let Predicates = [UseAVX] in {
6404 // If we're inserting an element from a vbroadcast of a load, fold the
6405 // load into the X86insertps instruction.
6406 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6407 (X86VBroadcast (loadf32 addr:$src2)), imm:$src3)),
6408 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6409 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6410 (X86VBroadcast (loadv4f32 addr:$src2)), imm:$src3)),
6411 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6414 //===----------------------------------------------------------------------===//
6415 // SSE4.1 - Round Instructions
6416 //===----------------------------------------------------------------------===//
6418 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6419 X86MemOperand x86memop, RegisterClass RC,
6420 PatFrag mem_frag32, PatFrag mem_frag64,
6421 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6422 let ExeDomain = SSEPackedSingle in {
6423 // Intrinsic operation, reg.
6424 // Vector intrinsic operation, reg
6425 def PSr : SS4AIi8<opcps, MRMSrcReg,
6426 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6427 !strconcat(OpcodeStr,
6428 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6429 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6430 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6432 // Vector intrinsic operation, mem
6433 def PSm : SS4AIi8<opcps, MRMSrcMem,
6434 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6435 !strconcat(OpcodeStr,
6436 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6438 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6439 IIC_SSE_ROUNDPS_MEM>, Sched<[WriteFAddLd]>;
6440 } // ExeDomain = SSEPackedSingle
6442 let ExeDomain = SSEPackedDouble in {
6443 // Vector intrinsic operation, reg
6444 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6445 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6446 !strconcat(OpcodeStr,
6447 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6448 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6449 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6451 // Vector intrinsic operation, mem
6452 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6453 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6454 !strconcat(OpcodeStr,
6455 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6457 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6458 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAddLd]>;
6459 } // ExeDomain = SSEPackedDouble
6462 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6465 Intrinsic F64Int, bit Is2Addr = 1> {
6466 let ExeDomain = GenericDomain in {
6468 let hasSideEffects = 0 in
6469 def SSr : SS4AIi8<opcss, MRMSrcReg,
6470 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32u8imm:$src3),
6472 !strconcat(OpcodeStr,
6473 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6474 !strconcat(OpcodeStr,
6475 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6476 []>, Sched<[WriteFAdd]>;
6478 // Intrinsic operation, reg.
6479 let isCodeGenOnly = 1 in
6480 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6481 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6483 !strconcat(OpcodeStr,
6484 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6485 !strconcat(OpcodeStr,
6486 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6487 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6490 // Intrinsic operation, mem.
6491 def SSm : SS4AIi8<opcss, MRMSrcMem,
6492 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32u8imm:$src3),
6494 !strconcat(OpcodeStr,
6495 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6496 !strconcat(OpcodeStr,
6497 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6499 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6500 Sched<[WriteFAddLd, ReadAfterLd]>;
6503 let hasSideEffects = 0 in
6504 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6505 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32u8imm:$src3),
6507 !strconcat(OpcodeStr,
6508 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6509 !strconcat(OpcodeStr,
6510 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6511 []>, Sched<[WriteFAdd]>;
6513 // Intrinsic operation, reg.
6514 let isCodeGenOnly = 1 in
6515 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6516 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6518 !strconcat(OpcodeStr,
6519 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6520 !strconcat(OpcodeStr,
6521 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6522 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6525 // Intrinsic operation, mem.
6526 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6527 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32u8imm:$src3),
6529 !strconcat(OpcodeStr,
6530 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6531 !strconcat(OpcodeStr,
6532 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6534 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6535 Sched<[WriteFAddLd, ReadAfterLd]>;
6536 } // ExeDomain = GenericDomain
6539 // FP round - roundss, roundps, roundsd, roundpd
6540 let Predicates = [HasAVX] in {
6542 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6543 loadv4f32, loadv2f64,
6544 int_x86_sse41_round_ps,
6545 int_x86_sse41_round_pd>, VEX;
6546 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6547 loadv8f32, loadv4f64,
6548 int_x86_avx_round_ps_256,
6549 int_x86_avx_round_pd_256>, VEX, VEX_L;
6550 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6551 int_x86_sse41_round_ss,
6552 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6555 let Predicates = [UseAVX] in {
6556 def : Pat<(ffloor FR32:$src),
6557 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x9))>;
6558 def : Pat<(f64 (ffloor FR64:$src)),
6559 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x9))>;
6560 def : Pat<(f32 (fnearbyint FR32:$src)),
6561 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6562 def : Pat<(f64 (fnearbyint FR64:$src)),
6563 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6564 def : Pat<(f32 (fceil FR32:$src)),
6565 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xA))>;
6566 def : Pat<(f64 (fceil FR64:$src)),
6567 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xA))>;
6568 def : Pat<(f32 (frint FR32:$src)),
6569 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6570 def : Pat<(f64 (frint FR64:$src)),
6571 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6572 def : Pat<(f32 (ftrunc FR32:$src)),
6573 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xB))>;
6574 def : Pat<(f64 (ftrunc FR64:$src)),
6575 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xB))>;
6578 let Predicates = [HasAVX] in {
6579 def : Pat<(v4f32 (ffloor VR128:$src)),
6580 (VROUNDPSr VR128:$src, (i32 0x9))>;
6581 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6582 (VROUNDPSr VR128:$src, (i32 0xC))>;
6583 def : Pat<(v4f32 (fceil VR128:$src)),
6584 (VROUNDPSr VR128:$src, (i32 0xA))>;
6585 def : Pat<(v4f32 (frint VR128:$src)),
6586 (VROUNDPSr VR128:$src, (i32 0x4))>;
6587 def : Pat<(v4f32 (ftrunc VR128:$src)),
6588 (VROUNDPSr VR128:$src, (i32 0xB))>;
6590 def : Pat<(v2f64 (ffloor VR128:$src)),
6591 (VROUNDPDr VR128:$src, (i32 0x9))>;
6592 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6593 (VROUNDPDr VR128:$src, (i32 0xC))>;
6594 def : Pat<(v2f64 (fceil VR128:$src)),
6595 (VROUNDPDr VR128:$src, (i32 0xA))>;
6596 def : Pat<(v2f64 (frint VR128:$src)),
6597 (VROUNDPDr VR128:$src, (i32 0x4))>;
6598 def : Pat<(v2f64 (ftrunc VR128:$src)),
6599 (VROUNDPDr VR128:$src, (i32 0xB))>;
6601 def : Pat<(v8f32 (ffloor VR256:$src)),
6602 (VROUNDYPSr VR256:$src, (i32 0x9))>;
6603 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6604 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6605 def : Pat<(v8f32 (fceil VR256:$src)),
6606 (VROUNDYPSr VR256:$src, (i32 0xA))>;
6607 def : Pat<(v8f32 (frint VR256:$src)),
6608 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6609 def : Pat<(v8f32 (ftrunc VR256:$src)),
6610 (VROUNDYPSr VR256:$src, (i32 0xB))>;
6612 def : Pat<(v4f64 (ffloor VR256:$src)),
6613 (VROUNDYPDr VR256:$src, (i32 0x9))>;
6614 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6615 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6616 def : Pat<(v4f64 (fceil VR256:$src)),
6617 (VROUNDYPDr VR256:$src, (i32 0xA))>;
6618 def : Pat<(v4f64 (frint VR256:$src)),
6619 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6620 def : Pat<(v4f64 (ftrunc VR256:$src)),
6621 (VROUNDYPDr VR256:$src, (i32 0xB))>;
6624 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6625 memopv4f32, memopv2f64,
6626 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6627 let Constraints = "$src1 = $dst" in
6628 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6629 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6631 let Predicates = [UseSSE41] in {
6632 def : Pat<(ffloor FR32:$src),
6633 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x9))>;
6634 def : Pat<(f64 (ffloor FR64:$src)),
6635 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x9))>;
6636 def : Pat<(f32 (fnearbyint FR32:$src)),
6637 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6638 def : Pat<(f64 (fnearbyint FR64:$src)),
6639 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6640 def : Pat<(f32 (fceil FR32:$src)),
6641 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xA))>;
6642 def : Pat<(f64 (fceil FR64:$src)),
6643 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xA))>;
6644 def : Pat<(f32 (frint FR32:$src)),
6645 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6646 def : Pat<(f64 (frint FR64:$src)),
6647 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6648 def : Pat<(f32 (ftrunc FR32:$src)),
6649 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xB))>;
6650 def : Pat<(f64 (ftrunc FR64:$src)),
6651 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xB))>;
6653 def : Pat<(v4f32 (ffloor VR128:$src)),
6654 (ROUNDPSr VR128:$src, (i32 0x9))>;
6655 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6656 (ROUNDPSr VR128:$src, (i32 0xC))>;
6657 def : Pat<(v4f32 (fceil VR128:$src)),
6658 (ROUNDPSr VR128:$src, (i32 0xA))>;
6659 def : Pat<(v4f32 (frint VR128:$src)),
6660 (ROUNDPSr VR128:$src, (i32 0x4))>;
6661 def : Pat<(v4f32 (ftrunc VR128:$src)),
6662 (ROUNDPSr VR128:$src, (i32 0xB))>;
6664 def : Pat<(v2f64 (ffloor VR128:$src)),
6665 (ROUNDPDr VR128:$src, (i32 0x9))>;
6666 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6667 (ROUNDPDr VR128:$src, (i32 0xC))>;
6668 def : Pat<(v2f64 (fceil VR128:$src)),
6669 (ROUNDPDr VR128:$src, (i32 0xA))>;
6670 def : Pat<(v2f64 (frint VR128:$src)),
6671 (ROUNDPDr VR128:$src, (i32 0x4))>;
6672 def : Pat<(v2f64 (ftrunc VR128:$src)),
6673 (ROUNDPDr VR128:$src, (i32 0xB))>;
6676 //===----------------------------------------------------------------------===//
6677 // SSE4.1 - Packed Bit Test
6678 //===----------------------------------------------------------------------===//
6680 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6681 // the intel intrinsic that corresponds to this.
6682 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6683 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6684 "vptest\t{$src2, $src1|$src1, $src2}",
6685 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6686 Sched<[WriteVecLogic]>, VEX;
6687 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6688 "vptest\t{$src2, $src1|$src1, $src2}",
6689 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
6690 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6692 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6693 "vptest\t{$src2, $src1|$src1, $src2}",
6694 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6695 Sched<[WriteVecLogic]>, VEX, VEX_L;
6696 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6697 "vptest\t{$src2, $src1|$src1, $src2}",
6698 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
6699 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX, VEX_L;
6702 let Defs = [EFLAGS] in {
6703 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6704 "ptest\t{$src2, $src1|$src1, $src2}",
6705 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6706 Sched<[WriteVecLogic]>;
6707 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6708 "ptest\t{$src2, $src1|$src1, $src2}",
6709 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6710 Sched<[WriteVecLogicLd, ReadAfterLd]>;
6713 // The bit test instructions below are AVX only
6714 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6715 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6716 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6717 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6718 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>,
6719 Sched<[WriteVecLogic]>, VEX;
6720 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6721 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6722 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6723 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6726 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6727 let ExeDomain = SSEPackedSingle in {
6728 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
6729 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
6732 let ExeDomain = SSEPackedDouble in {
6733 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
6734 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
6739 //===----------------------------------------------------------------------===//
6740 // SSE4.1 - Misc Instructions
6741 //===----------------------------------------------------------------------===//
6743 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6744 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6745 "popcnt{w}\t{$src, $dst|$dst, $src}",
6746 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6747 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6749 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6750 "popcnt{w}\t{$src, $dst|$dst, $src}",
6751 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6752 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6753 Sched<[WriteFAddLd]>, OpSize16, XS;
6755 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6756 "popcnt{l}\t{$src, $dst|$dst, $src}",
6757 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6758 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6761 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6762 "popcnt{l}\t{$src, $dst|$dst, $src}",
6763 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6764 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6765 Sched<[WriteFAddLd]>, OpSize32, XS;
6767 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6768 "popcnt{q}\t{$src, $dst|$dst, $src}",
6769 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
6770 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>, XS;
6771 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6772 "popcnt{q}\t{$src, $dst|$dst, $src}",
6773 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6774 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6775 Sched<[WriteFAddLd]>, XS;
6780 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6781 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6782 Intrinsic IntId128, PatFrag ld_frag,
6783 X86FoldableSchedWrite Sched> {
6784 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6786 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6787 [(set VR128:$dst, (IntId128 VR128:$src))]>,
6789 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6791 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6793 (IntId128 (bitconvert (ld_frag addr:$src))))]>,
6794 Sched<[Sched.Folded]>;
6797 // PHMIN has the same profile as PSAD, thus we use the same scheduling
6798 // model, although the naming is misleading.
6799 let Predicates = [HasAVX] in
6800 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6801 int_x86_sse41_phminposuw, loadv2i64,
6803 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6804 int_x86_sse41_phminposuw, memopv2i64,
6807 /// SS48I_binop_rm - Simple SSE41 binary operator.
6808 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6809 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6810 X86MemOperand x86memop, bit Is2Addr = 1,
6811 OpndItins itins = SSE_INTALU_ITINS_P> {
6812 let isCommutable = 1 in
6813 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6814 (ins RC:$src1, RC:$src2),
6816 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6817 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6818 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6819 Sched<[itins.Sched]>;
6820 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6821 (ins RC:$src1, x86memop:$src2),
6823 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6824 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6826 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>,
6827 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6830 /// SS48I_binop_rm2 - Simple SSE41 binary operator with different src and dst
6832 multiclass SS48I_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
6833 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
6834 PatFrag memop_frag, X86MemOperand x86memop,
6836 bit IsCommutable = 0, bit Is2Addr = 1> {
6837 let isCommutable = IsCommutable in
6838 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6839 (ins RC:$src1, RC:$src2),
6841 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6842 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6843 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
6844 Sched<[itins.Sched]>;
6845 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6846 (ins RC:$src1, x86memop:$src2),
6848 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6849 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6850 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
6851 (bitconvert (memop_frag addr:$src2)))))]>,
6852 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6855 let Predicates = [HasAVX, NoVLX] in {
6856 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", smin, v16i8, VR128,
6857 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6859 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", smin, v4i32, VR128,
6860 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6862 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", umin, v4i32, VR128,
6863 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6865 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", umin, v8i16, VR128,
6866 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6868 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", smax, v16i8, VR128,
6869 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6871 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", smax, v4i32, VR128,
6872 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6874 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", umax, v4i32, VR128,
6875 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6877 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", umax, v8i16, VR128,
6878 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6880 defm VPMULDQ : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v2i64, v4i32,
6881 VR128, loadv2i64, i128mem,
6882 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
6885 let Predicates = [HasAVX2, NoVLX] in {
6886 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", smin, v32i8, VR256,
6887 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6889 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", smin, v8i32, VR256,
6890 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6892 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", umin, v8i32, VR256,
6893 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6895 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", umin, v16i16, VR256,
6896 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6898 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", smax, v32i8, VR256,
6899 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6901 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", smax, v8i32, VR256,
6902 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6904 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", umax, v8i32, VR256,
6905 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6907 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", umax, v16i16, VR256,
6908 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6910 defm VPMULDQY : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v4i64, v8i32,
6911 VR256, loadv4i64, i256mem,
6912 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
6915 let Constraints = "$src1 = $dst" in {
6916 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", smin, v16i8, VR128,
6917 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6918 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", smin, v4i32, VR128,
6919 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6920 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", umin, v4i32, VR128,
6921 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6922 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", umin, v8i16, VR128,
6923 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6924 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", smax, v16i8, VR128,
6925 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6926 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", smax, v4i32, VR128,
6927 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6928 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", umax, v4i32, VR128,
6929 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6930 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", umax, v8i16, VR128,
6931 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6932 defm PMULDQ : SS48I_binop_rm2<0x28, "pmuldq", X86pmuldq, v2i64, v4i32,
6933 VR128, memopv2i64, i128mem,
6934 SSE_INTMUL_ITINS_P, 1>;
6937 let Predicates = [HasAVX, NoVLX] in {
6938 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6939 memopv2i64, i128mem, 0, SSE_PMULLD_ITINS>,
6941 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6942 memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6945 let Predicates = [HasAVX2] in {
6946 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6947 loadv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
6949 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6950 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6954 let Constraints = "$src1 = $dst" in {
6955 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6956 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
6957 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6958 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
6961 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6962 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6963 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6964 X86MemOperand x86memop, bit Is2Addr = 1,
6965 OpndItins itins = DEFAULT_ITINS> {
6966 let isCommutable = 1 in
6967 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6968 (ins RC:$src1, RC:$src2, u8imm:$src3),
6970 !strconcat(OpcodeStr,
6971 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6972 !strconcat(OpcodeStr,
6973 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6974 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
6975 Sched<[itins.Sched]>;
6976 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6977 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
6979 !strconcat(OpcodeStr,
6980 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6981 !strconcat(OpcodeStr,
6982 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6985 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
6986 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6989 /// SS41I_binop_rmi - SSE 4.1 binary operator with 8-bit immediate
6990 multiclass SS41I_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
6991 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6992 X86MemOperand x86memop, bit Is2Addr = 1,
6993 OpndItins itins = DEFAULT_ITINS> {
6994 let isCommutable = 1 in
6995 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6996 (ins RC:$src1, RC:$src2, u8imm:$src3),
6998 !strconcat(OpcodeStr,
6999 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7000 !strconcat(OpcodeStr,
7001 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7002 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, imm:$src3)))],
7003 itins.rr>, Sched<[itins.Sched]>;
7004 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
7005 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
7007 !strconcat(OpcodeStr,
7008 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7009 !strconcat(OpcodeStr,
7010 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7012 (OpVT (OpNode RC:$src1,
7013 (bitconvert (memop_frag addr:$src2)), imm:$src3)))], itins.rm>,
7014 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7017 let Predicates = [HasAVX] in {
7018 let isCommutable = 0 in {
7019 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
7020 VR128, loadv2i64, i128mem, 0,
7021 DEFAULT_ITINS_MPSADSCHED>, VEX_4V;
7024 let ExeDomain = SSEPackedSingle in {
7025 defm VBLENDPS : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v4f32,
7026 VR128, loadv4f32, f128mem, 0,
7027 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7028 defm VBLENDPSY : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v8f32,
7029 VR256, loadv8f32, f256mem, 0,
7030 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L;
7032 let ExeDomain = SSEPackedDouble in {
7033 defm VBLENDPD : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v2f64,
7034 VR128, loadv2f64, f128mem, 0,
7035 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7036 defm VBLENDPDY : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v4f64,
7037 VR256, loadv4f64, f256mem, 0,
7038 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L;
7040 defm VPBLENDW : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v8i16,
7041 VR128, loadv2i64, i128mem, 0,
7042 DEFAULT_ITINS_BLENDSCHED>, VEX_4V;
7044 let ExeDomain = SSEPackedSingle in
7045 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
7046 VR128, loadv4f32, f128mem, 0,
7047 SSE_DPPS_ITINS>, VEX_4V;
7048 let ExeDomain = SSEPackedDouble in
7049 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
7050 VR128, loadv2f64, f128mem, 0,
7051 SSE_DPPS_ITINS>, VEX_4V;
7052 let ExeDomain = SSEPackedSingle in
7053 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
7054 VR256, loadv8f32, i256mem, 0,
7055 SSE_DPPS_ITINS>, VEX_4V, VEX_L;
7058 let Predicates = [HasAVX2] in {
7059 let isCommutable = 0 in {
7060 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
7061 VR256, loadv4i64, i256mem, 0,
7062 DEFAULT_ITINS_MPSADSCHED>, VEX_4V, VEX_L;
7064 defm VPBLENDWY : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v16i16,
7065 VR256, loadv4i64, i256mem, 0,
7066 DEFAULT_ITINS_BLENDSCHED>, VEX_4V, VEX_L;
7069 let Constraints = "$src1 = $dst" in {
7070 let isCommutable = 0 in {
7071 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7072 VR128, memopv2i64, i128mem,
7073 1, SSE_MPSADBW_ITINS>;
7075 let ExeDomain = SSEPackedSingle in
7076 defm BLENDPS : SS41I_binop_rmi<0x0C, "blendps", X86Blendi, v4f32,
7077 VR128, memopv4f32, f128mem,
7078 1, SSE_INTALU_ITINS_FBLEND_P>;
7079 let ExeDomain = SSEPackedDouble in
7080 defm BLENDPD : SS41I_binop_rmi<0x0D, "blendpd", X86Blendi, v2f64,
7081 VR128, memopv2f64, f128mem,
7082 1, SSE_INTALU_ITINS_FBLEND_P>;
7083 defm PBLENDW : SS41I_binop_rmi<0x0E, "pblendw", X86Blendi, v8i16,
7084 VR128, memopv2i64, i128mem,
7085 1, SSE_INTALU_ITINS_BLEND_P>;
7086 let ExeDomain = SSEPackedSingle in
7087 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7088 VR128, memopv4f32, f128mem, 1,
7090 let ExeDomain = SSEPackedDouble in
7091 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7092 VR128, memopv2f64, f128mem, 1,
7096 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7097 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7098 RegisterClass RC, X86MemOperand x86memop,
7099 PatFrag mem_frag, Intrinsic IntId,
7100 X86FoldableSchedWrite Sched> {
7101 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7102 (ins RC:$src1, RC:$src2, RC:$src3),
7103 !strconcat(OpcodeStr,
7104 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7105 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7106 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7109 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7110 (ins RC:$src1, x86memop:$src2, RC:$src3),
7111 !strconcat(OpcodeStr,
7112 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7114 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7116 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7117 Sched<[Sched.Folded, ReadAfterLd]>;
7120 let Predicates = [HasAVX] in {
7121 let ExeDomain = SSEPackedDouble in {
7122 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7123 loadv2f64, int_x86_sse41_blendvpd,
7125 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7126 loadv4f64, int_x86_avx_blendv_pd_256,
7127 WriteFVarBlend>, VEX_L;
7128 } // ExeDomain = SSEPackedDouble
7129 let ExeDomain = SSEPackedSingle in {
7130 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7131 loadv4f32, int_x86_sse41_blendvps,
7133 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7134 loadv8f32, int_x86_avx_blendv_ps_256,
7135 WriteFVarBlend>, VEX_L;
7136 } // ExeDomain = SSEPackedSingle
7137 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7138 loadv2i64, int_x86_sse41_pblendvb,
7142 let Predicates = [HasAVX2] in {
7143 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7144 loadv4i64, int_x86_avx2_pblendvb,
7145 WriteVarBlend>, VEX_L;
7148 let Predicates = [HasAVX] in {
7149 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7150 (v16i8 VR128:$src2))),
7151 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7152 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7153 (v4i32 VR128:$src2))),
7154 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7155 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7156 (v4f32 VR128:$src2))),
7157 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7158 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7159 (v2i64 VR128:$src2))),
7160 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7161 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7162 (v2f64 VR128:$src2))),
7163 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7164 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7165 (v8i32 VR256:$src2))),
7166 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7167 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7168 (v8f32 VR256:$src2))),
7169 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7170 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7171 (v4i64 VR256:$src2))),
7172 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7173 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7174 (v4f64 VR256:$src2))),
7175 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7178 let Predicates = [HasAVX2] in {
7179 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7180 (v32i8 VR256:$src2))),
7181 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7185 // FIXME: Prefer a movss or movsd over a blendps when optimizing for size or
7186 // on targets where they have equal performance. These were changed to use
7187 // blends because blends have better throughput on SandyBridge and Haswell, but
7188 // movs[s/d] are 1-2 byte shorter instructions.
7189 let Predicates = [UseAVX] in {
7190 let AddedComplexity = 15 in {
7191 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
7192 // MOVS{S,D} to the lower bits.
7193 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
7194 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
7195 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7196 (VBLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7197 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7198 (VPBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7199 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
7200 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
7202 // Move low f32 and clear high bits.
7203 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
7204 (VBLENDPSYrri (v8f32 (AVX_SET0)), VR256:$src, (i8 1))>;
7206 // Move low f64 and clear high bits.
7207 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
7208 (VBLENDPDYrri (v4f64 (AVX_SET0)), VR256:$src, (i8 1))>;
7211 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
7212 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
7213 (SUBREG_TO_REG (i32 0),
7214 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
7216 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
7217 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
7218 (SUBREG_TO_REG (i64 0),
7219 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
7222 // These will incur an FP/int domain crossing penalty, but it may be the only
7223 // way without AVX2. Do not add any complexity because we may be able to match
7224 // more optimal patterns defined earlier in this file.
7225 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
7226 (VBLENDPSYrri (v8i32 (AVX_SET0)), VR256:$src, (i8 1))>;
7227 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
7228 (VBLENDPDYrri (v4i64 (AVX_SET0)), VR256:$src, (i8 1))>;
7231 // FIXME: Prefer a movss or movsd over a blendps when optimizing for size or
7232 // on targets where they have equal performance. These were changed to use
7233 // blends because blends have better throughput on SandyBridge and Haswell, but
7234 // movs[s/d] are 1-2 byte shorter instructions.
7235 let Predicates = [UseSSE41] in {
7236 // With SSE41 we can use blends for these patterns.
7237 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7238 (BLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7239 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7240 (PBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7241 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
7242 (BLENDPDrri (v2f64 (V_SET0)), VR128:$src, (i8 1))>;
7246 /// SS41I_ternary_int - SSE 4.1 ternary operator
7247 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7248 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7249 X86MemOperand x86memop, Intrinsic IntId,
7250 OpndItins itins = DEFAULT_ITINS> {
7251 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7252 (ins VR128:$src1, VR128:$src2),
7253 !strconcat(OpcodeStr,
7254 "\t{$src2, $dst|$dst, $src2}"),
7255 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7256 itins.rr>, Sched<[itins.Sched]>;
7258 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7259 (ins VR128:$src1, x86memop:$src2),
7260 !strconcat(OpcodeStr,
7261 "\t{$src2, $dst|$dst, $src2}"),
7264 (bitconvert (mem_frag addr:$src2)), XMM0))],
7265 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7269 let ExeDomain = SSEPackedDouble in
7270 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7271 int_x86_sse41_blendvpd,
7272 DEFAULT_ITINS_FBLENDSCHED>;
7273 let ExeDomain = SSEPackedSingle in
7274 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7275 int_x86_sse41_blendvps,
7276 DEFAULT_ITINS_FBLENDSCHED>;
7277 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7278 int_x86_sse41_pblendvb,
7279 DEFAULT_ITINS_VARBLENDSCHED>;
7281 // Aliases with the implicit xmm0 argument
7282 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7283 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7284 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7285 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7286 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7287 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7288 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7289 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7290 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7291 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7292 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7293 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7295 let Predicates = [UseSSE41] in {
7296 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7297 (v16i8 VR128:$src2))),
7298 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7299 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7300 (v4i32 VR128:$src2))),
7301 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7302 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7303 (v4f32 VR128:$src2))),
7304 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7305 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7306 (v2i64 VR128:$src2))),
7307 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7308 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7309 (v2f64 VR128:$src2))),
7310 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7313 let SchedRW = [WriteLoad] in {
7314 let Predicates = [HasAVX] in
7315 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7316 "vmovntdqa\t{$src, $dst|$dst, $src}",
7317 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7319 let Predicates = [HasAVX2] in
7320 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7321 "vmovntdqa\t{$src, $dst|$dst, $src}",
7322 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7324 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7325 "movntdqa\t{$src, $dst|$dst, $src}",
7326 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
7329 //===----------------------------------------------------------------------===//
7330 // SSE4.2 - Compare Instructions
7331 //===----------------------------------------------------------------------===//
7333 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7334 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7335 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7336 X86MemOperand x86memop, bit Is2Addr = 1> {
7337 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7338 (ins RC:$src1, RC:$src2),
7340 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7341 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7342 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
7343 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7344 (ins RC:$src1, x86memop:$src2),
7346 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7347 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7349 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>;
7352 let Predicates = [HasAVX] in
7353 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7354 loadv2i64, i128mem, 0>, VEX_4V;
7356 let Predicates = [HasAVX2] in
7357 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7358 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7360 let Constraints = "$src1 = $dst" in
7361 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7362 memopv2i64, i128mem>;
7364 //===----------------------------------------------------------------------===//
7365 // SSE4.2 - String/text Processing Instructions
7366 //===----------------------------------------------------------------------===//
7368 // Packed Compare Implicit Length Strings, Return Mask
7369 multiclass pseudo_pcmpistrm<string asm, PatFrag ld_frag> {
7370 def REG : PseudoI<(outs VR128:$dst),
7371 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7372 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7374 def MEM : PseudoI<(outs VR128:$dst),
7375 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7376 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7377 (bc_v16i8 (ld_frag addr:$src2)), imm:$src3))]>;
7380 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7381 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128", loadv2i64>,
7383 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128", memopv2i64>,
7384 Requires<[UseSSE42]>;
7387 multiclass pcmpistrm_SS42AI<string asm> {
7388 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7389 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7390 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7391 []>, Sched<[WritePCmpIStrM]>;
7393 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7394 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7395 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7396 []>, Sched<[WritePCmpIStrMLd, ReadAfterLd]>;
7399 let Defs = [XMM0, EFLAGS], hasSideEffects = 0 in {
7400 let Predicates = [HasAVX] in
7401 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7402 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7405 // Packed Compare Explicit Length Strings, Return Mask
7406 multiclass pseudo_pcmpestrm<string asm, PatFrag ld_frag> {
7407 def REG : PseudoI<(outs VR128:$dst),
7408 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7409 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7410 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7411 def MEM : PseudoI<(outs VR128:$dst),
7412 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7413 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7414 (bc_v16i8 (ld_frag addr:$src3)), EDX, imm:$src5))]>;
7417 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7418 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128", loadv2i64>,
7420 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128", memopv2i64>,
7421 Requires<[UseSSE42]>;
7424 multiclass SS42AI_pcmpestrm<string asm> {
7425 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7426 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7427 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7428 []>, Sched<[WritePCmpEStrM]>;
7430 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7431 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7432 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7433 []>, Sched<[WritePCmpEStrMLd, ReadAfterLd]>;
7436 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7437 let Predicates = [HasAVX] in
7438 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7439 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7442 // Packed Compare Implicit Length Strings, Return Index
7443 multiclass pseudo_pcmpistri<string asm, PatFrag ld_frag> {
7444 def REG : PseudoI<(outs GR32:$dst),
7445 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7446 [(set GR32:$dst, EFLAGS,
7447 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7448 def MEM : PseudoI<(outs GR32:$dst),
7449 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7450 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7451 (bc_v16i8 (ld_frag addr:$src2)), imm:$src3))]>;
7454 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7455 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI", loadv2i64>,
7457 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI", memopv2i64>,
7458 Requires<[UseSSE42]>;
7461 multiclass SS42AI_pcmpistri<string asm> {
7462 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7463 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7464 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7465 []>, Sched<[WritePCmpIStrI]>;
7467 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7468 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7469 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7470 []>, Sched<[WritePCmpIStrILd, ReadAfterLd]>;
7473 let Defs = [ECX, EFLAGS], hasSideEffects = 0 in {
7474 let Predicates = [HasAVX] in
7475 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7476 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7479 // Packed Compare Explicit Length Strings, Return Index
7480 multiclass pseudo_pcmpestri<string asm, PatFrag ld_frag> {
7481 def REG : PseudoI<(outs GR32:$dst),
7482 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7483 [(set GR32:$dst, EFLAGS,
7484 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7485 def MEM : PseudoI<(outs GR32:$dst),
7486 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7487 [(set GR32:$dst, EFLAGS,
7488 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (ld_frag addr:$src3)), EDX,
7492 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7493 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI", loadv2i64>,
7495 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI", memopv2i64>,
7496 Requires<[UseSSE42]>;
7499 multiclass SS42AI_pcmpestri<string asm> {
7500 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7501 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7502 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7503 []>, Sched<[WritePCmpEStrI]>;
7505 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7506 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7507 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7508 []>, Sched<[WritePCmpEStrILd, ReadAfterLd]>;
7511 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7512 let Predicates = [HasAVX] in
7513 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7514 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7517 //===----------------------------------------------------------------------===//
7518 // SSE4.2 - CRC Instructions
7519 //===----------------------------------------------------------------------===//
7521 // No CRC instructions have AVX equivalents
7523 // crc intrinsic instruction
7524 // This set of instructions are only rm, the only difference is the size
7526 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7527 RegisterClass RCIn, SDPatternOperator Int> :
7528 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7529 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7530 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>,
7533 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7534 X86MemOperand x86memop, SDPatternOperator Int> :
7535 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7536 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7537 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7538 IIC_CRC32_MEM>, Sched<[WriteFAddLd, ReadAfterLd]>;
7540 let Constraints = "$src1 = $dst" in {
7541 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7542 int_x86_sse42_crc32_32_8>;
7543 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7544 int_x86_sse42_crc32_32_8>;
7545 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7546 int_x86_sse42_crc32_32_16>, OpSize16;
7547 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7548 int_x86_sse42_crc32_32_16>, OpSize16;
7549 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7550 int_x86_sse42_crc32_32_32>, OpSize32;
7551 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7552 int_x86_sse42_crc32_32_32>, OpSize32;
7553 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7554 int_x86_sse42_crc32_64_64>, REX_W;
7555 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7556 int_x86_sse42_crc32_64_64>, REX_W;
7557 let hasSideEffects = 0 in {
7559 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7561 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7566 //===----------------------------------------------------------------------===//
7567 // SHA-NI Instructions
7568 //===----------------------------------------------------------------------===//
7570 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7572 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7573 (ins VR128:$src1, VR128:$src2),
7574 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7576 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7577 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7579 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7580 (ins VR128:$src1, i128mem:$src2),
7581 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7583 (set VR128:$dst, (IntId VR128:$src1,
7584 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7585 (set VR128:$dst, (IntId VR128:$src1,
7586 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7589 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7590 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7591 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7592 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7594 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7595 (i8 imm:$src3)))]>, TA;
7596 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7597 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7598 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7600 (int_x86_sha1rnds4 VR128:$src1,
7601 (bc_v4i32 (memopv2i64 addr:$src2)),
7602 (i8 imm:$src3)))]>, TA;
7604 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7605 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7606 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7609 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7611 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7612 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7615 // Aliases with explicit %xmm0
7616 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7617 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7618 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7619 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7621 //===----------------------------------------------------------------------===//
7622 // AES-NI Instructions
7623 //===----------------------------------------------------------------------===//
7625 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
7626 PatFrag ld_frag, bit Is2Addr = 1> {
7627 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7628 (ins VR128:$src1, VR128:$src2),
7630 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7631 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7632 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7633 Sched<[WriteAESDecEnc]>;
7634 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7635 (ins VR128:$src1, i128mem:$src2),
7637 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7638 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7640 (IntId128 VR128:$src1, (ld_frag addr:$src2)))]>,
7641 Sched<[WriteAESDecEncLd, ReadAfterLd]>;
7644 // Perform One Round of an AES Encryption/Decryption Flow
7645 let Predicates = [HasAVX, HasAES] in {
7646 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7647 int_x86_aesni_aesenc, loadv2i64, 0>, VEX_4V;
7648 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7649 int_x86_aesni_aesenclast, loadv2i64, 0>, VEX_4V;
7650 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7651 int_x86_aesni_aesdec, loadv2i64, 0>, VEX_4V;
7652 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7653 int_x86_aesni_aesdeclast, loadv2i64, 0>, VEX_4V;
7656 let Constraints = "$src1 = $dst" in {
7657 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7658 int_x86_aesni_aesenc, memopv2i64>;
7659 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7660 int_x86_aesni_aesenclast, memopv2i64>;
7661 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7662 int_x86_aesni_aesdec, memopv2i64>;
7663 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7664 int_x86_aesni_aesdeclast, memopv2i64>;
7667 // Perform the AES InvMixColumn Transformation
7668 let Predicates = [HasAVX, HasAES] in {
7669 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7671 "vaesimc\t{$src1, $dst|$dst, $src1}",
7673 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>,
7675 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7676 (ins i128mem:$src1),
7677 "vaesimc\t{$src1, $dst|$dst, $src1}",
7678 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7679 Sched<[WriteAESIMCLd]>, VEX;
7681 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7683 "aesimc\t{$src1, $dst|$dst, $src1}",
7685 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>;
7686 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7687 (ins i128mem:$src1),
7688 "aesimc\t{$src1, $dst|$dst, $src1}",
7689 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7690 Sched<[WriteAESIMCLd]>;
7692 // AES Round Key Generation Assist
7693 let Predicates = [HasAVX, HasAES] in {
7694 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7695 (ins VR128:$src1, u8imm:$src2),
7696 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7698 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7699 Sched<[WriteAESKeyGen]>, VEX;
7700 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7701 (ins i128mem:$src1, u8imm:$src2),
7702 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7704 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
7705 Sched<[WriteAESKeyGenLd]>, VEX;
7707 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7708 (ins VR128:$src1, u8imm:$src2),
7709 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7711 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7712 Sched<[WriteAESKeyGen]>;
7713 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7714 (ins i128mem:$src1, u8imm:$src2),
7715 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7717 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7718 Sched<[WriteAESKeyGenLd]>;
7720 //===----------------------------------------------------------------------===//
7721 // PCLMUL Instructions
7722 //===----------------------------------------------------------------------===//
7724 // AVX carry-less Multiplication instructions
7725 let isCommutable = 1 in
7726 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7727 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7728 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7730 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>,
7731 Sched<[WriteCLMul]>;
7733 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7734 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7735 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7736 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7737 (loadv2i64 addr:$src2), imm:$src3))]>,
7738 Sched<[WriteCLMulLd, ReadAfterLd]>;
7740 // Carry-less Multiplication instructions
7741 let Constraints = "$src1 = $dst" in {
7742 let isCommutable = 1 in
7743 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7744 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7745 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7747 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
7748 IIC_SSE_PCLMULQDQ_RR>, Sched<[WriteCLMul]>;
7750 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7751 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7752 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7753 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7754 (memopv2i64 addr:$src2), imm:$src3))],
7755 IIC_SSE_PCLMULQDQ_RM>,
7756 Sched<[WriteCLMulLd, ReadAfterLd]>;
7757 } // Constraints = "$src1 = $dst"
7760 multiclass pclmul_alias<string asm, int immop> {
7761 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7762 (PCLMULQDQrr VR128:$dst, VR128:$src, immop), 0>;
7764 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7765 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop), 0>;
7767 def : InstAlias<!strconcat("vpclmul", asm,
7768 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7769 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop),
7772 def : InstAlias<!strconcat("vpclmul", asm,
7773 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7774 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop),
7777 defm : pclmul_alias<"hqhq", 0x11>;
7778 defm : pclmul_alias<"hqlq", 0x01>;
7779 defm : pclmul_alias<"lqhq", 0x10>;
7780 defm : pclmul_alias<"lqlq", 0x00>;
7782 //===----------------------------------------------------------------------===//
7783 // SSE4A Instructions
7784 //===----------------------------------------------------------------------===//
7786 let Predicates = [HasSSE4A] in {
7788 let Constraints = "$src = $dst" in {
7789 def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst),
7790 (ins VR128:$src, u8imm:$len, u8imm:$idx),
7791 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7792 [(set VR128:$dst, (X86extrqi VR128:$src, imm:$len,
7794 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7795 (ins VR128:$src, VR128:$mask),
7796 "extrq\t{$mask, $src|$src, $mask}",
7797 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7798 VR128:$mask))]>, PD;
7800 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7801 (ins VR128:$src, VR128:$src2, u8imm:$len, u8imm:$idx),
7802 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7803 [(set VR128:$dst, (X86insertqi VR128:$src, VR128:$src2,
7804 imm:$len, imm:$idx))]>, XD;
7805 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7806 (ins VR128:$src, VR128:$mask),
7807 "insertq\t{$mask, $src|$src, $mask}",
7808 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7809 VR128:$mask))]>, XD;
7812 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7813 "movntss\t{$src, $dst|$dst, $src}",
7814 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7816 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7817 "movntsd\t{$src, $dst|$dst, $src}",
7818 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7821 //===----------------------------------------------------------------------===//
7823 //===----------------------------------------------------------------------===//
7825 //===----------------------------------------------------------------------===//
7826 // VBROADCAST - Load from memory and broadcast to all elements of the
7827 // destination operand
7829 class avx_broadcast_rm<bits<8> opc, string OpcodeStr, RegisterClass RC,
7830 X86MemOperand x86memop, ValueType VT,
7831 PatFrag ld_frag, SchedWrite Sched> :
7832 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7833 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7834 [(set RC:$dst, (VT (X86VBroadcast (ld_frag addr:$src))))]>,
7835 Sched<[Sched]>, VEX {
7839 // AVX2 adds register forms
7840 class avx2_broadcast_rr<bits<8> opc, string OpcodeStr, RegisterClass RC,
7841 ValueType ResVT, ValueType OpVT, SchedWrite Sched> :
7842 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7843 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7844 [(set RC:$dst, (ResVT (X86VBroadcast (OpVT VR128:$src))))]>,
7845 Sched<[Sched]>, VEX;
7847 let ExeDomain = SSEPackedSingle in {
7848 def VBROADCASTSSrm : avx_broadcast_rm<0x18, "vbroadcastss", VR128,
7849 f32mem, v4f32, loadf32, WriteLoad>;
7850 def VBROADCASTSSYrm : avx_broadcast_rm<0x18, "vbroadcastss", VR256,
7851 f32mem, v8f32, loadf32,
7852 WriteFShuffleLd>, VEX_L;
7854 let ExeDomain = SSEPackedDouble in
7855 def VBROADCASTSDYrm : avx_broadcast_rm<0x19, "vbroadcastsd", VR256, f64mem,
7856 v4f64, loadf64, WriteFShuffleLd>, VEX_L;
7858 let ExeDomain = SSEPackedSingle in {
7859 def VBROADCASTSSrr : avx2_broadcast_rr<0x18, "vbroadcastss", VR128,
7860 v4f32, v4f32, WriteFShuffle>;
7861 def VBROADCASTSSYrr : avx2_broadcast_rr<0x18, "vbroadcastss", VR256,
7862 v8f32, v4f32, WriteFShuffle256>, VEX_L;
7864 let ExeDomain = SSEPackedDouble in
7865 def VBROADCASTSDYrr : avx2_broadcast_rr<0x19, "vbroadcastsd", VR256,
7866 v4f64, v2f64, WriteFShuffle256>, VEX_L;
7868 let mayLoad = 1, Predicates = [HasAVX2] in
7869 def VBROADCASTI128 : AVX8I<0x5A, MRMSrcMem, (outs VR256:$dst),
7871 "vbroadcasti128\t{$src, $dst|$dst, $src}", []>,
7872 Sched<[WriteLoad]>, VEX, VEX_L;
7874 def VBROADCASTF128 : AVX8I<0x1A, MRMSrcMem, (outs VR256:$dst),
7876 "vbroadcastf128\t{$src, $dst|$dst, $src}",
7878 (int_x86_avx_vbroadcastf128_pd_256 addr:$src))]>,
7879 Sched<[WriteFShuffleLd]>, VEX, VEX_L;
7881 let Predicates = [HasAVX] in
7882 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7883 (VBROADCASTF128 addr:$src)>;
7886 //===----------------------------------------------------------------------===//
7887 // VINSERTF128 - Insert packed floating-point values
7889 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
7890 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7891 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
7892 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7893 []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
7895 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7896 (ins VR256:$src1, f128mem:$src2, u8imm:$src3),
7897 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7898 []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
7901 let Predicates = [HasAVX, NoVLX] in {
7902 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7904 (VINSERTF128rr VR256:$src1, VR128:$src2,
7905 (INSERT_get_vinsert128_imm VR256:$ins))>;
7906 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7908 (VINSERTF128rr VR256:$src1, VR128:$src2,
7909 (INSERT_get_vinsert128_imm VR256:$ins))>;
7911 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7913 (VINSERTF128rm VR256:$src1, addr:$src2,
7914 (INSERT_get_vinsert128_imm VR256:$ins))>;
7915 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7917 (VINSERTF128rm VR256:$src1, addr:$src2,
7918 (INSERT_get_vinsert128_imm VR256:$ins))>;
7921 let Predicates = [HasAVX1Only] in {
7922 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7924 (VINSERTF128rr VR256:$src1, VR128:$src2,
7925 (INSERT_get_vinsert128_imm VR256:$ins))>;
7926 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7928 (VINSERTF128rr VR256:$src1, VR128:$src2,
7929 (INSERT_get_vinsert128_imm VR256:$ins))>;
7930 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7932 (VINSERTF128rr VR256:$src1, VR128:$src2,
7933 (INSERT_get_vinsert128_imm VR256:$ins))>;
7934 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7936 (VINSERTF128rr VR256:$src1, VR128:$src2,
7937 (INSERT_get_vinsert128_imm VR256:$ins))>;
7939 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7941 (VINSERTF128rm VR256:$src1, addr:$src2,
7942 (INSERT_get_vinsert128_imm VR256:$ins))>;
7943 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
7944 (bc_v4i32 (loadv2i64 addr:$src2)),
7946 (VINSERTF128rm VR256:$src1, addr:$src2,
7947 (INSERT_get_vinsert128_imm VR256:$ins))>;
7948 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
7949 (bc_v16i8 (loadv2i64 addr:$src2)),
7951 (VINSERTF128rm VR256:$src1, addr:$src2,
7952 (INSERT_get_vinsert128_imm VR256:$ins))>;
7953 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
7954 (bc_v8i16 (loadv2i64 addr:$src2)),
7956 (VINSERTF128rm VR256:$src1, addr:$src2,
7957 (INSERT_get_vinsert128_imm VR256:$ins))>;
7960 //===----------------------------------------------------------------------===//
7961 // VEXTRACTF128 - Extract packed floating-point values
7963 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
7964 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7965 (ins VR256:$src1, u8imm:$src2),
7966 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7967 []>, Sched<[WriteFShuffle]>, VEX, VEX_L;
7969 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7970 (ins f128mem:$dst, VR256:$src1, u8imm:$src2),
7971 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7972 []>, Sched<[WriteStore]>, VEX, VEX_L;
7976 let Predicates = [HasAVX] in {
7977 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7978 (v4f32 (VEXTRACTF128rr
7979 (v8f32 VR256:$src1),
7980 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7981 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7982 (v2f64 (VEXTRACTF128rr
7983 (v4f64 VR256:$src1),
7984 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7986 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
7987 (iPTR imm))), addr:$dst),
7988 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7989 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7990 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
7991 (iPTR imm))), addr:$dst),
7992 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7993 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7996 let Predicates = [HasAVX1Only] in {
7997 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7998 (v2i64 (VEXTRACTF128rr
7999 (v4i64 VR256:$src1),
8000 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8001 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8002 (v4i32 (VEXTRACTF128rr
8003 (v8i32 VR256:$src1),
8004 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8005 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8006 (v8i16 (VEXTRACTF128rr
8007 (v16i16 VR256:$src1),
8008 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8009 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8010 (v16i8 (VEXTRACTF128rr
8011 (v32i8 VR256:$src1),
8012 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8014 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8015 (iPTR imm))), addr:$dst),
8016 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8017 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8018 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8019 (iPTR imm))), addr:$dst),
8020 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8021 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8022 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8023 (iPTR imm))), addr:$dst),
8024 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8025 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8026 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8027 (iPTR imm))), addr:$dst),
8028 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8029 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8032 //===----------------------------------------------------------------------===//
8033 // VMASKMOV - Conditional SIMD Packed Loads and Stores
8035 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
8036 Intrinsic IntLd, Intrinsic IntLd256,
8037 Intrinsic IntSt, Intrinsic IntSt256> {
8038 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
8039 (ins VR128:$src1, f128mem:$src2),
8040 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8041 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
8043 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
8044 (ins VR256:$src1, f256mem:$src2),
8045 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8046 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8048 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
8049 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
8050 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8051 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8052 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
8053 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
8054 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8055 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8058 let ExeDomain = SSEPackedSingle in
8059 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
8060 int_x86_avx_maskload_ps,
8061 int_x86_avx_maskload_ps_256,
8062 int_x86_avx_maskstore_ps,
8063 int_x86_avx_maskstore_ps_256>;
8064 let ExeDomain = SSEPackedDouble in
8065 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
8066 int_x86_avx_maskload_pd,
8067 int_x86_avx_maskload_pd_256,
8068 int_x86_avx_maskstore_pd,
8069 int_x86_avx_maskstore_pd_256>;
8071 //===----------------------------------------------------------------------===//
8072 // VPERMIL - Permute Single and Double Floating-Point Values
8074 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
8075 RegisterClass RC, X86MemOperand x86memop_f,
8076 X86MemOperand x86memop_i, PatFrag i_frag,
8077 Intrinsic IntVar, ValueType vt> {
8078 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
8079 (ins RC:$src1, RC:$src2),
8080 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8081 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V,
8082 Sched<[WriteFShuffle]>;
8083 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
8084 (ins RC:$src1, x86memop_i:$src2),
8085 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8086 [(set RC:$dst, (IntVar RC:$src1,
8087 (bitconvert (i_frag addr:$src2))))]>, VEX_4V,
8088 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8090 let Predicates = [HasAVX, NoVLX] in {
8091 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8092 (ins RC:$src1, u8imm:$src2),
8093 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8094 [(set RC:$dst, (vt (X86VPermilpi RC:$src1, (i8 imm:$src2))))]>, VEX,
8095 Sched<[WriteFShuffle]>;
8096 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
8097 (ins x86memop_f:$src1, u8imm:$src2),
8098 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8100 (vt (X86VPermilpi (load addr:$src1), (i8 imm:$src2))))]>, VEX,
8101 Sched<[WriteFShuffleLd]>;
8102 }// Predicates = [HasAVX, NoVLX]
8105 let ExeDomain = SSEPackedSingle in {
8106 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
8107 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
8108 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
8109 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
8111 let ExeDomain = SSEPackedDouble in {
8112 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
8113 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
8114 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
8115 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
8118 let Predicates = [HasAVX, NoVLX] in {
8119 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (v8i32 VR256:$src2))),
8120 (VPERMILPSYrr VR256:$src1, VR256:$src2)>;
8121 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
8122 (VPERMILPSYrm VR256:$src1, addr:$src2)>;
8123 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (v4i64 VR256:$src2))),
8124 (VPERMILPDYrr VR256:$src1, VR256:$src2)>;
8125 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (loadv4i64 addr:$src2))),
8126 (VPERMILPDYrm VR256:$src1, addr:$src2)>;
8128 def : Pat<(v8i32 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8129 (VPERMILPSYri VR256:$src1, imm:$imm)>;
8130 def : Pat<(v4i64 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8131 (VPERMILPDYri VR256:$src1, imm:$imm)>;
8132 def : Pat<(v8i32 (X86VPermilpi (bc_v8i32 (loadv4i64 addr:$src1)),
8134 (VPERMILPSYmi addr:$src1, imm:$imm)>;
8135 def : Pat<(v4i64 (X86VPermilpi (loadv4i64 addr:$src1), (i8 imm:$imm))),
8136 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8138 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (v4i32 VR128:$src2))),
8139 (VPERMILPSrr VR128:$src1, VR128:$src2)>;
8140 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)))),
8141 (VPERMILPSrm VR128:$src1, addr:$src2)>;
8142 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (v2i64 VR128:$src2))),
8143 (VPERMILPDrr VR128:$src1, VR128:$src2)>;
8144 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (loadv2i64 addr:$src2))),
8145 (VPERMILPDrm VR128:$src1, addr:$src2)>;
8147 def : Pat<(v2i64 (X86VPermilpi VR128:$src1, (i8 imm:$imm))),
8148 (VPERMILPDri VR128:$src1, imm:$imm)>;
8149 def : Pat<(v2i64 (X86VPermilpi (loadv2i64 addr:$src1), (i8 imm:$imm))),
8150 (VPERMILPDmi addr:$src1, imm:$imm)>;
8153 //===----------------------------------------------------------------------===//
8154 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8156 let ExeDomain = SSEPackedSingle in {
8157 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8158 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8159 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8160 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8161 (i8 imm:$src3))))]>, VEX_4V, VEX_L,
8162 Sched<[WriteFShuffle]>;
8163 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8164 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8165 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8166 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8167 (i8 imm:$src3)))]>, VEX_4V, VEX_L,
8168 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8171 let Predicates = [HasAVX] in {
8172 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8173 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8174 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8175 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8176 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8179 let Predicates = [HasAVX1Only] in {
8180 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8181 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8182 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8183 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8184 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8185 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8186 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8187 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8189 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8190 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8191 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8192 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8193 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8194 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8195 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8196 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8197 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8198 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8199 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8200 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8203 //===----------------------------------------------------------------------===//
8204 // VZERO - Zero YMM registers
8206 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8207 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8208 // Zero All YMM registers
8209 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8210 [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, Requires<[HasAVX]>;
8212 // Zero Upper bits of YMM registers
8213 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8214 [(int_x86_avx_vzeroupper)]>, PS, VEX, Requires<[HasAVX]>;
8217 //===----------------------------------------------------------------------===//
8218 // Half precision conversion instructions
8219 //===----------------------------------------------------------------------===//
8220 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8221 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8222 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8223 [(set RC:$dst, (Int VR128:$src))]>,
8224 T8PD, VEX, Sched<[WriteCvtF2F]>;
8225 let hasSideEffects = 0, mayLoad = 1 in
8226 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8227 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX,
8228 Sched<[WriteCvtF2FLd]>;
8231 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8232 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8233 (ins RC:$src1, i32u8imm:$src2),
8234 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8235 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8236 TAPD, VEX, Sched<[WriteCvtF2F]>;
8237 let hasSideEffects = 0, mayStore = 1,
8238 SchedRW = [WriteCvtF2FLd, WriteRMW] in
8239 def mr : Ii8<0x1D, MRMDestMem, (outs),
8240 (ins x86memop:$dst, RC:$src1, i32u8imm:$src2),
8241 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8245 let Predicates = [HasF16C] in {
8246 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8247 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8248 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8249 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8251 // Pattern match vcvtph2ps of a scalar i64 load.
8252 def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)),
8253 (VCVTPH2PSrm addr:$src)>;
8254 def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),
8255 (VCVTPH2PSrm addr:$src)>;
8257 def : Pat<(store (f64 (vector_extract (bc_v2f64 (v8i16
8258 (int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),
8260 (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;
8261 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v8i16
8262 (int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),
8264 (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;
8265 def : Pat<(store (v8i16 (int_x86_vcvtps2ph_256 VR256:$src1, i32:$src2)),
8267 (VCVTPS2PHYmr addr:$dst, VR256:$src1, imm:$src2)>;
8270 // Patterns for matching conversions from float to half-float and vice versa.
8271 let Predicates = [HasF16C] in {
8272 def : Pat<(fp_to_f16 FR32:$src),
8273 (i16 (EXTRACT_SUBREG (VMOVPDI2DIrr (VCVTPS2PHrr
8274 (COPY_TO_REGCLASS FR32:$src, VR128), 0)), sub_16bit))>;
8276 def : Pat<(f16_to_fp GR16:$src),
8277 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8278 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128)), FR32)) >;
8280 def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32:$src))),
8281 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8282 (VCVTPS2PHrr (COPY_TO_REGCLASS FR32:$src, VR128), 0)), FR32)) >;
8285 //===----------------------------------------------------------------------===//
8286 // AVX2 Instructions
8287 //===----------------------------------------------------------------------===//
8289 /// AVX2_binop_rmi - AVX2 binary operator with 8-bit immediate
8290 multiclass AVX2_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
8291 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
8292 X86MemOperand x86memop> {
8293 let isCommutable = 1 in
8294 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8295 (ins RC:$src1, RC:$src2, u8imm:$src3),
8296 !strconcat(OpcodeStr,
8297 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8298 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, imm:$src3)))]>,
8299 Sched<[WriteBlend]>, VEX_4V;
8300 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8301 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
8302 !strconcat(OpcodeStr,
8303 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8305 (OpVT (OpNode RC:$src1,
8306 (bitconvert (memop_frag addr:$src2)), imm:$src3)))]>,
8307 Sched<[WriteBlendLd, ReadAfterLd]>, VEX_4V;
8310 defm VPBLENDD : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v4i32,
8311 VR128, loadv2i64, i128mem>;
8312 defm VPBLENDDY : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v8i32,
8313 VR256, loadv4i64, i256mem>, VEX_L;
8315 //===----------------------------------------------------------------------===//
8316 // VPBROADCAST - Load from memory and broadcast to all elements of the
8317 // destination operand
8319 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8320 X86MemOperand x86memop, PatFrag ld_frag,
8321 ValueType OpVT128, ValueType OpVT256, Predicate prd> {
8322 let Predicates = [HasAVX2, prd] in {
8323 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8324 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8326 (OpVT128 (X86VBroadcast (OpVT128 VR128:$src))))]>,
8327 Sched<[WriteShuffle]>, VEX;
8328 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8329 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8331 (OpVT128 (X86VBroadcast (ld_frag addr:$src))))]>,
8332 Sched<[WriteLoad]>, VEX;
8333 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8334 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8336 (OpVT256 (X86VBroadcast (OpVT128 VR128:$src))))]>,
8337 Sched<[WriteShuffle256]>, VEX, VEX_L;
8338 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8339 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8341 (OpVT256 (X86VBroadcast (ld_frag addr:$src))))]>,
8342 Sched<[WriteLoad]>, VEX, VEX_L;
8344 // Provide aliases for broadcast from the same register class that
8345 // automatically does the extract.
8346 def : Pat<(OpVT256 (X86VBroadcast (OpVT256 VR256:$src))),
8347 (!cast<Instruction>(NAME#"Yrr")
8348 (OpVT128 (EXTRACT_SUBREG (OpVT256 VR256:$src),sub_xmm)))>;
8352 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8353 v16i8, v32i8, NoVLX_Or_NoBWI>;
8354 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8355 v8i16, v16i16, NoVLX_Or_NoBWI>;
8356 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8357 v4i32, v8i32, NoVLX>;
8358 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8359 v2i64, v4i64, NoVLX>;
8361 let Predicates = [HasAVX2] in {
8362 // loadi16 is tricky to fold, because !isTypeDesirableForOp, justifiably.
8363 // This means we'll encounter truncated i32 loads; match that here.
8364 def : Pat<(v8i16 (X86VBroadcast (i16 (trunc (i32 (load addr:$src)))))),
8365 (VPBROADCASTWrm addr:$src)>;
8366 def : Pat<(v16i16 (X86VBroadcast (i16 (trunc (i32 (load addr:$src)))))),
8367 (VPBROADCASTWYrm addr:$src)>;
8369 // Provide aliases for broadcast from the same register class that
8370 // automatically does the extract.
8371 def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256:$src))),
8372 (VBROADCASTSSYrr (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src),
8374 def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256:$src))),
8375 (VBROADCASTSDYrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src),
8378 // Provide fallback in case the load node that is used in the patterns above
8379 // is used by additional users, which prevents the pattern selection.
8380 let AddedComplexity = 20 in {
8381 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8382 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8383 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8384 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8385 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8386 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8388 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8389 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8390 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8391 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8392 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8393 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8395 def : Pat<(v16i8 (X86VBroadcast GR8:$src)),
8396 (VPBROADCASTBrr (COPY_TO_REGCLASS
8397 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8399 def : Pat<(v32i8 (X86VBroadcast GR8:$src)),
8400 (VPBROADCASTBYrr (COPY_TO_REGCLASS
8401 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8404 def : Pat<(v8i16 (X86VBroadcast GR16:$src)),
8405 (VPBROADCASTWrr (COPY_TO_REGCLASS
8406 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8408 def : Pat<(v16i16 (X86VBroadcast GR16:$src)),
8409 (VPBROADCASTWYrr (COPY_TO_REGCLASS
8410 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8413 // The patterns for VPBROADCASTD are not needed because they would match
8414 // the exact same thing as VBROADCASTSS patterns.
8416 def : Pat<(v2i64 (X86VBroadcast GR64:$src)),
8417 (VPBROADCASTQrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8418 // The v4i64 pattern is not needed because VBROADCASTSDYrr already match.
8422 // AVX1 broadcast patterns
8423 let Predicates = [HasAVX1Only] in {
8424 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8425 (VBROADCASTSSYrm addr:$src)>;
8426 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8427 (VBROADCASTSDYrm addr:$src)>;
8428 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8429 (VBROADCASTSSrm addr:$src)>;
8432 let Predicates = [HasAVX] in {
8433 // Provide fallback in case the load node that is used in the patterns above
8434 // is used by additional users, which prevents the pattern selection.
8435 let AddedComplexity = 20 in {
8436 // 128bit broadcasts:
8437 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8438 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8439 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8440 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8441 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8442 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8443 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8444 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8445 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8446 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8448 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8449 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8450 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8451 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8452 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8453 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8454 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8455 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8456 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8457 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8460 def : Pat<(v2f64 (X86VBroadcast f64:$src)),
8461 (VMOVDDUPrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8462 def : Pat<(v2i64 (X86VBroadcast i64:$src)),
8463 (VMOVDDUPrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8466 //===----------------------------------------------------------------------===//
8467 // VPERM - Permute instructions
8470 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8471 ValueType OpVT, X86FoldableSchedWrite Sched> {
8472 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8473 (ins VR256:$src1, VR256:$src2),
8474 !strconcat(OpcodeStr,
8475 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8477 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8478 Sched<[Sched]>, VEX_4V, VEX_L;
8479 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8480 (ins VR256:$src1, i256mem:$src2),
8481 !strconcat(OpcodeStr,
8482 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8484 (OpVT (X86VPermv VR256:$src1,
8485 (bitconvert (mem_frag addr:$src2)))))]>,
8486 Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
8489 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteShuffle256>;
8490 let ExeDomain = SSEPackedSingle in
8491 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFShuffle256>;
8493 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8494 ValueType OpVT, X86FoldableSchedWrite Sched> {
8495 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8496 (ins VR256:$src1, u8imm:$src2),
8497 !strconcat(OpcodeStr,
8498 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8500 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8501 Sched<[Sched]>, VEX, VEX_L;
8502 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8503 (ins i256mem:$src1, u8imm:$src2),
8504 !strconcat(OpcodeStr,
8505 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8507 (OpVT (X86VPermi (mem_frag addr:$src1),
8508 (i8 imm:$src2))))]>,
8509 Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L;
8512 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64,
8513 WriteShuffle256>, VEX_W;
8514 let ExeDomain = SSEPackedDouble in
8515 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64,
8516 WriteFShuffle256>, VEX_W;
8518 //===----------------------------------------------------------------------===//
8519 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8521 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8522 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8523 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8524 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8525 (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>,
8527 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8528 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8529 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8530 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8532 Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8534 let Predicates = [HasAVX2] in {
8535 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8536 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8537 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8538 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8539 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8540 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8542 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8544 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8545 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8546 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8547 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8548 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8550 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8554 //===----------------------------------------------------------------------===//
8555 // VINSERTI128 - Insert packed integer values
8557 let hasSideEffects = 0 in {
8558 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8559 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
8560 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8561 []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L;
8563 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8564 (ins VR256:$src1, i128mem:$src2, u8imm:$src3),
8565 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8566 []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8569 let Predicates = [HasAVX2, NoVLX] in {
8570 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8572 (VINSERTI128rr VR256:$src1, VR128:$src2,
8573 (INSERT_get_vinsert128_imm VR256:$ins))>;
8574 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8576 (VINSERTI128rr VR256:$src1, VR128:$src2,
8577 (INSERT_get_vinsert128_imm VR256:$ins))>;
8578 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8580 (VINSERTI128rr VR256:$src1, VR128:$src2,
8581 (INSERT_get_vinsert128_imm VR256:$ins))>;
8582 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8584 (VINSERTI128rr VR256:$src1, VR128:$src2,
8585 (INSERT_get_vinsert128_imm VR256:$ins))>;
8587 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8589 (VINSERTI128rm VR256:$src1, addr:$src2,
8590 (INSERT_get_vinsert128_imm VR256:$ins))>;
8591 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8592 (bc_v4i32 (loadv2i64 addr:$src2)),
8594 (VINSERTI128rm VR256:$src1, addr:$src2,
8595 (INSERT_get_vinsert128_imm VR256:$ins))>;
8596 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8597 (bc_v16i8 (loadv2i64 addr:$src2)),
8599 (VINSERTI128rm VR256:$src1, addr:$src2,
8600 (INSERT_get_vinsert128_imm VR256:$ins))>;
8601 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8602 (bc_v8i16 (loadv2i64 addr:$src2)),
8604 (VINSERTI128rm VR256:$src1, addr:$src2,
8605 (INSERT_get_vinsert128_imm VR256:$ins))>;
8608 //===----------------------------------------------------------------------===//
8609 // VEXTRACTI128 - Extract packed integer values
8611 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8612 (ins VR256:$src1, u8imm:$src2),
8613 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8614 Sched<[WriteShuffle256]>, VEX, VEX_L;
8615 let hasSideEffects = 0, mayStore = 1 in
8616 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8617 (ins i128mem:$dst, VR256:$src1, u8imm:$src2),
8618 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8619 Sched<[WriteStore]>, VEX, VEX_L;
8621 let Predicates = [HasAVX2] in {
8622 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8623 (v2i64 (VEXTRACTI128rr
8624 (v4i64 VR256:$src1),
8625 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8626 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8627 (v4i32 (VEXTRACTI128rr
8628 (v8i32 VR256:$src1),
8629 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8630 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8631 (v8i16 (VEXTRACTI128rr
8632 (v16i16 VR256:$src1),
8633 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8634 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8635 (v16i8 (VEXTRACTI128rr
8636 (v32i8 VR256:$src1),
8637 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8639 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8640 (iPTR imm))), addr:$dst),
8641 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8642 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8643 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8644 (iPTR imm))), addr:$dst),
8645 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8646 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8647 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8648 (iPTR imm))), addr:$dst),
8649 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8650 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8651 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8652 (iPTR imm))), addr:$dst),
8653 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8654 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8657 //===----------------------------------------------------------------------===//
8658 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8660 multiclass avx2_pmovmask<string OpcodeStr,
8661 Intrinsic IntLd128, Intrinsic IntLd256,
8662 Intrinsic IntSt128, Intrinsic IntSt256> {
8663 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8664 (ins VR128:$src1, i128mem:$src2),
8665 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8666 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8667 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8668 (ins VR256:$src1, i256mem:$src2),
8669 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8670 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8672 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8673 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8674 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8675 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8676 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8677 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8678 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8679 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8682 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8683 int_x86_avx2_maskload_d,
8684 int_x86_avx2_maskload_d_256,
8685 int_x86_avx2_maskstore_d,
8686 int_x86_avx2_maskstore_d_256>;
8687 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8688 int_x86_avx2_maskload_q,
8689 int_x86_avx2_maskload_q_256,
8690 int_x86_avx2_maskstore_q,
8691 int_x86_avx2_maskstore_q_256>, VEX_W;
8693 def: Pat<(X86mstore addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src)),
8694 (VMASKMOVPSYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8696 def: Pat<(X86mstore addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src)),
8697 (VPMASKMOVDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8699 def: Pat<(X86mstore addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src)),
8700 (VMASKMOVPSmr addr:$ptr, VR128:$mask, VR128:$src)>;
8702 def: Pat<(X86mstore addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src)),
8703 (VPMASKMOVDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8705 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8706 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8708 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask),
8709 (bc_v8f32 (v8i32 immAllZerosV)))),
8710 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8712 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src0))),
8713 (VBLENDVPSYrr VR256:$src0, (VMASKMOVPSYrm VR256:$mask, addr:$ptr),
8716 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8717 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8719 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 immAllZerosV))),
8720 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8722 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src0))),
8723 (VBLENDVPSYrr VR256:$src0, (VPMASKMOVDYrm VR256:$mask, addr:$ptr),
8726 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
8727 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
8729 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask),
8730 (bc_v4f32 (v4i32 immAllZerosV)))),
8731 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
8733 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src0))),
8734 (VBLENDVPSrr VR128:$src0, (VMASKMOVPSrm VR128:$mask, addr:$ptr),
8737 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
8738 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
8740 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 immAllZerosV))),
8741 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
8743 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src0))),
8744 (VBLENDVPSrr VR128:$src0, (VPMASKMOVDrm VR128:$mask, addr:$ptr),
8747 def: Pat<(X86mstore addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src)),
8748 (VMASKMOVPDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8750 def: Pat<(X86mstore addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src)),
8751 (VPMASKMOVQYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8753 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
8754 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
8756 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
8757 (v4f64 immAllZerosV))),
8758 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
8760 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src0))),
8761 (VBLENDVPDYrr VR256:$src0, (VMASKMOVPDYrm VR256:$mask, addr:$ptr),
8764 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
8765 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
8767 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
8768 (bc_v4i64 (v8i32 immAllZerosV)))),
8769 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
8771 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src0))),
8772 (VBLENDVPDYrr VR256:$src0, (VPMASKMOVQYrm VR256:$mask, addr:$ptr),
8775 def: Pat<(X86mstore addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src)),
8776 (VMASKMOVPDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8778 def: Pat<(X86mstore addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src)),
8779 (VPMASKMOVQmr addr:$ptr, VR128:$mask, VR128:$src)>;
8781 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
8782 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
8784 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
8785 (v2f64 immAllZerosV))),
8786 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
8788 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src0))),
8789 (VBLENDVPDrr VR128:$src0, (VMASKMOVPDrm VR128:$mask, addr:$ptr),
8792 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
8793 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
8795 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
8796 (bc_v2i64 (v4i32 immAllZerosV)))),
8797 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
8799 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src0))),
8800 (VBLENDVPDrr VR128:$src0, (VPMASKMOVQrm VR128:$mask, addr:$ptr),
8803 //===----------------------------------------------------------------------===//
8804 // Variable Bit Shifts
8806 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8807 ValueType vt128, ValueType vt256> {
8808 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8809 (ins VR128:$src1, VR128:$src2),
8810 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8812 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8813 VEX_4V, Sched<[WriteVarVecShift]>;
8814 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8815 (ins VR128:$src1, i128mem:$src2),
8816 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8818 (vt128 (OpNode VR128:$src1,
8819 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
8820 VEX_4V, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8821 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8822 (ins VR256:$src1, VR256:$src2),
8823 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8825 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8826 VEX_4V, VEX_L, Sched<[WriteVarVecShift]>;
8827 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8828 (ins VR256:$src1, i256mem:$src2),
8829 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8831 (vt256 (OpNode VR256:$src1,
8832 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
8833 VEX_4V, VEX_L, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8836 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8837 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8838 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8839 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8840 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8842 //===----------------------------------------------------------------------===//
8843 // VGATHER - GATHER Operations
8844 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8845 X86MemOperand memop128, X86MemOperand memop256> {
8846 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8847 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8848 !strconcat(OpcodeStr,
8849 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8851 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8852 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8853 !strconcat(OpcodeStr,
8854 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8855 []>, VEX_4VOp3, VEX_L;
8858 let mayLoad = 1, Constraints
8859 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
8861 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8862 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8863 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8864 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;
8866 let ExeDomain = SSEPackedDouble in {
8867 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8868 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8871 let ExeDomain = SSEPackedSingle in {
8872 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8873 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;