1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 bit rr_hasSideEffects = 0> {
85 let isCommutable = 1, neverHasSideEffects = rr_hasSideEffects in
86 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
88 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
89 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
91 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
93 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
94 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
98 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
99 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
100 string asm, string SSEVer, string FPSizeStr,
101 X86MemOperand x86memop, PatFrag mem_frag,
102 Domain d, bit Is2Addr = 1> {
103 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
105 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
106 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
107 [(set RC:$dst, (!cast<Intrinsic>(
108 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
109 RC:$src1, RC:$src2))], d>;
110 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
112 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
113 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
114 [(set RC:$dst, (!cast<Intrinsic>(
115 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
116 RC:$src1, (mem_frag addr:$src2)))], d>;
119 //===----------------------------------------------------------------------===//
120 // Non-instruction patterns
121 //===----------------------------------------------------------------------===//
123 // A vector extract of the first f32/f64 position is a subregister copy
124 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
125 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
126 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
127 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
129 // A 128-bit subvector extract from the first 256-bit vector position
130 // is a subregister copy that needs no instruction.
131 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
132 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
133 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
134 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
136 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
137 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
138 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
139 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
141 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
142 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
143 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
144 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
146 // A 128-bit subvector insert to the first 256-bit vector position
147 // is a subregister copy that needs no instruction.
148 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
149 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
150 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
151 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
152 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
153 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
154 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
155 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
156 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
157 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
158 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
159 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
161 // Implicitly promote a 32-bit scalar to a vector.
162 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
163 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
164 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
165 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
166 // Implicitly promote a 64-bit scalar to a vector.
167 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
168 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
169 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
170 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
172 // Bitcasts between 128-bit vector types. Return the original type since
173 // no instruction is needed for the conversion
174 let Predicates = [HasXMMInt] in {
175 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
176 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
177 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
178 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
179 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
180 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
181 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
182 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
183 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
184 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
185 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
186 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
187 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
188 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
189 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
190 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
191 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
192 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
193 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
194 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
195 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
196 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
197 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
198 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
199 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
200 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
201 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
202 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
203 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
204 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
207 // Bitcasts between 256-bit vector types. Return the original type since
208 // no instruction is needed for the conversion
209 let Predicates = [HasAVX] in {
210 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
211 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
212 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
213 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
214 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
215 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
216 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
217 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
218 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
219 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
220 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
221 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
222 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
223 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
224 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
225 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
226 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
227 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
228 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
229 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
230 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
231 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
232 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
233 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
234 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
235 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
236 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
237 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
238 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
239 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
242 // Alias instructions that map fld0 to pxor for sse.
243 // FIXME: Set encoding to pseudo!
244 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
245 canFoldAsLoad = 1 in {
246 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
247 [(set FR32:$dst, fp32imm0)]>,
248 Requires<[HasSSE1]>, TB, OpSize;
249 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
250 [(set FR64:$dst, fpimm0)]>,
251 Requires<[HasSSE2]>, TB, OpSize;
252 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
253 [(set FR32:$dst, fp32imm0)]>,
254 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
255 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
256 [(set FR64:$dst, fpimm0)]>,
257 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
260 //===----------------------------------------------------------------------===//
261 // AVX & SSE - Zero/One Vectors
262 //===----------------------------------------------------------------------===//
264 // Alias instruction that maps zero vector to pxor / xorp* for sse.
265 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
266 // swizzled by ExecutionDepsFix to pxor.
267 // We set canFoldAsLoad because this can be converted to a constant-pool
268 // load of an all-zeros value if folding it would be beneficial.
269 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
270 isPseudo = 1, neverHasSideEffects = 1 in {
271 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "", []>;
274 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
275 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
276 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
277 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
278 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
279 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
282 // The same as done above but for AVX. The 256-bit ISA does not support PI,
283 // and doesn't need it because on sandy bridge the register is set to zero
284 // at the rename stage without using any execution unit, so SET0PSY
285 // and SET0PDY can be used for vector int instructions without penalty
286 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
287 // JIT implementatioan, it does not expand the instructions below like
288 // X86MCInstLower does.
289 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
290 isCodeGenOnly = 1, Predicates = [HasAVX] in {
291 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
292 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
293 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
294 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
298 // AVX has no support for 256-bit integer instructions, but since the 128-bit
299 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
300 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
301 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
302 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
304 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
305 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
306 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
308 // We set canFoldAsLoad because this can be converted to a constant-pool
309 // load of an all-ones value if folding it would be beneficial.
310 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
311 // JIT implementation, it does not expand the instructions below like
312 // X86MCInstLower does.
313 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
314 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
315 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
316 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
317 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
318 isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in
319 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
320 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
323 //===----------------------------------------------------------------------===//
324 // SSE 1 & 2 - Move FP Scalar Instructions
326 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
327 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
328 // is used instead. Register-to-register movss/movsd is not modeled as an
329 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
330 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
331 //===----------------------------------------------------------------------===//
333 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
334 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
335 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
337 // Loading from memory automatically zeroing upper bits.
338 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
339 PatFrag mem_pat, string OpcodeStr> :
340 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
341 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
342 [(set RC:$dst, (mem_pat addr:$src))]>;
345 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
346 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
348 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
349 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
352 // For the disassembler
353 let isCodeGenOnly = 1 in {
354 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
355 (ins VR128:$src1, FR32:$src2),
356 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
358 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
359 (ins VR128:$src1, FR64:$src2),
360 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
364 let canFoldAsLoad = 1, isReMaterializable = 1 in {
365 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
367 let AddedComplexity = 20 in
368 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
372 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
373 "movss\t{$src, $dst|$dst, $src}",
374 [(store FR32:$src, addr:$dst)]>, XS, VEX, VEX_LIG;
375 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
376 "movsd\t{$src, $dst|$dst, $src}",
377 [(store FR64:$src, addr:$dst)]>, XD, VEX, VEX_LIG;
380 let Constraints = "$src1 = $dst" in {
381 def MOVSSrr : sse12_move_rr<FR32, v4f32,
382 "movss\t{$src2, $dst|$dst, $src2}">, XS;
383 def MOVSDrr : sse12_move_rr<FR64, v2f64,
384 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
386 // For the disassembler
387 let isCodeGenOnly = 1 in {
388 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
389 (ins VR128:$src1, FR32:$src2),
390 "movss\t{$src2, $dst|$dst, $src2}", []>, XS;
391 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
392 (ins VR128:$src1, FR64:$src2),
393 "movsd\t{$src2, $dst|$dst, $src2}", []>, XD;
397 let canFoldAsLoad = 1, isReMaterializable = 1 in {
398 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
400 let AddedComplexity = 20 in
401 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
404 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
405 "movss\t{$src, $dst|$dst, $src}",
406 [(store FR32:$src, addr:$dst)]>;
407 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
408 "movsd\t{$src, $dst|$dst, $src}",
409 [(store FR64:$src, addr:$dst)]>;
412 let Predicates = [HasSSE1] in {
413 let AddedComplexity = 15 in {
414 // Extract the low 32-bit value from one vector and insert it into another.
415 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
416 (MOVSSrr (v4f32 VR128:$src1),
417 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
418 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
419 (MOVSSrr (v4i32 VR128:$src1),
420 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
422 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
423 // MOVSS to the lower bits.
424 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
425 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
426 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
427 (MOVSSrr (v4f32 (V_SET0)),
428 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
429 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
430 (MOVSSrr (v4i32 (V_SET0)),
431 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
434 let AddedComplexity = 20 in {
435 // MOVSSrm zeros the high parts of the register; represent this
436 // with SUBREG_TO_REG.
437 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
438 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
439 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
440 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
441 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
442 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
445 // Extract and store.
446 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
449 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
451 // Shuffle with MOVSS
452 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
453 (MOVSSrr VR128:$src1, FR32:$src2)>;
454 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
455 (MOVSSrr (v4i32 VR128:$src1),
456 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
457 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
458 (MOVSSrr (v4f32 VR128:$src1),
459 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
462 let Predicates = [HasSSE2] in {
463 let AddedComplexity = 15 in {
464 // Extract the low 64-bit value from one vector and insert it into another.
465 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
466 (MOVSDrr (v2f64 VR128:$src1),
467 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
468 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
469 (MOVSDrr (v2i64 VR128:$src1),
470 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
472 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
473 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
474 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
475 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
476 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
478 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
479 // MOVSD to the lower bits.
480 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
481 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
484 let AddedComplexity = 20 in {
485 // MOVSDrm zeros the high parts of the register; represent this
486 // with SUBREG_TO_REG.
487 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
488 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
489 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
490 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
491 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
492 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
493 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
494 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
495 def : Pat<(v2f64 (X86vzload addr:$src)),
496 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
499 // Extract and store.
500 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
503 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
505 // Shuffle with MOVSD
506 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
507 (MOVSDrr VR128:$src1, FR64:$src2)>;
508 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
509 (MOVSDrr (v2i64 VR128:$src1),
510 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
511 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
512 (MOVSDrr (v2f64 VR128:$src1),
513 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
514 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
515 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
516 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
517 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
519 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
520 // is during lowering, where it's not possible to recognize the fold cause
521 // it has two uses through a bitcast. One use disappears at isel time and the
522 // fold opportunity reappears.
523 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
524 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),sub_sd))>;
525 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
526 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),sub_sd))>;
527 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
528 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
529 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
530 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
533 let Predicates = [HasAVX] in {
534 let AddedComplexity = 15 in {
535 // Extract the low 32-bit value from one vector and insert it into another.
536 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
537 (VMOVSSrr (v4f32 VR128:$src1),
538 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
539 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
540 (VMOVSSrr (v4i32 VR128:$src1),
541 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
543 // Extract the low 64-bit value from one vector and insert it into another.
544 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
545 (VMOVSDrr (v2f64 VR128:$src1),
546 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
547 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
548 (VMOVSDrr (v2i64 VR128:$src1),
549 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
551 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
552 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
553 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
554 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
555 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
557 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
558 // MOVS{S,D} to the lower bits.
559 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
560 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
561 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
562 (VMOVSSrr (v4f32 (V_SET0)),
563 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
564 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
565 (VMOVSSrr (v4i32 (V_SET0)),
566 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
567 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
568 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
571 let AddedComplexity = 20 in {
572 // MOVSSrm zeros the high parts of the register; represent this
573 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
574 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
575 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
576 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
577 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
578 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
579 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
581 // MOVSDrm zeros the high parts of the register; represent this
582 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
583 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
584 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
585 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
586 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
587 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
588 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
589 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
590 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
591 def : Pat<(v2f64 (X86vzload addr:$src)),
592 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
594 // Represent the same patterns above but in the form they appear for
596 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
597 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
598 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
599 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
600 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
601 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
603 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
604 (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
605 (SUBREG_TO_REG (i32 0),
606 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
608 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
609 (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
610 (SUBREG_TO_REG (i64 0),
611 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
614 // Extract and store.
615 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
618 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
619 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
622 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
624 // Shuffle with VMOVSS
625 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
626 (VMOVSSrr VR128:$src1, FR32:$src2)>;
627 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
628 (VMOVSSrr (v4i32 VR128:$src1),
629 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
630 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
631 (VMOVSSrr (v4f32 VR128:$src1),
632 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
634 // Shuffle with VMOVSD
635 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
636 (VMOVSDrr VR128:$src1, FR64:$src2)>;
637 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
638 (VMOVSDrr (v2i64 VR128:$src1),
639 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
640 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
641 (VMOVSDrr (v2f64 VR128:$src1),
642 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
643 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
644 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
646 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
647 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
650 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
651 // is during lowering, where it's not possible to recognize the fold cause
652 // it has two uses through a bitcast. One use disappears at isel time and the
653 // fold opportunity reappears.
654 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
655 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),
657 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
658 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
660 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
661 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
665 //===----------------------------------------------------------------------===//
666 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
667 //===----------------------------------------------------------------------===//
669 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
670 X86MemOperand x86memop, PatFrag ld_frag,
671 string asm, Domain d,
672 bit IsReMaterializable = 1> {
673 let neverHasSideEffects = 1 in
674 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
675 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
676 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
677 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
678 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
679 [(set RC:$dst, (ld_frag addr:$src))], d>;
682 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
683 "movaps", SSEPackedSingle>, TB, VEX;
684 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
685 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
686 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
687 "movups", SSEPackedSingle>, TB, VEX;
688 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
689 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
691 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
692 "movaps", SSEPackedSingle>, TB, VEX;
693 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
694 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
695 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
696 "movups", SSEPackedSingle>, TB, VEX;
697 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
698 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
699 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
700 "movaps", SSEPackedSingle>, TB;
701 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
702 "movapd", SSEPackedDouble>, TB, OpSize;
703 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
704 "movups", SSEPackedSingle>, TB;
705 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
706 "movupd", SSEPackedDouble, 0>, TB, OpSize;
708 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
709 "movaps\t{$src, $dst|$dst, $src}",
710 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
711 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
712 "movapd\t{$src, $dst|$dst, $src}",
713 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
714 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
715 "movups\t{$src, $dst|$dst, $src}",
716 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
717 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
718 "movupd\t{$src, $dst|$dst, $src}",
719 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
720 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
721 "movaps\t{$src, $dst|$dst, $src}",
722 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)]>, VEX;
723 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
724 "movapd\t{$src, $dst|$dst, $src}",
725 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)]>, VEX;
726 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
727 "movups\t{$src, $dst|$dst, $src}",
728 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
729 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
730 "movupd\t{$src, $dst|$dst, $src}",
731 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
734 let isCodeGenOnly = 1 in {
735 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
737 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
738 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
740 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
741 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
743 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
744 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
746 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
747 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
749 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
750 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
752 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
753 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
755 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
756 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
758 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
761 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
762 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
763 (VMOVUPSYmr addr:$dst, VR256:$src)>;
765 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
766 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
767 (VMOVUPDYmr addr:$dst, VR256:$src)>;
769 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
770 "movaps\t{$src, $dst|$dst, $src}",
771 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
772 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
773 "movapd\t{$src, $dst|$dst, $src}",
774 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
775 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
776 "movups\t{$src, $dst|$dst, $src}",
777 [(store (v4f32 VR128:$src), addr:$dst)]>;
778 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
779 "movupd\t{$src, $dst|$dst, $src}",
780 [(store (v2f64 VR128:$src), addr:$dst)]>;
783 let isCodeGenOnly = 1 in {
784 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
785 "movaps\t{$src, $dst|$dst, $src}", []>;
786 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
787 "movapd\t{$src, $dst|$dst, $src}", []>;
788 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
789 "movups\t{$src, $dst|$dst, $src}", []>;
790 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
791 "movupd\t{$src, $dst|$dst, $src}", []>;
794 let Predicates = [HasAVX] in {
795 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
796 (VMOVUPSmr addr:$dst, VR128:$src)>;
797 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
798 (VMOVUPDmr addr:$dst, VR128:$src)>;
801 let Predicates = [HasSSE1] in
802 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
803 (MOVUPSmr addr:$dst, VR128:$src)>;
804 let Predicates = [HasSSE2] in
805 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
806 (MOVUPDmr addr:$dst, VR128:$src)>;
808 // Use movaps / movups for SSE integer load / store (one byte shorter).
809 // The instructions selected below are then converted to MOVDQA/MOVDQU
810 // during the SSE domain pass.
811 let Predicates = [HasSSE1] in {
812 def : Pat<(alignedloadv4i32 addr:$src),
813 (MOVAPSrm addr:$src)>;
814 def : Pat<(loadv4i32 addr:$src),
815 (MOVUPSrm addr:$src)>;
816 def : Pat<(alignedloadv2i64 addr:$src),
817 (MOVAPSrm addr:$src)>;
818 def : Pat<(loadv2i64 addr:$src),
819 (MOVUPSrm addr:$src)>;
821 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
822 (MOVAPSmr addr:$dst, VR128:$src)>;
823 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
824 (MOVAPSmr addr:$dst, VR128:$src)>;
825 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
826 (MOVAPSmr addr:$dst, VR128:$src)>;
827 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
828 (MOVAPSmr addr:$dst, VR128:$src)>;
829 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
830 (MOVUPSmr addr:$dst, VR128:$src)>;
831 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
832 (MOVUPSmr addr:$dst, VR128:$src)>;
833 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
834 (MOVUPSmr addr:$dst, VR128:$src)>;
835 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
836 (MOVUPSmr addr:$dst, VR128:$src)>;
839 // Use vmovaps/vmovups for AVX integer load/store.
840 let Predicates = [HasAVX] in {
841 // 128-bit load/store
842 def : Pat<(alignedloadv4i32 addr:$src),
843 (VMOVAPSrm addr:$src)>;
844 def : Pat<(loadv4i32 addr:$src),
845 (VMOVUPSrm addr:$src)>;
846 def : Pat<(alignedloadv2i64 addr:$src),
847 (VMOVAPSrm addr:$src)>;
848 def : Pat<(loadv2i64 addr:$src),
849 (VMOVUPSrm addr:$src)>;
851 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
852 (VMOVAPSmr addr:$dst, VR128:$src)>;
853 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
854 (VMOVAPSmr addr:$dst, VR128:$src)>;
855 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
856 (VMOVAPSmr addr:$dst, VR128:$src)>;
857 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
858 (VMOVAPSmr addr:$dst, VR128:$src)>;
859 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
860 (VMOVUPSmr addr:$dst, VR128:$src)>;
861 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
862 (VMOVUPSmr addr:$dst, VR128:$src)>;
863 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
864 (VMOVUPSmr addr:$dst, VR128:$src)>;
865 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
866 (VMOVUPSmr addr:$dst, VR128:$src)>;
868 // 256-bit load/store
869 def : Pat<(alignedloadv4i64 addr:$src),
870 (VMOVAPSYrm addr:$src)>;
871 def : Pat<(loadv4i64 addr:$src),
872 (VMOVUPSYrm addr:$src)>;
873 def : Pat<(alignedloadv8i32 addr:$src),
874 (VMOVAPSYrm addr:$src)>;
875 def : Pat<(loadv8i32 addr:$src),
876 (VMOVUPSYrm addr:$src)>;
877 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
878 (VMOVAPSYmr addr:$dst, VR256:$src)>;
879 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
880 (VMOVAPSYmr addr:$dst, VR256:$src)>;
881 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
882 (VMOVAPSYmr addr:$dst, VR256:$src)>;
883 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
884 (VMOVAPSYmr addr:$dst, VR256:$src)>;
885 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
886 (VMOVUPSYmr addr:$dst, VR256:$src)>;
887 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
888 (VMOVUPSYmr addr:$dst, VR256:$src)>;
889 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
890 (VMOVUPSYmr addr:$dst, VR256:$src)>;
891 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
892 (VMOVUPSYmr addr:$dst, VR256:$src)>;
895 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
896 // bits are disregarded. FIXME: Set encoding to pseudo!
897 let neverHasSideEffects = 1 in {
898 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
899 "movaps\t{$src, $dst|$dst, $src}", []>;
900 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
901 "movapd\t{$src, $dst|$dst, $src}", []>;
902 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
903 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
904 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
905 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
908 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
909 // bits are disregarded. FIXME: Set encoding to pseudo!
910 let canFoldAsLoad = 1, isReMaterializable = 1 in {
911 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
912 "movaps\t{$src, $dst|$dst, $src}",
913 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
914 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
915 "movapd\t{$src, $dst|$dst, $src}",
916 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
917 let isCodeGenOnly = 1 in {
918 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
919 "movaps\t{$src, $dst|$dst, $src}",
920 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>, VEX;
921 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
922 "movapd\t{$src, $dst|$dst, $src}",
923 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>, VEX;
927 //===----------------------------------------------------------------------===//
928 // SSE 1 & 2 - Move Low packed FP Instructions
929 //===----------------------------------------------------------------------===//
931 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
932 PatFrag mov_frag, string base_opc,
934 def PSrm : PI<opc, MRMSrcMem,
935 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
936 !strconcat(base_opc, "s", asm_opr),
939 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
940 SSEPackedSingle>, TB;
942 def PDrm : PI<opc, MRMSrcMem,
943 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
944 !strconcat(base_opc, "d", asm_opr),
945 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
946 (scalar_to_vector (loadf64 addr:$src2)))))],
947 SSEPackedDouble>, TB, OpSize;
950 let AddedComplexity = 20 in {
951 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
952 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
954 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
955 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
956 "\t{$src2, $dst|$dst, $src2}">;
959 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
960 "movlps\t{$src, $dst|$dst, $src}",
961 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
962 (iPTR 0))), addr:$dst)]>, VEX;
963 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
964 "movlpd\t{$src, $dst|$dst, $src}",
965 [(store (f64 (vector_extract (v2f64 VR128:$src),
966 (iPTR 0))), addr:$dst)]>, VEX;
967 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
968 "movlps\t{$src, $dst|$dst, $src}",
969 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
970 (iPTR 0))), addr:$dst)]>;
971 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
972 "movlpd\t{$src, $dst|$dst, $src}",
973 [(store (f64 (vector_extract (v2f64 VR128:$src),
974 (iPTR 0))), addr:$dst)]>;
976 let Predicates = [HasAVX] in {
977 let AddedComplexity = 20 in {
978 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
979 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
980 (VMOVLPSrm VR128:$src1, addr:$src2)>;
981 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
982 (VMOVLPSrm VR128:$src1, addr:$src2)>;
983 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
984 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
985 (VMOVLPDrm VR128:$src1, addr:$src2)>;
986 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
987 (VMOVLPDrm VR128:$src1, addr:$src2)>;
990 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
991 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
992 (VMOVLPSmr addr:$src1, VR128:$src2)>;
993 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
994 VR128:$src2)), addr:$src1),
995 (VMOVLPSmr addr:$src1, VR128:$src2)>;
997 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
998 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
999 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1000 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1001 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1003 // Shuffle with VMOVLPS
1004 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1005 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1006 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1007 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1008 def : Pat<(X86Movlps VR128:$src1,
1009 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1010 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1012 // Shuffle with VMOVLPD
1013 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1014 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1015 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1016 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1017 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1018 (scalar_to_vector (loadf64 addr:$src2)))),
1019 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1022 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1024 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1025 def : Pat<(store (v4i32 (X86Movlps
1026 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1027 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1028 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1030 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1031 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1033 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1036 let Predicates = [HasSSE1] in {
1037 let AddedComplexity = 20 in {
1038 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
1039 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
1040 (MOVLPSrm VR128:$src1, addr:$src2)>;
1041 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
1042 (MOVLPSrm VR128:$src1, addr:$src2)>;
1045 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1046 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1047 (iPTR 0))), addr:$src1),
1048 (MOVLPSmr addr:$src1, VR128:$src2)>;
1049 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1050 (MOVLPSmr addr:$src1, VR128:$src2)>;
1051 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
1052 VR128:$src2)), addr:$src1),
1053 (MOVLPSmr addr:$src1, VR128:$src2)>;
1055 // Shuffle with MOVLPS
1056 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1057 (MOVLPSrm VR128:$src1, addr:$src2)>;
1058 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1059 (MOVLPSrm VR128:$src1, addr:$src2)>;
1060 def : Pat<(X86Movlps VR128:$src1,
1061 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1062 (MOVLPSrm VR128:$src1, addr:$src2)>;
1063 def : Pat<(X86Movlps VR128:$src1,
1064 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1065 (MOVLPSrm VR128:$src1, addr:$src2)>;
1068 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1070 (MOVLPSmr addr:$src1, VR128:$src2)>;
1071 def : Pat<(store (v4i32 (X86Movlps
1072 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1074 (MOVLPSmr addr:$src1, VR128:$src2)>;
1077 let Predicates = [HasSSE2] in {
1078 let AddedComplexity = 20 in {
1079 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
1080 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
1081 (MOVLPDrm VR128:$src1, addr:$src2)>;
1082 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
1083 (MOVLPDrm VR128:$src1, addr:$src2)>;
1086 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
1087 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1088 (MOVLPDmr addr:$src1, VR128:$src2)>;
1089 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1090 (MOVLPDmr addr:$src1, VR128:$src2)>;
1092 // Shuffle with MOVLPD
1093 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1094 (MOVLPDrm VR128:$src1, addr:$src2)>;
1095 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1096 (MOVLPDrm VR128:$src1, addr:$src2)>;
1097 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1098 (scalar_to_vector (loadf64 addr:$src2)))),
1099 (MOVLPDrm VR128:$src1, addr:$src2)>;
1102 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1104 (MOVLPDmr addr:$src1, VR128:$src2)>;
1105 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1107 (MOVLPDmr addr:$src1, VR128:$src2)>;
1110 //===----------------------------------------------------------------------===//
1111 // SSE 1 & 2 - Move Hi packed FP Instructions
1112 //===----------------------------------------------------------------------===//
1114 let AddedComplexity = 20 in {
1115 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1116 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
1118 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1119 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1120 "\t{$src2, $dst|$dst, $src2}">;
1123 // v2f64 extract element 1 is always custom lowered to unpack high to low
1124 // and extract element 0 so the non-store version isn't too horrible.
1125 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1126 "movhps\t{$src, $dst|$dst, $src}",
1127 [(store (f64 (vector_extract
1128 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1129 (undef)), (iPTR 0))), addr:$dst)]>,
1131 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1132 "movhpd\t{$src, $dst|$dst, $src}",
1133 [(store (f64 (vector_extract
1134 (v2f64 (unpckh VR128:$src, (undef))),
1135 (iPTR 0))), addr:$dst)]>,
1137 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1138 "movhps\t{$src, $dst|$dst, $src}",
1139 [(store (f64 (vector_extract
1140 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1141 (undef)), (iPTR 0))), addr:$dst)]>;
1142 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1143 "movhpd\t{$src, $dst|$dst, $src}",
1144 [(store (f64 (vector_extract
1145 (v2f64 (unpckh VR128:$src, (undef))),
1146 (iPTR 0))), addr:$dst)]>;
1148 let Predicates = [HasAVX] in {
1150 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1151 (VMOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1152 def : Pat<(X86Movlhps VR128:$src1,
1153 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1154 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1155 def : Pat<(X86Movlhps VR128:$src1,
1156 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1157 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1159 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
1160 // is during lowering, where it's not possible to recognize the load fold cause
1161 // it has two uses through a bitcast. One use disappears at isel time and the
1162 // fold opportunity reappears.
1163 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
1164 (scalar_to_vector (loadf64 addr:$src2)))),
1165 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1167 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1168 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1169 (scalar_to_vector (loadf64 addr:$src2)))),
1170 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1173 def : Pat<(store (f64 (vector_extract
1174 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1175 (VMOVHPSmr addr:$dst, VR128:$src)>;
1176 def : Pat<(store (f64 (vector_extract
1177 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1178 (VMOVHPDmr addr:$dst, VR128:$src)>;
1181 let Predicates = [HasSSE1] in {
1183 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1184 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1185 def : Pat<(X86Movlhps VR128:$src1,
1186 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1187 (MOVHPSrm VR128:$src1, addr:$src2)>;
1188 def : Pat<(X86Movlhps VR128:$src1,
1189 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1190 (MOVHPSrm VR128:$src1, addr:$src2)>;
1193 def : Pat<(store (f64 (vector_extract
1194 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1195 (MOVHPSmr addr:$dst, VR128:$src)>;
1198 let Predicates = [HasSSE2] in {
1199 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
1200 // is during lowering, where it's not possible to recognize the load fold cause
1201 // it has two uses through a bitcast. One use disappears at isel time and the
1202 // fold opportunity reappears.
1203 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
1204 (scalar_to_vector (loadf64 addr:$src2)))),
1205 (MOVHPDrm VR128:$src1, addr:$src2)>;
1207 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1208 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1209 (scalar_to_vector (loadf64 addr:$src2)))),
1210 (MOVHPDrm VR128:$src1, addr:$src2)>;
1213 def : Pat<(store (f64 (vector_extract
1214 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
1215 (MOVHPDmr addr:$dst, VR128:$src)>;
1218 //===----------------------------------------------------------------------===//
1219 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1220 //===----------------------------------------------------------------------===//
1222 let AddedComplexity = 20 in {
1223 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1224 (ins VR128:$src1, VR128:$src2),
1225 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1227 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
1229 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1230 (ins VR128:$src1, VR128:$src2),
1231 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1233 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
1236 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1237 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1238 (ins VR128:$src1, VR128:$src2),
1239 "movlhps\t{$src2, $dst|$dst, $src2}",
1241 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
1242 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1243 (ins VR128:$src1, VR128:$src2),
1244 "movhlps\t{$src2, $dst|$dst, $src2}",
1246 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
1249 let Predicates = [HasAVX] in {
1251 let AddedComplexity = 20 in {
1252 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1253 (VMOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1254 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1255 (VMOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1257 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
1258 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
1259 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1261 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
1262 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1263 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1264 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1265 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1266 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1269 let AddedComplexity = 20 in {
1270 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
1271 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
1272 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1274 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
1275 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
1276 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
1277 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
1278 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
1281 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
1282 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1283 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1284 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1287 let Predicates = [HasSSE1] in {
1289 let AddedComplexity = 20 in {
1290 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1291 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1292 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1293 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1295 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
1296 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
1297 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1299 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
1300 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1301 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1302 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1303 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1304 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1307 let AddedComplexity = 20 in {
1308 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
1309 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
1310 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1312 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
1313 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
1314 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
1315 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
1316 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
1319 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
1320 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1321 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1322 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1325 //===----------------------------------------------------------------------===//
1326 // SSE 1 & 2 - Conversion Instructions
1327 //===----------------------------------------------------------------------===//
1329 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1330 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1332 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1333 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
1334 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1335 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
1338 multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1339 X86MemOperand x86memop, string asm> {
1340 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm, []>;
1342 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm, []>;
1345 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1346 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1347 string asm, Domain d> {
1348 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1349 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
1350 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1351 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
1354 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1355 X86MemOperand x86memop, string asm> {
1356 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1357 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1359 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1360 (ins DstRC:$src1, x86memop:$src),
1361 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1364 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1365 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1367 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1368 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1370 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1371 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX,
1373 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1374 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
1375 VEX, VEX_W, VEX_LIG;
1377 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1378 // register, but the same isn't true when only using memory operands,
1379 // provide other assembly "l" and "q" forms to address this explicitly
1380 // where appropriate to do so.
1381 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
1383 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
1384 VEX_4V, VEX_W, VEX_LIG;
1385 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
1387 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
1389 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
1390 VEX_4V, VEX_W, VEX_LIG;
1392 let Predicates = [HasAVX] in {
1393 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1394 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1395 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1396 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1397 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1398 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1399 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1400 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1402 def : Pat<(f32 (sint_to_fp GR32:$src)),
1403 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1404 def : Pat<(f32 (sint_to_fp GR64:$src)),
1405 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1406 def : Pat<(f64 (sint_to_fp GR32:$src)),
1407 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1408 def : Pat<(f64 (sint_to_fp GR64:$src)),
1409 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1412 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1413 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
1414 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1415 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1416 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1417 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
1418 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1419 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1420 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1421 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
1422 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1423 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1424 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1425 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
1426 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1427 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1429 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1430 // and/or XMM operand(s).
1432 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1433 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
1435 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1436 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1437 [(set DstRC:$dst, (Int SrcRC:$src))]>;
1438 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
1439 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1440 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
1443 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1444 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1445 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
1446 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1448 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1449 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1450 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
1451 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1452 (ins DstRC:$src1, x86memop:$src2),
1454 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1455 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1456 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
1459 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1460 f128mem, load, "cvtsd2si">, XD, VEX;
1461 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1462 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
1465 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
1466 // Get rid of this hack or rename the intrinsics, there are several
1467 // intructions that only match with the intrinsic form, why create duplicates
1468 // to let them be recognized by the assembler?
1469 defm VCVTSD2SI : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
1470 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_LIG;
1471 defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
1472 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W,
1475 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1476 f128mem, load, "cvtsd2si{l}">, XD;
1477 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1478 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
1481 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1482 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
1483 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1484 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
1486 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1487 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
1488 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1489 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
1492 let Constraints = "$src1 = $dst" in {
1493 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1494 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1496 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1497 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1498 "cvtsi2ss{q}">, XS, REX_W;
1499 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1500 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1502 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1503 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1504 "cvtsi2sd">, XD, REX_W;
1509 // Aliases for intrinsics
1510 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1511 f32mem, load, "cvttss2si">, XS, VEX;
1512 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1513 int_x86_sse_cvttss2si64, f32mem, load,
1514 "cvttss2si">, XS, VEX, VEX_W;
1515 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1516 f128mem, load, "cvttsd2si">, XD, VEX;
1517 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1518 int_x86_sse2_cvttsd2si64, f128mem, load,
1519 "cvttsd2si">, XD, VEX, VEX_W;
1520 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1521 f32mem, load, "cvttss2si">, XS;
1522 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1523 int_x86_sse_cvttss2si64, f32mem, load,
1524 "cvttss2si{q}">, XS, REX_W;
1525 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1526 f128mem, load, "cvttsd2si">, XD;
1527 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1528 int_x86_sse2_cvttsd2si64, f128mem, load,
1529 "cvttsd2si{q}">, XD, REX_W;
1531 let Pattern = []<dag> in {
1532 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
1533 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS,
1535 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
1536 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1538 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
1539 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1540 SSEPackedSingle>, TB, VEX;
1541 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
1542 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1543 SSEPackedSingle>, TB, VEX;
1546 let Pattern = []<dag> in {
1547 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
1548 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
1549 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
1550 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1551 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
1552 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1553 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
1556 let Predicates = [HasSSE1] in {
1557 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1558 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1559 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1560 (CVTSS2SIrm addr:$src)>;
1561 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1562 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1563 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1564 (CVTSS2SI64rm addr:$src)>;
1567 let Predicates = [HasAVX] in {
1568 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1569 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1570 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1571 (VCVTSS2SIrm addr:$src)>;
1572 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1573 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1574 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1575 (VCVTSS2SI64rm addr:$src)>;
1580 // Convert scalar double to scalar single
1581 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1582 (ins FR64:$src1, FR64:$src2),
1583 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
1586 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1587 (ins FR64:$src1, f64mem:$src2),
1588 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1589 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1591 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1594 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1595 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1596 [(set FR32:$dst, (fround FR64:$src))]>;
1597 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1598 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1599 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1600 Requires<[HasSSE2, OptForSize]>;
1602 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1603 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
1605 let Constraints = "$src1 = $dst" in
1606 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1607 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
1609 // Convert scalar single to scalar double
1610 // SSE2 instructions with XS prefix
1611 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1612 (ins FR32:$src1, FR32:$src2),
1613 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1614 []>, XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1616 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1617 (ins FR32:$src1, f32mem:$src2),
1618 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1619 []>, XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1621 let Predicates = [HasAVX] in {
1622 def : Pat<(f64 (fextend FR32:$src)),
1623 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
1624 def : Pat<(fextend (loadf32 addr:$src)),
1625 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1626 def : Pat<(extloadf32 addr:$src),
1627 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1630 def : Pat<(extloadf32 addr:$src),
1631 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (MOVSSrm addr:$src))>,
1632 Requires<[HasAVX, OptForSpeed]>;
1634 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1635 "cvtss2sd\t{$src, $dst|$dst, $src}",
1636 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1637 Requires<[HasSSE2]>;
1638 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1639 "cvtss2sd\t{$src, $dst|$dst, $src}",
1640 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1641 Requires<[HasSSE2, OptForSize]>;
1643 // extload f32 -> f64. This matches load+fextend because we have a hack in
1644 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1646 // Since these loads aren't folded into the fextend, we have to match it
1648 def : Pat<(fextend (loadf32 addr:$src)),
1649 (CVTSS2SDrm addr:$src)>, Requires<[HasSSE2]>;
1650 def : Pat<(extloadf32 addr:$src),
1651 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1653 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1654 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1655 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1656 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1657 VR128:$src2))]>, XS, VEX_4V,
1659 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1660 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1661 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1662 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1663 (load addr:$src2)))]>, XS, VEX_4V,
1665 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1666 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1667 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1668 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1669 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1670 VR128:$src2))]>, XS,
1671 Requires<[HasSSE2]>;
1672 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1673 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1674 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1675 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1676 (load addr:$src2)))]>, XS,
1677 Requires<[HasSSE2]>;
1680 // Convert doubleword to packed single/double fp
1681 // SSE2 instructions without OpSize prefix
1682 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1683 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1684 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1685 TB, VEX, Requires<[HasAVX]>;
1686 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1687 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1688 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1689 (bitconvert (memopv2i64 addr:$src))))]>,
1690 TB, VEX, Requires<[HasAVX]>;
1691 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1692 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1693 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1694 TB, Requires<[HasSSE2]>;
1695 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1696 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1697 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1698 (bitconvert (memopv2i64 addr:$src))))]>,
1699 TB, Requires<[HasSSE2]>;
1701 // FIXME: why the non-intrinsic version is described as SSE3?
1702 // SSE2 instructions with XS prefix
1703 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1704 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1705 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1706 XS, VEX, Requires<[HasAVX]>;
1707 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1708 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1709 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1710 (bitconvert (memopv2i64 addr:$src))))]>,
1711 XS, VEX, Requires<[HasAVX]>;
1712 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1713 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1714 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1715 XS, Requires<[HasSSE2]>;
1716 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1717 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1718 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1719 (bitconvert (memopv2i64 addr:$src))))]>,
1720 XS, Requires<[HasSSE2]>;
1723 // Convert packed single/double fp to doubleword
1724 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1725 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1726 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1727 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1728 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1729 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1730 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1731 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1732 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1733 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1734 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1735 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1737 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1738 "cvtps2dq\t{$src, $dst|$dst, $src}",
1739 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
1741 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1743 "cvtps2dq\t{$src, $dst|$dst, $src}",
1744 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1745 (memop addr:$src)))]>, VEX;
1746 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1747 "cvtps2dq\t{$src, $dst|$dst, $src}",
1748 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1749 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1750 "cvtps2dq\t{$src, $dst|$dst, $src}",
1751 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1752 (memop addr:$src)))]>;
1754 // SSE2 packed instructions with XD prefix
1755 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1756 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1757 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1758 XD, VEX, Requires<[HasAVX]>;
1759 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1760 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1761 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1762 (memop addr:$src)))]>,
1763 XD, VEX, Requires<[HasAVX]>;
1764 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1765 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1766 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1767 XD, Requires<[HasSSE2]>;
1768 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1769 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1770 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1771 (memop addr:$src)))]>,
1772 XD, Requires<[HasSSE2]>;
1775 // Convert with truncation packed single/double fp to doubleword
1776 // SSE2 packed instructions with XS prefix
1777 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1778 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1780 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1781 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1782 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1783 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1785 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1786 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1787 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1788 "cvttps2dq\t{$src, $dst|$dst, $src}",
1790 (int_x86_sse2_cvttps2dq VR128:$src))]>;
1791 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1792 "cvttps2dq\t{$src, $dst|$dst, $src}",
1794 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
1796 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1797 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1799 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1800 XS, VEX, Requires<[HasAVX]>;
1801 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1802 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1803 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1804 (memop addr:$src)))]>,
1805 XS, VEX, Requires<[HasAVX]>;
1807 let Predicates = [HasSSE2] in {
1808 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1809 (Int_CVTDQ2PSrr VR128:$src)>;
1810 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1811 (CVTTPS2DQrr VR128:$src)>;
1814 let Predicates = [HasAVX] in {
1815 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1816 (Int_VCVTDQ2PSrr VR128:$src)>;
1817 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1818 (VCVTTPS2DQrr VR128:$src)>;
1819 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1820 (VCVTDQ2PSYrr VR256:$src)>;
1821 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1822 (VCVTTPS2DQYrr VR256:$src)>;
1825 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1826 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1828 (int_x86_sse2_cvttpd2dq VR128:$src))]>, VEX;
1829 let isCodeGenOnly = 1 in
1830 def VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1831 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1832 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1833 (memop addr:$src)))]>, VEX;
1834 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1835 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1836 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1837 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1838 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1839 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1840 (memop addr:$src)))]>;
1842 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1843 // register, but the same isn't true when using memory operands instead.
1844 // Provide other assembly rr and rm forms to address this explicitly.
1845 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1846 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1849 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1850 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1851 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1852 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1855 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1856 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
1857 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1858 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1860 // Convert packed single to packed double
1861 let Predicates = [HasAVX] in {
1862 // SSE2 instructions without OpSize prefix
1863 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1864 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1865 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1866 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1867 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1868 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1869 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1870 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1872 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1873 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1874 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1875 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1877 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1878 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1879 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1880 TB, VEX, Requires<[HasAVX]>;
1881 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1882 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1883 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1884 (load addr:$src)))]>,
1885 TB, VEX, Requires<[HasAVX]>;
1886 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1887 "cvtps2pd\t{$src, $dst|$dst, $src}",
1888 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1889 TB, Requires<[HasSSE2]>;
1890 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1891 "cvtps2pd\t{$src, $dst|$dst, $src}",
1892 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1893 (load addr:$src)))]>,
1894 TB, Requires<[HasSSE2]>;
1896 // Convert packed double to packed single
1897 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1898 // register, but the same isn't true when using memory operands instead.
1899 // Provide other assembly rr and rm forms to address this explicitly.
1900 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1901 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1902 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1903 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1906 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1907 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1908 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1909 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1912 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1913 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1914 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1915 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1916 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1917 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1918 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1919 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1922 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1923 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1924 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1925 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1927 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1928 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1929 (memop addr:$src)))]>;
1930 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1931 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1932 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1933 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1934 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1935 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1936 (memop addr:$src)))]>;
1938 // AVX 256-bit register conversion intrinsics
1939 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1940 // whenever possible to avoid declaring two versions of each one.
1941 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1942 (VCVTDQ2PSYrr VR256:$src)>;
1943 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
1944 (VCVTDQ2PSYrm addr:$src)>;
1946 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1947 (VCVTPD2PSYrr VR256:$src)>;
1948 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1949 (VCVTPD2PSYrm addr:$src)>;
1951 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1952 (VCVTPS2DQYrr VR256:$src)>;
1953 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1954 (VCVTPS2DQYrm addr:$src)>;
1956 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1957 (VCVTPS2PDYrr VR128:$src)>;
1958 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1959 (VCVTPS2PDYrm addr:$src)>;
1961 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1962 (VCVTTPD2DQYrr VR256:$src)>;
1963 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1964 (VCVTTPD2DQYrm addr:$src)>;
1966 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1967 (VCVTTPS2DQYrr VR256:$src)>;
1968 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1969 (VCVTTPS2DQYrm addr:$src)>;
1971 // Match fround and fextend for 128/256-bit conversions
1972 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
1973 (VCVTPD2PSYrr VR256:$src)>;
1974 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
1975 (VCVTPD2PSYrm addr:$src)>;
1977 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
1978 (VCVTPS2PDYrr VR128:$src)>;
1979 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
1980 (VCVTPS2PDYrm addr:$src)>;
1982 //===----------------------------------------------------------------------===//
1983 // SSE 1 & 2 - Compare Instructions
1984 //===----------------------------------------------------------------------===//
1986 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1987 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1988 SDNode OpNode, ValueType VT, PatFrag ld_frag,
1989 string asm, string asm_alt> {
1990 def rr : SIi8<0xC2, MRMSrcReg,
1991 (outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
1992 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))]>;
1993 def rm : SIi8<0xC2, MRMSrcMem,
1994 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, SSECC:$cc), asm,
1995 [(set RC:$dst, (OpNode (VT RC:$src1),
1996 (ld_frag addr:$src2), imm:$cc))]>;
1998 // Accept explicit immediate argument form instead of comparison code.
1999 let neverHasSideEffects = 1 in {
2000 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2001 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, []>;
2003 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2004 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, []>;
2008 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, X86cmpss, f32, loadf32,
2009 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2010 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
2011 XS, VEX_4V, VEX_LIG;
2012 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, X86cmpsd, f64, loadf64,
2013 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2014 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
2015 XD, VEX_4V, VEX_LIG;
2017 let Constraints = "$src1 = $dst" in {
2018 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, X86cmpss, f32, loadf32,
2019 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2020 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}">,
2022 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, X86cmpsd, f64, loadf64,
2023 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2024 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}">,
2028 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
2029 Intrinsic Int, string asm> {
2030 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2031 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
2032 [(set VR128:$dst, (Int VR128:$src1,
2033 VR128:$src, imm:$cc))]>;
2034 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2035 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
2036 [(set VR128:$dst, (Int VR128:$src1,
2037 (load addr:$src), imm:$cc))]>;
2040 // Aliases to match intrinsics which expect XMM operand(s).
2041 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2042 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
2044 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2045 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
2047 let Constraints = "$src1 = $dst" in {
2048 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2049 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
2050 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2051 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
2055 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2056 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2057 ValueType vt, X86MemOperand x86memop,
2058 PatFrag ld_frag, string OpcodeStr, Domain d> {
2059 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2060 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2061 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
2062 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2063 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2064 [(set EFLAGS, (OpNode (vt RC:$src1),
2065 (ld_frag addr:$src2)))], d>;
2068 let Defs = [EFLAGS] in {
2069 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2070 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2071 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2072 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2074 let Pattern = []<dag> in {
2075 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2076 "comiss", SSEPackedSingle>, TB, VEX,
2078 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2079 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2083 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2084 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2085 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2086 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2088 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2089 load, "comiss", SSEPackedSingle>, TB, VEX;
2090 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2091 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2092 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2093 "ucomiss", SSEPackedSingle>, TB;
2094 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2095 "ucomisd", SSEPackedDouble>, TB, OpSize;
2097 let Pattern = []<dag> in {
2098 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2099 "comiss", SSEPackedSingle>, TB;
2100 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2101 "comisd", SSEPackedDouble>, TB, OpSize;
2104 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2105 load, "ucomiss", SSEPackedSingle>, TB;
2106 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2107 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2109 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2110 "comiss", SSEPackedSingle>, TB;
2111 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2112 "comisd", SSEPackedDouble>, TB, OpSize;
2113 } // Defs = [EFLAGS]
2115 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
2116 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2117 Intrinsic Int, string asm, string asm_alt,
2119 let isAsmParserOnly = 1 in {
2120 def rri : PIi8<0xC2, MRMSrcReg,
2121 (outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
2122 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))], d>;
2123 def rmi : PIi8<0xC2, MRMSrcMem,
2124 (outs RC:$dst), (ins RC:$src1, f128mem:$src2, SSECC:$cc), asm,
2125 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))], d>;
2128 // Accept explicit immediate argument form instead of comparison code.
2129 def rri_alt : PIi8<0xC2, MRMSrcReg,
2130 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2132 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2133 (outs RC:$dst), (ins RC:$src1, f128mem:$src2, i8imm:$cc),
2137 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2138 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2139 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2140 SSEPackedSingle>, TB, VEX_4V;
2141 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2142 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2143 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2144 SSEPackedDouble>, TB, OpSize, VEX_4V;
2145 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
2146 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2147 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2148 SSEPackedSingle>, TB, VEX_4V;
2149 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
2150 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2151 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2152 SSEPackedDouble>, TB, OpSize, VEX_4V;
2153 let Constraints = "$src1 = $dst" in {
2154 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2155 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2156 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2157 SSEPackedSingle>, TB;
2158 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2159 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2160 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2161 SSEPackedDouble>, TB, OpSize;
2164 let Predicates = [HasSSE1] in {
2165 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2166 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2167 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2168 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2171 let Predicates = [HasSSE2] in {
2172 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2173 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2174 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2175 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2178 let Predicates = [HasAVX] in {
2179 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2180 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2181 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2182 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2183 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2184 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2185 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2186 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2188 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2189 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2190 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2191 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2192 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2193 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2194 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2195 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2198 //===----------------------------------------------------------------------===//
2199 // SSE 1 & 2 - Shuffle Instructions
2200 //===----------------------------------------------------------------------===//
2202 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2203 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2204 ValueType vt, string asm, PatFrag mem_frag,
2205 Domain d, bit IsConvertibleToThreeAddress = 0> {
2206 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2207 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
2208 [(set RC:$dst, (vt (shufp:$src3
2209 RC:$src1, (mem_frag addr:$src2))))], d>;
2210 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2211 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2212 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2214 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
2217 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2218 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2219 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2220 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2221 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2222 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2223 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2224 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2225 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2226 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2227 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2228 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2230 let Constraints = "$src1 = $dst" in {
2231 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2232 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2233 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2235 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2236 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2237 memopv2f64, SSEPackedDouble>, TB, OpSize;
2240 let Predicates = [HasSSE1] in {
2241 def : Pat<(v4f32 (X86Shufps VR128:$src1,
2242 (memopv4f32 addr:$src2), (i8 imm:$imm))),
2243 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2244 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2245 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2246 def : Pat<(v4i32 (X86Shufps VR128:$src1,
2247 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2248 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2249 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2250 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2251 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2252 // fall back to this for SSE1)
2253 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2254 (SHUFPSrri VR128:$src2, VR128:$src1,
2255 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2256 // Special unary SHUFPSrri case.
2257 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2258 (SHUFPSrri VR128:$src1, VR128:$src1,
2259 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2262 let Predicates = [HasSSE2] in {
2263 // Special binary v4i32 shuffle cases with SHUFPS.
2264 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2265 (SHUFPSrri VR128:$src1, VR128:$src2,
2266 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2267 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
2268 (bc_v4i32 (memopv2i64 addr:$src2)))),
2269 (SHUFPSrmi VR128:$src1, addr:$src2,
2270 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2271 // Special unary SHUFPDrri cases.
2272 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2273 (SHUFPDrri VR128:$src1, VR128:$src1,
2274 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2275 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2276 (SHUFPDrri VR128:$src1, VR128:$src1,
2277 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2278 // Special binary v2i64 shuffle cases using SHUFPDrri.
2279 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2280 (SHUFPDrri VR128:$src1, VR128:$src2,
2281 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2282 // Generic SHUFPD patterns
2283 def : Pat<(v2f64 (X86Shufps VR128:$src1,
2284 (memopv2f64 addr:$src2), (i8 imm:$imm))),
2285 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2286 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2287 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2288 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2289 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2292 let Predicates = [HasAVX] in {
2293 def : Pat<(v4f32 (X86Shufps VR128:$src1,
2294 (memopv4f32 addr:$src2), (i8 imm:$imm))),
2295 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2296 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2297 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2298 def : Pat<(v4i32 (X86Shufps VR128:$src1,
2299 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2300 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2301 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2302 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2303 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2304 // fall back to this for SSE1)
2305 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2306 (VSHUFPSrri VR128:$src2, VR128:$src1,
2307 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2308 // Special unary SHUFPSrri case.
2309 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2310 (VSHUFPSrri VR128:$src1, VR128:$src1,
2311 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2312 // Special binary v4i32 shuffle cases with SHUFPS.
2313 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2314 (VSHUFPSrri VR128:$src1, VR128:$src2,
2315 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2316 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
2317 (bc_v4i32 (memopv2i64 addr:$src2)))),
2318 (VSHUFPSrmi VR128:$src1, addr:$src2,
2319 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2320 // Special unary SHUFPDrri cases.
2321 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2322 (VSHUFPDrri VR128:$src1, VR128:$src1,
2323 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2324 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2325 (VSHUFPDrri VR128:$src1, VR128:$src1,
2326 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2327 // Special binary v2i64 shuffle cases using SHUFPDrri.
2328 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2329 (VSHUFPDrri VR128:$src1, VR128:$src2,
2330 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2332 def : Pat<(v2f64 (X86Shufps VR128:$src1,
2333 (memopv2f64 addr:$src2), (i8 imm:$imm))),
2334 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2335 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2336 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2337 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2338 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2341 def : Pat<(v8i32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2342 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2343 def : Pat<(v8i32 (X86Shufps VR256:$src1,
2344 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2345 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2347 def : Pat<(v8f32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2348 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2349 def : Pat<(v8f32 (X86Shufps VR256:$src1,
2350 (memopv8f32 addr:$src2), (i8 imm:$imm))),
2351 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2353 def : Pat<(v4i64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2354 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2355 def : Pat<(v4i64 (X86Shufpd VR256:$src1,
2356 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2357 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2359 def : Pat<(v4f64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2360 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2361 def : Pat<(v4f64 (X86Shufpd VR256:$src1,
2362 (memopv4f64 addr:$src2), (i8 imm:$imm))),
2363 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2366 //===----------------------------------------------------------------------===//
2367 // SSE 1 & 2 - Unpack Instructions
2368 //===----------------------------------------------------------------------===//
2370 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2371 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
2372 PatFrag mem_frag, RegisterClass RC,
2373 X86MemOperand x86memop, string asm,
2375 def rr : PI<opc, MRMSrcReg,
2376 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2378 (vt (OpNode RC:$src1, RC:$src2)))], d>;
2379 def rm : PI<opc, MRMSrcMem,
2380 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2382 (vt (OpNode RC:$src1,
2383 (mem_frag addr:$src2))))], d>;
2386 let AddedComplexity = 10 in {
2387 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2388 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2389 SSEPackedSingle>, TB, VEX_4V;
2390 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2391 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2392 SSEPackedDouble>, TB, OpSize, VEX_4V;
2393 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2394 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2395 SSEPackedSingle>, TB, VEX_4V;
2396 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2397 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2398 SSEPackedDouble>, TB, OpSize, VEX_4V;
2400 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
2401 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2402 SSEPackedSingle>, TB, VEX_4V;
2403 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
2404 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2405 SSEPackedDouble>, TB, OpSize, VEX_4V;
2406 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
2407 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2408 SSEPackedSingle>, TB, VEX_4V;
2409 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
2410 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2411 SSEPackedDouble>, TB, OpSize, VEX_4V;
2413 let Constraints = "$src1 = $dst" in {
2414 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2415 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2416 SSEPackedSingle>, TB;
2417 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2418 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2419 SSEPackedDouble>, TB, OpSize;
2420 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2421 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2422 SSEPackedSingle>, TB;
2423 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2424 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2425 SSEPackedDouble>, TB, OpSize;
2426 } // Constraints = "$src1 = $dst"
2427 } // AddedComplexity
2429 let Predicates = [HasSSE1] in {
2430 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
2431 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
2432 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
2433 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
2434 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
2435 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
2436 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
2437 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
2440 let Predicates = [HasSSE2] in {
2441 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
2442 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
2443 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
2444 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
2445 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
2446 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
2447 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
2448 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
2450 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
2451 // problem is during lowering, where it's not possible to recognize the load
2452 // fold cause it has two uses through a bitcast. One use disappears at isel
2453 // time and the fold opportunity reappears.
2454 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2455 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2457 let AddedComplexity = 10 in
2458 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2459 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2462 let Predicates = [HasAVX] in {
2463 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
2464 (VUNPCKLPSrm VR128:$src1, addr:$src2)>;
2465 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
2466 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>;
2467 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
2468 (VUNPCKHPSrm VR128:$src1, addr:$src2)>;
2469 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
2470 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>;
2472 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
2473 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2474 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
2475 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2476 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
2477 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2478 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, (memopv8i32 addr:$src2))),
2479 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2480 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, (memopv8f32 addr:$src2))),
2481 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2482 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
2483 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2484 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, (memopv8i32 addr:$src2))),
2485 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2486 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
2487 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2489 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
2490 (VUNPCKLPDrm VR128:$src1, addr:$src2)>;
2491 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
2492 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>;
2493 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
2494 (VUNPCKHPDrm VR128:$src1, addr:$src2)>;
2495 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
2496 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>;
2498 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
2499 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2500 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
2501 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2502 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, (memopv4i64 addr:$src2))),
2503 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2504 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
2505 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2506 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, (memopv4f64 addr:$src2))),
2507 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2508 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
2509 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2510 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, (memopv4i64 addr:$src2))),
2511 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2512 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
2513 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2515 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
2516 // problem is during lowering, where it's not possible to recognize the load
2517 // fold cause it has two uses through a bitcast. One use disappears at isel
2518 // time and the fold opportunity reappears.
2519 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2520 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2521 let AddedComplexity = 10 in
2522 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2523 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2526 //===----------------------------------------------------------------------===//
2527 // SSE 1 & 2 - Extract Floating-Point Sign mask
2528 //===----------------------------------------------------------------------===//
2530 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2531 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2533 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2534 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2535 [(set GR32:$dst, (Int RC:$src))], d>;
2536 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2537 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
2540 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2541 SSEPackedSingle>, TB;
2542 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2543 SSEPackedDouble>, TB, OpSize;
2545 def : Pat<(i32 (X86fgetsign FR32:$src)),
2546 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2547 sub_ss))>, Requires<[HasSSE1]>;
2548 def : Pat<(i64 (X86fgetsign FR32:$src)),
2549 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2550 sub_ss))>, Requires<[HasSSE1]>;
2551 def : Pat<(i32 (X86fgetsign FR64:$src)),
2552 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2553 sub_sd))>, Requires<[HasSSE2]>;
2554 def : Pat<(i64 (X86fgetsign FR64:$src)),
2555 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2556 sub_sd))>, Requires<[HasSSE2]>;
2558 let Predicates = [HasAVX] in {
2559 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2560 "movmskps", SSEPackedSingle>, TB, VEX;
2561 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2562 "movmskpd", SSEPackedDouble>, TB,
2564 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2565 "movmskps", SSEPackedSingle>, TB, VEX;
2566 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2567 "movmskpd", SSEPackedDouble>, TB,
2570 def : Pat<(i32 (X86fgetsign FR32:$src)),
2571 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2573 def : Pat<(i64 (X86fgetsign FR32:$src)),
2574 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2576 def : Pat<(i32 (X86fgetsign FR64:$src)),
2577 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2579 def : Pat<(i64 (X86fgetsign FR64:$src)),
2580 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2584 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2585 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2586 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2587 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
2589 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2590 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2591 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2592 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
2596 //===----------------------------------------------------------------------===//
2597 // SSE 1 & 2 - Logical Instructions
2598 //===----------------------------------------------------------------------===//
2600 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2602 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2604 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2605 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, TB, VEX_4V;
2607 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2608 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, TB, OpSize, VEX_4V;
2610 let Constraints = "$src1 = $dst" in {
2611 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2612 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
2614 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2615 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
2619 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2620 let mayLoad = 0 in {
2621 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
2622 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
2623 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
2626 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2627 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
2629 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2631 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2633 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2634 // are all promoted to v2i64, and the patterns are covered by the int
2635 // version. This is needed in SSE only, because v2i64 isn't supported on
2636 // SSE1, but only on SSE2.
2637 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2638 !strconcat(OpcodeStr, "ps"), f128mem, [],
2639 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2640 (memopv2i64 addr:$src2)))], 0, 1>, TB, VEX_4V;
2642 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2643 !strconcat(OpcodeStr, "pd"), f128mem,
2644 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2645 (bc_v2i64 (v2f64 VR128:$src2))))],
2646 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2647 (memopv2i64 addr:$src2)))], 0>,
2649 let Constraints = "$src1 = $dst" in {
2650 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2651 !strconcat(OpcodeStr, "ps"), f128mem,
2652 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2653 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2654 (memopv2i64 addr:$src2)))]>, TB;
2656 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2657 !strconcat(OpcodeStr, "pd"), f128mem,
2658 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2659 (bc_v2i64 (v2f64 VR128:$src2))))],
2660 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2661 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2665 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2667 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2669 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2670 !strconcat(OpcodeStr, "ps"), f256mem,
2671 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2672 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2673 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2675 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2676 !strconcat(OpcodeStr, "pd"), f256mem,
2677 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2678 (bc_v4i64 (v4f64 VR256:$src2))))],
2679 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2680 (memopv4i64 addr:$src2)))], 0>,
2684 // AVX 256-bit packed logical ops forms
2685 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2686 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2687 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2688 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2690 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2691 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2692 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2693 let isCommutable = 0 in
2694 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2696 //===----------------------------------------------------------------------===//
2697 // SSE 1 & 2 - Arithmetic Instructions
2698 //===----------------------------------------------------------------------===//
2700 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2703 /// In addition, we also have a special variant of the scalar form here to
2704 /// represent the associated intrinsic operation. This form is unlike the
2705 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2706 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2708 /// These three forms can each be reg+reg or reg+mem.
2711 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2713 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2715 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2716 OpNode, FR32, f32mem, Is2Addr>, XS;
2717 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2718 OpNode, FR64, f64mem, Is2Addr>, XD;
2721 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2723 let mayLoad = 0 in {
2724 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2725 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
2726 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2727 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
2731 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2733 let mayLoad = 0 in {
2734 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2735 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
2736 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2737 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
2741 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2743 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2744 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
2745 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2746 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
2749 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2751 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2752 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2753 SSEPackedSingle, Is2Addr>, TB;
2755 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2756 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2757 SSEPackedDouble, Is2Addr>, TB, OpSize;
2760 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
2761 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2762 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2763 SSEPackedSingle, 0>, TB;
2765 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2766 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2767 SSEPackedDouble, 0>, TB, OpSize;
2770 // Binary Arithmetic instructions
2771 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
2772 basic_sse12_fp_binop_s_int<0x58, "add", 0>, VEX_4V, VEX_LIG;
2773 defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
2774 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
2775 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
2776 basic_sse12_fp_binop_s_int<0x59, "mul", 0>, VEX_4V, VEX_LIG;
2777 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
2778 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
2780 let isCommutable = 0 in {
2781 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
2782 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>, VEX_4V, VEX_LIG;
2783 defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
2784 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
2785 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
2786 basic_sse12_fp_binop_s_int<0x5E, "div", 0>, VEX_4V, VEX_LIG;
2787 defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
2788 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
2789 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
2790 basic_sse12_fp_binop_s_int<0x5F, "max", 0>, VEX_4V, VEX_LIG;
2791 defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
2792 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
2793 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
2794 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
2795 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
2796 basic_sse12_fp_binop_s_int<0x5D, "min", 0>, VEX_4V, VEX_LIG;
2797 defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
2798 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
2799 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
2800 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
2803 let Constraints = "$src1 = $dst" in {
2804 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
2805 basic_sse12_fp_binop_p<0x58, "add", fadd>,
2806 basic_sse12_fp_binop_s_int<0x58, "add">;
2807 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
2808 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
2809 basic_sse12_fp_binop_s_int<0x59, "mul">;
2811 let isCommutable = 0 in {
2812 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
2813 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
2814 basic_sse12_fp_binop_s_int<0x5C, "sub">;
2815 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
2816 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
2817 basic_sse12_fp_binop_s_int<0x5E, "div">;
2818 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
2819 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
2820 basic_sse12_fp_binop_s_int<0x5F, "max">,
2821 basic_sse12_fp_binop_p_int<0x5F, "max">;
2822 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
2823 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
2824 basic_sse12_fp_binop_s_int<0x5D, "min">,
2825 basic_sse12_fp_binop_p_int<0x5D, "min">;
2830 /// In addition, we also have a special variant of the scalar form here to
2831 /// represent the associated intrinsic operation. This form is unlike the
2832 /// plain scalar form, in that it takes an entire vector (instead of a
2833 /// scalar) and leaves the top elements undefined.
2835 /// And, we have a special variant form for a full-vector intrinsic form.
2837 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2838 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2839 SDNode OpNode, Intrinsic F32Int> {
2840 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2841 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2842 [(set FR32:$dst, (OpNode FR32:$src))]>;
2843 // For scalar unary operations, fold a load into the operation
2844 // only in OptForSize mode. It eliminates an instruction, but it also
2845 // eliminates a whole-register clobber (the load), so it introduces a
2846 // partial register update condition.
2847 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
2848 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2849 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
2850 Requires<[HasSSE1, OptForSize]>;
2851 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2852 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2853 [(set VR128:$dst, (F32Int VR128:$src))]>;
2854 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
2855 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2856 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
2859 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
2860 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2861 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
2862 !strconcat(OpcodeStr,
2863 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2865 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
2866 !strconcat(OpcodeStr,
2867 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2868 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
2869 (ins ssmem:$src1, VR128:$src2),
2870 !strconcat(OpcodeStr,
2871 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2874 /// sse1_fp_unop_p - SSE1 unops in packed form.
2875 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2876 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2877 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2878 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
2879 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2880 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2881 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
2884 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
2885 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2886 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2887 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2888 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
2889 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2890 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2891 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
2894 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
2895 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2896 Intrinsic V4F32Int> {
2897 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2898 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2899 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
2900 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2901 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2902 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
2905 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
2906 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2907 Intrinsic V4F32Int> {
2908 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2909 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2910 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
2911 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2912 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2913 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
2916 /// sse2_fp_unop_s - SSE2 unops in scalar form.
2917 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
2918 SDNode OpNode, Intrinsic F64Int> {
2919 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
2920 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2921 [(set FR64:$dst, (OpNode FR64:$src))]>;
2922 // See the comments in sse1_fp_unop_s for why this is OptForSize.
2923 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
2924 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2925 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
2926 Requires<[HasSSE2, OptForSize]>;
2927 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2928 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2929 [(set VR128:$dst, (F64Int VR128:$src))]>;
2930 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
2931 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2932 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
2935 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
2936 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2937 let neverHasSideEffects = 1 in {
2938 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
2939 !strconcat(OpcodeStr,
2940 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2942 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
2943 !strconcat(OpcodeStr,
2944 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2946 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
2947 (ins VR128:$src1, sdmem:$src2),
2948 !strconcat(OpcodeStr,
2949 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2952 /// sse2_fp_unop_p - SSE2 unops in vector forms.
2953 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
2955 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2956 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2957 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
2958 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2959 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2960 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
2963 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
2964 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2965 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2966 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2967 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
2968 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2969 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2970 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
2973 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
2974 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2975 Intrinsic V2F64Int> {
2976 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2977 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2978 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
2979 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2980 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2981 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
2984 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
2985 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2986 Intrinsic V2F64Int> {
2987 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2988 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2989 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
2990 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2991 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2992 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
2995 let Predicates = [HasAVX] in {
2997 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
2998 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
3000 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
3001 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
3002 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
3003 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
3004 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
3005 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
3006 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
3007 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
3010 // Reciprocal approximations. Note that these typically require refinement
3011 // in order to obtain suitable precision.
3012 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
3013 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
3014 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
3015 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
3016 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
3018 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
3019 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
3020 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
3021 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
3022 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
3025 def : Pat<(f32 (fsqrt FR32:$src)),
3026 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3027 def : Pat<(f32 (fsqrt (load addr:$src))),
3028 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3029 Requires<[HasAVX, OptForSize]>;
3030 def : Pat<(f64 (fsqrt FR64:$src)),
3031 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3032 def : Pat<(f64 (fsqrt (load addr:$src))),
3033 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3034 Requires<[HasAVX, OptForSize]>;
3036 def : Pat<(f32 (X86frsqrt FR32:$src)),
3037 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3038 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3039 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3040 Requires<[HasAVX, OptForSize]>;
3042 def : Pat<(f32 (X86frcp FR32:$src)),
3043 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3044 def : Pat<(f32 (X86frcp (load addr:$src))),
3045 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3046 Requires<[HasAVX, OptForSize]>;
3048 let Predicates = [HasAVX] in {
3049 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3050 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3051 (VSQRTSSr (f32 (IMPLICIT_DEF)),
3052 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3054 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3055 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3057 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3058 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
3059 (VSQRTSDr (f64 (IMPLICIT_DEF)),
3060 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
3062 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3063 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3065 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3066 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3067 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3068 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3070 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3071 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3073 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3074 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3075 (VRCPSSr (f32 (IMPLICIT_DEF)),
3076 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3078 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3079 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3083 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
3084 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
3085 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
3086 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
3087 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
3088 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
3090 // Reciprocal approximations. Note that these typically require refinement
3091 // in order to obtain suitable precision.
3092 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
3093 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
3094 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
3095 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
3096 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
3097 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
3099 // There is no f64 version of the reciprocal approximation instructions.
3101 //===----------------------------------------------------------------------===//
3102 // SSE 1 & 2 - Non-temporal stores
3103 //===----------------------------------------------------------------------===//
3105 let AddedComplexity = 400 in { // Prefer non-temporal versions
3106 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3107 (ins f128mem:$dst, VR128:$src),
3108 "movntps\t{$src, $dst|$dst, $src}",
3109 [(alignednontemporalstore (v4f32 VR128:$src),
3111 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3112 (ins f128mem:$dst, VR128:$src),
3113 "movntpd\t{$src, $dst|$dst, $src}",
3114 [(alignednontemporalstore (v2f64 VR128:$src),
3116 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
3117 (ins f128mem:$dst, VR128:$src),
3118 "movntdq\t{$src, $dst|$dst, $src}",
3119 [(alignednontemporalstore (v2f64 VR128:$src),
3122 let ExeDomain = SSEPackedInt in
3123 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3124 (ins f128mem:$dst, VR128:$src),
3125 "movntdq\t{$src, $dst|$dst, $src}",
3126 [(alignednontemporalstore (v4f32 VR128:$src),
3129 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3130 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3132 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3133 (ins f256mem:$dst, VR256:$src),
3134 "movntps\t{$src, $dst|$dst, $src}",
3135 [(alignednontemporalstore (v8f32 VR256:$src),
3137 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3138 (ins f256mem:$dst, VR256:$src),
3139 "movntpd\t{$src, $dst|$dst, $src}",
3140 [(alignednontemporalstore (v4f64 VR256:$src),
3142 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
3143 (ins f256mem:$dst, VR256:$src),
3144 "movntdq\t{$src, $dst|$dst, $src}",
3145 [(alignednontemporalstore (v4f64 VR256:$src),
3147 let ExeDomain = SSEPackedInt in
3148 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3149 (ins f256mem:$dst, VR256:$src),
3150 "movntdq\t{$src, $dst|$dst, $src}",
3151 [(alignednontemporalstore (v8f32 VR256:$src),
3155 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
3156 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3157 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
3158 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
3159 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
3160 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
3162 let AddedComplexity = 400 in { // Prefer non-temporal versions
3163 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3164 "movntps\t{$src, $dst|$dst, $src}",
3165 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
3166 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3167 "movntpd\t{$src, $dst|$dst, $src}",
3168 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
3170 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3171 "movntdq\t{$src, $dst|$dst, $src}",
3172 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
3174 let ExeDomain = SSEPackedInt in
3175 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3176 "movntdq\t{$src, $dst|$dst, $src}",
3177 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
3179 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3180 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3182 // There is no AVX form for instructions below this point
3183 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3184 "movnti{l}\t{$src, $dst|$dst, $src}",
3185 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
3186 TB, Requires<[HasSSE2]>;
3187 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3188 "movnti{q}\t{$src, $dst|$dst, $src}",
3189 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
3190 TB, Requires<[HasSSE2]>;
3193 //===----------------------------------------------------------------------===//
3194 // SSE 1 & 2 - Prefetch and memory fence
3195 //===----------------------------------------------------------------------===//
3197 // Prefetch intrinsic.
3198 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
3199 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
3200 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
3201 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
3202 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
3203 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
3204 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
3205 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
3208 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3209 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3210 TB, Requires<[HasSSE2]>;
3212 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3213 // was introduced with SSE2, it's backward compatible.
3214 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3216 // Load, store, and memory fence
3217 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3218 "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
3219 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3220 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3221 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3222 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3224 def : Pat<(X86SFence), (SFENCE)>;
3225 def : Pat<(X86LFence), (LFENCE)>;
3226 def : Pat<(X86MFence), (MFENCE)>;
3228 //===----------------------------------------------------------------------===//
3229 // SSE 1 & 2 - Load/Store XCSR register
3230 //===----------------------------------------------------------------------===//
3232 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3233 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
3234 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3235 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
3237 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3238 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
3239 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3240 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
3242 //===---------------------------------------------------------------------===//
3243 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3244 //===---------------------------------------------------------------------===//
3246 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3248 let neverHasSideEffects = 1 in {
3249 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3250 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3251 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3252 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3254 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3255 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3256 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3257 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3260 let isCodeGenOnly = 1 in {
3261 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3262 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3263 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3264 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3265 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3266 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3267 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3268 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3271 let canFoldAsLoad = 1, mayLoad = 1 in {
3272 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3273 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3274 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3275 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3276 let Predicates = [HasAVX] in {
3277 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3278 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3279 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3280 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3284 let mayStore = 1 in {
3285 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3286 (ins i128mem:$dst, VR128:$src),
3287 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3288 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3289 (ins i256mem:$dst, VR256:$src),
3290 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3291 let Predicates = [HasAVX] in {
3292 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3293 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3294 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3295 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3299 let neverHasSideEffects = 1 in
3300 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3301 "movdqa\t{$src, $dst|$dst, $src}", []>;
3303 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3304 "movdqu\t{$src, $dst|$dst, $src}",
3305 []>, XS, Requires<[HasSSE2]>;
3308 let isCodeGenOnly = 1 in {
3309 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3310 "movdqa\t{$src, $dst|$dst, $src}", []>;
3312 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3313 "movdqu\t{$src, $dst|$dst, $src}",
3314 []>, XS, Requires<[HasSSE2]>;
3317 let canFoldAsLoad = 1, mayLoad = 1 in {
3318 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3319 "movdqa\t{$src, $dst|$dst, $src}",
3320 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
3321 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3322 "movdqu\t{$src, $dst|$dst, $src}",
3323 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
3324 XS, Requires<[HasSSE2]>;
3327 let mayStore = 1 in {
3328 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3329 "movdqa\t{$src, $dst|$dst, $src}",
3330 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
3331 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3332 "movdqu\t{$src, $dst|$dst, $src}",
3333 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
3334 XS, Requires<[HasSSE2]>;
3337 // Intrinsic forms of MOVDQU load and store
3338 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3339 "vmovdqu\t{$src, $dst|$dst, $src}",
3340 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3341 XS, VEX, Requires<[HasAVX]>;
3343 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3344 "movdqu\t{$src, $dst|$dst, $src}",
3345 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3346 XS, Requires<[HasSSE2]>;
3348 } // ExeDomain = SSEPackedInt
3350 let Predicates = [HasAVX] in {
3351 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
3352 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3353 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3356 //===---------------------------------------------------------------------===//
3357 // SSE2 - Packed Integer Arithmetic Instructions
3358 //===---------------------------------------------------------------------===//
3360 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3362 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3363 RegisterClass RC, PatFrag memop_frag,
3364 X86MemOperand x86memop, bit IsCommutable = 0,
3366 let isCommutable = IsCommutable in
3367 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3368 (ins RC:$src1, RC:$src2),
3370 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3371 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3372 [(set RC:$dst, (IntId RC:$src1, RC:$src2))]>;
3373 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3374 (ins RC:$src1, x86memop:$src2),
3376 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3377 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3378 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))]>;
3381 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
3382 string OpcodeStr, Intrinsic IntId,
3383 Intrinsic IntId2, RegisterClass RC,
3385 // src2 is always 128-bit
3386 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3387 (ins RC:$src1, VR128:$src2),
3389 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3390 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3391 [(set RC:$dst, (IntId RC:$src1, VR128:$src2))]>;
3392 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3393 (ins RC:$src1, i128mem:$src2),
3395 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3396 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3397 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memopv2i64 addr:$src2))))]>;
3398 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3399 (ins RC:$src1, i32i8imm:$src2),
3401 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3402 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3403 [(set RC:$dst, (IntId2 RC:$src1, (i32 imm:$src2)))]>;
3406 /// PDI_binop_rm - Simple SSE2 binary operator.
3407 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3408 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3409 X86MemOperand x86memop, bit IsCommutable = 0,
3411 let isCommutable = IsCommutable in
3412 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3413 (ins RC:$src1, RC:$src2),
3415 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3416 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3417 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
3418 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3419 (ins RC:$src1, x86memop:$src2),
3421 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3422 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3423 [(set RC:$dst, (OpVT (OpNode RC:$src1,
3424 (bitconvert (memop_frag addr:$src2)))))]>;
3427 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
3429 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
3430 /// to collapse (bitconvert VT to VT) into its operand.
3432 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
3433 bit IsCommutable = 0, bit Is2Addr = 1> {
3434 let isCommutable = IsCommutable in
3435 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3436 (ins VR128:$src1, VR128:$src2),
3438 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3439 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3440 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
3441 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3442 (ins VR128:$src1, i128mem:$src2),
3444 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3445 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3446 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
3449 /// PDI_binop_rm_v4i64 - Simple AVX2 binary operator whose type is v4i64.
3451 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
3452 /// to collapse (bitconvert VT to VT) into its operand.
3454 multiclass PDI_binop_rm_v4i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
3455 bit IsCommutable = 0> {
3456 let isCommutable = IsCommutable in
3457 def rr : PDI<opc, MRMSrcReg, (outs VR256:$dst),
3458 (ins VR256:$src1, VR256:$src2),
3459 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3460 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))]>;
3461 def rm : PDI<opc, MRMSrcMem, (outs VR256:$dst),
3462 (ins VR256:$src1, i256mem:$src2),
3463 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3464 [(set VR256:$dst, (OpNode VR256:$src1, (memopv4i64 addr:$src2)))]>;
3467 } // ExeDomain = SSEPackedInt
3469 // 128-bit Integer Arithmetic
3471 let Predicates = [HasAVX] in {
3472 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, VR128, memopv2i64,
3473 i128mem, 1, 0 /*3addr*/>, VEX_4V;
3474 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
3475 i128mem, 1, 0>, VEX_4V;
3476 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
3477 i128mem, 1, 0>, VEX_4V;
3478 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
3479 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
3480 i128mem, 1, 0>, VEX_4V;
3481 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
3482 i128mem, 0, 0>, VEX_4V;
3483 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
3484 i128mem, 0, 0>, VEX_4V;
3485 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
3486 i128mem, 0, 0>, VEX_4V;
3487 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
3490 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
3491 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3492 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w,
3493 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3494 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b,
3495 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3496 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w,
3497 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3498 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b,
3499 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3500 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w,
3501 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3502 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b,
3503 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3504 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w,
3505 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3506 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
3507 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3508 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
3509 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3510 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq,
3511 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3512 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
3513 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3514 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
3515 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3516 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w,
3517 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3518 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b,
3519 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3520 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w,
3521 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3522 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b,
3523 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3524 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w,
3525 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3526 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
3527 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3530 let Predicates = [HasAVX2] in {
3531 defm VPADDBY : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
3532 i256mem, 1, 0>, VEX_4V;
3533 defm VPADDWY : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
3534 i256mem, 1, 0>, VEX_4V;
3535 defm VPADDDY : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
3536 i256mem, 1, 0>, VEX_4V;
3537 defm VPADDQY : PDI_binop_rm_v4i64<0xD4, "vpaddq", add, 1>, VEX_4V;
3538 defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
3539 i256mem, 1, 0>, VEX_4V;
3540 defm VPSUBBY : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
3541 i256mem, 0, 0>, VEX_4V;
3542 defm VPSUBWY : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
3543 i256mem, 0, 0>, VEX_4V;
3544 defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
3545 i256mem, 0, 0>, VEX_4V;
3546 defm VPSUBQY : PDI_binop_rm_v4i64<0xFB, "vpsubq", sub, 0>, VEX_4V;
3549 defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
3550 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3551 defm VPSUBSWY : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_avx2_psubs_w,
3552 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3553 defm VPSUBUSBY : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_avx2_psubus_b,
3554 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3555 defm VPSUBUSWY : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_avx2_psubus_w,
3556 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3557 defm VPADDSBY : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_avx2_padds_b,
3558 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3559 defm VPADDSWY : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_avx2_padds_w,
3560 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3561 defm VPADDUSBY : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_avx2_paddus_b,
3562 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3563 defm VPADDUSWY : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_avx2_paddus_w,
3564 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3565 defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
3566 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3567 defm VPMULHWY : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
3568 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3569 defm VPMULUDQY : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_avx2_pmulu_dq,
3570 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3571 defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
3572 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3573 defm VPAVGBY : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
3574 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3575 defm VPAVGWY : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_avx2_pavg_w,
3576 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3577 defm VPMINUBY : PDI_binop_rm_int<0xDA, "vpminub", int_x86_avx2_pminu_b,
3578 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3579 defm VPMINSWY : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_avx2_pmins_w,
3580 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3581 defm VPMAXUBY : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_avx2_pmaxu_b,
3582 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3583 defm VPMAXSWY : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_avx2_pmaxs_w,
3584 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3585 defm VPSADBWY : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
3586 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3589 let Constraints = "$src1 = $dst" in {
3590 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, VR128, memopv2i64,
3592 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
3594 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
3596 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
3597 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
3599 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
3601 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
3603 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
3605 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
3608 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
3609 VR128, memopv2i64, i128mem>;
3610 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3611 VR128, memopv2i64, i128mem>;
3612 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b,
3613 VR128, memopv2i64, i128mem>;
3614 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w,
3615 VR128, memopv2i64, i128mem>;
3616 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3617 VR128, memopv2i64, i128mem, 1>;
3618 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3619 VR128, memopv2i64, i128mem, 1>;
3620 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3621 VR128, memopv2i64, i128mem, 1>;
3622 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3623 VR128, memopv2i64, i128mem, 1>;
3624 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3625 VR128, memopv2i64, i128mem, 1>;
3626 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3627 VR128, memopv2i64, i128mem, 1>;
3628 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq,
3629 VR128, memopv2i64, i128mem, 1>;
3630 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3631 VR128, memopv2i64, i128mem, 1>;
3632 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3633 VR128, memopv2i64, i128mem, 1>;
3634 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3635 VR128, memopv2i64, i128mem, 1>;
3636 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b,
3637 VR128, memopv2i64, i128mem, 1>;
3638 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w,
3639 VR128, memopv2i64, i128mem, 1>;
3640 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b,
3641 VR128, memopv2i64, i128mem, 1>;
3642 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w,
3643 VR128, memopv2i64, i128mem, 1>;
3644 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3645 VR128, memopv2i64, i128mem, 1>;
3647 } // Constraints = "$src1 = $dst"
3649 //===---------------------------------------------------------------------===//
3650 // SSE2 - Packed Integer Logical Instructions
3651 //===---------------------------------------------------------------------===//
3653 let Predicates = [HasAVX] in {
3654 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
3655 int_x86_sse2_psll_w, int_x86_sse2_pslli_w,
3657 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
3658 int_x86_sse2_psll_d, int_x86_sse2_pslli_d,
3660 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
3661 int_x86_sse2_psll_q, int_x86_sse2_pslli_q,
3664 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
3665 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w,
3667 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
3668 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d,
3670 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
3671 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q,
3674 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
3675 int_x86_sse2_psra_w, int_x86_sse2_psrai_w,
3677 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
3678 int_x86_sse2_psra_d, int_x86_sse2_psrai_d,
3681 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
3682 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
3683 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
3685 let ExeDomain = SSEPackedInt in {
3686 let neverHasSideEffects = 1 in {
3687 // 128-bit logical shifts.
3688 def VPSLLDQri : PDIi8<0x73, MRM7r,
3689 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3690 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3692 def VPSRLDQri : PDIi8<0x73, MRM3r,
3693 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3694 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3696 // PSRADQri doesn't exist in SSE[1-3].
3698 def VPANDNrr : PDI<0xDF, MRMSrcReg,
3699 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3700 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3702 (v2i64 (X86andnp VR128:$src1, VR128:$src2)))]>,VEX_4V;
3704 def VPANDNrm : PDI<0xDF, MRMSrcMem,
3705 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3706 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3707 [(set VR128:$dst, (X86andnp VR128:$src1,
3708 (memopv2i64 addr:$src2)))]>, VEX_4V;
3712 let Predicates = [HasAVX2] in {
3713 defm VPSLLWY : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
3714 int_x86_avx2_psll_w, int_x86_avx2_pslli_w,
3716 defm VPSLLDY : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
3717 int_x86_avx2_psll_d, int_x86_avx2_pslli_d,
3719 defm VPSLLQY : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
3720 int_x86_avx2_psll_q, int_x86_avx2_pslli_q,
3723 defm VPSRLWY : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
3724 int_x86_avx2_psrl_w, int_x86_avx2_psrli_w,
3726 defm VPSRLDY : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
3727 int_x86_avx2_psrl_d, int_x86_avx2_psrli_d,
3729 defm VPSRLQY : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
3730 int_x86_avx2_psrl_q, int_x86_avx2_psrli_q,
3733 defm VPSRAWY : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
3734 int_x86_avx2_psra_w, int_x86_avx2_psrai_w,
3736 defm VPSRADY : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
3737 int_x86_avx2_psra_d, int_x86_avx2_psrai_d,
3740 defm VPANDY : PDI_binop_rm_v4i64<0xDB, "vpand", and, 1>, VEX_4V;
3741 defm VPORY : PDI_binop_rm_v4i64<0xEB, "vpor" , or, 1>, VEX_4V;
3742 defm VPXORY : PDI_binop_rm_v4i64<0xEF, "vpxor", xor, 1>, VEX_4V;
3744 let ExeDomain = SSEPackedInt in {
3745 let neverHasSideEffects = 1 in {
3746 // 128-bit logical shifts.
3747 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3748 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3749 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3751 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3752 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3753 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3755 // PSRADQYri doesn't exist in SSE[1-3].
3757 def VPANDNYrr : PDI<0xDF, MRMSrcReg,
3758 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
3759 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3761 (v4i64 (X86andnp VR256:$src1, VR256:$src2)))]>,VEX_4V;
3763 def VPANDNYrm : PDI<0xDF, MRMSrcMem,
3764 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
3765 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3766 [(set VR256:$dst, (X86andnp VR256:$src1,
3767 (memopv4i64 addr:$src2)))]>, VEX_4V;
3771 let Constraints = "$src1 = $dst" in {
3772 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
3773 int_x86_sse2_psll_w, int_x86_sse2_pslli_w,
3775 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
3776 int_x86_sse2_psll_d, int_x86_sse2_pslli_d,
3778 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
3779 int_x86_sse2_psll_q, int_x86_sse2_pslli_q,
3782 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
3783 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w,
3785 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
3786 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d,
3788 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
3789 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q,
3792 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
3793 int_x86_sse2_psra_w, int_x86_sse2_psrai_w,
3795 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
3796 int_x86_sse2_psra_d, int_x86_sse2_psrai_d,
3799 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
3800 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
3801 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
3803 let ExeDomain = SSEPackedInt in {
3804 let neverHasSideEffects = 1 in {
3805 // 128-bit logical shifts.
3806 def PSLLDQri : PDIi8<0x73, MRM7r,
3807 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3808 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
3809 def PSRLDQri : PDIi8<0x73, MRM3r,
3810 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3811 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
3812 // PSRADQri doesn't exist in SSE[1-3].
3813 def PANDNrr : PDI<0xDF, MRMSrcReg,
3814 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3815 "pandn\t{$src2, $dst|$dst, $src2}", []>;
3818 def PANDNrm : PDI<0xDF, MRMSrcMem,
3819 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3820 "pandn\t{$src2, $dst|$dst, $src2}", []>;
3823 } // Constraints = "$src1 = $dst"
3825 let Predicates = [HasAVX] in {
3826 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3827 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3828 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3829 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3830 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3831 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
3832 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3833 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
3834 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3835 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3837 // Shift up / down and insert zero's.
3838 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3839 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3840 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3841 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3844 let Predicates = [HasAVX2] in {
3845 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
3846 (v4i64 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2)))>;
3847 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
3848 (v4i64 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2)))>;
3849 def : Pat<(int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2),
3850 (v4i64 (VPSLLDQYri VR256:$src1, imm:$src2))>;
3851 def : Pat<(int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2),
3852 (v4i64 (VPSRLDQYri VR256:$src1, imm:$src2))>;
3855 let Predicates = [HasSSE2] in {
3856 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3857 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3858 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3859 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3860 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3861 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
3862 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3863 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
3864 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3865 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3867 // Shift up / down and insert zero's.
3868 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3869 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3870 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3871 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3874 //===---------------------------------------------------------------------===//
3875 // SSE2 - Packed Integer Comparison Instructions
3876 //===---------------------------------------------------------------------===//
3878 let Predicates = [HasAVX] in {
3879 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b,
3880 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3881 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w,
3882 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3883 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d,
3884 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3885 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b,
3886 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3887 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w,
3888 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3889 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d,
3890 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3892 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3893 (VPCMPEQBrr VR128:$src1, VR128:$src2)>;
3894 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1,
3895 (bc_v16i8 (memopv2i64 addr:$src2)))),
3896 (VPCMPEQBrm VR128:$src1, addr:$src2)>;
3897 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3898 (VPCMPEQWrr VR128:$src1, VR128:$src2)>;
3899 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1,
3900 (bc_v8i16 (memopv2i64 addr:$src2)))),
3901 (VPCMPEQWrm VR128:$src1, addr:$src2)>;
3902 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3903 (VPCMPEQDrr VR128:$src1, VR128:$src2)>;
3904 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1,
3905 (bc_v4i32 (memopv2i64 addr:$src2)))),
3906 (VPCMPEQDrm VR128:$src1, addr:$src2)>;
3908 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3909 (VPCMPGTBrr VR128:$src1, VR128:$src2)>;
3910 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1,
3911 (bc_v16i8 (memopv2i64 addr:$src2)))),
3912 (VPCMPGTBrm VR128:$src1, addr:$src2)>;
3913 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3914 (VPCMPGTWrr VR128:$src1, VR128:$src2)>;
3915 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1,
3916 (bc_v8i16 (memopv2i64 addr:$src2)))),
3917 (VPCMPGTWrm VR128:$src1, addr:$src2)>;
3918 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3919 (VPCMPGTDrr VR128:$src1, VR128:$src2)>;
3920 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1,
3921 (bc_v4i32 (memopv2i64 addr:$src2)))),
3922 (VPCMPGTDrm VR128:$src1, addr:$src2)>;
3925 let Predicates = [HasAVX2] in {
3926 defm VPCMPEQBY : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_avx2_pcmpeq_b,
3927 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3928 defm VPCMPEQWY : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_avx2_pcmpeq_w,
3929 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3930 defm VPCMPEQDY : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_avx2_pcmpeq_d,
3931 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3932 defm VPCMPGTBY : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_avx2_pcmpgt_b,
3933 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3934 defm VPCMPGTWY : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_avx2_pcmpgt_w,
3935 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3936 defm VPCMPGTDY : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_avx2_pcmpgt_d,
3937 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3939 def : Pat<(v32i8 (X86pcmpeqb VR256:$src1, VR256:$src2)),
3940 (VPCMPEQBYrr VR256:$src1, VR256:$src2)>;
3941 def : Pat<(v32i8 (X86pcmpeqb VR256:$src1,
3942 (bc_v32i8 (memopv4i64 addr:$src2)))),
3943 (VPCMPEQBYrm VR256:$src1, addr:$src2)>;
3944 def : Pat<(v16i16 (X86pcmpeqw VR256:$src1, VR256:$src2)),
3945 (VPCMPEQWYrr VR256:$src1, VR256:$src2)>;
3946 def : Pat<(v16i16 (X86pcmpeqw VR256:$src1,
3947 (bc_v16i16 (memopv4i64 addr:$src2)))),
3948 (VPCMPEQWYrm VR256:$src1, addr:$src2)>;
3949 def : Pat<(v8i32 (X86pcmpeqd VR256:$src1, VR256:$src2)),
3950 (VPCMPEQDYrr VR256:$src1, VR256:$src2)>;
3951 def : Pat<(v8i32 (X86pcmpeqd VR256:$src1,
3952 (bc_v8i32 (memopv4i64 addr:$src2)))),
3953 (VPCMPEQDYrm VR256:$src1, addr:$src2)>;
3955 def : Pat<(v32i8 (X86pcmpgtb VR256:$src1, VR256:$src2)),
3956 (VPCMPGTBYrr VR256:$src1, VR256:$src2)>;
3957 def : Pat<(v32i8 (X86pcmpgtb VR256:$src1,
3958 (bc_v32i8 (memopv4i64 addr:$src2)))),
3959 (VPCMPGTBYrm VR256:$src1, addr:$src2)>;
3960 def : Pat<(v16i16 (X86pcmpgtw VR256:$src1, VR256:$src2)),
3961 (VPCMPGTWYrr VR256:$src1, VR256:$src2)>;
3962 def : Pat<(v16i16 (X86pcmpgtw VR256:$src1,
3963 (bc_v16i16 (memopv4i64 addr:$src2)))),
3964 (VPCMPGTWYrm VR256:$src1, addr:$src2)>;
3965 def : Pat<(v8i32 (X86pcmpgtd VR256:$src1, VR256:$src2)),
3966 (VPCMPGTDYrr VR256:$src1, VR256:$src2)>;
3967 def : Pat<(v8i32 (X86pcmpgtd VR256:$src1,
3968 (bc_v8i32 (memopv4i64 addr:$src2)))),
3969 (VPCMPGTDYrm VR256:$src1, addr:$src2)>;
3972 let Constraints = "$src1 = $dst" in {
3973 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b,
3974 VR128, memopv2i64, i128mem, 1>;
3975 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w,
3976 VR128, memopv2i64, i128mem, 1>;
3977 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d,
3978 VR128, memopv2i64, i128mem, 1>;
3979 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b,
3980 VR128, memopv2i64, i128mem>;
3981 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w,
3982 VR128, memopv2i64, i128mem>;
3983 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d,
3984 VR128, memopv2i64, i128mem>;
3985 } // Constraints = "$src1 = $dst"
3987 let Predicates = [HasSSE2] in {
3988 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3989 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
3990 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1,
3991 (bc_v16i8 (memopv2i64 addr:$src2)))),
3992 (PCMPEQBrm VR128:$src1, addr:$src2)>;
3993 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3994 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
3995 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1,
3996 (bc_v8i16 (memopv2i64 addr:$src2)))),
3997 (PCMPEQWrm VR128:$src1, addr:$src2)>;
3998 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3999 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
4000 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1,
4001 (bc_v4i32 (memopv2i64 addr:$src2)))),
4002 (PCMPEQDrm VR128:$src1, addr:$src2)>;
4004 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
4005 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
4006 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1,
4007 (bc_v16i8 (memopv2i64 addr:$src2)))),
4008 (PCMPGTBrm VR128:$src1, addr:$src2)>;
4009 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
4010 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
4011 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1,
4012 (bc_v8i16 (memopv2i64 addr:$src2)))),
4013 (PCMPGTWrm VR128:$src1, addr:$src2)>;
4014 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
4015 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
4016 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1,
4017 (bc_v4i32 (memopv2i64 addr:$src2)))),
4018 (PCMPGTDrm VR128:$src1, addr:$src2)>;
4021 //===---------------------------------------------------------------------===//
4022 // SSE2 - Packed Integer Pack Instructions
4023 //===---------------------------------------------------------------------===//
4025 let Predicates = [HasAVX] in {
4026 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
4027 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
4028 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
4029 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
4030 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
4031 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
4034 let Predicates = [HasAVX2] in {
4035 defm VPACKSSWBY : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_avx2_packsswb,
4036 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
4037 defm VPACKSSDWY : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_avx2_packssdw,
4038 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
4039 defm VPACKUSWBY : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_avx2_packuswb,
4040 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
4043 let Constraints = "$src1 = $dst" in {
4044 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4045 VR128, memopv2i64, i128mem>;
4046 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4047 VR128, memopv2i64, i128mem>;
4048 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4049 VR128, memopv2i64, i128mem>;
4050 } // Constraints = "$src1 = $dst"
4052 //===---------------------------------------------------------------------===//
4053 // SSE2 - Packed Integer Shuffle Instructions
4054 //===---------------------------------------------------------------------===//
4056 let ExeDomain = SSEPackedInt in {
4057 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
4059 def ri : Ii8<0x70, MRMSrcReg,
4060 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4061 !strconcat(OpcodeStr,
4062 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4063 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
4065 def mi : Ii8<0x70, MRMSrcMem,
4066 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4067 !strconcat(OpcodeStr,
4068 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4069 [(set VR128:$dst, (vt (pshuf_frag:$src2
4070 (bc_frag (memopv2i64 addr:$src1)),
4074 multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
4076 def Yri : Ii8<0x70, MRMSrcReg,
4077 (outs VR256:$dst), (ins VR256:$src1, i8imm:$src2),
4078 !strconcat(OpcodeStr,
4079 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4080 [(set VR256:$dst, (vt (pshuf_frag:$src2 VR256:$src1,
4082 def Ymi : Ii8<0x70, MRMSrcMem,
4083 (outs VR256:$dst), (ins i256mem:$src1, i8imm:$src2),
4084 !strconcat(OpcodeStr,
4085 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4086 [(set VR256:$dst, (vt (pshuf_frag:$src2
4087 (bc_frag (memopv4i64 addr:$src1)),
4090 } // ExeDomain = SSEPackedInt
4092 let Predicates = [HasAVX] in {
4093 let AddedComplexity = 5 in
4094 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize,
4097 // SSE2 with ImmT == Imm8 and XS prefix.
4098 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
4101 // SSE2 with ImmT == Imm8 and XD prefix.
4102 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
4105 let AddedComplexity = 5 in
4106 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
4107 (VPSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
4108 // Unary v4f32 shuffle with VPSHUF* in order to fold a load.
4109 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
4110 (VPSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
4112 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
4114 (VPSHUFDmi addr:$src1, imm:$imm)>;
4115 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
4117 (VPSHUFDmi addr:$src1, imm:$imm)>;
4118 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4119 (VPSHUFDri VR128:$src1, imm:$imm)>;
4120 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4121 (VPSHUFDri VR128:$src1, imm:$imm)>;
4122 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
4123 (VPSHUFHWri VR128:$src, imm:$imm)>;
4124 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
4126 (VPSHUFHWmi addr:$src, imm:$imm)>;
4127 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
4128 (VPSHUFLWri VR128:$src, imm:$imm)>;
4129 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
4131 (VPSHUFLWmi addr:$src, imm:$imm)>;
4134 let Predicates = [HasAVX2] in {
4135 let AddedComplexity = 5 in
4136 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, pshufd, bc_v8i32>, TB,
4139 // SSE2 with ImmT == Imm8 and XS prefix.
4140 defm VPSHUFHW : sse2_pshuffle_y<"vpshufhw", v16i16, pshufhw, bc_v16i16>, XS,
4143 // SSE2 with ImmT == Imm8 and XD prefix.
4144 defm VPSHUFLW : sse2_pshuffle_y<"vpshuflw", v16i16, pshuflw, bc_v16i16>, XD,
4148 let Predicates = [HasSSE2] in {
4149 let AddedComplexity = 5 in
4150 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
4152 // SSE2 with ImmT == Imm8 and XS prefix.
4153 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
4155 // SSE2 with ImmT == Imm8 and XD prefix.
4156 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
4158 let AddedComplexity = 5 in
4159 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
4160 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
4161 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
4162 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
4163 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
4165 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
4167 (PSHUFDmi addr:$src1, imm:$imm)>;
4168 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
4170 (PSHUFDmi addr:$src1, imm:$imm)>;
4171 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4172 (PSHUFDri VR128:$src1, imm:$imm)>;
4173 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4174 (PSHUFDri VR128:$src1, imm:$imm)>;
4175 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
4176 (PSHUFHWri VR128:$src, imm:$imm)>;
4177 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
4179 (PSHUFHWmi addr:$src, imm:$imm)>;
4180 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
4181 (PSHUFLWri VR128:$src, imm:$imm)>;
4182 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
4184 (PSHUFLWmi addr:$src, imm:$imm)>;
4187 //===---------------------------------------------------------------------===//
4188 // SSE2 - Packed Integer Unpack Instructions
4189 //===---------------------------------------------------------------------===//
4191 let ExeDomain = SSEPackedInt in {
4192 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4193 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4194 def rr : PDI<opc, MRMSrcReg,
4195 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4197 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4198 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4199 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))]>;
4200 def rm : PDI<opc, MRMSrcMem,
4201 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4203 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4204 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4205 [(set VR128:$dst, (OpNode VR128:$src1,
4206 (bc_frag (memopv2i64
4210 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4211 SDNode OpNode, PatFrag bc_frag> {
4212 def Yrr : PDI<opc, MRMSrcReg,
4213 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4214 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4215 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
4216 def Yrm : PDI<opc, MRMSrcMem,
4217 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4218 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4219 [(set VR256:$dst, (OpNode VR256:$src1,
4220 (bc_frag (memopv4i64 addr:$src2))))]>;
4223 let Predicates = [HasAVX] in {
4224 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Punpcklbw,
4225 bc_v16i8, 0>, VEX_4V;
4226 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Punpcklwd,
4227 bc_v8i16, 0>, VEX_4V;
4228 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Punpckldq,
4229 bc_v4i32, 0>, VEX_4V;
4231 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
4232 /// knew to collapse (bitconvert VT to VT) into its operand.
4233 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
4234 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4235 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4236 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
4237 VR128:$src2)))]>, VEX_4V;
4238 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
4239 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4240 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4241 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
4242 (memopv2i64 addr:$src2))))]>, VEX_4V;
4244 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Punpckhbw,
4245 bc_v16i8, 0>, VEX_4V;
4246 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Punpckhwd,
4247 bc_v8i16, 0>, VEX_4V;
4248 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Punpckhdq,
4249 bc_v4i32, 0>, VEX_4V;
4251 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
4252 /// knew to collapse (bitconvert VT to VT) into its operand.
4253 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
4254 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4255 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4256 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
4257 VR128:$src2)))]>, VEX_4V;
4258 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
4259 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4260 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4261 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
4262 (memopv2i64 addr:$src2))))]>, VEX_4V;
4265 let Predicates = [HasAVX2] in {
4266 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Punpcklbw,
4268 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Punpcklwd,
4270 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Punpckldq,
4273 /// FIXME: we could eliminate this and use sse2_unpack_y instead if tblgen
4274 /// knew to collapse (bitconvert VT to VT) into its operand.
4275 def VPUNPCKLQDQYrr : PDI<0x6C, MRMSrcReg,
4276 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4277 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4278 [(set VR256:$dst, (v4i64 (X86Punpcklqdq VR256:$src1,
4279 VR256:$src2)))]>, VEX_4V;
4280 def VPUNPCKLQDQYrm : PDI<0x6C, MRMSrcMem,
4281 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4282 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4283 [(set VR256:$dst, (v4i64 (X86Punpcklqdq VR256:$src1,
4284 (memopv4i64 addr:$src2))))]>, VEX_4V;
4286 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Punpckhbw,
4288 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Punpckhwd,
4290 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Punpckhdq,
4293 /// FIXME: we could eliminate this and use sse2_unpack_y instead if tblgen
4294 /// knew to collapse (bitconvert VT to VT) into its operand.
4295 def VPUNPCKHQDQYrr : PDI<0x6D, MRMSrcReg,
4296 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4297 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4298 [(set VR256:$dst, (v4i64 (X86Punpckhqdq VR256:$src1,
4299 VR256:$src2)))]>, VEX_4V;
4300 def VPUNPCKHQDQYrm : PDI<0x6D, MRMSrcMem,
4301 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4302 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4303 [(set VR256:$dst, (v4i64 (X86Punpckhqdq VR256:$src1,
4304 (memopv4i64 addr:$src2))))]>, VEX_4V;
4307 let Constraints = "$src1 = $dst" in {
4308 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Punpcklbw, bc_v16i8>;
4309 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Punpcklwd, bc_v8i16>;
4310 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Punpckldq, bc_v4i32>;
4312 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
4313 /// knew to collapse (bitconvert VT to VT) into its operand.
4314 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
4315 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4316 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
4318 (v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)))]>;
4319 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
4320 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4321 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
4323 (v2i64 (X86Punpcklqdq VR128:$src1,
4324 (memopv2i64 addr:$src2))))]>;
4326 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Punpckhbw, bc_v16i8>;
4327 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Punpckhwd, bc_v8i16>;
4328 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Punpckhdq, bc_v4i32>;
4330 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
4331 /// knew to collapse (bitconvert VT to VT) into its operand.
4332 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
4333 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4334 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
4336 (v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)))]>;
4337 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
4338 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4339 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
4341 (v2i64 (X86Punpckhqdq VR128:$src1,
4342 (memopv2i64 addr:$src2))))]>;
4344 } // ExeDomain = SSEPackedInt
4346 // Splat v2f64 / v2i64
4347 let AddedComplexity = 10 in {
4348 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
4349 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
4350 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
4351 (VPUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasAVX]>;
4354 //===---------------------------------------------------------------------===//
4355 // SSE2 - Packed Integer Extract and Insert
4356 //===---------------------------------------------------------------------===//
4358 let ExeDomain = SSEPackedInt in {
4359 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4360 def rri : Ii8<0xC4, MRMSrcReg,
4361 (outs VR128:$dst), (ins VR128:$src1,
4362 GR32:$src2, i32i8imm:$src3),
4364 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4365 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4367 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
4368 def rmi : Ii8<0xC4, MRMSrcMem,
4369 (outs VR128:$dst), (ins VR128:$src1,
4370 i16mem:$src2, i32i8imm:$src3),
4372 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4373 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4375 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4380 let Predicates = [HasAVX] in
4381 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4382 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4383 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4384 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4385 imm:$src2))]>, TB, OpSize, VEX;
4386 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4387 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4388 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4389 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4393 let Predicates = [HasAVX] in {
4394 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4395 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4396 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4397 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4398 []>, TB, OpSize, VEX_4V;
4401 let Constraints = "$src1 = $dst" in
4402 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
4404 } // ExeDomain = SSEPackedInt
4406 //===---------------------------------------------------------------------===//
4407 // SSE2 - Packed Mask Creation
4408 //===---------------------------------------------------------------------===//
4410 let ExeDomain = SSEPackedInt in {
4412 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4413 "pmovmskb\t{$src, $dst|$dst, $src}",
4414 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
4415 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4416 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4418 let Predicates = [HasAVX2] in {
4419 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4420 "pmovmskb\t{$src, $dst|$dst, $src}",
4421 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX;
4422 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4423 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4426 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4427 "pmovmskb\t{$src, $dst|$dst, $src}",
4428 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
4430 } // ExeDomain = SSEPackedInt
4432 //===---------------------------------------------------------------------===//
4433 // SSE2 - Conditional Store
4434 //===---------------------------------------------------------------------===//
4436 let ExeDomain = SSEPackedInt in {
4439 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4440 (ins VR128:$src, VR128:$mask),
4441 "maskmovdqu\t{$mask, $src|$src, $mask}",
4442 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
4444 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4445 (ins VR128:$src, VR128:$mask),
4446 "maskmovdqu\t{$mask, $src|$src, $mask}",
4447 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
4450 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4451 "maskmovdqu\t{$mask, $src|$src, $mask}",
4452 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
4454 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4455 "maskmovdqu\t{$mask, $src|$src, $mask}",
4456 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
4458 } // ExeDomain = SSEPackedInt
4460 //===---------------------------------------------------------------------===//
4461 // SSE2 - Move Doubleword
4462 //===---------------------------------------------------------------------===//
4464 //===---------------------------------------------------------------------===//
4465 // Move Int Doubleword to Packed Double Int
4467 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4468 "movd\t{$src, $dst|$dst, $src}",
4470 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
4471 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4472 "movd\t{$src, $dst|$dst, $src}",
4474 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
4476 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4477 "mov{d|q}\t{$src, $dst|$dst, $src}",
4479 (v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
4480 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4481 "mov{d|q}\t{$src, $dst|$dst, $src}",
4482 [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
4484 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4485 "movd\t{$src, $dst|$dst, $src}",
4487 (v4i32 (scalar_to_vector GR32:$src)))]>;
4488 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4489 "movd\t{$src, $dst|$dst, $src}",
4491 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
4492 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4493 "mov{d|q}\t{$src, $dst|$dst, $src}",
4495 (v2i64 (scalar_to_vector GR64:$src)))]>;
4496 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4497 "mov{d|q}\t{$src, $dst|$dst, $src}",
4498 [(set FR64:$dst, (bitconvert GR64:$src))]>;
4500 //===---------------------------------------------------------------------===//
4501 // Move Int Doubleword to Single Scalar
4503 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4504 "movd\t{$src, $dst|$dst, $src}",
4505 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
4507 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4508 "movd\t{$src, $dst|$dst, $src}",
4509 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
4511 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4512 "movd\t{$src, $dst|$dst, $src}",
4513 [(set FR32:$dst, (bitconvert GR32:$src))]>;
4515 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4516 "movd\t{$src, $dst|$dst, $src}",
4517 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
4519 //===---------------------------------------------------------------------===//
4520 // Move Packed Doubleword Int to Packed Double Int
4522 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4523 "movd\t{$src, $dst|$dst, $src}",
4524 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4526 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4527 (ins i32mem:$dst, VR128:$src),
4528 "movd\t{$src, $dst|$dst, $src}",
4529 [(store (i32 (vector_extract (v4i32 VR128:$src),
4530 (iPTR 0))), addr:$dst)]>, VEX;
4531 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4532 "movd\t{$src, $dst|$dst, $src}",
4533 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4535 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4536 "movd\t{$src, $dst|$dst, $src}",
4537 [(store (i32 (vector_extract (v4i32 VR128:$src),
4538 (iPTR 0))), addr:$dst)]>;
4540 //===---------------------------------------------------------------------===//
4541 // Move Packed Doubleword Int first element to Doubleword Int
4543 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4544 "mov{d|q}\t{$src, $dst|$dst, $src}",
4545 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4547 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4549 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4550 "mov{d|q}\t{$src, $dst|$dst, $src}",
4551 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4554 //===---------------------------------------------------------------------===//
4555 // Bitcast FR64 <-> GR64
4557 let Predicates = [HasAVX] in
4558 def VMOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4559 "vmovq\t{$src, $dst|$dst, $src}",
4560 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4562 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4563 "mov{d|q}\t{$src, $dst|$dst, $src}",
4564 [(set GR64:$dst, (bitconvert FR64:$src))]>;
4565 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4566 "movq\t{$src, $dst|$dst, $src}",
4567 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
4569 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4570 "movq\t{$src, $dst|$dst, $src}",
4571 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
4572 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4573 "mov{d|q}\t{$src, $dst|$dst, $src}",
4574 [(set GR64:$dst, (bitconvert FR64:$src))]>;
4575 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4576 "movq\t{$src, $dst|$dst, $src}",
4577 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
4579 //===---------------------------------------------------------------------===//
4580 // Move Scalar Single to Double Int
4582 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4583 "movd\t{$src, $dst|$dst, $src}",
4584 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
4585 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4586 "movd\t{$src, $dst|$dst, $src}",
4587 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
4588 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4589 "movd\t{$src, $dst|$dst, $src}",
4590 [(set GR32:$dst, (bitconvert FR32:$src))]>;
4591 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4592 "movd\t{$src, $dst|$dst, $src}",
4593 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
4595 //===---------------------------------------------------------------------===//
4596 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4598 let AddedComplexity = 15 in {
4599 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4600 "movd\t{$src, $dst|$dst, $src}",
4601 [(set VR128:$dst, (v4i32 (X86vzmovl
4602 (v4i32 (scalar_to_vector GR32:$src)))))]>,
4604 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4605 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4606 [(set VR128:$dst, (v2i64 (X86vzmovl
4607 (v2i64 (scalar_to_vector GR64:$src)))))]>,
4610 let AddedComplexity = 15 in {
4611 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4612 "movd\t{$src, $dst|$dst, $src}",
4613 [(set VR128:$dst, (v4i32 (X86vzmovl
4614 (v4i32 (scalar_to_vector GR32:$src)))))]>;
4615 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4616 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4617 [(set VR128:$dst, (v2i64 (X86vzmovl
4618 (v2i64 (scalar_to_vector GR64:$src)))))]>;
4621 let AddedComplexity = 20 in {
4622 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4623 "movd\t{$src, $dst|$dst, $src}",
4625 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4626 (loadi32 addr:$src))))))]>,
4628 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4629 "movd\t{$src, $dst|$dst, $src}",
4631 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4632 (loadi32 addr:$src))))))]>;
4635 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4636 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
4637 (MOVZDI2PDIrm addr:$src)>;
4638 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4639 (MOVZDI2PDIrm addr:$src)>;
4640 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4641 (MOVZDI2PDIrm addr:$src)>;
4644 let Predicates = [HasAVX] in {
4645 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4646 let AddedComplexity = 20 in {
4647 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
4648 (VMOVZDI2PDIrm addr:$src)>;
4649 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4650 (VMOVZDI2PDIrm addr:$src)>;
4651 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4652 (VMOVZDI2PDIrm addr:$src)>;
4654 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4655 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4656 (v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
4657 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4658 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4659 (v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
4660 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4663 // These are the correct encodings of the instructions so that we know how to
4664 // read correct assembly, even though we continue to emit the wrong ones for
4665 // compatibility with Darwin's buggy assembler.
4666 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4667 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4668 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4669 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4670 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4671 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4672 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4673 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4674 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4675 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4676 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4677 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4679 //===---------------------------------------------------------------------===//
4680 // SSE2 - Move Quadword
4681 //===---------------------------------------------------------------------===//
4683 //===---------------------------------------------------------------------===//
4684 // Move Quadword Int to Packed Quadword Int
4686 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4687 "vmovq\t{$src, $dst|$dst, $src}",
4689 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4690 VEX, Requires<[HasAVX]>;
4691 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4692 "movq\t{$src, $dst|$dst, $src}",
4694 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4695 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
4697 //===---------------------------------------------------------------------===//
4698 // Move Packed Quadword Int to Quadword Int
4700 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4701 "movq\t{$src, $dst|$dst, $src}",
4702 [(store (i64 (vector_extract (v2i64 VR128:$src),
4703 (iPTR 0))), addr:$dst)]>, VEX;
4704 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4705 "movq\t{$src, $dst|$dst, $src}",
4706 [(store (i64 (vector_extract (v2i64 VR128:$src),
4707 (iPTR 0))), addr:$dst)]>;
4709 //===---------------------------------------------------------------------===//
4710 // Store / copy lower 64-bits of a XMM register.
4712 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4713 "movq\t{$src, $dst|$dst, $src}",
4714 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4715 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4716 "movq\t{$src, $dst|$dst, $src}",
4717 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
4719 let AddedComplexity = 20 in
4720 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4721 "vmovq\t{$src, $dst|$dst, $src}",
4723 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4724 (loadi64 addr:$src))))))]>,
4725 XS, VEX, Requires<[HasAVX]>;
4727 let AddedComplexity = 20 in
4728 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4729 "movq\t{$src, $dst|$dst, $src}",
4731 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4732 (loadi64 addr:$src))))))]>,
4733 XS, Requires<[HasSSE2]>;
4735 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4736 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4737 (MOVZQI2PQIrm addr:$src)>;
4738 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4739 (MOVZQI2PQIrm addr:$src)>;
4740 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4743 let Predicates = [HasAVX], AddedComplexity = 20 in {
4744 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4745 (VMOVZQI2PQIrm addr:$src)>;
4746 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4747 (VMOVZQI2PQIrm addr:$src)>;
4748 def : Pat<(v2i64 (X86vzload addr:$src)),
4749 (VMOVZQI2PQIrm addr:$src)>;
4752 //===---------------------------------------------------------------------===//
4753 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4754 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4756 let AddedComplexity = 15 in
4757 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4758 "vmovq\t{$src, $dst|$dst, $src}",
4759 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4760 XS, VEX, Requires<[HasAVX]>;
4761 let AddedComplexity = 15 in
4762 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4763 "movq\t{$src, $dst|$dst, $src}",
4764 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4765 XS, Requires<[HasSSE2]>;
4767 let AddedComplexity = 20 in
4768 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4769 "vmovq\t{$src, $dst|$dst, $src}",
4770 [(set VR128:$dst, (v2i64 (X86vzmovl
4771 (loadv2i64 addr:$src))))]>,
4772 XS, VEX, Requires<[HasAVX]>;
4773 let AddedComplexity = 20 in {
4774 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4775 "movq\t{$src, $dst|$dst, $src}",
4776 [(set VR128:$dst, (v2i64 (X86vzmovl
4777 (loadv2i64 addr:$src))))]>,
4778 XS, Requires<[HasSSE2]>;
4781 let AddedComplexity = 20 in {
4782 let Predicates = [HasSSE2] in {
4783 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
4784 (MOVZPQILo2PQIrm addr:$src)>;
4785 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4786 (MOVZPQILo2PQIrr VR128:$src)>;
4788 let Predicates = [HasAVX] in {
4789 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
4790 (VMOVZPQILo2PQIrm addr:$src)>;
4791 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4792 (VMOVZPQILo2PQIrr VR128:$src)>;
4796 // Instructions to match in the assembler
4797 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4798 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4799 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4800 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4801 // Recognize "movd" with GR64 destination, but encode as a "movq"
4802 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4803 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4805 // Instructions for the disassembler
4806 // xr = XMM register
4809 let Predicates = [HasAVX] in
4810 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4811 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4812 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4813 "movq\t{$src, $dst|$dst, $src}", []>, XS;
4815 //===---------------------------------------------------------------------===//
4816 // SSE3 - Conversion Instructions
4817 //===---------------------------------------------------------------------===//
4819 // Convert Packed Double FP to Packed DW Integers
4820 let Predicates = [HasAVX] in {
4821 // The assembler can recognize rr 256-bit instructions by seeing a ymm
4822 // register, but the same isn't true when using memory operands instead.
4823 // Provide other assembly rr and rm forms to address this explicitly.
4824 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4825 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4826 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4827 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4830 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4831 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4832 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4833 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4836 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4837 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
4838 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
4839 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4842 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4843 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4844 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4845 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4847 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
4848 (VCVTPD2DQYrr VR256:$src)>;
4849 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
4850 (VCVTPD2DQYrm addr:$src)>;
4852 // Convert Packed DW Integers to Packed Double FP
4853 let Predicates = [HasAVX] in {
4854 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4855 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4856 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4857 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4858 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
4859 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4860 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
4861 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4864 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4865 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4866 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4867 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4869 // AVX 256-bit register conversion intrinsics
4870 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
4871 (VCVTDQ2PDYrr VR128:$src)>;
4872 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
4873 (VCVTDQ2PDYrm addr:$src)>;
4875 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
4876 (VCVTPD2DQYrr VR256:$src)>;
4877 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
4878 (VCVTPD2DQYrm addr:$src)>;
4880 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
4881 (VCVTDQ2PDYrr VR128:$src)>;
4882 def : Pat<(v4f64 (sint_to_fp (memopv4i32 addr:$src))),
4883 (VCVTDQ2PDYrm addr:$src)>;
4885 //===---------------------------------------------------------------------===//
4886 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4887 //===---------------------------------------------------------------------===//
4888 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4889 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4890 X86MemOperand x86memop> {
4891 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4892 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4893 [(set RC:$dst, (vt (OpNode RC:$src)))]>;
4894 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4895 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4896 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>;
4899 let Predicates = [HasAVX] in {
4900 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4901 v4f32, VR128, memopv4f32, f128mem>, VEX;
4902 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4903 v4f32, VR128, memopv4f32, f128mem>, VEX;
4904 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4905 v8f32, VR256, memopv8f32, f256mem>, VEX;
4906 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4907 v8f32, VR256, memopv8f32, f256mem>, VEX;
4909 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4910 memopv4f32, f128mem>;
4911 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4912 memopv4f32, f128mem>;
4914 let Predicates = [HasSSE3] in {
4915 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4916 (MOVSHDUPrr VR128:$src)>;
4917 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4918 (MOVSHDUPrm addr:$src)>;
4919 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4920 (MOVSLDUPrr VR128:$src)>;
4921 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4922 (MOVSLDUPrm addr:$src)>;
4925 let Predicates = [HasAVX] in {
4926 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4927 (VMOVSHDUPrr VR128:$src)>;
4928 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4929 (VMOVSHDUPrm addr:$src)>;
4930 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4931 (VMOVSLDUPrr VR128:$src)>;
4932 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4933 (VMOVSLDUPrm addr:$src)>;
4934 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4935 (VMOVSHDUPYrr VR256:$src)>;
4936 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4937 (VMOVSHDUPYrm addr:$src)>;
4938 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4939 (VMOVSLDUPYrr VR256:$src)>;
4940 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4941 (VMOVSLDUPYrm addr:$src)>;
4944 //===---------------------------------------------------------------------===//
4945 // SSE3 - Replicate Double FP - MOVDDUP
4946 //===---------------------------------------------------------------------===//
4948 multiclass sse3_replicate_dfp<string OpcodeStr> {
4949 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4950 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4951 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
4952 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4953 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4955 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
4959 // FIXME: Merge with above classe when there're patterns for the ymm version
4960 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4961 let Predicates = [HasAVX] in {
4962 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4963 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4965 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4966 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4971 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4972 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4973 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
4975 let Predicates = [HasSSE3] in {
4976 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
4978 (MOVDDUPrm addr:$src)>;
4979 let AddedComplexity = 5 in {
4980 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
4981 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
4982 (MOVDDUPrm addr:$src)>;
4983 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
4984 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
4985 (MOVDDUPrm addr:$src)>;
4987 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4988 (MOVDDUPrm addr:$src)>;
4989 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4990 (MOVDDUPrm addr:$src)>;
4991 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4992 (MOVDDUPrm addr:$src)>;
4993 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
4994 (MOVDDUPrm addr:$src)>;
4995 def : Pat<(X86Movddup (bc_v2f64
4996 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4997 (MOVDDUPrm addr:$src)>;
5000 let Predicates = [HasAVX] in {
5001 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
5003 (VMOVDDUPrm addr:$src)>;
5004 let AddedComplexity = 5 in {
5005 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
5006 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
5007 (VMOVDDUPrm addr:$src)>;
5008 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
5009 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
5010 (VMOVDDUPrm addr:$src)>;
5012 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5013 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5014 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5015 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5016 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5017 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5018 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5019 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5020 def : Pat<(X86Movddup (bc_v2f64
5021 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5022 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5025 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
5026 (VMOVDDUPYrm addr:$src)>;
5027 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
5028 (VMOVDDUPYrm addr:$src)>;
5029 def : Pat<(X86Movddup (v4f64 (scalar_to_vector (loadf64 addr:$src)))),
5030 (VMOVDDUPYrm addr:$src)>;
5031 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5032 (VMOVDDUPYrm addr:$src)>;
5033 def : Pat<(X86Movddup (v4f64 VR256:$src)),
5034 (VMOVDDUPYrr VR256:$src)>;
5035 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5036 (VMOVDDUPYrr VR256:$src)>;
5039 //===---------------------------------------------------------------------===//
5040 // SSE3 - Move Unaligned Integer
5041 //===---------------------------------------------------------------------===//
5043 let Predicates = [HasAVX] in {
5044 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5045 "vlddqu\t{$src, $dst|$dst, $src}",
5046 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5047 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5048 "vlddqu\t{$src, $dst|$dst, $src}",
5049 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
5051 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5052 "lddqu\t{$src, $dst|$dst, $src}",
5053 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
5055 //===---------------------------------------------------------------------===//
5056 // SSE3 - Arithmetic
5057 //===---------------------------------------------------------------------===//
5059 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5060 X86MemOperand x86memop, bit Is2Addr = 1> {
5061 def rr : I<0xD0, MRMSrcReg,
5062 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5064 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5065 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5066 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
5067 def rm : I<0xD0, MRMSrcMem,
5068 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5070 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5071 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5072 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
5075 let Predicates = [HasAVX] in {
5076 let ExeDomain = SSEPackedSingle in {
5077 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5078 f128mem, 0>, TB, XD, VEX_4V;
5079 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5080 f256mem, 0>, TB, XD, VEX_4V;
5082 let ExeDomain = SSEPackedDouble in {
5083 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5084 f128mem, 0>, TB, OpSize, VEX_4V;
5085 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5086 f256mem, 0>, TB, OpSize, VEX_4V;
5089 let Constraints = "$src1 = $dst", Predicates = [HasSSE3] in {
5090 let ExeDomain = SSEPackedSingle in
5091 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5093 let ExeDomain = SSEPackedDouble in
5094 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5095 f128mem>, TB, OpSize;
5098 //===---------------------------------------------------------------------===//
5099 // SSE3 Instructions
5100 //===---------------------------------------------------------------------===//
5103 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5104 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5105 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5107 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5108 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5109 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))]>;
5111 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5113 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5114 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5115 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))]>;
5117 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5118 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5119 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5121 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5122 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5123 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))]>;
5125 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5127 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5128 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5129 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))]>;
5132 let Predicates = [HasAVX] in {
5133 let ExeDomain = SSEPackedSingle in {
5134 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5135 X86fhadd, 0>, VEX_4V;
5136 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5137 X86fhsub, 0>, VEX_4V;
5138 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5139 X86fhadd, 0>, VEX_4V;
5140 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5141 X86fhsub, 0>, VEX_4V;
5143 let ExeDomain = SSEPackedDouble in {
5144 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5145 X86fhadd, 0>, VEX_4V;
5146 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5147 X86fhsub, 0>, VEX_4V;
5148 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5149 X86fhadd, 0>, VEX_4V;
5150 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5151 X86fhsub, 0>, VEX_4V;
5155 let Constraints = "$src1 = $dst" in {
5156 let ExeDomain = SSEPackedSingle in {
5157 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5158 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5160 let ExeDomain = SSEPackedDouble in {
5161 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5162 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5166 //===---------------------------------------------------------------------===//
5167 // SSSE3 - Packed Absolute Instructions
5168 //===---------------------------------------------------------------------===//
5171 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5172 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5173 PatFrag mem_frag128, Intrinsic IntId128> {
5174 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5176 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5177 [(set VR128:$dst, (IntId128 VR128:$src))]>,
5180 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5182 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5185 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
5188 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5189 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5190 PatFrag mem_frag256, Intrinsic IntId256> {
5191 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5193 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5194 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5197 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5199 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5202 (bitconvert (mem_frag256 addr:$src))))]>, OpSize;
5205 let Predicates = [HasAVX] in {
5206 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
5207 int_x86_ssse3_pabs_b_128>, VEX;
5208 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
5209 int_x86_ssse3_pabs_w_128>, VEX;
5210 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
5211 int_x86_ssse3_pabs_d_128>, VEX;
5214 let Predicates = [HasAVX2] in {
5215 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb", memopv32i8,
5216 int_x86_avx2_pabs_b>, VEX;
5217 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw", memopv16i16,
5218 int_x86_avx2_pabs_w>, VEX;
5219 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd", memopv8i32,
5220 int_x86_avx2_pabs_d>, VEX;
5223 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
5224 int_x86_ssse3_pabs_b_128>;
5225 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
5226 int_x86_ssse3_pabs_w_128>;
5227 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
5228 int_x86_ssse3_pabs_d_128>;
5230 //===---------------------------------------------------------------------===//
5231 // SSSE3 - Packed Binary Operator Instructions
5232 //===---------------------------------------------------------------------===//
5234 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5235 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5236 PatFrag mem_frag128, Intrinsic IntId128,
5238 let isCommutable = 1 in
5239 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5240 (ins VR128:$src1, VR128:$src2),
5242 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5243 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5244 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5246 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5247 (ins VR128:$src1, i128mem:$src2),
5249 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5250 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5252 (IntId128 VR128:$src1,
5253 (bitconvert (mem_frag128 addr:$src2))))]>, OpSize;
5256 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5257 PatFrag mem_frag256, Intrinsic IntId256> {
5258 let isCommutable = 1 in
5259 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5260 (ins VR256:$src1, VR256:$src2),
5261 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5262 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5264 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5265 (ins VR256:$src1, i256mem:$src2),
5266 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5268 (IntId256 VR256:$src1,
5269 (bitconvert (mem_frag256 addr:$src2))))]>, OpSize;
5272 let ImmT = NoImm, Predicates = [HasAVX] in {
5273 let isCommutable = 0 in {
5274 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
5275 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
5276 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
5277 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
5278 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
5279 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
5280 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
5281 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
5282 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
5283 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
5284 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
5285 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
5286 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
5287 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
5288 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
5289 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
5290 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
5291 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
5292 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
5293 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
5294 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
5295 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
5297 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
5298 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
5301 let ImmT = NoImm, Predicates = [HasAVX2] in {
5302 let isCommutable = 0 in {
5303 defm VPHADDW : SS3I_binop_rm_int_y<0x01, "vphaddw", memopv16i16,
5304 int_x86_avx2_phadd_w>, VEX_4V;
5305 defm VPHADDD : SS3I_binop_rm_int_y<0x02, "vphaddd", memopv8i32,
5306 int_x86_avx2_phadd_d>, VEX_4V;
5307 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw", memopv16i16,
5308 int_x86_avx2_phadd_sw>, VEX_4V;
5309 defm VPHSUBW : SS3I_binop_rm_int_y<0x05, "vphsubw", memopv16i16,
5310 int_x86_avx2_phsub_w>, VEX_4V;
5311 defm VPHSUBD : SS3I_binop_rm_int_y<0x06, "vphsubd", memopv8i32,
5312 int_x86_avx2_phsub_d>, VEX_4V;
5313 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw", memopv16i16,
5314 int_x86_avx2_phsub_sw>, VEX_4V;
5315 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw", memopv32i8,
5316 int_x86_avx2_pmadd_ub_sw>, VEX_4V;
5317 defm VPSHUFB : SS3I_binop_rm_int_y<0x00, "vpshufb", memopv32i8,
5318 int_x86_avx2_pshuf_b>, VEX_4V;
5319 defm VPSIGNB : SS3I_binop_rm_int_y<0x08, "vpsignb", memopv16i8,
5320 int_x86_avx2_psign_b>, VEX_4V;
5321 defm VPSIGNW : SS3I_binop_rm_int_y<0x09, "vpsignw", memopv8i16,
5322 int_x86_avx2_psign_w>, VEX_4V;
5323 defm VPSIGND : SS3I_binop_rm_int_y<0x0A, "vpsignd", memopv4i32,
5324 int_x86_avx2_psign_d>, VEX_4V;
5326 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw", memopv16i16,
5327 int_x86_avx2_pmul_hr_sw>, VEX_4V;
5330 // None of these have i8 immediate fields.
5331 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5332 let isCommutable = 0 in {
5333 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
5334 int_x86_ssse3_phadd_w_128>;
5335 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
5336 int_x86_ssse3_phadd_d_128>;
5337 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
5338 int_x86_ssse3_phadd_sw_128>;
5339 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
5340 int_x86_ssse3_phsub_w_128>;
5341 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
5342 int_x86_ssse3_phsub_d_128>;
5343 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
5344 int_x86_ssse3_phsub_sw_128>;
5345 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
5346 int_x86_ssse3_pmadd_ub_sw_128>;
5347 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
5348 int_x86_ssse3_pshuf_b_128>;
5349 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
5350 int_x86_ssse3_psign_b_128>;
5351 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
5352 int_x86_ssse3_psign_w_128>;
5353 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
5354 int_x86_ssse3_psign_d_128>;
5356 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
5357 int_x86_ssse3_pmul_hr_sw_128>;
5360 let Predicates = [HasSSSE3] in {
5361 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
5362 (PSHUFBrr128 VR128:$src, VR128:$mask)>;
5363 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
5364 (PSHUFBrm128 VR128:$src, addr:$mask)>;
5366 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
5367 (PSIGNBrr128 VR128:$src1, VR128:$src2)>;
5368 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
5369 (PSIGNWrr128 VR128:$src1, VR128:$src2)>;
5370 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
5371 (PSIGNDrr128 VR128:$src1, VR128:$src2)>;
5374 let Predicates = [HasAVX] in {
5375 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
5376 (VPSHUFBrr128 VR128:$src, VR128:$mask)>;
5377 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
5378 (VPSHUFBrm128 VR128:$src, addr:$mask)>;
5380 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
5381 (VPSIGNBrr128 VR128:$src1, VR128:$src2)>;
5382 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
5383 (VPSIGNWrr128 VR128:$src1, VR128:$src2)>;
5384 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
5385 (VPSIGNDrr128 VR128:$src1, VR128:$src2)>;
5388 //===---------------------------------------------------------------------===//
5389 // SSSE3 - Packed Align Instruction Patterns
5390 //===---------------------------------------------------------------------===//
5392 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
5393 let neverHasSideEffects = 1 in {
5394 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5395 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5397 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5399 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5402 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5403 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5405 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5407 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5412 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
5413 let neverHasSideEffects = 1 in {
5414 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5415 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5417 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5420 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5421 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5423 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5428 let Predicates = [HasAVX] in
5429 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5430 let Predicates = [HasAVX2] in
5431 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V;
5432 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
5433 defm PALIGN : ssse3_palign<"palignr">;
5435 let Predicates = [HasSSSE3] in {
5436 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5437 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5438 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5439 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5440 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5441 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5442 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5443 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5446 let Predicates = [HasAVX] in {
5447 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5448 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5449 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5450 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5451 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5452 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5453 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5454 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5457 //===---------------------------------------------------------------------===//
5458 // SSSE3 - Thread synchronization
5459 //===---------------------------------------------------------------------===//
5461 let usesCustomInserter = 1 in {
5462 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5463 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
5464 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
5465 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
5468 let Uses = [EAX, ECX, EDX] in
5469 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
5470 Requires<[HasSSE3]>;
5471 let Uses = [ECX, EAX] in
5472 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
5473 Requires<[HasSSE3]>;
5475 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5476 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5478 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5479 Requires<[In32BitMode]>;
5480 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5481 Requires<[In64BitMode]>;
5483 //===----------------------------------------------------------------------===//
5484 // SSE4.1 - Packed Move with Sign/Zero Extend
5485 //===----------------------------------------------------------------------===//
5487 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5488 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5489 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5490 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5492 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5493 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5495 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5499 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5501 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5502 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5503 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5505 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5506 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5507 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5510 let Predicates = [HasAVX] in {
5511 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5513 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5515 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5517 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5519 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5521 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5525 let Predicates = [HasAVX2] in {
5526 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5527 int_x86_avx2_pmovsxbw>, VEX;
5528 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5529 int_x86_avx2_pmovsxwd>, VEX;
5530 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5531 int_x86_avx2_pmovsxdq>, VEX;
5532 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5533 int_x86_avx2_pmovzxbw>, VEX;
5534 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5535 int_x86_avx2_pmovzxwd>, VEX;
5536 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5537 int_x86_avx2_pmovzxdq>, VEX;
5540 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5541 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5542 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5543 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5544 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5545 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5547 let Predicates = [HasSSE41] in {
5548 // Common patterns involving scalar load.
5549 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5550 (PMOVSXBWrm addr:$src)>;
5551 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5552 (PMOVSXBWrm addr:$src)>;
5554 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5555 (PMOVSXWDrm addr:$src)>;
5556 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5557 (PMOVSXWDrm addr:$src)>;
5559 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5560 (PMOVSXDQrm addr:$src)>;
5561 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5562 (PMOVSXDQrm addr:$src)>;
5564 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5565 (PMOVZXBWrm addr:$src)>;
5566 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5567 (PMOVZXBWrm addr:$src)>;
5569 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5570 (PMOVZXWDrm addr:$src)>;
5571 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5572 (PMOVZXWDrm addr:$src)>;
5574 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5575 (PMOVZXDQrm addr:$src)>;
5576 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5577 (PMOVZXDQrm addr:$src)>;
5580 let Predicates = [HasAVX] in {
5581 // Common patterns involving scalar load.
5582 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5583 (VPMOVSXBWrm addr:$src)>;
5584 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5585 (VPMOVSXBWrm addr:$src)>;
5587 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5588 (VPMOVSXWDrm addr:$src)>;
5589 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5590 (VPMOVSXWDrm addr:$src)>;
5592 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5593 (VPMOVSXDQrm addr:$src)>;
5594 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5595 (VPMOVSXDQrm addr:$src)>;
5597 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5598 (VPMOVZXBWrm addr:$src)>;
5599 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5600 (VPMOVZXBWrm addr:$src)>;
5602 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5603 (VPMOVZXWDrm addr:$src)>;
5604 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5605 (VPMOVZXWDrm addr:$src)>;
5607 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5608 (VPMOVZXDQrm addr:$src)>;
5609 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5610 (VPMOVZXDQrm addr:$src)>;
5614 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5615 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5616 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5617 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5619 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5620 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5622 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5626 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5628 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5629 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5630 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5632 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5633 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5635 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5639 let Predicates = [HasAVX] in {
5640 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5642 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5644 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5646 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5650 let Predicates = [HasAVX2] in {
5651 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5652 int_x86_avx2_pmovsxbd>, VEX;
5653 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5654 int_x86_avx2_pmovsxwq>, VEX;
5655 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5656 int_x86_avx2_pmovzxbd>, VEX;
5657 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5658 int_x86_avx2_pmovzxwq>, VEX;
5661 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5662 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5663 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5664 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5666 let Predicates = [HasSSE41] in {
5667 // Common patterns involving scalar load
5668 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5669 (PMOVSXBDrm addr:$src)>;
5670 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5671 (PMOVSXWQrm addr:$src)>;
5673 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5674 (PMOVZXBDrm addr:$src)>;
5675 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5676 (PMOVZXWQrm addr:$src)>;
5679 let Predicates = [HasAVX] in {
5680 // Common patterns involving scalar load
5681 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5682 (VPMOVSXBDrm addr:$src)>;
5683 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5684 (VPMOVSXWQrm addr:$src)>;
5686 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5687 (VPMOVZXBDrm addr:$src)>;
5688 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5689 (VPMOVZXWQrm addr:$src)>;
5692 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5693 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5694 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5695 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5697 // Expecting a i16 load any extended to i32 value.
5698 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5699 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5700 [(set VR128:$dst, (IntId (bitconvert
5701 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5705 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5707 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5708 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5709 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5711 // Expecting a i16 load any extended to i32 value.
5712 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5713 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5714 [(set VR256:$dst, (IntId (bitconvert
5715 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5719 let Predicates = [HasAVX] in {
5720 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5722 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5725 let Predicates = [HasAVX2] in {
5726 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5727 int_x86_avx2_pmovsxbq>, VEX;
5728 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5729 int_x86_avx2_pmovzxbq>, VEX;
5731 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5732 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5734 let Predicates = [HasSSE41] in {
5735 // Common patterns involving scalar load
5736 def : Pat<(int_x86_sse41_pmovsxbq
5737 (bitconvert (v4i32 (X86vzmovl
5738 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5739 (PMOVSXBQrm addr:$src)>;
5741 def : Pat<(int_x86_sse41_pmovzxbq
5742 (bitconvert (v4i32 (X86vzmovl
5743 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5744 (PMOVZXBQrm addr:$src)>;
5747 let Predicates = [HasAVX] in {
5748 // Common patterns involving scalar load
5749 def : Pat<(int_x86_sse41_pmovsxbq
5750 (bitconvert (v4i32 (X86vzmovl
5751 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5752 (VPMOVSXBQrm addr:$src)>;
5754 def : Pat<(int_x86_sse41_pmovzxbq
5755 (bitconvert (v4i32 (X86vzmovl
5756 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5757 (VPMOVZXBQrm addr:$src)>;
5760 //===----------------------------------------------------------------------===//
5761 // SSE4.1 - Extract Instructions
5762 //===----------------------------------------------------------------------===//
5764 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5765 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5766 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5767 (ins VR128:$src1, i32i8imm:$src2),
5768 !strconcat(OpcodeStr,
5769 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5770 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5772 let neverHasSideEffects = 1, mayStore = 1 in
5773 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5774 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5775 !strconcat(OpcodeStr,
5776 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5779 // There's an AssertZext in the way of writing the store pattern
5780 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5783 let Predicates = [HasAVX] in {
5784 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5785 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5786 (ins VR128:$src1, i32i8imm:$src2),
5787 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5790 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5793 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5794 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5795 let neverHasSideEffects = 1, mayStore = 1 in
5796 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5797 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5798 !strconcat(OpcodeStr,
5799 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5802 // There's an AssertZext in the way of writing the store pattern
5803 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5806 let Predicates = [HasAVX] in
5807 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5809 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5812 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5813 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5814 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5815 (ins VR128:$src1, i32i8imm:$src2),
5816 !strconcat(OpcodeStr,
5817 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5819 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5820 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5821 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5822 !strconcat(OpcodeStr,
5823 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5824 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5825 addr:$dst)]>, OpSize;
5828 let Predicates = [HasAVX] in
5829 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5831 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5833 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5834 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5835 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5836 (ins VR128:$src1, i32i8imm:$src2),
5837 !strconcat(OpcodeStr,
5838 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5840 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5841 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5842 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5843 !strconcat(OpcodeStr,
5844 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5845 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5846 addr:$dst)]>, OpSize, REX_W;
5849 let Predicates = [HasAVX] in
5850 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5852 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5854 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5856 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5857 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5858 (ins VR128:$src1, i32i8imm:$src2),
5859 !strconcat(OpcodeStr,
5860 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5862 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5864 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5865 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5866 !strconcat(OpcodeStr,
5867 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5868 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5869 addr:$dst)]>, OpSize;
5872 let ExeDomain = SSEPackedSingle in {
5873 let Predicates = [HasAVX] in {
5874 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5875 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5876 (ins VR128:$src1, i32i8imm:$src2),
5877 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
5880 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
5883 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
5884 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5887 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5888 Requires<[HasSSE41]>;
5889 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5892 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5895 //===----------------------------------------------------------------------===//
5896 // SSE4.1 - Insert Instructions
5897 //===----------------------------------------------------------------------===//
5899 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5900 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5901 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5903 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5905 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5907 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5908 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5909 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
5911 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5913 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5915 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
5916 imm:$src3))]>, OpSize;
5919 let Predicates = [HasAVX] in
5920 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
5921 let Constraints = "$src1 = $dst" in
5922 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
5924 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
5925 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5926 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5928 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5930 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5932 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
5934 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5935 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
5937 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5939 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5941 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
5942 imm:$src3)))]>, OpSize;
5945 let Predicates = [HasAVX] in
5946 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
5947 let Constraints = "$src1 = $dst" in
5948 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
5950 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
5951 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5952 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
5954 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5956 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5958 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
5960 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5961 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
5963 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5965 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5967 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
5968 imm:$src3)))]>, OpSize;
5971 let Predicates = [HasAVX] in
5972 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
5973 let Constraints = "$src1 = $dst" in
5974 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
5976 // insertps has a few different modes, there's the first two here below which
5977 // are optimized inserts that won't zero arbitrary elements in the destination
5978 // vector. The next one matches the intrinsic and could zero arbitrary elements
5979 // in the target vector.
5980 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
5981 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5982 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
5984 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5986 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5988 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
5990 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5991 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
5993 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5995 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5997 (X86insrtps VR128:$src1,
5998 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
5999 imm:$src3))]>, OpSize;
6002 let ExeDomain = SSEPackedSingle in {
6003 let Constraints = "$src1 = $dst" in
6004 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
6005 let Predicates = [HasAVX] in
6006 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6009 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
6010 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
6012 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
6013 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
6014 Requires<[HasSSE41]>;
6016 //===----------------------------------------------------------------------===//
6017 // SSE4.1 - Round Instructions
6018 //===----------------------------------------------------------------------===//
6020 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6021 X86MemOperand x86memop, RegisterClass RC,
6022 PatFrag mem_frag32, PatFrag mem_frag64,
6023 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6024 let ExeDomain = SSEPackedSingle in {
6025 // Intrinsic operation, reg.
6026 // Vector intrinsic operation, reg
6027 def PSr : SS4AIi8<opcps, MRMSrcReg,
6028 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6029 !strconcat(OpcodeStr,
6030 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6031 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
6034 // Vector intrinsic operation, mem
6035 def PSm : SS4AIi8<opcps, MRMSrcMem,
6036 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6037 !strconcat(OpcodeStr,
6038 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6040 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
6042 } // ExeDomain = SSEPackedSingle
6044 let ExeDomain = SSEPackedDouble in {
6045 // Vector intrinsic operation, reg
6046 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6047 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6048 !strconcat(OpcodeStr,
6049 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6050 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
6053 // Vector intrinsic operation, mem
6054 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6055 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6056 !strconcat(OpcodeStr,
6057 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6059 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
6061 } // ExeDomain = SSEPackedDouble
6064 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6067 Intrinsic F64Int, bit Is2Addr = 1> {
6068 let ExeDomain = GenericDomain in {
6069 // Intrinsic operation, reg.
6070 def SSr : SS4AIi8<opcss, MRMSrcReg,
6071 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6073 !strconcat(OpcodeStr,
6074 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6075 !strconcat(OpcodeStr,
6076 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6077 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6080 // Intrinsic operation, mem.
6081 def SSm : SS4AIi8<opcss, MRMSrcMem,
6082 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6084 !strconcat(OpcodeStr,
6085 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6086 !strconcat(OpcodeStr,
6087 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6089 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6092 // Intrinsic operation, reg.
6093 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6094 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6096 !strconcat(OpcodeStr,
6097 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6098 !strconcat(OpcodeStr,
6099 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6100 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6103 // Intrinsic operation, mem.
6104 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6105 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6107 !strconcat(OpcodeStr,
6108 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6109 !strconcat(OpcodeStr,
6110 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6112 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6114 } // ExeDomain = GenericDomain
6117 // FP round - roundss, roundps, roundsd, roundpd
6118 let Predicates = [HasAVX] in {
6120 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6121 memopv4f32, memopv2f64,
6122 int_x86_sse41_round_ps,
6123 int_x86_sse41_round_pd>, VEX;
6124 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6125 memopv8f32, memopv4f64,
6126 int_x86_avx_round_ps_256,
6127 int_x86_avx_round_pd_256>, VEX;
6128 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6129 int_x86_sse41_round_ss,
6130 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6133 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6134 memopv4f32, memopv2f64,
6135 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6136 let Constraints = "$src1 = $dst" in
6137 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6138 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6140 //===----------------------------------------------------------------------===//
6141 // SSE4.1 - Packed Bit Test
6142 //===----------------------------------------------------------------------===//
6144 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6145 // the intel intrinsic that corresponds to this.
6146 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6147 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6148 "vptest\t{$src2, $src1|$src1, $src2}",
6149 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
6151 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6152 "vptest\t{$src2, $src1|$src1, $src2}",
6153 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
6156 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6157 "vptest\t{$src2, $src1|$src1, $src2}",
6158 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6160 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6161 "vptest\t{$src2, $src1|$src1, $src2}",
6162 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6166 let Defs = [EFLAGS] in {
6167 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6168 "ptest\t{$src2, $src1|$src1, $src2}",
6169 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
6171 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6172 "ptest\t{$src2, $src1|$src1, $src2}",
6173 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
6177 // The bit test instructions below are AVX only
6178 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6179 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6180 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6181 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6182 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6183 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6184 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6185 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6189 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6190 let ExeDomain = SSEPackedSingle in {
6191 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6192 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
6194 let ExeDomain = SSEPackedDouble in {
6195 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6196 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
6200 //===----------------------------------------------------------------------===//
6201 // SSE4.1 - Misc Instructions
6202 //===----------------------------------------------------------------------===//
6204 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6205 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6206 "popcnt{w}\t{$src, $dst|$dst, $src}",
6207 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6209 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6210 "popcnt{w}\t{$src, $dst|$dst, $src}",
6211 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6212 (implicit EFLAGS)]>, OpSize, XS;
6214 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6215 "popcnt{l}\t{$src, $dst|$dst, $src}",
6216 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6218 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6219 "popcnt{l}\t{$src, $dst|$dst, $src}",
6220 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6221 (implicit EFLAGS)]>, XS;
6223 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6224 "popcnt{q}\t{$src, $dst|$dst, $src}",
6225 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6227 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6228 "popcnt{q}\t{$src, $dst|$dst, $src}",
6229 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6230 (implicit EFLAGS)]>, XS;
6235 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6236 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6237 Intrinsic IntId128> {
6238 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6240 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6241 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6242 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6244 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6247 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
6250 let Predicates = [HasAVX] in
6251 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6252 int_x86_sse41_phminposuw>, VEX;
6253 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6254 int_x86_sse41_phminposuw>;
6256 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6257 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6258 Intrinsic IntId128, bit Is2Addr = 1> {
6259 let isCommutable = 1 in
6260 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6261 (ins VR128:$src1, VR128:$src2),
6263 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6264 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6265 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6266 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6267 (ins VR128:$src1, i128mem:$src2),
6269 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6270 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6272 (IntId128 VR128:$src1,
6273 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
6276 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6277 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6278 Intrinsic IntId256> {
6279 let isCommutable = 1 in
6280 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6281 (ins VR256:$src1, VR256:$src2),
6282 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6283 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6284 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6285 (ins VR256:$src1, i256mem:$src2),
6286 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6288 (IntId256 VR256:$src1,
6289 (bitconvert (memopv32i8 addr:$src2))))]>, OpSize;
6292 let Predicates = [HasAVX] in {
6293 let isCommutable = 0 in
6294 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6296 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
6298 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
6300 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
6302 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
6304 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
6306 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
6308 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
6310 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
6312 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
6314 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6317 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
6318 (VPCMPEQQrr VR128:$src1, VR128:$src2)>;
6319 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
6320 (VPCMPEQQrm VR128:$src1, addr:$src2)>;
6323 let Predicates = [HasAVX2] in {
6324 let isCommutable = 0 in
6325 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6326 int_x86_avx2_packusdw>, VEX_4V;
6327 defm VPCMPEQQ : SS41I_binop_rm_int_y<0x29, "vpcmpeqq",
6328 int_x86_avx2_pcmpeq_q>, VEX_4V;
6329 defm VPMINSB : SS41I_binop_rm_int_y<0x38, "vpminsb",
6330 int_x86_avx2_pmins_b>, VEX_4V;
6331 defm VPMINSD : SS41I_binop_rm_int_y<0x39, "vpminsd",
6332 int_x86_avx2_pmins_d>, VEX_4V;
6333 defm VPMINUD : SS41I_binop_rm_int_y<0x3B, "vpminud",
6334 int_x86_avx2_pminu_d>, VEX_4V;
6335 defm VPMINUW : SS41I_binop_rm_int_y<0x3A, "vpminuw",
6336 int_x86_avx2_pminu_w>, VEX_4V;
6337 defm VPMAXSB : SS41I_binop_rm_int_y<0x3C, "vpmaxsb",
6338 int_x86_avx2_pmaxs_b>, VEX_4V;
6339 defm VPMAXSD : SS41I_binop_rm_int_y<0x3D, "vpmaxsd",
6340 int_x86_avx2_pmaxs_d>, VEX_4V;
6341 defm VPMAXUD : SS41I_binop_rm_int_y<0x3F, "vpmaxud",
6342 int_x86_avx2_pmaxu_d>, VEX_4V;
6343 defm VPMAXUW : SS41I_binop_rm_int_y<0x3E, "vpmaxuw",
6344 int_x86_avx2_pmaxu_w>, VEX_4V;
6345 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6346 int_x86_avx2_pmul_dq>, VEX_4V;
6348 def : Pat<(v4i64 (X86pcmpeqq VR256:$src1, VR256:$src2)),
6349 (VPCMPEQQYrr VR256:$src1, VR256:$src2)>;
6350 def : Pat<(v4i64 (X86pcmpeqq VR256:$src1, (memop addr:$src2))),
6351 (VPCMPEQQYrm VR256:$src1, addr:$src2)>;
6354 let Constraints = "$src1 = $dst" in {
6355 let isCommutable = 0 in
6356 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6357 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
6358 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
6359 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
6360 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
6361 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
6362 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
6363 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
6364 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
6365 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
6366 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6369 let Predicates = [HasSSE41] in {
6370 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
6371 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
6372 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
6373 (PCMPEQQrm VR128:$src1, addr:$src2)>;
6376 /// SS48I_binop_rm - Simple SSE41 binary operator.
6377 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6378 ValueType OpVT, bit Is2Addr = 1> {
6379 let isCommutable = 1 in
6380 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6381 (ins VR128:$src1, VR128:$src2),
6383 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6384 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6385 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
6387 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6388 (ins VR128:$src1, i128mem:$src2),
6390 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6391 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6392 [(set VR128:$dst, (OpNode VR128:$src1,
6393 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
6397 /// SS48I_binop_rm - Simple SSE41 binary operator.
6398 multiclass SS48I_binop_rm_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
6400 let isCommutable = 1 in
6401 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6402 (ins VR256:$src1, VR256:$src2),
6403 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6404 [(set VR256:$dst, (OpVT (OpNode VR256:$src1, VR256:$src2)))]>,
6406 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6407 (ins VR256:$src1, i256mem:$src2),
6408 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6409 [(set VR256:$dst, (OpNode VR256:$src1,
6410 (bc_v8i32 (memopv4i64 addr:$src2))))]>,
6414 let Predicates = [HasAVX] in
6415 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
6416 let Predicates = [HasAVX2] in
6417 defm VPMULLD : SS48I_binop_rm_y<0x40, "vpmulld", mul, v8i32>, VEX_4V;
6418 let Constraints = "$src1 = $dst" in
6419 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
6421 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6422 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6423 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6424 X86MemOperand x86memop, bit Is2Addr = 1> {
6425 let isCommutable = 1 in
6426 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6427 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6429 !strconcat(OpcodeStr,
6430 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6431 !strconcat(OpcodeStr,
6432 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6433 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6435 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6436 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6438 !strconcat(OpcodeStr,
6439 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6440 !strconcat(OpcodeStr,
6441 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6444 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6448 let Predicates = [HasAVX] in {
6449 let isCommutable = 0 in {
6450 let ExeDomain = SSEPackedSingle in {
6451 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6452 VR128, memopv16i8, i128mem, 0>, VEX_4V;
6453 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6454 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
6456 let ExeDomain = SSEPackedDouble in {
6457 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6458 VR128, memopv16i8, i128mem, 0>, VEX_4V;
6459 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6460 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
6462 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6463 VR128, memopv16i8, i128mem, 0>, VEX_4V;
6464 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6465 VR128, memopv16i8, i128mem, 0>, VEX_4V;
6467 let ExeDomain = SSEPackedSingle in
6468 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6469 VR128, memopv16i8, i128mem, 0>, VEX_4V;
6470 let ExeDomain = SSEPackedDouble in
6471 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6472 VR128, memopv16i8, i128mem, 0>, VEX_4V;
6473 let ExeDomain = SSEPackedSingle in
6474 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6475 VR256, memopv32i8, i256mem, 0>, VEX_4V;
6478 let Predicates = [HasAVX2] in {
6479 let isCommutable = 0 in {
6480 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6481 VR256, memopv32i8, i256mem, 0>, VEX_4V;
6482 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6483 VR256, memopv32i8, i256mem, 0>, VEX_4V;
6487 let Constraints = "$src1 = $dst" in {
6488 let isCommutable = 0 in {
6489 let ExeDomain = SSEPackedSingle in
6490 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6491 VR128, memopv16i8, i128mem>;
6492 let ExeDomain = SSEPackedDouble in
6493 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6494 VR128, memopv16i8, i128mem>;
6495 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6496 VR128, memopv16i8, i128mem>;
6497 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6498 VR128, memopv16i8, i128mem>;
6500 let ExeDomain = SSEPackedSingle in
6501 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6502 VR128, memopv16i8, i128mem>;
6503 let ExeDomain = SSEPackedDouble in
6504 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6505 VR128, memopv16i8, i128mem>;
6508 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6509 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6510 RegisterClass RC, X86MemOperand x86memop,
6511 PatFrag mem_frag, Intrinsic IntId> {
6512 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
6513 (ins RC:$src1, RC:$src2, RC:$src3),
6514 !strconcat(OpcodeStr,
6515 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6516 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6517 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6519 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
6520 (ins RC:$src1, x86memop:$src2, RC:$src3),
6521 !strconcat(OpcodeStr,
6522 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6524 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6526 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6529 let Predicates = [HasAVX] in {
6530 let ExeDomain = SSEPackedDouble in {
6531 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
6532 memopv16i8, int_x86_sse41_blendvpd>;
6533 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
6534 memopv32i8, int_x86_avx_blendv_pd_256>;
6535 } // ExeDomain = SSEPackedDouble
6536 let ExeDomain = SSEPackedSingle in {
6537 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
6538 memopv16i8, int_x86_sse41_blendvps>;
6539 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
6540 memopv32i8, int_x86_avx_blendv_ps_256>;
6541 } // ExeDomain = SSEPackedSingle
6542 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6543 memopv16i8, int_x86_sse41_pblendvb>;
6546 let Predicates = [HasAVX2] in {
6547 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6548 memopv32i8, int_x86_avx2_pblendvb>;
6551 let Predicates = [HasAVX] in {
6552 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6553 (v16i8 VR128:$src2))),
6554 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6555 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6556 (v4i32 VR128:$src2))),
6557 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6558 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6559 (v4f32 VR128:$src2))),
6560 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6561 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6562 (v2i64 VR128:$src2))),
6563 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6564 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6565 (v2f64 VR128:$src2))),
6566 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6567 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6568 (v8i32 VR256:$src2))),
6569 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6570 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6571 (v8f32 VR256:$src2))),
6572 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6573 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6574 (v4i64 VR256:$src2))),
6575 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6576 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6577 (v4f64 VR256:$src2))),
6578 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6581 let Predicates = [HasAVX2] in {
6582 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6583 (v32i8 VR256:$src2))),
6584 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6587 /// SS41I_ternary_int - SSE 4.1 ternary operator
6588 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6589 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
6590 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6591 (ins VR128:$src1, VR128:$src2),
6592 !strconcat(OpcodeStr,
6593 "\t{$src2, $dst|$dst, $src2}"),
6594 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6597 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6598 (ins VR128:$src1, i128mem:$src2),
6599 !strconcat(OpcodeStr,
6600 "\t{$src2, $dst|$dst, $src2}"),
6603 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
6607 let ExeDomain = SSEPackedDouble in
6608 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
6609 let ExeDomain = SSEPackedSingle in
6610 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
6611 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
6613 let Predicates = [HasSSE41] in {
6614 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6615 (v16i8 VR128:$src2))),
6616 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6617 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6618 (v4i32 VR128:$src2))),
6619 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6620 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6621 (v4f32 VR128:$src2))),
6622 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6623 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6624 (v2i64 VR128:$src2))),
6625 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6626 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6627 (v2f64 VR128:$src2))),
6628 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6631 let Predicates = [HasAVX] in
6632 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6633 "vmovntdqa\t{$src, $dst|$dst, $src}",
6634 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6636 let Predicates = [HasAVX2] in
6637 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
6638 "vmovntdqa\t{$src, $dst|$dst, $src}",
6639 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
6641 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6642 "movntdqa\t{$src, $dst|$dst, $src}",
6643 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6646 //===----------------------------------------------------------------------===//
6647 // SSE4.2 - Compare Instructions
6648 //===----------------------------------------------------------------------===//
6650 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
6651 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
6652 Intrinsic IntId128, bit Is2Addr = 1> {
6653 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
6654 (ins VR128:$src1, VR128:$src2),
6656 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6657 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6658 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
6660 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
6661 (ins VR128:$src1, i128mem:$src2),
6663 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6664 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6666 (IntId128 VR128:$src1,
6667 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
6670 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
6671 multiclass SS42I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6672 Intrinsic IntId256> {
6673 def Yrr : SS428I<opc, MRMSrcReg, (outs VR256:$dst),
6674 (ins VR256:$src1, VR256:$src2),
6675 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6676 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
6678 def Yrm : SS428I<opc, MRMSrcMem, (outs VR256:$dst),
6679 (ins VR256:$src1, i256mem:$src2),
6680 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6682 (IntId256 VR256:$src1,
6683 (bitconvert (memopv32i8 addr:$src2))))]>, OpSize;
6686 let Predicates = [HasAVX] in {
6687 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
6690 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
6691 (VPCMPGTQrr VR128:$src1, VR128:$src2)>;
6692 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
6693 (VPCMPGTQrm VR128:$src1, addr:$src2)>;
6696 let Predicates = [HasAVX2] in {
6697 defm VPCMPGTQ : SS42I_binop_rm_int_y<0x37, "vpcmpgtq", int_x86_avx2_pcmpgt_q>,
6700 def : Pat<(v4i64 (X86pcmpgtq VR256:$src1, VR256:$src2)),
6701 (VPCMPGTQYrr VR256:$src1, VR256:$src2)>;
6702 def : Pat<(v4i64 (X86pcmpgtq VR256:$src1, (memop addr:$src2))),
6703 (VPCMPGTQYrm VR256:$src1, addr:$src2)>;
6706 let Constraints = "$src1 = $dst" in
6707 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
6709 let Predicates = [HasSSE42] in {
6710 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
6711 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
6712 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
6713 (PCMPGTQrm VR128:$src1, addr:$src2)>;
6716 //===----------------------------------------------------------------------===//
6717 // SSE4.2 - String/text Processing Instructions
6718 //===----------------------------------------------------------------------===//
6720 // Packed Compare Implicit Length Strings, Return Mask
6721 multiclass pseudo_pcmpistrm<string asm> {
6722 def REG : PseudoI<(outs VR128:$dst),
6723 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6724 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6726 def MEM : PseudoI<(outs VR128:$dst),
6727 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6728 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6729 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6732 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6733 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
6734 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6737 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1, Predicates = [HasAVX] in {
6738 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6739 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6740 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6742 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6743 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6744 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6747 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
6748 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6749 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6750 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6752 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6753 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6754 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6757 // Packed Compare Explicit Length Strings, Return Mask
6758 multiclass pseudo_pcmpestrm<string asm> {
6759 def REG : PseudoI<(outs VR128:$dst),
6760 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6761 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6762 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6763 def MEM : PseudoI<(outs VR128:$dst),
6764 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6765 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6766 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6769 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6770 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
6771 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6774 let Predicates = [HasAVX],
6775 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6776 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6777 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6778 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6780 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6781 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6782 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6785 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6786 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6787 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6788 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6790 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6791 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6792 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6795 // Packed Compare Implicit Length Strings, Return Index
6796 let Defs = [ECX, EFLAGS] in {
6797 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
6798 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6799 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6800 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6801 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
6802 (implicit EFLAGS)]>, OpSize;
6803 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6804 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6805 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6806 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
6807 (implicit EFLAGS)]>, OpSize;
6811 let Predicates = [HasAVX] in {
6812 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
6814 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
6816 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
6818 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
6820 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
6822 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
6826 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
6827 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
6828 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
6829 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
6830 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
6831 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
6833 // Packed Compare Explicit Length Strings, Return Index
6834 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
6835 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
6836 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6837 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6838 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6839 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
6840 (implicit EFLAGS)]>, OpSize;
6841 def rm : SS42AI<0x61, MRMSrcMem, (outs),
6842 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6843 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6845 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
6846 (implicit EFLAGS)]>, OpSize;
6850 let Predicates = [HasAVX] in {
6851 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
6853 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
6855 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
6857 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
6859 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
6861 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
6865 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
6866 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
6867 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
6868 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
6869 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
6870 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
6872 //===----------------------------------------------------------------------===//
6873 // SSE4.2 - CRC Instructions
6874 //===----------------------------------------------------------------------===//
6876 // No CRC instructions have AVX equivalents
6878 // crc intrinsic instruction
6879 // This set of instructions are only rm, the only difference is the size
6881 let Constraints = "$src1 = $dst" in {
6882 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
6883 (ins GR32:$src1, i8mem:$src2),
6884 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6886 (int_x86_sse42_crc32_32_8 GR32:$src1,
6887 (load addr:$src2)))]>;
6888 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
6889 (ins GR32:$src1, GR8:$src2),
6890 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6892 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
6893 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6894 (ins GR32:$src1, i16mem:$src2),
6895 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6897 (int_x86_sse42_crc32_32_16 GR32:$src1,
6898 (load addr:$src2)))]>,
6900 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6901 (ins GR32:$src1, GR16:$src2),
6902 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6904 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
6906 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6907 (ins GR32:$src1, i32mem:$src2),
6908 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6910 (int_x86_sse42_crc32_32_32 GR32:$src1,
6911 (load addr:$src2)))]>;
6912 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6913 (ins GR32:$src1, GR32:$src2),
6914 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6916 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
6917 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
6918 (ins GR64:$src1, i8mem:$src2),
6919 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6921 (int_x86_sse42_crc32_64_8 GR64:$src1,
6922 (load addr:$src2)))]>,
6924 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
6925 (ins GR64:$src1, GR8:$src2),
6926 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6928 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
6930 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
6931 (ins GR64:$src1, i64mem:$src2),
6932 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6934 (int_x86_sse42_crc32_64_64 GR64:$src1,
6935 (load addr:$src2)))]>,
6937 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
6938 (ins GR64:$src1, GR64:$src2),
6939 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6941 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
6945 //===----------------------------------------------------------------------===//
6946 // AES-NI Instructions
6947 //===----------------------------------------------------------------------===//
6949 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
6950 Intrinsic IntId128, bit Is2Addr = 1> {
6951 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
6952 (ins VR128:$src1, VR128:$src2),
6954 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6955 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6956 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
6958 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
6959 (ins VR128:$src1, i128mem:$src2),
6961 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6962 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6964 (IntId128 VR128:$src1,
6965 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
6968 // Perform One Round of an AES Encryption/Decryption Flow
6969 let Predicates = [HasAVX, HasAES] in {
6970 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
6971 int_x86_aesni_aesenc, 0>, VEX_4V;
6972 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
6973 int_x86_aesni_aesenclast, 0>, VEX_4V;
6974 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
6975 int_x86_aesni_aesdec, 0>, VEX_4V;
6976 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
6977 int_x86_aesni_aesdeclast, 0>, VEX_4V;
6980 let Constraints = "$src1 = $dst" in {
6981 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
6982 int_x86_aesni_aesenc>;
6983 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
6984 int_x86_aesni_aesenclast>;
6985 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
6986 int_x86_aesni_aesdec>;
6987 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
6988 int_x86_aesni_aesdeclast>;
6991 let Predicates = [HasAES] in {
6992 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
6993 (AESENCrr VR128:$src1, VR128:$src2)>;
6994 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
6995 (AESENCrm VR128:$src1, addr:$src2)>;
6996 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
6997 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
6998 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
6999 (AESENCLASTrm VR128:$src1, addr:$src2)>;
7000 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
7001 (AESDECrr VR128:$src1, VR128:$src2)>;
7002 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
7003 (AESDECrm VR128:$src1, addr:$src2)>;
7004 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
7005 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
7006 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
7007 (AESDECLASTrm VR128:$src1, addr:$src2)>;
7010 let Predicates = [HasAVX, HasAES], AddedComplexity = 20 in {
7011 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
7012 (VAESENCrr VR128:$src1, VR128:$src2)>;
7013 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
7014 (VAESENCrm VR128:$src1, addr:$src2)>;
7015 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
7016 (VAESENCLASTrr VR128:$src1, VR128:$src2)>;
7017 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
7018 (VAESENCLASTrm VR128:$src1, addr:$src2)>;
7019 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
7020 (VAESDECrr VR128:$src1, VR128:$src2)>;
7021 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
7022 (VAESDECrm VR128:$src1, addr:$src2)>;
7023 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
7024 (VAESDECLASTrr VR128:$src1, VR128:$src2)>;
7025 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
7026 (VAESDECLASTrm VR128:$src1, addr:$src2)>;
7029 // Perform the AES InvMixColumn Transformation
7030 let Predicates = [HasAVX, HasAES] in {
7031 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7033 "vaesimc\t{$src1, $dst|$dst, $src1}",
7035 (int_x86_aesni_aesimc VR128:$src1))]>,
7037 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7038 (ins i128mem:$src1),
7039 "vaesimc\t{$src1, $dst|$dst, $src1}",
7041 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
7044 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7046 "aesimc\t{$src1, $dst|$dst, $src1}",
7048 (int_x86_aesni_aesimc VR128:$src1))]>,
7050 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7051 (ins i128mem:$src1),
7052 "aesimc\t{$src1, $dst|$dst, $src1}",
7054 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
7057 // AES Round Key Generation Assist
7058 let Predicates = [HasAVX, HasAES] in {
7059 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7060 (ins VR128:$src1, i8imm:$src2),
7061 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7063 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7065 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7066 (ins i128mem:$src1, i8imm:$src2),
7067 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7069 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
7073 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7074 (ins VR128:$src1, i8imm:$src2),
7075 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7077 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7079 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7080 (ins i128mem:$src1, i8imm:$src2),
7081 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7083 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
7087 //===----------------------------------------------------------------------===//
7088 // CLMUL Instructions
7089 //===----------------------------------------------------------------------===//
7091 // Carry-less Multiplication instructions
7092 let neverHasSideEffects = 1 in {
7093 let Constraints = "$src1 = $dst" in {
7094 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7095 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7096 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7100 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7101 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7102 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7106 // AVX carry-less Multiplication instructions
7107 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7108 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7109 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7113 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7114 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7115 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7120 multiclass pclmul_alias<string asm, int immop> {
7121 def : InstAlias<!strconcat("pclmul", asm,
7122 "dq {$src, $dst|$dst, $src}"),
7123 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7125 def : InstAlias<!strconcat("pclmul", asm,
7126 "dq {$src, $dst|$dst, $src}"),
7127 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7129 def : InstAlias<!strconcat("vpclmul", asm,
7130 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7131 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7133 def : InstAlias<!strconcat("vpclmul", asm,
7134 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7135 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7137 defm : pclmul_alias<"hqhq", 0x11>;
7138 defm : pclmul_alias<"hqlq", 0x01>;
7139 defm : pclmul_alias<"lqhq", 0x10>;
7140 defm : pclmul_alias<"lqlq", 0x00>;
7142 //===----------------------------------------------------------------------===//
7144 //===----------------------------------------------------------------------===//
7146 //===----------------------------------------------------------------------===//
7147 // VBROADCAST - Load from memory and broadcast to all elements of the
7148 // destination operand
7150 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7151 X86MemOperand x86memop, Intrinsic Int> :
7152 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7153 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7154 [(set RC:$dst, (Int addr:$src))]>, VEX;
7156 // AVX2 adds register forms
7157 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7159 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7160 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7161 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7163 let ExeDomain = SSEPackedSingle in {
7164 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7165 int_x86_avx_vbroadcast_ss>;
7166 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7167 int_x86_avx_vbroadcast_ss_256>;
7169 let ExeDomain = SSEPackedDouble in
7170 def VBROADCASTSDrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7171 int_x86_avx_vbroadcast_sd_256>;
7172 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7173 int_x86_avx_vbroadcastf128_pd_256>;
7175 let ExeDomain = SSEPackedSingle in {
7176 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7177 int_x86_avx2_vbroadcast_ss_ps>;
7178 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7179 int_x86_avx2_vbroadcast_ss_ps_256>;
7181 let ExeDomain = SSEPackedDouble in
7182 def VBROADCASTSDrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7183 int_x86_avx2_vbroadcast_sd_pd_256>;
7185 let Predicates = [HasAVX2] in
7186 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7187 int_x86_avx2_vbroadcasti128>;
7189 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7190 (VBROADCASTF128 addr:$src)>;
7192 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7193 (VBROADCASTSSYrm addr:$src)>;
7194 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7195 (VBROADCASTSDrm addr:$src)>;
7196 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
7197 (VBROADCASTSSYrm addr:$src)>;
7198 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
7199 (VBROADCASTSDrm addr:$src)>;
7201 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
7202 (VBROADCASTSSrm addr:$src)>;
7203 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7204 (VBROADCASTSSrm addr:$src)>;
7206 //===----------------------------------------------------------------------===//
7207 // VINSERTF128 - Insert packed floating-point values
7209 let neverHasSideEffects = 1 in {
7210 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7211 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7212 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7215 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7216 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7217 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7221 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
7222 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
7223 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
7224 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
7225 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
7226 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
7228 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7230 (VINSERTF128rr VR256:$src1, VR128:$src2,
7231 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7232 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7234 (VINSERTF128rr VR256:$src1, VR128:$src2,
7235 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7236 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7238 (VINSERTF128rr VR256:$src1, VR128:$src2,
7239 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7240 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7242 (VINSERTF128rr VR256:$src1, VR128:$src2,
7243 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7244 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7246 (VINSERTF128rr VR256:$src1, VR128:$src2,
7247 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7248 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7250 (VINSERTF128rr VR256:$src1, VR128:$src2,
7251 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7253 //===----------------------------------------------------------------------===//
7254 // VEXTRACTF128 - Extract packed floating-point values
7256 let neverHasSideEffects = 1 in {
7257 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7258 (ins VR256:$src1, i8imm:$src2),
7259 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7262 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7263 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7264 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7268 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
7269 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7270 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
7271 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7272 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
7273 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7275 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7276 (v4f32 (VEXTRACTF128rr
7277 (v8f32 VR256:$src1),
7278 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7279 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7280 (v2f64 (VEXTRACTF128rr
7281 (v4f64 VR256:$src1),
7282 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7283 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7284 (v4i32 (VEXTRACTF128rr
7285 (v8i32 VR256:$src1),
7286 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7287 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7288 (v2i64 (VEXTRACTF128rr
7289 (v4i64 VR256:$src1),
7290 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7291 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7292 (v8i16 (VEXTRACTF128rr
7293 (v16i16 VR256:$src1),
7294 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7295 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7296 (v16i8 (VEXTRACTF128rr
7297 (v32i8 VR256:$src1),
7298 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7300 //===----------------------------------------------------------------------===//
7301 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7303 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7304 Intrinsic IntLd, Intrinsic IntLd256,
7305 Intrinsic IntSt, Intrinsic IntSt256,
7306 PatFrag pf128, PatFrag pf256> {
7307 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7308 (ins VR128:$src1, f128mem:$src2),
7309 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7310 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7312 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7313 (ins VR256:$src1, f256mem:$src2),
7314 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7315 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7317 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7318 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7319 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7320 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7321 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7322 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7323 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7324 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7327 let ExeDomain = SSEPackedSingle in
7328 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7329 int_x86_avx_maskload_ps,
7330 int_x86_avx_maskload_ps_256,
7331 int_x86_avx_maskstore_ps,
7332 int_x86_avx_maskstore_ps_256,
7333 memopv4f32, memopv8f32>;
7334 let ExeDomain = SSEPackedDouble in
7335 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7336 int_x86_avx_maskload_pd,
7337 int_x86_avx_maskload_pd_256,
7338 int_x86_avx_maskstore_pd,
7339 int_x86_avx_maskstore_pd_256,
7340 memopv2f64, memopv4f64>;
7342 //===----------------------------------------------------------------------===//
7343 // VPERMIL - Permute Single and Double Floating-Point Values
7345 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7346 RegisterClass RC, X86MemOperand x86memop_f,
7347 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
7348 Intrinsic IntVar, Intrinsic IntImm> {
7349 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7350 (ins RC:$src1, RC:$src2),
7351 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7352 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7353 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7354 (ins RC:$src1, x86memop_i:$src2),
7355 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7356 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
7358 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7359 (ins RC:$src1, i8imm:$src2),
7360 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7361 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
7362 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7363 (ins x86memop_f:$src1, i8imm:$src2),
7364 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7365 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
7368 let ExeDomain = SSEPackedSingle in {
7369 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7370 memopv4f32, memopv4i32,
7371 int_x86_avx_vpermilvar_ps,
7372 int_x86_avx_vpermil_ps>;
7373 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7374 memopv8f32, memopv8i32,
7375 int_x86_avx_vpermilvar_ps_256,
7376 int_x86_avx_vpermil_ps_256>;
7378 let ExeDomain = SSEPackedDouble in {
7379 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7380 memopv2f64, memopv2i64,
7381 int_x86_avx_vpermilvar_pd,
7382 int_x86_avx_vpermil_pd>;
7383 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7384 memopv4f64, memopv4i64,
7385 int_x86_avx_vpermilvar_pd_256,
7386 int_x86_avx_vpermil_pd_256>;
7389 def : Pat<(v8f32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
7390 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7391 def : Pat<(v4f64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
7392 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7393 def : Pat<(v8i32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
7394 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7395 def : Pat<(v4i64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
7396 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7398 //===----------------------------------------------------------------------===//
7399 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7401 let neverHasSideEffects = 1 in {
7402 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7403 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7404 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7407 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7408 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7409 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7413 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
7414 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
7415 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
7416 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
7417 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
7418 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
7420 def : Pat<(int_x86_avx_vperm2f128_ps_256
7421 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
7422 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
7423 def : Pat<(int_x86_avx_vperm2f128_pd_256
7424 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
7425 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
7426 def : Pat<(int_x86_avx_vperm2f128_si_256
7427 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
7428 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
7430 def : Pat<(v8f32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7431 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7432 def : Pat<(v8i32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7433 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7434 def : Pat<(v4i64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7435 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7436 def : Pat<(v4f64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7437 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7438 def : Pat<(v32i8 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7439 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7440 def : Pat<(v16i16 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7441 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7443 //===----------------------------------------------------------------------===//
7444 // VZERO - Zero YMM registers
7446 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7447 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7448 // Zero All YMM registers
7449 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7450 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7452 // Zero Upper bits of YMM registers
7453 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7454 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7457 //===----------------------------------------------------------------------===//
7458 // Half precision conversion instructions
7459 //===----------------------------------------------------------------------===//
7460 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7461 let Predicates = [HasAVX, HasF16C] in {
7462 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7463 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7464 [(set RC:$dst, (Int VR128:$src))]>,
7466 let neverHasSideEffects = 1, mayLoad = 1 in
7467 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7468 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7472 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7473 let Predicates = [HasAVX, HasF16C] in {
7474 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7475 (ins RC:$src1, i32i8imm:$src2),
7476 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7477 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7479 let neverHasSideEffects = 1, mayLoad = 1 in
7480 def mr : Ii8<0x1D, MRMDestMem, (outs x86memop:$dst),
7481 (ins RC:$src1, i32i8imm:$src2),
7482 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7487 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7488 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>;
7489 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7490 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>;
7492 //===----------------------------------------------------------------------===//
7493 // AVX2 Instructions
7494 //===----------------------------------------------------------------------===//
7496 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7497 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7498 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7499 X86MemOperand x86memop> {
7500 let isCommutable = 1 in
7501 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7502 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7503 !strconcat(OpcodeStr,
7504 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7505 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7507 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7508 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7509 !strconcat(OpcodeStr,
7510 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7513 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7517 let isCommutable = 0 in {
7518 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7519 VR128, memopv16i8, i128mem>;
7520 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7521 VR256, memopv32i8, i256mem>;
7524 //===----------------------------------------------------------------------===//
7525 // VPBROADCAST - Load from memory and broadcast to all elements of the
7526 // destination operand
7528 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7529 X86MemOperand x86memop, PatFrag ld_frag,
7530 Intrinsic Int128, Intrinsic Int256> {
7531 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7532 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7533 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7534 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7535 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7537 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7538 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7539 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7540 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX;
7541 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7542 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7544 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7547 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7548 int_x86_avx2_pbroadcastb_128,
7549 int_x86_avx2_pbroadcastb_256>;
7550 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7551 int_x86_avx2_pbroadcastw_128,
7552 int_x86_avx2_pbroadcastw_256>;
7553 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7554 int_x86_avx2_pbroadcastd_128,
7555 int_x86_avx2_pbroadcastd_256>;
7556 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7557 int_x86_avx2_pbroadcastq_128,
7558 int_x86_avx2_pbroadcastq_256>;
7560 //===----------------------------------------------------------------------===//
7561 // VPERM - Permute instructions
7564 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7566 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7567 (ins VR256:$src1, VR256:$src2),
7568 !strconcat(OpcodeStr,
7569 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7570 [(set VR256:$dst, (Int VR256:$src1, VR256:$src2))]>, VEX_4V;
7571 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7572 (ins VR256:$src1, i256mem:$src2),
7573 !strconcat(OpcodeStr,
7574 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7575 [(set VR256:$dst, (Int VR256:$src1, (mem_frag addr:$src2)))]>,
7579 defm VPERMD : avx2_perm<0x36, "vpermd", memopv8i32, int_x86_avx2_permd>;
7580 let ExeDomain = SSEPackedSingle in
7581 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, int_x86_avx2_permps>;
7583 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7585 def Yrr : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7586 (ins VR256:$src1, i8imm:$src2),
7587 !strconcat(OpcodeStr,
7588 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7589 [(set VR256:$dst, (Int VR256:$src1, imm:$src2))]>, VEX;
7590 def Yrm : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
7591 (ins i256mem:$src1, i8imm:$src2),
7592 !strconcat(OpcodeStr,
7593 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7594 [(set VR256:$dst, (Int (mem_frag addr:$src1), imm:$src2))]>,
7598 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, int_x86_avx2_permq>,
7600 let ExeDomain = SSEPackedDouble in
7601 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, int_x86_avx2_permpd>,
7604 //===----------------------------------------------------------------------===//
7605 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7607 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7608 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7609 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7611 (int_x86_avx2_vperm2i128 VR256:$src1, VR256:$src2, imm:$src3))]>,
7613 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
7614 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7615 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7617 (int_x86_avx2_vperm2i128 VR256:$src1, (memopv4i64 addr:$src2),
7621 //===----------------------------------------------------------------------===//
7622 // VINSERTI128 - Insert packed integer values
7624 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7625 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7626 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7628 (int_x86_avx2_vinserti128 VR256:$src1, VR128:$src2, imm:$src3))]>,
7630 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
7631 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
7632 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7634 (int_x86_avx2_vinserti128 VR256:$src1, (memopv2i64 addr:$src2),
7635 imm:$src3))]>, VEX_4V;
7637 //===----------------------------------------------------------------------===//
7638 // VEXTRACTI128 - Extract packed integer values
7640 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
7641 (ins VR256:$src1, i8imm:$src2),
7642 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7644 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
7646 let neverHasSideEffects = 1, mayStore = 1 in
7647 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
7648 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
7649 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, VEX;
7651 //===----------------------------------------------------------------------===//
7652 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
7654 multiclass avx2_pmovmask<string OpcodeStr,
7655 Intrinsic IntLd128, Intrinsic IntLd256,
7656 Intrinsic IntSt128, Intrinsic IntSt256,
7657 PatFrag pf128, PatFrag pf256> {
7658 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
7659 (ins VR128:$src1, i128mem:$src2),
7660 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7661 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
7662 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
7663 (ins VR256:$src1, i256mem:$src2),
7664 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7665 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>, VEX_4V;
7666 def mr : AVX28I<0x8e, MRMDestMem, (outs),
7667 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
7668 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7669 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7670 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
7671 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
7672 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7673 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7676 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
7677 int_x86_avx2_maskload_d,
7678 int_x86_avx2_maskload_d_256,
7679 int_x86_avx2_maskstore_d,
7680 int_x86_avx2_maskstore_d_256,
7681 memopv4i32, memopv8i32>;
7682 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
7683 int_x86_avx2_maskload_q,
7684 int_x86_avx2_maskload_q_256,
7685 int_x86_avx2_maskstore_q,
7686 int_x86_avx2_maskstore_q_256,
7687 memopv2i64, memopv4i64>, VEX_W;
7690 //===----------------------------------------------------------------------===//
7691 // Variable Bit Shifts
7693 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr,
7694 Intrinsic Int128, Intrinsic Int256> {
7695 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
7696 (ins VR128:$src1, VR128:$src2),
7697 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7698 [(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2))]>, VEX_4V;
7699 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
7700 (ins VR128:$src1, i128mem:$src2),
7701 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7703 (Int128 VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))]>,
7705 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7706 (ins VR256:$src1, VR256:$src2),
7707 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7708 [(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2))]>, VEX_4V;
7709 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7710 (ins VR256:$src1, i256mem:$src2),
7711 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7713 (Int256 VR256:$src1, (bitconvert (memopv4i64 addr:$src2))))]>,
7717 multiclass avx2_var_shift_i64<bits<8> opc, string OpcodeStr,
7718 Intrinsic Int128, Intrinsic Int256> {
7719 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
7720 (ins VR128:$src1, VR128:$src2),
7721 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7722 [(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2))]>, VEX_4V;
7723 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
7724 (ins VR128:$src1, i128mem:$src2),
7725 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7727 (Int128 VR128:$src1, (memopv2i64 addr:$src2)))]>,
7729 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7730 (ins VR256:$src1, VR256:$src2),
7731 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7732 [(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2))]>, VEX_4V;
7733 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7734 (ins VR256:$src1, i256mem:$src2),
7735 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7737 (Int256 VR256:$src1, (memopv4i64 addr:$src2)))]>,
7741 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", int_x86_avx2_psllv_d,
7742 int_x86_avx2_psllv_d_256>;
7743 defm VPSLLVQ : avx2_var_shift_i64<0x47, "vpsllvq", int_x86_avx2_psllv_q,
7744 int_x86_avx2_psllv_q_256>, VEX_W;
7745 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", int_x86_avx2_psrlv_d,
7746 int_x86_avx2_psrlv_d_256>;
7747 defm VPSRLVQ : avx2_var_shift_i64<0x45, "vpsrlvq", int_x86_avx2_psrlv_q,
7748 int_x86_avx2_psrlv_q_256>, VEX_W;
7749 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", int_x86_avx2_psrav_d,
7750 int_x86_avx2_psrav_d_256>;
7752 let Predicates = [HasAVX2] in {
7753 def : Pat<(v4i32 (shl (v4i32 VR128:$src1), (v4i32 VR128:$src2))),
7754 (VPSLLVDrr VR128:$src1, VR128:$src2)>;
7755 def : Pat<(v2i64 (shl (v2i64 VR128:$src1), (v2i64 VR128:$src2))),
7756 (VPSLLVQrr VR128:$src1, VR128:$src2)>;
7757 def : Pat<(v4i32 (srl (v4i32 VR128:$src1), (v4i32 VR128:$src2))),
7758 (VPSRLVDrr VR128:$src1, VR128:$src2)>;
7759 def : Pat<(v2i64 (srl (v2i64 VR128:$src1), (v2i64 VR128:$src2))),
7760 (VPSRLVQrr VR128:$src1, VR128:$src2)>;
7761 def : Pat<(v4i32 (sra (v4i32 VR128:$src1), (v4i32 VR128:$src2))),
7762 (VPSRAVDrr VR128:$src1, VR128:$src2)>;
7763 def : Pat<(v8i32 (shl (v8i32 VR256:$src1), (v8i32 VR256:$src2))),
7764 (VPSLLVDYrr VR256:$src1, VR256:$src2)>;
7765 def : Pat<(v4i64 (shl (v4i64 VR256:$src1), (v4i64 VR256:$src2))),
7766 (VPSLLVQYrr VR256:$src1, VR256:$src2)>;
7767 def : Pat<(v8i32 (srl (v8i32 VR256:$src1), (v8i32 VR256:$src2))),
7768 (VPSRLVDYrr VR256:$src1, VR256:$src2)>;
7769 def : Pat<(v4i64 (srl (v4i64 VR256:$src1), (v4i64 VR256:$src2))),
7770 (VPSRLVQYrr VR256:$src1, VR256:$src2)>;
7771 def : Pat<(v8i32 (sra (v8i32 VR256:$src1), (v8i32 VR256:$src2))),
7772 (VPSRAVDYrr VR256:$src1, VR256:$src2)>;
7774 def : Pat<(v4i32 (shl (v4i32 VR128:$src1),
7775 (bc_v4i32 (memopv2i64 addr:$src2)))),
7776 (VPSLLVDrm VR128:$src1, addr:$src2)>;
7777 def : Pat<(v2i64 (shl (v2i64 VR128:$src1), (memopv2i64 addr:$src2))),
7778 (VPSLLVQrm VR128:$src1, addr:$src2)>;
7779 def : Pat<(v4i32 (srl (v4i32 VR128:$src1),
7780 (bc_v4i32 (memopv2i64 addr:$src2)))),
7781 (VPSRLVDrm VR128:$src1, addr:$src2)>;
7782 def : Pat<(v2i64 (srl (v2i64 VR128:$src1), (memopv2i64 addr:$src2))),
7783 (VPSRLVQrm VR128:$src1, addr:$src2)>;
7784 def : Pat<(v4i32 (sra (v4i32 VR128:$src1),
7785 (bc_v4i32 (memopv2i64 addr:$src2)))),
7786 (VPSRAVDrm VR128:$src1, addr:$src2)>;
7787 def : Pat<(v8i32 (shl (v8i32 VR256:$src1),
7788 (bc_v8i32 (memopv4i64 addr:$src2)))),
7789 (VPSLLVDYrm VR256:$src1, addr:$src2)>;
7790 def : Pat<(v4i64 (shl (v4i64 VR256:$src1), (memopv4i64 addr:$src2))),
7791 (VPSLLVQYrm VR256:$src1, addr:$src2)>;
7792 def : Pat<(v8i32 (srl (v8i32 VR256:$src1),
7793 (bc_v8i32 (memopv4i64 addr:$src2)))),
7794 (VPSRLVDYrm VR256:$src1, addr:$src2)>;
7795 def : Pat<(v4i64 (srl (v4i64 VR256:$src1), (memopv4i64 addr:$src2))),
7796 (VPSRLVQYrm VR256:$src1, addr:$src2)>;
7797 def : Pat<(v8i32 (sra (v8i32 VR256:$src1),
7798 (bc_v8i32 (memopv4i64 addr:$src2)))),
7799 (VPSRAVDYrm VR256:$src1, addr:$src2)>;