1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pshufb : SDNode<"X86ISD::PSHUFB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
42 def X86pextrb : SDNode<"X86ISD::PEXTRB",
43 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
44 def X86pextrw : SDNode<"X86ISD::PEXTRW",
45 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
46 def X86pinsrb : SDNode<"X86ISD::PINSRB",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86pinsrw : SDNode<"X86ISD::PINSRW",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
52 def X86insrtps : SDNode<"X86ISD::INSERTPS",
53 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
54 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
55 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
56 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
57 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
58 [SDNPHasChain, SDNPMayLoad]>;
59 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
60 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
61 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
62 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
63 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
65 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
66 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
67 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
68 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
69 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
70 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
72 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
75 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
77 //===----------------------------------------------------------------------===//
78 // SSE Complex Patterns
79 //===----------------------------------------------------------------------===//
81 // These are 'extloads' from a scalar to the low element of a vector, zeroing
82 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
84 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
85 [SDNPHasChain, SDNPMayLoad]>;
86 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
87 [SDNPHasChain, SDNPMayLoad]>;
89 def ssmem : Operand<v4f32> {
90 let PrintMethod = "printf32mem";
91 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
92 let ParserMatchClass = X86MemAsmOperand;
94 def sdmem : Operand<v2f64> {
95 let PrintMethod = "printf64mem";
96 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
97 let ParserMatchClass = X86MemAsmOperand;
100 //===----------------------------------------------------------------------===//
101 // SSE pattern fragments
102 //===----------------------------------------------------------------------===//
104 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
105 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
106 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
107 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
109 // Like 'store', but always requires vector alignment.
110 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
111 (store node:$val, node:$ptr), [{
112 return cast<StoreSDNode>(N)->getAlignment() >= 16;
115 // Like 'load', but always requires vector alignment.
116 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
117 return cast<LoadSDNode>(N)->getAlignment() >= 16;
120 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
121 (f32 (alignedload node:$ptr))>;
122 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
123 (f64 (alignedload node:$ptr))>;
124 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
125 (v4f32 (alignedload node:$ptr))>;
126 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
127 (v2f64 (alignedload node:$ptr))>;
128 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
129 (v4i32 (alignedload node:$ptr))>;
130 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
131 (v2i64 (alignedload node:$ptr))>;
133 // Like 'load', but uses special alignment checks suitable for use in
134 // memory operands in most SSE instructions, which are required to
135 // be naturally aligned on some targets but not on others. If the subtarget
136 // allows unaligned accesses, match any load, though this may require
137 // setting a feature bit in the processor (on startup, for example).
138 // Opteron 10h and later implement such a feature.
139 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
140 return Subtarget->hasVectorUAMem()
141 || cast<LoadSDNode>(N)->getAlignment() >= 16;
144 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
145 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
146 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
147 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
148 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
149 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
150 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
152 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
154 // FIXME: 8 byte alignment for mmx reads is not required
155 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
156 return cast<LoadSDNode>(N)->getAlignment() >= 8;
159 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
160 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
161 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
162 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
165 // Like 'store', but requires the non-temporal bit to be set
166 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
167 (st node:$val, node:$ptr), [{
168 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
169 return ST->isNonTemporal();
173 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
174 (st node:$val, node:$ptr), [{
175 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
176 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
177 ST->getAddressingMode() == ISD::UNINDEXED &&
178 ST->getAlignment() >= 16;
182 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
183 (st node:$val, node:$ptr), [{
184 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
185 return ST->isNonTemporal() &&
186 ST->getAlignment() < 16;
190 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
191 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
192 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
193 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
194 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
195 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
197 def vzmovl_v2i64 : PatFrag<(ops node:$src),
198 (bitconvert (v2i64 (X86vzmovl
199 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
200 def vzmovl_v4i32 : PatFrag<(ops node:$src),
201 (bitconvert (v4i32 (X86vzmovl
202 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
204 def vzload_v2i64 : PatFrag<(ops node:$src),
205 (bitconvert (v2i64 (X86vzload node:$src)))>;
208 def fp32imm0 : PatLeaf<(f32 fpimm), [{
209 return N->isExactlyValue(+0.0);
212 // BYTE_imm - Transform bit immediates into byte immediates.
213 def BYTE_imm : SDNodeXForm<imm, [{
214 // Transformation function: imm >> 3
215 return getI32Imm(N->getZExtValue() >> 3);
218 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
220 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
221 return getI8Imm(X86::getShuffleSHUFImmediate(N));
224 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
226 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
227 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
230 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
232 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
233 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
236 // SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to
238 def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{
239 return getI8Imm(X86::getShufflePALIGNRImmediate(N));
242 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
243 (vector_shuffle node:$lhs, node:$rhs), [{
244 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
245 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
248 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
249 (vector_shuffle node:$lhs, node:$rhs), [{
250 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
253 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
254 (vector_shuffle node:$lhs, node:$rhs), [{
255 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
258 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
259 (vector_shuffle node:$lhs, node:$rhs), [{
260 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
263 def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
264 (vector_shuffle node:$lhs, node:$rhs), [{
265 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
268 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
269 (vector_shuffle node:$lhs, node:$rhs), [{
270 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
273 def movl : PatFrag<(ops node:$lhs, node:$rhs),
274 (vector_shuffle node:$lhs, node:$rhs), [{
275 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
278 def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
279 (vector_shuffle node:$lhs, node:$rhs), [{
280 return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
283 def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
284 (vector_shuffle node:$lhs, node:$rhs), [{
285 return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
288 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
289 (vector_shuffle node:$lhs, node:$rhs), [{
290 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
293 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
294 (vector_shuffle node:$lhs, node:$rhs), [{
295 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
298 def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
299 (vector_shuffle node:$lhs, node:$rhs), [{
300 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
303 def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
304 (vector_shuffle node:$lhs, node:$rhs), [{
305 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
308 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
309 (vector_shuffle node:$lhs, node:$rhs), [{
310 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
311 }], SHUFFLE_get_shuf_imm>;
313 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
314 (vector_shuffle node:$lhs, node:$rhs), [{
315 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
316 }], SHUFFLE_get_shuf_imm>;
318 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
319 (vector_shuffle node:$lhs, node:$rhs), [{
320 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
321 }], SHUFFLE_get_pshufhw_imm>;
323 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
324 (vector_shuffle node:$lhs, node:$rhs), [{
325 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
326 }], SHUFFLE_get_pshuflw_imm>;
328 def palign : PatFrag<(ops node:$lhs, node:$rhs),
329 (vector_shuffle node:$lhs, node:$rhs), [{
330 return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
331 }], SHUFFLE_get_palign_imm>;
333 //===----------------------------------------------------------------------===//
334 // SSE scalar FP Instructions
335 //===----------------------------------------------------------------------===//
337 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
338 // instruction selection into a branch sequence.
339 let Uses = [EFLAGS], usesCustomInserter = 1 in {
340 def CMOV_FR32 : I<0, Pseudo,
341 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
342 "#CMOV_FR32 PSEUDO!",
343 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
345 def CMOV_FR64 : I<0, Pseudo,
346 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
347 "#CMOV_FR64 PSEUDO!",
348 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
350 def CMOV_V4F32 : I<0, Pseudo,
351 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
352 "#CMOV_V4F32 PSEUDO!",
354 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
356 def CMOV_V2F64 : I<0, Pseudo,
357 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
358 "#CMOV_V2F64 PSEUDO!",
360 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
362 def CMOV_V2I64 : I<0, Pseudo,
363 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
364 "#CMOV_V2I64 PSEUDO!",
366 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
370 //===----------------------------------------------------------------------===//
372 //===----------------------------------------------------------------------===//
374 // Move Instructions. Register-to-register movss is not used for FR32
375 // register copies because it's a partial register update; FsMOVAPSrr is
376 // used instead. Register-to-register movss is not modeled as an INSERT_SUBREG
377 // because INSERT_SUBREG requires that the insert be implementable in terms of
378 // a copy, and just mentioned, we don't use movss for copies.
379 let Constraints = "$src1 = $dst" in
380 def MOVSSrr : SSI<0x10, MRMSrcReg,
381 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
382 "movss\t{$src2, $dst|$dst, $src2}",
383 [(set (v4f32 VR128:$dst),
384 (movl VR128:$src1, (scalar_to_vector FR32:$src2)))]>;
386 // Extract the low 32-bit value from one vector and insert it into another.
387 let AddedComplexity = 15 in
388 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
389 (MOVSSrr (v4f32 VR128:$src1),
390 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
392 // Implicitly promote a 32-bit scalar to a vector.
393 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
394 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
396 // Loading from memory automatically zeroing upper bits.
397 let canFoldAsLoad = 1, isReMaterializable = 1 in
398 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
399 "movss\t{$src, $dst|$dst, $src}",
400 [(set FR32:$dst, (loadf32 addr:$src))]>;
402 // MOVSSrm zeros the high parts of the register; represent this
403 // with SUBREG_TO_REG.
404 let AddedComplexity = 20 in {
405 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
406 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
407 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
408 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
409 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
410 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
413 // Store scalar value to memory.
414 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
415 "movss\t{$src, $dst|$dst, $src}",
416 [(store FR32:$src, addr:$dst)]>;
418 // Extract and store.
419 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
422 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
424 // Conversion instructions
425 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
426 "cvttss2si\t{$src, $dst|$dst, $src}",
427 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
428 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
429 "cvttss2si\t{$src, $dst|$dst, $src}",
430 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
431 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
432 "cvtsi2ss\t{$src, $dst|$dst, $src}",
433 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
434 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
435 "cvtsi2ss\t{$src, $dst|$dst, $src}",
436 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
438 // Match intrinsics which expect XMM operand(s).
439 def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
440 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
441 def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
442 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
444 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
445 "cvtss2si\t{$src, $dst|$dst, $src}",
446 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
447 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
448 "cvtss2si\t{$src, $dst|$dst, $src}",
449 [(set GR32:$dst, (int_x86_sse_cvtss2si
450 (load addr:$src)))]>;
452 // Match intrinsics which expect MM and XMM operand(s).
453 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
454 "cvtps2pi\t{$src, $dst|$dst, $src}",
455 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
456 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
457 "cvtps2pi\t{$src, $dst|$dst, $src}",
458 [(set VR64:$dst, (int_x86_sse_cvtps2pi
459 (load addr:$src)))]>;
460 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
461 "cvttps2pi\t{$src, $dst|$dst, $src}",
462 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
463 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
464 "cvttps2pi\t{$src, $dst|$dst, $src}",
465 [(set VR64:$dst, (int_x86_sse_cvttps2pi
466 (load addr:$src)))]>;
467 let Constraints = "$src1 = $dst" in {
468 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
469 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
470 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
471 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
473 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
474 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
475 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
476 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
477 (load addr:$src2)))]>;
480 // Aliases for intrinsics
481 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
482 "cvttss2si\t{$src, $dst|$dst, $src}",
484 (int_x86_sse_cvttss2si VR128:$src))]>;
485 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
486 "cvttss2si\t{$src, $dst|$dst, $src}",
488 (int_x86_sse_cvttss2si(load addr:$src)))]>;
490 let Constraints = "$src1 = $dst" in {
491 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
492 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
493 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
494 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
496 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
497 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
498 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
499 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
500 (loadi32 addr:$src2)))]>;
503 // Comparison instructions
504 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
505 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
506 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
507 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
509 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
510 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
511 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
513 // Accept explicit immediate argument form instead of comparison code.
514 let isAsmParserOnly = 1 in {
515 def CMPSSrr_alt : SSIi8<0xC2, MRMSrcReg,
516 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
517 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
519 def CMPSSrm_alt : SSIi8<0xC2, MRMSrcMem,
520 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
521 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
525 let Defs = [EFLAGS] in {
526 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
527 "ucomiss\t{$src2, $src1|$src1, $src2}",
528 [(set EFLAGS, (X86cmp FR32:$src1, FR32:$src2))]>;
529 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
530 "ucomiss\t{$src2, $src1|$src1, $src2}",
531 [(set EFLAGS, (X86cmp FR32:$src1, (loadf32 addr:$src2)))]>;
533 def COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
534 "comiss\t{$src2, $src1|$src1, $src2}", []>;
535 def COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
536 "comiss\t{$src2, $src1|$src1, $src2}", []>;
540 // Aliases to match intrinsics which expect XMM operand(s).
541 let Constraints = "$src1 = $dst" in {
542 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
544 (ins VR128:$src1, VR128:$src, SSECC:$cc),
545 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
546 [(set VR128:$dst, (int_x86_sse_cmp_ss
548 VR128:$src, imm:$cc))]>;
549 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
551 (ins VR128:$src1, f32mem:$src, SSECC:$cc),
552 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
553 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
554 (load addr:$src), imm:$cc))]>;
557 let Defs = [EFLAGS] in {
558 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
559 "ucomiss\t{$src2, $src1|$src1, $src2}",
560 [(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
562 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
563 "ucomiss\t{$src2, $src1|$src1, $src2}",
564 [(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
565 (load addr:$src2)))]>;
567 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
568 "comiss\t{$src2, $src1|$src1, $src2}",
569 [(set EFLAGS, (X86comi (v4f32 VR128:$src1),
571 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
572 "comiss\t{$src2, $src1|$src1, $src2}",
573 [(set EFLAGS, (X86comi (v4f32 VR128:$src1),
574 (load addr:$src2)))]>;
577 // Aliases of packed SSE1 instructions for scalar use. These all have names
578 // that start with 'Fs'.
580 // Alias instructions that map fld0 to pxor for sse.
581 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
583 // FIXME: Set encoding to pseudo!
584 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
585 [(set FR32:$dst, fp32imm0)]>,
586 Requires<[HasSSE1]>, TB, OpSize;
588 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
590 let neverHasSideEffects = 1 in
591 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
592 "movaps\t{$src, $dst|$dst, $src}", []>;
594 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
596 let canFoldAsLoad = 1, isReMaterializable = 1 in
597 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
598 "movaps\t{$src, $dst|$dst, $src}",
599 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
601 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
603 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
604 SDNode OpNode, int NoPat = 0,
605 bit MayLoad = 0, bit Commutable = 1> {
606 def PSrr : PSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
607 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
609 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))])> {
610 let isCommutable = Commutable;
613 def PDrr : PDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
614 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
616 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))])> {
617 let isCommutable = Commutable;
620 def PSrm : PSI<opc, MRMSrcMem, (outs FR32:$dst),
621 (ins FR32:$src1, f128mem:$src2),
622 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
624 [(set FR32:$dst, (OpNode FR32:$src1,
625 (memopfsf32 addr:$src2)))])> {
626 let mayLoad = MayLoad;
629 def PDrm : PDI<opc, MRMSrcMem, (outs FR64:$dst),
630 (ins FR64:$src1, f128mem:$src2),
631 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
633 [(set FR64:$dst, (OpNode FR64:$src1,
634 (memopfsf64 addr:$src2)))])> {
635 let mayLoad = MayLoad;
639 // Alias bitwise logical operations using SSE logical ops on packed FP values.
640 let Constraints = "$src1 = $dst" in {
641 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
642 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
643 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
645 let neverHasSideEffects = 1 in
646 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef, 1, 1, 0>;
649 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
650 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
651 RegisterClass RC, X86MemOperand memop> {
652 let isCommutable = 1 in {
653 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
654 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
656 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memop:$src2),
657 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
660 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
661 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
662 RegisterClass RC, ValueType vt,
663 X86MemOperand x86memop, PatFrag mem_frag,
665 let isCommutable = 1 in
666 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
667 OpcodeStr, [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))],d>;
668 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
669 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1,
670 (mem_frag addr:$src2)))],d>;
673 /// basic_sse12_fp_binop_rm - SSE 1 & 2 binops come in both scalar and
676 /// In addition, we also have a special variant of the scalar form here to
677 /// represent the associated intrinsic operation. This form is unlike the
678 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
679 /// and leaves the top elements unmodified (therefore these cannot be commuted).
681 /// These three forms can each be reg+reg or reg+mem, so there are a total of
682 /// six "instructions".
684 let Constraints = "$src1 = $dst" in {
685 multiclass basic_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
686 SDNode OpNode, bit Commutable = 0> {
688 let Constraints = "", isAsmParserOnly = 1 in {
689 defm V#NAME#SS : sse12_fp_scalar<opc,
690 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
691 OpNode, FR32, f32mem>, XS, VEX_4V;
693 defm V#NAME#SD : sse12_fp_scalar<opc,
694 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
695 OpNode, FR64, f64mem>, XD, VEX_4V;
697 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
698 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
699 VR128, v4f32, f128mem, memopv4f32, SSEPackedSingle>,
702 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
703 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
704 VR128, v2f64, f128mem, memopv2f64, SSEPackedDouble>,
708 let Constraints = "$src1 = $dst" in {
709 defm SS : sse12_fp_scalar<opc,
710 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
711 OpNode, FR32, f32mem>, XS;
713 defm SD : sse12_fp_scalar<opc,
714 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
715 OpNode, FR64, f64mem>, XD;
717 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
718 "ps\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v4f32,
719 f128mem, memopv4f32, SSEPackedSingle>, TB;
721 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
722 "pd\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v2f64,
723 f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
726 // Intrinsic operation, reg+reg.
727 def V#NAME#SSrr_Int : VSSI<opc, MRMSrcReg, (outs VR128:$dst),
728 (ins VR128:$src1, VR128:$src2),
729 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
730 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse_",
731 !strconcat(OpcodeStr, "_ss")) VR128:$src1,
733 // int_x86_sse_xxx_ss
734 let Constraints = "";
737 def V#NAME#SDrr_Int : VSDI<opc, MRMSrcReg, (outs VR128:$dst),
738 (ins VR128:$src1, VR128:$src2),
739 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
740 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse2_",
741 !strconcat(OpcodeStr, "_sd")) VR128:$src1,
743 // int_x86_sse2_xxx_sd
744 let Constraints = "";
747 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
748 (ins VR128:$src1, VR128:$src2),
749 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
750 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse_",
751 !strconcat(OpcodeStr, "_ss")) VR128:$src1,
753 // int_x86_sse_xxx_ss
755 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
756 (ins VR128:$src1, VR128:$src2),
757 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
758 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse2_",
759 !strconcat(OpcodeStr, "_sd")) VR128:$src1,
761 // int_x86_sse2_xxx_sd
763 // Intrinsic operation, reg+mem.
764 def V#NAME#SSrm_Int : VSSI<opc, MRMSrcMem, (outs VR128:$dst),
765 (ins VR128:$src1, ssmem:$src2),
766 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
767 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse_",
768 !strconcat(OpcodeStr, "_ss")) VR128:$src1,
769 sse_load_f32:$src2))]> {
770 // int_x86_sse_xxx_ss
771 let Constraints = "";
774 def V#NAME#SDrm_Int : VSDI<opc, MRMSrcMem, (outs VR128:$dst),
775 (ins VR128:$src1, sdmem:$src2),
776 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
777 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse2_",
778 !strconcat(OpcodeStr, "_sd")) VR128:$src1,
779 sse_load_f64:$src2))]> {
780 // int_x86_sse2_xxx_sd
781 let Constraints = "";
784 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
785 (ins VR128:$src1, ssmem:$src2),
786 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
787 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse_",
788 !strconcat(OpcodeStr, "_ss")) VR128:$src1,
789 sse_load_f32:$src2))]>;
790 // int_x86_sse_xxx_ss
792 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
793 (ins VR128:$src1, sdmem:$src2),
794 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
795 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse2_",
796 !strconcat(OpcodeStr, "_sd")) VR128:$src1,
797 sse_load_f64:$src2))]>;
798 // int_x86_sse2_xxx_sd
802 // Arithmetic instructions
803 defm ADD : basic_sse12_fp_binop_rm<0x58, "add", fadd, 1>;
804 defm MUL : basic_sse12_fp_binop_rm<0x59, "mul", fmul, 1>;
806 let isCommutable = 0 in {
807 defm SUB : basic_sse12_fp_binop_rm<0x5C, "sub", fsub>;
808 defm DIV : basic_sse12_fp_binop_rm<0x5E, "div", fdiv>;
811 /// sse12_fp_binop_rm - Other SSE 1 & 2 binops
813 /// This multiclass is like basic_sse12_fp_binop_rm, with the addition of
814 /// instructions for a full-vector intrinsic form. Operations that map
815 /// onto C operators don't use this form since they just use the plain
816 /// vector form instead of having a separate vector intrinsic form.
818 /// This provides a total of eight "instructions".
820 let Constraints = "$src1 = $dst" in {
821 multiclass sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
822 SDNode OpNode, bit Commutable = 0> {
824 let Constraints = "", isAsmParserOnly = 1 in {
825 // Scalar operation, reg+reg.
826 defm V#NAME#SS : sse12_fp_scalar<opc,
827 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
828 OpNode, FR32, f32mem>, XS, VEX_4V;
830 defm V#NAME#SD : sse12_fp_scalar<opc,
831 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
832 OpNode, FR64, f64mem>, XD, VEX_4V;
835 let Constraints = "$src1 = $dst" in {
836 // Scalar operation, reg+reg.
837 defm SS : sse12_fp_scalar<opc,
838 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
839 OpNode, FR32, f32mem>, XS;
840 defm SD : sse12_fp_scalar<opc,
841 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
842 OpNode, FR64, f64mem>, XD;
845 // Vector operation, reg+reg.
846 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
847 (ins VR128:$src1, VR128:$src2),
848 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
849 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
850 let isCommutable = Commutable;
853 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
854 (ins VR128:$src1, VR128:$src2),
855 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
856 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
857 let isCommutable = Commutable;
860 // Vector operation, reg+mem.
861 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
862 (ins VR128:$src1, f128mem:$src2),
863 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
864 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
866 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
867 (ins VR128:$src1, f128mem:$src2),
868 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
869 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
871 // Intrinsic operation, reg+reg.
872 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
873 (ins VR128:$src1, VR128:$src2),
874 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
875 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse_",
876 !strconcat(OpcodeStr, "_ss")) VR128:$src1,
878 // int_x86_sse_xxx_ss
879 let isCommutable = Commutable;
882 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
883 (ins VR128:$src1, VR128:$src2),
884 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
885 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse2_",
886 !strconcat(OpcodeStr, "_sd")) VR128:$src1,
888 // int_x86_sse2_xxx_sd
889 let isCommutable = Commutable;
892 // Intrinsic operation, reg+mem.
893 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
894 (ins VR128:$src1, ssmem:$src2),
895 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
896 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse_",
897 !strconcat(OpcodeStr, "_ss")) VR128:$src1,
898 sse_load_f32:$src2))]>;
899 // int_x86_sse_xxx_ss
901 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
902 (ins VR128:$src1, sdmem:$src2),
903 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
904 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse2_",
905 !strconcat(OpcodeStr, "_sd")) VR128:$src1,
906 sse_load_f64:$src2))]>;
907 // int_x86_sse2_xxx_sd
909 // Vector intrinsic operation, reg+reg.
910 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
911 (ins VR128:$src1, VR128:$src2),
912 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
913 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse_",
914 !strconcat(OpcodeStr, "_ps")) VR128:$src1,
916 // int_x86_sse_xxx_ps
917 let isCommutable = Commutable;
920 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
921 (ins VR128:$src1, VR128:$src2),
922 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
923 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse2_",
924 !strconcat(OpcodeStr, "_pd")) VR128:$src1,
926 // int_x86_sse2_xxx_pd
927 let isCommutable = Commutable;
930 // Vector intrinsic operation, reg+mem.
931 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
932 (ins VR128:$src1, f128mem:$src2),
933 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
934 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse_",
935 !strconcat(OpcodeStr, "_ps")) VR128:$src1,
936 (memopv4f32 addr:$src2)))]>;
937 // int_x86_sse_xxx_ps
939 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
940 (ins VR128:$src1, f128mem:$src2),
941 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
942 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse2_",
943 !strconcat(OpcodeStr, "_pd")) VR128:$src1,
944 (memopv2f64 addr:$src2)))]>;
945 // int_x86_sse2_xxx_pd
949 let isCommutable = 0 in {
950 defm MAX : sse12_fp_binop_rm<0x5F, "max", X86fmax>;
951 defm MIN : sse12_fp_binop_rm<0x5D, "min", X86fmin>;
954 //===----------------------------------------------------------------------===//
955 // SSE packed FP Instructions
958 let neverHasSideEffects = 1 in
959 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
960 "movaps\t{$src, $dst|$dst, $src}", []>;
961 let canFoldAsLoad = 1, isReMaterializable = 1 in
962 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
963 "movaps\t{$src, $dst|$dst, $src}",
964 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
966 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
967 "movaps\t{$src, $dst|$dst, $src}",
968 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
970 let neverHasSideEffects = 1 in
971 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
972 "movups\t{$src, $dst|$dst, $src}", []>;
973 let canFoldAsLoad = 1, isReMaterializable = 1 in
974 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
975 "movups\t{$src, $dst|$dst, $src}",
976 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
977 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
978 "movups\t{$src, $dst|$dst, $src}",
979 [(store (v4f32 VR128:$src), addr:$dst)]>;
981 // Intrinsic forms of MOVUPS load and store
982 let canFoldAsLoad = 1, isReMaterializable = 1 in
983 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
984 "movups\t{$src, $dst|$dst, $src}",
985 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
986 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
987 "movups\t{$src, $dst|$dst, $src}",
988 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
990 let Constraints = "$src1 = $dst" in {
991 let AddedComplexity = 20 in {
992 def MOVLPSrm : PSI<0x12, MRMSrcMem,
993 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
994 "movlps\t{$src2, $dst|$dst, $src2}",
997 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
998 def MOVHPSrm : PSI<0x16, MRMSrcMem,
999 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1000 "movhps\t{$src2, $dst|$dst, $src2}",
1002 (movlhps VR128:$src1,
1003 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
1004 } // AddedComplexity
1005 } // Constraints = "$src1 = $dst"
1008 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1009 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1011 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1012 "movlps\t{$src, $dst|$dst, $src}",
1013 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1014 (iPTR 0))), addr:$dst)]>;
1016 // v2f64 extract element 1 is always custom lowered to unpack high to low
1017 // and extract element 0 so the non-store version isn't too horrible.
1018 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1019 "movhps\t{$src, $dst|$dst, $src}",
1020 [(store (f64 (vector_extract
1021 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1022 (undef)), (iPTR 0))), addr:$dst)]>;
1024 let Constraints = "$src1 = $dst" in {
1025 let AddedComplexity = 20 in {
1026 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1027 (ins VR128:$src1, VR128:$src2),
1028 "movlhps\t{$src2, $dst|$dst, $src2}",
1030 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
1032 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1033 (ins VR128:$src1, VR128:$src2),
1034 "movhlps\t{$src2, $dst|$dst, $src2}",
1036 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
1037 } // AddedComplexity
1038 } // Constraints = "$src1 = $dst"
1040 let AddedComplexity = 20 in {
1041 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1042 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1043 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1044 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1051 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
1053 /// In addition, we also have a special variant of the scalar form here to
1054 /// represent the associated intrinsic operation. This form is unlike the
1055 /// plain scalar form, in that it takes an entire vector (instead of a
1056 /// scalar) and leaves the top elements undefined.
1058 /// And, we have a special variant form for a full-vector intrinsic form.
1060 /// These four forms can each have a reg or a mem operand, so there are a
1061 /// total of eight "instructions".
1063 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
1067 bit Commutable = 0> {
1068 // Scalar operation, reg.
1069 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1070 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1071 [(set FR32:$dst, (OpNode FR32:$src))]> {
1072 let isCommutable = Commutable;
1075 // Scalar operation, mem.
1076 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1077 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1078 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1079 Requires<[HasSSE1, OptForSize]>;
1081 // Vector operation, reg.
1082 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1083 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1084 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
1085 let isCommutable = Commutable;
1088 // Vector operation, mem.
1089 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1090 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1091 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1093 // Intrinsic operation, reg.
1094 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1095 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1096 [(set VR128:$dst, (F32Int VR128:$src))]> {
1097 let isCommutable = Commutable;
1100 // Intrinsic operation, mem.
1101 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1102 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1103 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1105 // Vector intrinsic operation, reg
1106 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1107 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1108 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
1109 let isCommutable = Commutable;
1112 // Vector intrinsic operation, mem
1113 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1114 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1115 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1119 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
1120 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
1122 // Reciprocal approximations. Note that these typically require refinement
1123 // in order to obtain suitable precision.
1124 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
1125 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
1126 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
1127 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
1129 /// sse12_fp_pack_logical - SSE 1 & 2 packed FP logical ops
1131 multiclass sse12_fp_pack_logical<bits<8> opc, string OpcodeStr,
1132 SDNode OpNode, int HasPat = 0,
1134 list<list<dag>> Pattern = []> {
1135 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
1136 (ins VR128:$src1, VR128:$src2),
1137 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
1138 !if(HasPat, Pattern[0],
1139 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1141 { let isCommutable = Commutable; }
1143 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1144 (ins VR128:$src1, VR128:$src2),
1145 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1146 !if(HasPat, Pattern[1],
1147 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1148 (bc_v2i64 (v2f64 VR128:$src2))))])>
1149 { let isCommutable = Commutable; }
1151 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
1152 (ins VR128:$src1, f128mem:$src2),
1153 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
1154 !if(HasPat, Pattern[2],
1155 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1156 (memopv2i64 addr:$src2)))])>;
1158 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1159 (ins VR128:$src1, f128mem:$src2),
1160 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1161 !if(HasPat, Pattern[3],
1162 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1163 (memopv2i64 addr:$src2)))])>;
1167 let Constraints = "$src1 = $dst" in {
1168 defm AND : sse12_fp_pack_logical<0x54, "and", and>;
1169 defm OR : sse12_fp_pack_logical<0x56, "or", or>;
1170 defm XOR : sse12_fp_pack_logical<0x57, "xor", xor>;
1171 defm ANDN : sse12_fp_pack_logical<0x55, "andn", undef /* dummy */, 1, 0, [
1173 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1174 (bc_v2i64 (v4i32 immAllOnesV))),
1177 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1178 (bc_v2i64 (v2f64 VR128:$src2))))],
1180 [(set VR128:$dst, (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
1181 (bc_v2i64 (v4i32 immAllOnesV))),
1182 (memopv2i64 addr:$src2))))],
1184 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1185 (memopv2i64 addr:$src2)))]]>;
1188 let Constraints = "$src1 = $dst" in {
1189 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
1190 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1191 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1192 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1193 VR128:$src, imm:$cc))]>;
1194 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
1195 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1196 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1197 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1198 (memop addr:$src), imm:$cc))]>;
1200 // Accept explicit immediate argument form instead of comparison code.
1201 let isAsmParserOnly = 1 in {
1202 def CMPPSrri_alt : PSIi8<0xC2, MRMSrcReg,
1203 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, i8imm:$src2),
1204 "cmpps\t{$src2, $src, $dst|$dst, $src, $src}", []>;
1205 def CMPPSrmi_alt : PSIi8<0xC2, MRMSrcMem,
1206 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, i8imm:$src2),
1207 "cmpps\t{$src2, $src, $dst|$dst, $src, $src}", []>;
1210 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1211 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1212 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1213 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1215 // Shuffle and unpack instructions
1216 let Constraints = "$src1 = $dst" in {
1217 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
1218 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
1219 (outs VR128:$dst), (ins VR128:$src1,
1220 VR128:$src2, i8imm:$src3),
1221 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1223 (v4f32 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1224 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
1225 (outs VR128:$dst), (ins VR128:$src1,
1226 f128mem:$src2, i8imm:$src3),
1227 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1230 VR128:$src1, (memopv4f32 addr:$src2))))]>;
1232 let AddedComplexity = 10 in {
1233 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1234 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1235 "unpckhps\t{$src2, $dst|$dst, $src2}",
1237 (v4f32 (unpckh VR128:$src1, VR128:$src2)))]>;
1238 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1239 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1240 "unpckhps\t{$src2, $dst|$dst, $src2}",
1242 (v4f32 (unpckh VR128:$src1,
1243 (memopv4f32 addr:$src2))))]>;
1245 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1246 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1247 "unpcklps\t{$src2, $dst|$dst, $src2}",
1249 (v4f32 (unpckl VR128:$src1, VR128:$src2)))]>;
1250 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1251 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1252 "unpcklps\t{$src2, $dst|$dst, $src2}",
1254 (unpckl VR128:$src1, (memopv4f32 addr:$src2)))]>;
1255 } // AddedComplexity
1256 } // Constraints = "$src1 = $dst"
1259 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1260 "movmskps\t{$src, $dst|$dst, $src}",
1261 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
1262 def MOVMSKPDrr : PDI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1263 "movmskpd\t{$src, $dst|$dst, $src}",
1264 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
1266 // Prefetch intrinsic.
1267 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
1268 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
1269 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
1270 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
1271 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
1272 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
1273 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
1274 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
1276 // Non-temporal stores
1277 def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1278 "movntps\t{$src, $dst|$dst, $src}",
1279 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
1281 let AddedComplexity = 400 in { // Prefer non-temporal versions
1282 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1283 "movntps\t{$src, $dst|$dst, $src}",
1284 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1286 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1287 "movntdq\t{$src, $dst|$dst, $src}",
1288 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
1290 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1291 "movnti\t{$src, $dst|$dst, $src}",
1292 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
1293 TB, Requires<[HasSSE2]>;
1295 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1296 "movnti\t{$src, $dst|$dst, $src}",
1297 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
1298 TB, Requires<[HasSSE2]>;
1301 // Load, store, and memory fence
1302 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
1303 TB, Requires<[HasSSE1]>;
1306 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
1307 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
1308 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
1309 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
1311 // Alias instructions that map zero vector to pxor / xorp* for sse.
1312 // We set canFoldAsLoad because this can be converted to a constant-pool
1313 // load of an all-zeros value if folding it would be beneficial.
1314 // FIXME: Change encoding to pseudo!
1315 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
1316 isCodeGenOnly = 1 in {
1317 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1318 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
1319 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1320 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
1321 let ExeDomain = SSEPackedInt in
1322 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
1323 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
1326 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
1327 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
1328 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
1330 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1331 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1333 //===---------------------------------------------------------------------===//
1334 // SSE2 Instructions
1335 //===---------------------------------------------------------------------===//
1337 // Move Instructions. Register-to-register movsd is not used for FR64
1338 // register copies because it's a partial register update; FsMOVAPDrr is
1339 // used instead. Register-to-register movsd is not modeled as an INSERT_SUBREG
1340 // because INSERT_SUBREG requires that the insert be implementable in terms of
1341 // a copy, and just mentioned, we don't use movsd for copies.
1342 let Constraints = "$src1 = $dst" in
1343 def MOVSDrr : SDI<0x10, MRMSrcReg,
1344 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
1345 "movsd\t{$src2, $dst|$dst, $src2}",
1346 [(set (v2f64 VR128:$dst),
1347 (movl VR128:$src1, (scalar_to_vector FR64:$src2)))]>;
1349 // Extract the low 64-bit value from one vector and insert it into another.
1350 let AddedComplexity = 15 in
1351 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
1352 (MOVSDrr (v2f64 VR128:$src1),
1353 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
1355 // Implicitly promote a 64-bit scalar to a vector.
1356 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
1357 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
1359 // Loading from memory automatically zeroing upper bits.
1360 let canFoldAsLoad = 1, isReMaterializable = 1, AddedComplexity = 20 in
1361 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1362 "movsd\t{$src, $dst|$dst, $src}",
1363 [(set FR64:$dst, (loadf64 addr:$src))]>;
1365 // MOVSDrm zeros the high parts of the register; represent this
1366 // with SUBREG_TO_REG.
1367 let AddedComplexity = 20 in {
1368 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1369 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1370 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1371 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1372 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1373 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1374 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1375 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1376 def : Pat<(v2f64 (X86vzload addr:$src)),
1377 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1380 // Store scalar value to memory.
1381 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1382 "movsd\t{$src, $dst|$dst, $src}",
1383 [(store FR64:$src, addr:$dst)]>;
1385 // Extract and store.
1386 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
1389 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
1391 // Conversion instructions
1392 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1393 "cvttsd2si\t{$src, $dst|$dst, $src}",
1394 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1395 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1396 "cvttsd2si\t{$src, $dst|$dst, $src}",
1397 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1398 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1399 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1400 [(set FR32:$dst, (fround FR64:$src))]>;
1401 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1402 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1403 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1404 Requires<[HasSSE2, OptForSize]>;
1405 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1406 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1407 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1408 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1409 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1410 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1412 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1413 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1414 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1415 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1416 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1417 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1418 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1419 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1420 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1421 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1422 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1423 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1424 def CVTDQ2PSrr : PSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1425 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1426 def CVTDQ2PSrm : PSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1427 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1428 def COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1429 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1430 def COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1431 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1433 // SSE2 instructions with XS prefix
1434 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1435 "cvtss2sd\t{$src, $dst|$dst, $src}",
1436 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1437 Requires<[HasSSE2]>;
1438 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1439 "cvtss2sd\t{$src, $dst|$dst, $src}",
1440 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1441 Requires<[HasSSE2, OptForSize]>;
1443 def : Pat<(extloadf32 addr:$src),
1444 (CVTSS2SDrr (MOVSSrm addr:$src))>,
1445 Requires<[HasSSE2, OptForSpeed]>;
1447 // Match intrinsics which expect XMM operand(s).
1448 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1449 "cvtsd2si\t{$src, $dst|$dst, $src}",
1450 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1451 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1452 "cvtsd2si\t{$src, $dst|$dst, $src}",
1453 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1454 (load addr:$src)))]>;
1456 // Match intrinsics which expect MM and XMM operand(s).
1457 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1458 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1459 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1460 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1461 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1462 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1463 (memop addr:$src)))]>;
1464 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1465 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1466 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1467 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1468 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1469 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1470 (memop addr:$src)))]>;
1471 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1472 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1473 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1474 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1475 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1476 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1477 (load addr:$src)))]>;
1479 // Aliases for intrinsics
1480 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1481 "cvttsd2si\t{$src, $dst|$dst, $src}",
1483 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1484 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1485 "cvttsd2si\t{$src, $dst|$dst, $src}",
1486 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1487 (load addr:$src)))]>;
1489 // Comparison instructions
1490 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1491 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1492 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1493 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1495 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1496 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1497 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1499 // Accept explicit immediate argument form instead of comparison code.
1500 let isAsmParserOnly = 1 in {
1501 def CMPSDrr_alt : SDIi8<0xC2, MRMSrcReg,
1502 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
1503 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
1505 def CMPSDrm_alt : SDIi8<0xC2, MRMSrcMem,
1506 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
1507 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
1511 let Defs = [EFLAGS] in {
1512 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1513 "ucomisd\t{$src2, $src1|$src1, $src2}",
1514 [(set EFLAGS, (X86cmp FR64:$src1, FR64:$src2))]>;
1515 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1516 "ucomisd\t{$src2, $src1|$src1, $src2}",
1517 [(set EFLAGS, (X86cmp FR64:$src1, (loadf64 addr:$src2)))]>;
1518 } // Defs = [EFLAGS]
1520 // Aliases to match intrinsics which expect XMM operand(s).
1521 let Constraints = "$src1 = $dst" in {
1522 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1524 (ins VR128:$src1, VR128:$src, SSECC:$cc),
1525 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1526 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1527 VR128:$src, imm:$cc))]>;
1528 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1530 (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1531 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1532 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1533 (load addr:$src), imm:$cc))]>;
1536 let Defs = [EFLAGS] in {
1537 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1538 "ucomisd\t{$src2, $src1|$src1, $src2}",
1539 [(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
1541 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1542 "ucomisd\t{$src2, $src1|$src1, $src2}",
1543 [(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
1544 (load addr:$src2)))]>;
1546 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1547 "comisd\t{$src2, $src1|$src1, $src2}",
1548 [(set EFLAGS, (X86comi (v2f64 VR128:$src1),
1550 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1551 "comisd\t{$src2, $src1|$src1, $src2}",
1552 [(set EFLAGS, (X86comi (v2f64 VR128:$src1),
1553 (load addr:$src2)))]>;
1554 } // Defs = [EFLAGS]
1556 // Aliases of packed SSE2 instructions for scalar use. These all have names
1557 // that start with 'Fs'.
1559 // Alias instructions that map fld0 to pxor for sse.
1560 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1561 canFoldAsLoad = 1 in
1562 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1563 [(set FR64:$dst, fpimm0)]>,
1564 Requires<[HasSSE2]>, TB, OpSize;
1566 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1568 let neverHasSideEffects = 1 in
1569 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1570 "movapd\t{$src, $dst|$dst, $src}", []>;
1572 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1574 let canFoldAsLoad = 1, isReMaterializable = 1 in
1575 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1576 "movapd\t{$src, $dst|$dst, $src}",
1577 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1579 //===---------------------------------------------------------------------===//
1580 // SSE packed FP Instructions
1582 // Move Instructions
1583 let neverHasSideEffects = 1 in
1584 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1585 "movapd\t{$src, $dst|$dst, $src}", []>;
1586 let canFoldAsLoad = 1, isReMaterializable = 1 in
1587 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1588 "movapd\t{$src, $dst|$dst, $src}",
1589 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1591 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1592 "movapd\t{$src, $dst|$dst, $src}",
1593 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1595 let neverHasSideEffects = 1 in
1596 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1597 "movupd\t{$src, $dst|$dst, $src}", []>;
1598 let canFoldAsLoad = 1 in
1599 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1600 "movupd\t{$src, $dst|$dst, $src}",
1601 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1602 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1603 "movupd\t{$src, $dst|$dst, $src}",
1604 [(store (v2f64 VR128:$src), addr:$dst)]>;
1606 // Intrinsic forms of MOVUPD load and store
1607 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1608 "movupd\t{$src, $dst|$dst, $src}",
1609 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1610 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1611 "movupd\t{$src, $dst|$dst, $src}",
1612 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1614 let Constraints = "$src1 = $dst" in {
1615 let AddedComplexity = 20 in {
1616 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1617 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1618 "movlpd\t{$src2, $dst|$dst, $src2}",
1620 (v2f64 (movlp VR128:$src1,
1621 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1622 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1623 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1624 "movhpd\t{$src2, $dst|$dst, $src2}",
1626 (v2f64 (movlhps VR128:$src1,
1627 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1628 } // AddedComplexity
1629 } // Constraints = "$src1 = $dst"
1631 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1632 "movlpd\t{$src, $dst|$dst, $src}",
1633 [(store (f64 (vector_extract (v2f64 VR128:$src),
1634 (iPTR 0))), addr:$dst)]>;
1636 // v2f64 extract element 1 is always custom lowered to unpack high to low
1637 // and extract element 0 so the non-store version isn't too horrible.
1638 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1639 "movhpd\t{$src, $dst|$dst, $src}",
1640 [(store (f64 (vector_extract
1641 (v2f64 (unpckh VR128:$src, (undef))),
1642 (iPTR 0))), addr:$dst)]>;
1644 // SSE2 instructions without OpSize prefix
1645 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1646 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1647 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1648 TB, Requires<[HasSSE2]>;
1649 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1650 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1651 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1652 (bitconvert (memopv2i64 addr:$src))))]>,
1653 TB, Requires<[HasSSE2]>;
1655 // SSE2 instructions with XS prefix
1656 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1657 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1658 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1659 XS, Requires<[HasSSE2]>;
1660 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1661 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1662 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1663 (bitconvert (memopv2i64 addr:$src))))]>,
1664 XS, Requires<[HasSSE2]>;
1666 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1667 "cvtps2dq\t{$src, $dst|$dst, $src}",
1668 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1669 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1670 "cvtps2dq\t{$src, $dst|$dst, $src}",
1671 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1672 (memop addr:$src)))]>;
1673 // SSE2 packed instructions with XS prefix
1674 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1675 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1676 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1677 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1679 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1680 "cvttps2dq\t{$src, $dst|$dst, $src}",
1682 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1683 XS, Requires<[HasSSE2]>;
1684 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1685 "cvttps2dq\t{$src, $dst|$dst, $src}",
1686 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1687 (memop addr:$src)))]>,
1688 XS, Requires<[HasSSE2]>;
1690 // SSE2 packed instructions with XD prefix
1691 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1692 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1693 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1694 XD, Requires<[HasSSE2]>;
1695 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1696 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1697 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1698 (memop addr:$src)))]>,
1699 XD, Requires<[HasSSE2]>;
1701 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1702 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1703 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1704 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1705 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1706 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1707 (memop addr:$src)))]>;
1709 // SSE2 instructions without OpSize prefix
1710 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1711 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1712 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1713 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1715 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1716 "cvtps2pd\t{$src, $dst|$dst, $src}",
1717 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1718 TB, Requires<[HasSSE2]>;
1719 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1720 "cvtps2pd\t{$src, $dst|$dst, $src}",
1721 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1722 (load addr:$src)))]>,
1723 TB, Requires<[HasSSE2]>;
1725 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1726 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1727 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1728 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1731 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1732 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1733 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1734 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1735 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1736 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1737 (memop addr:$src)))]>;
1739 // Match intrinsics which expect XMM operand(s).
1740 // Aliases for intrinsics
1741 let Constraints = "$src1 = $dst" in {
1742 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1743 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1744 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1745 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1747 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1748 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1749 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1750 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1751 (loadi32 addr:$src2)))]>;
1752 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1753 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1754 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1755 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1757 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1758 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1759 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1760 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1761 (load addr:$src2)))]>;
1762 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1763 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1764 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1765 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1766 VR128:$src2))]>, XS,
1767 Requires<[HasSSE2]>;
1768 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1769 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1770 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1771 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1772 (load addr:$src2)))]>, XS,
1773 Requires<[HasSSE2]>;
1778 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1780 /// In addition, we also have a special variant of the scalar form here to
1781 /// represent the associated intrinsic operation. This form is unlike the
1782 /// plain scalar form, in that it takes an entire vector (instead of a
1783 /// scalar) and leaves the top elements undefined.
1785 /// And, we have a special variant form for a full-vector intrinsic form.
1787 /// These four forms can each have a reg or a mem operand, so there are a
1788 /// total of eight "instructions".
1790 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1794 bit Commutable = 0> {
1795 // Scalar operation, reg.
1796 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1797 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1798 [(set FR64:$dst, (OpNode FR64:$src))]> {
1799 let isCommutable = Commutable;
1802 // Scalar operation, mem.
1803 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1804 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1805 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1807 // Vector operation, reg.
1808 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1809 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1810 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1811 let isCommutable = Commutable;
1814 // Vector operation, mem.
1815 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1816 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1817 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1819 // Intrinsic operation, reg.
1820 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1821 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1822 [(set VR128:$dst, (F64Int VR128:$src))]> {
1823 let isCommutable = Commutable;
1826 // Intrinsic operation, mem.
1827 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1828 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1829 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1831 // Vector intrinsic operation, reg
1832 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1833 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1834 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1835 let isCommutable = Commutable;
1838 // Vector intrinsic operation, mem
1839 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1840 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1841 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1845 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1846 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1848 // There is no f64 version of the reciprocal approximation instructions.
1850 let Constraints = "$src1 = $dst" in {
1851 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1852 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1853 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1854 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1855 VR128:$src, imm:$cc))]>;
1856 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1857 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1858 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1859 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1860 (memop addr:$src), imm:$cc))]>;
1862 // Accept explicit immediate argument form instead of comparison code.
1863 let isAsmParserOnly = 1 in {
1864 def CMPPDrri_alt : PDIi8<0xC2, MRMSrcReg,
1865 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, i8imm:$src2),
1866 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
1867 def CMPPDrmi_alt : PDIi8<0xC2, MRMSrcMem,
1868 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, i8imm:$src2),
1869 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
1872 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1873 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1874 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1875 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1877 // Shuffle and unpack instructions
1878 let Constraints = "$src1 = $dst" in {
1879 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1880 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1881 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1883 (v2f64 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1884 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1885 (outs VR128:$dst), (ins VR128:$src1,
1886 f128mem:$src2, i8imm:$src3),
1887 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1890 VR128:$src1, (memopv2f64 addr:$src2))))]>;
1892 let AddedComplexity = 10 in {
1893 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1894 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1895 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1897 (v2f64 (unpckh VR128:$src1, VR128:$src2)))]>;
1898 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1899 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1900 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1902 (v2f64 (unpckh VR128:$src1,
1903 (memopv2f64 addr:$src2))))]>;
1905 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1906 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1907 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1909 (v2f64 (unpckl VR128:$src1, VR128:$src2)))]>;
1910 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1911 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1912 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1914 (unpckl VR128:$src1, (memopv2f64 addr:$src2)))]>;
1915 } // AddedComplexity
1916 } // Constraints = "$src1 = $dst"
1919 //===---------------------------------------------------------------------===//
1920 // SSE integer instructions
1921 let ExeDomain = SSEPackedInt in {
1923 // Move Instructions
1924 let neverHasSideEffects = 1 in
1925 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1926 "movdqa\t{$src, $dst|$dst, $src}", []>;
1927 let canFoldAsLoad = 1, mayLoad = 1 in
1928 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1929 "movdqa\t{$src, $dst|$dst, $src}",
1930 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1932 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1933 "movdqa\t{$src, $dst|$dst, $src}",
1934 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1935 let canFoldAsLoad = 1, mayLoad = 1 in
1936 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1937 "movdqu\t{$src, $dst|$dst, $src}",
1938 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1939 XS, Requires<[HasSSE2]>;
1941 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1942 "movdqu\t{$src, $dst|$dst, $src}",
1943 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1944 XS, Requires<[HasSSE2]>;
1946 // Intrinsic forms of MOVDQU load and store
1947 let canFoldAsLoad = 1 in
1948 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1949 "movdqu\t{$src, $dst|$dst, $src}",
1950 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1951 XS, Requires<[HasSSE2]>;
1952 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1953 "movdqu\t{$src, $dst|$dst, $src}",
1954 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1955 XS, Requires<[HasSSE2]>;
1957 let Constraints = "$src1 = $dst" in {
1959 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1960 bit Commutable = 0> {
1961 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1962 (ins VR128:$src1, VR128:$src2),
1963 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1964 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1965 let isCommutable = Commutable;
1967 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1968 (ins VR128:$src1, i128mem:$src2),
1969 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1970 [(set VR128:$dst, (IntId VR128:$src1,
1971 (bitconvert (memopv2i64
1975 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1977 Intrinsic IntId, Intrinsic IntId2> {
1978 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1979 (ins VR128:$src1, VR128:$src2),
1980 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1981 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1982 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1983 (ins VR128:$src1, i128mem:$src2),
1984 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1985 [(set VR128:$dst, (IntId VR128:$src1,
1986 (bitconvert (memopv2i64 addr:$src2))))]>;
1987 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
1988 (ins VR128:$src1, i32i8imm:$src2),
1989 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1990 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
1993 /// PDI_binop_rm - Simple SSE2 binary operator.
1994 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1995 ValueType OpVT, bit Commutable = 0> {
1996 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1997 (ins VR128:$src1, VR128:$src2),
1998 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1999 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
2000 let isCommutable = Commutable;
2002 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2003 (ins VR128:$src1, i128mem:$src2),
2004 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2005 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2006 (bitconvert (memopv2i64 addr:$src2)))))]>;
2009 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2011 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2012 /// to collapse (bitconvert VT to VT) into its operand.
2014 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2015 bit Commutable = 0> {
2016 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2017 (ins VR128:$src1, VR128:$src2),
2018 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2019 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
2020 let isCommutable = Commutable;
2022 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2023 (ins VR128:$src1, i128mem:$src2),
2024 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2025 [(set VR128:$dst, (OpNode VR128:$src1,
2026 (memopv2i64 addr:$src2)))]>;
2029 } // Constraints = "$src1 = $dst"
2030 } // ExeDomain = SSEPackedInt
2032 // 128-bit Integer Arithmetic
2034 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2035 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2036 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2037 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2039 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2040 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2041 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2042 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2044 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2045 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2046 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2047 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2049 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2050 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2051 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2052 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2054 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2056 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2057 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
2058 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2060 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2062 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2063 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2066 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2067 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2068 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2069 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2070 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2073 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2074 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2075 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2076 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2077 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2078 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2080 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2081 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2082 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2083 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2084 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2085 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2087 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2088 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2089 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2090 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2092 // 128-bit logical shifts.
2093 let Constraints = "$src1 = $dst", neverHasSideEffects = 1,
2094 ExeDomain = SSEPackedInt in {
2095 def PSLLDQri : PDIi8<0x73, MRM7r,
2096 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2097 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2098 def PSRLDQri : PDIi8<0x73, MRM3r,
2099 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2100 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2101 // PSRADQri doesn't exist in SSE[1-3].
2104 let Predicates = [HasSSE2] in {
2105 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2106 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2107 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2108 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2109 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2110 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2111 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2112 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2113 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2114 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2116 // Shift up / down and insert zero's.
2117 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2118 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2119 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2120 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2124 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2125 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
2126 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2128 let Constraints = "$src1 = $dst", ExeDomain = SSEPackedInt in {
2129 def PANDNrr : PDI<0xDF, MRMSrcReg,
2130 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2131 "pandn\t{$src2, $dst|$dst, $src2}",
2132 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2135 def PANDNrm : PDI<0xDF, MRMSrcMem,
2136 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2137 "pandn\t{$src2, $dst|$dst, $src2}",
2138 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2139 (memopv2i64 addr:$src2))))]>;
2142 // SSE2 Integer comparison
2143 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
2144 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
2145 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
2146 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2147 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2148 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2150 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2151 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2152 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2153 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2154 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2155 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2156 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2157 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2158 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2159 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2160 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2161 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2163 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2164 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2165 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2166 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2167 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2168 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2169 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2170 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2171 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2172 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2173 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2174 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2177 // Pack instructions
2178 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2179 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2180 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2182 let ExeDomain = SSEPackedInt in {
2184 // Shuffle and unpack instructions
2185 let AddedComplexity = 5 in {
2186 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2187 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2188 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2189 [(set VR128:$dst, (v4i32 (pshufd:$src2
2190 VR128:$src1, (undef))))]>;
2191 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2192 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2193 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2194 [(set VR128:$dst, (v4i32 (pshufd:$src2
2195 (bc_v4i32 (memopv2i64 addr:$src1)),
2199 // SSE2 with ImmT == Imm8 and XS prefix.
2200 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2201 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2202 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2203 [(set VR128:$dst, (v8i16 (pshufhw:$src2 VR128:$src1,
2205 XS, Requires<[HasSSE2]>;
2206 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2207 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2208 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2209 [(set VR128:$dst, (v8i16 (pshufhw:$src2
2210 (bc_v8i16 (memopv2i64 addr:$src1)),
2212 XS, Requires<[HasSSE2]>;
2214 // SSE2 with ImmT == Imm8 and XD prefix.
2215 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2216 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2217 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2218 [(set VR128:$dst, (v8i16 (pshuflw:$src2 VR128:$src1,
2220 XD, Requires<[HasSSE2]>;
2221 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2222 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2223 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2224 [(set VR128:$dst, (v8i16 (pshuflw:$src2
2225 (bc_v8i16 (memopv2i64 addr:$src1)),
2227 XD, Requires<[HasSSE2]>;
2229 // Unpack instructions
2230 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2231 PatFrag unp_frag, PatFrag bc_frag> {
2232 def rr : PDI<opc, MRMSrcReg,
2233 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2234 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2235 [(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
2236 def rm : PDI<opc, MRMSrcMem,
2237 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2238 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2239 [(set VR128:$dst, (unp_frag VR128:$src1,
2240 (bc_frag (memopv2i64
2244 let Constraints = "$src1 = $dst" in {
2245 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, unpckl, bc_v16i8>;
2246 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, unpckl, bc_v8i16>;
2247 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, unpckl, bc_v4i32>;
2249 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2250 /// knew to collapse (bitconvert VT to VT) into its operand.
2251 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2252 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2253 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2255 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2256 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2257 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2258 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2260 (v2i64 (unpckl VR128:$src1,
2261 (memopv2i64 addr:$src2))))]>;
2263 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, unpckh, bc_v16i8>;
2264 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, unpckh, bc_v8i16>;
2265 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, unpckh, bc_v4i32>;
2267 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2268 /// knew to collapse (bitconvert VT to VT) into its operand.
2269 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2270 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2271 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2273 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2274 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2275 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2276 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2278 (v2i64 (unpckh VR128:$src1,
2279 (memopv2i64 addr:$src2))))]>;
2283 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2284 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2285 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2286 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2288 let Constraints = "$src1 = $dst" in {
2289 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2290 (outs VR128:$dst), (ins VR128:$src1,
2291 GR32:$src2, i32i8imm:$src3),
2292 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2294 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2295 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2296 (outs VR128:$dst), (ins VR128:$src1,
2297 i16mem:$src2, i32i8imm:$src3),
2298 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2300 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2305 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2306 "pmovmskb\t{$src, $dst|$dst, $src}",
2307 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2309 // Conditional store
2311 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2312 "maskmovdqu\t{$mask, $src|$src, $mask}",
2313 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2316 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2317 "maskmovdqu\t{$mask, $src|$src, $mask}",
2318 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2320 } // ExeDomain = SSEPackedInt
2322 // Non-temporal stores
2323 def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2324 "movntpd\t{$src, $dst|$dst, $src}",
2325 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2326 let ExeDomain = SSEPackedInt in
2327 def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2328 "movntdq\t{$src, $dst|$dst, $src}",
2329 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2330 def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2331 "movnti\t{$src, $dst|$dst, $src}",
2332 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2333 TB, Requires<[HasSSE2]>;
2335 let AddedComplexity = 400 in { // Prefer non-temporal versions
2336 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2337 "movntpd\t{$src, $dst|$dst, $src}",
2338 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2340 let ExeDomain = SSEPackedInt in
2341 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2342 "movntdq\t{$src, $dst|$dst, $src}",
2343 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2347 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2348 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2349 TB, Requires<[HasSSE2]>;
2351 // Load, store, and memory fence
2352 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
2353 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2354 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
2355 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2357 // Pause. This "instruction" is encoded as "rep; nop", so even though it
2358 // was introduced with SSE2, it's backward compatible.
2359 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
2361 //TODO: custom lower this so as to never even generate the noop
2362 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2364 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2365 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2366 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2369 // Alias instructions that map zero vector to pxor / xorp* for sse.
2370 // We set canFoldAsLoad because this can be converted to a constant-pool
2371 // load of an all-ones value if folding it would be beneficial.
2372 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2373 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
2374 // FIXME: Change encoding to pseudo.
2375 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
2376 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2378 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2379 "movd\t{$src, $dst|$dst, $src}",
2381 (v4i32 (scalar_to_vector GR32:$src)))]>;
2382 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2383 "movd\t{$src, $dst|$dst, $src}",
2385 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2387 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2388 "movd\t{$src, $dst|$dst, $src}",
2389 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2391 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2392 "movd\t{$src, $dst|$dst, $src}",
2393 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2395 // SSE2 instructions with XS prefix
2396 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2397 "movq\t{$src, $dst|$dst, $src}",
2399 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2400 Requires<[HasSSE2]>;
2401 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2402 "movq\t{$src, $dst|$dst, $src}",
2403 [(store (i64 (vector_extract (v2i64 VR128:$src),
2404 (iPTR 0))), addr:$dst)]>;
2406 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
2407 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
2409 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2410 "movd\t{$src, $dst|$dst, $src}",
2411 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2413 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2414 "movd\t{$src, $dst|$dst, $src}",
2415 [(store (i32 (vector_extract (v4i32 VR128:$src),
2416 (iPTR 0))), addr:$dst)]>;
2418 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2419 "movd\t{$src, $dst|$dst, $src}",
2420 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2421 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2422 "movd\t{$src, $dst|$dst, $src}",
2423 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2425 // Store / copy lower 64-bits of a XMM register.
2426 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2427 "movq\t{$src, $dst|$dst, $src}",
2428 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2430 // movd / movq to XMM register zero-extends
2431 let AddedComplexity = 15 in {
2432 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2433 "movd\t{$src, $dst|$dst, $src}",
2434 [(set VR128:$dst, (v4i32 (X86vzmovl
2435 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2436 // This is X86-64 only.
2437 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2438 "mov{d|q}\t{$src, $dst|$dst, $src}",
2439 [(set VR128:$dst, (v2i64 (X86vzmovl
2440 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2443 let AddedComplexity = 20 in {
2444 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2445 "movd\t{$src, $dst|$dst, $src}",
2447 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2448 (loadi32 addr:$src))))))]>;
2450 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2451 (MOVZDI2PDIrm addr:$src)>;
2452 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2453 (MOVZDI2PDIrm addr:$src)>;
2454 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2455 (MOVZDI2PDIrm addr:$src)>;
2457 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2458 "movq\t{$src, $dst|$dst, $src}",
2460 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2461 (loadi64 addr:$src))))))]>, XS,
2462 Requires<[HasSSE2]>;
2464 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2465 (MOVZQI2PQIrm addr:$src)>;
2466 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2467 (MOVZQI2PQIrm addr:$src)>;
2468 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2471 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2472 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2473 let AddedComplexity = 15 in
2474 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2475 "movq\t{$src, $dst|$dst, $src}",
2476 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2477 XS, Requires<[HasSSE2]>;
2479 let AddedComplexity = 20 in {
2480 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2481 "movq\t{$src, $dst|$dst, $src}",
2482 [(set VR128:$dst, (v2i64 (X86vzmovl
2483 (loadv2i64 addr:$src))))]>,
2484 XS, Requires<[HasSSE2]>;
2486 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2487 (MOVZPQILo2PQIrm addr:$src)>;
2490 // Instructions for the disassembler
2491 // xr = XMM register
2494 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2495 "movq\t{$src, $dst|$dst, $src}", []>, XS;
2497 //===---------------------------------------------------------------------===//
2498 // SSE3 Instructions
2499 //===---------------------------------------------------------------------===//
2501 // Move Instructions
2502 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2503 "movshdup\t{$src, $dst|$dst, $src}",
2504 [(set VR128:$dst, (v4f32 (movshdup
2505 VR128:$src, (undef))))]>;
2506 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2507 "movshdup\t{$src, $dst|$dst, $src}",
2508 [(set VR128:$dst, (movshdup
2509 (memopv4f32 addr:$src), (undef)))]>;
2511 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2512 "movsldup\t{$src, $dst|$dst, $src}",
2513 [(set VR128:$dst, (v4f32 (movsldup
2514 VR128:$src, (undef))))]>;
2515 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2516 "movsldup\t{$src, $dst|$dst, $src}",
2517 [(set VR128:$dst, (movsldup
2518 (memopv4f32 addr:$src), (undef)))]>;
2520 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2521 "movddup\t{$src, $dst|$dst, $src}",
2522 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
2523 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2524 "movddup\t{$src, $dst|$dst, $src}",
2526 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
2529 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
2531 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2533 let AddedComplexity = 5 in {
2534 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
2535 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2536 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
2537 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2538 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
2539 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2540 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
2541 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2545 let Constraints = "$src1 = $dst" in {
2546 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2547 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2548 "addsubps\t{$src2, $dst|$dst, $src2}",
2549 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2551 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2552 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2553 "addsubps\t{$src2, $dst|$dst, $src2}",
2554 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2555 (memop addr:$src2)))]>;
2556 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2557 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2558 "addsubpd\t{$src2, $dst|$dst, $src2}",
2559 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2561 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2562 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2563 "addsubpd\t{$src2, $dst|$dst, $src2}",
2564 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2565 (memop addr:$src2)))]>;
2568 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2569 "lddqu\t{$src, $dst|$dst, $src}",
2570 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2573 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2574 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2575 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2576 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2577 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2578 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2579 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2580 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2581 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2582 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2583 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2584 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2585 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2586 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2587 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2588 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2590 let Constraints = "$src1 = $dst" in {
2591 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2592 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2593 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2594 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2595 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2596 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2597 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2598 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2601 // Thread synchronization
2602 def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
2603 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2604 def MWAIT : I<0x01, MRM_C9, (outs), (ins), "mwait",
2605 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2607 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2608 let AddedComplexity = 15 in
2609 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
2610 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2611 let AddedComplexity = 20 in
2612 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2613 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2615 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2616 let AddedComplexity = 15 in
2617 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
2618 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2619 let AddedComplexity = 20 in
2620 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2621 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2623 //===---------------------------------------------------------------------===//
2624 // SSSE3 Instructions
2625 //===---------------------------------------------------------------------===//
2627 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2628 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2629 Intrinsic IntId64, Intrinsic IntId128> {
2630 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2631 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2632 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2634 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2635 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2637 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2639 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2641 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2642 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2645 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2647 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2650 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2653 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2654 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2655 Intrinsic IntId64, Intrinsic IntId128> {
2656 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2658 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2659 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2661 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2663 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2666 (bitconvert (memopv4i16 addr:$src))))]>;
2668 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2670 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2671 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2674 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2676 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2679 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2682 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2683 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2684 Intrinsic IntId64, Intrinsic IntId128> {
2685 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2687 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2688 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2690 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2692 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2695 (bitconvert (memopv2i32 addr:$src))))]>;
2697 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2699 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2700 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2703 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2705 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2708 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2711 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2712 int_x86_ssse3_pabs_b,
2713 int_x86_ssse3_pabs_b_128>;
2714 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2715 int_x86_ssse3_pabs_w,
2716 int_x86_ssse3_pabs_w_128>;
2717 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2718 int_x86_ssse3_pabs_d,
2719 int_x86_ssse3_pabs_d_128>;
2721 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2722 let Constraints = "$src1 = $dst" in {
2723 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2724 Intrinsic IntId64, Intrinsic IntId128,
2725 bit Commutable = 0> {
2726 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2727 (ins VR64:$src1, VR64:$src2),
2728 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2729 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2730 let isCommutable = Commutable;
2732 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2733 (ins VR64:$src1, i64mem:$src2),
2734 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2736 (IntId64 VR64:$src1,
2737 (bitconvert (memopv8i8 addr:$src2))))]>;
2739 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2740 (ins VR128:$src1, VR128:$src2),
2741 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2742 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2744 let isCommutable = Commutable;
2746 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2747 (ins VR128:$src1, i128mem:$src2),
2748 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2750 (IntId128 VR128:$src1,
2751 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2755 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2756 let Constraints = "$src1 = $dst" in {
2757 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2758 Intrinsic IntId64, Intrinsic IntId128,
2759 bit Commutable = 0> {
2760 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2761 (ins VR64:$src1, VR64:$src2),
2762 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2763 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2764 let isCommutable = Commutable;
2766 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2767 (ins VR64:$src1, i64mem:$src2),
2768 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2770 (IntId64 VR64:$src1,
2771 (bitconvert (memopv4i16 addr:$src2))))]>;
2773 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2774 (ins VR128:$src1, VR128:$src2),
2775 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2776 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2778 let isCommutable = Commutable;
2780 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2781 (ins VR128:$src1, i128mem:$src2),
2782 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2784 (IntId128 VR128:$src1,
2785 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2789 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2790 let Constraints = "$src1 = $dst" in {
2791 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2792 Intrinsic IntId64, Intrinsic IntId128,
2793 bit Commutable = 0> {
2794 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2795 (ins VR64:$src1, VR64:$src2),
2796 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2797 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2798 let isCommutable = Commutable;
2800 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2801 (ins VR64:$src1, i64mem:$src2),
2802 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2804 (IntId64 VR64:$src1,
2805 (bitconvert (memopv2i32 addr:$src2))))]>;
2807 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2808 (ins VR128:$src1, VR128:$src2),
2809 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2810 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2812 let isCommutable = Commutable;
2814 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2815 (ins VR128:$src1, i128mem:$src2),
2816 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2818 (IntId128 VR128:$src1,
2819 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2823 let ImmT = NoImm in { // None of these have i8 immediate fields.
2824 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2825 int_x86_ssse3_phadd_w,
2826 int_x86_ssse3_phadd_w_128>;
2827 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2828 int_x86_ssse3_phadd_d,
2829 int_x86_ssse3_phadd_d_128>;
2830 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2831 int_x86_ssse3_phadd_sw,
2832 int_x86_ssse3_phadd_sw_128>;
2833 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2834 int_x86_ssse3_phsub_w,
2835 int_x86_ssse3_phsub_w_128>;
2836 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2837 int_x86_ssse3_phsub_d,
2838 int_x86_ssse3_phsub_d_128>;
2839 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2840 int_x86_ssse3_phsub_sw,
2841 int_x86_ssse3_phsub_sw_128>;
2842 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2843 int_x86_ssse3_pmadd_ub_sw,
2844 int_x86_ssse3_pmadd_ub_sw_128>;
2845 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2846 int_x86_ssse3_pmul_hr_sw,
2847 int_x86_ssse3_pmul_hr_sw_128, 1>;
2849 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2850 int_x86_ssse3_pshuf_b,
2851 int_x86_ssse3_pshuf_b_128>;
2852 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2853 int_x86_ssse3_psign_b,
2854 int_x86_ssse3_psign_b_128>;
2855 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2856 int_x86_ssse3_psign_w,
2857 int_x86_ssse3_psign_w_128>;
2858 defm PSIGND : SS3I_binop_rm_int_32<0x0A, "psignd",
2859 int_x86_ssse3_psign_d,
2860 int_x86_ssse3_psign_d_128>;
2863 // palignr patterns.
2864 let Constraints = "$src1 = $dst" in {
2865 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2866 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
2867 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2869 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2870 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
2871 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2874 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2875 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
2876 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2878 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2879 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
2880 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2884 let AddedComplexity = 5 in {
2886 def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
2887 (PALIGNR64rr VR64:$src2, VR64:$src1,
2888 (SHUFFLE_get_palign_imm VR64:$src3))>,
2889 Requires<[HasSSSE3]>;
2890 def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)),
2891 (PALIGNR64rr VR64:$src2, VR64:$src1,
2892 (SHUFFLE_get_palign_imm VR64:$src3))>,
2893 Requires<[HasSSSE3]>;
2894 def : Pat<(v2f32 (palign:$src3 VR64:$src1, VR64:$src2)),
2895 (PALIGNR64rr VR64:$src2, VR64:$src1,
2896 (SHUFFLE_get_palign_imm VR64:$src3))>,
2897 Requires<[HasSSSE3]>;
2898 def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)),
2899 (PALIGNR64rr VR64:$src2, VR64:$src1,
2900 (SHUFFLE_get_palign_imm VR64:$src3))>,
2901 Requires<[HasSSSE3]>;
2902 def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)),
2903 (PALIGNR64rr VR64:$src2, VR64:$src1,
2904 (SHUFFLE_get_palign_imm VR64:$src3))>,
2905 Requires<[HasSSSE3]>;
2907 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
2908 (PALIGNR128rr VR128:$src2, VR128:$src1,
2909 (SHUFFLE_get_palign_imm VR128:$src3))>,
2910 Requires<[HasSSSE3]>;
2911 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
2912 (PALIGNR128rr VR128:$src2, VR128:$src1,
2913 (SHUFFLE_get_palign_imm VR128:$src3))>,
2914 Requires<[HasSSSE3]>;
2915 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
2916 (PALIGNR128rr VR128:$src2, VR128:$src1,
2917 (SHUFFLE_get_palign_imm VR128:$src3))>,
2918 Requires<[HasSSSE3]>;
2919 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
2920 (PALIGNR128rr VR128:$src2, VR128:$src1,
2921 (SHUFFLE_get_palign_imm VR128:$src3))>,
2922 Requires<[HasSSSE3]>;
2925 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
2926 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
2927 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
2928 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
2930 //===---------------------------------------------------------------------===//
2931 // Non-Instruction Patterns
2932 //===---------------------------------------------------------------------===//
2934 // extload f32 -> f64. This matches load+fextend because we have a hack in
2935 // the isel (PreprocessForFPConvert) that can introduce loads after dag
2937 // Since these loads aren't folded into the fextend, we have to match it
2939 let Predicates = [HasSSE2] in
2940 def : Pat<(fextend (loadf32 addr:$src)),
2941 (CVTSS2SDrm addr:$src)>;
2944 let Predicates = [HasSSE2] in {
2945 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2946 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2947 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2948 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2949 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2950 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2951 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2952 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2953 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2954 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2955 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2956 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2957 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2958 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2959 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2960 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2961 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2962 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2963 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2964 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2965 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2966 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2967 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2968 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2969 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2970 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2971 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2972 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2973 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2974 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2977 // Move scalar to XMM zero-extended
2978 // movd to XMM register zero-extends
2979 let AddedComplexity = 15 in {
2980 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2981 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
2982 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
2983 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
2984 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
2985 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
2986 (MOVSSrr (v4f32 (V_SET0PS)),
2987 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
2988 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
2989 (MOVSSrr (v4i32 (V_SET0PI)),
2990 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
2993 // Splat v2f64 / v2i64
2994 let AddedComplexity = 10 in {
2995 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2996 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2997 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
2998 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2999 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3000 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3001 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
3002 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3005 // Special unary SHUFPSrri case.
3006 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3007 (SHUFPSrri VR128:$src1, VR128:$src1,
3008 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3009 let AddedComplexity = 5 in
3010 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3011 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3012 Requires<[HasSSE2]>;
3013 // Special unary SHUFPDrri case.
3014 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3015 (SHUFPDrri VR128:$src1, VR128:$src1,
3016 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3017 Requires<[HasSSE2]>;
3018 // Special unary SHUFPDrri case.
3019 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3020 (SHUFPDrri VR128:$src1, VR128:$src1,
3021 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3022 Requires<[HasSSE2]>;
3023 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3024 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3025 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3026 Requires<[HasSSE2]>;
3028 // Special binary v4i32 shuffle cases with SHUFPS.
3029 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3030 (SHUFPSrri VR128:$src1, VR128:$src2,
3031 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3032 Requires<[HasSSE2]>;
3033 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3034 (SHUFPSrmi VR128:$src1, addr:$src2,
3035 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3036 Requires<[HasSSE2]>;
3037 // Special binary v2i64 shuffle cases using SHUFPDrri.
3038 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3039 (SHUFPDrri VR128:$src1, VR128:$src2,
3040 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3041 Requires<[HasSSE2]>;
3043 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3044 let AddedComplexity = 15 in {
3045 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3046 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3047 Requires<[OptForSpeed, HasSSE2]>;
3048 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3049 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3050 Requires<[OptForSpeed, HasSSE2]>;
3052 let AddedComplexity = 10 in {
3053 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3054 (UNPCKLPSrr VR128:$src, VR128:$src)>;
3055 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3056 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
3057 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3058 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
3059 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3060 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3063 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3064 let AddedComplexity = 15 in {
3065 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3066 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3067 Requires<[OptForSpeed, HasSSE2]>;
3068 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3069 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3070 Requires<[OptForSpeed, HasSSE2]>;
3072 let AddedComplexity = 10 in {
3073 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3074 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3075 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3076 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3077 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3078 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3079 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3080 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3083 let AddedComplexity = 20 in {
3084 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3085 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3086 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3088 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3089 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3090 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3092 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3093 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3094 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3095 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3096 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3099 let AddedComplexity = 20 in {
3100 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3101 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3102 (MOVLPSrm VR128:$src1, addr:$src2)>;
3103 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3104 (MOVLPDrm VR128:$src1, addr:$src2)>;
3105 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3106 (MOVLPSrm VR128:$src1, addr:$src2)>;
3107 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3108 (MOVLPDrm VR128:$src1, addr:$src2)>;
3111 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3112 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3113 (MOVLPSmr addr:$src1, VR128:$src2)>;
3114 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3115 (MOVLPDmr addr:$src1, VR128:$src2)>;
3116 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3118 (MOVLPSmr addr:$src1, VR128:$src2)>;
3119 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3120 (MOVLPDmr addr:$src1, VR128:$src2)>;
3122 let AddedComplexity = 15 in {
3123 // Setting the lowest element in the vector.
3124 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3125 (MOVSSrr (v4i32 VR128:$src1),
3126 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3127 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3128 (MOVSDrr (v2i64 VR128:$src1),
3129 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
3131 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3132 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3133 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3134 Requires<[HasSSE2]>;
3135 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3136 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3137 Requires<[HasSSE2]>;
3140 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3141 // fall back to this for SSE1)
3142 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3143 (SHUFPSrri VR128:$src2, VR128:$src1,
3144 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3146 // Set lowest element and zero upper elements.
3147 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3148 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3150 // Some special case pandn patterns.
3151 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3153 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3154 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3156 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3157 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3159 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3161 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3162 (memop addr:$src2))),
3163 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3164 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3165 (memop addr:$src2))),
3166 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3167 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3168 (memop addr:$src2))),
3169 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3171 // vector -> vector casts
3172 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3173 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3174 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3175 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3176 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3177 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3178 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3179 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3181 // Use movaps / movups for SSE integer load / store (one byte shorter).
3182 def : Pat<(alignedloadv4i32 addr:$src),
3183 (MOVAPSrm addr:$src)>;
3184 def : Pat<(loadv4i32 addr:$src),
3185 (MOVUPSrm addr:$src)>;
3186 def : Pat<(alignedloadv2i64 addr:$src),
3187 (MOVAPSrm addr:$src)>;
3188 def : Pat<(loadv2i64 addr:$src),
3189 (MOVUPSrm addr:$src)>;
3191 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3192 (MOVAPSmr addr:$dst, VR128:$src)>;
3193 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3194 (MOVAPSmr addr:$dst, VR128:$src)>;
3195 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3196 (MOVAPSmr addr:$dst, VR128:$src)>;
3197 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3198 (MOVAPSmr addr:$dst, VR128:$src)>;
3199 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3200 (MOVUPSmr addr:$dst, VR128:$src)>;
3201 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3202 (MOVUPSmr addr:$dst, VR128:$src)>;
3203 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3204 (MOVUPSmr addr:$dst, VR128:$src)>;
3205 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3206 (MOVUPSmr addr:$dst, VR128:$src)>;
3208 //===----------------------------------------------------------------------===//
3209 // SSE4.1 Instructions
3210 //===----------------------------------------------------------------------===//
3212 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3215 Intrinsic V2F64Int> {
3216 // Intrinsic operation, reg.
3217 // Vector intrinsic operation, reg
3218 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3219 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3220 !strconcat(OpcodeStr,
3221 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3222 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3225 // Vector intrinsic operation, mem
3226 def PSm_Int : Ii8<opcps, MRMSrcMem,
3227 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3228 !strconcat(OpcodeStr,
3229 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3231 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3233 Requires<[HasSSE41]>;
3235 // Vector intrinsic operation, reg
3236 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3237 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3238 !strconcat(OpcodeStr,
3239 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3240 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3243 // Vector intrinsic operation, mem
3244 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3245 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3246 !strconcat(OpcodeStr,
3247 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3249 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3253 let Constraints = "$src1 = $dst" in {
3254 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3258 // Intrinsic operation, reg.
3259 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3261 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3262 !strconcat(OpcodeStr,
3263 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3265 (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3268 // Intrinsic operation, mem.
3269 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3271 (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3272 !strconcat(OpcodeStr,
3273 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3275 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
3278 // Intrinsic operation, reg.
3279 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3281 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3282 !strconcat(OpcodeStr,
3283 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3285 (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3288 // Intrinsic operation, mem.
3289 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3291 (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
3292 !strconcat(OpcodeStr,
3293 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3295 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
3300 // FP round - roundss, roundps, roundsd, roundpd
3301 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
3302 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
3303 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
3304 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
3306 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3307 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3308 Intrinsic IntId128> {
3309 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3311 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3312 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3313 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3315 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3318 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3321 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3322 int_x86_sse41_phminposuw>;
3324 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3325 let Constraints = "$src1 = $dst" in {
3326 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3327 Intrinsic IntId128, bit Commutable = 0> {
3328 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3329 (ins VR128:$src1, VR128:$src2),
3330 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3331 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3333 let isCommutable = Commutable;
3335 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3336 (ins VR128:$src1, i128mem:$src2),
3337 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3339 (IntId128 VR128:$src1,
3340 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3344 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3345 int_x86_sse41_pcmpeqq, 1>;
3346 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3347 int_x86_sse41_packusdw, 0>;
3348 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3349 int_x86_sse41_pminsb, 1>;
3350 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3351 int_x86_sse41_pminsd, 1>;
3352 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3353 int_x86_sse41_pminud, 1>;
3354 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3355 int_x86_sse41_pminuw, 1>;
3356 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3357 int_x86_sse41_pmaxsb, 1>;
3358 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3359 int_x86_sse41_pmaxsd, 1>;
3360 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3361 int_x86_sse41_pmaxud, 1>;
3362 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3363 int_x86_sse41_pmaxuw, 1>;
3365 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
3367 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3368 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3369 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3370 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3372 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3373 let Constraints = "$src1 = $dst" in {
3374 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3375 SDNode OpNode, Intrinsic IntId128,
3376 bit Commutable = 0> {
3377 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3378 (ins VR128:$src1, VR128:$src2),
3379 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3380 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3381 VR128:$src2))]>, OpSize {
3382 let isCommutable = Commutable;
3384 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3385 (ins VR128:$src1, VR128:$src2),
3386 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3387 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3389 let isCommutable = Commutable;
3391 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3392 (ins VR128:$src1, i128mem:$src2),
3393 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3395 (OpVT (OpNode VR128:$src1, (memop addr:$src2))))]>, OpSize;
3396 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3397 (ins VR128:$src1, i128mem:$src2),
3398 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3400 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3405 /// SS48I_binop_rm - Simple SSE41 binary operator.
3406 let Constraints = "$src1 = $dst" in {
3407 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3408 ValueType OpVT, bit Commutable = 0> {
3409 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3410 (ins VR128:$src1, VR128:$src2),
3411 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3412 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
3414 let isCommutable = Commutable;
3416 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3417 (ins VR128:$src1, i128mem:$src2),
3418 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3419 [(set VR128:$dst, (OpNode VR128:$src1,
3420 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
3425 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, 1>;
3427 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3428 let Constraints = "$src1 = $dst" in {
3429 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3430 Intrinsic IntId128, bit Commutable = 0> {
3431 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3432 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3433 !strconcat(OpcodeStr,
3434 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3436 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3438 let isCommutable = Commutable;
3440 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3441 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3442 !strconcat(OpcodeStr,
3443 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3445 (IntId128 VR128:$src1,
3446 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3451 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3452 int_x86_sse41_blendps, 0>;
3453 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3454 int_x86_sse41_blendpd, 0>;
3455 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3456 int_x86_sse41_pblendw, 0>;
3457 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3458 int_x86_sse41_dpps, 1>;
3459 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3460 int_x86_sse41_dppd, 1>;
3461 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3462 int_x86_sse41_mpsadbw, 0>;
3465 /// SS41I_ternary_int - SSE 4.1 ternary operator
3466 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3467 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3468 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3469 (ins VR128:$src1, VR128:$src2),
3470 !strconcat(OpcodeStr,
3471 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3472 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3475 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3476 (ins VR128:$src1, i128mem:$src2),
3477 !strconcat(OpcodeStr,
3478 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3481 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3485 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3486 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3487 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3490 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3491 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3492 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3493 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3495 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3496 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3498 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3502 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3503 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3504 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3505 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3506 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3507 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3509 // Common patterns involving scalar load.
3510 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3511 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3512 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3513 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3515 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3516 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3517 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3518 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3520 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3521 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3522 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3523 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3525 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3526 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3527 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3528 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3530 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3531 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3532 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3533 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3535 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3536 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3537 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3538 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3541 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3542 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3543 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3544 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3546 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3547 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3549 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3553 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3554 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3555 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3556 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3558 // Common patterns involving scalar load
3559 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3560 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3561 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3562 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3564 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3565 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3566 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3567 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3570 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3571 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3572 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3573 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3575 // Expecting a i16 load any extended to i32 value.
3576 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3577 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3578 [(set VR128:$dst, (IntId (bitconvert
3579 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3583 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3584 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
3586 // Common patterns involving scalar load
3587 def : Pat<(int_x86_sse41_pmovsxbq
3588 (bitconvert (v4i32 (X86vzmovl
3589 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3590 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3592 def : Pat<(int_x86_sse41_pmovzxbq
3593 (bitconvert (v4i32 (X86vzmovl
3594 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3595 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3598 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3599 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3600 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3601 (ins VR128:$src1, i32i8imm:$src2),
3602 !strconcat(OpcodeStr,
3603 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3604 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3606 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3607 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3608 !strconcat(OpcodeStr,
3609 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3612 // There's an AssertZext in the way of writing the store pattern
3613 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3616 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3619 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3620 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3621 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3622 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3623 !strconcat(OpcodeStr,
3624 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3627 // There's an AssertZext in the way of writing the store pattern
3628 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3631 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3634 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3635 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3636 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3637 (ins VR128:$src1, i32i8imm:$src2),
3638 !strconcat(OpcodeStr,
3639 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3641 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3642 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3643 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3644 !strconcat(OpcodeStr,
3645 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3646 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3647 addr:$dst)]>, OpSize;
3650 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3653 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3655 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3656 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3657 (ins VR128:$src1, i32i8imm:$src2),
3658 !strconcat(OpcodeStr,
3659 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3661 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3663 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3664 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3665 !strconcat(OpcodeStr,
3666 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3667 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3668 addr:$dst)]>, OpSize;
3671 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3673 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3674 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3677 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3678 Requires<[HasSSE41]>;
3680 let Constraints = "$src1 = $dst" in {
3681 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3682 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3683 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3684 !strconcat(OpcodeStr,
3685 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3687 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3688 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3689 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3690 !strconcat(OpcodeStr,
3691 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3693 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3694 imm:$src3))]>, OpSize;
3698 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3700 let Constraints = "$src1 = $dst" in {
3701 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3702 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3703 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3704 !strconcat(OpcodeStr,
3705 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3707 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3709 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3710 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3711 !strconcat(OpcodeStr,
3712 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3714 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3715 imm:$src3)))]>, OpSize;
3719 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3721 // insertps has a few different modes, there's the first two here below which
3722 // are optimized inserts that won't zero arbitrary elements in the destination
3723 // vector. The next one matches the intrinsic and could zero arbitrary elements
3724 // in the target vector.
3725 let Constraints = "$src1 = $dst" in {
3726 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3727 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3728 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3729 !strconcat(OpcodeStr,
3730 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3732 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
3734 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3735 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3736 !strconcat(OpcodeStr,
3737 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3739 (X86insrtps VR128:$src1,
3740 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
3741 imm:$src3))]>, OpSize;
3745 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3747 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
3748 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
3750 // ptest instruction we'll lower to this in X86ISelLowering primarily from
3751 // the intel intrinsic that corresponds to this.
3752 let Defs = [EFLAGS] in {
3753 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3754 "ptest \t{$src2, $src1|$src1, $src2}",
3755 [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
3757 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3758 "ptest \t{$src2, $src1|$src1, $src2}",
3759 [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
3763 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3764 "movntdqa\t{$src, $dst|$dst, $src}",
3765 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
3769 //===----------------------------------------------------------------------===//
3770 // SSE4.2 Instructions
3771 //===----------------------------------------------------------------------===//
3773 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3774 let Constraints = "$src1 = $dst" in {
3775 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3776 Intrinsic IntId128, bit Commutable = 0> {
3777 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3778 (ins VR128:$src1, VR128:$src2),
3779 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3780 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3782 let isCommutable = Commutable;
3784 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3785 (ins VR128:$src1, i128mem:$src2),
3786 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3788 (IntId128 VR128:$src1,
3789 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3793 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3795 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3796 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3797 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3798 (PCMPGTQrm VR128:$src1, addr:$src2)>;
3800 // crc intrinsic instruction
3801 // This set of instructions are only rm, the only difference is the size
3803 let Constraints = "$src1 = $dst" in {
3804 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
3805 (ins GR32:$src1, i8mem:$src2),
3806 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3808 (int_x86_sse42_crc32_8 GR32:$src1,
3809 (load addr:$src2)))]>;
3810 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
3811 (ins GR32:$src1, GR8:$src2),
3812 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3814 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;
3815 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3816 (ins GR32:$src1, i16mem:$src2),
3817 "crc32{w} \t{$src2, $src1|$src1, $src2}",
3819 (int_x86_sse42_crc32_16 GR32:$src1,
3820 (load addr:$src2)))]>,
3822 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3823 (ins GR32:$src1, GR16:$src2),
3824 "crc32{w} \t{$src2, $src1|$src1, $src2}",
3826 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
3828 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3829 (ins GR32:$src1, i32mem:$src2),
3830 "crc32{l} \t{$src2, $src1|$src1, $src2}",
3832 (int_x86_sse42_crc32_32 GR32:$src1,
3833 (load addr:$src2)))]>;
3834 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3835 (ins GR32:$src1, GR32:$src2),
3836 "crc32{l} \t{$src2, $src1|$src1, $src2}",
3838 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;
3839 def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
3840 (ins GR64:$src1, i8mem:$src2),
3841 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3843 (int_x86_sse42_crc64_8 GR64:$src1,
3844 (load addr:$src2)))]>,
3846 def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
3847 (ins GR64:$src1, GR8:$src2),
3848 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3850 (int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,
3852 def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
3853 (ins GR64:$src1, i64mem:$src2),
3854 "crc32{q} \t{$src2, $src1|$src1, $src2}",
3856 (int_x86_sse42_crc64_64 GR64:$src1,
3857 (load addr:$src2)))]>,
3859 def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
3860 (ins GR64:$src1, GR64:$src2),
3861 "crc32{q} \t{$src2, $src1|$src1, $src2}",
3863 (int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,
3867 // String/text processing instructions.
3868 let Defs = [EFLAGS], usesCustomInserter = 1 in {
3869 def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3870 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3871 "#PCMPISTRM128rr PSEUDO!",
3872 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
3873 imm:$src3))]>, OpSize;
3874 def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3875 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3876 "#PCMPISTRM128rm PSEUDO!",
3877 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, (load addr:$src2),
3878 imm:$src3))]>, OpSize;
3881 let Defs = [XMM0, EFLAGS] in {
3882 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
3883 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3884 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3885 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
3886 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3887 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3890 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
3891 def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3892 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3893 "#PCMPESTRM128rr PSEUDO!",
3895 (int_x86_sse42_pcmpestrm128
3896 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
3898 def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3899 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3900 "#PCMPESTRM128rm PSEUDO!",
3901 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
3902 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
3906 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
3907 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
3908 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3909 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3910 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
3911 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3912 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3915 let Defs = [ECX, EFLAGS] in {
3916 multiclass SS42AI_pcmpistri<Intrinsic IntId128> {
3917 def rr : SS42AI<0x63, MRMSrcReg, (outs),
3918 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3919 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3920 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
3921 (implicit EFLAGS)]>, OpSize;
3922 def rm : SS42AI<0x63, MRMSrcMem, (outs),
3923 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3924 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3925 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
3926 (implicit EFLAGS)]>, OpSize;
3930 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
3931 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
3932 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
3933 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
3934 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
3935 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
3937 let Defs = [ECX, EFLAGS] in {
3938 let Uses = [EAX, EDX] in {
3939 multiclass SS42AI_pcmpestri<Intrinsic IntId128> {
3940 def rr : SS42AI<0x61, MRMSrcReg, (outs),
3941 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3942 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
3943 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
3944 (implicit EFLAGS)]>, OpSize;
3945 def rm : SS42AI<0x61, MRMSrcMem, (outs),
3946 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3947 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
3949 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
3950 (implicit EFLAGS)]>, OpSize;
3955 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
3956 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
3957 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
3958 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
3959 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
3960 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
3962 //===----------------------------------------------------------------------===//
3963 // AES-NI Instructions
3964 //===----------------------------------------------------------------------===//
3966 let Constraints = "$src1 = $dst" in {
3967 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
3968 Intrinsic IntId128, bit Commutable = 0> {
3969 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
3970 (ins VR128:$src1, VR128:$src2),
3971 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3972 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3974 let isCommutable = Commutable;
3976 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
3977 (ins VR128:$src1, i128mem:$src2),
3978 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3980 (IntId128 VR128:$src1,
3981 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3985 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
3986 int_x86_aesni_aesenc>;
3987 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
3988 int_x86_aesni_aesenclast>;
3989 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
3990 int_x86_aesni_aesdec>;
3991 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
3992 int_x86_aesni_aesdeclast>;
3994 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
3995 (AESENCrr VR128:$src1, VR128:$src2)>;
3996 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
3997 (AESENCrm VR128:$src1, addr:$src2)>;
3998 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
3999 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
4000 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
4001 (AESENCLASTrm VR128:$src1, addr:$src2)>;
4002 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
4003 (AESDECrr VR128:$src1, VR128:$src2)>;
4004 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
4005 (AESDECrm VR128:$src1, addr:$src2)>;
4006 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
4007 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
4008 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
4009 (AESDECLASTrm VR128:$src1, addr:$src2)>;
4011 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
4013 "aesimc\t{$src1, $dst|$dst, $src1}",
4015 (int_x86_aesni_aesimc VR128:$src1))]>,
4018 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
4019 (ins i128mem:$src1),
4020 "aesimc\t{$src1, $dst|$dst, $src1}",
4022 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
4025 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
4026 (ins VR128:$src1, i8imm:$src2),
4027 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4029 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
4031 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
4032 (ins i128mem:$src1, i8imm:$src2),
4033 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4035 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),