1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 let isCommutable = 1 in
85 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
90 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
97 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
98 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
99 string asm, string SSEVer, string FPSizeStr,
100 X86MemOperand x86memop, PatFrag mem_frag,
101 Domain d, bit Is2Addr = 1> {
102 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
104 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
105 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
106 [(set RC:$dst, (!cast<Intrinsic>(
107 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
108 RC:$src1, RC:$src2))], d>;
109 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
111 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
113 [(set RC:$dst, (!cast<Intrinsic>(
114 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
115 RC:$src1, (mem_frag addr:$src2)))], d>;
118 //===----------------------------------------------------------------------===//
119 // Non-instruction patterns
120 //===----------------------------------------------------------------------===//
122 // A vector extract of the first f32/f64 position is a subregister copy
123 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
124 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
125 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
126 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
128 // A 128-bit subvector extract from the first 256-bit vector position
129 // is a subregister copy that needs no instruction.
130 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
131 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
132 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
133 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
135 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
136 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
137 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
138 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
140 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
141 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
142 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
143 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
145 // A 128-bit subvector insert to the first 256-bit vector position
146 // is a subregister copy that needs no instruction.
147 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
148 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
149 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
150 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
151 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
152 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
153 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
154 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
155 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
156 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
157 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
158 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
160 // Implicitly promote a 32-bit scalar to a vector.
161 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
162 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
163 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
164 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
165 // Implicitly promote a 64-bit scalar to a vector.
166 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
167 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
168 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
169 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
171 // Bitcasts between 128-bit vector types. Return the original type since
172 // no instruction is needed for the conversion
173 let Predicates = [HasXMMInt] in {
174 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
175 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
176 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
177 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
178 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
179 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
180 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
181 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
182 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
183 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
184 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
185 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
186 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
187 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
188 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
189 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
190 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
191 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
192 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
193 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
194 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
195 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
196 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
197 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
198 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
199 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
200 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
201 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
202 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
203 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
206 // Bitcasts between 256-bit vector types. Return the original type since
207 // no instruction is needed for the conversion
208 let Predicates = [HasAVX] in {
209 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
210 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
211 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
212 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
213 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
214 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
215 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
216 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
217 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
218 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
219 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
220 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
221 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
222 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
223 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
224 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
225 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
226 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
227 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
228 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
229 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
230 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
231 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
232 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
233 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
234 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
235 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
236 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
237 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
238 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
241 // Alias instructions that map fld0 to pxor for sse.
242 // FIXME: Set encoding to pseudo!
243 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
244 canFoldAsLoad = 1 in {
245 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
246 [(set FR32:$dst, fp32imm0)]>,
247 Requires<[HasSSE1]>, TB, OpSize;
248 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
249 [(set FR64:$dst, fpimm0)]>,
250 Requires<[HasSSE2]>, TB, OpSize;
251 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
252 [(set FR32:$dst, fp32imm0)]>,
253 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
254 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
255 [(set FR64:$dst, fpimm0)]>,
256 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
259 //===----------------------------------------------------------------------===//
260 // AVX & SSE - Zero/One Vectors
261 //===----------------------------------------------------------------------===//
263 // Alias instructions that map zero vector to pxor / xorp* for sse.
264 // We set canFoldAsLoad because this can be converted to a constant-pool
265 // load of an all-zeros value if folding it would be beneficial.
266 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
267 // JIT implementation, it does not expand the instructions below like
268 // X86MCInstLower does.
269 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
270 isCodeGenOnly = 1 in {
271 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
272 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
273 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
274 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
275 let ExeDomain = SSEPackedInt in
276 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
277 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
280 // The same as done above but for AVX. The 128-bit versions are the
281 // same, but re-encoded. The 256-bit does not support PI version, and
282 // doesn't need it because on sandy bridge the register is set to zero
283 // at the rename stage without using any execution unit, so SET0PSY
284 // and SET0PDY can be used for vector int instructions without penalty
285 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
286 // JIT implementatioan, it does not expand the instructions below like
287 // X86MCInstLower does.
288 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
289 isCodeGenOnly = 1, Predicates = [HasAVX] in {
290 def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
291 [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V;
292 def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
293 [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V;
294 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
295 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
296 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
297 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
298 let ExeDomain = SSEPackedInt in
299 def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
300 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
303 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
304 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
305 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
307 // AVX has no support for 256-bit integer instructions, but since the 128-bit
308 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
309 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
310 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
311 (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
313 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
314 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
315 (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
317 // We set canFoldAsLoad because this can be converted to a constant-pool
318 // load of an all-ones value if folding it would be beneficial.
319 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
320 // JIT implementation, it does not expand the instructions below like
321 // X86MCInstLower does.
322 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
323 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
324 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
325 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
326 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
327 isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in
328 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
329 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
332 //===----------------------------------------------------------------------===//
333 // SSE 1 & 2 - Move FP Scalar Instructions
335 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
336 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
337 // is used instead. Register-to-register movss/movsd is not modeled as an
338 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
339 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
340 //===----------------------------------------------------------------------===//
342 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
343 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
344 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
346 // Loading from memory automatically zeroing upper bits.
347 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
348 PatFrag mem_pat, string OpcodeStr> :
349 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
350 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
351 [(set RC:$dst, (mem_pat addr:$src))]>;
354 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
355 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
356 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
357 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
359 // For the disassembler
360 let isCodeGenOnly = 1 in {
361 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
362 (ins VR128:$src1, FR32:$src2),
363 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
365 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
366 (ins VR128:$src1, FR64:$src2),
367 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
371 let canFoldAsLoad = 1, isReMaterializable = 1 in {
372 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
373 let AddedComplexity = 20 in
374 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
377 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
378 "movss\t{$src, $dst|$dst, $src}",
379 [(store FR32:$src, addr:$dst)]>, XS, VEX;
380 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
381 "movsd\t{$src, $dst|$dst, $src}",
382 [(store FR64:$src, addr:$dst)]>, XD, VEX;
385 let Constraints = "$src1 = $dst" in {
386 def MOVSSrr : sse12_move_rr<FR32, v4f32,
387 "movss\t{$src2, $dst|$dst, $src2}">, XS;
388 def MOVSDrr : sse12_move_rr<FR64, v2f64,
389 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
391 // For the disassembler
392 let isCodeGenOnly = 1 in {
393 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
394 (ins VR128:$src1, FR32:$src2),
395 "movss\t{$src2, $dst|$dst, $src2}", []>, XS;
396 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
397 (ins VR128:$src1, FR64:$src2),
398 "movsd\t{$src2, $dst|$dst, $src2}", []>, XD;
402 let canFoldAsLoad = 1, isReMaterializable = 1 in {
403 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
405 let AddedComplexity = 20 in
406 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
409 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
410 "movss\t{$src, $dst|$dst, $src}",
411 [(store FR32:$src, addr:$dst)]>;
412 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
413 "movsd\t{$src, $dst|$dst, $src}",
414 [(store FR64:$src, addr:$dst)]>;
417 let Predicates = [HasSSE1] in {
418 let AddedComplexity = 15 in {
419 // Extract the low 32-bit value from one vector and insert it into another.
420 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
421 (MOVSSrr (v4f32 VR128:$src1),
422 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
423 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
424 (MOVSSrr (v4i32 VR128:$src1),
425 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
427 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
428 // MOVSS to the lower bits.
429 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
430 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
431 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
432 (MOVSSrr (v4f32 (V_SET0PS)),
433 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
434 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
435 (MOVSSrr (v4i32 (V_SET0PI)),
436 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
439 let AddedComplexity = 20 in {
440 // MOVSSrm zeros the high parts of the register; represent this
441 // with SUBREG_TO_REG.
442 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
443 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
444 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
445 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
446 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
447 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
450 // Extract and store.
451 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
454 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
456 // Shuffle with MOVSS
457 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
458 (MOVSSrr VR128:$src1, FR32:$src2)>;
459 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
460 (MOVSSrr (v4i32 VR128:$src1),
461 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
462 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
463 (MOVSSrr (v4f32 VR128:$src1),
464 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
467 let Predicates = [HasSSE2] in {
468 let AddedComplexity = 15 in {
469 // Extract the low 64-bit value from one vector and insert it into another.
470 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
471 (MOVSDrr (v2f64 VR128:$src1),
472 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
473 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
474 (MOVSDrr (v2i64 VR128:$src1),
475 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
477 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
478 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
479 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
480 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
481 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
483 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
484 // MOVSD to the lower bits.
485 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
486 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
489 let AddedComplexity = 20 in {
490 // MOVSDrm zeros the high parts of the register; represent this
491 // with SUBREG_TO_REG.
492 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
493 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
494 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
495 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
496 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
497 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
498 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
499 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
500 def : Pat<(v2f64 (X86vzload addr:$src)),
501 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
504 // Extract and store.
505 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
508 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
510 // Shuffle with MOVSD
511 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
512 (MOVSDrr VR128:$src1, FR64:$src2)>;
513 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
514 (MOVSDrr (v2i64 VR128:$src1),
515 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
516 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
517 (MOVSDrr (v2f64 VR128:$src1),
518 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
519 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
520 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
521 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
522 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
524 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
525 // is during lowering, where it's not possible to recognize the fold cause
526 // it has two uses through a bitcast. One use disappears at isel time and the
527 // fold opportunity reappears.
528 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
529 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
530 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
531 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
534 let Predicates = [HasAVX] in {
535 let AddedComplexity = 15 in {
536 // Extract the low 32-bit value from one vector and insert it into another.
537 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
538 (VMOVSSrr (v4f32 VR128:$src1),
539 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
540 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
541 (VMOVSSrr (v4i32 VR128:$src1),
542 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
544 // Extract the low 64-bit value from one vector and insert it into another.
545 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
546 (VMOVSDrr (v2f64 VR128:$src1),
547 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
548 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
549 (VMOVSDrr (v2i64 VR128:$src1),
550 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
552 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
553 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
554 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
555 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
556 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
558 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
559 // MOVS{S,D} to the lower bits.
560 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
561 (VMOVSSrr (v4f32 (AVX_SET0PS)), FR32:$src)>;
562 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
563 (VMOVSSrr (v4f32 (AVX_SET0PS)),
564 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
565 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
566 (VMOVSSrr (v4i32 (AVX_SET0PI)),
567 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
568 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
569 (VMOVSDrr (v2f64 (AVX_SET0PS)), FR64:$src)>;
572 let AddedComplexity = 20 in {
573 // MOVSSrm zeros the high parts of the register; represent this
574 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
575 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
576 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
577 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
578 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
579 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
580 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
582 // MOVSDrm zeros the high parts of the register; represent this
583 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
584 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
585 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
586 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
587 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
588 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
589 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
590 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
591 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
592 def : Pat<(v2f64 (X86vzload addr:$src)),
593 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
595 // Represent the same patterns above but in the form they appear for
597 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
598 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
599 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
600 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
601 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
602 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
604 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
605 (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
606 (SUBREG_TO_REG (i32 0),
607 (v4f32 (VMOVSSrr (v4f32 (AVX_SET0PS)), FR32:$src)),
609 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
610 (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
611 (SUBREG_TO_REG (i64 0),
612 (v2f64 (VMOVSDrr (v2f64 (AVX_SET0PS)), FR64:$src)),
615 // Extract and store.
616 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
619 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
620 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
623 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
625 // Shuffle with VMOVSS
626 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
627 (VMOVSSrr VR128:$src1, FR32:$src2)>;
628 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
629 (VMOVSSrr (v4i32 VR128:$src1),
630 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
631 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
632 (VMOVSSrr (v4f32 VR128:$src1),
633 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
635 // Shuffle with VMOVSD
636 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
637 (VMOVSDrr VR128:$src1, FR64:$src2)>;
638 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
639 (VMOVSDrr (v2i64 VR128:$src1),
640 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
641 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
642 (VMOVSDrr (v2f64 VR128:$src1),
643 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
644 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
645 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
647 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
648 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
651 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
652 // is during lowering, where it's not possible to recognize the fold cause
653 // it has two uses through a bitcast. One use disappears at isel time and the
654 // fold opportunity reappears.
655 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
656 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
658 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
659 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
663 //===----------------------------------------------------------------------===//
664 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
665 //===----------------------------------------------------------------------===//
667 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
668 X86MemOperand x86memop, PatFrag ld_frag,
669 string asm, Domain d,
670 bit IsReMaterializable = 1> {
671 let neverHasSideEffects = 1 in
672 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
673 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
674 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
675 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
676 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
677 [(set RC:$dst, (ld_frag addr:$src))], d>;
680 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
681 "movaps", SSEPackedSingle>, TB, VEX;
682 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
683 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
684 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
685 "movups", SSEPackedSingle>, TB, VEX;
686 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
687 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
689 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
690 "movaps", SSEPackedSingle>, TB, VEX;
691 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
692 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
693 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
694 "movups", SSEPackedSingle>, TB, VEX;
695 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
696 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
697 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
698 "movaps", SSEPackedSingle>, TB;
699 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
700 "movapd", SSEPackedDouble>, TB, OpSize;
701 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
702 "movups", SSEPackedSingle>, TB;
703 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
704 "movupd", SSEPackedDouble, 0>, TB, OpSize;
706 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
707 "movaps\t{$src, $dst|$dst, $src}",
708 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
709 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
710 "movapd\t{$src, $dst|$dst, $src}",
711 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
712 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
713 "movups\t{$src, $dst|$dst, $src}",
714 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
715 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
716 "movupd\t{$src, $dst|$dst, $src}",
717 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
718 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
719 "movaps\t{$src, $dst|$dst, $src}",
720 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)]>, VEX;
721 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
722 "movapd\t{$src, $dst|$dst, $src}",
723 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)]>, VEX;
724 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
725 "movups\t{$src, $dst|$dst, $src}",
726 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
727 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
728 "movupd\t{$src, $dst|$dst, $src}",
729 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
732 let isCodeGenOnly = 1 in {
733 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
735 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
736 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
738 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
739 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
741 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
742 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
744 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
745 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
747 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
748 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
750 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
751 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
753 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
754 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
756 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
759 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
760 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
761 (VMOVUPSYmr addr:$dst, VR256:$src)>;
763 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
764 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
765 (VMOVUPDYmr addr:$dst, VR256:$src)>;
767 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
768 "movaps\t{$src, $dst|$dst, $src}",
769 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
770 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
771 "movapd\t{$src, $dst|$dst, $src}",
772 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
773 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
774 "movups\t{$src, $dst|$dst, $src}",
775 [(store (v4f32 VR128:$src), addr:$dst)]>;
776 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
777 "movupd\t{$src, $dst|$dst, $src}",
778 [(store (v2f64 VR128:$src), addr:$dst)]>;
781 let isCodeGenOnly = 1 in {
782 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
783 "movaps\t{$src, $dst|$dst, $src}", []>;
784 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
785 "movapd\t{$src, $dst|$dst, $src}", []>;
786 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
787 "movups\t{$src, $dst|$dst, $src}", []>;
788 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
789 "movupd\t{$src, $dst|$dst, $src}", []>;
792 let Predicates = [HasAVX] in {
793 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
794 (VMOVUPSmr addr:$dst, VR128:$src)>;
795 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
796 (VMOVUPDmr addr:$dst, VR128:$src)>;
799 let Predicates = [HasSSE1] in
800 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
801 (MOVUPSmr addr:$dst, VR128:$src)>;
802 let Predicates = [HasSSE2] in
803 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
804 (MOVUPDmr addr:$dst, VR128:$src)>;
806 // Use movaps / movups for SSE integer load / store (one byte shorter).
807 // The instructions selected below are then converted to MOVDQA/MOVDQU
808 // during the SSE domain pass.
809 let Predicates = [HasSSE1] in {
810 def : Pat<(alignedloadv4i32 addr:$src),
811 (MOVAPSrm addr:$src)>;
812 def : Pat<(loadv4i32 addr:$src),
813 (MOVUPSrm addr:$src)>;
814 def : Pat<(alignedloadv2i64 addr:$src),
815 (MOVAPSrm addr:$src)>;
816 def : Pat<(loadv2i64 addr:$src),
817 (MOVUPSrm addr:$src)>;
819 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
820 (MOVAPSmr addr:$dst, VR128:$src)>;
821 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
822 (MOVAPSmr addr:$dst, VR128:$src)>;
823 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
824 (MOVAPSmr addr:$dst, VR128:$src)>;
825 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
826 (MOVAPSmr addr:$dst, VR128:$src)>;
827 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
828 (MOVUPSmr addr:$dst, VR128:$src)>;
829 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
830 (MOVUPSmr addr:$dst, VR128:$src)>;
831 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
832 (MOVUPSmr addr:$dst, VR128:$src)>;
833 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
834 (MOVUPSmr addr:$dst, VR128:$src)>;
837 // Use vmovaps/vmovups for AVX integer load/store.
838 let Predicates = [HasAVX] in {
839 // 128-bit load/store
840 def : Pat<(alignedloadv4i32 addr:$src),
841 (VMOVAPSrm addr:$src)>;
842 def : Pat<(loadv4i32 addr:$src),
843 (VMOVUPSrm addr:$src)>;
844 def : Pat<(alignedloadv2i64 addr:$src),
845 (VMOVAPSrm addr:$src)>;
846 def : Pat<(loadv2i64 addr:$src),
847 (VMOVUPSrm addr:$src)>;
849 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
850 (VMOVAPSmr addr:$dst, VR128:$src)>;
851 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
852 (VMOVAPSmr addr:$dst, VR128:$src)>;
853 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
854 (VMOVAPSmr addr:$dst, VR128:$src)>;
855 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
856 (VMOVAPSmr addr:$dst, VR128:$src)>;
857 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
858 (VMOVUPSmr addr:$dst, VR128:$src)>;
859 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
860 (VMOVUPSmr addr:$dst, VR128:$src)>;
861 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
862 (VMOVUPSmr addr:$dst, VR128:$src)>;
863 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
864 (VMOVUPSmr addr:$dst, VR128:$src)>;
866 // 256-bit load/store
867 def : Pat<(alignedloadv4i64 addr:$src),
868 (VMOVAPSYrm addr:$src)>;
869 def : Pat<(loadv4i64 addr:$src),
870 (VMOVUPSYrm addr:$src)>;
871 def : Pat<(alignedloadv8i32 addr:$src),
872 (VMOVAPSYrm addr:$src)>;
873 def : Pat<(loadv8i32 addr:$src),
874 (VMOVUPSYrm addr:$src)>;
875 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
876 (VMOVAPSYmr addr:$dst, VR256:$src)>;
877 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
878 (VMOVAPSYmr addr:$dst, VR256:$src)>;
879 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
880 (VMOVAPSYmr addr:$dst, VR256:$src)>;
881 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
882 (VMOVAPSYmr addr:$dst, VR256:$src)>;
883 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
884 (VMOVUPSYmr addr:$dst, VR256:$src)>;
885 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
886 (VMOVUPSYmr addr:$dst, VR256:$src)>;
887 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
888 (VMOVUPSYmr addr:$dst, VR256:$src)>;
889 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
890 (VMOVUPSYmr addr:$dst, VR256:$src)>;
893 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
894 // bits are disregarded. FIXME: Set encoding to pseudo!
895 let neverHasSideEffects = 1 in {
896 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
897 "movaps\t{$src, $dst|$dst, $src}", []>;
898 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
899 "movapd\t{$src, $dst|$dst, $src}", []>;
900 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
901 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
902 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
903 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
906 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
907 // bits are disregarded. FIXME: Set encoding to pseudo!
908 let canFoldAsLoad = 1, isReMaterializable = 1 in {
909 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
910 "movaps\t{$src, $dst|$dst, $src}",
911 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
912 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
913 "movapd\t{$src, $dst|$dst, $src}",
914 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
915 let isCodeGenOnly = 1 in {
916 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
917 "movaps\t{$src, $dst|$dst, $src}",
918 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>, VEX;
919 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
920 "movapd\t{$src, $dst|$dst, $src}",
921 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>, VEX;
925 //===----------------------------------------------------------------------===//
926 // SSE 1 & 2 - Move Low packed FP Instructions
927 //===----------------------------------------------------------------------===//
929 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
930 PatFrag mov_frag, string base_opc,
932 def PSrm : PI<opc, MRMSrcMem,
933 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
934 !strconcat(base_opc, "s", asm_opr),
937 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
938 SSEPackedSingle>, TB;
940 def PDrm : PI<opc, MRMSrcMem,
941 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
942 !strconcat(base_opc, "d", asm_opr),
943 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
944 (scalar_to_vector (loadf64 addr:$src2)))))],
945 SSEPackedDouble>, TB, OpSize;
948 let AddedComplexity = 20 in {
949 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
950 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
952 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
953 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
954 "\t{$src2, $dst|$dst, $src2}">;
957 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
958 "movlps\t{$src, $dst|$dst, $src}",
959 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
960 (iPTR 0))), addr:$dst)]>, VEX;
961 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
962 "movlpd\t{$src, $dst|$dst, $src}",
963 [(store (f64 (vector_extract (v2f64 VR128:$src),
964 (iPTR 0))), addr:$dst)]>, VEX;
965 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
966 "movlps\t{$src, $dst|$dst, $src}",
967 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
968 (iPTR 0))), addr:$dst)]>;
969 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
970 "movlpd\t{$src, $dst|$dst, $src}",
971 [(store (f64 (vector_extract (v2f64 VR128:$src),
972 (iPTR 0))), addr:$dst)]>;
974 let Predicates = [HasAVX] in {
975 let AddedComplexity = 20 in {
976 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
977 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
978 (VMOVLPSrm VR128:$src1, addr:$src2)>;
979 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
980 (VMOVLPSrm VR128:$src1, addr:$src2)>;
981 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
982 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
983 (VMOVLPDrm VR128:$src1, addr:$src2)>;
984 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
985 (VMOVLPDrm VR128:$src1, addr:$src2)>;
988 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
989 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
990 (VMOVLPSmr addr:$src1, VR128:$src2)>;
991 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
992 VR128:$src2)), addr:$src1),
993 (VMOVLPSmr addr:$src1, VR128:$src2)>;
995 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
996 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
997 (VMOVLPDmr addr:$src1, VR128:$src2)>;
998 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
999 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1001 // Shuffle with VMOVLPS
1002 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1003 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1004 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1005 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1006 def : Pat<(X86Movlps VR128:$src1,
1007 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1008 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1010 // Shuffle with VMOVLPD
1011 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1012 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1013 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1014 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1015 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1016 (scalar_to_vector (loadf64 addr:$src2)))),
1017 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1020 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1022 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1023 def : Pat<(store (v4i32 (X86Movlps
1024 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1025 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1026 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1028 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1029 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1031 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1034 let Predicates = [HasSSE1] in {
1035 let AddedComplexity = 20 in {
1036 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
1037 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
1038 (MOVLPSrm VR128:$src1, addr:$src2)>;
1039 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
1040 (MOVLPSrm VR128:$src1, addr:$src2)>;
1043 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1044 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1045 (MOVLPSmr addr:$src1, VR128:$src2)>;
1046 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
1047 VR128:$src2)), addr:$src1),
1048 (MOVLPSmr addr:$src1, VR128:$src2)>;
1050 // Shuffle with MOVLPS
1051 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1052 (MOVLPSrm VR128:$src1, addr:$src2)>;
1053 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1054 (MOVLPSrm VR128:$src1, addr:$src2)>;
1055 def : Pat<(X86Movlps VR128:$src1,
1056 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1057 (MOVLPSrm VR128:$src1, addr:$src2)>;
1060 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1062 (MOVLPSmr addr:$src1, VR128:$src2)>;
1063 def : Pat<(store (v4i32 (X86Movlps
1064 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1066 (MOVLPSmr addr:$src1, VR128:$src2)>;
1069 let Predicates = [HasSSE2] in {
1070 let AddedComplexity = 20 in {
1071 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
1072 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
1073 (MOVLPDrm VR128:$src1, addr:$src2)>;
1074 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
1075 (MOVLPDrm VR128:$src1, addr:$src2)>;
1078 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
1079 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1080 (MOVLPDmr addr:$src1, VR128:$src2)>;
1081 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1082 (MOVLPDmr addr:$src1, VR128:$src2)>;
1084 // Shuffle with MOVLPD
1085 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1086 (MOVLPDrm VR128:$src1, addr:$src2)>;
1087 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1088 (MOVLPDrm VR128:$src1, addr:$src2)>;
1089 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1090 (scalar_to_vector (loadf64 addr:$src2)))),
1091 (MOVLPDrm VR128:$src1, addr:$src2)>;
1094 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1096 (MOVLPDmr addr:$src1, VR128:$src2)>;
1097 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1099 (MOVLPDmr addr:$src1, VR128:$src2)>;
1102 //===----------------------------------------------------------------------===//
1103 // SSE 1 & 2 - Move Hi packed FP Instructions
1104 //===----------------------------------------------------------------------===//
1106 let AddedComplexity = 20 in {
1107 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1108 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
1110 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1111 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1112 "\t{$src2, $dst|$dst, $src2}">;
1115 // v2f64 extract element 1 is always custom lowered to unpack high to low
1116 // and extract element 0 so the non-store version isn't too horrible.
1117 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1118 "movhps\t{$src, $dst|$dst, $src}",
1119 [(store (f64 (vector_extract
1120 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1121 (undef)), (iPTR 0))), addr:$dst)]>,
1123 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1124 "movhpd\t{$src, $dst|$dst, $src}",
1125 [(store (f64 (vector_extract
1126 (v2f64 (unpckh VR128:$src, (undef))),
1127 (iPTR 0))), addr:$dst)]>,
1129 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1130 "movhps\t{$src, $dst|$dst, $src}",
1131 [(store (f64 (vector_extract
1132 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1133 (undef)), (iPTR 0))), addr:$dst)]>;
1134 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1135 "movhpd\t{$src, $dst|$dst, $src}",
1136 [(store (f64 (vector_extract
1137 (v2f64 (unpckh VR128:$src, (undef))),
1138 (iPTR 0))), addr:$dst)]>;
1140 let Predicates = [HasAVX] in {
1142 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1143 (VMOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1144 def : Pat<(X86Movlhps VR128:$src1,
1145 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1146 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1147 def : Pat<(X86Movlhps VR128:$src1,
1148 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1149 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1151 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
1152 // is during lowering, where it's not possible to recognize the load fold cause
1153 // it has two uses through a bitcast. One use disappears at isel time and the
1154 // fold opportunity reappears.
1155 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
1156 (scalar_to_vector (loadf64 addr:$src2)))),
1157 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1159 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1160 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1161 (scalar_to_vector (loadf64 addr:$src2)))),
1162 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1165 def : Pat<(store (f64 (vector_extract
1166 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1167 (VMOVHPSmr addr:$dst, VR128:$src)>;
1168 def : Pat<(store (f64 (vector_extract
1169 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1170 (VMOVHPDmr addr:$dst, VR128:$src)>;
1173 let Predicates = [HasSSE1] in {
1175 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1176 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1177 def : Pat<(X86Movlhps VR128:$src1,
1178 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1179 (MOVHPSrm VR128:$src1, addr:$src2)>;
1180 def : Pat<(X86Movlhps VR128:$src1,
1181 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1182 (MOVHPSrm VR128:$src1, addr:$src2)>;
1185 def : Pat<(store (f64 (vector_extract
1186 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1187 (MOVHPSmr addr:$dst, VR128:$src)>;
1190 let Predicates = [HasSSE2] in {
1191 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
1192 // is during lowering, where it's not possible to recognize the load fold cause
1193 // it has two uses through a bitcast. One use disappears at isel time and the
1194 // fold opportunity reappears.
1195 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
1196 (scalar_to_vector (loadf64 addr:$src2)))),
1197 (MOVHPDrm VR128:$src1, addr:$src2)>;
1199 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1200 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1201 (scalar_to_vector (loadf64 addr:$src2)))),
1202 (MOVHPDrm VR128:$src1, addr:$src2)>;
1205 def : Pat<(store (f64 (vector_extract
1206 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
1207 (MOVHPDmr addr:$dst, VR128:$src)>;
1210 //===----------------------------------------------------------------------===//
1211 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1212 //===----------------------------------------------------------------------===//
1214 let AddedComplexity = 20 in {
1215 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1216 (ins VR128:$src1, VR128:$src2),
1217 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1219 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
1221 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1222 (ins VR128:$src1, VR128:$src2),
1223 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1225 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
1228 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1229 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1230 (ins VR128:$src1, VR128:$src2),
1231 "movlhps\t{$src2, $dst|$dst, $src2}",
1233 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
1234 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1235 (ins VR128:$src1, VR128:$src2),
1236 "movhlps\t{$src2, $dst|$dst, $src2}",
1238 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
1241 let Predicates = [HasAVX] in {
1243 let AddedComplexity = 20 in {
1244 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1245 (VMOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1246 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1247 (VMOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1249 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
1250 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
1251 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1253 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
1254 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1255 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1256 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1257 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1258 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1261 let AddedComplexity = 20 in {
1262 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
1263 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
1264 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1266 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
1267 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
1268 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
1269 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
1270 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
1273 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
1274 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1275 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1276 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1279 let Predicates = [HasSSE1] in {
1281 let AddedComplexity = 20 in {
1282 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1283 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1284 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1285 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1287 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
1288 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
1289 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1291 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
1292 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1293 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1294 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1295 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1296 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1299 let AddedComplexity = 20 in {
1300 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
1301 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
1302 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1304 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
1305 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
1306 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
1307 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
1308 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
1311 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
1312 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1313 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1314 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1317 //===----------------------------------------------------------------------===//
1318 // SSE 1 & 2 - Conversion Instructions
1319 //===----------------------------------------------------------------------===//
1321 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1322 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1324 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1325 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
1326 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1327 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
1330 multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1331 X86MemOperand x86memop, string asm> {
1332 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm, []>;
1334 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm, []>;
1337 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1338 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1339 string asm, Domain d> {
1340 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1341 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
1342 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1343 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
1346 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1347 X86MemOperand x86memop, string asm> {
1348 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1349 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1351 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1352 (ins DstRC:$src1, x86memop:$src),
1353 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1356 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1357 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
1358 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1359 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1361 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1362 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
1363 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1364 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
1367 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1368 // register, but the same isn't true when only using memory operands,
1369 // provide other assembly "l" and "q" forms to address this explicitly
1370 // where appropriate to do so.
1371 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
1373 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
1375 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
1377 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
1379 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
1382 let Predicates = [HasAVX] in {
1383 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1384 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1385 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1386 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1387 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1388 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1389 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1390 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1392 def : Pat<(f32 (sint_to_fp GR32:$src)),
1393 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1394 def : Pat<(f32 (sint_to_fp GR64:$src)),
1395 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1396 def : Pat<(f64 (sint_to_fp GR32:$src)),
1397 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1398 def : Pat<(f64 (sint_to_fp GR64:$src)),
1399 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1402 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1403 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
1404 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1405 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1406 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1407 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
1408 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1409 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1410 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1411 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
1412 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1413 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1414 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1415 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
1416 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1417 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1419 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1420 // and/or XMM operand(s).
1422 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1423 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
1425 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1426 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1427 [(set DstRC:$dst, (Int SrcRC:$src))]>;
1428 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
1429 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1430 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
1433 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1434 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1435 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
1436 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1438 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1439 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1440 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
1441 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1442 (ins DstRC:$src1, x86memop:$src2),
1444 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1445 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1446 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
1449 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1450 f128mem, load, "cvtsd2si">, XD, VEX;
1451 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1452 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
1455 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
1456 // Get rid of this hack or rename the intrinsics, there are several
1457 // intructions that only match with the intrinsic form, why create duplicates
1458 // to let them be recognized by the assembler?
1459 defm VCVTSD2SI : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
1460 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
1461 defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
1462 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
1464 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1465 f128mem, load, "cvtsd2si{l}">, XD;
1466 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1467 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
1470 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1471 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
1472 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1473 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
1475 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1476 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
1477 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1478 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
1481 let Constraints = "$src1 = $dst" in {
1482 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1483 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1485 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1486 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1487 "cvtsi2ss{q}">, XS, REX_W;
1488 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1489 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1491 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1492 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1493 "cvtsi2sd">, XD, REX_W;
1498 // Aliases for intrinsics
1499 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1500 f32mem, load, "cvttss2si">, XS, VEX;
1501 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1502 int_x86_sse_cvttss2si64, f32mem, load,
1503 "cvttss2si">, XS, VEX, VEX_W;
1504 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1505 f128mem, load, "cvttsd2si">, XD, VEX;
1506 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1507 int_x86_sse2_cvttsd2si64, f128mem, load,
1508 "cvttsd2si">, XD, VEX, VEX_W;
1509 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1510 f32mem, load, "cvttss2si">, XS;
1511 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1512 int_x86_sse_cvttss2si64, f32mem, load,
1513 "cvttss2si{q}">, XS, REX_W;
1514 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1515 f128mem, load, "cvttsd2si">, XD;
1516 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1517 int_x86_sse2_cvttsd2si64, f128mem, load,
1518 "cvttsd2si{q}">, XD, REX_W;
1520 let Pattern = []<dag> in {
1521 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
1522 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
1523 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
1524 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1526 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
1527 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1528 SSEPackedSingle>, TB, VEX;
1529 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
1530 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1531 SSEPackedSingle>, TB, VEX;
1534 let Pattern = []<dag> in {
1535 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
1536 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
1537 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
1538 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1539 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
1540 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1541 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
1544 let Predicates = [HasSSE1] in {
1545 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1546 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1547 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1548 (CVTSS2SIrm addr:$src)>;
1549 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1550 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1551 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1552 (CVTSS2SI64rm addr:$src)>;
1555 let Predicates = [HasAVX] in {
1556 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1557 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1558 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1559 (VCVTSS2SIrm addr:$src)>;
1560 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1561 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1562 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1563 (VCVTSS2SI64rm addr:$src)>;
1568 // Convert scalar double to scalar single
1569 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1570 (ins FR64:$src1, FR64:$src2),
1571 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
1574 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1575 (ins FR64:$src1, f64mem:$src2),
1576 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1577 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
1579 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1582 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1583 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1584 [(set FR32:$dst, (fround FR64:$src))]>;
1585 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1586 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1587 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1588 Requires<[HasSSE2, OptForSize]>;
1590 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1591 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
1593 let Constraints = "$src1 = $dst" in
1594 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1595 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
1597 // Convert scalar single to scalar double
1598 // SSE2 instructions with XS prefix
1599 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1600 (ins FR32:$src1, FR32:$src2),
1601 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1602 []>, XS, Requires<[HasAVX]>, VEX_4V;
1604 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1605 (ins FR32:$src1, f32mem:$src2),
1606 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1607 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
1609 let Predicates = [HasAVX] in {
1610 def : Pat<(f64 (fextend FR32:$src)),
1611 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
1612 def : Pat<(fextend (loadf32 addr:$src)),
1613 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1614 def : Pat<(extloadf32 addr:$src),
1615 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1618 def : Pat<(extloadf32 addr:$src),
1619 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (MOVSSrm addr:$src))>,
1620 Requires<[HasAVX, OptForSpeed]>;
1622 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1623 "cvtss2sd\t{$src, $dst|$dst, $src}",
1624 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1625 Requires<[HasSSE2]>;
1626 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1627 "cvtss2sd\t{$src, $dst|$dst, $src}",
1628 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1629 Requires<[HasSSE2, OptForSize]>;
1631 // extload f32 -> f64. This matches load+fextend because we have a hack in
1632 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1634 // Since these loads aren't folded into the fextend, we have to match it
1636 def : Pat<(fextend (loadf32 addr:$src)),
1637 (CVTSS2SDrm addr:$src)>, Requires<[HasSSE2]>;
1638 def : Pat<(extloadf32 addr:$src),
1639 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1641 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1642 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1643 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1644 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1645 VR128:$src2))]>, XS, VEX_4V,
1647 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1648 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1649 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1650 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1651 (load addr:$src2)))]>, XS, VEX_4V,
1653 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1654 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1655 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1656 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1657 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1658 VR128:$src2))]>, XS,
1659 Requires<[HasSSE2]>;
1660 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1661 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1662 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1663 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1664 (load addr:$src2)))]>, XS,
1665 Requires<[HasSSE2]>;
1668 // Convert doubleword to packed single/double fp
1669 // SSE2 instructions without OpSize prefix
1670 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1671 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1672 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1673 TB, VEX, Requires<[HasAVX]>;
1674 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1675 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1676 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1677 (bitconvert (memopv2i64 addr:$src))))]>,
1678 TB, VEX, Requires<[HasAVX]>;
1679 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1680 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1681 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1682 TB, Requires<[HasSSE2]>;
1683 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1684 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1685 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1686 (bitconvert (memopv2i64 addr:$src))))]>,
1687 TB, Requires<[HasSSE2]>;
1689 // FIXME: why the non-intrinsic version is described as SSE3?
1690 // SSE2 instructions with XS prefix
1691 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1692 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1693 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1694 XS, VEX, Requires<[HasAVX]>;
1695 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1696 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1697 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1698 (bitconvert (memopv2i64 addr:$src))))]>,
1699 XS, VEX, Requires<[HasAVX]>;
1700 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1701 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1702 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1703 XS, Requires<[HasSSE2]>;
1704 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1705 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1706 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1707 (bitconvert (memopv2i64 addr:$src))))]>,
1708 XS, Requires<[HasSSE2]>;
1711 // Convert packed single/double fp to doubleword
1712 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1713 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1714 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1715 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1716 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1717 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1718 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1719 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1720 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1721 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1722 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1723 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1725 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1726 "cvtps2dq\t{$src, $dst|$dst, $src}",
1727 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
1729 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1731 "cvtps2dq\t{$src, $dst|$dst, $src}",
1732 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1733 (memop addr:$src)))]>, VEX;
1734 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1735 "cvtps2dq\t{$src, $dst|$dst, $src}",
1736 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1737 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1738 "cvtps2dq\t{$src, $dst|$dst, $src}",
1739 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1740 (memop addr:$src)))]>;
1742 // SSE2 packed instructions with XD prefix
1743 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1744 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1745 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1746 XD, VEX, Requires<[HasAVX]>;
1747 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1748 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1749 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1750 (memop addr:$src)))]>,
1751 XD, VEX, Requires<[HasAVX]>;
1752 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1753 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1754 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1755 XD, Requires<[HasSSE2]>;
1756 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1757 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1758 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1759 (memop addr:$src)))]>,
1760 XD, Requires<[HasSSE2]>;
1763 // Convert with truncation packed single/double fp to doubleword
1764 // SSE2 packed instructions with XS prefix
1765 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1766 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1768 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1769 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1770 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1771 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1773 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1774 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1775 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1776 "cvttps2dq\t{$src, $dst|$dst, $src}",
1778 (int_x86_sse2_cvttps2dq VR128:$src))]>;
1779 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1780 "cvttps2dq\t{$src, $dst|$dst, $src}",
1782 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
1784 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1785 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1787 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1788 XS, VEX, Requires<[HasAVX]>;
1789 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1790 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1791 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1792 (memop addr:$src)))]>,
1793 XS, VEX, Requires<[HasAVX]>;
1795 let Predicates = [HasSSE2] in {
1796 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1797 (Int_CVTDQ2PSrr VR128:$src)>;
1798 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1799 (CVTTPS2DQrr VR128:$src)>;
1802 let Predicates = [HasAVX] in {
1803 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1804 (Int_VCVTDQ2PSrr VR128:$src)>;
1805 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1806 (VCVTTPS2DQrr VR128:$src)>;
1807 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1808 (VCVTDQ2PSYrr VR256:$src)>;
1809 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1810 (VCVTTPS2DQYrr VR256:$src)>;
1813 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1814 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1816 (int_x86_sse2_cvttpd2dq VR128:$src))]>, VEX;
1817 let isCodeGenOnly = 1 in
1818 def VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1819 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1820 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1821 (memop addr:$src)))]>, VEX;
1822 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1823 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1824 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1825 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1826 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1827 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1828 (memop addr:$src)))]>;
1830 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1831 // register, but the same isn't true when using memory operands instead.
1832 // Provide other assembly rr and rm forms to address this explicitly.
1833 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1834 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1837 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1838 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1839 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1840 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1843 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1844 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
1845 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1846 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1848 // Convert packed single to packed double
1849 let Predicates = [HasAVX] in {
1850 // SSE2 instructions without OpSize prefix
1851 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1852 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1853 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1854 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1855 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1856 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1857 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1858 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1860 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1861 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1862 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1863 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1865 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1866 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1867 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1868 TB, VEX, Requires<[HasAVX]>;
1869 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1870 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1871 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1872 (load addr:$src)))]>,
1873 TB, VEX, Requires<[HasAVX]>;
1874 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1875 "cvtps2pd\t{$src, $dst|$dst, $src}",
1876 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1877 TB, Requires<[HasSSE2]>;
1878 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1879 "cvtps2pd\t{$src, $dst|$dst, $src}",
1880 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1881 (load addr:$src)))]>,
1882 TB, Requires<[HasSSE2]>;
1884 // Convert packed double to packed single
1885 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1886 // register, but the same isn't true when using memory operands instead.
1887 // Provide other assembly rr and rm forms to address this explicitly.
1888 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1889 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1890 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1891 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1894 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1895 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1896 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1897 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1900 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1901 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1902 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1903 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1904 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1905 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1906 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1907 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1910 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1911 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1912 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1913 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1915 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1916 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1917 (memop addr:$src)))]>;
1918 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1919 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1920 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1921 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1922 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1923 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1924 (memop addr:$src)))]>;
1926 // AVX 256-bit register conversion intrinsics
1927 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1928 // whenever possible to avoid declaring two versions of each one.
1929 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1930 (VCVTDQ2PSYrr VR256:$src)>;
1931 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
1932 (VCVTDQ2PSYrm addr:$src)>;
1934 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1935 (VCVTPD2PSYrr VR256:$src)>;
1936 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1937 (VCVTPD2PSYrm addr:$src)>;
1939 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1940 (VCVTPS2DQYrr VR256:$src)>;
1941 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1942 (VCVTPS2DQYrm addr:$src)>;
1944 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1945 (VCVTPS2PDYrr VR128:$src)>;
1946 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1947 (VCVTPS2PDYrm addr:$src)>;
1949 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1950 (VCVTTPD2DQYrr VR256:$src)>;
1951 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1952 (VCVTTPD2DQYrm addr:$src)>;
1954 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1955 (VCVTTPS2DQYrr VR256:$src)>;
1956 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1957 (VCVTTPS2DQYrm addr:$src)>;
1959 // Match fround and fextend for 128/256-bit conversions
1960 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
1961 (VCVTPD2PSYrr VR256:$src)>;
1962 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
1963 (VCVTPD2PSYrm addr:$src)>;
1965 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
1966 (VCVTPS2PDYrr VR128:$src)>;
1967 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
1968 (VCVTPS2PDYrm addr:$src)>;
1970 //===----------------------------------------------------------------------===//
1971 // SSE 1 & 2 - Compare Instructions
1972 //===----------------------------------------------------------------------===//
1974 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1975 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1976 SDNode OpNode, ValueType VT, PatFrag ld_frag,
1977 string asm, string asm_alt> {
1978 def rr : SIi8<0xC2, MRMSrcReg,
1979 (outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
1980 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))]>;
1981 def rm : SIi8<0xC2, MRMSrcMem,
1982 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, SSECC:$cc), asm,
1983 [(set RC:$dst, (OpNode (VT RC:$src1),
1984 (ld_frag addr:$src2), imm:$cc))]>;
1986 // Accept explicit immediate argument form instead of comparison code.
1987 let neverHasSideEffects = 1 in {
1988 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
1989 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, []>;
1991 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
1992 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, []>;
1996 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, X86cmpss, f32, loadf32,
1997 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1998 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
2000 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, X86cmpsd, f64, loadf64,
2001 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2002 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
2005 let Constraints = "$src1 = $dst" in {
2006 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, X86cmpss, f32, loadf32,
2007 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2008 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}">,
2010 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, X86cmpsd, f64, loadf64,
2011 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2012 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}">,
2016 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
2017 Intrinsic Int, string asm> {
2018 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2019 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
2020 [(set VR128:$dst, (Int VR128:$src1,
2021 VR128:$src, imm:$cc))]>;
2022 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2023 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
2024 [(set VR128:$dst, (Int VR128:$src1,
2025 (load addr:$src), imm:$cc))]>;
2028 // Aliases to match intrinsics which expect XMM operand(s).
2029 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2030 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
2032 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2033 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
2035 let Constraints = "$src1 = $dst" in {
2036 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2037 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
2038 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2039 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
2043 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2044 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2045 ValueType vt, X86MemOperand x86memop,
2046 PatFrag ld_frag, string OpcodeStr, Domain d> {
2047 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2048 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2049 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
2050 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2051 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2052 [(set EFLAGS, (OpNode (vt RC:$src1),
2053 (ld_frag addr:$src2)))], d>;
2056 let Defs = [EFLAGS] in {
2057 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2058 "ucomiss", SSEPackedSingle>, TB, VEX;
2059 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2060 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2061 let Pattern = []<dag> in {
2062 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2063 "comiss", SSEPackedSingle>, TB, VEX;
2064 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2065 "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2068 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2069 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2070 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2071 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2073 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2074 load, "comiss", SSEPackedSingle>, TB, VEX;
2075 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2076 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2077 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2078 "ucomiss", SSEPackedSingle>, TB;
2079 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2080 "ucomisd", SSEPackedDouble>, TB, OpSize;
2082 let Pattern = []<dag> in {
2083 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2084 "comiss", SSEPackedSingle>, TB;
2085 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2086 "comisd", SSEPackedDouble>, TB, OpSize;
2089 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2090 load, "ucomiss", SSEPackedSingle>, TB;
2091 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2092 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2094 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2095 "comiss", SSEPackedSingle>, TB;
2096 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2097 "comisd", SSEPackedDouble>, TB, OpSize;
2098 } // Defs = [EFLAGS]
2100 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
2101 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2102 Intrinsic Int, string asm, string asm_alt,
2104 let isAsmParserOnly = 1 in {
2105 def rri : PIi8<0xC2, MRMSrcReg,
2106 (outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
2107 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))], d>;
2108 def rmi : PIi8<0xC2, MRMSrcMem,
2109 (outs RC:$dst), (ins RC:$src1, f128mem:$src2, SSECC:$cc), asm,
2110 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))], d>;
2113 // Accept explicit immediate argument form instead of comparison code.
2114 def rri_alt : PIi8<0xC2, MRMSrcReg,
2115 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2117 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2118 (outs RC:$dst), (ins RC:$src1, f128mem:$src2, i8imm:$cc),
2122 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2123 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2124 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2125 SSEPackedSingle>, TB, VEX_4V;
2126 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2127 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2128 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2129 SSEPackedDouble>, TB, OpSize, VEX_4V;
2130 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
2131 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2132 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2133 SSEPackedSingle>, TB, VEX_4V;
2134 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
2135 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2136 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2137 SSEPackedDouble>, TB, OpSize, VEX_4V;
2138 let Constraints = "$src1 = $dst" in {
2139 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2140 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2141 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2142 SSEPackedSingle>, TB;
2143 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2144 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2145 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2146 SSEPackedDouble>, TB, OpSize;
2149 let Predicates = [HasSSE1] in {
2150 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2151 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2152 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2153 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2156 let Predicates = [HasSSE2] in {
2157 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2158 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2159 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2160 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2163 let Predicates = [HasAVX] in {
2164 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2165 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2166 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2167 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2168 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2169 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2170 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2171 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2173 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2174 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2175 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2176 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2177 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2178 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2179 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2180 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2183 //===----------------------------------------------------------------------===//
2184 // SSE 1 & 2 - Shuffle Instructions
2185 //===----------------------------------------------------------------------===//
2187 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2188 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2189 ValueType vt, string asm, PatFrag mem_frag,
2190 Domain d, bit IsConvertibleToThreeAddress = 0> {
2191 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2192 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
2193 [(set RC:$dst, (vt (shufp:$src3
2194 RC:$src1, (mem_frag addr:$src2))))], d>;
2195 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2196 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2197 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2199 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
2202 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2203 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2204 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2205 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2206 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2207 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2208 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2209 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2210 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2211 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2212 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2213 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2215 let Constraints = "$src1 = $dst" in {
2216 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2217 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2218 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2220 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2221 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2222 memopv2f64, SSEPackedDouble>, TB, OpSize;
2225 let Predicates = [HasSSE1] in {
2226 def : Pat<(v4f32 (X86Shufps VR128:$src1,
2227 (memopv4f32 addr:$src2), (i8 imm:$imm))),
2228 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2229 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2230 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2231 def : Pat<(v4i32 (X86Shufps VR128:$src1,
2232 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2233 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2234 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2235 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2236 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2237 // fall back to this for SSE1)
2238 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2239 (SHUFPSrri VR128:$src2, VR128:$src1,
2240 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2241 // Special unary SHUFPSrri case.
2242 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2243 (SHUFPSrri VR128:$src1, VR128:$src1,
2244 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2247 let Predicates = [HasSSE2] in {
2248 // Special binary v4i32 shuffle cases with SHUFPS.
2249 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2250 (SHUFPSrri VR128:$src1, VR128:$src2,
2251 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2252 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
2253 (bc_v4i32 (memopv2i64 addr:$src2)))),
2254 (SHUFPSrmi VR128:$src1, addr:$src2,
2255 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2256 // Special unary SHUFPDrri cases.
2257 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2258 (SHUFPDrri VR128:$src1, VR128:$src1,
2259 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2260 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2261 (SHUFPDrri VR128:$src1, VR128:$src1,
2262 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2263 // Special binary v2i64 shuffle cases using SHUFPDrri.
2264 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2265 (SHUFPDrri VR128:$src1, VR128:$src2,
2266 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2267 // Generic SHUFPD patterns
2268 def : Pat<(v2f64 (X86Shufps VR128:$src1,
2269 (memopv2f64 addr:$src2), (i8 imm:$imm))),
2270 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2271 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2272 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2273 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2274 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2277 let Predicates = [HasAVX] in {
2278 def : Pat<(v4f32 (X86Shufps VR128:$src1,
2279 (memopv4f32 addr:$src2), (i8 imm:$imm))),
2280 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2281 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2282 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2283 def : Pat<(v4i32 (X86Shufps VR128:$src1,
2284 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2285 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2286 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2287 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2288 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2289 // fall back to this for SSE1)
2290 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2291 (VSHUFPSrri VR128:$src2, VR128:$src1,
2292 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2293 // Special unary SHUFPSrri case.
2294 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2295 (VSHUFPSrri VR128:$src1, VR128:$src1,
2296 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2297 // Special binary v4i32 shuffle cases with SHUFPS.
2298 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2299 (VSHUFPSrri VR128:$src1, VR128:$src2,
2300 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2301 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
2302 (bc_v4i32 (memopv2i64 addr:$src2)))),
2303 (VSHUFPSrmi VR128:$src1, addr:$src2,
2304 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2305 // Special unary SHUFPDrri cases.
2306 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2307 (VSHUFPDrri VR128:$src1, VR128:$src1,
2308 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2309 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2310 (VSHUFPDrri VR128:$src1, VR128:$src1,
2311 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2312 // Special binary v2i64 shuffle cases using SHUFPDrri.
2313 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2314 (VSHUFPDrri VR128:$src1, VR128:$src2,
2315 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2317 def : Pat<(v2f64 (X86Shufps VR128:$src1,
2318 (memopv2f64 addr:$src2), (i8 imm:$imm))),
2319 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2320 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2321 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2322 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2323 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2326 def : Pat<(v8i32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2327 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2328 def : Pat<(v8i32 (X86Shufps VR256:$src1,
2329 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2330 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2332 def : Pat<(v8f32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2333 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2334 def : Pat<(v8f32 (X86Shufps VR256:$src1,
2335 (memopv8f32 addr:$src2), (i8 imm:$imm))),
2336 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2338 def : Pat<(v4i64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2339 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2340 def : Pat<(v4i64 (X86Shufpd VR256:$src1,
2341 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2342 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2344 def : Pat<(v4f64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2345 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2346 def : Pat<(v4f64 (X86Shufpd VR256:$src1,
2347 (memopv4f64 addr:$src2), (i8 imm:$imm))),
2348 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2351 //===----------------------------------------------------------------------===//
2352 // SSE 1 & 2 - Unpack Instructions
2353 //===----------------------------------------------------------------------===//
2355 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2356 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
2357 PatFrag mem_frag, RegisterClass RC,
2358 X86MemOperand x86memop, string asm,
2360 def rr : PI<opc, MRMSrcReg,
2361 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2363 (vt (OpNode RC:$src1, RC:$src2)))], d>;
2364 def rm : PI<opc, MRMSrcMem,
2365 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2367 (vt (OpNode RC:$src1,
2368 (mem_frag addr:$src2))))], d>;
2371 let AddedComplexity = 10 in {
2372 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2373 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2374 SSEPackedSingle>, TB, VEX_4V;
2375 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2376 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2377 SSEPackedDouble>, TB, OpSize, VEX_4V;
2378 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2379 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2380 SSEPackedSingle>, TB, VEX_4V;
2381 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2382 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2383 SSEPackedDouble>, TB, OpSize, VEX_4V;
2385 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
2386 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2387 SSEPackedSingle>, TB, VEX_4V;
2388 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
2389 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2390 SSEPackedDouble>, TB, OpSize, VEX_4V;
2391 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
2392 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2393 SSEPackedSingle>, TB, VEX_4V;
2394 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
2395 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2396 SSEPackedDouble>, TB, OpSize, VEX_4V;
2398 let Constraints = "$src1 = $dst" in {
2399 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2400 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2401 SSEPackedSingle>, TB;
2402 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2403 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2404 SSEPackedDouble>, TB, OpSize;
2405 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2406 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2407 SSEPackedSingle>, TB;
2408 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2409 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2410 SSEPackedDouble>, TB, OpSize;
2411 } // Constraints = "$src1 = $dst"
2412 } // AddedComplexity
2414 let Predicates = [HasSSE1] in {
2415 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
2416 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
2417 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
2418 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
2419 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
2420 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
2421 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
2422 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
2425 let Predicates = [HasSSE2] in {
2426 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
2427 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
2428 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
2429 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
2430 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
2431 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
2432 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
2433 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
2435 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
2436 // problem is during lowering, where it's not possible to recognize the load
2437 // fold cause it has two uses through a bitcast. One use disappears at isel
2438 // time and the fold opportunity reappears.
2439 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2440 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2442 let AddedComplexity = 10 in
2443 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2444 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2447 let Predicates = [HasAVX] in {
2448 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
2449 (VUNPCKLPSrm VR128:$src1, addr:$src2)>;
2450 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
2451 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>;
2452 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
2453 (VUNPCKHPSrm VR128:$src1, addr:$src2)>;
2454 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
2455 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>;
2457 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
2458 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2459 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
2460 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2461 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
2462 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2463 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, (memopv8i32 addr:$src2))),
2464 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2465 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, (memopv8f32 addr:$src2))),
2466 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2467 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
2468 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2469 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, (memopv8i32 addr:$src2))),
2470 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2471 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
2472 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2474 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
2475 (VUNPCKLPDrm VR128:$src1, addr:$src2)>;
2476 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
2477 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>;
2478 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
2479 (VUNPCKHPDrm VR128:$src1, addr:$src2)>;
2480 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
2481 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>;
2483 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
2484 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2485 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
2486 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2487 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, (memopv4i64 addr:$src2))),
2488 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2489 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
2490 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2491 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, (memopv4f64 addr:$src2))),
2492 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2493 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
2494 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2495 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, (memopv4i64 addr:$src2))),
2496 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2497 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
2498 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2500 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
2501 // problem is during lowering, where it's not possible to recognize the load
2502 // fold cause it has two uses through a bitcast. One use disappears at isel
2503 // time and the fold opportunity reappears.
2504 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2505 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2506 let AddedComplexity = 10 in
2507 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2508 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2511 //===----------------------------------------------------------------------===//
2512 // SSE 1 & 2 - Extract Floating-Point Sign mask
2513 //===----------------------------------------------------------------------===//
2515 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2516 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2518 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2519 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2520 [(set GR32:$dst, (Int RC:$src))], d>;
2521 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2522 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
2525 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2526 SSEPackedSingle>, TB;
2527 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2528 SSEPackedDouble>, TB, OpSize;
2530 def : Pat<(i32 (X86fgetsign FR32:$src)),
2531 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2532 sub_ss))>, Requires<[HasSSE1]>;
2533 def : Pat<(i64 (X86fgetsign FR32:$src)),
2534 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2535 sub_ss))>, Requires<[HasSSE1]>;
2536 def : Pat<(i32 (X86fgetsign FR64:$src)),
2537 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2538 sub_sd))>, Requires<[HasSSE2]>;
2539 def : Pat<(i64 (X86fgetsign FR64:$src)),
2540 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2541 sub_sd))>, Requires<[HasSSE2]>;
2543 let Predicates = [HasAVX] in {
2544 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2545 "movmskps", SSEPackedSingle>, TB, VEX;
2546 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2547 "movmskpd", SSEPackedDouble>, TB,
2549 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2550 "movmskps", SSEPackedSingle>, TB, VEX;
2551 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2552 "movmskpd", SSEPackedDouble>, TB,
2555 def : Pat<(i32 (X86fgetsign FR32:$src)),
2556 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2558 def : Pat<(i64 (X86fgetsign FR32:$src)),
2559 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2561 def : Pat<(i32 (X86fgetsign FR64:$src)),
2562 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2564 def : Pat<(i64 (X86fgetsign FR64:$src)),
2565 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2569 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2570 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2571 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2572 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
2574 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2575 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2576 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2577 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
2581 //===----------------------------------------------------------------------===//
2582 // SSE 1 & 2 - Logical Instructions
2583 //===----------------------------------------------------------------------===//
2585 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2587 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2589 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2590 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, TB, VEX_4V;
2592 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2593 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, TB, OpSize, VEX_4V;
2595 let Constraints = "$src1 = $dst" in {
2596 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2597 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
2599 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2600 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
2604 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2605 let mayLoad = 0 in {
2606 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
2607 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
2608 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
2611 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2612 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
2614 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2616 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2618 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2619 // are all promoted to v2i64, and the patterns are covered by the int
2620 // version. This is needed in SSE only, because v2i64 isn't supported on
2621 // SSE1, but only on SSE2.
2622 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2623 !strconcat(OpcodeStr, "ps"), f128mem, [],
2624 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2625 (memopv2i64 addr:$src2)))], 0>, TB, VEX_4V;
2627 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2628 !strconcat(OpcodeStr, "pd"), f128mem,
2629 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2630 (bc_v2i64 (v2f64 VR128:$src2))))],
2631 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2632 (memopv2i64 addr:$src2)))], 0>,
2634 let Constraints = "$src1 = $dst" in {
2635 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2636 !strconcat(OpcodeStr, "ps"), f128mem,
2637 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2638 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2639 (memopv2i64 addr:$src2)))]>, TB;
2641 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2642 !strconcat(OpcodeStr, "pd"), f128mem,
2643 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2644 (bc_v2i64 (v2f64 VR128:$src2))))],
2645 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2646 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2650 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2652 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2654 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2655 !strconcat(OpcodeStr, "ps"), f256mem,
2656 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2657 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2658 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2660 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2661 !strconcat(OpcodeStr, "pd"), f256mem,
2662 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2663 (bc_v4i64 (v4f64 VR256:$src2))))],
2664 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2665 (memopv4i64 addr:$src2)))], 0>,
2669 // AVX 256-bit packed logical ops forms
2670 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2671 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2672 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2673 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2675 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2676 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2677 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2678 let isCommutable = 0 in
2679 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2681 //===----------------------------------------------------------------------===//
2682 // SSE 1 & 2 - Arithmetic Instructions
2683 //===----------------------------------------------------------------------===//
2685 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2688 /// In addition, we also have a special variant of the scalar form here to
2689 /// represent the associated intrinsic operation. This form is unlike the
2690 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2691 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2693 /// These three forms can each be reg+reg or reg+mem.
2696 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2698 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2700 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2701 OpNode, FR32, f32mem, Is2Addr>, XS;
2702 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2703 OpNode, FR64, f64mem, Is2Addr>, XD;
2706 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2708 let mayLoad = 0 in {
2709 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2710 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
2711 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2712 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
2716 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2718 let mayLoad = 0 in {
2719 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2720 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
2721 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2722 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
2726 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2728 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2729 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
2730 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2731 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
2734 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2736 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2737 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2738 SSEPackedSingle, Is2Addr>, TB;
2740 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2741 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2742 SSEPackedDouble, Is2Addr>, TB, OpSize;
2745 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
2746 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2747 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2748 SSEPackedSingle, 0>, TB;
2750 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2751 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2752 SSEPackedDouble, 0>, TB, OpSize;
2755 // Binary Arithmetic instructions
2756 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
2757 basic_sse12_fp_binop_s_int<0x58, "add", 0>,
2758 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
2759 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
2760 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
2761 basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
2762 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
2763 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
2765 let isCommutable = 0 in {
2766 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
2767 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
2768 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
2769 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
2770 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
2771 basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
2772 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
2773 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
2774 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
2775 basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
2776 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
2777 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
2778 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
2779 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
2780 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
2781 basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
2782 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
2783 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
2784 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
2785 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
2788 let Constraints = "$src1 = $dst" in {
2789 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
2790 basic_sse12_fp_binop_p<0x58, "add", fadd>,
2791 basic_sse12_fp_binop_s_int<0x58, "add">;
2792 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
2793 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
2794 basic_sse12_fp_binop_s_int<0x59, "mul">;
2796 let isCommutable = 0 in {
2797 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
2798 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
2799 basic_sse12_fp_binop_s_int<0x5C, "sub">;
2800 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
2801 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
2802 basic_sse12_fp_binop_s_int<0x5E, "div">;
2803 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
2804 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
2805 basic_sse12_fp_binop_s_int<0x5F, "max">,
2806 basic_sse12_fp_binop_p_int<0x5F, "max">;
2807 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
2808 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
2809 basic_sse12_fp_binop_s_int<0x5D, "min">,
2810 basic_sse12_fp_binop_p_int<0x5D, "min">;
2815 /// In addition, we also have a special variant of the scalar form here to
2816 /// represent the associated intrinsic operation. This form is unlike the
2817 /// plain scalar form, in that it takes an entire vector (instead of a
2818 /// scalar) and leaves the top elements undefined.
2820 /// And, we have a special variant form for a full-vector intrinsic form.
2822 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2823 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2824 SDNode OpNode, Intrinsic F32Int> {
2825 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2826 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2827 [(set FR32:$dst, (OpNode FR32:$src))]>;
2828 // For scalar unary operations, fold a load into the operation
2829 // only in OptForSize mode. It eliminates an instruction, but it also
2830 // eliminates a whole-register clobber (the load), so it introduces a
2831 // partial register update condition.
2832 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
2833 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2834 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
2835 Requires<[HasSSE1, OptForSize]>;
2836 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2837 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2838 [(set VR128:$dst, (F32Int VR128:$src))]>;
2839 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
2840 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2841 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
2844 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
2845 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2846 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
2847 !strconcat(OpcodeStr,
2848 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2850 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
2851 !strconcat(OpcodeStr,
2852 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2853 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
2854 (ins ssmem:$src1, VR128:$src2),
2855 !strconcat(OpcodeStr,
2856 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2859 /// sse1_fp_unop_p - SSE1 unops in packed form.
2860 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2861 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2862 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2863 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
2864 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2865 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2866 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
2869 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
2870 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2871 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2872 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2873 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
2874 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2875 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2876 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
2879 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
2880 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2881 Intrinsic V4F32Int> {
2882 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2883 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2884 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
2885 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2886 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2887 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
2890 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
2891 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2892 Intrinsic V4F32Int> {
2893 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2894 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2895 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
2896 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2897 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2898 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
2901 /// sse2_fp_unop_s - SSE2 unops in scalar form.
2902 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
2903 SDNode OpNode, Intrinsic F64Int> {
2904 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
2905 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2906 [(set FR64:$dst, (OpNode FR64:$src))]>;
2907 // See the comments in sse1_fp_unop_s for why this is OptForSize.
2908 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
2909 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2910 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
2911 Requires<[HasSSE2, OptForSize]>;
2912 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2913 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2914 [(set VR128:$dst, (F64Int VR128:$src))]>;
2915 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
2916 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2917 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
2920 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
2921 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2922 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
2923 !strconcat(OpcodeStr,
2924 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2925 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
2926 !strconcat(OpcodeStr,
2927 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2928 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
2929 (ins VR128:$src1, sdmem:$src2),
2930 !strconcat(OpcodeStr,
2931 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2934 /// sse2_fp_unop_p - SSE2 unops in vector forms.
2935 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
2937 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2938 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2939 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
2940 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2941 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2942 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
2945 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
2946 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2947 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2948 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2949 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
2950 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2951 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2952 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
2955 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
2956 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2957 Intrinsic V2F64Int> {
2958 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2959 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2960 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
2961 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2962 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2963 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
2966 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
2967 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2968 Intrinsic V2F64Int> {
2969 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2970 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2971 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
2972 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2973 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2974 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
2977 let Predicates = [HasAVX] in {
2979 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
2980 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V;
2982 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
2983 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
2984 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
2985 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
2986 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
2987 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
2988 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
2989 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
2992 // Reciprocal approximations. Note that these typically require refinement
2993 // in order to obtain suitable precision.
2994 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V;
2995 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
2996 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
2997 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
2998 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
3000 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V;
3001 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
3002 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
3003 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
3004 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
3007 def : Pat<(f32 (fsqrt FR32:$src)),
3008 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3009 def : Pat<(f32 (fsqrt (load addr:$src))),
3010 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3011 Requires<[HasAVX, OptForSize]>;
3012 def : Pat<(f64 (fsqrt FR64:$src)),
3013 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3014 def : Pat<(f64 (fsqrt (load addr:$src))),
3015 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3016 Requires<[HasAVX, OptForSize]>;
3018 def : Pat<(f32 (X86frsqrt FR32:$src)),
3019 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3020 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3021 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3022 Requires<[HasAVX, OptForSize]>;
3024 def : Pat<(f32 (X86frcp FR32:$src)),
3025 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3026 def : Pat<(f32 (X86frcp (load addr:$src))),
3027 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3028 Requires<[HasAVX, OptForSize]>;
3030 let Predicates = [HasAVX] in {
3031 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3032 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3033 (VSQRTSSr (f32 (IMPLICIT_DEF)),
3034 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3036 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3037 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3039 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3040 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
3041 (VSQRTSDr (f64 (IMPLICIT_DEF)),
3042 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
3044 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3045 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3047 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3048 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3049 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3050 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3052 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3053 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3055 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3056 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3057 (VRCPSSr (f32 (IMPLICIT_DEF)),
3058 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3060 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3061 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3065 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
3066 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
3067 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
3068 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
3069 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
3070 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
3072 // Reciprocal approximations. Note that these typically require refinement
3073 // in order to obtain suitable precision.
3074 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
3075 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
3076 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
3077 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
3078 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
3079 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
3081 // There is no f64 version of the reciprocal approximation instructions.
3083 //===----------------------------------------------------------------------===//
3084 // SSE 1 & 2 - Non-temporal stores
3085 //===----------------------------------------------------------------------===//
3087 let AddedComplexity = 400 in { // Prefer non-temporal versions
3088 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3089 (ins f128mem:$dst, VR128:$src),
3090 "movntps\t{$src, $dst|$dst, $src}",
3091 [(alignednontemporalstore (v4f32 VR128:$src),
3093 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3094 (ins f128mem:$dst, VR128:$src),
3095 "movntpd\t{$src, $dst|$dst, $src}",
3096 [(alignednontemporalstore (v2f64 VR128:$src),
3098 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
3099 (ins f128mem:$dst, VR128:$src),
3100 "movntdq\t{$src, $dst|$dst, $src}",
3101 [(alignednontemporalstore (v2f64 VR128:$src),
3104 let ExeDomain = SSEPackedInt in
3105 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3106 (ins f128mem:$dst, VR128:$src),
3107 "movntdq\t{$src, $dst|$dst, $src}",
3108 [(alignednontemporalstore (v4f32 VR128:$src),
3111 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3112 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3114 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3115 (ins f256mem:$dst, VR256:$src),
3116 "movntps\t{$src, $dst|$dst, $src}",
3117 [(alignednontemporalstore (v8f32 VR256:$src),
3119 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3120 (ins f256mem:$dst, VR256:$src),
3121 "movntpd\t{$src, $dst|$dst, $src}",
3122 [(alignednontemporalstore (v4f64 VR256:$src),
3124 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
3125 (ins f256mem:$dst, VR256:$src),
3126 "movntdq\t{$src, $dst|$dst, $src}",
3127 [(alignednontemporalstore (v4f64 VR256:$src),
3129 let ExeDomain = SSEPackedInt in
3130 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3131 (ins f256mem:$dst, VR256:$src),
3132 "movntdq\t{$src, $dst|$dst, $src}",
3133 [(alignednontemporalstore (v8f32 VR256:$src),
3137 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
3138 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3139 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
3140 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
3141 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
3142 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
3144 let AddedComplexity = 400 in { // Prefer non-temporal versions
3145 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3146 "movntps\t{$src, $dst|$dst, $src}",
3147 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
3148 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3149 "movntpd\t{$src, $dst|$dst, $src}",
3150 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
3152 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3153 "movntdq\t{$src, $dst|$dst, $src}",
3154 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
3156 let ExeDomain = SSEPackedInt in
3157 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3158 "movntdq\t{$src, $dst|$dst, $src}",
3159 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
3161 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3162 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3164 // There is no AVX form for instructions below this point
3165 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3166 "movnti{l}\t{$src, $dst|$dst, $src}",
3167 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
3168 TB, Requires<[HasSSE2]>;
3169 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3170 "movnti{q}\t{$src, $dst|$dst, $src}",
3171 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
3172 TB, Requires<[HasSSE2]>;
3175 //===----------------------------------------------------------------------===//
3176 // SSE 1 & 2 - Prefetch and memory fence
3177 //===----------------------------------------------------------------------===//
3179 // Prefetch intrinsic.
3180 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
3181 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
3182 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
3183 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
3184 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
3185 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
3186 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
3187 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
3190 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3191 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3192 TB, Requires<[HasSSE2]>;
3194 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3195 // was introduced with SSE2, it's backward compatible.
3196 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3198 // Load, store, and memory fence
3199 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3200 "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
3201 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3202 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3203 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3204 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3206 def : Pat<(X86SFence), (SFENCE)>;
3207 def : Pat<(X86LFence), (LFENCE)>;
3208 def : Pat<(X86MFence), (MFENCE)>;
3210 //===----------------------------------------------------------------------===//
3211 // SSE 1 & 2 - Load/Store XCSR register
3212 //===----------------------------------------------------------------------===//
3214 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3215 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
3216 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3217 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
3219 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3220 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
3221 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3222 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
3224 //===---------------------------------------------------------------------===//
3225 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3226 //===---------------------------------------------------------------------===//
3228 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3230 let neverHasSideEffects = 1 in {
3231 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3232 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3233 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3234 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3236 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3237 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3238 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3239 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3242 let isCodeGenOnly = 1 in {
3243 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3244 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3245 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3246 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3247 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3248 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3249 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3250 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3253 let canFoldAsLoad = 1, mayLoad = 1 in {
3254 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3255 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3256 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3257 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3258 let Predicates = [HasAVX] in {
3259 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3260 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3261 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3262 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3266 let mayStore = 1 in {
3267 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3268 (ins i128mem:$dst, VR128:$src),
3269 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3270 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3271 (ins i256mem:$dst, VR256:$src),
3272 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3273 let Predicates = [HasAVX] in {
3274 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3275 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3276 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3277 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3281 let neverHasSideEffects = 1 in
3282 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3283 "movdqa\t{$src, $dst|$dst, $src}", []>;
3285 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3286 "movdqu\t{$src, $dst|$dst, $src}",
3287 []>, XS, Requires<[HasSSE2]>;
3290 let isCodeGenOnly = 1 in {
3291 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3292 "movdqa\t{$src, $dst|$dst, $src}", []>;
3294 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3295 "movdqu\t{$src, $dst|$dst, $src}",
3296 []>, XS, Requires<[HasSSE2]>;
3299 let canFoldAsLoad = 1, mayLoad = 1 in {
3300 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3301 "movdqa\t{$src, $dst|$dst, $src}",
3302 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
3303 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3304 "movdqu\t{$src, $dst|$dst, $src}",
3305 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
3306 XS, Requires<[HasSSE2]>;
3309 let mayStore = 1 in {
3310 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3311 "movdqa\t{$src, $dst|$dst, $src}",
3312 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
3313 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3314 "movdqu\t{$src, $dst|$dst, $src}",
3315 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
3316 XS, Requires<[HasSSE2]>;
3319 // Intrinsic forms of MOVDQU load and store
3320 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3321 "vmovdqu\t{$src, $dst|$dst, $src}",
3322 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3323 XS, VEX, Requires<[HasAVX]>;
3325 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3326 "movdqu\t{$src, $dst|$dst, $src}",
3327 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3328 XS, Requires<[HasSSE2]>;
3330 } // ExeDomain = SSEPackedInt
3332 let Predicates = [HasAVX] in {
3333 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
3334 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3335 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3338 //===---------------------------------------------------------------------===//
3339 // SSE2 - Packed Integer Arithmetic Instructions
3340 //===---------------------------------------------------------------------===//
3342 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3344 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3345 bit IsCommutable = 0, bit Is2Addr = 1> {
3346 let isCommutable = IsCommutable in
3347 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3348 (ins VR128:$src1, VR128:$src2),
3350 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3351 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3352 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
3353 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3354 (ins VR128:$src1, i128mem:$src2),
3356 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3357 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3358 [(set VR128:$dst, (IntId VR128:$src1,
3359 (bitconvert (memopv2i64 addr:$src2))))]>;
3362 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
3363 string OpcodeStr, Intrinsic IntId,
3364 Intrinsic IntId2, bit Is2Addr = 1> {
3365 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3366 (ins VR128:$src1, VR128:$src2),
3368 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3369 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3370 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
3371 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3372 (ins VR128:$src1, i128mem:$src2),
3374 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3375 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3376 [(set VR128:$dst, (IntId VR128:$src1,
3377 (bitconvert (memopv2i64 addr:$src2))))]>;
3378 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
3379 (ins VR128:$src1, i32i8imm:$src2),
3381 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3382 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3383 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
3386 /// PDI_binop_rm - Simple SSE2 binary operator.
3387 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3388 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
3389 let isCommutable = IsCommutable in
3390 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3391 (ins VR128:$src1, VR128:$src2),
3393 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3394 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3395 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
3396 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3397 (ins VR128:$src1, i128mem:$src2),
3399 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3400 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3401 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
3402 (bitconvert (memopv2i64 addr:$src2)))))]>;
3405 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
3407 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
3408 /// to collapse (bitconvert VT to VT) into its operand.
3410 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
3411 bit IsCommutable = 0, bit Is2Addr = 1> {
3412 let isCommutable = IsCommutable in
3413 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3414 (ins VR128:$src1, VR128:$src2),
3416 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3417 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3418 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
3419 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3420 (ins VR128:$src1, i128mem:$src2),
3422 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3423 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3424 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
3427 } // ExeDomain = SSEPackedInt
3429 // 128-bit Integer Arithmetic
3431 let Predicates = [HasAVX] in {
3432 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
3433 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
3434 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
3435 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
3436 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
3437 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
3438 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
3439 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
3440 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
3443 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
3445 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
3447 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
3449 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
3451 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
3453 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
3455 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
3457 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
3459 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
3461 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
3463 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
3465 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
3467 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
3469 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
3471 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
3473 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
3475 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
3477 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
3479 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
3483 let Constraints = "$src1 = $dst" in {
3484 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
3485 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
3486 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
3487 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
3488 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
3489 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
3490 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
3491 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
3492 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
3495 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
3496 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
3497 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
3498 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
3499 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
3500 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
3501 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
3502 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
3503 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
3504 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
3505 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
3506 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
3507 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
3508 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
3509 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
3510 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
3511 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
3512 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
3513 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
3515 } // Constraints = "$src1 = $dst"
3517 //===---------------------------------------------------------------------===//
3518 // SSE2 - Packed Integer Logical Instructions
3519 //===---------------------------------------------------------------------===//
3521 let Predicates = [HasAVX] in {
3522 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
3523 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
3525 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
3526 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
3528 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
3529 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
3532 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
3533 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
3535 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
3536 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
3538 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
3539 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
3542 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
3543 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
3545 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
3546 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
3549 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
3550 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
3551 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
3553 let ExeDomain = SSEPackedInt in {
3554 let neverHasSideEffects = 1 in {
3555 // 128-bit logical shifts.
3556 def VPSLLDQri : PDIi8<0x73, MRM7r,
3557 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3558 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3560 def VPSRLDQri : PDIi8<0x73, MRM3r,
3561 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3562 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3564 // PSRADQri doesn't exist in SSE[1-3].
3566 def VPANDNrr : PDI<0xDF, MRMSrcReg,
3567 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3568 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3570 (v2i64 (X86andnp VR128:$src1, VR128:$src2)))]>,VEX_4V;
3572 def VPANDNrm : PDI<0xDF, MRMSrcMem,
3573 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3574 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3575 [(set VR128:$dst, (X86andnp VR128:$src1,
3576 (memopv2i64 addr:$src2)))]>, VEX_4V;
3580 let Constraints = "$src1 = $dst" in {
3581 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
3582 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
3583 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
3584 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
3585 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
3586 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
3588 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
3589 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
3590 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
3591 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
3592 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
3593 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
3595 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
3596 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
3597 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
3598 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
3600 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
3601 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
3602 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
3604 let ExeDomain = SSEPackedInt in {
3605 let neverHasSideEffects = 1 in {
3606 // 128-bit logical shifts.
3607 def PSLLDQri : PDIi8<0x73, MRM7r,
3608 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3609 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
3610 def PSRLDQri : PDIi8<0x73, MRM3r,
3611 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3612 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
3613 // PSRADQri doesn't exist in SSE[1-3].
3615 def PANDNrr : PDI<0xDF, MRMSrcReg,
3616 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3617 "pandn\t{$src2, $dst|$dst, $src2}", []>;
3619 def PANDNrm : PDI<0xDF, MRMSrcMem,
3620 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3621 "pandn\t{$src2, $dst|$dst, $src2}", []>;
3623 } // Constraints = "$src1 = $dst"
3625 let Predicates = [HasAVX] in {
3626 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3627 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3628 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3629 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3630 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3631 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
3632 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3633 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
3634 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3635 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3637 // Shift up / down and insert zero's.
3638 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3639 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3640 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3641 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3644 let Predicates = [HasSSE2] in {
3645 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3646 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3647 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3648 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3649 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3650 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
3651 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3652 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
3653 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3654 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3656 // Shift up / down and insert zero's.
3657 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3658 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3659 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3660 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3663 //===---------------------------------------------------------------------===//
3664 // SSE2 - Packed Integer Comparison Instructions
3665 //===---------------------------------------------------------------------===//
3667 let Predicates = [HasAVX] in {
3668 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
3670 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
3672 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
3674 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
3676 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
3678 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
3681 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3682 (VPCMPEQBrr VR128:$src1, VR128:$src2)>;
3683 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
3684 (VPCMPEQBrm VR128:$src1, addr:$src2)>;
3685 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3686 (VPCMPEQWrr VR128:$src1, VR128:$src2)>;
3687 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
3688 (VPCMPEQWrm VR128:$src1, addr:$src2)>;
3689 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3690 (VPCMPEQDrr VR128:$src1, VR128:$src2)>;
3691 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
3692 (VPCMPEQDrm VR128:$src1, addr:$src2)>;
3694 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3695 (VPCMPGTBrr VR128:$src1, VR128:$src2)>;
3696 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
3697 (VPCMPGTBrm VR128:$src1, addr:$src2)>;
3698 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3699 (VPCMPGTWrr VR128:$src1, VR128:$src2)>;
3700 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
3701 (VPCMPGTWrm VR128:$src1, addr:$src2)>;
3702 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3703 (VPCMPGTDrr VR128:$src1, VR128:$src2)>;
3704 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
3705 (VPCMPGTDrm VR128:$src1, addr:$src2)>;
3708 let Constraints = "$src1 = $dst" in {
3709 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
3710 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
3711 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
3712 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
3713 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
3714 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
3715 } // Constraints = "$src1 = $dst"
3717 let Predicates = [HasSSE2] in {
3718 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3719 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
3720 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
3721 (PCMPEQBrm VR128:$src1, addr:$src2)>;
3722 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3723 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
3724 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
3725 (PCMPEQWrm VR128:$src1, addr:$src2)>;
3726 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3727 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
3728 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
3729 (PCMPEQDrm VR128:$src1, addr:$src2)>;
3731 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3732 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
3733 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
3734 (PCMPGTBrm VR128:$src1, addr:$src2)>;
3735 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3736 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
3737 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
3738 (PCMPGTWrm VR128:$src1, addr:$src2)>;
3739 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3740 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
3741 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
3742 (PCMPGTDrm VR128:$src1, addr:$src2)>;
3745 //===---------------------------------------------------------------------===//
3746 // SSE2 - Packed Integer Pack Instructions
3747 //===---------------------------------------------------------------------===//
3749 let Predicates = [HasAVX] in {
3750 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
3752 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
3754 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
3758 let Constraints = "$src1 = $dst" in {
3759 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
3760 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
3761 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
3762 } // Constraints = "$src1 = $dst"
3764 //===---------------------------------------------------------------------===//
3765 // SSE2 - Packed Integer Shuffle Instructions
3766 //===---------------------------------------------------------------------===//
3768 let ExeDomain = SSEPackedInt in {
3769 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
3771 def ri : Ii8<0x70, MRMSrcReg,
3772 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
3773 !strconcat(OpcodeStr,
3774 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3775 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
3777 def mi : Ii8<0x70, MRMSrcMem,
3778 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
3779 !strconcat(OpcodeStr,
3780 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3781 [(set VR128:$dst, (vt (pshuf_frag:$src2
3782 (bc_frag (memopv2i64 addr:$src1)),
3785 } // ExeDomain = SSEPackedInt
3787 let Predicates = [HasAVX] in {
3788 let AddedComplexity = 5 in
3789 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize,
3792 // SSE2 with ImmT == Imm8 and XS prefix.
3793 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
3796 // SSE2 with ImmT == Imm8 and XD prefix.
3797 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
3800 let AddedComplexity = 5 in
3801 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3802 (VPSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3803 // Unary v4f32 shuffle with VPSHUF* in order to fold a load.
3804 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3805 (VPSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3807 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
3809 (VPSHUFDmi addr:$src1, imm:$imm)>;
3810 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
3812 (VPSHUFDmi addr:$src1, imm:$imm)>;
3813 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3814 (VPSHUFDri VR128:$src1, imm:$imm)>;
3815 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3816 (VPSHUFDri VR128:$src1, imm:$imm)>;
3817 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
3818 (VPSHUFHWri VR128:$src, imm:$imm)>;
3819 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
3821 (VPSHUFHWmi addr:$src, imm:$imm)>;
3822 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
3823 (VPSHUFLWri VR128:$src, imm:$imm)>;
3824 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
3826 (VPSHUFLWmi addr:$src, imm:$imm)>;
3829 let Predicates = [HasSSE2] in {
3830 let AddedComplexity = 5 in
3831 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
3833 // SSE2 with ImmT == Imm8 and XS prefix.
3834 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
3836 // SSE2 with ImmT == Imm8 and XD prefix.
3837 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
3839 let AddedComplexity = 5 in
3840 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3841 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3842 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3843 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3844 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3846 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
3848 (PSHUFDmi addr:$src1, imm:$imm)>;
3849 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
3851 (PSHUFDmi addr:$src1, imm:$imm)>;
3852 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3853 (PSHUFDri VR128:$src1, imm:$imm)>;
3854 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3855 (PSHUFDri VR128:$src1, imm:$imm)>;
3856 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
3857 (PSHUFHWri VR128:$src, imm:$imm)>;
3858 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
3860 (PSHUFHWmi addr:$src, imm:$imm)>;
3861 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
3862 (PSHUFLWri VR128:$src, imm:$imm)>;
3863 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
3865 (PSHUFLWmi addr:$src, imm:$imm)>;
3868 //===---------------------------------------------------------------------===//
3869 // SSE2 - Packed Integer Unpack Instructions
3870 //===---------------------------------------------------------------------===//
3872 let ExeDomain = SSEPackedInt in {
3873 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
3874 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
3875 def rr : PDI<opc, MRMSrcReg,
3876 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3878 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3879 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3880 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))]>;
3881 def rm : PDI<opc, MRMSrcMem,
3882 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3884 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3885 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3886 [(set VR128:$dst, (OpNode VR128:$src1,
3887 (bc_frag (memopv2i64
3891 let Predicates = [HasAVX] in {
3892 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Punpcklbw,
3893 bc_v16i8, 0>, VEX_4V;
3894 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Punpcklwd,
3895 bc_v8i16, 0>, VEX_4V;
3896 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Punpckldq,
3897 bc_v4i32, 0>, VEX_4V;
3899 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3900 /// knew to collapse (bitconvert VT to VT) into its operand.
3901 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
3902 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3903 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3904 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
3905 VR128:$src2)))]>, VEX_4V;
3906 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
3907 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3908 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3909 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
3910 (memopv2i64 addr:$src2))))]>, VEX_4V;
3912 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Punpckhbw,
3913 bc_v16i8, 0>, VEX_4V;
3914 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Punpckhwd,
3915 bc_v8i16, 0>, VEX_4V;
3916 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Punpckhdq,
3917 bc_v4i32, 0>, VEX_4V;
3919 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3920 /// knew to collapse (bitconvert VT to VT) into its operand.
3921 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
3922 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3923 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3924 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
3925 VR128:$src2)))]>, VEX_4V;
3926 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
3927 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3928 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3929 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
3930 (memopv2i64 addr:$src2))))]>, VEX_4V;
3933 let Constraints = "$src1 = $dst" in {
3934 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Punpcklbw, bc_v16i8>;
3935 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Punpcklwd, bc_v8i16>;
3936 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Punpckldq, bc_v4i32>;
3938 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3939 /// knew to collapse (bitconvert VT to VT) into its operand.
3940 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
3941 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3942 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
3944 (v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)))]>;
3945 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
3946 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3947 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
3949 (v2i64 (X86Punpcklqdq VR128:$src1,
3950 (memopv2i64 addr:$src2))))]>;
3952 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Punpckhbw, bc_v16i8>;
3953 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Punpckhwd, bc_v8i16>;
3954 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Punpckhdq, bc_v4i32>;
3956 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3957 /// knew to collapse (bitconvert VT to VT) into its operand.
3958 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
3959 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3960 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
3962 (v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)))]>;
3963 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
3964 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3965 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
3967 (v2i64 (X86Punpckhqdq VR128:$src1,
3968 (memopv2i64 addr:$src2))))]>;
3970 } // ExeDomain = SSEPackedInt
3972 // Splat v2f64 / v2i64
3973 let AddedComplexity = 10 in {
3974 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3975 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3976 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3977 (VPUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasAVX]>;
3980 //===---------------------------------------------------------------------===//
3981 // SSE2 - Packed Integer Extract and Insert
3982 //===---------------------------------------------------------------------===//
3984 let ExeDomain = SSEPackedInt in {
3985 multiclass sse2_pinsrw<bit Is2Addr = 1> {
3986 def rri : Ii8<0xC4, MRMSrcReg,
3987 (outs VR128:$dst), (ins VR128:$src1,
3988 GR32:$src2, i32i8imm:$src3),
3990 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3991 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3993 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
3994 def rmi : Ii8<0xC4, MRMSrcMem,
3995 (outs VR128:$dst), (ins VR128:$src1,
3996 i16mem:$src2, i32i8imm:$src3),
3998 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3999 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4001 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4006 let Predicates = [HasAVX] in
4007 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4008 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4009 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4010 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4011 imm:$src2))]>, TB, OpSize, VEX;
4012 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4013 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4014 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4015 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4019 let Predicates = [HasAVX] in {
4020 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4021 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4022 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4023 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4024 []>, TB, OpSize, VEX_4V;
4027 let Constraints = "$src1 = $dst" in
4028 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
4030 } // ExeDomain = SSEPackedInt
4032 //===---------------------------------------------------------------------===//
4033 // SSE2 - Packed Mask Creation
4034 //===---------------------------------------------------------------------===//
4036 let ExeDomain = SSEPackedInt in {
4038 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4039 "pmovmskb\t{$src, $dst|$dst, $src}",
4040 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
4041 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4042 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4043 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4044 "pmovmskb\t{$src, $dst|$dst, $src}",
4045 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
4047 } // ExeDomain = SSEPackedInt
4049 //===---------------------------------------------------------------------===//
4050 // SSE2 - Conditional Store
4051 //===---------------------------------------------------------------------===//
4053 let ExeDomain = SSEPackedInt in {
4056 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4057 (ins VR128:$src, VR128:$mask),
4058 "maskmovdqu\t{$mask, $src|$src, $mask}",
4059 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
4061 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4062 (ins VR128:$src, VR128:$mask),
4063 "maskmovdqu\t{$mask, $src|$src, $mask}",
4064 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
4067 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4068 "maskmovdqu\t{$mask, $src|$src, $mask}",
4069 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
4071 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4072 "maskmovdqu\t{$mask, $src|$src, $mask}",
4073 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
4075 } // ExeDomain = SSEPackedInt
4077 //===---------------------------------------------------------------------===//
4078 // SSE2 - Move Doubleword
4079 //===---------------------------------------------------------------------===//
4081 //===---------------------------------------------------------------------===//
4082 // Move Int Doubleword to Packed Double Int
4084 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4085 "movd\t{$src, $dst|$dst, $src}",
4087 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
4088 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4089 "movd\t{$src, $dst|$dst, $src}",
4091 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
4093 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4094 "mov{d|q}\t{$src, $dst|$dst, $src}",
4096 (v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
4097 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4098 "mov{d|q}\t{$src, $dst|$dst, $src}",
4099 [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
4101 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4102 "movd\t{$src, $dst|$dst, $src}",
4104 (v4i32 (scalar_to_vector GR32:$src)))]>;
4105 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4106 "movd\t{$src, $dst|$dst, $src}",
4108 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
4109 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4110 "mov{d|q}\t{$src, $dst|$dst, $src}",
4112 (v2i64 (scalar_to_vector GR64:$src)))]>;
4113 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4114 "mov{d|q}\t{$src, $dst|$dst, $src}",
4115 [(set FR64:$dst, (bitconvert GR64:$src))]>;
4117 //===---------------------------------------------------------------------===//
4118 // Move Int Doubleword to Single Scalar
4120 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4121 "movd\t{$src, $dst|$dst, $src}",
4122 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
4124 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4125 "movd\t{$src, $dst|$dst, $src}",
4126 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
4128 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4129 "movd\t{$src, $dst|$dst, $src}",
4130 [(set FR32:$dst, (bitconvert GR32:$src))]>;
4132 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4133 "movd\t{$src, $dst|$dst, $src}",
4134 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
4136 //===---------------------------------------------------------------------===//
4137 // Move Packed Doubleword Int to Packed Double Int
4139 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4140 "movd\t{$src, $dst|$dst, $src}",
4141 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4143 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4144 (ins i32mem:$dst, VR128:$src),
4145 "movd\t{$src, $dst|$dst, $src}",
4146 [(store (i32 (vector_extract (v4i32 VR128:$src),
4147 (iPTR 0))), addr:$dst)]>, VEX;
4148 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4149 "movd\t{$src, $dst|$dst, $src}",
4150 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4152 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4153 "movd\t{$src, $dst|$dst, $src}",
4154 [(store (i32 (vector_extract (v4i32 VR128:$src),
4155 (iPTR 0))), addr:$dst)]>;
4157 //===---------------------------------------------------------------------===//
4158 // Move Packed Doubleword Int first element to Doubleword Int
4160 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4161 "mov{d|q}\t{$src, $dst|$dst, $src}",
4162 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4164 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4166 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4167 "mov{d|q}\t{$src, $dst|$dst, $src}",
4168 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4171 //===---------------------------------------------------------------------===//
4172 // Bitcast FR64 <-> GR64
4174 let Predicates = [HasAVX] in
4175 def VMOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4176 "vmovq\t{$src, $dst|$dst, $src}",
4177 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4179 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4180 "mov{d|q}\t{$src, $dst|$dst, $src}",
4181 [(set GR64:$dst, (bitconvert FR64:$src))]>;
4182 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4183 "movq\t{$src, $dst|$dst, $src}",
4184 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
4186 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4187 "movq\t{$src, $dst|$dst, $src}",
4188 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
4189 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4190 "mov{d|q}\t{$src, $dst|$dst, $src}",
4191 [(set GR64:$dst, (bitconvert FR64:$src))]>;
4192 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4193 "movq\t{$src, $dst|$dst, $src}",
4194 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
4196 //===---------------------------------------------------------------------===//
4197 // Move Scalar Single to Double Int
4199 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4200 "movd\t{$src, $dst|$dst, $src}",
4201 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
4202 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4203 "movd\t{$src, $dst|$dst, $src}",
4204 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
4205 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4206 "movd\t{$src, $dst|$dst, $src}",
4207 [(set GR32:$dst, (bitconvert FR32:$src))]>;
4208 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4209 "movd\t{$src, $dst|$dst, $src}",
4210 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
4212 //===---------------------------------------------------------------------===//
4213 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4215 let AddedComplexity = 15 in {
4216 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4217 "movd\t{$src, $dst|$dst, $src}",
4218 [(set VR128:$dst, (v4i32 (X86vzmovl
4219 (v4i32 (scalar_to_vector GR32:$src)))))]>,
4221 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4222 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4223 [(set VR128:$dst, (v2i64 (X86vzmovl
4224 (v2i64 (scalar_to_vector GR64:$src)))))]>,
4227 let AddedComplexity = 15 in {
4228 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4229 "movd\t{$src, $dst|$dst, $src}",
4230 [(set VR128:$dst, (v4i32 (X86vzmovl
4231 (v4i32 (scalar_to_vector GR32:$src)))))]>;
4232 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4233 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4234 [(set VR128:$dst, (v2i64 (X86vzmovl
4235 (v2i64 (scalar_to_vector GR64:$src)))))]>;
4238 let AddedComplexity = 20 in {
4239 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4240 "movd\t{$src, $dst|$dst, $src}",
4242 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4243 (loadi32 addr:$src))))))]>,
4245 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4246 "movd\t{$src, $dst|$dst, $src}",
4248 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4249 (loadi32 addr:$src))))))]>;
4252 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4253 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
4254 (MOVZDI2PDIrm addr:$src)>;
4255 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4256 (MOVZDI2PDIrm addr:$src)>;
4257 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4258 (MOVZDI2PDIrm addr:$src)>;
4261 let Predicates = [HasAVX] in {
4262 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4263 let AddedComplexity = 20 in {
4264 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
4265 (VMOVZDI2PDIrm addr:$src)>;
4266 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4267 (VMOVZDI2PDIrm addr:$src)>;
4268 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4269 (VMOVZDI2PDIrm addr:$src)>;
4271 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4272 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4273 (v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
4274 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4275 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4276 (v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
4277 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4280 // These are the correct encodings of the instructions so that we know how to
4281 // read correct assembly, even though we continue to emit the wrong ones for
4282 // compatibility with Darwin's buggy assembler.
4283 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4284 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4285 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4286 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4287 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4288 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4289 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4290 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4291 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4292 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4293 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4294 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4296 //===---------------------------------------------------------------------===//
4297 // SSE2 - Move Quadword
4298 //===---------------------------------------------------------------------===//
4300 //===---------------------------------------------------------------------===//
4301 // Move Quadword Int to Packed Quadword Int
4303 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4304 "vmovq\t{$src, $dst|$dst, $src}",
4306 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4307 VEX, Requires<[HasAVX]>;
4308 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4309 "movq\t{$src, $dst|$dst, $src}",
4311 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4312 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
4314 //===---------------------------------------------------------------------===//
4315 // Move Packed Quadword Int to Quadword Int
4317 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4318 "movq\t{$src, $dst|$dst, $src}",
4319 [(store (i64 (vector_extract (v2i64 VR128:$src),
4320 (iPTR 0))), addr:$dst)]>, VEX;
4321 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4322 "movq\t{$src, $dst|$dst, $src}",
4323 [(store (i64 (vector_extract (v2i64 VR128:$src),
4324 (iPTR 0))), addr:$dst)]>;
4326 //===---------------------------------------------------------------------===//
4327 // Store / copy lower 64-bits of a XMM register.
4329 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4330 "movq\t{$src, $dst|$dst, $src}",
4331 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4332 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4333 "movq\t{$src, $dst|$dst, $src}",
4334 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
4336 let AddedComplexity = 20 in
4337 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4338 "vmovq\t{$src, $dst|$dst, $src}",
4340 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4341 (loadi64 addr:$src))))))]>,
4342 XS, VEX, Requires<[HasAVX]>;
4344 let AddedComplexity = 20 in
4345 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4346 "movq\t{$src, $dst|$dst, $src}",
4348 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4349 (loadi64 addr:$src))))))]>,
4350 XS, Requires<[HasSSE2]>;
4352 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4353 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4354 (MOVZQI2PQIrm addr:$src)>;
4355 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4356 (MOVZQI2PQIrm addr:$src)>;
4357 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4360 let Predicates = [HasAVX], AddedComplexity = 20 in {
4361 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4362 (VMOVZQI2PQIrm addr:$src)>;
4363 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4364 (VMOVZQI2PQIrm addr:$src)>;
4365 def : Pat<(v2i64 (X86vzload addr:$src)),
4366 (VMOVZQI2PQIrm addr:$src)>;
4369 //===---------------------------------------------------------------------===//
4370 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4371 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4373 let AddedComplexity = 15 in
4374 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4375 "vmovq\t{$src, $dst|$dst, $src}",
4376 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4377 XS, VEX, Requires<[HasAVX]>;
4378 let AddedComplexity = 15 in
4379 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4380 "movq\t{$src, $dst|$dst, $src}",
4381 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4382 XS, Requires<[HasSSE2]>;
4384 let AddedComplexity = 20 in
4385 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4386 "vmovq\t{$src, $dst|$dst, $src}",
4387 [(set VR128:$dst, (v2i64 (X86vzmovl
4388 (loadv2i64 addr:$src))))]>,
4389 XS, VEX, Requires<[HasAVX]>;
4390 let AddedComplexity = 20 in {
4391 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4392 "movq\t{$src, $dst|$dst, $src}",
4393 [(set VR128:$dst, (v2i64 (X86vzmovl
4394 (loadv2i64 addr:$src))))]>,
4395 XS, Requires<[HasSSE2]>;
4398 let AddedComplexity = 20 in {
4399 let Predicates = [HasSSE2] in {
4400 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
4401 (MOVZPQILo2PQIrm addr:$src)>;
4402 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4403 (MOVZPQILo2PQIrr VR128:$src)>;
4405 let Predicates = [HasAVX] in {
4406 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
4407 (VMOVZPQILo2PQIrm addr:$src)>;
4408 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4409 (VMOVZPQILo2PQIrr VR128:$src)>;
4413 // Instructions to match in the assembler
4414 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4415 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4416 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4417 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4418 // Recognize "movd" with GR64 destination, but encode as a "movq"
4419 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4420 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4422 // Instructions for the disassembler
4423 // xr = XMM register
4426 let Predicates = [HasAVX] in
4427 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4428 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4429 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4430 "movq\t{$src, $dst|$dst, $src}", []>, XS;
4432 //===---------------------------------------------------------------------===//
4433 // SSE3 - Conversion Instructions
4434 //===---------------------------------------------------------------------===//
4436 // Convert Packed Double FP to Packed DW Integers
4437 let Predicates = [HasAVX] in {
4438 // The assembler can recognize rr 256-bit instructions by seeing a ymm
4439 // register, but the same isn't true when using memory operands instead.
4440 // Provide other assembly rr and rm forms to address this explicitly.
4441 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4442 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4443 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4444 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4447 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4448 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4449 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4450 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4453 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4454 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
4455 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
4456 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4459 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4460 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4461 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4462 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4464 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
4465 (VCVTPD2DQYrr VR256:$src)>;
4466 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
4467 (VCVTPD2DQYrm addr:$src)>;
4469 // Convert Packed DW Integers to Packed Double FP
4470 let Predicates = [HasAVX] in {
4471 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4472 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4473 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4474 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4475 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
4476 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4477 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
4478 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4481 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4482 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4483 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4484 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4486 // AVX 256-bit register conversion intrinsics
4487 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
4488 (VCVTDQ2PDYrr VR128:$src)>;
4489 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
4490 (VCVTDQ2PDYrm addr:$src)>;
4492 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
4493 (VCVTPD2DQYrr VR256:$src)>;
4494 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
4495 (VCVTPD2DQYrm addr:$src)>;
4497 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
4498 (VCVTDQ2PDYrr VR128:$src)>;
4499 def : Pat<(v4f64 (sint_to_fp (memopv4i32 addr:$src))),
4500 (VCVTDQ2PDYrm addr:$src)>;
4502 //===---------------------------------------------------------------------===//
4503 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4504 //===---------------------------------------------------------------------===//
4505 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4506 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4507 X86MemOperand x86memop> {
4508 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4509 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4510 [(set RC:$dst, (vt (OpNode RC:$src)))]>;
4511 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4512 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4513 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>;
4516 let Predicates = [HasAVX] in {
4517 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4518 v4f32, VR128, memopv4f32, f128mem>, VEX;
4519 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4520 v4f32, VR128, memopv4f32, f128mem>, VEX;
4521 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4522 v8f32, VR256, memopv8f32, f256mem>, VEX;
4523 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4524 v8f32, VR256, memopv8f32, f256mem>, VEX;
4526 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4527 memopv4f32, f128mem>;
4528 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4529 memopv4f32, f128mem>;
4531 let Predicates = [HasSSE3] in {
4532 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4533 (MOVSHDUPrr VR128:$src)>;
4534 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4535 (MOVSHDUPrm addr:$src)>;
4536 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4537 (MOVSLDUPrr VR128:$src)>;
4538 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4539 (MOVSLDUPrm addr:$src)>;
4542 let Predicates = [HasAVX] in {
4543 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4544 (VMOVSHDUPrr VR128:$src)>;
4545 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4546 (VMOVSHDUPrm addr:$src)>;
4547 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4548 (VMOVSLDUPrr VR128:$src)>;
4549 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4550 (VMOVSLDUPrm addr:$src)>;
4551 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4552 (VMOVSHDUPYrr VR256:$src)>;
4553 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4554 (VMOVSHDUPYrm addr:$src)>;
4555 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4556 (VMOVSLDUPYrr VR256:$src)>;
4557 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4558 (VMOVSLDUPYrm addr:$src)>;
4561 //===---------------------------------------------------------------------===//
4562 // SSE3 - Replicate Double FP - MOVDDUP
4563 //===---------------------------------------------------------------------===//
4565 multiclass sse3_replicate_dfp<string OpcodeStr> {
4566 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4567 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4568 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
4569 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4570 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4572 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
4576 // FIXME: Merge with above classe when there're patterns for the ymm version
4577 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4578 let Predicates = [HasAVX] in {
4579 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4580 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4582 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4583 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4588 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4589 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4590 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
4592 let Predicates = [HasSSE3] in {
4593 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
4595 (MOVDDUPrm addr:$src)>;
4596 let AddedComplexity = 5 in {
4597 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
4598 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
4599 (MOVDDUPrm addr:$src)>;
4600 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
4601 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
4602 (MOVDDUPrm addr:$src)>;
4604 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4605 (MOVDDUPrm addr:$src)>;
4606 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4607 (MOVDDUPrm addr:$src)>;
4608 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4609 (MOVDDUPrm addr:$src)>;
4610 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
4611 (MOVDDUPrm addr:$src)>;
4612 def : Pat<(X86Movddup (bc_v2f64
4613 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4614 (MOVDDUPrm addr:$src)>;
4617 let Predicates = [HasAVX] in {
4618 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
4620 (VMOVDDUPrm addr:$src)>;
4621 let AddedComplexity = 5 in {
4622 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
4623 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
4624 (VMOVDDUPrm addr:$src)>;
4625 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
4626 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
4627 (VMOVDDUPrm addr:$src)>;
4629 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4630 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4631 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4632 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4633 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4634 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4635 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
4636 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4637 def : Pat<(X86Movddup (bc_v2f64
4638 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4639 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4642 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4643 (VMOVDDUPYrm addr:$src)>;
4644 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4645 (VMOVDDUPYrm addr:$src)>;
4646 def : Pat<(X86Movddup (v4f64 (scalar_to_vector (loadf64 addr:$src)))),
4647 (VMOVDDUPYrm addr:$src)>;
4648 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4649 (VMOVDDUPYrm addr:$src)>;
4650 def : Pat<(X86Movddup (v4f64 VR256:$src)),
4651 (VMOVDDUPYrr VR256:$src)>;
4652 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4653 (VMOVDDUPYrr VR256:$src)>;
4656 //===---------------------------------------------------------------------===//
4657 // SSE3 - Move Unaligned Integer
4658 //===---------------------------------------------------------------------===//
4660 let Predicates = [HasAVX] in {
4661 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4662 "vlddqu\t{$src, $dst|$dst, $src}",
4663 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4664 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4665 "vlddqu\t{$src, $dst|$dst, $src}",
4666 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
4668 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4669 "lddqu\t{$src, $dst|$dst, $src}",
4670 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
4672 //===---------------------------------------------------------------------===//
4673 // SSE3 - Arithmetic
4674 //===---------------------------------------------------------------------===//
4676 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4677 X86MemOperand x86memop, bit Is2Addr = 1> {
4678 def rr : I<0xD0, MRMSrcReg,
4679 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4681 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4682 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4683 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
4684 def rm : I<0xD0, MRMSrcMem,
4685 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4687 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4688 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4689 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
4692 let Predicates = [HasAVX],
4693 ExeDomain = SSEPackedDouble in {
4694 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4695 f128mem, 0>, TB, XD, VEX_4V;
4696 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4697 f128mem, 0>, TB, OpSize, VEX_4V;
4698 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4699 f256mem, 0>, TB, XD, VEX_4V;
4700 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
4701 f256mem, 0>, TB, OpSize, VEX_4V;
4703 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
4704 ExeDomain = SSEPackedDouble in {
4705 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
4707 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
4708 f128mem>, TB, OpSize;
4711 //===---------------------------------------------------------------------===//
4712 // SSE3 Instructions
4713 //===---------------------------------------------------------------------===//
4716 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4717 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4718 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4720 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4721 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4722 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))]>;
4724 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4726 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4727 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4728 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))]>;
4730 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4731 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4732 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4734 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4735 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4736 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))]>;
4738 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4740 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4741 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4742 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))]>;
4745 let Predicates = [HasAVX] in {
4746 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
4747 X86fhadd, 0>, VEX_4V;
4748 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
4749 X86fhadd, 0>, VEX_4V;
4750 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
4751 X86fhsub, 0>, VEX_4V;
4752 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
4753 X86fhsub, 0>, VEX_4V;
4754 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
4755 X86fhadd, 0>, VEX_4V;
4756 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
4757 X86fhadd, 0>, VEX_4V;
4758 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
4759 X86fhsub, 0>, VEX_4V;
4760 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
4761 X86fhsub, 0>, VEX_4V;
4764 let Constraints = "$src1 = $dst" in {
4765 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
4766 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
4767 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
4768 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
4771 //===---------------------------------------------------------------------===//
4772 // SSSE3 - Packed Absolute Instructions
4773 //===---------------------------------------------------------------------===//
4776 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
4777 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
4778 PatFrag mem_frag128, Intrinsic IntId128> {
4779 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4781 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4782 [(set VR128:$dst, (IntId128 VR128:$src))]>,
4785 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4787 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4790 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
4793 let Predicates = [HasAVX] in {
4794 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
4795 int_x86_ssse3_pabs_b_128>, VEX;
4796 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
4797 int_x86_ssse3_pabs_w_128>, VEX;
4798 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
4799 int_x86_ssse3_pabs_d_128>, VEX;
4802 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
4803 int_x86_ssse3_pabs_b_128>;
4804 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
4805 int_x86_ssse3_pabs_w_128>;
4806 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
4807 int_x86_ssse3_pabs_d_128>;
4809 //===---------------------------------------------------------------------===//
4810 // SSSE3 - Packed Binary Operator Instructions
4811 //===---------------------------------------------------------------------===//
4813 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
4814 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
4815 PatFrag mem_frag128, Intrinsic IntId128,
4817 let isCommutable = 1 in
4818 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4819 (ins VR128:$src1, VR128:$src2),
4821 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4822 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4823 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4825 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4826 (ins VR128:$src1, i128mem:$src2),
4828 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4829 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4831 (IntId128 VR128:$src1,
4832 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4835 let ImmT = NoImm, Predicates = [HasAVX] in {
4836 let isCommutable = 0 in {
4837 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
4838 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
4839 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
4840 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
4841 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
4842 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
4843 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
4844 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
4845 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
4846 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
4847 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
4848 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
4849 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
4850 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
4851 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
4852 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
4853 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
4854 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
4855 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
4856 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
4857 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
4858 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
4860 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
4861 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
4864 // None of these have i8 immediate fields.
4865 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
4866 let isCommutable = 0 in {
4867 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
4868 int_x86_ssse3_phadd_w_128>;
4869 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
4870 int_x86_ssse3_phadd_d_128>;
4871 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
4872 int_x86_ssse3_phadd_sw_128>;
4873 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
4874 int_x86_ssse3_phsub_w_128>;
4875 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
4876 int_x86_ssse3_phsub_d_128>;
4877 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
4878 int_x86_ssse3_phsub_sw_128>;
4879 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
4880 int_x86_ssse3_pmadd_ub_sw_128>;
4881 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
4882 int_x86_ssse3_pshuf_b_128>;
4883 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
4884 int_x86_ssse3_psign_b_128>;
4885 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
4886 int_x86_ssse3_psign_w_128>;
4887 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
4888 int_x86_ssse3_psign_d_128>;
4890 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
4891 int_x86_ssse3_pmul_hr_sw_128>;
4894 let Predicates = [HasSSSE3] in {
4895 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
4896 (PSHUFBrr128 VR128:$src, VR128:$mask)>;
4897 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
4898 (PSHUFBrm128 VR128:$src, addr:$mask)>;
4900 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
4901 (PSIGNBrr128 VR128:$src1, VR128:$src2)>;
4902 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
4903 (PSIGNWrr128 VR128:$src1, VR128:$src2)>;
4904 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
4905 (PSIGNDrr128 VR128:$src1, VR128:$src2)>;
4908 let Predicates = [HasAVX] in {
4909 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
4910 (VPSHUFBrr128 VR128:$src, VR128:$mask)>;
4911 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
4912 (VPSHUFBrm128 VR128:$src, addr:$mask)>;
4914 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
4915 (VPSIGNBrr128 VR128:$src1, VR128:$src2)>;
4916 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
4917 (VPSIGNWrr128 VR128:$src1, VR128:$src2)>;
4918 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
4919 (VPSIGNDrr128 VR128:$src1, VR128:$src2)>;
4922 //===---------------------------------------------------------------------===//
4923 // SSSE3 - Packed Align Instruction Patterns
4924 //===---------------------------------------------------------------------===//
4926 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
4927 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
4928 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4930 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4932 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4934 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
4935 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4937 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4939 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4943 let Predicates = [HasAVX] in
4944 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
4945 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
4946 defm PALIGN : ssse3_palign<"palignr">;
4948 let Predicates = [HasSSSE3] in {
4949 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4950 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4951 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4952 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4953 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4954 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4955 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4956 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4959 let Predicates = [HasAVX] in {
4960 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4961 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4962 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4963 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4964 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4965 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4966 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4967 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4970 //===---------------------------------------------------------------------===//
4971 // SSSE3 - Thread synchronization
4972 //===---------------------------------------------------------------------===//
4974 let usesCustomInserter = 1 in {
4975 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
4976 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
4977 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
4978 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
4981 let Uses = [EAX, ECX, EDX] in
4982 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
4983 Requires<[HasSSE3]>;
4984 let Uses = [ECX, EAX] in
4985 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
4986 Requires<[HasSSE3]>;
4988 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
4989 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
4991 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
4992 Requires<[In32BitMode]>;
4993 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
4994 Requires<[In64BitMode]>;
4996 //===----------------------------------------------------------------------===//
4997 // SSE4.1 - Packed Move with Sign/Zero Extend
4998 //===----------------------------------------------------------------------===//
5000 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5001 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5002 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5003 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5005 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5006 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5008 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5012 let Predicates = [HasAVX] in {
5013 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5015 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5017 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5019 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5021 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5023 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5027 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5028 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5029 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5030 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5031 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5032 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5034 let Predicates = [HasSSE41] in {
5035 // Common patterns involving scalar load.
5036 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5037 (PMOVSXBWrm addr:$src)>;
5038 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5039 (PMOVSXBWrm addr:$src)>;
5041 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5042 (PMOVSXWDrm addr:$src)>;
5043 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5044 (PMOVSXWDrm addr:$src)>;
5046 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5047 (PMOVSXDQrm addr:$src)>;
5048 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5049 (PMOVSXDQrm addr:$src)>;
5051 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5052 (PMOVZXBWrm addr:$src)>;
5053 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5054 (PMOVZXBWrm addr:$src)>;
5056 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5057 (PMOVZXWDrm addr:$src)>;
5058 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5059 (PMOVZXWDrm addr:$src)>;
5061 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5062 (PMOVZXDQrm addr:$src)>;
5063 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5064 (PMOVZXDQrm addr:$src)>;
5067 let Predicates = [HasAVX] in {
5068 // Common patterns involving scalar load.
5069 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5070 (VPMOVSXBWrm addr:$src)>;
5071 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5072 (VPMOVSXBWrm addr:$src)>;
5074 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5075 (VPMOVSXWDrm addr:$src)>;
5076 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5077 (VPMOVSXWDrm addr:$src)>;
5079 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5080 (VPMOVSXDQrm addr:$src)>;
5081 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5082 (VPMOVSXDQrm addr:$src)>;
5084 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5085 (VPMOVZXBWrm addr:$src)>;
5086 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5087 (VPMOVZXBWrm addr:$src)>;
5089 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5090 (VPMOVZXWDrm addr:$src)>;
5091 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5092 (VPMOVZXWDrm addr:$src)>;
5094 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5095 (VPMOVZXDQrm addr:$src)>;
5096 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5097 (VPMOVZXDQrm addr:$src)>;
5101 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5102 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5103 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5104 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5106 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5107 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5109 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5113 let Predicates = [HasAVX] in {
5114 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5116 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5118 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5120 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5124 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5125 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5126 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5127 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5129 let Predicates = [HasSSE41] in {
5130 // Common patterns involving scalar load
5131 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5132 (PMOVSXBDrm addr:$src)>;
5133 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5134 (PMOVSXWQrm addr:$src)>;
5136 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5137 (PMOVZXBDrm addr:$src)>;
5138 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5139 (PMOVZXWQrm addr:$src)>;
5142 let Predicates = [HasAVX] in {
5143 // Common patterns involving scalar load
5144 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5145 (VPMOVSXBDrm addr:$src)>;
5146 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5147 (VPMOVSXWQrm addr:$src)>;
5149 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5150 (VPMOVZXBDrm addr:$src)>;
5151 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5152 (VPMOVZXWQrm addr:$src)>;
5155 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5156 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5157 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5158 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5160 // Expecting a i16 load any extended to i32 value.
5161 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5162 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5163 [(set VR128:$dst, (IntId (bitconvert
5164 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5168 let Predicates = [HasAVX] in {
5169 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5171 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5174 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5175 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5177 let Predicates = [HasSSE41] in {
5178 // Common patterns involving scalar load
5179 def : Pat<(int_x86_sse41_pmovsxbq
5180 (bitconvert (v4i32 (X86vzmovl
5181 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5182 (PMOVSXBQrm addr:$src)>;
5184 def : Pat<(int_x86_sse41_pmovzxbq
5185 (bitconvert (v4i32 (X86vzmovl
5186 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5187 (PMOVZXBQrm addr:$src)>;
5190 let Predicates = [HasAVX] in {
5191 // Common patterns involving scalar load
5192 def : Pat<(int_x86_sse41_pmovsxbq
5193 (bitconvert (v4i32 (X86vzmovl
5194 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5195 (VPMOVSXBQrm addr:$src)>;
5197 def : Pat<(int_x86_sse41_pmovzxbq
5198 (bitconvert (v4i32 (X86vzmovl
5199 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5200 (VPMOVZXBQrm addr:$src)>;
5203 //===----------------------------------------------------------------------===//
5204 // SSE4.1 - Extract Instructions
5205 //===----------------------------------------------------------------------===//
5207 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5208 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5209 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5210 (ins VR128:$src1, i32i8imm:$src2),
5211 !strconcat(OpcodeStr,
5212 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5213 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5215 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5216 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5217 !strconcat(OpcodeStr,
5218 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5221 // There's an AssertZext in the way of writing the store pattern
5222 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5225 let Predicates = [HasAVX] in {
5226 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5227 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5228 (ins VR128:$src1, i32i8imm:$src2),
5229 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5232 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5235 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5236 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5237 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5238 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5239 !strconcat(OpcodeStr,
5240 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5243 // There's an AssertZext in the way of writing the store pattern
5244 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5247 let Predicates = [HasAVX] in
5248 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5250 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5253 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5254 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5255 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5256 (ins VR128:$src1, i32i8imm:$src2),
5257 !strconcat(OpcodeStr,
5258 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5260 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5261 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5262 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5263 !strconcat(OpcodeStr,
5264 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5265 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5266 addr:$dst)]>, OpSize;
5269 let Predicates = [HasAVX] in
5270 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5272 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5274 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5275 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5276 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5277 (ins VR128:$src1, i32i8imm:$src2),
5278 !strconcat(OpcodeStr,
5279 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5281 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5282 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5283 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5284 !strconcat(OpcodeStr,
5285 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5286 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5287 addr:$dst)]>, OpSize, REX_W;
5290 let Predicates = [HasAVX] in
5291 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5293 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5295 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5297 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5298 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5299 (ins VR128:$src1, i32i8imm:$src2),
5300 !strconcat(OpcodeStr,
5301 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5303 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5305 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5306 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5307 !strconcat(OpcodeStr,
5308 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5309 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5310 addr:$dst)]>, OpSize;
5313 let Predicates = [HasAVX] in {
5314 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5315 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5316 (ins VR128:$src1, i32i8imm:$src2),
5317 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
5320 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
5322 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
5323 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5326 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5327 Requires<[HasSSE41]>;
5328 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5331 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5334 //===----------------------------------------------------------------------===//
5335 // SSE4.1 - Insert Instructions
5336 //===----------------------------------------------------------------------===//
5338 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5339 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5340 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5342 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5344 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5346 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5347 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5348 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
5350 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5352 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5354 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
5355 imm:$src3))]>, OpSize;
5358 let Predicates = [HasAVX] in
5359 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
5360 let Constraints = "$src1 = $dst" in
5361 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
5363 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
5364 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5365 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5367 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5369 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5371 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
5373 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5374 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
5376 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5378 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5380 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
5381 imm:$src3)))]>, OpSize;
5384 let Predicates = [HasAVX] in
5385 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
5386 let Constraints = "$src1 = $dst" in
5387 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
5389 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
5390 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5391 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
5393 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5395 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5397 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
5399 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5400 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
5402 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5404 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5406 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
5407 imm:$src3)))]>, OpSize;
5410 let Predicates = [HasAVX] in
5411 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
5412 let Constraints = "$src1 = $dst" in
5413 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
5415 // insertps has a few different modes, there's the first two here below which
5416 // are optimized inserts that won't zero arbitrary elements in the destination
5417 // vector. The next one matches the intrinsic and could zero arbitrary elements
5418 // in the target vector.
5419 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
5420 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5421 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
5423 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5425 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5427 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
5429 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5430 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
5432 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5434 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5436 (X86insrtps VR128:$src1,
5437 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
5438 imm:$src3))]>, OpSize;
5441 let Constraints = "$src1 = $dst" in
5442 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
5443 let Predicates = [HasAVX] in
5444 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
5446 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
5447 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
5449 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
5450 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
5451 Requires<[HasSSE41]>;
5453 //===----------------------------------------------------------------------===//
5454 // SSE4.1 - Round Instructions
5455 //===----------------------------------------------------------------------===//
5457 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
5458 X86MemOperand x86memop, RegisterClass RC,
5459 PatFrag mem_frag32, PatFrag mem_frag64,
5460 Intrinsic V4F32Int, Intrinsic V2F64Int> {
5461 // Intrinsic operation, reg.
5462 // Vector intrinsic operation, reg
5463 def PSr : SS4AIi8<opcps, MRMSrcReg,
5464 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5465 !strconcat(OpcodeStr,
5466 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5467 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
5470 // Vector intrinsic operation, mem
5471 def PSm : Ii8<opcps, MRMSrcMem,
5472 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5473 !strconcat(OpcodeStr,
5474 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5476 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
5478 Requires<[HasSSE41]>;
5480 // Vector intrinsic operation, reg
5481 def PDr : SS4AIi8<opcpd, MRMSrcReg,
5482 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5483 !strconcat(OpcodeStr,
5484 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5485 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
5488 // Vector intrinsic operation, mem
5489 def PDm : SS4AIi8<opcpd, MRMSrcMem,
5490 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5491 !strconcat(OpcodeStr,
5492 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5494 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
5498 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
5499 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
5500 // Intrinsic operation, reg.
5501 // Vector intrinsic operation, reg
5502 def PSr_AVX : SS4AIi8<opcps, MRMSrcReg,
5503 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5504 !strconcat(OpcodeStr,
5505 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5508 // Vector intrinsic operation, mem
5509 def PSm_AVX : Ii8<opcps, MRMSrcMem,
5510 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5511 !strconcat(OpcodeStr,
5512 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5513 []>, TA, OpSize, Requires<[HasSSE41]>;
5515 // Vector intrinsic operation, reg
5516 def PDr_AVX : SS4AIi8<opcpd, MRMSrcReg,
5517 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5518 !strconcat(OpcodeStr,
5519 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5522 // Vector intrinsic operation, mem
5523 def PDm_AVX : SS4AIi8<opcpd, MRMSrcMem,
5524 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5525 !strconcat(OpcodeStr,
5526 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5530 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
5533 Intrinsic F64Int, bit Is2Addr = 1> {
5534 // Intrinsic operation, reg.
5535 def SSr : SS4AIi8<opcss, MRMSrcReg,
5536 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5538 !strconcat(OpcodeStr,
5539 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5540 !strconcat(OpcodeStr,
5541 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5542 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
5545 // Intrinsic operation, mem.
5546 def SSm : SS4AIi8<opcss, MRMSrcMem,
5547 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
5549 !strconcat(OpcodeStr,
5550 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5551 !strconcat(OpcodeStr,
5552 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5554 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
5557 // Intrinsic operation, reg.
5558 def SDr : SS4AIi8<opcsd, MRMSrcReg,
5559 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5561 !strconcat(OpcodeStr,
5562 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5563 !strconcat(OpcodeStr,
5564 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5565 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
5568 // Intrinsic operation, mem.
5569 def SDm : SS4AIi8<opcsd, MRMSrcMem,
5570 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
5572 !strconcat(OpcodeStr,
5573 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5574 !strconcat(OpcodeStr,
5575 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5577 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
5581 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
5583 // Intrinsic operation, reg.
5584 def SSr_AVX : SS4AIi8<opcss, MRMSrcReg,
5585 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5586 !strconcat(OpcodeStr,
5587 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5590 // Intrinsic operation, mem.
5591 def SSm_AVX : SS4AIi8<opcss, MRMSrcMem,
5592 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
5593 !strconcat(OpcodeStr,
5594 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5597 // Intrinsic operation, reg.
5598 def SDr_AVX : SS4AIi8<opcsd, MRMSrcReg,
5599 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5600 !strconcat(OpcodeStr,
5601 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5604 // Intrinsic operation, mem.
5605 def SDm_AVX : SS4AIi8<opcsd, MRMSrcMem,
5606 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
5607 !strconcat(OpcodeStr,
5608 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5612 // FP round - roundss, roundps, roundsd, roundpd
5613 let Predicates = [HasAVX] in {
5615 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
5616 memopv4f32, memopv2f64,
5617 int_x86_sse41_round_ps,
5618 int_x86_sse41_round_pd>, VEX;
5619 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
5620 memopv8f32, memopv4f64,
5621 int_x86_avx_round_ps_256,
5622 int_x86_avx_round_pd_256>, VEX;
5623 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
5624 int_x86_sse41_round_ss,
5625 int_x86_sse41_round_sd, 0>, VEX_4V;
5627 // Instructions for the assembler
5628 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
5630 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
5632 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
5635 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
5636 memopv4f32, memopv2f64,
5637 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
5638 let Constraints = "$src1 = $dst" in
5639 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
5640 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
5642 //===----------------------------------------------------------------------===//
5643 // SSE4.1 - Packed Bit Test
5644 //===----------------------------------------------------------------------===//
5646 // ptest instruction we'll lower to this in X86ISelLowering primarily from
5647 // the intel intrinsic that corresponds to this.
5648 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5649 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5650 "vptest\t{$src2, $src1|$src1, $src2}",
5651 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5653 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5654 "vptest\t{$src2, $src1|$src1, $src2}",
5655 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5658 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
5659 "vptest\t{$src2, $src1|$src1, $src2}",
5660 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
5662 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
5663 "vptest\t{$src2, $src1|$src1, $src2}",
5664 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
5668 let Defs = [EFLAGS] in {
5669 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5670 "ptest \t{$src2, $src1|$src1, $src2}",
5671 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5673 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5674 "ptest \t{$src2, $src1|$src1, $src2}",
5675 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5679 // The bit test instructions below are AVX only
5680 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
5681 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
5682 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
5683 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5684 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
5685 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
5686 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5687 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
5691 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5692 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
5693 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
5694 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
5695 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
5698 //===----------------------------------------------------------------------===//
5699 // SSE4.1 - Misc Instructions
5700 //===----------------------------------------------------------------------===//
5702 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
5703 "popcnt{w}\t{$src, $dst|$dst, $src}",
5704 [(set GR16:$dst, (ctpop GR16:$src))]>, OpSize, XS;
5705 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
5706 "popcnt{w}\t{$src, $dst|$dst, $src}",
5707 [(set GR16:$dst, (ctpop (loadi16 addr:$src)))]>, OpSize, XS;
5709 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
5710 "popcnt{l}\t{$src, $dst|$dst, $src}",
5711 [(set GR32:$dst, (ctpop GR32:$src))]>, XS;
5712 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
5713 "popcnt{l}\t{$src, $dst|$dst, $src}",
5714 [(set GR32:$dst, (ctpop (loadi32 addr:$src)))]>, XS;
5716 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
5717 "popcnt{q}\t{$src, $dst|$dst, $src}",
5718 [(set GR64:$dst, (ctpop GR64:$src))]>, XS;
5719 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
5720 "popcnt{q}\t{$src, $dst|$dst, $src}",
5721 [(set GR64:$dst, (ctpop (loadi64 addr:$src)))]>, XS;
5725 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
5726 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
5727 Intrinsic IntId128> {
5728 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5730 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5731 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
5732 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5734 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5737 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
5740 let Predicates = [HasAVX] in
5741 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
5742 int_x86_sse41_phminposuw>, VEX;
5743 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
5744 int_x86_sse41_phminposuw>;
5746 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
5747 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
5748 Intrinsic IntId128, bit Is2Addr = 1> {
5749 let isCommutable = 1 in
5750 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5751 (ins VR128:$src1, VR128:$src2),
5753 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5754 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5755 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
5756 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5757 (ins VR128:$src1, i128mem:$src2),
5759 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5760 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5762 (IntId128 VR128:$src1,
5763 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5766 let Predicates = [HasAVX] in {
5767 let isCommutable = 0 in
5768 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
5770 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
5772 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
5774 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
5776 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
5778 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
5780 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
5782 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
5784 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
5786 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
5788 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
5791 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
5792 (VPCMPEQQrr VR128:$src1, VR128:$src2)>;
5793 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
5794 (VPCMPEQQrm VR128:$src1, addr:$src2)>;
5797 let Constraints = "$src1 = $dst" in {
5798 let isCommutable = 0 in
5799 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
5800 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
5801 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
5802 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
5803 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
5804 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
5805 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
5806 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
5807 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
5808 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
5809 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
5812 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
5813 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
5814 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
5815 (PCMPEQQrm VR128:$src1, addr:$src2)>;
5817 /// SS48I_binop_rm - Simple SSE41 binary operator.
5818 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5819 ValueType OpVT, bit Is2Addr = 1> {
5820 let isCommutable = 1 in
5821 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5822 (ins VR128:$src1, VR128:$src2),
5824 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5825 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5826 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
5828 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5829 (ins VR128:$src1, i128mem:$src2),
5831 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5832 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5833 [(set VR128:$dst, (OpNode VR128:$src1,
5834 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
5838 let Predicates = [HasAVX] in
5839 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
5840 let Constraints = "$src1 = $dst" in
5841 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
5843 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
5844 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
5845 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
5846 X86MemOperand x86memop, bit Is2Addr = 1> {
5847 let isCommutable = 1 in
5848 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
5849 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
5851 !strconcat(OpcodeStr,
5852 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5853 !strconcat(OpcodeStr,
5854 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5855 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
5857 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
5858 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
5860 !strconcat(OpcodeStr,
5861 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5862 !strconcat(OpcodeStr,
5863 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5866 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
5870 let Predicates = [HasAVX] in {
5871 let isCommutable = 0 in {
5872 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
5873 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5874 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
5875 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5876 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
5877 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
5878 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
5879 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
5880 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
5881 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5882 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
5883 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5885 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
5886 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5887 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
5888 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5889 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
5890 VR256, memopv32i8, i256mem, 0>, VEX_4V;
5893 let Constraints = "$src1 = $dst" in {
5894 let isCommutable = 0 in {
5895 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
5896 VR128, memopv16i8, i128mem>;
5897 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
5898 VR128, memopv16i8, i128mem>;
5899 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
5900 VR128, memopv16i8, i128mem>;
5901 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
5902 VR128, memopv16i8, i128mem>;
5904 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
5905 VR128, memopv16i8, i128mem>;
5906 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
5907 VR128, memopv16i8, i128mem>;
5910 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
5911 let Predicates = [HasAVX] in {
5912 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
5913 RegisterClass RC, X86MemOperand x86memop,
5914 PatFrag mem_frag, Intrinsic IntId> {
5915 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
5916 (ins RC:$src1, RC:$src2, RC:$src3),
5917 !strconcat(OpcodeStr,
5918 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5919 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
5920 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
5922 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
5923 (ins RC:$src1, x86memop:$src2, RC:$src3),
5924 !strconcat(OpcodeStr,
5925 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5927 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
5929 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
5933 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
5934 memopv16i8, int_x86_sse41_blendvpd>;
5935 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
5936 memopv16i8, int_x86_sse41_blendvps>;
5937 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
5938 memopv16i8, int_x86_sse41_pblendvb>;
5939 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
5940 memopv32i8, int_x86_avx_blendv_pd_256>;
5941 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
5942 memopv32i8, int_x86_avx_blendv_ps_256>;
5944 let Predicates = [HasAVX] in {
5945 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
5946 (v16i8 VR128:$src2))),
5947 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
5948 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
5949 (v4i32 VR128:$src2))),
5950 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
5951 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
5952 (v4f32 VR128:$src2))),
5953 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
5954 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
5955 (v2i64 VR128:$src2))),
5956 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
5957 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
5958 (v2f64 VR128:$src2))),
5959 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
5960 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
5961 (v8i32 VR256:$src2))),
5962 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
5963 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
5964 (v8f32 VR256:$src2))),
5965 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
5966 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
5967 (v4i64 VR256:$src2))),
5968 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
5969 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
5970 (v4f64 VR256:$src2))),
5971 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
5974 /// SS41I_ternary_int - SSE 4.1 ternary operator
5975 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
5976 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5977 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5978 (ins VR128:$src1, VR128:$src2),
5979 !strconcat(OpcodeStr,
5980 "\t{$src2, $dst|$dst, $src2}"),
5981 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
5984 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5985 (ins VR128:$src1, i128mem:$src2),
5986 !strconcat(OpcodeStr,
5987 "\t{$src2, $dst|$dst, $src2}"),
5990 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
5994 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
5995 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
5996 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
5998 let Predicates = [HasSSE41] in {
5999 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6000 (v16i8 VR128:$src2))),
6001 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6002 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6003 (v4i32 VR128:$src2))),
6004 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6005 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6006 (v4f32 VR128:$src2))),
6007 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6008 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6009 (v2i64 VR128:$src2))),
6010 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6011 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6012 (v2f64 VR128:$src2))),
6013 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6016 let Predicates = [HasAVX] in
6017 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6018 "vmovntdqa\t{$src, $dst|$dst, $src}",
6019 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6021 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6022 "movntdqa\t{$src, $dst|$dst, $src}",
6023 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6026 //===----------------------------------------------------------------------===//
6027 // SSE4.2 - Compare Instructions
6028 //===----------------------------------------------------------------------===//
6030 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
6031 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
6032 Intrinsic IntId128, bit Is2Addr = 1> {
6033 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
6034 (ins VR128:$src1, VR128:$src2),
6036 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6037 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6038 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
6040 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
6041 (ins VR128:$src1, i128mem:$src2),
6043 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6044 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6046 (IntId128 VR128:$src1,
6047 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
6050 let Predicates = [HasAVX] in {
6051 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
6054 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
6055 (VPCMPGTQrr VR128:$src1, VR128:$src2)>;
6056 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
6057 (VPCMPGTQrm VR128:$src1, addr:$src2)>;
6060 let Constraints = "$src1 = $dst" in
6061 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
6063 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
6064 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
6065 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
6066 (PCMPGTQrm VR128:$src1, addr:$src2)>;
6068 //===----------------------------------------------------------------------===//
6069 // SSE4.2 - String/text Processing Instructions
6070 //===----------------------------------------------------------------------===//
6072 // Packed Compare Implicit Length Strings, Return Mask
6073 multiclass pseudo_pcmpistrm<string asm> {
6074 def REG : PseudoI<(outs VR128:$dst),
6075 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6076 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6078 def MEM : PseudoI<(outs VR128:$dst),
6079 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6080 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6081 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6084 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6085 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
6086 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6089 let Defs = [XMM0, EFLAGS], Predicates = [HasAVX] in {
6090 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6091 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6092 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6093 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6094 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6095 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6098 let Defs = [XMM0, EFLAGS] in {
6099 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6100 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6101 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6102 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6103 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6104 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6107 // Packed Compare Explicit Length Strings, Return Mask
6108 multiclass pseudo_pcmpestrm<string asm> {
6109 def REG : PseudoI<(outs VR128:$dst),
6110 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6111 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6112 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6113 def MEM : PseudoI<(outs VR128:$dst),
6114 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6115 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6116 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6119 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6120 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
6121 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6124 let Predicates = [HasAVX],
6125 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
6126 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6127 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6128 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6129 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6130 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6131 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6134 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
6135 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6136 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6137 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6138 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6139 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6140 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6143 // Packed Compare Implicit Length Strings, Return Index
6144 let Defs = [ECX, EFLAGS] in {
6145 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
6146 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6147 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6148 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6149 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
6150 (implicit EFLAGS)]>, OpSize;
6151 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6152 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6153 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6154 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
6155 (implicit EFLAGS)]>, OpSize;
6159 let Predicates = [HasAVX] in {
6160 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
6162 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
6164 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
6166 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
6168 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
6170 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
6174 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
6175 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
6176 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
6177 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
6178 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
6179 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
6181 // Packed Compare Explicit Length Strings, Return Index
6182 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
6183 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
6184 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6185 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6186 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6187 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
6188 (implicit EFLAGS)]>, OpSize;
6189 def rm : SS42AI<0x61, MRMSrcMem, (outs),
6190 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6191 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6193 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
6194 (implicit EFLAGS)]>, OpSize;
6198 let Predicates = [HasAVX] in {
6199 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
6201 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
6203 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
6205 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
6207 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
6209 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
6213 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
6214 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
6215 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
6216 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
6217 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
6218 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
6220 //===----------------------------------------------------------------------===//
6221 // SSE4.2 - CRC Instructions
6222 //===----------------------------------------------------------------------===//
6224 // No CRC instructions have AVX equivalents
6226 // crc intrinsic instruction
6227 // This set of instructions are only rm, the only difference is the size
6229 let Constraints = "$src1 = $dst" in {
6230 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
6231 (ins GR32:$src1, i8mem:$src2),
6232 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6234 (int_x86_sse42_crc32_32_8 GR32:$src1,
6235 (load addr:$src2)))]>;
6236 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
6237 (ins GR32:$src1, GR8:$src2),
6238 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6240 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
6241 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6242 (ins GR32:$src1, i16mem:$src2),
6243 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6245 (int_x86_sse42_crc32_32_16 GR32:$src1,
6246 (load addr:$src2)))]>,
6248 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6249 (ins GR32:$src1, GR16:$src2),
6250 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6252 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
6254 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6255 (ins GR32:$src1, i32mem:$src2),
6256 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6258 (int_x86_sse42_crc32_32_32 GR32:$src1,
6259 (load addr:$src2)))]>;
6260 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6261 (ins GR32:$src1, GR32:$src2),
6262 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6264 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
6265 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
6266 (ins GR64:$src1, i8mem:$src2),
6267 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6269 (int_x86_sse42_crc32_64_8 GR64:$src1,
6270 (load addr:$src2)))]>,
6272 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
6273 (ins GR64:$src1, GR8:$src2),
6274 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6276 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
6278 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
6279 (ins GR64:$src1, i64mem:$src2),
6280 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6282 (int_x86_sse42_crc32_64_64 GR64:$src1,
6283 (load addr:$src2)))]>,
6285 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
6286 (ins GR64:$src1, GR64:$src2),
6287 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6289 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
6293 //===----------------------------------------------------------------------===//
6294 // AES-NI Instructions
6295 //===----------------------------------------------------------------------===//
6297 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
6298 Intrinsic IntId128, bit Is2Addr = 1> {
6299 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
6300 (ins VR128:$src1, VR128:$src2),
6302 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6303 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6304 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
6306 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
6307 (ins VR128:$src1, i128mem:$src2),
6309 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6310 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6312 (IntId128 VR128:$src1,
6313 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
6316 // Perform One Round of an AES Encryption/Decryption Flow
6317 let Predicates = [HasAVX, HasAES] in {
6318 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
6319 int_x86_aesni_aesenc, 0>, VEX_4V;
6320 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
6321 int_x86_aesni_aesenclast, 0>, VEX_4V;
6322 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
6323 int_x86_aesni_aesdec, 0>, VEX_4V;
6324 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
6325 int_x86_aesni_aesdeclast, 0>, VEX_4V;
6328 let Constraints = "$src1 = $dst" in {
6329 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
6330 int_x86_aesni_aesenc>;
6331 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
6332 int_x86_aesni_aesenclast>;
6333 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
6334 int_x86_aesni_aesdec>;
6335 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
6336 int_x86_aesni_aesdeclast>;
6339 let Predicates = [HasAES] in {
6340 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
6341 (AESENCrr VR128:$src1, VR128:$src2)>;
6342 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
6343 (AESENCrm VR128:$src1, addr:$src2)>;
6344 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
6345 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
6346 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
6347 (AESENCLASTrm VR128:$src1, addr:$src2)>;
6348 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
6349 (AESDECrr VR128:$src1, VR128:$src2)>;
6350 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
6351 (AESDECrm VR128:$src1, addr:$src2)>;
6352 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
6353 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
6354 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
6355 (AESDECLASTrm VR128:$src1, addr:$src2)>;
6358 let Predicates = [HasAVX, HasAES], AddedComplexity = 20 in {
6359 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
6360 (VAESENCrr VR128:$src1, VR128:$src2)>;
6361 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
6362 (VAESENCrm VR128:$src1, addr:$src2)>;
6363 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
6364 (VAESENCLASTrr VR128:$src1, VR128:$src2)>;
6365 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
6366 (VAESENCLASTrm VR128:$src1, addr:$src2)>;
6367 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
6368 (VAESDECrr VR128:$src1, VR128:$src2)>;
6369 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
6370 (VAESDECrm VR128:$src1, addr:$src2)>;
6371 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
6372 (VAESDECLASTrr VR128:$src1, VR128:$src2)>;
6373 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
6374 (VAESDECLASTrm VR128:$src1, addr:$src2)>;
6377 // Perform the AES InvMixColumn Transformation
6378 let Predicates = [HasAVX, HasAES] in {
6379 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6381 "vaesimc\t{$src1, $dst|$dst, $src1}",
6383 (int_x86_aesni_aesimc VR128:$src1))]>,
6385 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
6386 (ins i128mem:$src1),
6387 "vaesimc\t{$src1, $dst|$dst, $src1}",
6389 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
6392 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6394 "aesimc\t{$src1, $dst|$dst, $src1}",
6396 (int_x86_aesni_aesimc VR128:$src1))]>,
6398 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
6399 (ins i128mem:$src1),
6400 "aesimc\t{$src1, $dst|$dst, $src1}",
6402 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
6405 // AES Round Key Generation Assist
6406 let Predicates = [HasAVX, HasAES] in {
6407 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
6408 (ins VR128:$src1, i8imm:$src2),
6409 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6411 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
6413 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
6414 (ins i128mem:$src1, i8imm:$src2),
6415 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6417 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
6421 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
6422 (ins VR128:$src1, i8imm:$src2),
6423 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6425 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
6427 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
6428 (ins i128mem:$src1, i8imm:$src2),
6429 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6431 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
6435 //===----------------------------------------------------------------------===//
6436 // CLMUL Instructions
6437 //===----------------------------------------------------------------------===//
6439 // Carry-less Multiplication instructions
6440 let Constraints = "$src1 = $dst" in {
6441 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
6442 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6443 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
6446 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
6447 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6448 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
6452 // AVX carry-less Multiplication instructions
6453 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
6454 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6455 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6458 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
6459 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6460 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6464 multiclass pclmul_alias<string asm, int immop> {
6465 def : InstAlias<!strconcat("pclmul", asm,
6466 "dq {$src, $dst|$dst, $src}"),
6467 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
6469 def : InstAlias<!strconcat("pclmul", asm,
6470 "dq {$src, $dst|$dst, $src}"),
6471 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
6473 def : InstAlias<!strconcat("vpclmul", asm,
6474 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
6475 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
6477 def : InstAlias<!strconcat("vpclmul", asm,
6478 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
6479 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
6481 defm : pclmul_alias<"hqhq", 0x11>;
6482 defm : pclmul_alias<"hqlq", 0x01>;
6483 defm : pclmul_alias<"lqhq", 0x10>;
6484 defm : pclmul_alias<"lqlq", 0x00>;
6486 //===----------------------------------------------------------------------===//
6488 //===----------------------------------------------------------------------===//
6490 //===----------------------------------------------------------------------===//
6491 // VBROADCAST - Load from memory and broadcast to all elements of the
6492 // destination operand
6494 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
6495 X86MemOperand x86memop, Intrinsic Int> :
6496 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
6497 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6498 [(set RC:$dst, (Int addr:$src))]>, VEX;
6500 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
6501 int_x86_avx_vbroadcastss>;
6502 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
6503 int_x86_avx_vbroadcastss_256>;
6504 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
6505 int_x86_avx_vbroadcast_sd_256>;
6506 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
6507 int_x86_avx_vbroadcastf128_pd_256>;
6509 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
6510 (VBROADCASTF128 addr:$src)>;
6512 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
6513 (VBROADCASTSSY addr:$src)>;
6514 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
6515 (VBROADCASTSD addr:$src)>;
6516 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
6517 (VBROADCASTSSY addr:$src)>;
6518 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
6519 (VBROADCASTSD addr:$src)>;
6521 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
6522 (VBROADCASTSS addr:$src)>;
6523 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
6524 (VBROADCASTSS addr:$src)>;
6526 //===----------------------------------------------------------------------===//
6527 // VINSERTF128 - Insert packed floating-point values
6529 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
6530 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
6531 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6533 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
6534 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
6535 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6538 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
6539 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6540 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
6541 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6542 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
6543 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6545 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
6547 (VINSERTF128rr VR256:$src1, VR128:$src2,
6548 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6549 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
6551 (VINSERTF128rr VR256:$src1, VR128:$src2,
6552 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6553 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
6555 (VINSERTF128rr VR256:$src1, VR128:$src2,
6556 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6557 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
6559 (VINSERTF128rr VR256:$src1, VR128:$src2,
6560 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6561 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
6563 (VINSERTF128rr VR256:$src1, VR128:$src2,
6564 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6565 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
6567 (VINSERTF128rr VR256:$src1, VR128:$src2,
6568 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6570 //===----------------------------------------------------------------------===//
6571 // VEXTRACTF128 - Extract packed floating-point values
6573 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
6574 (ins VR256:$src1, i8imm:$src2),
6575 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6577 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
6578 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
6579 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6582 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
6583 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6584 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
6585 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6586 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
6587 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6589 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6590 (v4f32 (VEXTRACTF128rr
6591 (v8f32 VR256:$src1),
6592 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6593 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6594 (v2f64 (VEXTRACTF128rr
6595 (v4f64 VR256:$src1),
6596 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6597 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6598 (v4i32 (VEXTRACTF128rr
6599 (v8i32 VR256:$src1),
6600 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6601 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6602 (v2i64 (VEXTRACTF128rr
6603 (v4i64 VR256:$src1),
6604 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6605 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6606 (v8i16 (VEXTRACTF128rr
6607 (v16i16 VR256:$src1),
6608 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6609 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6610 (v16i8 (VEXTRACTF128rr
6611 (v32i8 VR256:$src1),
6612 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6614 //===----------------------------------------------------------------------===//
6615 // VMASKMOV - Conditional SIMD Packed Loads and Stores
6617 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
6618 Intrinsic IntLd, Intrinsic IntLd256,
6619 Intrinsic IntSt, Intrinsic IntSt256,
6620 PatFrag pf128, PatFrag pf256> {
6621 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
6622 (ins VR128:$src1, f128mem:$src2),
6623 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6624 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
6626 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
6627 (ins VR256:$src1, f256mem:$src2),
6628 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6629 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
6631 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
6632 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
6633 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6634 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
6635 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
6636 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
6637 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6638 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
6641 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
6642 int_x86_avx_maskload_ps,
6643 int_x86_avx_maskload_ps_256,
6644 int_x86_avx_maskstore_ps,
6645 int_x86_avx_maskstore_ps_256,
6646 memopv4f32, memopv8f32>;
6647 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
6648 int_x86_avx_maskload_pd,
6649 int_x86_avx_maskload_pd_256,
6650 int_x86_avx_maskstore_pd,
6651 int_x86_avx_maskstore_pd_256,
6652 memopv2f64, memopv4f64>;
6654 //===----------------------------------------------------------------------===//
6655 // VPERMIL - Permute Single and Double Floating-Point Values
6657 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
6658 RegisterClass RC, X86MemOperand x86memop_f,
6659 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
6660 Intrinsic IntVar, Intrinsic IntImm> {
6661 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
6662 (ins RC:$src1, RC:$src2),
6663 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6664 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
6665 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
6666 (ins RC:$src1, x86memop_i:$src2),
6667 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6668 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
6670 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
6671 (ins RC:$src1, i8imm:$src2),
6672 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6673 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
6674 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
6675 (ins x86memop_f:$src1, i8imm:$src2),
6676 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6677 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
6680 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
6681 memopv4f32, memopv4i32,
6682 int_x86_avx_vpermilvar_ps,
6683 int_x86_avx_vpermil_ps>;
6684 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
6685 memopv8f32, memopv8i32,
6686 int_x86_avx_vpermilvar_ps_256,
6687 int_x86_avx_vpermil_ps_256>;
6688 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
6689 memopv2f64, memopv2i64,
6690 int_x86_avx_vpermilvar_pd,
6691 int_x86_avx_vpermil_pd>;
6692 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
6693 memopv4f64, memopv4i64,
6694 int_x86_avx_vpermilvar_pd_256,
6695 int_x86_avx_vpermil_pd_256>;
6697 def : Pat<(v8f32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
6698 (VPERMILPSYri VR256:$src1, imm:$imm)>;
6699 def : Pat<(v4f64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
6700 (VPERMILPDYri VR256:$src1, imm:$imm)>;
6701 def : Pat<(v8i32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
6702 (VPERMILPSYri VR256:$src1, imm:$imm)>;
6703 def : Pat<(v4i64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
6704 (VPERMILPDYri VR256:$src1, imm:$imm)>;
6706 //===----------------------------------------------------------------------===//
6707 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
6709 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
6710 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
6711 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6713 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
6714 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
6715 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6718 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
6719 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6720 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
6721 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6722 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
6723 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6725 def : Pat<(int_x86_avx_vperm2f128_ps_256
6726 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
6727 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6728 def : Pat<(int_x86_avx_vperm2f128_pd_256
6729 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
6730 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6731 def : Pat<(int_x86_avx_vperm2f128_si_256
6732 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
6733 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6735 def : Pat<(v8f32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6736 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6737 def : Pat<(v8i32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6738 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6739 def : Pat<(v4i64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6740 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6741 def : Pat<(v4f64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6742 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6743 def : Pat<(v32i8 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6744 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6745 def : Pat<(v16i16 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6746 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6748 //===----------------------------------------------------------------------===//
6749 // VZERO - Zero YMM registers
6751 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
6752 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
6753 // Zero All YMM registers
6754 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
6755 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
6757 // Zero Upper bits of YMM registers
6758 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
6759 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;