1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pshufb : SDNode<"X86ISD::PSHUFB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
42 def X86pextrb : SDNode<"X86ISD::PEXTRB",
43 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
44 def X86pextrw : SDNode<"X86ISD::PEXTRW",
45 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
46 def X86pinsrb : SDNode<"X86ISD::PINSRB",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86pinsrw : SDNode<"X86ISD::PINSRW",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
52 def X86insrtps : SDNode<"X86ISD::INSERTPS",
53 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
54 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
55 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
56 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
57 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
58 [SDNPHasChain, SDNPMayLoad]>;
59 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
60 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
61 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
62 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
63 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
65 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
66 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
67 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
68 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
69 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
70 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
72 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
75 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
77 //===----------------------------------------------------------------------===//
78 // SSE Complex Patterns
79 //===----------------------------------------------------------------------===//
81 // These are 'extloads' from a scalar to the low element of a vector, zeroing
82 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
84 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
85 [SDNPHasChain, SDNPMayLoad]>;
86 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
87 [SDNPHasChain, SDNPMayLoad]>;
89 def ssmem : Operand<v4f32> {
90 let PrintMethod = "printf32mem";
91 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
92 let ParserMatchClass = X86MemAsmOperand;
94 def sdmem : Operand<v2f64> {
95 let PrintMethod = "printf64mem";
96 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
97 let ParserMatchClass = X86MemAsmOperand;
100 //===----------------------------------------------------------------------===//
101 // SSE pattern fragments
102 //===----------------------------------------------------------------------===//
104 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
105 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
106 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
107 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
109 // Like 'store', but always requires vector alignment.
110 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
111 (store node:$val, node:$ptr), [{
112 return cast<StoreSDNode>(N)->getAlignment() >= 16;
115 // Like 'load', but always requires vector alignment.
116 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
117 return cast<LoadSDNode>(N)->getAlignment() >= 16;
120 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
121 (f32 (alignedload node:$ptr))>;
122 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
123 (f64 (alignedload node:$ptr))>;
124 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
125 (v4f32 (alignedload node:$ptr))>;
126 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
127 (v2f64 (alignedload node:$ptr))>;
128 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
129 (v4i32 (alignedload node:$ptr))>;
130 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
131 (v2i64 (alignedload node:$ptr))>;
133 // Like 'load', but uses special alignment checks suitable for use in
134 // memory operands in most SSE instructions, which are required to
135 // be naturally aligned on some targets but not on others. If the subtarget
136 // allows unaligned accesses, match any load, though this may require
137 // setting a feature bit in the processor (on startup, for example).
138 // Opteron 10h and later implement such a feature.
139 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
140 return Subtarget->hasVectorUAMem()
141 || cast<LoadSDNode>(N)->getAlignment() >= 16;
144 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
145 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
146 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
147 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
148 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
149 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
150 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
152 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
154 // FIXME: 8 byte alignment for mmx reads is not required
155 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
156 return cast<LoadSDNode>(N)->getAlignment() >= 8;
159 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
160 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
161 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
162 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
165 // Like 'store', but requires the non-temporal bit to be set
166 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
167 (st node:$val, node:$ptr), [{
168 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
169 return ST->isNonTemporal();
173 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
174 (st node:$val, node:$ptr), [{
175 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
176 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
177 ST->getAddressingMode() == ISD::UNINDEXED &&
178 ST->getAlignment() >= 16;
182 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
183 (st node:$val, node:$ptr), [{
184 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
185 return ST->isNonTemporal() &&
186 ST->getAlignment() < 16;
190 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
191 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
192 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
193 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
194 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
195 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
197 def vzmovl_v2i64 : PatFrag<(ops node:$src),
198 (bitconvert (v2i64 (X86vzmovl
199 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
200 def vzmovl_v4i32 : PatFrag<(ops node:$src),
201 (bitconvert (v4i32 (X86vzmovl
202 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
204 def vzload_v2i64 : PatFrag<(ops node:$src),
205 (bitconvert (v2i64 (X86vzload node:$src)))>;
208 def fp32imm0 : PatLeaf<(f32 fpimm), [{
209 return N->isExactlyValue(+0.0);
212 // BYTE_imm - Transform bit immediates into byte immediates.
213 def BYTE_imm : SDNodeXForm<imm, [{
214 // Transformation function: imm >> 3
215 return getI32Imm(N->getZExtValue() >> 3);
218 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
220 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
221 return getI8Imm(X86::getShuffleSHUFImmediate(N));
224 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
226 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
227 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
230 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
232 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
233 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
236 // SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to
238 def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{
239 return getI8Imm(X86::getShufflePALIGNRImmediate(N));
242 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
243 (vector_shuffle node:$lhs, node:$rhs), [{
244 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
245 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
248 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
249 (vector_shuffle node:$lhs, node:$rhs), [{
250 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
253 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
254 (vector_shuffle node:$lhs, node:$rhs), [{
255 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
258 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
259 (vector_shuffle node:$lhs, node:$rhs), [{
260 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
263 def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
264 (vector_shuffle node:$lhs, node:$rhs), [{
265 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
268 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
269 (vector_shuffle node:$lhs, node:$rhs), [{
270 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
273 def movl : PatFrag<(ops node:$lhs, node:$rhs),
274 (vector_shuffle node:$lhs, node:$rhs), [{
275 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
278 def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
279 (vector_shuffle node:$lhs, node:$rhs), [{
280 return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
283 def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
284 (vector_shuffle node:$lhs, node:$rhs), [{
285 return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
288 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
289 (vector_shuffle node:$lhs, node:$rhs), [{
290 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
293 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
294 (vector_shuffle node:$lhs, node:$rhs), [{
295 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
298 def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
299 (vector_shuffle node:$lhs, node:$rhs), [{
300 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
303 def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
304 (vector_shuffle node:$lhs, node:$rhs), [{
305 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
308 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
309 (vector_shuffle node:$lhs, node:$rhs), [{
310 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
311 }], SHUFFLE_get_shuf_imm>;
313 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
314 (vector_shuffle node:$lhs, node:$rhs), [{
315 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
316 }], SHUFFLE_get_shuf_imm>;
318 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
319 (vector_shuffle node:$lhs, node:$rhs), [{
320 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
321 }], SHUFFLE_get_pshufhw_imm>;
323 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
324 (vector_shuffle node:$lhs, node:$rhs), [{
325 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
326 }], SHUFFLE_get_pshuflw_imm>;
328 def palign : PatFrag<(ops node:$lhs, node:$rhs),
329 (vector_shuffle node:$lhs, node:$rhs), [{
330 return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
331 }], SHUFFLE_get_palign_imm>;
333 //===----------------------------------------------------------------------===//
334 // SSE scalar FP Instructions
335 //===----------------------------------------------------------------------===//
337 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
338 // instruction selection into a branch sequence.
339 let Uses = [EFLAGS], usesCustomInserter = 1 in {
340 def CMOV_FR32 : I<0, Pseudo,
341 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
342 "#CMOV_FR32 PSEUDO!",
343 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
345 def CMOV_FR64 : I<0, Pseudo,
346 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
347 "#CMOV_FR64 PSEUDO!",
348 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
350 def CMOV_V4F32 : I<0, Pseudo,
351 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
352 "#CMOV_V4F32 PSEUDO!",
354 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
356 def CMOV_V2F64 : I<0, Pseudo,
357 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
358 "#CMOV_V2F64 PSEUDO!",
360 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
362 def CMOV_V2I64 : I<0, Pseudo,
363 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
364 "#CMOV_V2I64 PSEUDO!",
366 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
370 //===----------------------------------------------------------------------===//
371 // SSE 1 & 2 Instructions Classes
372 //===----------------------------------------------------------------------===//
374 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
375 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
376 RegisterClass RC, X86MemOperand x86memop> {
377 let isCommutable = 1 in {
378 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
379 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
381 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
382 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
385 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
386 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
387 string asm, string SSEVer, string FPSizeStr,
388 Operand memopr, ComplexPattern mem_cpat> {
389 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
390 asm, [(set RC:$dst, (
391 !nameconcat<Intrinsic>("int_x86_sse",
392 !strconcat(SSEVer, !strconcat("_",
393 !strconcat(OpcodeStr, FPSizeStr))))
394 RC:$src1, RC:$src2))]>;
395 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
396 asm, [(set RC:$dst, (
397 !nameconcat<Intrinsic>("int_x86_sse",
398 !strconcat(SSEVer, !strconcat("_",
399 !strconcat(OpcodeStr, FPSizeStr))))
400 RC:$src1, mem_cpat:$src2))]>;
403 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
404 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
405 RegisterClass RC, ValueType vt,
406 X86MemOperand x86memop, PatFrag mem_frag,
407 Domain d, bit MayLoad = 0> {
408 let isCommutable = 1 in
409 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
410 OpcodeStr, [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))],d>;
411 let mayLoad = MayLoad in
412 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
413 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1,
414 (mem_frag addr:$src2)))],d>;
417 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
418 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
419 string OpcodeStr, X86MemOperand x86memop,
420 list<dag> pat_rr, list<dag> pat_rm> {
421 let isCommutable = 1 in
422 def rr : PI<opc, MRMSrcReg, (outs RC:$dst),
423 (ins RC:$src1, RC:$src2), OpcodeStr, pat_rr, d>;
424 def rm : PI<opc, MRMSrcMem, (outs RC:$dst),
425 (ins RC:$src1, x86memop:$src2), OpcodeStr, pat_rm, d>;
428 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
429 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
430 string asm, string SSEVer, string FPSizeStr,
431 X86MemOperand x86memop, PatFrag mem_frag,
433 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
434 asm, [(set RC:$dst, (
435 !nameconcat<Intrinsic>("int_x86_sse",
436 !strconcat(SSEVer, !strconcat("_",
437 !strconcat(OpcodeStr, FPSizeStr))))
438 RC:$src1, RC:$src2))], d>;
439 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
440 asm, [(set RC:$dst, (
441 !nameconcat<Intrinsic>("int_x86_sse",
442 !strconcat(SSEVer, !strconcat("_",
443 !strconcat(OpcodeStr, FPSizeStr))))
444 RC:$src1, (mem_frag addr:$src2)))], d>;
447 //===----------------------------------------------------------------------===//
449 //===----------------------------------------------------------------------===//
451 // Move Instructions. Register-to-register movss is not used for FR32
452 // register copies because it's a partial register update; FsMOVAPSrr is
453 // used instead. Register-to-register movss is not modeled as an INSERT_SUBREG
454 // because INSERT_SUBREG requires that the insert be implementable in terms of
455 // a copy, and just mentioned, we don't use movss for copies.
456 let Constraints = "$src1 = $dst" in
457 def MOVSSrr : SSI<0x10, MRMSrcReg,
458 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
459 "movss\t{$src2, $dst|$dst, $src2}",
460 [(set (v4f32 VR128:$dst),
461 (movl VR128:$src1, (scalar_to_vector FR32:$src2)))]>;
463 // Extract the low 32-bit value from one vector and insert it into another.
464 let AddedComplexity = 15 in
465 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
466 (MOVSSrr (v4f32 VR128:$src1),
467 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
469 // Implicitly promote a 32-bit scalar to a vector.
470 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
471 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
473 // Loading from memory automatically zeroing upper bits.
474 let canFoldAsLoad = 1, isReMaterializable = 1 in
475 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
476 "movss\t{$src, $dst|$dst, $src}",
477 [(set FR32:$dst, (loadf32 addr:$src))]>;
479 // MOVSSrm zeros the high parts of the register; represent this
480 // with SUBREG_TO_REG.
481 let AddedComplexity = 20 in {
482 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
483 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
484 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
485 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
486 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
487 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
490 // Store scalar value to memory.
491 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
492 "movss\t{$src, $dst|$dst, $src}",
493 [(store FR32:$src, addr:$dst)]>;
495 // Extract and store.
496 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
499 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
501 // Conversion instructions
502 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
503 "cvttss2si\t{$src, $dst|$dst, $src}",
504 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
505 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
506 "cvttss2si\t{$src, $dst|$dst, $src}",
507 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
508 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
509 "cvtsi2ss\t{$src, $dst|$dst, $src}",
510 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
511 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
512 "cvtsi2ss\t{$src, $dst|$dst, $src}",
513 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
515 // Match intrinsics which expect XMM operand(s).
516 def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
517 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
518 def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
519 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
521 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
522 "cvtss2si\t{$src, $dst|$dst, $src}",
523 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
524 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
525 "cvtss2si\t{$src, $dst|$dst, $src}",
526 [(set GR32:$dst, (int_x86_sse_cvtss2si
527 (load addr:$src)))]>;
529 // Match intrinsics which expect MM and XMM operand(s).
530 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
531 "cvtps2pi\t{$src, $dst|$dst, $src}",
532 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
533 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
534 "cvtps2pi\t{$src, $dst|$dst, $src}",
535 [(set VR64:$dst, (int_x86_sse_cvtps2pi
536 (load addr:$src)))]>;
537 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
538 "cvttps2pi\t{$src, $dst|$dst, $src}",
539 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
540 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
541 "cvttps2pi\t{$src, $dst|$dst, $src}",
542 [(set VR64:$dst, (int_x86_sse_cvttps2pi
543 (load addr:$src)))]>;
544 let Constraints = "$src1 = $dst" in {
545 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
546 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
547 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
548 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
550 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
551 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
552 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
553 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
554 (load addr:$src2)))]>;
557 // Aliases for intrinsics
558 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
559 "cvttss2si\t{$src, $dst|$dst, $src}",
561 (int_x86_sse_cvttss2si VR128:$src))]>;
562 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
563 "cvttss2si\t{$src, $dst|$dst, $src}",
565 (int_x86_sse_cvttss2si(load addr:$src)))]>;
567 let Constraints = "$src1 = $dst" in {
568 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
569 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
570 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
571 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
573 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
574 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
575 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
576 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
577 (loadi32 addr:$src2)))]>;
580 // Comparison instructions
581 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
582 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
583 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
584 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
586 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
587 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
588 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
590 // Accept explicit immediate argument form instead of comparison code.
591 let isAsmParserOnly = 1 in {
592 def CMPSSrr_alt : SSIi8<0xC2, MRMSrcReg,
593 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
594 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
596 def CMPSSrm_alt : SSIi8<0xC2, MRMSrcMem,
597 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
598 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
602 let Defs = [EFLAGS] in {
603 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
604 "ucomiss\t{$src2, $src1|$src1, $src2}",
605 [(set EFLAGS, (X86cmp FR32:$src1, FR32:$src2))]>;
606 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
607 "ucomiss\t{$src2, $src1|$src1, $src2}",
608 [(set EFLAGS, (X86cmp FR32:$src1, (loadf32 addr:$src2)))]>;
610 def COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
611 "comiss\t{$src2, $src1|$src1, $src2}", []>;
612 def COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
613 "comiss\t{$src2, $src1|$src1, $src2}", []>;
617 // Aliases to match intrinsics which expect XMM operand(s).
618 let Constraints = "$src1 = $dst" in {
619 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
621 (ins VR128:$src1, VR128:$src, SSECC:$cc),
622 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
623 [(set VR128:$dst, (int_x86_sse_cmp_ss
625 VR128:$src, imm:$cc))]>;
626 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
628 (ins VR128:$src1, f32mem:$src, SSECC:$cc),
629 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
630 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
631 (load addr:$src), imm:$cc))]>;
634 let Defs = [EFLAGS] in {
635 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
636 "ucomiss\t{$src2, $src1|$src1, $src2}",
637 [(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
639 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
640 "ucomiss\t{$src2, $src1|$src1, $src2}",
641 [(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
642 (load addr:$src2)))]>;
644 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
645 "comiss\t{$src2, $src1|$src1, $src2}",
646 [(set EFLAGS, (X86comi (v4f32 VR128:$src1),
648 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
649 "comiss\t{$src2, $src1|$src1, $src2}",
650 [(set EFLAGS, (X86comi (v4f32 VR128:$src1),
651 (load addr:$src2)))]>;
654 // Aliases of packed SSE1 instructions for scalar use. These all have names
655 // that start with 'Fs'.
657 // Alias instructions that map fld0 to pxor for sse.
658 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
660 // FIXME: Set encoding to pseudo!
661 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
662 [(set FR32:$dst, fp32imm0)]>,
663 Requires<[HasSSE1]>, TB, OpSize;
665 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
667 let neverHasSideEffects = 1 in
668 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
669 "movaps\t{$src, $dst|$dst, $src}", []>;
671 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
673 let canFoldAsLoad = 1, isReMaterializable = 1 in
674 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
675 "movaps\t{$src, $dst|$dst, $src}",
676 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
678 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
680 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
681 SDNode OpNode, bit MayLoad = 0> {
682 let isAsmParserOnly = 1 in {
683 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
684 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode, FR32,
685 f32, f128mem, memopfsf32, SSEPackedSingle, MayLoad>, VEX_4V;
687 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
688 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode, FR64,
689 f64, f128mem, memopfsf64, SSEPackedDouble, MayLoad>, OpSize,
693 let Constraints = "$src1 = $dst" in {
694 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
695 "ps\t{$src2, $dst|$dst, $src2}"), OpNode, FR32, f32,
696 f128mem, memopfsf32, SSEPackedSingle, MayLoad>, TB;
698 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
699 "pd\t{$src2, $dst|$dst, $src2}"), OpNode, FR64, f64,
700 f128mem, memopfsf64, SSEPackedDouble, MayLoad>, TB, OpSize;
704 // Alias bitwise logical operations using SSE logical ops on packed FP values.
705 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
706 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
707 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
709 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
710 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef, 1>;
712 /// basic_sse12_fp_binop_rm - SSE 1 & 2 binops come in both scalar and
715 /// In addition, we also have a special variant of the scalar form here to
716 /// represent the associated intrinsic operation. This form is unlike the
717 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
718 /// and leaves the top elements unmodified (therefore these cannot be commuted).
720 /// These three forms can each be reg+reg or reg+mem, so there are a total of
721 /// six "instructions".
723 multiclass basic_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
726 let isAsmParserOnly = 1 in {
727 defm V#NAME#SS : sse12_fp_scalar<opc,
728 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
729 OpNode, FR32, f32mem>, XS, VEX_4V;
731 defm V#NAME#SD : sse12_fp_scalar<opc,
732 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
733 OpNode, FR64, f64mem>, XD, VEX_4V;
735 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
736 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
737 VR128, v4f32, f128mem, memopv4f32, SSEPackedSingle>,
740 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
741 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
742 VR128, v2f64, f128mem, memopv2f64, SSEPackedDouble>,
745 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
746 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
747 "", "_ss", ssmem, sse_load_f32>, XS, VEX_4V;
749 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
750 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
751 "2", "_sd", sdmem, sse_load_f64>, XD, VEX_4V;
754 let Constraints = "$src1 = $dst" in {
755 defm SS : sse12_fp_scalar<opc,
756 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
757 OpNode, FR32, f32mem>, XS;
759 defm SD : sse12_fp_scalar<opc,
760 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
761 OpNode, FR64, f64mem>, XD;
763 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
764 "ps\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v4f32,
765 f128mem, memopv4f32, SSEPackedSingle>, TB;
767 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
768 "pd\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v2f64,
769 f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
771 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
772 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
773 "", "_ss", ssmem, sse_load_f32>, XS;
775 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
776 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
777 "2", "_sd", sdmem, sse_load_f64>, XD;
781 // Arithmetic instructions
782 defm ADD : basic_sse12_fp_binop_rm<0x58, "add", fadd>;
783 defm MUL : basic_sse12_fp_binop_rm<0x59, "mul", fmul>;
785 let isCommutable = 0 in {
786 defm SUB : basic_sse12_fp_binop_rm<0x5C, "sub", fsub>;
787 defm DIV : basic_sse12_fp_binop_rm<0x5E, "div", fdiv>;
790 /// sse12_fp_binop_rm - Other SSE 1 & 2 binops
792 /// This multiclass is like basic_sse12_fp_binop_rm, with the addition of
793 /// instructions for a full-vector intrinsic form. Operations that map
794 /// onto C operators don't use this form since they just use the plain
795 /// vector form instead of having a separate vector intrinsic form.
797 /// This provides a total of eight "instructions".
799 multiclass sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
802 let isAsmParserOnly = 1 in {
803 // Scalar operation, reg+reg.
804 defm V#NAME#SS : sse12_fp_scalar<opc,
805 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
806 OpNode, FR32, f32mem>, XS, VEX_4V;
808 defm V#NAME#SD : sse12_fp_scalar<opc,
809 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
810 OpNode, FR64, f64mem>, XD, VEX_4V;
812 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
813 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
814 VR128, v4f32, f128mem, memopv4f32, SSEPackedSingle>,
817 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
818 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
819 VR128, v2f64, f128mem, memopv2f64, SSEPackedDouble>,
822 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
823 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
824 "", "_ss", ssmem, sse_load_f32>, XS, VEX_4V;
826 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
827 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
828 "2", "_sd", sdmem, sse_load_f64>, XD, VEX_4V;
830 defm V#NAME#PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
831 !strconcat(OpcodeStr, "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
832 "", "_ps", f128mem, memopv4f32, SSEPackedSingle>, VEX_4V;
834 defm V#NAME#PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
835 !strconcat(OpcodeStr, "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
836 "2", "_pd", f128mem, memopv2f64, SSEPackedDouble>, OpSize,
840 let Constraints = "$src1 = $dst" in {
841 // Scalar operation, reg+reg.
842 defm SS : sse12_fp_scalar<opc,
843 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
844 OpNode, FR32, f32mem>, XS;
845 defm SD : sse12_fp_scalar<opc,
846 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
847 OpNode, FR64, f64mem>, XD;
848 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
849 "ps\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v4f32,
850 f128mem, memopv4f32, SSEPackedSingle>, TB;
852 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
853 "pd\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v2f64,
854 f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
856 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
857 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
858 "", "_ss", ssmem, sse_load_f32>, XS;
860 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
861 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
862 "2", "_sd", sdmem, sse_load_f64>, XD;
864 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
865 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
866 "", "_ps", f128mem, memopv4f32, SSEPackedSingle>, TB;
868 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
869 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
870 "2", "_pd", f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
874 let isCommutable = 0 in {
875 defm MAX : sse12_fp_binop_rm<0x5F, "max", X86fmax>;
876 defm MIN : sse12_fp_binop_rm<0x5D, "min", X86fmin>;
879 //===----------------------------------------------------------------------===//
880 // SSE packed FP Instructions
883 let neverHasSideEffects = 1 in
884 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
885 "movaps\t{$src, $dst|$dst, $src}", []>;
886 let canFoldAsLoad = 1, isReMaterializable = 1 in
887 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
888 "movaps\t{$src, $dst|$dst, $src}",
889 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
891 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
892 "movaps\t{$src, $dst|$dst, $src}",
893 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
895 let neverHasSideEffects = 1 in
896 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
897 "movups\t{$src, $dst|$dst, $src}", []>;
898 let canFoldAsLoad = 1, isReMaterializable = 1 in
899 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
900 "movups\t{$src, $dst|$dst, $src}",
901 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
902 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
903 "movups\t{$src, $dst|$dst, $src}",
904 [(store (v4f32 VR128:$src), addr:$dst)]>;
906 // Intrinsic forms of MOVUPS load and store
907 let canFoldAsLoad = 1, isReMaterializable = 1 in
908 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
909 "movups\t{$src, $dst|$dst, $src}",
910 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
911 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
912 "movups\t{$src, $dst|$dst, $src}",
913 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
915 let Constraints = "$src1 = $dst" in {
916 let AddedComplexity = 20 in {
917 def MOVLPSrm : PSI<0x12, MRMSrcMem,
918 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
919 "movlps\t{$src2, $dst|$dst, $src2}",
922 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
923 def MOVHPSrm : PSI<0x16, MRMSrcMem,
924 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
925 "movhps\t{$src2, $dst|$dst, $src2}",
927 (movlhps VR128:$src1,
928 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
930 } // Constraints = "$src1 = $dst"
933 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
934 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
936 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
937 "movlps\t{$src, $dst|$dst, $src}",
938 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
939 (iPTR 0))), addr:$dst)]>;
941 // v2f64 extract element 1 is always custom lowered to unpack high to low
942 // and extract element 0 so the non-store version isn't too horrible.
943 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
944 "movhps\t{$src, $dst|$dst, $src}",
945 [(store (f64 (vector_extract
946 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
947 (undef)), (iPTR 0))), addr:$dst)]>;
949 let Constraints = "$src1 = $dst" in {
950 let AddedComplexity = 20 in {
951 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
952 (ins VR128:$src1, VR128:$src2),
953 "movlhps\t{$src2, $dst|$dst, $src2}",
955 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
957 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
958 (ins VR128:$src1, VR128:$src2),
959 "movhlps\t{$src2, $dst|$dst, $src2}",
961 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
963 } // Constraints = "$src1 = $dst"
965 let AddedComplexity = 20 in {
966 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
967 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
968 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
969 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
976 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
978 /// In addition, we also have a special variant of the scalar form here to
979 /// represent the associated intrinsic operation. This form is unlike the
980 /// plain scalar form, in that it takes an entire vector (instead of a
981 /// scalar) and leaves the top elements undefined.
983 /// And, we have a special variant form for a full-vector intrinsic form.
985 /// These four forms can each have a reg or a mem operand, so there are a
986 /// total of eight "instructions".
988 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
992 bit Commutable = 0> {
993 // Scalar operation, reg.
994 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
995 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
996 [(set FR32:$dst, (OpNode FR32:$src))]> {
997 let isCommutable = Commutable;
1000 // Scalar operation, mem.
1001 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1002 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1003 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1004 Requires<[HasSSE1, OptForSize]>;
1006 // Vector operation, reg.
1007 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1008 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1009 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
1010 let isCommutable = Commutable;
1013 // Vector operation, mem.
1014 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1015 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1016 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1018 // Intrinsic operation, reg.
1019 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1020 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1021 [(set VR128:$dst, (F32Int VR128:$src))]> {
1022 let isCommutable = Commutable;
1025 // Intrinsic operation, mem.
1026 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1027 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1028 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1030 // Vector intrinsic operation, reg
1031 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1032 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1033 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
1034 let isCommutable = Commutable;
1037 // Vector intrinsic operation, mem
1038 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1039 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1040 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1044 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
1045 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
1047 // Reciprocal approximations. Note that these typically require refinement
1048 // in order to obtain suitable precision.
1049 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
1050 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
1051 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
1052 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
1054 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
1056 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
1057 SDNode OpNode, int HasPat = 0,
1058 list<list<dag>> Pattern = []> {
1059 let isAsmParserOnly = 1 in {
1060 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1061 !strconcat(OpcodeStr, "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1063 !if(HasPat, Pattern[0], // rr
1064 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1066 !if(HasPat, Pattern[2], // rm
1067 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1068 (memopv2i64 addr:$src2)))])>,
1071 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1072 !strconcat(OpcodeStr, "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1074 !if(HasPat, Pattern[1], // rr
1075 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1078 !if(HasPat, Pattern[3], // rm
1079 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1080 (memopv2i64 addr:$src2)))])>,
1083 let Constraints = "$src1 = $dst" in {
1084 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1085 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"), f128mem,
1086 !if(HasPat, Pattern[0], // rr
1087 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1089 !if(HasPat, Pattern[2], // rm
1090 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1091 (memopv2i64 addr:$src2)))])>, TB;
1093 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1094 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"), f128mem,
1095 !if(HasPat, Pattern[1], // rr
1096 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1099 !if(HasPat, Pattern[3], // rm
1100 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1101 (memopv2i64 addr:$src2)))])>,
1107 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
1108 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
1109 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
1110 let isCommutable = 0 in
1111 defm ANDN : sse12_fp_packed_logical<0x55, "andn", undef /* dummy */, 1, [
1113 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1114 (bc_v2i64 (v4i32 immAllOnesV))),
1117 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1118 (bc_v2i64 (v2f64 VR128:$src2))))],
1120 [(set VR128:$dst, (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
1121 (bc_v2i64 (v4i32 immAllOnesV))),
1122 (memopv2i64 addr:$src2))))],
1124 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1125 (memopv2i64 addr:$src2)))]]>;
1127 let Constraints = "$src1 = $dst" in {
1128 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
1129 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1130 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1131 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1132 VR128:$src, imm:$cc))]>;
1133 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
1134 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1135 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1136 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1137 (memop addr:$src), imm:$cc))]>;
1138 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1139 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1140 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1141 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1142 VR128:$src, imm:$cc))]>;
1143 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1144 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1145 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1146 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1147 (memop addr:$src), imm:$cc))]>;
1149 // Accept explicit immediate argument form instead of comparison code.
1150 let isAsmParserOnly = 1 in {
1151 def CMPPSrri_alt : PSIi8<0xC2, MRMSrcReg,
1152 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, i8imm:$src2),
1153 "cmpps\t{$src2, $src, $dst|$dst, $src, $src}", []>;
1154 def CMPPSrmi_alt : PSIi8<0xC2, MRMSrcMem,
1155 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, i8imm:$src2),
1156 "cmpps\t{$src2, $src, $dst|$dst, $src, $src}", []>;
1157 def CMPPDrri_alt : PDIi8<0xC2, MRMSrcReg,
1158 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, i8imm:$src2),
1159 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
1160 def CMPPDrmi_alt : PDIi8<0xC2, MRMSrcMem,
1161 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, i8imm:$src2),
1162 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
1165 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1166 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1167 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1168 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1169 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1170 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1171 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1172 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1174 // Shuffle and unpack instructions
1175 let Constraints = "$src1 = $dst" in {
1176 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
1177 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
1178 (outs VR128:$dst), (ins VR128:$src1,
1179 VR128:$src2, i8imm:$src3),
1180 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1182 (v4f32 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1183 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
1184 (outs VR128:$dst), (ins VR128:$src1,
1185 f128mem:$src2, i8imm:$src3),
1186 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1189 VR128:$src1, (memopv4f32 addr:$src2))))]>;
1190 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1191 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1192 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1194 (v2f64 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1195 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1196 (outs VR128:$dst), (ins VR128:$src1,
1197 f128mem:$src2, i8imm:$src3),
1198 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1201 VR128:$src1, (memopv2f64 addr:$src2))))]>;
1203 let AddedComplexity = 10 in {
1204 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1205 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1206 "unpckhps\t{$src2, $dst|$dst, $src2}",
1208 (v4f32 (unpckh VR128:$src1, VR128:$src2)))]>;
1209 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1210 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1211 "unpckhps\t{$src2, $dst|$dst, $src2}",
1213 (v4f32 (unpckh VR128:$src1,
1214 (memopv4f32 addr:$src2))))]>;
1216 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1217 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1218 "unpcklps\t{$src2, $dst|$dst, $src2}",
1220 (v4f32 (unpckl VR128:$src1, VR128:$src2)))]>;
1221 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1222 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1223 "unpcklps\t{$src2, $dst|$dst, $src2}",
1225 (unpckl VR128:$src1, (memopv4f32 addr:$src2)))]>;
1226 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1227 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1228 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1230 (v2f64 (unpckh VR128:$src1, VR128:$src2)))]>;
1231 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1232 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1233 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1235 (v2f64 (unpckh VR128:$src1,
1236 (memopv2f64 addr:$src2))))]>;
1238 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1239 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1240 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1242 (v2f64 (unpckl VR128:$src1, VR128:$src2)))]>;
1243 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1244 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1245 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1247 (unpckl VR128:$src1, (memopv2f64 addr:$src2)))]>;
1248 } // AddedComplexity
1249 } // Constraints = "$src1 = $dst"
1252 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1253 "movmskps\t{$src, $dst|$dst, $src}",
1254 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
1255 def MOVMSKPDrr : PDI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1256 "movmskpd\t{$src, $dst|$dst, $src}",
1257 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
1259 // Prefetch intrinsic.
1260 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
1261 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
1262 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
1263 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
1264 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
1265 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
1266 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
1267 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
1269 // Non-temporal stores
1270 def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1271 "movntps\t{$src, $dst|$dst, $src}",
1272 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
1274 let AddedComplexity = 400 in { // Prefer non-temporal versions
1275 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1276 "movntps\t{$src, $dst|$dst, $src}",
1277 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1279 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1280 "movntdq\t{$src, $dst|$dst, $src}",
1281 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
1283 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1284 "movnti\t{$src, $dst|$dst, $src}",
1285 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
1286 TB, Requires<[HasSSE2]>;
1288 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1289 "movnti\t{$src, $dst|$dst, $src}",
1290 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
1291 TB, Requires<[HasSSE2]>;
1294 // Load, store, and memory fence
1295 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
1296 TB, Requires<[HasSSE1]>;
1299 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
1300 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
1301 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
1302 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
1304 // Alias instructions that map zero vector to pxor / xorp* for sse.
1305 // We set canFoldAsLoad because this can be converted to a constant-pool
1306 // load of an all-zeros value if folding it would be beneficial.
1307 // FIXME: Change encoding to pseudo!
1308 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
1309 isCodeGenOnly = 1 in {
1310 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1311 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
1312 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1313 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
1314 let ExeDomain = SSEPackedInt in
1315 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
1316 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
1319 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
1320 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
1321 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
1323 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1324 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1326 //===---------------------------------------------------------------------===//
1327 // SSE2 Instructions
1328 //===---------------------------------------------------------------------===//
1330 // Move Instructions. Register-to-register movsd is not used for FR64
1331 // register copies because it's a partial register update; FsMOVAPDrr is
1332 // used instead. Register-to-register movsd is not modeled as an INSERT_SUBREG
1333 // because INSERT_SUBREG requires that the insert be implementable in terms of
1334 // a copy, and just mentioned, we don't use movsd for copies.
1335 let Constraints = "$src1 = $dst" in
1336 def MOVSDrr : SDI<0x10, MRMSrcReg,
1337 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
1338 "movsd\t{$src2, $dst|$dst, $src2}",
1339 [(set (v2f64 VR128:$dst),
1340 (movl VR128:$src1, (scalar_to_vector FR64:$src2)))]>;
1342 // Extract the low 64-bit value from one vector and insert it into another.
1343 let AddedComplexity = 15 in
1344 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
1345 (MOVSDrr (v2f64 VR128:$src1),
1346 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
1348 // Implicitly promote a 64-bit scalar to a vector.
1349 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
1350 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
1352 // Loading from memory automatically zeroing upper bits.
1353 let canFoldAsLoad = 1, isReMaterializable = 1, AddedComplexity = 20 in
1354 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1355 "movsd\t{$src, $dst|$dst, $src}",
1356 [(set FR64:$dst, (loadf64 addr:$src))]>;
1358 // MOVSDrm zeros the high parts of the register; represent this
1359 // with SUBREG_TO_REG.
1360 let AddedComplexity = 20 in {
1361 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1362 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1363 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1364 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1365 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1366 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1367 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1368 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1369 def : Pat<(v2f64 (X86vzload addr:$src)),
1370 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1373 // Store scalar value to memory.
1374 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1375 "movsd\t{$src, $dst|$dst, $src}",
1376 [(store FR64:$src, addr:$dst)]>;
1378 // Extract and store.
1379 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
1382 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
1384 // Conversion instructions
1385 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1386 "cvttsd2si\t{$src, $dst|$dst, $src}",
1387 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1388 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1389 "cvttsd2si\t{$src, $dst|$dst, $src}",
1390 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1391 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1392 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1393 [(set FR32:$dst, (fround FR64:$src))]>;
1394 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1395 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1396 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1397 Requires<[HasSSE2, OptForSize]>;
1398 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1399 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1400 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1401 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1402 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1403 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1405 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1406 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1407 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1408 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1409 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1410 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1411 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1412 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1413 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1414 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1415 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1416 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1417 def CVTDQ2PSrr : PSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1418 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1419 def CVTDQ2PSrm : PSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1420 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1421 def COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1422 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1423 def COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1424 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1426 // SSE2 instructions with XS prefix
1427 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1428 "cvtss2sd\t{$src, $dst|$dst, $src}",
1429 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1430 Requires<[HasSSE2]>;
1431 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1432 "cvtss2sd\t{$src, $dst|$dst, $src}",
1433 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1434 Requires<[HasSSE2, OptForSize]>;
1436 def : Pat<(extloadf32 addr:$src),
1437 (CVTSS2SDrr (MOVSSrm addr:$src))>,
1438 Requires<[HasSSE2, OptForSpeed]>;
1440 // Match intrinsics which expect XMM operand(s).
1441 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1442 "cvtsd2si\t{$src, $dst|$dst, $src}",
1443 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1444 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1445 "cvtsd2si\t{$src, $dst|$dst, $src}",
1446 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1447 (load addr:$src)))]>;
1449 // Match intrinsics which expect MM and XMM operand(s).
1450 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1451 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1452 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1453 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1454 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1455 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1456 (memop addr:$src)))]>;
1457 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1458 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1459 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1460 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1461 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1462 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1463 (memop addr:$src)))]>;
1464 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1465 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1466 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1467 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1468 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1469 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1470 (load addr:$src)))]>;
1472 // Aliases for intrinsics
1473 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1474 "cvttsd2si\t{$src, $dst|$dst, $src}",
1476 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1477 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1478 "cvttsd2si\t{$src, $dst|$dst, $src}",
1479 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1480 (load addr:$src)))]>;
1482 // Comparison instructions
1483 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1484 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1485 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1486 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1488 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1489 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1490 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1492 // Accept explicit immediate argument form instead of comparison code.
1493 let isAsmParserOnly = 1 in {
1494 def CMPSDrr_alt : SDIi8<0xC2, MRMSrcReg,
1495 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
1496 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
1498 def CMPSDrm_alt : SDIi8<0xC2, MRMSrcMem,
1499 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
1500 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
1504 let Defs = [EFLAGS] in {
1505 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1506 "ucomisd\t{$src2, $src1|$src1, $src2}",
1507 [(set EFLAGS, (X86cmp FR64:$src1, FR64:$src2))]>;
1508 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1509 "ucomisd\t{$src2, $src1|$src1, $src2}",
1510 [(set EFLAGS, (X86cmp FR64:$src1, (loadf64 addr:$src2)))]>;
1511 } // Defs = [EFLAGS]
1513 // Aliases to match intrinsics which expect XMM operand(s).
1514 let Constraints = "$src1 = $dst" in {
1515 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1517 (ins VR128:$src1, VR128:$src, SSECC:$cc),
1518 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1519 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1520 VR128:$src, imm:$cc))]>;
1521 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1523 (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1524 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1525 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1526 (load addr:$src), imm:$cc))]>;
1529 let Defs = [EFLAGS] in {
1530 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1531 "ucomisd\t{$src2, $src1|$src1, $src2}",
1532 [(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
1534 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1535 "ucomisd\t{$src2, $src1|$src1, $src2}",
1536 [(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
1537 (load addr:$src2)))]>;
1539 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1540 "comisd\t{$src2, $src1|$src1, $src2}",
1541 [(set EFLAGS, (X86comi (v2f64 VR128:$src1),
1543 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1544 "comisd\t{$src2, $src1|$src1, $src2}",
1545 [(set EFLAGS, (X86comi (v2f64 VR128:$src1),
1546 (load addr:$src2)))]>;
1547 } // Defs = [EFLAGS]
1549 // Aliases of packed SSE2 instructions for scalar use. These all have names
1550 // that start with 'Fs'.
1552 // Alias instructions that map fld0 to pxor for sse.
1553 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1554 canFoldAsLoad = 1 in
1555 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1556 [(set FR64:$dst, fpimm0)]>,
1557 Requires<[HasSSE2]>, TB, OpSize;
1559 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1561 let neverHasSideEffects = 1 in
1562 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1563 "movapd\t{$src, $dst|$dst, $src}", []>;
1565 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1567 let canFoldAsLoad = 1, isReMaterializable = 1 in
1568 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1569 "movapd\t{$src, $dst|$dst, $src}",
1570 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1572 //===---------------------------------------------------------------------===//
1573 // SSE packed FP Instructions
1575 // Move Instructions
1576 let neverHasSideEffects = 1 in
1577 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1578 "movapd\t{$src, $dst|$dst, $src}", []>;
1579 let canFoldAsLoad = 1, isReMaterializable = 1 in
1580 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1581 "movapd\t{$src, $dst|$dst, $src}",
1582 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1584 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1585 "movapd\t{$src, $dst|$dst, $src}",
1586 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1588 let neverHasSideEffects = 1 in
1589 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1590 "movupd\t{$src, $dst|$dst, $src}", []>;
1591 let canFoldAsLoad = 1 in
1592 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1593 "movupd\t{$src, $dst|$dst, $src}",
1594 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1595 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1596 "movupd\t{$src, $dst|$dst, $src}",
1597 [(store (v2f64 VR128:$src), addr:$dst)]>;
1599 // Intrinsic forms of MOVUPD load and store
1600 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1601 "movupd\t{$src, $dst|$dst, $src}",
1602 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1603 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1604 "movupd\t{$src, $dst|$dst, $src}",
1605 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1607 let Constraints = "$src1 = $dst" in {
1608 let AddedComplexity = 20 in {
1609 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1610 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1611 "movlpd\t{$src2, $dst|$dst, $src2}",
1613 (v2f64 (movlp VR128:$src1,
1614 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1615 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1616 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1617 "movhpd\t{$src2, $dst|$dst, $src2}",
1619 (v2f64 (movlhps VR128:$src1,
1620 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1621 } // AddedComplexity
1622 } // Constraints = "$src1 = $dst"
1624 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1625 "movlpd\t{$src, $dst|$dst, $src}",
1626 [(store (f64 (vector_extract (v2f64 VR128:$src),
1627 (iPTR 0))), addr:$dst)]>;
1629 // v2f64 extract element 1 is always custom lowered to unpack high to low
1630 // and extract element 0 so the non-store version isn't too horrible.
1631 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1632 "movhpd\t{$src, $dst|$dst, $src}",
1633 [(store (f64 (vector_extract
1634 (v2f64 (unpckh VR128:$src, (undef))),
1635 (iPTR 0))), addr:$dst)]>;
1637 // SSE2 instructions without OpSize prefix
1638 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1639 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1640 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1641 TB, Requires<[HasSSE2]>;
1642 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1643 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1644 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1645 (bitconvert (memopv2i64 addr:$src))))]>,
1646 TB, Requires<[HasSSE2]>;
1648 // SSE2 instructions with XS prefix
1649 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1650 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1651 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1652 XS, Requires<[HasSSE2]>;
1653 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1654 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1655 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1656 (bitconvert (memopv2i64 addr:$src))))]>,
1657 XS, Requires<[HasSSE2]>;
1659 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1660 "cvtps2dq\t{$src, $dst|$dst, $src}",
1661 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1662 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1663 "cvtps2dq\t{$src, $dst|$dst, $src}",
1664 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1665 (memop addr:$src)))]>;
1666 // SSE2 packed instructions with XS prefix
1667 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1668 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1669 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1670 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1672 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1673 "cvttps2dq\t{$src, $dst|$dst, $src}",
1675 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1676 XS, Requires<[HasSSE2]>;
1677 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1678 "cvttps2dq\t{$src, $dst|$dst, $src}",
1679 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1680 (memop addr:$src)))]>,
1681 XS, Requires<[HasSSE2]>;
1683 // SSE2 packed instructions with XD prefix
1684 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1685 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1686 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1687 XD, Requires<[HasSSE2]>;
1688 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1689 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1690 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1691 (memop addr:$src)))]>,
1692 XD, Requires<[HasSSE2]>;
1694 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1695 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1696 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1697 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1698 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1699 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1700 (memop addr:$src)))]>;
1702 // SSE2 instructions without OpSize prefix
1703 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1704 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1705 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1706 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1708 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1709 "cvtps2pd\t{$src, $dst|$dst, $src}",
1710 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1711 TB, Requires<[HasSSE2]>;
1712 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1713 "cvtps2pd\t{$src, $dst|$dst, $src}",
1714 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1715 (load addr:$src)))]>,
1716 TB, Requires<[HasSSE2]>;
1718 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1719 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1720 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1721 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1724 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1725 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1726 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1727 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1728 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1729 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1730 (memop addr:$src)))]>;
1732 // Match intrinsics which expect XMM operand(s).
1733 // Aliases for intrinsics
1734 let Constraints = "$src1 = $dst" in {
1735 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1736 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1737 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1738 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1740 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1741 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1742 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1743 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1744 (loadi32 addr:$src2)))]>;
1745 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1746 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1747 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1748 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1750 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1751 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1752 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1753 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1754 (load addr:$src2)))]>;
1755 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1756 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1757 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1758 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1759 VR128:$src2))]>, XS,
1760 Requires<[HasSSE2]>;
1761 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1762 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1763 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1764 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1765 (load addr:$src2)))]>, XS,
1766 Requires<[HasSSE2]>;
1771 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1773 /// In addition, we also have a special variant of the scalar form here to
1774 /// represent the associated intrinsic operation. This form is unlike the
1775 /// plain scalar form, in that it takes an entire vector (instead of a
1776 /// scalar) and leaves the top elements undefined.
1778 /// And, we have a special variant form for a full-vector intrinsic form.
1780 /// These four forms can each have a reg or a mem operand, so there are a
1781 /// total of eight "instructions".
1783 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1787 bit Commutable = 0> {
1788 // Scalar operation, reg.
1789 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1790 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1791 [(set FR64:$dst, (OpNode FR64:$src))]> {
1792 let isCommutable = Commutable;
1795 // Scalar operation, mem.
1796 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1797 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1798 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1800 // Vector operation, reg.
1801 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1802 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1803 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1804 let isCommutable = Commutable;
1807 // Vector operation, mem.
1808 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1809 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1810 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1812 // Intrinsic operation, reg.
1813 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1814 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1815 [(set VR128:$dst, (F64Int VR128:$src))]> {
1816 let isCommutable = Commutable;
1819 // Intrinsic operation, mem.
1820 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1821 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1822 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1824 // Vector intrinsic operation, reg
1825 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1826 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1827 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1828 let isCommutable = Commutable;
1831 // Vector intrinsic operation, mem
1832 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1833 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1834 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1838 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1839 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1841 // There is no f64 version of the reciprocal approximation instructions.
1843 //===---------------------------------------------------------------------===//
1844 // SSE integer instructions
1845 let ExeDomain = SSEPackedInt in {
1847 // Move Instructions
1848 let neverHasSideEffects = 1 in
1849 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1850 "movdqa\t{$src, $dst|$dst, $src}", []>;
1851 let canFoldAsLoad = 1, mayLoad = 1 in
1852 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1853 "movdqa\t{$src, $dst|$dst, $src}",
1854 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1856 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1857 "movdqa\t{$src, $dst|$dst, $src}",
1858 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1859 let canFoldAsLoad = 1, mayLoad = 1 in
1860 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1861 "movdqu\t{$src, $dst|$dst, $src}",
1862 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1863 XS, Requires<[HasSSE2]>;
1865 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1866 "movdqu\t{$src, $dst|$dst, $src}",
1867 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1868 XS, Requires<[HasSSE2]>;
1870 // Intrinsic forms of MOVDQU load and store
1871 let canFoldAsLoad = 1 in
1872 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1873 "movdqu\t{$src, $dst|$dst, $src}",
1874 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1875 XS, Requires<[HasSSE2]>;
1876 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1877 "movdqu\t{$src, $dst|$dst, $src}",
1878 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1879 XS, Requires<[HasSSE2]>;
1881 let Constraints = "$src1 = $dst" in {
1883 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1884 bit Commutable = 0> {
1885 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1886 (ins VR128:$src1, VR128:$src2),
1887 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1888 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1889 let isCommutable = Commutable;
1891 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1892 (ins VR128:$src1, i128mem:$src2),
1893 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1894 [(set VR128:$dst, (IntId VR128:$src1,
1895 (bitconvert (memopv2i64
1899 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1901 Intrinsic IntId, Intrinsic IntId2> {
1902 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1903 (ins VR128:$src1, VR128:$src2),
1904 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1905 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1906 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1907 (ins VR128:$src1, i128mem:$src2),
1908 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1909 [(set VR128:$dst, (IntId VR128:$src1,
1910 (bitconvert (memopv2i64 addr:$src2))))]>;
1911 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
1912 (ins VR128:$src1, i32i8imm:$src2),
1913 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1914 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
1917 /// PDI_binop_rm - Simple SSE2 binary operator.
1918 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1919 ValueType OpVT, bit Commutable = 0> {
1920 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1921 (ins VR128:$src1, VR128:$src2),
1922 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1923 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1924 let isCommutable = Commutable;
1926 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1927 (ins VR128:$src1, i128mem:$src2),
1928 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1929 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1930 (bitconvert (memopv2i64 addr:$src2)))))]>;
1933 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1935 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1936 /// to collapse (bitconvert VT to VT) into its operand.
1938 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1939 bit Commutable = 0> {
1940 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1941 (ins VR128:$src1, VR128:$src2),
1942 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1943 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1944 let isCommutable = Commutable;
1946 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1947 (ins VR128:$src1, i128mem:$src2),
1948 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1949 [(set VR128:$dst, (OpNode VR128:$src1,
1950 (memopv2i64 addr:$src2)))]>;
1953 } // Constraints = "$src1 = $dst"
1954 } // ExeDomain = SSEPackedInt
1956 // 128-bit Integer Arithmetic
1958 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1959 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1960 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1961 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1963 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1964 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1965 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1966 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1968 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1969 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1970 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1971 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1973 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1974 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1975 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1976 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1978 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1980 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1981 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1982 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1984 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1986 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1987 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1990 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1991 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1992 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1993 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1994 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
1997 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
1998 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
1999 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2000 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2001 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2002 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2004 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2005 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2006 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2007 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2008 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2009 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2011 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2012 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2013 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2014 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2016 // 128-bit logical shifts.
2017 let Constraints = "$src1 = $dst", neverHasSideEffects = 1,
2018 ExeDomain = SSEPackedInt in {
2019 def PSLLDQri : PDIi8<0x73, MRM7r,
2020 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2021 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2022 def PSRLDQri : PDIi8<0x73, MRM3r,
2023 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2024 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2025 // PSRADQri doesn't exist in SSE[1-3].
2028 let Predicates = [HasSSE2] in {
2029 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2030 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2031 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2032 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2033 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2034 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2035 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2036 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2037 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2038 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2040 // Shift up / down and insert zero's.
2041 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2042 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2043 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2044 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2048 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2049 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
2050 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2052 let Constraints = "$src1 = $dst", ExeDomain = SSEPackedInt in {
2053 def PANDNrr : PDI<0xDF, MRMSrcReg,
2054 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2055 "pandn\t{$src2, $dst|$dst, $src2}",
2056 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2059 def PANDNrm : PDI<0xDF, MRMSrcMem,
2060 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2061 "pandn\t{$src2, $dst|$dst, $src2}",
2062 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2063 (memopv2i64 addr:$src2))))]>;
2066 // SSE2 Integer comparison
2067 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
2068 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
2069 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
2070 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2071 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2072 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2074 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2075 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2076 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2077 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2078 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2079 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2080 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2081 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2082 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2083 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2084 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2085 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2087 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2088 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2089 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2090 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2091 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2092 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2093 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2094 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2095 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2096 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2097 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2098 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2101 // Pack instructions
2102 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2103 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2104 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2106 let ExeDomain = SSEPackedInt in {
2108 // Shuffle and unpack instructions
2109 let AddedComplexity = 5 in {
2110 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2111 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2112 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2113 [(set VR128:$dst, (v4i32 (pshufd:$src2
2114 VR128:$src1, (undef))))]>;
2115 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2116 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2117 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2118 [(set VR128:$dst, (v4i32 (pshufd:$src2
2119 (bc_v4i32 (memopv2i64 addr:$src1)),
2123 // SSE2 with ImmT == Imm8 and XS prefix.
2124 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2125 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2126 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2127 [(set VR128:$dst, (v8i16 (pshufhw:$src2 VR128:$src1,
2129 XS, Requires<[HasSSE2]>;
2130 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2131 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2132 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2133 [(set VR128:$dst, (v8i16 (pshufhw:$src2
2134 (bc_v8i16 (memopv2i64 addr:$src1)),
2136 XS, Requires<[HasSSE2]>;
2138 // SSE2 with ImmT == Imm8 and XD prefix.
2139 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2140 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2141 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2142 [(set VR128:$dst, (v8i16 (pshuflw:$src2 VR128:$src1,
2144 XD, Requires<[HasSSE2]>;
2145 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2146 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2147 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2148 [(set VR128:$dst, (v8i16 (pshuflw:$src2
2149 (bc_v8i16 (memopv2i64 addr:$src1)),
2151 XD, Requires<[HasSSE2]>;
2153 // Unpack instructions
2154 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2155 PatFrag unp_frag, PatFrag bc_frag> {
2156 def rr : PDI<opc, MRMSrcReg,
2157 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2158 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2159 [(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
2160 def rm : PDI<opc, MRMSrcMem,
2161 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2162 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2163 [(set VR128:$dst, (unp_frag VR128:$src1,
2164 (bc_frag (memopv2i64
2168 let Constraints = "$src1 = $dst" in {
2169 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, unpckl, bc_v16i8>;
2170 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, unpckl, bc_v8i16>;
2171 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, unpckl, bc_v4i32>;
2173 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2174 /// knew to collapse (bitconvert VT to VT) into its operand.
2175 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2176 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2177 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2179 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2180 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2181 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2182 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2184 (v2i64 (unpckl VR128:$src1,
2185 (memopv2i64 addr:$src2))))]>;
2187 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, unpckh, bc_v16i8>;
2188 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, unpckh, bc_v8i16>;
2189 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, unpckh, bc_v4i32>;
2191 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2192 /// knew to collapse (bitconvert VT to VT) into its operand.
2193 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2194 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2195 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2197 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2198 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2199 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2200 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2202 (v2i64 (unpckh VR128:$src1,
2203 (memopv2i64 addr:$src2))))]>;
2207 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2208 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2209 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2210 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2212 let Constraints = "$src1 = $dst" in {
2213 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2214 (outs VR128:$dst), (ins VR128:$src1,
2215 GR32:$src2, i32i8imm:$src3),
2216 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2218 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2219 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2220 (outs VR128:$dst), (ins VR128:$src1,
2221 i16mem:$src2, i32i8imm:$src3),
2222 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2224 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2229 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2230 "pmovmskb\t{$src, $dst|$dst, $src}",
2231 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2233 // Conditional store
2235 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2236 "maskmovdqu\t{$mask, $src|$src, $mask}",
2237 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2240 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2241 "maskmovdqu\t{$mask, $src|$src, $mask}",
2242 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2244 } // ExeDomain = SSEPackedInt
2246 // Non-temporal stores
2247 def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2248 "movntpd\t{$src, $dst|$dst, $src}",
2249 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2250 let ExeDomain = SSEPackedInt in
2251 def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2252 "movntdq\t{$src, $dst|$dst, $src}",
2253 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2254 def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2255 "movnti\t{$src, $dst|$dst, $src}",
2256 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2257 TB, Requires<[HasSSE2]>;
2259 let AddedComplexity = 400 in { // Prefer non-temporal versions
2260 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2261 "movntpd\t{$src, $dst|$dst, $src}",
2262 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2264 let ExeDomain = SSEPackedInt in
2265 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2266 "movntdq\t{$src, $dst|$dst, $src}",
2267 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2271 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2272 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2273 TB, Requires<[HasSSE2]>;
2275 // Load, store, and memory fence
2276 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
2277 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2278 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
2279 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2281 // Pause. This "instruction" is encoded as "rep; nop", so even though it
2282 // was introduced with SSE2, it's backward compatible.
2283 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
2285 //TODO: custom lower this so as to never even generate the noop
2286 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2288 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2289 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2290 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2293 // Alias instructions that map zero vector to pxor / xorp* for sse.
2294 // We set canFoldAsLoad because this can be converted to a constant-pool
2295 // load of an all-ones value if folding it would be beneficial.
2296 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2297 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
2298 // FIXME: Change encoding to pseudo.
2299 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
2300 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2302 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2303 "movd\t{$src, $dst|$dst, $src}",
2305 (v4i32 (scalar_to_vector GR32:$src)))]>;
2306 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2307 "movd\t{$src, $dst|$dst, $src}",
2309 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2311 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2312 "movd\t{$src, $dst|$dst, $src}",
2313 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2315 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2316 "movd\t{$src, $dst|$dst, $src}",
2317 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2319 // SSE2 instructions with XS prefix
2320 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2321 "movq\t{$src, $dst|$dst, $src}",
2323 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2324 Requires<[HasSSE2]>;
2325 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2326 "movq\t{$src, $dst|$dst, $src}",
2327 [(store (i64 (vector_extract (v2i64 VR128:$src),
2328 (iPTR 0))), addr:$dst)]>;
2330 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
2331 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
2333 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2334 "movd\t{$src, $dst|$dst, $src}",
2335 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2337 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2338 "movd\t{$src, $dst|$dst, $src}",
2339 [(store (i32 (vector_extract (v4i32 VR128:$src),
2340 (iPTR 0))), addr:$dst)]>;
2342 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2343 "movd\t{$src, $dst|$dst, $src}",
2344 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2345 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2346 "movd\t{$src, $dst|$dst, $src}",
2347 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2349 // Store / copy lower 64-bits of a XMM register.
2350 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2351 "movq\t{$src, $dst|$dst, $src}",
2352 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2354 // movd / movq to XMM register zero-extends
2355 let AddedComplexity = 15 in {
2356 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2357 "movd\t{$src, $dst|$dst, $src}",
2358 [(set VR128:$dst, (v4i32 (X86vzmovl
2359 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2360 // This is X86-64 only.
2361 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2362 "mov{d|q}\t{$src, $dst|$dst, $src}",
2363 [(set VR128:$dst, (v2i64 (X86vzmovl
2364 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2367 let AddedComplexity = 20 in {
2368 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2369 "movd\t{$src, $dst|$dst, $src}",
2371 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2372 (loadi32 addr:$src))))))]>;
2374 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2375 (MOVZDI2PDIrm addr:$src)>;
2376 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2377 (MOVZDI2PDIrm addr:$src)>;
2378 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2379 (MOVZDI2PDIrm addr:$src)>;
2381 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2382 "movq\t{$src, $dst|$dst, $src}",
2384 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2385 (loadi64 addr:$src))))))]>, XS,
2386 Requires<[HasSSE2]>;
2388 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2389 (MOVZQI2PQIrm addr:$src)>;
2390 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2391 (MOVZQI2PQIrm addr:$src)>;
2392 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2395 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2396 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2397 let AddedComplexity = 15 in
2398 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2399 "movq\t{$src, $dst|$dst, $src}",
2400 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2401 XS, Requires<[HasSSE2]>;
2403 let AddedComplexity = 20 in {
2404 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2405 "movq\t{$src, $dst|$dst, $src}",
2406 [(set VR128:$dst, (v2i64 (X86vzmovl
2407 (loadv2i64 addr:$src))))]>,
2408 XS, Requires<[HasSSE2]>;
2410 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2411 (MOVZPQILo2PQIrm addr:$src)>;
2414 // Instructions for the disassembler
2415 // xr = XMM register
2418 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2419 "movq\t{$src, $dst|$dst, $src}", []>, XS;
2421 //===---------------------------------------------------------------------===//
2422 // SSE3 Instructions
2423 //===---------------------------------------------------------------------===//
2425 // Move Instructions
2426 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2427 "movshdup\t{$src, $dst|$dst, $src}",
2428 [(set VR128:$dst, (v4f32 (movshdup
2429 VR128:$src, (undef))))]>;
2430 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2431 "movshdup\t{$src, $dst|$dst, $src}",
2432 [(set VR128:$dst, (movshdup
2433 (memopv4f32 addr:$src), (undef)))]>;
2435 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2436 "movsldup\t{$src, $dst|$dst, $src}",
2437 [(set VR128:$dst, (v4f32 (movsldup
2438 VR128:$src, (undef))))]>;
2439 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2440 "movsldup\t{$src, $dst|$dst, $src}",
2441 [(set VR128:$dst, (movsldup
2442 (memopv4f32 addr:$src), (undef)))]>;
2444 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2445 "movddup\t{$src, $dst|$dst, $src}",
2446 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
2447 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2448 "movddup\t{$src, $dst|$dst, $src}",
2450 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
2453 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
2455 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2457 let AddedComplexity = 5 in {
2458 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
2459 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2460 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
2461 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2462 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
2463 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2464 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
2465 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2469 let Constraints = "$src1 = $dst" in {
2470 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2471 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2472 "addsubps\t{$src2, $dst|$dst, $src2}",
2473 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2475 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2476 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2477 "addsubps\t{$src2, $dst|$dst, $src2}",
2478 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2479 (memop addr:$src2)))]>;
2480 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2481 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2482 "addsubpd\t{$src2, $dst|$dst, $src2}",
2483 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2485 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2486 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2487 "addsubpd\t{$src2, $dst|$dst, $src2}",
2488 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2489 (memop addr:$src2)))]>;
2492 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2493 "lddqu\t{$src, $dst|$dst, $src}",
2494 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2497 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2498 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2499 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2500 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2501 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2502 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2503 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2504 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2505 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2506 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2507 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2508 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2509 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2510 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2511 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2512 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2514 let Constraints = "$src1 = $dst" in {
2515 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2516 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2517 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2518 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2519 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2520 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2521 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2522 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2525 // Thread synchronization
2526 def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
2527 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2528 def MWAIT : I<0x01, MRM_C9, (outs), (ins), "mwait",
2529 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2531 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2532 let AddedComplexity = 15 in
2533 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
2534 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2535 let AddedComplexity = 20 in
2536 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2537 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2539 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2540 let AddedComplexity = 15 in
2541 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
2542 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2543 let AddedComplexity = 20 in
2544 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2545 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2547 //===---------------------------------------------------------------------===//
2548 // SSSE3 Instructions
2549 //===---------------------------------------------------------------------===//
2551 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2552 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2553 Intrinsic IntId64, Intrinsic IntId128> {
2554 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2555 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2556 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2558 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2559 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2561 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2563 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2565 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2566 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2569 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2571 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2574 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2577 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2578 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2579 Intrinsic IntId64, Intrinsic IntId128> {
2580 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2582 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2583 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2585 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2587 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2590 (bitconvert (memopv4i16 addr:$src))))]>;
2592 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2595 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2598 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2600 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2603 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2606 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2607 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2608 Intrinsic IntId64, Intrinsic IntId128> {
2609 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2611 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2612 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2614 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2616 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2619 (bitconvert (memopv2i32 addr:$src))))]>;
2621 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2623 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2624 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2627 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2629 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2632 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2635 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2636 int_x86_ssse3_pabs_b,
2637 int_x86_ssse3_pabs_b_128>;
2638 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2639 int_x86_ssse3_pabs_w,
2640 int_x86_ssse3_pabs_w_128>;
2641 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2642 int_x86_ssse3_pabs_d,
2643 int_x86_ssse3_pabs_d_128>;
2645 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2646 let Constraints = "$src1 = $dst" in {
2647 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2648 Intrinsic IntId64, Intrinsic IntId128,
2649 bit Commutable = 0> {
2650 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2651 (ins VR64:$src1, VR64:$src2),
2652 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2653 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2654 let isCommutable = Commutable;
2656 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2657 (ins VR64:$src1, i64mem:$src2),
2658 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2660 (IntId64 VR64:$src1,
2661 (bitconvert (memopv8i8 addr:$src2))))]>;
2663 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2664 (ins VR128:$src1, VR128:$src2),
2665 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2666 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2668 let isCommutable = Commutable;
2670 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2671 (ins VR128:$src1, i128mem:$src2),
2672 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2674 (IntId128 VR128:$src1,
2675 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2679 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2680 let Constraints = "$src1 = $dst" in {
2681 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2682 Intrinsic IntId64, Intrinsic IntId128,
2683 bit Commutable = 0> {
2684 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2685 (ins VR64:$src1, VR64:$src2),
2686 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2687 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2688 let isCommutable = Commutable;
2690 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2691 (ins VR64:$src1, i64mem:$src2),
2692 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2694 (IntId64 VR64:$src1,
2695 (bitconvert (memopv4i16 addr:$src2))))]>;
2697 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2698 (ins VR128:$src1, VR128:$src2),
2699 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2700 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2702 let isCommutable = Commutable;
2704 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2705 (ins VR128:$src1, i128mem:$src2),
2706 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2708 (IntId128 VR128:$src1,
2709 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2713 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2714 let Constraints = "$src1 = $dst" in {
2715 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2716 Intrinsic IntId64, Intrinsic IntId128,
2717 bit Commutable = 0> {
2718 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2719 (ins VR64:$src1, VR64:$src2),
2720 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2721 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2722 let isCommutable = Commutable;
2724 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2725 (ins VR64:$src1, i64mem:$src2),
2726 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2728 (IntId64 VR64:$src1,
2729 (bitconvert (memopv2i32 addr:$src2))))]>;
2731 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2732 (ins VR128:$src1, VR128:$src2),
2733 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2734 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2736 let isCommutable = Commutable;
2738 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2739 (ins VR128:$src1, i128mem:$src2),
2740 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2742 (IntId128 VR128:$src1,
2743 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2747 let ImmT = NoImm in { // None of these have i8 immediate fields.
2748 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2749 int_x86_ssse3_phadd_w,
2750 int_x86_ssse3_phadd_w_128>;
2751 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2752 int_x86_ssse3_phadd_d,
2753 int_x86_ssse3_phadd_d_128>;
2754 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2755 int_x86_ssse3_phadd_sw,
2756 int_x86_ssse3_phadd_sw_128>;
2757 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2758 int_x86_ssse3_phsub_w,
2759 int_x86_ssse3_phsub_w_128>;
2760 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2761 int_x86_ssse3_phsub_d,
2762 int_x86_ssse3_phsub_d_128>;
2763 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2764 int_x86_ssse3_phsub_sw,
2765 int_x86_ssse3_phsub_sw_128>;
2766 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2767 int_x86_ssse3_pmadd_ub_sw,
2768 int_x86_ssse3_pmadd_ub_sw_128>;
2769 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2770 int_x86_ssse3_pmul_hr_sw,
2771 int_x86_ssse3_pmul_hr_sw_128, 1>;
2773 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2774 int_x86_ssse3_pshuf_b,
2775 int_x86_ssse3_pshuf_b_128>;
2776 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2777 int_x86_ssse3_psign_b,
2778 int_x86_ssse3_psign_b_128>;
2779 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2780 int_x86_ssse3_psign_w,
2781 int_x86_ssse3_psign_w_128>;
2782 defm PSIGND : SS3I_binop_rm_int_32<0x0A, "psignd",
2783 int_x86_ssse3_psign_d,
2784 int_x86_ssse3_psign_d_128>;
2787 // palignr patterns.
2788 let Constraints = "$src1 = $dst" in {
2789 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2790 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
2791 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2793 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2794 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
2795 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2798 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2799 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
2800 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2802 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2803 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
2804 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2808 let AddedComplexity = 5 in {
2810 def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
2811 (PALIGNR64rr VR64:$src2, VR64:$src1,
2812 (SHUFFLE_get_palign_imm VR64:$src3))>,
2813 Requires<[HasSSSE3]>;
2814 def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)),
2815 (PALIGNR64rr VR64:$src2, VR64:$src1,
2816 (SHUFFLE_get_palign_imm VR64:$src3))>,
2817 Requires<[HasSSSE3]>;
2818 def : Pat<(v2f32 (palign:$src3 VR64:$src1, VR64:$src2)),
2819 (PALIGNR64rr VR64:$src2, VR64:$src1,
2820 (SHUFFLE_get_palign_imm VR64:$src3))>,
2821 Requires<[HasSSSE3]>;
2822 def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)),
2823 (PALIGNR64rr VR64:$src2, VR64:$src1,
2824 (SHUFFLE_get_palign_imm VR64:$src3))>,
2825 Requires<[HasSSSE3]>;
2826 def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)),
2827 (PALIGNR64rr VR64:$src2, VR64:$src1,
2828 (SHUFFLE_get_palign_imm VR64:$src3))>,
2829 Requires<[HasSSSE3]>;
2831 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
2832 (PALIGNR128rr VR128:$src2, VR128:$src1,
2833 (SHUFFLE_get_palign_imm VR128:$src3))>,
2834 Requires<[HasSSSE3]>;
2835 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
2836 (PALIGNR128rr VR128:$src2, VR128:$src1,
2837 (SHUFFLE_get_palign_imm VR128:$src3))>,
2838 Requires<[HasSSSE3]>;
2839 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
2840 (PALIGNR128rr VR128:$src2, VR128:$src1,
2841 (SHUFFLE_get_palign_imm VR128:$src3))>,
2842 Requires<[HasSSSE3]>;
2843 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
2844 (PALIGNR128rr VR128:$src2, VR128:$src1,
2845 (SHUFFLE_get_palign_imm VR128:$src3))>,
2846 Requires<[HasSSSE3]>;
2849 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
2850 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
2851 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
2852 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
2854 //===---------------------------------------------------------------------===//
2855 // Non-Instruction Patterns
2856 //===---------------------------------------------------------------------===//
2858 // extload f32 -> f64. This matches load+fextend because we have a hack in
2859 // the isel (PreprocessForFPConvert) that can introduce loads after dag
2861 // Since these loads aren't folded into the fextend, we have to match it
2863 let Predicates = [HasSSE2] in
2864 def : Pat<(fextend (loadf32 addr:$src)),
2865 (CVTSS2SDrm addr:$src)>;
2868 let Predicates = [HasSSE2] in {
2869 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2870 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2871 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2872 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2873 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2874 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2875 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2876 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2877 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2878 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2879 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2880 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2881 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2882 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2883 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2884 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2885 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2886 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2887 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2888 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2889 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2890 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2891 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2892 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2893 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2894 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2895 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2896 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2897 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2898 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2901 // Move scalar to XMM zero-extended
2902 // movd to XMM register zero-extends
2903 let AddedComplexity = 15 in {
2904 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2905 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
2906 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
2907 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
2908 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
2909 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
2910 (MOVSSrr (v4f32 (V_SET0PS)),
2911 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
2912 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
2913 (MOVSSrr (v4i32 (V_SET0PI)),
2914 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
2917 // Splat v2f64 / v2i64
2918 let AddedComplexity = 10 in {
2919 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2920 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2921 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
2922 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2923 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
2924 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2925 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
2926 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2929 // Special unary SHUFPSrri case.
2930 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2931 (SHUFPSrri VR128:$src1, VR128:$src1,
2932 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2933 let AddedComplexity = 5 in
2934 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
2935 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2936 Requires<[HasSSE2]>;
2937 // Special unary SHUFPDrri case.
2938 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2939 (SHUFPDrri VR128:$src1, VR128:$src1,
2940 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2941 Requires<[HasSSE2]>;
2942 // Special unary SHUFPDrri case.
2943 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2944 (SHUFPDrri VR128:$src1, VR128:$src1,
2945 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2946 Requires<[HasSSE2]>;
2947 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2948 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
2949 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2950 Requires<[HasSSE2]>;
2952 // Special binary v4i32 shuffle cases with SHUFPS.
2953 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2954 (SHUFPSrri VR128:$src1, VR128:$src2,
2955 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2956 Requires<[HasSSE2]>;
2957 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
2958 (SHUFPSrmi VR128:$src1, addr:$src2,
2959 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2960 Requires<[HasSSE2]>;
2961 // Special binary v2i64 shuffle cases using SHUFPDrri.
2962 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2963 (SHUFPDrri VR128:$src1, VR128:$src2,
2964 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2965 Requires<[HasSSE2]>;
2967 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2968 let AddedComplexity = 15 in {
2969 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
2970 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2971 Requires<[OptForSpeed, HasSSE2]>;
2972 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
2973 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2974 Requires<[OptForSpeed, HasSSE2]>;
2976 let AddedComplexity = 10 in {
2977 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
2978 (UNPCKLPSrr VR128:$src, VR128:$src)>;
2979 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
2980 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
2981 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
2982 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
2983 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
2984 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
2987 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2988 let AddedComplexity = 15 in {
2989 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
2990 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2991 Requires<[OptForSpeed, HasSSE2]>;
2992 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
2993 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2994 Requires<[OptForSpeed, HasSSE2]>;
2996 let AddedComplexity = 10 in {
2997 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
2998 (UNPCKHPSrr VR128:$src, VR128:$src)>;
2999 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3000 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3001 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3002 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3003 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3004 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3007 let AddedComplexity = 20 in {
3008 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3009 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3010 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3012 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3013 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3014 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3016 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3017 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3018 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3019 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3020 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3023 let AddedComplexity = 20 in {
3024 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3025 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3026 (MOVLPSrm VR128:$src1, addr:$src2)>;
3027 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3028 (MOVLPDrm VR128:$src1, addr:$src2)>;
3029 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3030 (MOVLPSrm VR128:$src1, addr:$src2)>;
3031 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3032 (MOVLPDrm VR128:$src1, addr:$src2)>;
3035 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3036 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3037 (MOVLPSmr addr:$src1, VR128:$src2)>;
3038 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3039 (MOVLPDmr addr:$src1, VR128:$src2)>;
3040 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3042 (MOVLPSmr addr:$src1, VR128:$src2)>;
3043 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3044 (MOVLPDmr addr:$src1, VR128:$src2)>;
3046 let AddedComplexity = 15 in {
3047 // Setting the lowest element in the vector.
3048 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3049 (MOVSSrr (v4i32 VR128:$src1),
3050 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3051 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3052 (MOVSDrr (v2i64 VR128:$src1),
3053 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
3055 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3056 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3057 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3058 Requires<[HasSSE2]>;
3059 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3060 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3061 Requires<[HasSSE2]>;
3064 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3065 // fall back to this for SSE1)
3066 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3067 (SHUFPSrri VR128:$src2, VR128:$src1,
3068 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3070 // Set lowest element and zero upper elements.
3071 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3072 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3074 // Some special case pandn patterns.
3075 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3077 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3078 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3080 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3081 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3083 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3085 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3086 (memop addr:$src2))),
3087 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3088 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3089 (memop addr:$src2))),
3090 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3091 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3092 (memop addr:$src2))),
3093 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3095 // vector -> vector casts
3096 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3097 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3098 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3099 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3100 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3101 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3102 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3103 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3105 // Use movaps / movups for SSE integer load / store (one byte shorter).
3106 def : Pat<(alignedloadv4i32 addr:$src),
3107 (MOVAPSrm addr:$src)>;
3108 def : Pat<(loadv4i32 addr:$src),
3109 (MOVUPSrm addr:$src)>;
3110 def : Pat<(alignedloadv2i64 addr:$src),
3111 (MOVAPSrm addr:$src)>;
3112 def : Pat<(loadv2i64 addr:$src),
3113 (MOVUPSrm addr:$src)>;
3115 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3116 (MOVAPSmr addr:$dst, VR128:$src)>;
3117 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3118 (MOVAPSmr addr:$dst, VR128:$src)>;
3119 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3120 (MOVAPSmr addr:$dst, VR128:$src)>;
3121 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3122 (MOVAPSmr addr:$dst, VR128:$src)>;
3123 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3124 (MOVUPSmr addr:$dst, VR128:$src)>;
3125 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3126 (MOVUPSmr addr:$dst, VR128:$src)>;
3127 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3128 (MOVUPSmr addr:$dst, VR128:$src)>;
3129 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3130 (MOVUPSmr addr:$dst, VR128:$src)>;
3132 //===----------------------------------------------------------------------===//
3133 // SSE4.1 Instructions
3134 //===----------------------------------------------------------------------===//
3136 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3139 Intrinsic V2F64Int> {
3140 // Intrinsic operation, reg.
3141 // Vector intrinsic operation, reg
3142 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3143 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3144 !strconcat(OpcodeStr,
3145 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3146 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3149 // Vector intrinsic operation, mem
3150 def PSm_Int : Ii8<opcps, MRMSrcMem,
3151 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3152 !strconcat(OpcodeStr,
3153 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3155 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3157 Requires<[HasSSE41]>;
3159 // Vector intrinsic operation, reg
3160 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3161 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3162 !strconcat(OpcodeStr,
3163 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3164 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3167 // Vector intrinsic operation, mem
3168 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3169 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3170 !strconcat(OpcodeStr,
3171 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3173 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3177 let Constraints = "$src1 = $dst" in {
3178 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3182 // Intrinsic operation, reg.
3183 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3185 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3186 !strconcat(OpcodeStr,
3187 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3189 (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3192 // Intrinsic operation, mem.
3193 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3195 (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3196 !strconcat(OpcodeStr,
3197 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3199 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
3202 // Intrinsic operation, reg.
3203 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3205 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3206 !strconcat(OpcodeStr,
3207 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3209 (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3212 // Intrinsic operation, mem.
3213 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3215 (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
3216 !strconcat(OpcodeStr,
3217 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3219 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
3224 // FP round - roundss, roundps, roundsd, roundpd
3225 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
3226 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
3227 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
3228 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
3230 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3231 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3232 Intrinsic IntId128> {
3233 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3235 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3236 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3237 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3239 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3242 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3245 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3246 int_x86_sse41_phminposuw>;
3248 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3249 let Constraints = "$src1 = $dst" in {
3250 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3251 Intrinsic IntId128, bit Commutable = 0> {
3252 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3253 (ins VR128:$src1, VR128:$src2),
3254 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3255 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3257 let isCommutable = Commutable;
3259 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3260 (ins VR128:$src1, i128mem:$src2),
3261 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3263 (IntId128 VR128:$src1,
3264 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3268 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3269 int_x86_sse41_pcmpeqq, 1>;
3270 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3271 int_x86_sse41_packusdw, 0>;
3272 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3273 int_x86_sse41_pminsb, 1>;
3274 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3275 int_x86_sse41_pminsd, 1>;
3276 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3277 int_x86_sse41_pminud, 1>;
3278 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3279 int_x86_sse41_pminuw, 1>;
3280 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3281 int_x86_sse41_pmaxsb, 1>;
3282 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3283 int_x86_sse41_pmaxsd, 1>;
3284 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3285 int_x86_sse41_pmaxud, 1>;
3286 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3287 int_x86_sse41_pmaxuw, 1>;
3289 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
3291 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3292 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3293 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3294 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3296 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3297 let Constraints = "$src1 = $dst" in {
3298 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3299 SDNode OpNode, Intrinsic IntId128,
3300 bit Commutable = 0> {
3301 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3302 (ins VR128:$src1, VR128:$src2),
3303 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3304 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3305 VR128:$src2))]>, OpSize {
3306 let isCommutable = Commutable;
3308 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3309 (ins VR128:$src1, VR128:$src2),
3310 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3311 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3313 let isCommutable = Commutable;
3315 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3316 (ins VR128:$src1, i128mem:$src2),
3317 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3319 (OpVT (OpNode VR128:$src1, (memop addr:$src2))))]>, OpSize;
3320 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3321 (ins VR128:$src1, i128mem:$src2),
3322 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3324 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3329 /// SS48I_binop_rm - Simple SSE41 binary operator.
3330 let Constraints = "$src1 = $dst" in {
3331 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3332 ValueType OpVT, bit Commutable = 0> {
3333 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3334 (ins VR128:$src1, VR128:$src2),
3335 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3336 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
3338 let isCommutable = Commutable;
3340 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3341 (ins VR128:$src1, i128mem:$src2),
3342 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3343 [(set VR128:$dst, (OpNode VR128:$src1,
3344 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
3349 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, 1>;
3351 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3352 let Constraints = "$src1 = $dst" in {
3353 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3354 Intrinsic IntId128, bit Commutable = 0> {
3355 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3356 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3357 !strconcat(OpcodeStr,
3358 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3360 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3362 let isCommutable = Commutable;
3364 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3365 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3366 !strconcat(OpcodeStr,
3367 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3369 (IntId128 VR128:$src1,
3370 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3375 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3376 int_x86_sse41_blendps, 0>;
3377 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3378 int_x86_sse41_blendpd, 0>;
3379 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3380 int_x86_sse41_pblendw, 0>;
3381 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3382 int_x86_sse41_dpps, 1>;
3383 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3384 int_x86_sse41_dppd, 1>;
3385 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3386 int_x86_sse41_mpsadbw, 0>;
3389 /// SS41I_ternary_int - SSE 4.1 ternary operator
3390 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3391 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3392 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3393 (ins VR128:$src1, VR128:$src2),
3394 !strconcat(OpcodeStr,
3395 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3396 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3399 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3400 (ins VR128:$src1, i128mem:$src2),
3401 !strconcat(OpcodeStr,
3402 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3405 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3409 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3410 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3411 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3414 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3415 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3416 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3417 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3419 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3420 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3422 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3426 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3427 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3428 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3429 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3430 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3431 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3433 // Common patterns involving scalar load.
3434 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3435 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3436 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3437 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3439 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3440 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3441 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3442 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3444 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3445 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3446 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3447 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3449 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3450 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3451 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3452 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3454 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3455 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3456 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3457 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3459 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3460 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3461 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3462 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3465 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3466 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3467 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3468 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3470 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3471 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3473 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3477 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3478 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3479 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3480 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3482 // Common patterns involving scalar load
3483 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3484 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3485 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3486 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3488 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3489 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3490 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3491 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3494 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3495 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3496 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3497 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3499 // Expecting a i16 load any extended to i32 value.
3500 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3501 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3502 [(set VR128:$dst, (IntId (bitconvert
3503 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3507 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3508 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
3510 // Common patterns involving scalar load
3511 def : Pat<(int_x86_sse41_pmovsxbq
3512 (bitconvert (v4i32 (X86vzmovl
3513 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3514 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3516 def : Pat<(int_x86_sse41_pmovzxbq
3517 (bitconvert (v4i32 (X86vzmovl
3518 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3519 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3522 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3523 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3524 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3525 (ins VR128:$src1, i32i8imm:$src2),
3526 !strconcat(OpcodeStr,
3527 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3528 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3530 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3531 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3532 !strconcat(OpcodeStr,
3533 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3536 // There's an AssertZext in the way of writing the store pattern
3537 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3540 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3543 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3544 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3545 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3546 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3547 !strconcat(OpcodeStr,
3548 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3551 // There's an AssertZext in the way of writing the store pattern
3552 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3555 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3558 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3559 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3560 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3561 (ins VR128:$src1, i32i8imm:$src2),
3562 !strconcat(OpcodeStr,
3563 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3565 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3566 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3567 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3568 !strconcat(OpcodeStr,
3569 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3570 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3571 addr:$dst)]>, OpSize;
3574 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3577 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3579 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3580 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3581 (ins VR128:$src1, i32i8imm:$src2),
3582 !strconcat(OpcodeStr,
3583 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3585 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3587 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3588 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3589 !strconcat(OpcodeStr,
3590 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3591 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3592 addr:$dst)]>, OpSize;
3595 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3597 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3598 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3601 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3602 Requires<[HasSSE41]>;
3604 let Constraints = "$src1 = $dst" in {
3605 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3606 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3607 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3608 !strconcat(OpcodeStr,
3609 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3611 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3612 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3613 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3614 !strconcat(OpcodeStr,
3615 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3617 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3618 imm:$src3))]>, OpSize;
3622 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3624 let Constraints = "$src1 = $dst" in {
3625 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3626 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3627 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3628 !strconcat(OpcodeStr,
3629 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3631 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3633 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3634 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3635 !strconcat(OpcodeStr,
3636 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3638 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3639 imm:$src3)))]>, OpSize;
3643 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3645 // insertps has a few different modes, there's the first two here below which
3646 // are optimized inserts that won't zero arbitrary elements in the destination
3647 // vector. The next one matches the intrinsic and could zero arbitrary elements
3648 // in the target vector.
3649 let Constraints = "$src1 = $dst" in {
3650 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3651 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3652 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3653 !strconcat(OpcodeStr,
3654 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3656 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
3658 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3659 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3660 !strconcat(OpcodeStr,
3661 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3663 (X86insrtps VR128:$src1,
3664 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
3665 imm:$src3))]>, OpSize;
3669 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3671 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
3672 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
3674 // ptest instruction we'll lower to this in X86ISelLowering primarily from
3675 // the intel intrinsic that corresponds to this.
3676 let Defs = [EFLAGS] in {
3677 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3678 "ptest \t{$src2, $src1|$src1, $src2}",
3679 [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
3681 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3682 "ptest \t{$src2, $src1|$src1, $src2}",
3683 [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
3687 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3688 "movntdqa\t{$src, $dst|$dst, $src}",
3689 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
3693 //===----------------------------------------------------------------------===//
3694 // SSE4.2 Instructions
3695 //===----------------------------------------------------------------------===//
3697 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3698 let Constraints = "$src1 = $dst" in {
3699 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3700 Intrinsic IntId128, bit Commutable = 0> {
3701 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3702 (ins VR128:$src1, VR128:$src2),
3703 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3704 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3706 let isCommutable = Commutable;
3708 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3709 (ins VR128:$src1, i128mem:$src2),
3710 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3712 (IntId128 VR128:$src1,
3713 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3717 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3719 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3720 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3721 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3722 (PCMPGTQrm VR128:$src1, addr:$src2)>;
3724 // crc intrinsic instruction
3725 // This set of instructions are only rm, the only difference is the size
3727 let Constraints = "$src1 = $dst" in {
3728 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
3729 (ins GR32:$src1, i8mem:$src2),
3730 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3732 (int_x86_sse42_crc32_8 GR32:$src1,
3733 (load addr:$src2)))]>;
3734 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
3735 (ins GR32:$src1, GR8:$src2),
3736 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3738 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;
3739 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3740 (ins GR32:$src1, i16mem:$src2),
3741 "crc32{w} \t{$src2, $src1|$src1, $src2}",
3743 (int_x86_sse42_crc32_16 GR32:$src1,
3744 (load addr:$src2)))]>,
3746 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3747 (ins GR32:$src1, GR16:$src2),
3748 "crc32{w} \t{$src2, $src1|$src1, $src2}",
3750 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
3752 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3753 (ins GR32:$src1, i32mem:$src2),
3754 "crc32{l} \t{$src2, $src1|$src1, $src2}",
3756 (int_x86_sse42_crc32_32 GR32:$src1,
3757 (load addr:$src2)))]>;
3758 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3759 (ins GR32:$src1, GR32:$src2),
3760 "crc32{l} \t{$src2, $src1|$src1, $src2}",
3762 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;
3763 def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
3764 (ins GR64:$src1, i8mem:$src2),
3765 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3767 (int_x86_sse42_crc64_8 GR64:$src1,
3768 (load addr:$src2)))]>,
3770 def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
3771 (ins GR64:$src1, GR8:$src2),
3772 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3774 (int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,
3776 def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
3777 (ins GR64:$src1, i64mem:$src2),
3778 "crc32{q} \t{$src2, $src1|$src1, $src2}",
3780 (int_x86_sse42_crc64_64 GR64:$src1,
3781 (load addr:$src2)))]>,
3783 def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
3784 (ins GR64:$src1, GR64:$src2),
3785 "crc32{q} \t{$src2, $src1|$src1, $src2}",
3787 (int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,
3791 // String/text processing instructions.
3792 let Defs = [EFLAGS], usesCustomInserter = 1 in {
3793 def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3794 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3795 "#PCMPISTRM128rr PSEUDO!",
3796 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
3797 imm:$src3))]>, OpSize;
3798 def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3799 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3800 "#PCMPISTRM128rm PSEUDO!",
3801 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, (load addr:$src2),
3802 imm:$src3))]>, OpSize;
3805 let Defs = [XMM0, EFLAGS] in {
3806 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
3807 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3808 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3809 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
3810 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3811 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3814 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
3815 def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3816 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3817 "#PCMPESTRM128rr PSEUDO!",
3819 (int_x86_sse42_pcmpestrm128
3820 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
3822 def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3823 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3824 "#PCMPESTRM128rm PSEUDO!",
3825 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
3826 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
3830 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
3831 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
3832 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3833 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3834 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
3835 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3836 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3839 let Defs = [ECX, EFLAGS] in {
3840 multiclass SS42AI_pcmpistri<Intrinsic IntId128> {
3841 def rr : SS42AI<0x63, MRMSrcReg, (outs),
3842 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3843 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3844 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
3845 (implicit EFLAGS)]>, OpSize;
3846 def rm : SS42AI<0x63, MRMSrcMem, (outs),
3847 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3848 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3849 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
3850 (implicit EFLAGS)]>, OpSize;
3854 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
3855 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
3856 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
3857 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
3858 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
3859 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
3861 let Defs = [ECX, EFLAGS] in {
3862 let Uses = [EAX, EDX] in {
3863 multiclass SS42AI_pcmpestri<Intrinsic IntId128> {
3864 def rr : SS42AI<0x61, MRMSrcReg, (outs),
3865 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3866 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
3867 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
3868 (implicit EFLAGS)]>, OpSize;
3869 def rm : SS42AI<0x61, MRMSrcMem, (outs),
3870 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3871 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
3873 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
3874 (implicit EFLAGS)]>, OpSize;
3879 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
3880 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
3881 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
3882 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
3883 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
3884 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
3886 //===----------------------------------------------------------------------===//
3887 // AES-NI Instructions
3888 //===----------------------------------------------------------------------===//
3890 let Constraints = "$src1 = $dst" in {
3891 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
3892 Intrinsic IntId128, bit Commutable = 0> {
3893 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
3894 (ins VR128:$src1, VR128:$src2),
3895 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3896 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3898 let isCommutable = Commutable;
3900 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
3901 (ins VR128:$src1, i128mem:$src2),
3902 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3904 (IntId128 VR128:$src1,
3905 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3909 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
3910 int_x86_aesni_aesenc>;
3911 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
3912 int_x86_aesni_aesenclast>;
3913 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
3914 int_x86_aesni_aesdec>;
3915 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
3916 int_x86_aesni_aesdeclast>;
3918 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
3919 (AESENCrr VR128:$src1, VR128:$src2)>;
3920 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
3921 (AESENCrm VR128:$src1, addr:$src2)>;
3922 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
3923 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
3924 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
3925 (AESENCLASTrm VR128:$src1, addr:$src2)>;
3926 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
3927 (AESDECrr VR128:$src1, VR128:$src2)>;
3928 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
3929 (AESDECrm VR128:$src1, addr:$src2)>;
3930 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
3931 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
3932 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
3933 (AESDECLASTrm VR128:$src1, addr:$src2)>;
3935 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
3937 "aesimc\t{$src1, $dst|$dst, $src1}",
3939 (int_x86_aesni_aesimc VR128:$src1))]>,
3942 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
3943 (ins i128mem:$src1),
3944 "aesimc\t{$src1, $dst|$dst, $src1}",
3946 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
3949 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
3950 (ins VR128:$src1, i8imm:$src2),
3951 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3953 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
3955 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
3956 (ins i128mem:$src1, i8imm:$src2),
3957 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3959 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),