1 //====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 MMX instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Instruction templates
18 //===----------------------------------------------------------------------===//
20 // MMXI - MMX instructions with TB prefix.
21 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
22 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
23 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
24 // MMXID - MMX instructions with XD prefix.
25 // MMXIS - MMX instructions with XS prefix.
26 class MMXI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
27 : I<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>;
28 class MMX2I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
29 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasMMX]>;
30 class MMXIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
31 : Ii8<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>;
32 class MMXID<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
33 : Ii8<o, F, ops, asm, pattern>, XD, Requires<[HasMMX]>;
34 class MMXIS<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
35 : Ii8<o, F, ops, asm, pattern>, XS, Requires<[HasMMX]>;
37 // Some 'special' instructions
38 def IMPLICIT_DEF_VR64 : I<0, Pseudo, (ops VR64:$dst),
40 [(set VR64:$dst, (v8i8 (undef)))]>,
43 // 64-bit vector undef's.
44 def : Pat<(v8i8 (undef)), (IMPLICIT_DEF_VR64)>;
45 def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>;
46 def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>;
47 def : Pat<(v1i64 (undef)), (IMPLICIT_DEF_VR64)>;
49 //===----------------------------------------------------------------------===//
50 // MMX Pattern Fragments
51 //===----------------------------------------------------------------------===//
53 def load_mmx : PatFrag<(ops node:$ptr), (v1i64 (load node:$ptr))>;
55 def bc_v8i8 : PatFrag<(ops node:$in), (v8i8 (bitconvert node:$in))>;
56 def bc_v4i16 : PatFrag<(ops node:$in), (v4i16 (bitconvert node:$in))>;
57 def bc_v2i32 : PatFrag<(ops node:$in), (v2i32 (bitconvert node:$in))>;
58 def bc_v1i64 : PatFrag<(ops node:$in), (v1i64 (bitconvert node:$in))>;
60 //===----------------------------------------------------------------------===//
62 //===----------------------------------------------------------------------===//
64 // MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
66 def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
67 return getI8Imm(X86::getShuffleSHUFImmediate(N));
70 // Patterns for: vector_shuffle v1, v2, <2, 6, 3, 7, ...>
71 def MMX_UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
72 return X86::isUNPCKHMask(N);
75 // Patterns for: vector_shuffle v1, v2, <0, 4, 2, 5, ...>
76 def MMX_UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
77 return X86::isUNPCKLMask(N);
80 // Patterns for: vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
81 def MMX_UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
82 return X86::isUNPCKH_v_undef_Mask(N);
85 // Patterns for: vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
86 def MMX_UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
87 return X86::isUNPCKL_v_undef_Mask(N);
90 // Patterns for shuffling.
91 def MMX_PSHUFW_shuffle_mask : PatLeaf<(build_vector), [{
92 return X86::isPSHUFDMask(N);
93 }], MMX_SHUFFLE_get_shuf_imm>;
95 // Patterns for: vector_shuffle v1, v2, <4, 5, 2, 3>; etc.
96 def MMX_MOVL_shuffle_mask : PatLeaf<(build_vector), [{
97 return X86::isMOVLMask(N);
100 //===----------------------------------------------------------------------===//
102 //===----------------------------------------------------------------------===//
104 let isTwoAddress = 1 in {
105 // MMXI_binop_rm - Simple MMX binary operator.
106 multiclass MMXI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
107 ValueType OpVT, bit Commutable = 0> {
108 def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
109 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
110 [(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
111 let isCommutable = Commutable;
113 def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
114 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
115 [(set VR64:$dst, (OpVT (OpNode VR64:$src1,
117 (load_mmx addr:$src2)))))]>;
120 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
121 bit Commutable = 0> {
122 def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
123 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
124 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
125 let isCommutable = Commutable;
127 def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
128 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
129 [(set VR64:$dst, (IntId VR64:$src1,
130 (bitconvert (load_mmx addr:$src2))))]>;
133 // MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
135 // FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen knew
136 // to collapse (bitconvert VT to VT) into its operand.
138 multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
139 bit Commutable = 0> {
140 def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
141 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
142 [(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
143 let isCommutable = Commutable;
145 def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
146 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
148 (OpNode VR64:$src1,(load_mmx addr:$src2)))]>;
151 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
152 string OpcodeStr, Intrinsic IntId> {
153 def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
154 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
155 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
156 def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
157 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
158 [(set VR64:$dst, (IntId VR64:$src1,
159 (bitconvert (load_mmx addr:$src2))))]>;
160 def ri : MMXIi8<opc2, ImmForm, (ops VR64:$dst, VR64:$src1, i32i8imm:$src2),
161 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
162 [(set VR64:$dst, (IntId VR64:$src1,
163 (scalar_to_vector (i32 imm:$src2))))]>;
167 //===----------------------------------------------------------------------===//
168 // MMX EMMS & FEMMS Instructions
169 //===----------------------------------------------------------------------===//
171 def MMX_EMMS : MMXI<0x77, RawFrm, (ops), "emms", [(int_x86_mmx_emms)]>;
172 def MMX_FEMMS : MMXI<0x0E, RawFrm, (ops), "femms", [(int_x86_mmx_femms)]>;
174 //===----------------------------------------------------------------------===//
175 // MMX Scalar Instructions
176 //===----------------------------------------------------------------------===//
178 // Data Transfer Instructions
179 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
180 "movd {$src, $dst|$dst, $src}", []>;
181 def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
182 "movd {$src, $dst|$dst, $src}", []>;
183 def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src),
184 "movd {$src, $dst|$dst, $src}", []>;
186 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src),
187 "movq {$src, $dst|$dst, $src}", []>;
188 def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src),
189 "movq {$src, $dst|$dst, $src}",
190 [(set VR64:$dst, (load_mmx addr:$src))]>;
191 def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
192 "movq {$src, $dst|$dst, $src}",
193 [(store (v1i64 VR64:$src), addr:$dst)]>;
195 def MMX_MOVDQ2Qrr : MMXID<0xD6, MRMDestMem, (ops VR64:$dst, VR128:$src),
196 "movdq2q {$src, $dst|$dst, $src}",
198 (v1i64 (vector_extract (v2i64 VR128:$src),
201 def MMX_MOVQ2DQrr : MMXIS<0xD6, MRMDestMem, (ops VR128:$dst, VR64:$src),
202 "movq2dq {$src, $dst|$dst, $src}",
204 (bitconvert (v1i64 VR64:$src)))]>;
206 def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (ops i64mem:$dst, VR64:$src),
207 "movntq {$src, $dst|$dst, $src}",
208 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>;
210 let AddedComplexity = 15 in
211 // movd to MMX register zero-extends
212 def MMX_MOVZDI2PDIrr : MMX2I<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
213 "movd {$src, $dst|$dst, $src}",
215 (v2i32 (vector_shuffle immAllZerosV,
216 (v2i32 (scalar_to_vector GR32:$src)),
217 MMX_MOVL_shuffle_mask)))]>;
218 let AddedComplexity = 20 in
219 def MMX_MOVZDI2PDIrm : MMX2I<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
220 "movd {$src, $dst|$dst, $src}",
222 (v2i32 (vector_shuffle immAllZerosV,
223 (v2i32 (scalar_to_vector
224 (loadi32 addr:$src))),
225 MMX_MOVL_shuffle_mask)))]>;
227 // Arithmetic Instructions
230 defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>;
231 defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>;
232 defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>;
233 defm MMX_PADDQ : MMXI_binop_rm<0xD4, "paddq", add, v1i64, 1>;
235 defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>;
236 defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
238 defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
239 defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
242 defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>;
243 defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>;
244 defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>;
245 defm MMX_PSUBQ : MMXI_binop_rm<0xFB, "psubq", sub, v1i64>;
247 defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>;
248 defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
250 defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
251 defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
254 defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>;
256 defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>;
257 defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>;
258 defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 1>;
261 defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
263 defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 1>;
264 defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 1>;
266 defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, 1>;
267 defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, 1>;
269 defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, 1>;
270 defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 1>;
272 defm MMX_PSADBW : MMXI_binop_rm_int<0xE0, "psadbw", int_x86_mmx_psad_bw, 1>;
274 // Logical Instructions
275 defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>;
276 defm MMX_POR : MMXI_binop_rm_v1i64<0xEB, "por" , or, 1>;
277 defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>;
279 let isTwoAddress = 1 in {
280 def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg,
281 (ops VR64:$dst, VR64:$src1, VR64:$src2),
282 "pandn {$src2, $dst|$dst, $src2}",
283 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
285 def MMX_PANDNrm : MMXI<0xDF, MRMSrcMem,
286 (ops VR64:$dst, VR64:$src1, i64mem:$src2),
287 "pandn {$src2, $dst|$dst, $src2}",
288 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
289 (load addr:$src2))))]>;
292 // Shift Instructions
293 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
295 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
297 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
300 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
302 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
304 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
307 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
309 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
312 // Comparison Instructions
313 defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>;
314 defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w>;
315 defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d>;
317 defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b>;
318 defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w>;
319 defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d>;
321 // Conversion Instructions
323 // -- Unpack Instructions
324 let isTwoAddress = 1 in {
325 // Unpack High Packed Data Instructions
326 def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
327 (ops VR64:$dst, VR64:$src1, VR64:$src2),
328 "punpckhbw {$src2, $dst|$dst, $src2}",
330 (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
331 MMX_UNPCKH_shuffle_mask)))]>;
332 def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
333 (ops VR64:$dst, VR64:$src1, i64mem:$src2),
334 "punpckhbw {$src2, $dst|$dst, $src2}",
336 (v8i8 (vector_shuffle VR64:$src1,
337 (bc_v8i8 (load_mmx addr:$src2)),
338 MMX_UNPCKH_shuffle_mask)))]>;
340 def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
341 (ops VR64:$dst, VR64:$src1, VR64:$src2),
342 "punpckhwd {$src2, $dst|$dst, $src2}",
344 (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
345 MMX_UNPCKH_shuffle_mask)))]>;
346 def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
347 (ops VR64:$dst, VR64:$src1, i64mem:$src2),
348 "punpckhwd {$src2, $dst|$dst, $src2}",
350 (v4i16 (vector_shuffle VR64:$src1,
351 (bc_v4i16 (load_mmx addr:$src2)),
352 MMX_UNPCKH_shuffle_mask)))]>;
354 def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
355 (ops VR64:$dst, VR64:$src1, VR64:$src2),
356 "punpckhdq {$src2, $dst|$dst, $src2}",
358 (v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
359 MMX_UNPCKH_shuffle_mask)))]>;
360 def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
361 (ops VR64:$dst, VR64:$src1, i64mem:$src2),
362 "punpckhdq {$src2, $dst|$dst, $src2}",
364 (v2i32 (vector_shuffle VR64:$src1,
365 (bc_v2i32 (load_mmx addr:$src2)),
366 MMX_UNPCKH_shuffle_mask)))]>;
368 // Unpack Low Packed Data Instructions
369 def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg,
370 (ops VR64:$dst, VR64:$src1, VR64:$src2),
371 "punpcklbw {$src2, $dst|$dst, $src2}",
373 (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
374 MMX_UNPCKL_shuffle_mask)))]>;
375 def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem,
376 (ops VR64:$dst, VR64:$src1, i64mem:$src2),
377 "punpcklbw {$src2, $dst|$dst, $src2}",
379 (v8i8 (vector_shuffle VR64:$src1,
380 (bc_v8i8 (load_mmx addr:$src2)),
381 MMX_UNPCKL_shuffle_mask)))]>;
383 def MMX_PUNPCKLWDrr : MMXI<0x61, MRMSrcReg,
384 (ops VR64:$dst, VR64:$src1, VR64:$src2),
385 "punpcklwd {$src2, $dst|$dst, $src2}",
387 (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
388 MMX_UNPCKL_shuffle_mask)))]>;
389 def MMX_PUNPCKLWDrm : MMXI<0x61, MRMSrcMem,
390 (ops VR64:$dst, VR64:$src1, i64mem:$src2),
391 "punpcklwd {$src2, $dst|$dst, $src2}",
393 (v4i16 (vector_shuffle VR64:$src1,
394 (bc_v4i16 (load_mmx addr:$src2)),
395 MMX_UNPCKL_shuffle_mask)))]>;
397 def MMX_PUNPCKLDQrr : MMXI<0x62, MRMSrcReg,
398 (ops VR64:$dst, VR64:$src1, VR64:$src2),
399 "punpckldq {$src2, $dst|$dst, $src2}",
401 (v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
402 MMX_UNPCKL_shuffle_mask)))]>;
403 def MMX_PUNPCKLDQrm : MMXI<0x62, MRMSrcMem,
404 (ops VR64:$dst, VR64:$src1, i64mem:$src2),
405 "punpckldq {$src2, $dst|$dst, $src2}",
407 (v2i32 (vector_shuffle VR64:$src1,
408 (bc_v2i32 (load_mmx addr:$src2)),
409 MMX_UNPCKL_shuffle_mask)))]>;
412 // -- Pack Instructions
413 defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
414 defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
415 defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
417 // -- Shuffle Instructions
418 def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
419 (ops VR64:$dst, VR64:$src1, i8imm:$src2),
420 "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}",
422 (v4i16 (vector_shuffle
424 MMX_PSHUFW_shuffle_mask:$src2)))]>;
425 def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
426 (ops VR64:$dst, i64mem:$src1, i8imm:$src2),
427 "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}",
429 (v4i16 (vector_shuffle
430 (bc_v4i16 (load_mmx addr:$src1)),
432 MMX_PSHUFW_shuffle_mask:$src2)))]>;
434 // -- Conversion Instructions
435 def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
436 "cvtpd2pi {$src, $dst|$dst, $src}", []>;
437 def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (ops VR64:$dst, f128mem:$src),
438 "cvtpd2pi {$src, $dst|$dst, $src}", []>;
440 def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
441 "cvtpi2pd {$src, $dst|$dst, $src}", []>;
442 def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
443 "cvtpi2pd {$src, $dst|$dst, $src}", []>;
445 def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
446 "cvtpi2ps {$src, $dst|$dst, $src}", []>;
447 def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
448 "cvtpi2ps {$src, $dst|$dst, $src}", []>;
450 def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
451 "cvtps2pi {$src, $dst|$dst, $src}", []>;
452 def MMX_CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
453 "cvtps2pi {$src, $dst|$dst, $src}", []>;
455 def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (ops VR64:$dst, VR128:$src),
456 "cvttpd2pi {$src, $dst|$dst, $src}", []>;
457 def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (ops VR64:$dst, f128mem:$src),
458 "cvttpd2pi {$src, $dst|$dst, $src}", []>;
460 def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (ops VR64:$dst, VR128:$src),
461 "cvttps2pi {$src, $dst|$dst, $src}", []>;
462 def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
463 "cvttps2pi {$src, $dst|$dst, $src}", []>;
466 def MMX_X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
467 def MMX_X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
469 def MMX_PEXTRWri : MMXIi8<0xC5, MRMSrcReg,
470 (ops GR32:$dst, VR64:$src1, i16i8imm:$src2),
471 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
472 [(set GR32:$dst, (MMX_X86pextrw (v4i16 VR64:$src1),
473 (iPTR imm:$src2)))]>;
474 let isTwoAddress = 1 in {
475 def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg,
476 (ops VR64:$dst, VR64:$src1, GR32:$src2, i16i8imm:$src3),
477 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
478 [(set VR64:$dst, (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
479 GR32:$src2, (iPTR imm:$src3))))]>;
480 def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem,
481 (ops VR64:$dst, VR64:$src1, i16mem:$src2, i16i8imm:$src3),
482 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
484 (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
485 (i32 (anyext (loadi16 addr:$src2))),
486 (iPTR imm:$src3))))]>;
490 def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (ops GR32:$dst, VR64:$src),
491 "pmovmskb {$src, $dst|$dst, $src}",
492 [(set GR32:$dst, (int_x86_mmx_pmovmskb VR64:$src))]>;
495 def MMX_MASKMOVQ : MMXI<0xF7, MRMDestMem, (ops VR64:$src, VR64:$mask),
496 "maskmovq {$mask, $src|$src, $mask}",
497 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>,
500 //===----------------------------------------------------------------------===//
501 // Alias Instructions
502 //===----------------------------------------------------------------------===//
504 // Alias instructions that map zero vector to pxor.
505 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
506 def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (ops VR64:$dst),
508 [(set VR64:$dst, (v1i64 immAllZerosV))]>;
509 def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (ops VR64:$dst),
510 "pcmpeqd $dst, $dst",
511 [(set VR64:$dst, (v1i64 immAllOnesV))]>;
513 //===----------------------------------------------------------------------===//
514 // Non-Instruction Patterns
515 //===----------------------------------------------------------------------===//
517 // Store 64-bit integer vector values.
518 def : Pat<(store (v8i8 VR64:$src), addr:$dst),
519 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
520 def : Pat<(store (v4i16 VR64:$src), addr:$dst),
521 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
522 def : Pat<(store (v2i32 VR64:$src), addr:$dst),
523 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
524 def : Pat<(store (v1i64 VR64:$src), addr:$dst),
525 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
527 // 64-bit vector all zero's.
528 def : Pat<(v8i8 immAllZerosV), (MMX_V_SET0)>;
529 def : Pat<(v4i16 immAllZerosV), (MMX_V_SET0)>;
530 def : Pat<(v2i32 immAllZerosV), (MMX_V_SET0)>;
531 def : Pat<(v1i64 immAllZerosV), (MMX_V_SET0)>;
533 // 64-bit vector all one's.
534 def : Pat<(v8i8 immAllOnesV), (MMX_V_SETALLONES)>;
535 def : Pat<(v4i16 immAllOnesV), (MMX_V_SETALLONES)>;
536 def : Pat<(v2i32 immAllOnesV), (MMX_V_SETALLONES)>;
537 def : Pat<(v1i64 immAllOnesV), (MMX_V_SETALLONES)>;
540 def : Pat<(v8i8 (bitconvert (v1i64 VR64:$src))), (v8i8 VR64:$src)>;
541 def : Pat<(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src)>;
542 def : Pat<(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src)>;
543 def : Pat<(v4i16 (bitconvert (v1i64 VR64:$src))), (v4i16 VR64:$src)>;
544 def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
545 def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>;
546 def : Pat<(v2i32 (bitconvert (v1i64 VR64:$src))), (v2i32 VR64:$src)>;
547 def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
548 def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>;
549 def : Pat<(v1i64 (bitconvert (v2i32 VR64:$src))), (v1i64 VR64:$src)>;
550 def : Pat<(v1i64 (bitconvert (v4i16 VR64:$src))), (v1i64 VR64:$src)>;
551 def : Pat<(v1i64 (bitconvert (v8i8 VR64:$src))), (v1i64 VR64:$src)>;
553 def MMX_X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>;
555 // Move scalar to XMM zero-extended
556 // movd to XMM register zero-extends
557 let AddedComplexity = 15 in {
558 def : Pat<(v8i8 (vector_shuffle immAllZerosV,
559 (v8i8 (MMX_X86s2vec GR32:$src)), MMX_MOVL_shuffle_mask)),
560 (MMX_MOVZDI2PDIrr GR32:$src)>;
561 def : Pat<(v4i16 (vector_shuffle immAllZerosV,
562 (v4i16 (MMX_X86s2vec GR32:$src)), MMX_MOVL_shuffle_mask)),
563 (MMX_MOVZDI2PDIrr GR32:$src)>;
564 def : Pat<(v2i32 (vector_shuffle immAllZerosV,
565 (v2i32 (MMX_X86s2vec GR32:$src)), MMX_MOVL_shuffle_mask)),
566 (MMX_MOVZDI2PDIrr GR32:$src)>;
569 // Scalar to v2i32 / v4i16 / v8i8. The source may be a GR32, but only the lower
570 // 8 or 16-bits matter.
571 def : Pat<(v8i8 (MMX_X86s2vec GR32:$src)), (MMX_MOVD64rr GR32:$src)>;
572 def : Pat<(v4i16 (MMX_X86s2vec GR32:$src)), (MMX_MOVD64rr GR32:$src)>;
573 def : Pat<(v2i32 (MMX_X86s2vec GR32:$src)), (MMX_MOVD64rr GR32:$src)>;
575 // Patterns to perform canonical versions of vector shuffling.
576 let AddedComplexity = 10 in {
577 def : Pat<(v8i8 (vector_shuffle VR64:$src, (undef),
578 MMX_UNPCKL_v_undef_shuffle_mask)),
579 (MMX_PUNPCKLBWrr VR64:$src, VR64:$src)>;
580 def : Pat<(v4i16 (vector_shuffle VR64:$src, (undef),
581 MMX_UNPCKL_v_undef_shuffle_mask)),
582 (MMX_PUNPCKLWDrr VR64:$src, VR64:$src)>;
583 def : Pat<(v2i32 (vector_shuffle VR64:$src, (undef),
584 MMX_UNPCKL_v_undef_shuffle_mask)),
585 (MMX_PUNPCKLDQrr VR64:$src, VR64:$src)>;
588 let AddedComplexity = 10 in {
589 def : Pat<(v8i8 (vector_shuffle VR64:$src, (undef),
590 MMX_UNPCKH_v_undef_shuffle_mask)),
591 (MMX_PUNPCKHBWrr VR64:$src, VR64:$src)>;
592 def : Pat<(v4i16 (vector_shuffle VR64:$src, (undef),
593 MMX_UNPCKH_v_undef_shuffle_mask)),
594 (MMX_PUNPCKHWDrr VR64:$src, VR64:$src)>;
595 def : Pat<(v2i32 (vector_shuffle VR64:$src, (undef),
596 MMX_UNPCKH_v_undef_shuffle_mask)),
597 (MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
600 // Patterns to perform vector shuffling with a zeroed out vector.
601 let AddedComplexity = 20 in {
602 def : Pat<(bc_v2i32 (vector_shuffle immAllZerosV,
603 (v2i32 (scalar_to_vector (load_mmx addr:$src))),
604 MMX_UNPCKL_shuffle_mask)),
605 (MMX_PUNPCKLDQrm VR64:$src, VR64:$src)>;
608 // Some special case PANDN patterns.
609 // FIXME: Get rid of these.
610 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
612 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
613 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV))),
615 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
616 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV))),
618 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
620 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
622 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
623 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV))),
625 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
626 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV))),
628 (MMX_PANDNrm VR64:$src1, addr:$src2)>;