1 //====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 MMX instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Instruction templates
18 //===----------------------------------------------------------------------===//
20 // MMXI - MMX instructions with TB prefix.
21 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
22 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
23 class MMXI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
24 : I<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>;
25 class MMX2I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
26 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasMMX]>;
27 class MMXIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
28 : Ii8<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>;
30 // Some 'special' instructions
31 def IMPLICIT_DEF_VR64 : I<0, Pseudo, (ops VR64:$dst),
33 [(set VR64:$dst, (v8i8 (undef)))]>,
36 // 64-bit vector undef's.
37 def : Pat<(v8i8 (undef)), (IMPLICIT_DEF_VR64)>;
38 def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>;
39 def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>;
40 def : Pat<(v1i64 (undef)), (IMPLICIT_DEF_VR64)>;
42 //===----------------------------------------------------------------------===//
43 // MMX Pattern Fragments
44 //===----------------------------------------------------------------------===//
46 def load_mmx : PatFrag<(ops node:$ptr), (v1i64 (load node:$ptr))>;
48 def bc_v8i8 : PatFrag<(ops node:$in), (v8i8 (bitconvert node:$in))>;
49 def bc_v4i16 : PatFrag<(ops node:$in), (v4i16 (bitconvert node:$in))>;
50 def bc_v2i32 : PatFrag<(ops node:$in), (v2i32 (bitconvert node:$in))>;
51 def bc_v1i64 : PatFrag<(ops node:$in), (v1i64 (bitconvert node:$in))>;
53 //===----------------------------------------------------------------------===//
55 //===----------------------------------------------------------------------===//
57 let isTwoAddress = 1 in {
58 // MMXI_binop_rm - Simple MMX binary operator.
59 multiclass MMXI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
60 ValueType OpVT, bit Commutable = 0> {
61 def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
62 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
63 [(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
64 let isCommutable = Commutable;
66 def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
67 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
68 [(set VR64:$dst, (OpVT (OpNode VR64:$src1,
70 (load_mmx addr:$src2)))))]>;
73 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
75 def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
76 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
77 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
78 let isCommutable = Commutable;
80 def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
81 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
82 [(set VR64:$dst, (IntId VR64:$src1,
83 (bitconvert (load_mmx addr:$src2))))]>;
86 // MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
88 // FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen knew
89 // to collapse (bitconvert VT to VT) into its operand.
91 multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
93 def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
94 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
95 [(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
96 let isCommutable = Commutable;
98 def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
99 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
101 (OpNode VR64:$src1,(load_mmx addr:$src2)))]>;
104 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
105 string OpcodeStr, Intrinsic IntId> {
106 def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
107 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
108 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
109 def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
110 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
111 [(set VR64:$dst, (IntId VR64:$src1,
112 (bitconvert (load_mmx addr:$src2))))]>;
113 def ri : MMXIi8<opc2, ImmForm, (ops VR64:$dst, VR64:$src1, i32i8imm:$src2),
114 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
115 [(set VR64:$dst, (IntId VR64:$src1,
116 (scalar_to_vector (i32 imm:$src2))))]>;
120 //===----------------------------------------------------------------------===//
121 // MMX EMMS Instruction
122 //===----------------------------------------------------------------------===//
124 def MMX_EMMS : MMXI<0x77, RawFrm, (ops), "emms", [(int_x86_mmx_emms)]>;
126 //===----------------------------------------------------------------------===//
127 // MMX Scalar Instructions
128 //===----------------------------------------------------------------------===//
130 // Arithmetic Instructions
133 defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>;
134 defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>;
135 defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>;
137 defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>;
138 defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
140 defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
141 defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
144 defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>;
145 defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>;
146 defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>;
148 defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>;
149 defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
151 defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
152 defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
155 defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>;
156 defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw" , int_x86_mmx_pmulh_w , 1>;
158 // -- Multiply and Add
159 defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
161 // Logical Instructions
162 defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>;
163 defm MMX_POR : MMXI_binop_rm_v1i64<0xEB, "por" , or, 1>;
164 defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>;
166 let isTwoAddress = 1 in {
167 def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg,
168 (ops VR64:$dst, VR64:$src1, VR64:$src2),
169 "pandn {$src2, $dst|$dst, $src2}",
170 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
172 def MMX_PANDNrm : MMXI<0xDF, MRMSrcMem,
173 (ops VR64:$dst, VR64:$src1, i64mem:$src2),
174 "pandn {$src2, $dst|$dst, $src2}",
175 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
176 (load addr:$src2))))]>;
179 // Shift Instructions
180 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
182 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
184 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
187 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
189 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
191 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
194 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
196 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
199 // Comparison Instructions
200 defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>;
201 defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w>;
202 defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d>;
204 defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b>;
205 defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w>;
206 defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d>;
208 // Conversion Instructions
209 def MMX_UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
210 return X86::isUNPCKHMask(N);
213 def MMX_UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
214 return X86::isUNPCKLMask(N);
217 // -- Unpack Instructions
218 let isTwoAddress = 1 in {
219 // Unpack High Packed Data Instructions
220 def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
221 (ops VR64:$dst, VR64:$src1, VR64:$src2),
222 "punpckhbw {$src2, $dst|$dst, $src2}",
224 (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
225 MMX_UNPCKH_shuffle_mask)))]>;
226 def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
227 (ops VR64:$dst, VR64:$src1, i64mem:$src2),
228 "punpckhbw {$src2, $dst|$dst, $src2}",
230 (v8i8 (vector_shuffle VR64:$src1,
231 (bc_v8i8 (load_mmx addr:$src2)),
232 MMX_UNPCKH_shuffle_mask)))]>;
234 def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
235 (ops VR64:$dst, VR64:$src1, VR64:$src2),
236 "punpckhwd {$src2, $dst|$dst, $src2}",
238 (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
239 MMX_UNPCKH_shuffle_mask)))]>;
240 def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
241 (ops VR64:$dst, VR64:$src1, i64mem:$src2),
242 "punpckhwd {$src2, $dst|$dst, $src2}",
244 (v4i16 (vector_shuffle VR64:$src1,
245 (bc_v4i16 (load_mmx addr:$src2)),
246 MMX_UNPCKH_shuffle_mask)))]>;
248 def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
249 (ops VR64:$dst, VR64:$src1, VR64:$src2),
250 "punpckhdq {$src2, $dst|$dst, $src2}",
252 (v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
253 MMX_UNPCKH_shuffle_mask)))]>;
254 def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
255 (ops VR64:$dst, VR64:$src1, i64mem:$src2),
256 "punpckhdq {$src2, $dst|$dst, $src2}",
258 (v2i32 (vector_shuffle VR64:$src1,
259 (bc_v2i32 (load_mmx addr:$src2)),
260 MMX_UNPCKH_shuffle_mask)))]>;
262 // Unpack Low Packed Data Instructions
263 def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg,
264 (ops VR64:$dst, VR64:$src1, VR64:$src2),
265 "punpcklbw {$src2, $dst|$dst, $src2}",
267 (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
268 MMX_UNPCKL_shuffle_mask)))]>;
269 def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem,
270 (ops VR64:$dst, VR64:$src1, i64mem:$src2),
271 "punpcklbw {$src2, $dst|$dst, $src2}",
273 (v8i8 (vector_shuffle VR64:$src1,
274 (bc_v8i8 (load_mmx addr:$src2)),
275 MMX_UNPCKL_shuffle_mask)))]>;
277 def MMX_PUNPCKLWDrr : MMXI<0x61, MRMSrcReg,
278 (ops VR64:$dst, VR64:$src1, VR64:$src2),
279 "punpcklwd {$src2, $dst|$dst, $src2}",
281 (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
282 MMX_UNPCKL_shuffle_mask)))]>;
283 def MMX_PUNPCKLWDrm : MMXI<0x61, MRMSrcMem,
284 (ops VR64:$dst, VR64:$src1, i64mem:$src2),
285 "punpcklwd {$src2, $dst|$dst, $src2}",
287 (v4i16 (vector_shuffle VR64:$src1,
288 (bc_v4i16 (load_mmx addr:$src2)),
289 MMX_UNPCKL_shuffle_mask)))]>;
291 def MMX_PUNPCKLDQrr : MMXI<0x62, MRMSrcReg,
292 (ops VR64:$dst, VR64:$src1, VR64:$src2),
293 "punpckldq {$src2, $dst|$dst, $src2}",
295 (v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
296 MMX_UNPCKL_shuffle_mask)))]>;
297 def MMX_PUNPCKLDQrm : MMXI<0x62, MRMSrcMem,
298 (ops VR64:$dst, VR64:$src1, i64mem:$src2),
299 "punpckldq {$src2, $dst|$dst, $src2}",
301 (v2i32 (vector_shuffle VR64:$src1,
302 (bc_v2i32 (load_mmx addr:$src2)),
303 MMX_UNPCKL_shuffle_mask)))]>;
306 // -- Pack Instructions
307 defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
308 defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
309 defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
311 // Data Transfer Instructions
312 def MOVD64rr : MMXI<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
313 "movd {$src, $dst|$dst, $src}", []>;
314 def MOVD64rm : MMXI<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
315 "movd {$src, $dst|$dst, $src}", []>;
316 def MOVD64mr : MMXI<0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src),
317 "movd {$src, $dst|$dst, $src}", []>;
319 def MOVQ64rr : MMXI<0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src),
320 "movq {$src, $dst|$dst, $src}", []>;
321 def MOVQ64rm : MMXI<0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src),
322 "movq {$src, $dst|$dst, $src}",
323 [(set VR64:$dst, (load_mmx addr:$src))]>;
324 def MOVQ64mr : MMXI<0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
325 "movq {$src, $dst|$dst, $src}",
326 [(store (v1i64 VR64:$src), addr:$dst)]>;
328 // Conversion instructions
329 def CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
330 "cvtpi2ps {$src, $dst|$dst, $src}", []>;
331 def CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
332 "cvtpi2ps {$src, $dst|$dst, $src}", []>;
333 def CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
334 "cvtpi2pd {$src, $dst|$dst, $src}", []>;
335 def CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
336 "cvtpi2pd {$src, $dst|$dst, $src}", []>;
337 def CVTTPS2PIrr: I<0x2C, MRMSrcReg, (ops VR64:$dst, VR128:$src),
338 "cvttps2pi {$src, $dst|$dst, $src}", []>, TB,
340 def CVTTPS2PIrm: I<0x2C, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
341 "cvttps2pi {$src, $dst|$dst, $src}", []>, TB,
343 def CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
344 "cvtps2pi {$src, $dst|$dst, $src}", []>;
345 def CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
346 "cvtps2pi {$src, $dst|$dst, $src}", []>;
347 def CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
348 "cvtpd2pi {$src, $dst|$dst, $src}", []>;
349 def CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (ops VR64:$dst, f128mem:$src),
350 "cvtpd2pi {$src, $dst|$dst, $src}", []>;
352 // Shuffle and unpack instructions
353 def PSHUFWri : MMXIi8<0x70, MRMSrcReg,
354 (ops VR64:$dst, VR64:$src1, i8imm:$src2),
355 "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
356 def PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
357 (ops VR64:$dst, i64mem:$src1, i8imm:$src2),
358 "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
361 def MOVNTQ : I<0xE7, MRMDestMem, (ops i64mem:$dst, VR64:$src),
362 "movntq {$src, $dst|$dst, $src}", []>, TB,
365 def MASKMOVQ : I<0xF7, MRMDestMem, (ops VR64:$src, VR64:$mask),
366 "maskmovq {$mask, $src|$src, $mask}", []>, TB,
369 //===----------------------------------------------------------------------===//
370 // Alias Instructions
371 //===----------------------------------------------------------------------===//
373 // Alias instructions that map zero vector to pxor.
374 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
375 let isReMaterializable = 1 in {
376 def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (ops VR64:$dst),
378 [(set VR64:$dst, (v1i64 immAllZerosV))]>;
379 def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (ops VR64:$dst),
380 "pcmpeqd $dst, $dst",
381 [(set VR64:$dst, (v1i64 immAllOnesV))]>;
384 //===----------------------------------------------------------------------===//
385 // Non-Instruction Patterns
386 //===----------------------------------------------------------------------===//
388 // Store 64-bit integer vector values.
389 def : Pat<(store (v8i8 VR64:$src), addr:$dst),
390 (MOVQ64mr addr:$dst, VR64:$src)>;
391 def : Pat<(store (v4i16 VR64:$src), addr:$dst),
392 (MOVQ64mr addr:$dst, VR64:$src)>;
393 def : Pat<(store (v2i32 VR64:$src), addr:$dst),
394 (MOVQ64mr addr:$dst, VR64:$src)>;
396 // 64-bit vector all zero's.
397 def : Pat<(v8i8 immAllZerosV), (MMX_V_SET0)>;
398 def : Pat<(v4i16 immAllZerosV), (MMX_V_SET0)>;
399 def : Pat<(v2i32 immAllZerosV), (MMX_V_SET0)>;
400 def : Pat<(v1i64 immAllZerosV), (MMX_V_SET0)>;
402 // 64-bit vector all one's.
403 def : Pat<(v8i8 immAllOnesV), (MMX_V_SETALLONES)>;
404 def : Pat<(v4i16 immAllOnesV), (MMX_V_SETALLONES)>;
405 def : Pat<(v2i32 immAllOnesV), (MMX_V_SETALLONES)>;
406 def : Pat<(v1i64 immAllOnesV), (MMX_V_SETALLONES)>;
409 def : Pat<(v8i8 (bitconvert (v1i64 VR64:$src))), (v8i8 VR64:$src)>;
410 def : Pat<(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src)>;
411 def : Pat<(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src)>;
412 def : Pat<(v4i16 (bitconvert (v1i64 VR64:$src))), (v4i16 VR64:$src)>;
413 def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
414 def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>;
415 def : Pat<(v2i32 (bitconvert (v1i64 VR64:$src))), (v2i32 VR64:$src)>;
416 def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
417 def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>;
418 def : Pat<(v1i64 (bitconvert (v2i32 VR64:$src))), (v1i64 VR64:$src)>;
419 def : Pat<(v1i64 (bitconvert (v4i16 VR64:$src))), (v1i64 VR64:$src)>;
420 def : Pat<(v1i64 (bitconvert (v8i8 VR64:$src))), (v1i64 VR64:$src)>;
423 // MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
424 // MMX_PSHUF*, MMX_SHUFP* etc. imm.
425 def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
426 return getI8Imm(X86::getShuffleSHUFImmediate(N));
429 def MMX_splat_mask : PatLeaf<(build_vector), [{
430 return X86::isSplatMask(N);
431 }], MMX_SHUFFLE_get_shuf_imm>;
433 let AddedComplexity = 10 in {
434 def : Pat<(vector_shuffle (v1i64 VR64:$src), (undef),
436 (MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
437 def : Pat<(vector_shuffle (v1i64 VR64:$src), (undef),
438 MMX_UNPCKH_shuffle_mask:$sm),
439 (MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
442 def MMX_X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>;
444 // Scalar to v4i16 / v8i8. The source may be a GR32, but only the lower 8 or
446 def : Pat<(v8i8 (MMX_X86s2vec GR32:$src)), (MOVD64rr GR32:$src)>;
447 def : Pat<(v4i16 (MMX_X86s2vec GR32:$src)), (MOVD64rr GR32:$src)>;
449 // Some special case PANDN patterns.
450 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
452 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
453 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV))),
455 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
456 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV))),
458 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
460 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
462 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
463 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV))),
465 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
466 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV))),
468 (MMX_PANDNrm VR64:$src1, addr:$src2)>;