1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 //def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
36 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
41 SDTCisInt<0>, SDTCisVT<1, i32>]>;
43 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
44 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
50 // RES1, RES2, FLAGS = op LHS, RHS
51 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
55 SDTCisInt<0>, SDTCisVT<1, i32>]>;
56 def SDTX86BrCond : SDTypeProfile<0, 3,
57 [SDTCisVT<0, OtherVT>,
58 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
60 def SDTX86SetCC : SDTypeProfile<1, 2,
62 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
63 def SDTX86SetCC_C : SDTypeProfile<1, 2,
65 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
67 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
69 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
71 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
73 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
75 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
76 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
77 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
79 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
80 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
83 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
85 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
89 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
95 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
97 def SDTX86Void : SDTypeProfile<0, 0, []>;
99 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
101 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
103 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
105 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
107 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
109 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
111 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
113 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
115 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
116 [SDNPHasChain,SDNPSideEffect]>;
117 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
119 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
121 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
125 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
126 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
127 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
128 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
130 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
131 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
133 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
134 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
136 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
137 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
139 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
141 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
142 [SDNPHasChain, SDNPSideEffect]>;
144 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand,
145 [SDNPHasChain, SDNPSideEffect]>;
147 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
148 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
149 SDNPMayLoad, SDNPMemOperand]>;
150 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
151 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
152 SDNPMayLoad, SDNPMemOperand]>;
153 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
154 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
155 SDNPMayLoad, SDNPMemOperand]>;
157 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
158 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
159 def X86iret : SDNode<"X86ISD::IRET", SDTX86Ret,
160 [SDNPHasChain, SDNPOptInGlue]>;
162 def X86vastart_save_xmm_regs :
163 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
164 SDT_X86VASTART_SAVE_XMM_REGS,
165 [SDNPHasChain, SDNPVariadic]>;
167 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
168 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
170 def X86callseq_start :
171 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
172 [SDNPHasChain, SDNPOutGlue]>;
174 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
175 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
177 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
178 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
181 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
182 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
183 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
184 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
187 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
188 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
189 def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void,
190 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
191 def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void,
192 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
194 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
195 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
197 def X86RecoverFrameAlloc : SDNode<"ISD::LOCAL_RECOVER",
198 SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
201 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
202 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
204 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
205 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
207 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
210 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
211 SDTypeProfile<1, 1, [SDTCisInt<0>,
213 [SDNPHasChain, SDNPSideEffect]>;
214 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
215 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
216 [SDNPHasChain, SDNPSideEffect]>;
218 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
219 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
221 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
223 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
224 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
226 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
228 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
229 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
231 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
232 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
233 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
235 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
237 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
240 def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>;
242 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
244 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
245 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
247 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
250 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
251 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
253 //===----------------------------------------------------------------------===//
254 // X86 Operand Definitions.
257 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
258 // the index operand of an address, to conform to x86 encoding restrictions.
259 def ptr_rc_nosp : PointerLikeRegClass<1>;
261 // *mem - Operand definitions for the funky X86 addressing mode operands.
263 def X86MemAsmOperand : AsmOperandClass {
266 let RenderMethod = "addMemOperands" in {
267 def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; }
268 def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; }
269 def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; }
270 def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; }
271 def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; }
272 def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; }
273 def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; }
274 def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; }
275 // Gather mem operands
276 def X86MemVX32Operand : AsmOperandClass { let Name = "MemVX32"; }
277 def X86MemVY32Operand : AsmOperandClass { let Name = "MemVY32"; }
278 def X86MemVZ32Operand : AsmOperandClass { let Name = "MemVZ32"; }
279 def X86MemVX64Operand : AsmOperandClass { let Name = "MemVX64"; }
280 def X86MemVY64Operand : AsmOperandClass { let Name = "MemVY64"; }
281 def X86MemVZ64Operand : AsmOperandClass { let Name = "MemVZ64"; }
282 def X86MemVX32XOperand : AsmOperandClass { let Name = "MemVX32X"; }
283 def X86MemVY32XOperand : AsmOperandClass { let Name = "MemVY32X"; }
284 def X86MemVX64XOperand : AsmOperandClass { let Name = "MemVX64X"; }
285 def X86MemVY64XOperand : AsmOperandClass { let Name = "MemVY64X"; }
288 def X86AbsMemAsmOperand : AsmOperandClass {
290 let SuperClasses = [X86MemAsmOperand];
293 class X86MemOperand<string printMethod,
294 AsmOperandClass parserMatchClass = X86MemAsmOperand> : Operand<iPTR> {
295 let PrintMethod = printMethod;
296 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
297 let ParserMatchClass = parserMatchClass;
298 let OperandType = "OPERAND_MEMORY";
301 // Gather mem operands
302 class X86VMemOperand<RegisterClass RC, string printMethod,
303 AsmOperandClass parserMatchClass>
304 : X86MemOperand<printMethod, parserMatchClass> {
305 let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, i8imm);
308 def anymem : X86MemOperand<"printanymem">;
310 def opaque32mem : X86MemOperand<"printopaquemem">;
311 def opaque48mem : X86MemOperand<"printopaquemem">;
312 def opaque80mem : X86MemOperand<"printopaquemem">;
313 def opaque512mem : X86MemOperand<"printopaquemem">;
315 def i8mem : X86MemOperand<"printi8mem", X86Mem8AsmOperand>;
316 def i16mem : X86MemOperand<"printi16mem", X86Mem16AsmOperand>;
317 def i32mem : X86MemOperand<"printi32mem", X86Mem32AsmOperand>;
318 def i64mem : X86MemOperand<"printi64mem", X86Mem64AsmOperand>;
319 def i128mem : X86MemOperand<"printi128mem", X86Mem128AsmOperand>;
320 def i256mem : X86MemOperand<"printi256mem", X86Mem256AsmOperand>;
321 def i512mem : X86MemOperand<"printi512mem", X86Mem512AsmOperand>;
322 def f32mem : X86MemOperand<"printf32mem", X86Mem32AsmOperand>;
323 def f64mem : X86MemOperand<"printf64mem", X86Mem64AsmOperand>;
324 def f80mem : X86MemOperand<"printf80mem", X86Mem80AsmOperand>;
325 def f128mem : X86MemOperand<"printf128mem", X86Mem128AsmOperand>;
326 def f256mem : X86MemOperand<"printf256mem", X86Mem256AsmOperand>;
327 def f512mem : X86MemOperand<"printf512mem", X86Mem512AsmOperand>;
329 def v512mem : X86VMemOperand<VR512, "printf512mem", X86Mem512AsmOperand>;
331 // Gather mem operands
332 def vx32mem : X86VMemOperand<VR128, "printi32mem", X86MemVX32Operand>;
333 def vy32mem : X86VMemOperand<VR256, "printi32mem", X86MemVY32Operand>;
334 def vx64mem : X86VMemOperand<VR128, "printi64mem", X86MemVX64Operand>;
335 def vy64mem : X86VMemOperand<VR256, "printi64mem", X86MemVY64Operand>;
337 def vx32xmem : X86VMemOperand<VR128X, "printi32mem", X86MemVX32XOperand>;
338 def vx64xmem : X86VMemOperand<VR128X, "printi32mem", X86MemVX64XOperand>;
339 def vy32xmem : X86VMemOperand<VR256X, "printi32mem", X86MemVY32XOperand>;
340 def vy64xmem : X86VMemOperand<VR256X, "printi64mem", X86MemVY64XOperand>;
341 def vz32mem : X86VMemOperand<VR512, "printi32mem", X86MemVZ32Operand>;
342 def vz64mem : X86VMemOperand<VR512, "printi64mem", X86MemVZ64Operand>;
344 // A version of i8mem for use on x86-64 and x32 that uses a NOREX GPR instead
345 // of a plain GPR, so that it doesn't potentially require a REX prefix.
346 def ptr_rc_norex : PointerLikeRegClass<2>;
347 def ptr_rc_norex_nosp : PointerLikeRegClass<3>;
349 def i8mem_NOREX : Operand<iPTR> {
350 let PrintMethod = "printi8mem";
351 let MIOperandInfo = (ops ptr_rc_norex, i8imm, ptr_rc_norex_nosp, i32imm, i8imm);
352 let ParserMatchClass = X86Mem8AsmOperand;
353 let OperandType = "OPERAND_MEMORY";
356 // GPRs available for tailcall.
357 // It represents GR32_TC, GR64_TC or GR64_TCW64.
358 def ptr_rc_tailcall : PointerLikeRegClass<4>;
360 // Special i32mem for addresses of load folding tail calls. These are not
361 // allowed to use callee-saved registers since they must be scheduled
362 // after callee-saved register are popped.
363 def i32mem_TC : Operand<i32> {
364 let PrintMethod = "printi32mem";
365 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
367 let ParserMatchClass = X86Mem32AsmOperand;
368 let OperandType = "OPERAND_MEMORY";
371 // Special i64mem for addresses of load folding tail calls. These are not
372 // allowed to use callee-saved registers since they must be scheduled
373 // after callee-saved register are popped.
374 def i64mem_TC : Operand<i64> {
375 let PrintMethod = "printi64mem";
376 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
377 ptr_rc_tailcall, i32imm, i8imm);
378 let ParserMatchClass = X86Mem64AsmOperand;
379 let OperandType = "OPERAND_MEMORY";
382 let OperandType = "OPERAND_PCREL",
383 ParserMatchClass = X86AbsMemAsmOperand,
384 PrintMethod = "printPCRelImm" in {
385 def i32imm_pcrel : Operand<i32>;
386 def i16imm_pcrel : Operand<i16>;
388 // Branch targets have OtherVT type and print as pc-relative values.
389 def brtarget : Operand<OtherVT>;
390 def brtarget8 : Operand<OtherVT>;
394 // Special parser to detect 16-bit mode to select 16-bit displacement.
395 def X86AbsMem16AsmOperand : AsmOperandClass {
396 let Name = "AbsMem16";
397 let RenderMethod = "addAbsMemOperands";
398 let SuperClasses = [X86AbsMemAsmOperand];
401 // Branch targets have OtherVT type and print as pc-relative values.
402 let OperandType = "OPERAND_PCREL",
403 PrintMethod = "printPCRelImm" in {
404 let ParserMatchClass = X86AbsMem16AsmOperand in
405 def brtarget16 : Operand<OtherVT>;
406 let ParserMatchClass = X86AbsMemAsmOperand in
407 def brtarget32 : Operand<OtherVT>;
410 let RenderMethod = "addSrcIdxOperands" in {
411 def X86SrcIdx8Operand : AsmOperandClass {
412 let Name = "SrcIdx8";
413 let SuperClasses = [X86Mem8AsmOperand];
415 def X86SrcIdx16Operand : AsmOperandClass {
416 let Name = "SrcIdx16";
417 let SuperClasses = [X86Mem16AsmOperand];
419 def X86SrcIdx32Operand : AsmOperandClass {
420 let Name = "SrcIdx32";
421 let SuperClasses = [X86Mem32AsmOperand];
423 def X86SrcIdx64Operand : AsmOperandClass {
424 let Name = "SrcIdx64";
425 let SuperClasses = [X86Mem64AsmOperand];
427 } // RenderMethod = "addSrcIdxOperands"
429 let RenderMethod = "addDstIdxOperands" in {
430 def X86DstIdx8Operand : AsmOperandClass {
431 let Name = "DstIdx8";
432 let SuperClasses = [X86Mem8AsmOperand];
434 def X86DstIdx16Operand : AsmOperandClass {
435 let Name = "DstIdx16";
436 let SuperClasses = [X86Mem16AsmOperand];
438 def X86DstIdx32Operand : AsmOperandClass {
439 let Name = "DstIdx32";
440 let SuperClasses = [X86Mem32AsmOperand];
442 def X86DstIdx64Operand : AsmOperandClass {
443 let Name = "DstIdx64";
444 let SuperClasses = [X86Mem64AsmOperand];
446 } // RenderMethod = "addDstIdxOperands"
448 let RenderMethod = "addMemOffsOperands" in {
449 def X86MemOffs16_8AsmOperand : AsmOperandClass {
450 let Name = "MemOffs16_8";
451 let SuperClasses = [X86Mem8AsmOperand];
453 def X86MemOffs16_16AsmOperand : AsmOperandClass {
454 let Name = "MemOffs16_16";
455 let SuperClasses = [X86Mem16AsmOperand];
457 def X86MemOffs16_32AsmOperand : AsmOperandClass {
458 let Name = "MemOffs16_32";
459 let SuperClasses = [X86Mem32AsmOperand];
461 def X86MemOffs32_8AsmOperand : AsmOperandClass {
462 let Name = "MemOffs32_8";
463 let SuperClasses = [X86Mem8AsmOperand];
465 def X86MemOffs32_16AsmOperand : AsmOperandClass {
466 let Name = "MemOffs32_16";
467 let SuperClasses = [X86Mem16AsmOperand];
469 def X86MemOffs32_32AsmOperand : AsmOperandClass {
470 let Name = "MemOffs32_32";
471 let SuperClasses = [X86Mem32AsmOperand];
473 def X86MemOffs32_64AsmOperand : AsmOperandClass {
474 let Name = "MemOffs32_64";
475 let SuperClasses = [X86Mem64AsmOperand];
477 def X86MemOffs64_8AsmOperand : AsmOperandClass {
478 let Name = "MemOffs64_8";
479 let SuperClasses = [X86Mem8AsmOperand];
481 def X86MemOffs64_16AsmOperand : AsmOperandClass {
482 let Name = "MemOffs64_16";
483 let SuperClasses = [X86Mem16AsmOperand];
485 def X86MemOffs64_32AsmOperand : AsmOperandClass {
486 let Name = "MemOffs64_32";
487 let SuperClasses = [X86Mem32AsmOperand];
489 def X86MemOffs64_64AsmOperand : AsmOperandClass {
490 let Name = "MemOffs64_64";
491 let SuperClasses = [X86Mem64AsmOperand];
493 } // RenderMethod = "addMemOffsOperands"
495 class X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
496 : X86MemOperand<printMethod, parserMatchClass> {
497 let MIOperandInfo = (ops ptr_rc, i8imm);
500 class X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
501 : X86MemOperand<printMethod, parserMatchClass> {
502 let MIOperandInfo = (ops ptr_rc);
505 def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>;
506 def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>;
507 def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>;
508 def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>;
509 def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>;
510 def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>;
511 def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>;
512 def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>;
514 class X86MemOffsOperand<Operand immOperand, string printMethod,
515 AsmOperandClass parserMatchClass>
516 : X86MemOperand<printMethod, parserMatchClass> {
517 let MIOperandInfo = (ops immOperand, i8imm);
520 def offset16_8 : X86MemOffsOperand<i16imm, "printMemOffs8",
521 X86MemOffs16_8AsmOperand>;
522 def offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16",
523 X86MemOffs16_16AsmOperand>;
524 def offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32",
525 X86MemOffs16_32AsmOperand>;
526 def offset32_8 : X86MemOffsOperand<i32imm, "printMemOffs8",
527 X86MemOffs32_8AsmOperand>;
528 def offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16",
529 X86MemOffs32_16AsmOperand>;
530 def offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32",
531 X86MemOffs32_32AsmOperand>;
532 def offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64",
533 X86MemOffs32_64AsmOperand>;
534 def offset64_8 : X86MemOffsOperand<i64imm, "printMemOffs8",
535 X86MemOffs64_8AsmOperand>;
536 def offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16",
537 X86MemOffs64_16AsmOperand>;
538 def offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32",
539 X86MemOffs64_32AsmOperand>;
540 def offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64",
541 X86MemOffs64_64AsmOperand>;
543 def SSECC : Operand<i8> {
544 let PrintMethod = "printSSEAVXCC";
545 let OperandType = "OPERAND_IMMEDIATE";
548 def i8immZExt3 : ImmLeaf<i8, [{
549 return Imm >= 0 && Imm < 8;
552 def AVXCC : Operand<i8> {
553 let PrintMethod = "printSSEAVXCC";
554 let OperandType = "OPERAND_IMMEDIATE";
557 def i8immZExt5 : ImmLeaf<i8, [{
558 return Imm >= 0 && Imm < 32;
561 def AVX512ICC : Operand<i8> {
562 let PrintMethod = "printSSEAVXCC";
563 let OperandType = "OPERAND_IMMEDIATE";
566 def XOPCC : Operand<i8> {
567 let PrintMethod = "printXOPCC";
568 let OperandType = "OPERAND_IMMEDIATE";
571 class ImmSExtAsmOperandClass : AsmOperandClass {
572 let SuperClasses = [ImmAsmOperand];
573 let RenderMethod = "addImmOperands";
576 def X86GR32orGR64AsmOperand : AsmOperandClass {
577 let Name = "GR32orGR64";
580 def GR32orGR64 : RegisterOperand<GR32> {
581 let ParserMatchClass = X86GR32orGR64AsmOperand;
583 def AVX512RCOperand : AsmOperandClass {
584 let Name = "AVX512RC";
586 def AVX512RC : Operand<i32> {
587 let PrintMethod = "printRoundingControl";
588 let OperandType = "OPERAND_IMMEDIATE";
589 let ParserMatchClass = AVX512RCOperand;
592 // Sign-extended immediate classes. We don't need to define the full lattice
593 // here because there is no instruction with an ambiguity between ImmSExti64i32
596 // The strange ranges come from the fact that the assembler always works with
597 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
598 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
601 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
602 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
603 let Name = "ImmSExti64i32";
606 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
607 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
608 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
609 let Name = "ImmSExti16i8";
610 let SuperClasses = [ImmSExti64i32AsmOperand];
613 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
614 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
615 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
616 let Name = "ImmSExti32i8";
620 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
621 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
622 let Name = "ImmSExti64i8";
623 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
624 ImmSExti64i32AsmOperand];
627 // Unsigned immediate used by SSE/AVX instructions
629 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
630 def ImmUnsignedi8AsmOperand : AsmOperandClass {
631 let Name = "ImmUnsignedi8";
632 let RenderMethod = "addImmOperands";
635 // A couple of more descriptive operand definitions.
636 // 16-bits but only 8 bits are significant.
637 def i16i8imm : Operand<i16> {
638 let ParserMatchClass = ImmSExti16i8AsmOperand;
639 let OperandType = "OPERAND_IMMEDIATE";
641 // 32-bits but only 8 bits are significant.
642 def i32i8imm : Operand<i32> {
643 let ParserMatchClass = ImmSExti32i8AsmOperand;
644 let OperandType = "OPERAND_IMMEDIATE";
647 // 64-bits but only 32 bits are significant.
648 def i64i32imm : Operand<i64> {
649 let ParserMatchClass = ImmSExti64i32AsmOperand;
650 let OperandType = "OPERAND_IMMEDIATE";
653 // 64-bits but only 8 bits are significant.
654 def i64i8imm : Operand<i64> {
655 let ParserMatchClass = ImmSExti64i8AsmOperand;
656 let OperandType = "OPERAND_IMMEDIATE";
659 // Unsigned 8-bit immediate used by SSE/AVX instructions.
660 def u8imm : Operand<i8> {
661 let PrintMethod = "printU8Imm";
662 let ParserMatchClass = ImmUnsignedi8AsmOperand;
663 let OperandType = "OPERAND_IMMEDIATE";
666 // 32-bit immediate but only 8-bits are significant and they are unsigned.
667 // Used by some SSE/AVX instructions that use intrinsics.
668 def i32u8imm : Operand<i32> {
669 let PrintMethod = "printU8Imm";
670 let ParserMatchClass = ImmUnsignedi8AsmOperand;
671 let OperandType = "OPERAND_IMMEDIATE";
674 // 64-bits but only 32 bits are significant, and those bits are treated as being
676 def i64i32imm_pcrel : Operand<i64> {
677 let PrintMethod = "printPCRelImm";
678 let ParserMatchClass = X86AbsMemAsmOperand;
679 let OperandType = "OPERAND_PCREL";
682 def lea64_32mem : Operand<i32> {
683 let PrintMethod = "printanymem";
684 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
685 let ParserMatchClass = X86MemAsmOperand;
688 // Memory operands that use 64-bit pointers in both ILP32 and LP64.
689 def lea64mem : Operand<i64> {
690 let PrintMethod = "printanymem";
691 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
692 let ParserMatchClass = X86MemAsmOperand;
696 //===----------------------------------------------------------------------===//
697 // X86 Complex Pattern Definitions.
700 // Define X86-specific addressing mode.
701 def addr : ComplexPattern<iPTR, 5, "selectAddr", [], [SDNPWantParent]>;
702 def lea32addr : ComplexPattern<i32, 5, "selectLEAAddr",
703 [add, sub, mul, X86mul_imm, shl, or, frameindex],
705 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
706 def lea64_32addr : ComplexPattern<i32, 5, "selectLEA64_32Addr",
707 [add, sub, mul, X86mul_imm, shl, or,
708 frameindex, X86WrapperRIP],
711 def tls32addr : ComplexPattern<i32, 5, "selectTLSADDRAddr",
712 [tglobaltlsaddr], []>;
714 def tls32baseaddr : ComplexPattern<i32, 5, "selectTLSADDRAddr",
715 [tglobaltlsaddr], []>;
717 def lea64addr : ComplexPattern<i64, 5, "selectLEAAddr",
718 [add, sub, mul, X86mul_imm, shl, or, frameindex,
721 def tls64addr : ComplexPattern<i64, 5, "selectTLSADDRAddr",
722 [tglobaltlsaddr], []>;
724 def tls64baseaddr : ComplexPattern<i64, 5, "selectTLSADDRAddr",
725 [tglobaltlsaddr], []>;
727 def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr", [],[SDNPWantParent]>;
729 //===----------------------------------------------------------------------===//
730 // X86 Instruction Predicate Definitions.
731 def HasCMov : Predicate<"Subtarget->hasCMov()">;
732 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
734 def HasMMX : Predicate<"Subtarget->hasMMX()">;
735 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
736 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
737 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
738 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
739 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
740 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
741 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
742 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
743 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
744 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
745 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
746 def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">;
747 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
748 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
749 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
750 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
751 def HasAVX : Predicate<"Subtarget->hasAVX()">;
752 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
753 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
754 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">,
755 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">;
756 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
757 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
758 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
759 def HasCDI : Predicate<"Subtarget->hasCDI()">,
760 AssemblerPredicate<"FeatureCDI", "AVX-512 CD ISA">;
761 def HasPFI : Predicate<"Subtarget->hasPFI()">,
762 AssemblerPredicate<"FeaturePFI", "AVX-512 PF ISA">;
763 def HasERI : Predicate<"Subtarget->hasERI()">,
764 AssemblerPredicate<"FeatureERI", "AVX-512 ER ISA">;
765 def HasDQI : Predicate<"Subtarget->hasDQI()">,
766 AssemblerPredicate<"FeatureDQI", "AVX-512 DQ ISA">;
767 def NoDQI : Predicate<"!Subtarget->hasDQI()">;
768 def HasBWI : Predicate<"Subtarget->hasBWI()">,
769 AssemblerPredicate<"FeatureBWI", "AVX-512 BW ISA">;
770 def NoBWI : Predicate<"!Subtarget->hasBWI()">;
771 def HasVLX : Predicate<"Subtarget->hasVLX()">,
772 AssemblerPredicate<"FeatureVLX", "AVX-512 VL ISA">;
773 def NoVLX : Predicate<"!Subtarget->hasVLX()">;
774 def NoVLX_Or_NoBWI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasBWI()">;
775 def NoVLX_Or_NoDQI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasDQI()">;
776 def PKU : Predicate<"!Subtarget->hasPKU()">;
778 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
779 def HasAES : Predicate<"Subtarget->hasAES()">;
780 def HasFXSR : Predicate<"Subtarget->hasFXSR()">;
781 def HasXSAVE : Predicate<"Subtarget->hasXSAVE()">;
782 def HasXSAVEOPT : Predicate<"Subtarget->hasXSAVEOPT()">;
783 def HasXSAVEC : Predicate<"Subtarget->hasXSAVEC()">;
784 def HasXSAVES : Predicate<"Subtarget->hasXSAVES()">;
785 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
786 def HasFMA : Predicate<"Subtarget->hasFMA()">;
787 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">;
788 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
789 def HasXOP : Predicate<"Subtarget->hasXOP()">;
790 def HasTBM : Predicate<"Subtarget->hasTBM()">;
791 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
792 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
793 def HasF16C : Predicate<"Subtarget->hasF16C()">;
794 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
795 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
796 def HasBMI : Predicate<"Subtarget->hasBMI()">;
797 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
798 def HasRTM : Predicate<"Subtarget->hasRTM()">;
799 def HasHLE : Predicate<"Subtarget->hasHLE()">;
800 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
801 def HasADX : Predicate<"Subtarget->hasADX()">;
802 def HasSHA : Predicate<"Subtarget->hasSHA()">;
803 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
804 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
805 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
806 def HasLAHFSAHF : Predicate<"Subtarget->hasLAHFSAHF()">;
807 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
808 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
809 def HasMPX : Predicate<"Subtarget->hasMPX()">;
810 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
811 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
812 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
813 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
814 AssemblerPredicate<"Mode64Bit", "64-bit mode">;
815 def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">;
816 def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">;
817 def In16BitMode : Predicate<"Subtarget->is16Bit()">,
818 AssemblerPredicate<"Mode16Bit", "16-bit mode">;
819 def Not16BitMode : Predicate<"!Subtarget->is16Bit()">,
820 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">;
821 def In32BitMode : Predicate<"Subtarget->is32Bit()">,
822 AssemblerPredicate<"Mode32Bit", "32-bit mode">;
823 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
824 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
825 def NotWin64WithoutFP : Predicate<"!Subtarget->isTargetWin64() ||"
826 "Subtarget->getFrameLowering()->hasFP(*MF)">;
827 def IsPS4 : Predicate<"Subtarget->isTargetPS4()">;
828 def NotPS4 : Predicate<"!Subtarget->isTargetPS4()">;
829 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
830 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
831 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
832 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
833 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
834 "TM.getCodeModel() != CodeModel::Kernel">;
835 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
836 "TM.getCodeModel() == CodeModel::Kernel">;
837 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
838 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
839 def OptForSize : Predicate<"OptForSize">;
840 def OptForMinSize : Predicate<"OptForMinSize">;
841 def OptForSpeed : Predicate<"!OptForSize">;
842 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
843 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
844 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
845 def NotSlowIncDec : Predicate<"!Subtarget->slowIncDec()">;
846 def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">;
848 //===----------------------------------------------------------------------===//
849 // X86 Instruction Format Definitions.
852 include "X86InstrFormats.td"
854 //===----------------------------------------------------------------------===//
855 // Pattern fragments.
858 // X86 specific condition code. These correspond to CondCode in
859 // X86InstrInfo.h. They must be kept in synch.
860 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
861 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
862 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
863 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
864 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
865 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
866 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
867 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
868 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
869 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
870 def X86_COND_NO : PatLeaf<(i8 10)>;
871 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
872 def X86_COND_NS : PatLeaf<(i8 12)>;
873 def X86_COND_O : PatLeaf<(i8 13)>;
874 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
875 def X86_COND_S : PatLeaf<(i8 15)>;
877 // Predicate used to help when pattern matching LZCNT/TZCNT.
878 def X86_COND_E_OR_NE : ImmLeaf<i8, [{
879 return (Imm == X86::COND_E) || (Imm == X86::COND_NE);
883 def i16immSExt8 : ImmLeaf<i16, [{ return isInt<8>(Imm); }]>;
884 def i32immSExt8 : ImmLeaf<i32, [{ return isInt<8>(Imm); }]>;
885 def i64immSExt8 : ImmLeaf<i64, [{ return isInt<8>(Imm); }]>;
887 // If we have multiple users of an immediate, it's much smaller to reuse
888 // the register, rather than encode the immediate in every instruction.
889 // This has the risk of increasing register pressure from stretched live
890 // ranges, however, the immediates should be trivial to rematerialize by
891 // the RA in the event of high register pressure.
892 // TODO : This is currently enabled for stores and binary ops. There are more
893 // cases for which this can be enabled, though this catches the bulk of the
895 // TODO2 : This should really also be enabled under O2, but there's currently
896 // an issue with RA where we don't pull the constants into their users
897 // when we rematerialize them. I'll follow-up on enabling O2 after we fix that
899 // TODO3 : This is currently limited to single basic blocks (DAG creation
900 // pulls block immediates to the top and merges them if necessary).
901 // Eventually, it would be nice to allow ConstantHoisting to merge constants
902 // globally for potentially added savings.
904 def imm8_su : PatLeaf<(i8 imm), [{
905 return !shouldAvoidImmediateInstFormsForSize(N);
907 def imm16_su : PatLeaf<(i16 imm), [{
908 return !shouldAvoidImmediateInstFormsForSize(N);
910 def imm32_su : PatLeaf<(i32 imm), [{
911 return !shouldAvoidImmediateInstFormsForSize(N);
914 def i16immSExt8_su : PatLeaf<(i16immSExt8), [{
915 return !shouldAvoidImmediateInstFormsForSize(N);
917 def i32immSExt8_su : PatLeaf<(i32immSExt8), [{
918 return !shouldAvoidImmediateInstFormsForSize(N);
922 def i64immSExt32 : ImmLeaf<i64, [{ return isInt<32>(Imm); }]>;
925 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
927 def i64immZExt32 : ImmLeaf<i64, [{ return isUInt<32>(Imm); }]>;
929 def i64immZExt32SExt8 : ImmLeaf<i64, [{
930 return isUInt<32>(Imm) && isInt<8>(static_cast<int32_t>(Imm));
933 // Helper fragments for loads.
934 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
935 // known to be 32-bit aligned or better. Ditto for i8 to i16.
936 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
937 LoadSDNode *LD = cast<LoadSDNode>(N);
938 ISD::LoadExtType ExtType = LD->getExtensionType();
939 if (ExtType == ISD::NON_EXTLOAD)
941 if (ExtType == ISD::EXTLOAD)
942 return LD->getAlignment() >= 2 && !LD->isVolatile();
946 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
947 LoadSDNode *LD = cast<LoadSDNode>(N);
948 ISD::LoadExtType ExtType = LD->getExtensionType();
949 if (ExtType == ISD::EXTLOAD)
950 return LD->getAlignment() >= 2 && !LD->isVolatile();
954 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
955 LoadSDNode *LD = cast<LoadSDNode>(N);
956 ISD::LoadExtType ExtType = LD->getExtensionType();
957 if (ExtType == ISD::NON_EXTLOAD)
959 if (ExtType == ISD::EXTLOAD)
960 return LD->getAlignment() >= 4 && !LD->isVolatile();
964 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
965 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
966 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
967 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
968 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
969 def loadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr))>;
971 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
972 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
973 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
974 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
975 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
976 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
978 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
979 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
980 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
981 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
982 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
983 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
984 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
985 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
986 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
987 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
989 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
990 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
991 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
992 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
993 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
994 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
995 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
996 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
997 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
998 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
1001 // An 'and' node with a single use.
1002 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
1003 return N->hasOneUse();
1005 // An 'srl' node with a single use.
1006 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
1007 return N->hasOneUse();
1009 // An 'trunc' node with a single use.
1010 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
1011 return N->hasOneUse();
1014 //===----------------------------------------------------------------------===//
1015 // Instruction list.
1019 let hasSideEffects = 0, SchedRW = [WriteZero] in {
1020 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
1021 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero),
1022 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
1023 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero),
1024 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
1028 // Constructing a stack frame.
1029 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
1030 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
1032 let SchedRW = [WriteALU] in {
1033 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in
1034 def LEAVE : I<0xC9, RawFrm,
1035 (outs), (ins), "leave", [], IIC_LEAVE>,
1036 Requires<[Not64BitMode]>;
1038 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in
1039 def LEAVE64 : I<0xC9, RawFrm,
1040 (outs), (ins), "leave", [], IIC_LEAVE>,
1041 Requires<[In64BitMode]>;
1044 //===----------------------------------------------------------------------===//
1045 // Miscellaneous Instructions.
1048 let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in {
1049 let mayLoad = 1, SchedRW = [WriteLoad] in {
1050 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
1051 IIC_POP_REG16>, OpSize16;
1052 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
1053 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
1054 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
1055 IIC_POP_REG>, OpSize16;
1056 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
1057 IIC_POP_MEM>, OpSize16;
1058 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
1059 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
1060 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
1061 IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>;
1062 } // mayLoad, SchedRW
1064 let mayStore = 1, SchedRW = [WriteStore] in {
1065 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
1066 IIC_PUSH_REG>, OpSize16;
1067 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1068 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
1069 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
1070 IIC_PUSH_REG>, OpSize16;
1071 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1072 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
1074 def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
1075 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16;
1076 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1077 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16;
1079 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
1080 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1081 Requires<[Not64BitMode]>;
1082 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
1083 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1084 Requires<[Not64BitMode]>;
1085 } // mayStore, SchedRW
1087 let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in {
1088 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
1089 IIC_PUSH_MEM>, OpSize16;
1090 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
1091 IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;
1092 } // mayLoad, mayStore, SchedRW
1096 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
1097 SchedRW = [WriteLoad] in {
1098 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>,
1100 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
1101 OpSize32, Requires<[Not64BitMode]>;
1104 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0,
1105 SchedRW = [WriteStore] in {
1106 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
1108 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
1109 OpSize32, Requires<[Not64BitMode]>;
1112 let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in {
1113 let mayLoad = 1, SchedRW = [WriteLoad] in {
1114 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1115 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1116 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1117 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1118 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [],
1119 IIC_POP_MEM>, OpSize32, Requires<[In64BitMode]>;
1120 } // mayLoad, SchedRW
1121 let mayStore = 1, SchedRW = [WriteStore] in {
1122 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1123 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1124 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1125 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1126 } // mayStore, SchedRW
1127 let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in {
1128 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
1129 IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>;
1130 } // mayLoad, mayStore, SchedRW
1133 let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,
1134 SchedRW = [WriteStore] in {
1135 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
1136 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
1137 def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
1138 "push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1139 Requires<[In64BitMode]>;
1142 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
1143 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
1144 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>;
1145 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in
1146 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
1147 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>;
1149 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
1150 mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in {
1151 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>,
1152 OpSize32, Requires<[Not64BitMode]>;
1153 def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>,
1154 OpSize16, Requires<[Not64BitMode]>;
1156 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
1157 mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
1158 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>,
1159 OpSize32, Requires<[Not64BitMode]>;
1160 def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>,
1161 OpSize16, Requires<[Not64BitMode]>;
1164 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
1165 // GR32 = bswap GR32
1166 def BSWAP32r : I<0xC8, AddRegFrm,
1167 (outs GR32:$dst), (ins GR32:$src),
1169 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB;
1171 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
1173 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
1174 } // Constraints = "$src = $dst", SchedRW
1176 // Bit scan instructions.
1177 let Defs = [EFLAGS] in {
1178 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1179 "bsf{w}\t{$src, $dst|$dst, $src}",
1180 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
1181 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1182 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1183 "bsf{w}\t{$src, $dst|$dst, $src}",
1184 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
1185 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1186 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1187 "bsf{l}\t{$src, $dst|$dst, $src}",
1188 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
1189 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1190 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1191 "bsf{l}\t{$src, $dst|$dst, $src}",
1192 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
1193 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1194 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1195 "bsf{q}\t{$src, $dst|$dst, $src}",
1196 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
1197 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1198 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1199 "bsf{q}\t{$src, $dst|$dst, $src}",
1200 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
1201 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1203 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1204 "bsr{w}\t{$src, $dst|$dst, $src}",
1205 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))],
1206 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1207 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1208 "bsr{w}\t{$src, $dst|$dst, $src}",
1209 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
1210 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1211 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1212 "bsr{l}\t{$src, $dst|$dst, $src}",
1213 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
1214 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1215 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1216 "bsr{l}\t{$src, $dst|$dst, $src}",
1217 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
1218 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1219 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1220 "bsr{q}\t{$src, $dst|$dst, $src}",
1221 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))],
1222 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1223 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1224 "bsr{q}\t{$src, $dst|$dst, $src}",
1225 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
1226 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1227 } // Defs = [EFLAGS]
1229 let SchedRW = [WriteMicrocoded] in {
1230 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1231 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
1232 def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src),
1233 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1234 def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src),
1235 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16;
1236 def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src),
1237 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32;
1238 def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src),
1239 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1242 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1243 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
1244 def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins),
1245 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>;
1246 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
1247 def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins),
1248 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16;
1249 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
1250 def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins),
1251 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32;
1252 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
1253 def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins),
1254 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>;
1256 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1257 let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in
1258 def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst),
1259 "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>;
1260 let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in
1261 def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst),
1262 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16;
1263 let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in
1264 def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst),
1265 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32;
1266 let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in
1267 def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst),
1268 "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>;
1270 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1271 let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in {
1272 def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
1273 "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1274 def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
1275 "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16;
1276 def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src),
1277 "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32;
1278 def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src),
1279 "cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1283 //===----------------------------------------------------------------------===//
1284 // Move Instructions.
1286 let SchedRW = [WriteMove] in {
1287 let hasSideEffects = 0 in {
1288 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1289 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1290 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1291 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1292 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1293 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1294 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1295 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1298 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1299 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1300 "mov{b}\t{$src, $dst|$dst, $src}",
1301 [(set GR8:$dst, imm:$src)], IIC_MOV>;
1302 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1303 "mov{w}\t{$src, $dst|$dst, $src}",
1304 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16;
1305 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1306 "mov{l}\t{$src, $dst|$dst, $src}",
1307 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize32;
1308 def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1309 "mov{q}\t{$src, $dst|$dst, $src}",
1310 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
1312 let isReMaterializable = 1 in {
1313 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1314 "movabs{q}\t{$src, $dst|$dst, $src}",
1315 [(set GR64:$dst, imm:$src)], IIC_MOV>;
1318 // Longer forms that use a ModR/M byte. Needed for disassembler
1319 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1320 def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src),
1321 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1322 def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src),
1323 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1324 def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src),
1325 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1329 let SchedRW = [WriteStore] in {
1330 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1331 "mov{b}\t{$src, $dst|$dst, $src}",
1332 [(store (i8 imm8_su:$src), addr:$dst)], IIC_MOV_MEM>;
1333 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1334 "mov{w}\t{$src, $dst|$dst, $src}",
1335 [(store (i16 imm16_su:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
1336 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1337 "mov{l}\t{$src, $dst|$dst, $src}",
1338 [(store (i32 imm32_su:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32;
1339 def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1340 "mov{q}\t{$src, $dst|$dst, $src}",
1341 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1344 let hasSideEffects = 0 in {
1346 /// Memory offset versions of moves. The immediate is an address mode sized
1347 /// offset from the segment base.
1348 let SchedRW = [WriteALU] in {
1349 let mayLoad = 1 in {
1351 def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src),
1352 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1355 def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src),
1356 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1359 def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src),
1360 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1363 def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src),
1364 "mov{q}\t{$src, %rax|rax, $src}", [], IIC_MOV_MEM>,
1368 def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src),
1369 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, AdSize16;
1371 def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src),
1372 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1375 def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src),
1376 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1379 let mayStore = 1 in {
1381 def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs offset32_8:$dst), (ins),
1382 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize32;
1384 def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_16:$dst), (ins),
1385 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1388 def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_32:$dst), (ins),
1389 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1392 def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs offset32_64:$dst), (ins),
1393 "mov{q}\t{%rax, $dst|$dst, rax}", [], IIC_MOV_MEM>,
1397 def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs offset16_8:$dst), (ins),
1398 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize16;
1400 def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_16:$dst), (ins),
1401 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1404 def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_32:$dst), (ins),
1405 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1410 // These forms all have full 64-bit absolute addresses in their instructions
1411 // and use the movabs mnemonic to indicate this specific form.
1412 let mayLoad = 1 in {
1414 def MOV8ao64 : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src),
1415 "movabs{b}\t{$src, %al|al, $src}", []>, AdSize64;
1417 def MOV16ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src),
1418 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16, AdSize64;
1420 def MOV32ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src),
1421 "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32,
1424 def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src),
1425 "movabs{q}\t{$src, %rax|rax, $src}", []>, AdSize64;
1428 let mayStore = 1 in {
1430 def MOV8o64a : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset64_8:$dst), (ins),
1431 "movabs{b}\t{%al, $dst|$dst, al}", []>, AdSize64;
1433 def MOV16o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_16:$dst), (ins),
1434 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, AdSize64;
1436 def MOV32o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_32:$dst), (ins),
1437 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32,
1440 def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs offset64_64:$dst), (ins),
1441 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, AdSize64;
1443 } // hasSideEffects = 0
1445 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1446 SchedRW = [WriteMove] in {
1447 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1448 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1449 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1450 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1451 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1452 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1453 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1454 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1457 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1458 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1459 "mov{b}\t{$src, $dst|$dst, $src}",
1460 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1461 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1462 "mov{w}\t{$src, $dst|$dst, $src}",
1463 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16;
1464 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1465 "mov{l}\t{$src, $dst|$dst, $src}",
1466 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32;
1467 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1468 "mov{q}\t{$src, $dst|$dst, $src}",
1469 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1472 let SchedRW = [WriteStore] in {
1473 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1474 "mov{b}\t{$src, $dst|$dst, $src}",
1475 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1476 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1477 "mov{w}\t{$src, $dst|$dst, $src}",
1478 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
1479 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1480 "mov{l}\t{$src, $dst|$dst, $src}",
1481 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32;
1482 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1483 "mov{q}\t{$src, $dst|$dst, $src}",
1484 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1487 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1488 // that they can be used for copying and storing h registers, which can't be
1489 // encoded when a REX prefix is present.
1490 let isCodeGenOnly = 1 in {
1491 let hasSideEffects = 0 in
1492 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1493 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1494 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
1496 let mayStore = 1, hasSideEffects = 0 in
1497 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1498 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1499 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1500 IIC_MOV_MEM>, Sched<[WriteStore]>;
1501 let mayLoad = 1, hasSideEffects = 0,
1502 canFoldAsLoad = 1, isReMaterializable = 1 in
1503 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1504 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1505 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1506 IIC_MOV_MEM>, Sched<[WriteLoad]>;
1510 // Condition code ops, incl. set if equal/not equal/...
1511 let SchedRW = [WriteALU] in {
1512 let Defs = [EFLAGS], Uses = [AH] in
1513 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1514 [(set EFLAGS, (X86sahf AH))], IIC_AHF>,
1515 Requires<[HasLAHFSAHF]>;
1516 let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in
1517 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1518 IIC_AHF>, // AH = flags
1519 Requires<[HasLAHFSAHF]>;
1522 //===----------------------------------------------------------------------===//
1523 // Bit tests instructions: BT, BTS, BTR, BTC.
1525 let Defs = [EFLAGS] in {
1526 let SchedRW = [WriteALU] in {
1527 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1528 "bt{w}\t{$src2, $src1|$src1, $src2}",
1529 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1531 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1532 "bt{l}\t{$src2, $src1|$src1, $src2}",
1533 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
1535 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1536 "bt{q}\t{$src2, $src1|$src1, $src2}",
1537 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1540 // Unlike with the register+register form, the memory+register form of the
1541 // bt instruction does not ignore the high bits of the index. From ISel's
1542 // perspective, this is pretty bizarre. Make these instructions disassembly
1545 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
1546 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1547 "bt{w}\t{$src2, $src1|$src1, $src2}",
1548 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1549 // (implicit EFLAGS)]
1551 >, OpSize16, TB, Requires<[FastBTMem]>;
1552 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1553 "bt{l}\t{$src2, $src1|$src1, $src2}",
1554 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1555 // (implicit EFLAGS)]
1557 >, OpSize32, TB, Requires<[FastBTMem]>;
1558 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1559 "bt{q}\t{$src2, $src1|$src1, $src2}",
1560 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1561 // (implicit EFLAGS)]
1566 let SchedRW = [WriteALU] in {
1567 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1568 "bt{w}\t{$src2, $src1|$src1, $src2}",
1569 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1570 IIC_BT_RI>, OpSize16, TB;
1571 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1572 "bt{l}\t{$src2, $src1|$src1, $src2}",
1573 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1574 IIC_BT_RI>, OpSize32, TB;
1575 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1576 "bt{q}\t{$src2, $src1|$src1, $src2}",
1577 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1581 // Note that these instructions don't need FastBTMem because that
1582 // only applies when the other operand is in a register. When it's
1583 // an immediate, bt is still fast.
1584 let SchedRW = [WriteALU] in {
1585 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1586 "bt{w}\t{$src2, $src1|$src1, $src2}",
1587 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1588 ], IIC_BT_MI>, OpSize16, TB;
1589 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1590 "bt{l}\t{$src2, $src1|$src1, $src2}",
1591 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1592 ], IIC_BT_MI>, OpSize32, TB;
1593 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1594 "bt{q}\t{$src2, $src1|$src1, $src2}",
1595 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1596 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1599 let hasSideEffects = 0 in {
1600 let SchedRW = [WriteALU] in {
1601 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1602 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1604 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1605 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1607 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1608 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1611 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1612 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1613 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1615 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1616 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1618 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1619 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1622 let SchedRW = [WriteALU] in {
1623 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1624 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1626 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1627 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1629 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1630 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1633 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1634 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1635 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1637 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1638 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1640 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1641 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1644 let SchedRW = [WriteALU] in {
1645 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1646 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1648 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1649 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1651 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1652 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1655 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1656 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1657 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1659 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1660 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1662 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1663 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1666 let SchedRW = [WriteALU] in {
1667 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1668 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1670 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1671 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1673 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1674 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1677 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1678 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1679 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1681 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1682 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1684 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1685 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1688 let SchedRW = [WriteALU] in {
1689 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1690 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1692 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1693 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1695 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1696 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1699 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1700 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1701 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1703 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1704 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1706 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1707 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1710 let SchedRW = [WriteALU] in {
1711 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1712 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1714 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1715 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1717 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1718 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1721 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1722 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1723 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1725 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1726 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1728 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1729 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1731 } // hasSideEffects = 0
1732 } // Defs = [EFLAGS]
1735 //===----------------------------------------------------------------------===//
1739 // Atomic swap. These are just normal xchg instructions. But since a memory
1740 // operand is referenced, the atomicity is ensured.
1741 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1742 InstrItinClass itin> {
1743 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
1744 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1745 (ins GR8:$val, i8mem:$ptr),
1746 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1749 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1751 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1752 (ins GR16:$val, i16mem:$ptr),
1753 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1756 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1758 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1759 (ins GR32:$val, i32mem:$ptr),
1760 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1763 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1765 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1766 (ins GR64:$val, i64mem:$ptr),
1767 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1770 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1775 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1777 // Swap between registers.
1778 let SchedRW = [WriteALU] in {
1779 let Constraints = "$val = $dst" in {
1780 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1781 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1782 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1783 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1785 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1786 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1788 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1789 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1792 // Swap between EAX and other registers.
1793 let Uses = [AX], Defs = [AX] in
1794 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1795 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16;
1796 let Uses = [EAX], Defs = [EAX] in
1797 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1798 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1799 OpSize32, Requires<[Not64BitMode]>;
1800 let Uses = [EAX], Defs = [EAX] in
1801 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1802 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1803 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1804 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1805 OpSize32, Requires<[In64BitMode]>;
1806 let Uses = [RAX], Defs = [RAX] in
1807 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1808 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>;
1811 let SchedRW = [WriteALU] in {
1812 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1813 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1814 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1815 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1817 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1818 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1820 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1821 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1824 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1825 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1826 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1827 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1828 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1830 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1831 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1833 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1834 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1838 let SchedRW = [WriteALU] in {
1839 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1840 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1841 IIC_CMPXCHG_REG8>, TB;
1842 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1843 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1844 IIC_CMPXCHG_REG>, TB, OpSize16;
1845 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1846 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1847 IIC_CMPXCHG_REG>, TB, OpSize32;
1848 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1849 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1850 IIC_CMPXCHG_REG>, TB;
1853 let SchedRW = [WriteALULd, WriteRMW] in {
1854 let mayLoad = 1, mayStore = 1 in {
1855 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1856 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1857 IIC_CMPXCHG_MEM8>, TB;
1858 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1859 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1860 IIC_CMPXCHG_MEM>, TB, OpSize16;
1861 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1862 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1863 IIC_CMPXCHG_MEM>, TB, OpSize32;
1864 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1865 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1866 IIC_CMPXCHG_MEM>, TB;
1869 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1870 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1871 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1873 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1874 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1875 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1876 TB, Requires<[HasCmpxchg16b]>;
1880 // Lock instruction prefix
1881 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1883 // Rex64 instruction prefix
1884 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>,
1885 Requires<[In64BitMode]>;
1887 // Data16 instruction prefix
1888 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1890 // Repeat string operation instruction prefixes
1891 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1892 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1893 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1894 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1895 // Repeat while not equal (used with CMPS and SCAS)
1896 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1900 // String manipulation instructions
1901 let SchedRW = [WriteMicrocoded] in {
1902 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1903 let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in
1904 def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),
1905 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>;
1906 let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in
1907 def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),
1908 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16;
1909 let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in
1910 def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),
1911 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32;
1912 let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in
1913 def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
1914 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>;
1917 let SchedRW = [WriteSystem] in {
1918 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1919 let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in {
1920 def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src),
1921 "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>;
1922 def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src),
1923 "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16;
1924 def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src),
1925 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32;
1928 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1929 let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in {
1930 def INSB : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
1931 "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
1932 def INSW : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
1933 "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
1934 def INSL : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
1935 "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32;
1939 // Flag instructions
1940 let SchedRW = [WriteALU] in {
1941 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1942 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1943 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1944 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1945 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1946 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1947 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1949 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1952 // Table lookup instructions
1953 let Uses = [AL,EBX], Defs = [AL], hasSideEffects = 0, mayLoad = 1 in
1954 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
1957 let SchedRW = [WriteMicrocoded] in {
1958 // ASCII Adjust After Addition
1959 let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in
1960 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1961 Requires<[Not64BitMode]>;
1963 // ASCII Adjust AX Before Division
1964 let Uses = [AX], Defs = [AX,EFLAGS], hasSideEffects = 0 in
1965 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1966 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>;
1968 // ASCII Adjust AX After Multiply
1969 let Uses = [AL], Defs = [AX,EFLAGS], hasSideEffects = 0 in
1970 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1971 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>;
1973 // ASCII Adjust AL After Subtraction - sets
1974 let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in
1975 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1976 Requires<[Not64BitMode]>;
1978 // Decimal Adjust AL after Addition
1979 let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in
1980 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1981 Requires<[Not64BitMode]>;
1983 // Decimal Adjust AL after Subtraction
1984 let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in
1985 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1986 Requires<[Not64BitMode]>;
1989 let SchedRW = [WriteSystem] in {
1990 // Check Array Index Against Bounds
1991 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1992 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
1993 Requires<[Not64BitMode]>;
1994 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1995 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize32,
1996 Requires<[Not64BitMode]>;
1998 // Adjust RPL Field of Segment Selector
1999 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
2000 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
2001 Requires<[Not64BitMode]>;
2002 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
2003 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
2004 Requires<[Not64BitMode]>;
2007 //===----------------------------------------------------------------------===//
2008 // MOVBE Instructions
2010 let Predicates = [HasMOVBE] in {
2011 let SchedRW = [WriteALULd] in {
2012 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2013 "movbe{w}\t{$src, $dst|$dst, $src}",
2014 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
2016 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2017 "movbe{l}\t{$src, $dst|$dst, $src}",
2018 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
2020 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2021 "movbe{q}\t{$src, $dst|$dst, $src}",
2022 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
2025 let SchedRW = [WriteStore] in {
2026 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
2027 "movbe{w}\t{$src, $dst|$dst, $src}",
2028 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
2030 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2031 "movbe{l}\t{$src, $dst|$dst, $src}",
2032 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
2034 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2035 "movbe{q}\t{$src, $dst|$dst, $src}",
2036 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
2041 //===----------------------------------------------------------------------===//
2042 // RDRAND Instruction
2044 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
2045 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
2047 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
2048 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
2050 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB;
2051 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
2053 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
2056 //===----------------------------------------------------------------------===//
2057 // RDSEED Instruction
2059 let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
2060 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
2062 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
2063 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
2065 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB;
2066 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
2068 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
2071 //===----------------------------------------------------------------------===//
2072 // LZCNT Instruction
2074 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
2075 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2076 "lzcnt{w}\t{$src, $dst|$dst, $src}",
2077 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
2079 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2080 "lzcnt{w}\t{$src, $dst|$dst, $src}",
2081 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
2082 (implicit EFLAGS)]>, XS, OpSize16;
2084 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2085 "lzcnt{l}\t{$src, $dst|$dst, $src}",
2086 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,
2088 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2089 "lzcnt{l}\t{$src, $dst|$dst, $src}",
2090 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
2091 (implicit EFLAGS)]>, XS, OpSize32;
2093 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2094 "lzcnt{q}\t{$src, $dst|$dst, $src}",
2095 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
2097 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2098 "lzcnt{q}\t{$src, $dst|$dst, $src}",
2099 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
2100 (implicit EFLAGS)]>, XS;
2103 let Predicates = [HasLZCNT] in {
2104 def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
2105 (X86cmp GR16:$src, (i16 0))),
2106 (LZCNT16rr GR16:$src)>;
2107 def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
2108 (X86cmp GR32:$src, (i32 0))),
2109 (LZCNT32rr GR32:$src)>;
2110 def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
2111 (X86cmp GR64:$src, (i64 0))),
2112 (LZCNT64rr GR64:$src)>;
2113 def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E_OR_NE),
2114 (X86cmp GR16:$src, (i16 0))),
2115 (LZCNT16rr GR16:$src)>;
2116 def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E_OR_NE),
2117 (X86cmp GR32:$src, (i32 0))),
2118 (LZCNT32rr GR32:$src)>;
2119 def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E_OR_NE),
2120 (X86cmp GR64:$src, (i64 0))),
2121 (LZCNT64rr GR64:$src)>;
2123 def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
2124 (X86cmp (loadi16 addr:$src), (i16 0))),
2125 (LZCNT16rm addr:$src)>;
2126 def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2127 (X86cmp (loadi32 addr:$src), (i32 0))),
2128 (LZCNT32rm addr:$src)>;
2129 def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2130 (X86cmp (loadi64 addr:$src), (i64 0))),
2131 (LZCNT64rm addr:$src)>;
2132 def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2133 (X86cmp (loadi16 addr:$src), (i16 0))),
2134 (LZCNT16rm addr:$src)>;
2135 def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2136 (X86cmp (loadi32 addr:$src), (i32 0))),
2137 (LZCNT32rm addr:$src)>;
2138 def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2139 (X86cmp (loadi64 addr:$src), (i64 0))),
2140 (LZCNT64rm addr:$src)>;
2143 //===----------------------------------------------------------------------===//
2146 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2147 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2148 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2149 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
2151 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2152 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2153 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
2154 (implicit EFLAGS)]>, XS, OpSize16;
2156 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2157 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2158 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,
2160 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2161 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2162 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
2163 (implicit EFLAGS)]>, XS, OpSize32;
2165 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2166 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2167 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
2169 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2170 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2171 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
2172 (implicit EFLAGS)]>, XS;
2175 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
2176 RegisterClass RC, X86MemOperand x86memop> {
2177 let hasSideEffects = 0 in {
2178 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
2179 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2182 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
2183 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2188 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2189 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
2190 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
2191 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
2192 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
2193 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>;
2194 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W;
2197 //===----------------------------------------------------------------------===//
2198 // Pattern fragments to auto generate BMI instructions.
2199 //===----------------------------------------------------------------------===//
2201 let Predicates = [HasBMI] in {
2202 // FIXME: patterns for the load versions are not implemented
2203 def : Pat<(and GR32:$src, (add GR32:$src, -1)),
2204 (BLSR32rr GR32:$src)>;
2205 def : Pat<(and GR64:$src, (add GR64:$src, -1)),
2206 (BLSR64rr GR64:$src)>;
2208 def : Pat<(xor GR32:$src, (add GR32:$src, -1)),
2209 (BLSMSK32rr GR32:$src)>;
2210 def : Pat<(xor GR64:$src, (add GR64:$src, -1)),
2211 (BLSMSK64rr GR64:$src)>;
2213 def : Pat<(and GR32:$src, (ineg GR32:$src)),
2214 (BLSI32rr GR32:$src)>;
2215 def : Pat<(and GR64:$src, (ineg GR64:$src)),
2216 (BLSI64rr GR64:$src)>;
2219 let Predicates = [HasBMI] in {
2220 def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
2221 (X86cmp GR16:$src, (i16 0))),
2222 (TZCNT16rr GR16:$src)>;
2223 def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
2224 (X86cmp GR32:$src, (i32 0))),
2225 (TZCNT32rr GR32:$src)>;
2226 def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
2227 (X86cmp GR64:$src, (i64 0))),
2228 (TZCNT64rr GR64:$src)>;
2229 def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E_OR_NE),
2230 (X86cmp GR16:$src, (i16 0))),
2231 (TZCNT16rr GR16:$src)>;
2232 def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E_OR_NE),
2233 (X86cmp GR32:$src, (i32 0))),
2234 (TZCNT32rr GR32:$src)>;
2235 def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E_OR_NE),
2236 (X86cmp GR64:$src, (i64 0))),
2237 (TZCNT64rr GR64:$src)>;
2239 def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
2240 (X86cmp (loadi16 addr:$src), (i16 0))),
2241 (TZCNT16rm addr:$src)>;
2242 def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2243 (X86cmp (loadi32 addr:$src), (i32 0))),
2244 (TZCNT32rm addr:$src)>;
2245 def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2246 (X86cmp (loadi64 addr:$src), (i64 0))),
2247 (TZCNT64rm addr:$src)>;
2248 def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2249 (X86cmp (loadi16 addr:$src), (i16 0))),
2250 (TZCNT16rm addr:$src)>;
2251 def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2252 (X86cmp (loadi32 addr:$src), (i32 0))),
2253 (TZCNT32rm addr:$src)>;
2254 def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2255 (X86cmp (loadi64 addr:$src), (i64 0))),
2256 (TZCNT64rm addr:$src)>;
2260 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
2261 X86MemOperand x86memop, Intrinsic Int,
2263 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2264 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2265 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
2267 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
2268 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2269 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
2270 (implicit EFLAGS)]>, T8PS, VEX_4VOp3;
2273 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2274 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
2275 int_x86_bmi_bextr_32, loadi32>;
2276 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
2277 int_x86_bmi_bextr_64, loadi64>, VEX_W;
2280 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
2281 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
2282 int_x86_bmi_bzhi_32, loadi32>;
2283 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
2284 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
2288 def CountTrailingOnes : SDNodeXForm<imm, [{
2289 // Count the trailing ones in the immediate.
2290 return getI8Imm(countTrailingOnes(N->getZExtValue()), SDLoc(N));
2293 def BZHIMask : ImmLeaf<i64, [{
2294 return isMask_64(Imm) && (countTrailingOnes<uint64_t>(Imm) > 32);
2297 let Predicates = [HasBMI2] in {
2298 def : Pat<(and GR64:$src, BZHIMask:$mask),
2299 (BZHI64rr GR64:$src,
2300 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2301 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>;
2303 def : Pat<(and GR32:$src, (add (shl 1, GR8:$lz), -1)),
2304 (BZHI32rr GR32:$src,
2305 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2307 def : Pat<(and (loadi32 addr:$src), (add (shl 1, GR8:$lz), -1)),
2308 (BZHI32rm addr:$src,
2309 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2311 def : Pat<(and GR64:$src, (add (shl 1, GR8:$lz), -1)),
2312 (BZHI64rr GR64:$src,
2313 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2315 def : Pat<(and (loadi64 addr:$src), (add (shl 1, GR8:$lz), -1)),
2316 (BZHI64rm addr:$src,
2317 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2320 let Predicates = [HasBMI] in {
2321 def : Pat<(X86bextr GR32:$src1, GR32:$src2),
2322 (BEXTR32rr GR32:$src1, GR32:$src2)>;
2323 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
2324 (BEXTR32rm addr:$src1, GR32:$src2)>;
2325 def : Pat<(X86bextr GR64:$src1, GR64:$src2),
2326 (BEXTR64rr GR64:$src1, GR64:$src2)>;
2327 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
2328 (BEXTR64rm addr:$src1, GR64:$src2)>;
2331 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
2332 X86MemOperand x86memop, Intrinsic Int,
2334 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2335 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2336 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
2338 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2339 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2340 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
2343 let Predicates = [HasBMI2] in {
2344 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
2345 int_x86_bmi_pdep_32, loadi32>, T8XD;
2346 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
2347 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
2348 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
2349 int_x86_bmi_pext_32, loadi32>, T8XS;
2350 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
2351 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
2354 //===----------------------------------------------------------------------===//
2357 let Predicates = [HasTBM], Defs = [EFLAGS] in {
2359 multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
2360 X86MemOperand x86memop, PatFrag ld_frag,
2361 Intrinsic Int, Operand immtype,
2362 SDPatternOperator immoperator> {
2363 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
2364 !strconcat(OpcodeStr,
2365 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2366 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>,
2368 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst),
2369 (ins x86memop:$src1, immtype:$cntl),
2370 !strconcat(OpcodeStr,
2371 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2372 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
2376 defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32,
2377 int_x86_tbm_bextri_u32, i32imm, imm>;
2378 let ImmT = Imm32S in
2379 defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64,
2380 int_x86_tbm_bextri_u64, i64i32imm,
2381 i64immSExt32>, VEX_W;
2383 multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
2384 RegisterClass RC, string OpcodeStr,
2385 X86MemOperand x86memop, PatFrag ld_frag> {
2386 let hasSideEffects = 0 in {
2387 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src),
2388 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2391 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src),
2392 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2397 multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
2398 Format FormReg, Format FormMem> {
2399 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem,
2401 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem,
2405 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
2406 defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>;
2407 defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>;
2408 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>;
2409 defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>;
2410 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>;
2411 defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>;
2412 defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
2413 defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
2416 //===----------------------------------------------------------------------===//
2417 // MONITORX/MWAITX Instructions
2419 let SchedRW = [WriteSystem] in {
2420 let Uses = [EAX, ECX, EDX] in
2421 def MONITORXrrr : I<0x01, MRM_FA, (outs), (ins), "monitorx", [],
2422 IIC_SSE_MONITOR>, TB;
2423 let Uses = [ECX, EAX, EBX] in
2424 def MWAITXrr : I<0x01, MRM_FB, (outs), (ins), "mwaitx", [], IIC_SSE_MWAIT>,
2428 def : InstAlias<"mwaitx\t{%eax, %ecx, %ebx|ebx, ecx, eax}", (MWAITXrr)>, Requires<[Not64BitMode]>;
2429 def : InstAlias<"mwaitx\t{%rax, %rcx, %rbx|rbx, rcx, rax}", (MWAITXrr)>, Requires<[In64BitMode]>;
2431 def : InstAlias<"monitorx\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORXrrr)>,
2432 Requires<[Not64BitMode]>;
2433 def : InstAlias<"monitorx\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORXrrr)>,
2434 Requires<[In64BitMode]>;
2436 //===----------------------------------------------------------------------===//
2437 // CLZERO Instruction
2440 def CLZEROr : I<0x01, MRM_FC, (outs), (ins), "clzero", []>, TB;
2442 //===----------------------------------------------------------------------===//
2443 // Pattern fragments to auto generate TBM instructions.
2444 //===----------------------------------------------------------------------===//
2446 let Predicates = [HasTBM] in {
2447 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)),
2448 (BEXTRI32ri GR32:$src1, imm:$src2)>;
2449 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)),
2450 (BEXTRI32mi addr:$src1, imm:$src2)>;
2451 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2),
2452 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>;
2453 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2),
2454 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>;
2456 // FIXME: patterns for the load versions are not implemented
2457 def : Pat<(and GR32:$src, (add GR32:$src, 1)),
2458 (BLCFILL32rr GR32:$src)>;
2459 def : Pat<(and GR64:$src, (add GR64:$src, 1)),
2460 (BLCFILL64rr GR64:$src)>;
2462 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
2463 (BLCI32rr GR32:$src)>;
2464 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
2465 (BLCI64rr GR64:$src)>;
2467 // Extra patterns because opt can optimize the above patterns to this.
2468 def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
2469 (BLCI32rr GR32:$src)>;
2470 def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
2471 (BLCI64rr GR64:$src)>;
2473 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
2474 (BLCIC32rr GR32:$src)>;
2475 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),
2476 (BLCIC64rr GR64:$src)>;
2478 def : Pat<(xor GR32:$src, (add GR32:$src, 1)),
2479 (BLCMSK32rr GR32:$src)>;
2480 def : Pat<(xor GR64:$src, (add GR64:$src, 1)),
2481 (BLCMSK64rr GR64:$src)>;
2483 def : Pat<(or GR32:$src, (add GR32:$src, 1)),
2484 (BLCS32rr GR32:$src)>;
2485 def : Pat<(or GR64:$src, (add GR64:$src, 1)),
2486 (BLCS64rr GR64:$src)>;
2488 def : Pat<(or GR32:$src, (add GR32:$src, -1)),
2489 (BLSFILL32rr GR32:$src)>;
2490 def : Pat<(or GR64:$src, (add GR64:$src, -1)),
2491 (BLSFILL64rr GR64:$src)>;
2493 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
2494 (BLSIC32rr GR32:$src)>;
2495 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
2496 (BLSIC64rr GR64:$src)>;
2498 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)),
2499 (T1MSKC32rr GR32:$src)>;
2500 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)),
2501 (T1MSKC64rr GR64:$src)>;
2503 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)),
2504 (TZMSK32rr GR32:$src)>;
2505 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)),
2506 (TZMSK64rr GR64:$src)>;
2509 //===----------------------------------------------------------------------===//
2510 // Memory Instructions
2513 def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2514 "clflushopt\t$src", []>, PD;
2515 def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", []>, PD;
2516 def PCOMMIT : I<0xAE, MRM_F8, (outs), (ins), "pcommit", []>, PD;
2519 //===----------------------------------------------------------------------===//
2521 //===----------------------------------------------------------------------===//
2523 include "X86InstrArithmetic.td"
2524 include "X86InstrCMovSetCC.td"
2525 include "X86InstrExtension.td"
2526 include "X86InstrControl.td"
2527 include "X86InstrShiftRotate.td"
2529 // X87 Floating Point Stack.
2530 include "X86InstrFPStack.td"
2532 // SIMD support (SSE, MMX and AVX)
2533 include "X86InstrFragmentsSIMD.td"
2535 // FMA - Fused Multiply-Add support (requires FMA)
2536 include "X86InstrFMA.td"
2539 include "X86InstrXOP.td"
2541 // SSE, MMX and 3DNow! vector support.
2542 include "X86InstrSSE.td"
2543 include "X86InstrAVX512.td"
2544 include "X86InstrMMX.td"
2545 include "X86Instr3DNow.td"
2548 include "X86InstrMPX.td"
2550 include "X86InstrVMX.td"
2551 include "X86InstrSVM.td"
2553 include "X86InstrTSX.td"
2554 include "X86InstrSGX.td"
2556 // System instructions.
2557 include "X86InstrSystem.td"
2559 // Compiler Pseudo Instructions and Pat Patterns
2560 include "X86InstrCompiler.td"
2562 //===----------------------------------------------------------------------===//
2563 // Assembler Mnemonic Aliases
2564 //===----------------------------------------------------------------------===//
2566 def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>;
2567 def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>;
2568 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
2570 def : MnemonicAlias<"cbw", "cbtw", "att">;
2571 def : MnemonicAlias<"cwde", "cwtl", "att">;
2572 def : MnemonicAlias<"cwd", "cwtd", "att">;
2573 def : MnemonicAlias<"cdq", "cltd", "att">;
2574 def : MnemonicAlias<"cdqe", "cltq", "att">;
2575 def : MnemonicAlias<"cqo", "cqto", "att">;
2577 // In 64-bit mode lret maps to lretl; it is not ambiguous with lretq.
2578 def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>;
2579 def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>;
2581 def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>;
2582 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;
2584 def : MnemonicAlias<"loopz", "loope">;
2585 def : MnemonicAlias<"loopnz", "loopne">;
2587 def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>;
2588 def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>;
2589 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;
2590 def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>;
2591 def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>;
2592 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>;
2593 def : MnemonicAlias<"popfd", "popfl", "att">;
2595 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
2596 // all modes. However: "push (addr)" and "push $42" should default to
2597 // pushl/pushq depending on the current mode. Similar for "pop %bx"
2598 def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>;
2599 def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>;
2600 def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>;
2601 def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>;
2602 def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>;
2603 def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
2604 def : MnemonicAlias<"pushfd", "pushfl", "att">;
2606 def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>;
2607 def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>;
2608 def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>;
2609 def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>;
2610 def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>;
2611 def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>;
2613 def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>;
2614 def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>;
2615 def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>;
2616 def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>;
2618 def : MnemonicAlias<"repe", "rep">;
2619 def : MnemonicAlias<"repz", "rep">;
2620 def : MnemonicAlias<"repnz", "repne">;
2622 def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>;
2623 def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>;
2624 def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>;
2626 def : MnemonicAlias<"sal", "shl", "intel">;
2627 def : MnemonicAlias<"salb", "shlb", "att">;
2628 def : MnemonicAlias<"salw", "shlw", "att">;
2629 def : MnemonicAlias<"sall", "shll", "att">;
2630 def : MnemonicAlias<"salq", "shlq", "att">;
2632 def : MnemonicAlias<"smovb", "movsb", "att">;
2633 def : MnemonicAlias<"smovw", "movsw", "att">;
2634 def : MnemonicAlias<"smovl", "movsl", "att">;
2635 def : MnemonicAlias<"smovq", "movsq", "att">;
2637 def : MnemonicAlias<"ud2a", "ud2", "att">;
2638 def : MnemonicAlias<"verrw", "verr", "att">;
2640 // System instruction aliases.
2641 def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>;
2642 def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>;
2643 def : MnemonicAlias<"sysret", "sysretl", "att">;
2644 def : MnemonicAlias<"sysexit", "sysexitl", "att">;
2646 def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>;
2647 def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>;
2648 def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>;
2649 def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>;
2650 def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>;
2651 def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>;
2652 def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>;
2653 def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>;
2654 def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>;
2655 def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>;
2656 def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>;
2657 def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>;
2660 // Floating point stack aliases.
2661 def : MnemonicAlias<"fcmovz", "fcmove", "att">;
2662 def : MnemonicAlias<"fcmova", "fcmovnbe", "att">;
2663 def : MnemonicAlias<"fcmovnae", "fcmovb", "att">;
2664 def : MnemonicAlias<"fcmovna", "fcmovbe", "att">;
2665 def : MnemonicAlias<"fcmovae", "fcmovnb", "att">;
2666 def : MnemonicAlias<"fcomip", "fcompi">;
2667 def : MnemonicAlias<"fildq", "fildll", "att">;
2668 def : MnemonicAlias<"fistpq", "fistpll", "att">;
2669 def : MnemonicAlias<"fisttpq", "fisttpll", "att">;
2670 def : MnemonicAlias<"fldcww", "fldcw", "att">;
2671 def : MnemonicAlias<"fnstcww", "fnstcw", "att">;
2672 def : MnemonicAlias<"fnstsww", "fnstsw", "att">;
2673 def : MnemonicAlias<"fucomip", "fucompi">;
2674 def : MnemonicAlias<"fwait", "wait">;
2676 def : MnemonicAlias<"fxsaveq", "fxsave64", "att">;
2677 def : MnemonicAlias<"fxrstorq", "fxrstor64", "att">;
2678 def : MnemonicAlias<"xsaveq", "xsave64", "att">;
2679 def : MnemonicAlias<"xrstorq", "xrstor64", "att">;
2680 def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">;
2681 def : MnemonicAlias<"xrstorsq", "xrstors64", "att">;
2682 def : MnemonicAlias<"xsavecq", "xsavec64", "att">;
2683 def : MnemonicAlias<"xsavesq", "xsaves64", "att">;
2685 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond,
2687 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
2688 !strconcat(Prefix, NewCond, Suffix), VariantName>;
2690 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
2691 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
2692 /// example "setz" -> "sete".
2693 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix,
2695 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb
2696 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete
2697 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe
2698 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae
2699 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae
2700 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle
2701 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge
2702 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne
2703 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp
2704 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp
2706 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb
2707 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta
2708 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl
2709 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg
2712 // Aliases for set<CC>
2713 defm : IntegerCondCodeMnemonicAlias<"set", "">;
2714 // Aliases for j<CC>
2715 defm : IntegerCondCodeMnemonicAlias<"j", "">;
2716 // Aliases for cmov<CC>{w,l,q}
2717 defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">;
2718 defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">;
2719 defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">;
2720 // No size suffix for intel-style asm.
2721 defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">;
2724 //===----------------------------------------------------------------------===//
2725 // Assembler Instruction Aliases
2726 //===----------------------------------------------------------------------===//
2728 // aad/aam default to base 10 if no operand is specified.
2729 def : InstAlias<"aad", (AAD8i8 10)>, Requires<[Not64BitMode]>;
2730 def : InstAlias<"aam", (AAM8i8 10)>, Requires<[Not64BitMode]>;
2732 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
2733 // Likewise for btc/btr/bts.
2734 def : InstAlias<"bt {$imm, $mem|$mem, $imm}",
2735 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2736 def : InstAlias<"btc {$imm, $mem|$mem, $imm}",
2737 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2738 def : InstAlias<"btr {$imm, $mem|$mem, $imm}",
2739 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2740 def : InstAlias<"bts {$imm, $mem|$mem, $imm}",
2741 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2744 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>;
2745 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>;
2746 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;
2747 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
2749 // lods aliases. Accept the destination being omitted because it's implicit
2750 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2751 // in the destination.
2752 def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>;
2753 def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>;
2754 def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>;
2755 def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2756 def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>;
2757 def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>;
2758 def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>;
2759 def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2761 // stos aliases. Accept the source being omitted because it's implicit in
2762 // the mnemonic, or the mnemonic suffix being omitted because it's implicit
2764 def : InstAlias<"stosb $dst", (STOSB dstidx8:$dst), 0>;
2765 def : InstAlias<"stosw $dst", (STOSW dstidx16:$dst), 0>;
2766 def : InstAlias<"stos{l|d} $dst", (STOSL dstidx32:$dst), 0>;
2767 def : InstAlias<"stosq $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2768 def : InstAlias<"stos {%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>;
2769 def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>;
2770 def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>;
2771 def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2773 // scas aliases. Accept the destination being omitted because it's implicit
2774 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2775 // in the destination.
2776 def : InstAlias<"scasb $dst", (SCASB dstidx8:$dst), 0>;
2777 def : InstAlias<"scasw $dst", (SCASW dstidx16:$dst), 0>;
2778 def : InstAlias<"scas{l|d} $dst", (SCASL dstidx32:$dst), 0>;
2779 def : InstAlias<"scasq $dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2780 def : InstAlias<"scas {$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>;
2781 def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>;
2782 def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>;
2783 def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2785 // div and idiv aliases for explicit A register.
2786 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
2787 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
2788 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;
2789 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;
2790 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>;
2791 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;
2792 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;
2793 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;
2794 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>;
2795 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;
2796 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;
2797 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;
2798 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>;
2799 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;
2800 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
2801 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
2805 // Various unary fpstack operations default to operating on on ST1.
2806 // For example, "fxch" -> "fxch %st(1)"
2807 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
2808 def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>;
2809 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
2810 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
2811 def : InstAlias<"fmul", (MUL_FPrST0 ST1), 0>;
2812 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
2813 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
2814 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
2815 def : InstAlias<"fxch", (XCH_F ST1), 0>;
2816 def : InstAlias<"fcom", (COM_FST0r ST1), 0>;
2817 def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>;
2818 def : InstAlias<"fcomi", (COM_FIr ST1), 0>;
2819 def : InstAlias<"fcompi", (COM_FIPr ST1), 0>;
2820 def : InstAlias<"fucom", (UCOM_Fr ST1), 0>;
2821 def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>;
2822 def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>;
2823 def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;
2825 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
2826 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
2827 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
2829 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
2830 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"),
2831 (Inst RST:$op), EmitAlias>;
2832 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"),
2833 (Inst ST0), EmitAlias>;
2836 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
2837 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
2838 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
2839 defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>;
2840 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
2841 defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>;
2842 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
2843 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
2844 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
2845 defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>;
2846 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
2847 defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>;
2848 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
2849 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
2850 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
2851 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
2854 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
2855 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
2856 // solely because gas supports it.
2857 def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
2858 def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
2859 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
2860 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
2861 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
2862 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
2864 // We accept "fnstsw %eax" even though it only writes %ax.
2865 def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>;
2866 def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>;
2867 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
2869 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
2870 // this is compatible with what GAS does.
2871 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2872 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2873 def : InstAlias<"lcall {*}$dst", (FARCALL32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2874 def : InstAlias<"ljmp {*}$dst", (FARJMP32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2875 def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2876 def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2877 def : InstAlias<"lcall {*}$dst", (FARCALL16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2878 def : InstAlias<"ljmp {*}$dst", (FARJMP16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2880 def : InstAlias<"call {*}$dst", (CALL64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2881 def : InstAlias<"jmp {*}$dst", (JMP64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2882 def : InstAlias<"call {*}$dst", (CALL32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2883 def : InstAlias<"jmp {*}$dst", (JMP32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2884 def : InstAlias<"call {*}$dst", (CALL16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2885 def : InstAlias<"jmp {*}$dst", (JMP16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2888 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
2889 def : InstAlias<"imul{w} {$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>;
2890 def : InstAlias<"imul{w} {$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>;
2891 def : InstAlias<"imul{l} {$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>;
2892 def : InstAlias<"imul{l} {$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>;
2893 def : InstAlias<"imul{q} {$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>;
2894 def : InstAlias<"imul{q} {$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>;
2896 // inb %dx -> inb %al, %dx
2897 def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
2898 def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
2899 def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;
2900 def : InstAlias<"inb\t$port", (IN8ri u8imm:$port), 0>;
2901 def : InstAlias<"inw\t$port", (IN16ri u8imm:$port), 0>;
2902 def : InstAlias<"inl\t$port", (IN32ri u8imm:$port), 0>;
2905 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
2906 def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2907 def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2908 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2909 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2910 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
2911 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
2912 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2913 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2915 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
2916 // the move. All segment/mem forms are equivalent, this has the shortest
2918 def : InstAlias<"mov {$mem, $seg|$seg, $mem}", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>;
2919 def : InstAlias<"mov {$seg, $mem|$mem, $seg}", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>;
2921 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
2922 def : InstAlias<"movq {$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>;
2924 // Match 'movq GR64, MMX' as an alias for movd.
2925 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2926 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
2927 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2928 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
2931 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
2932 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
2933 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
2934 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
2935 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
2936 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
2937 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
2940 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
2941 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
2942 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
2943 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
2944 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
2945 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
2946 // Note: No GR32->GR64 movzx form.
2948 // outb %dx -> outb %al, %dx
2949 def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;
2950 def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;
2951 def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;
2952 def : InstAlias<"outb\t$port", (OUT8ir u8imm:$port), 0>;
2953 def : InstAlias<"outw\t$port", (OUT16ir u8imm:$port), 0>;
2954 def : InstAlias<"outl\t$port", (OUT32ir u8imm:$port), 0>;
2956 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2957 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2958 // errors, since its encoding is the most compact.
2959 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>;
2961 // shld/shrd op,op -> shld op, op, CL
2962 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
2963 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;
2964 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;
2965 def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>;
2966 def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>;
2967 def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>;
2969 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;
2970 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;
2971 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;
2972 def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>;
2973 def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>;
2974 def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>;
2976 /* FIXME: This is disabled because the asm matcher is currently incapable of
2977 * matching a fixed immediate like $1.
2978 // "shl X, $1" is an alias for "shl X".
2979 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2980 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2981 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2982 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2983 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2984 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2985 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2986 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2987 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2988 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2989 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2990 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2991 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2992 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2993 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2994 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2995 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2998 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2999 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
3000 defm : ShiftRotateByOneAlias<"rol", "ROL">;
3001 defm : ShiftRotateByOneAlias<"ror", "ROR">;
3004 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
3005 def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}",
3006 (TEST8rm GR8 :$val, i8mem :$mem), 0>;
3007 def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}",
3008 (TEST16rm GR16:$val, i16mem:$mem), 0>;
3009 def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}",
3010 (TEST32rm GR32:$val, i32mem:$mem), 0>;
3011 def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}",
3012 (TEST64rm GR64:$val, i64mem:$mem), 0>;
3014 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
3015 def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}",
3016 (XCHG8rm GR8 :$val, i8mem :$mem), 0>;
3017 def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}",
3018 (XCHG16rm GR16:$val, i16mem:$mem), 0>;
3019 def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}",
3020 (XCHG32rm GR32:$val, i32mem:$mem), 0>;
3021 def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}",
3022 (XCHG64rm GR64:$val, i64mem:$mem), 0>;
3024 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
3025 def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>;
3026 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
3027 (XCHG32ar GR32:$src), 0>, Requires<[Not64BitMode]>;
3028 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
3029 (XCHG32ar64 GR32_NOAX:$src), 0>, Requires<[In64BitMode]>;
3030 def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>;
3032 // These aliases exist to get the parser to prioritize matching 8-bit
3033 // immediate encodings over matching the implicit ax/eax/rax encodings. By
3034 // explicitly mentioning the A register here, these entries will be ordered
3035 // first due to the more explicit immediate type.
3036 def : InstAlias<"adc{w}\t{$imm, %ax|ax, $imm}", (ADC16ri8 AX, i16i8imm:$imm), 0>;
3037 def : InstAlias<"add{w}\t{$imm, %ax|ax, $imm}", (ADD16ri8 AX, i16i8imm:$imm), 0>;
3038 def : InstAlias<"and{w}\t{$imm, %ax|ax, $imm}", (AND16ri8 AX, i16i8imm:$imm), 0>;
3039 def : InstAlias<"cmp{w}\t{$imm, %ax|ax, $imm}", (CMP16ri8 AX, i16i8imm:$imm), 0>;
3040 def : InstAlias<"or{w}\t{$imm, %ax|ax, $imm}", (OR16ri8 AX, i16i8imm:$imm), 0>;
3041 def : InstAlias<"sbb{w}\t{$imm, %ax|ax, $imm}", (SBB16ri8 AX, i16i8imm:$imm), 0>;
3042 def : InstAlias<"sub{w}\t{$imm, %ax|ax, $imm}", (SUB16ri8 AX, i16i8imm:$imm), 0>;
3043 def : InstAlias<"xor{w}\t{$imm, %ax|ax, $imm}", (XOR16ri8 AX, i16i8imm:$imm), 0>;
3045 def : InstAlias<"adc{l}\t{$imm, %eax|eax, $imm}", (ADC32ri8 EAX, i32i8imm:$imm), 0>;
3046 def : InstAlias<"add{l}\t{$imm, %eax|eax, $imm}", (ADD32ri8 EAX, i32i8imm:$imm), 0>;
3047 def : InstAlias<"and{l}\t{$imm, %eax|eax, $imm}", (AND32ri8 EAX, i32i8imm:$imm), 0>;
3048 def : InstAlias<"cmp{l}\t{$imm, %eax|eax, $imm}", (CMP32ri8 EAX, i32i8imm:$imm), 0>;
3049 def : InstAlias<"or{l}\t{$imm, %eax|eax, $imm}", (OR32ri8 EAX, i32i8imm:$imm), 0>;
3050 def : InstAlias<"sbb{l}\t{$imm, %eax|eax, $imm}", (SBB32ri8 EAX, i32i8imm:$imm), 0>;
3051 def : InstAlias<"sub{l}\t{$imm, %eax|eax, $imm}", (SUB32ri8 EAX, i32i8imm:$imm), 0>;
3052 def : InstAlias<"xor{l}\t{$imm, %eax|eax, $imm}", (XOR32ri8 EAX, i32i8imm:$imm), 0>;
3054 def : InstAlias<"adc{q}\t{$imm, %rax|rax, $imm}", (ADC64ri8 RAX, i64i8imm:$imm), 0>;
3055 def : InstAlias<"add{q}\t{$imm, %rax|rax, $imm}", (ADD64ri8 RAX, i64i8imm:$imm), 0>;
3056 def : InstAlias<"and{q}\t{$imm, %rax|rax, $imm}", (AND64ri8 RAX, i64i8imm:$imm), 0>;
3057 def : InstAlias<"cmp{q}\t{$imm, %rax|rax, $imm}", (CMP64ri8 RAX, i64i8imm:$imm), 0>;
3058 def : InstAlias<"or{q}\t{$imm, %rax|rax, $imm}", (OR64ri8 RAX, i64i8imm:$imm), 0>;
3059 def : InstAlias<"sbb{q}\t{$imm, %rax|rax, $imm}", (SBB64ri8 RAX, i64i8imm:$imm), 0>;
3060 def : InstAlias<"sub{q}\t{$imm, %rax|rax, $imm}", (SUB64ri8 RAX, i64i8imm:$imm), 0>;
3061 def : InstAlias<"xor{q}\t{$imm, %rax|rax, $imm}", (XOR64ri8 RAX, i64i8imm:$imm), 0>;