1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
33 def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
37 def SDTX86BrCond : SDTypeProfile<0, 3,
38 [SDTCisVT<0, OtherVT>,
39 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
41 def SDTX86SetCC : SDTypeProfile<1, 2,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
47 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
49 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
50 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
51 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
53 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
54 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
57 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
59 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
63 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
65 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
67 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
69 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
71 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
73 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
75 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
77 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
78 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
79 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
80 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
82 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
84 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
86 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
87 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
89 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
91 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
92 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
94 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
95 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
97 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
98 [SDNPHasChain, SDNPMayStore,
99 SDNPMayLoad, SDNPMemOperand]>;
100 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
101 [SDNPHasChain, SDNPMayStore,
102 SDNPMayLoad, SDNPMemOperand]>;
103 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
104 [SDNPHasChain, SDNPMayStore,
105 SDNPMayLoad, SDNPMemOperand]>;
106 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
107 [SDNPHasChain, SDNPMayStore,
108 SDNPMayLoad, SDNPMemOperand]>;
109 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
110 [SDNPHasChain, SDNPMayStore,
111 SDNPMayLoad, SDNPMemOperand]>;
112 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
113 [SDNPHasChain, SDNPMayStore,
114 SDNPMayLoad, SDNPMemOperand]>;
115 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
116 [SDNPHasChain, SDNPMayStore,
117 SDNPMayLoad, SDNPMemOperand]>;
118 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
119 [SDNPHasChain, SDNPOptInFlag]>;
121 def X86vastart_save_xmm_regs :
122 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
123 SDT_X86VASTART_SAVE_XMM_REGS,
126 def X86callseq_start :
127 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
128 [SDNPHasChain, SDNPOutFlag]>;
130 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
131 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
133 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
134 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
136 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
137 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
138 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
139 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
142 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
143 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
145 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
146 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
148 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
149 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
150 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
151 SDT_X86SegmentBaseAddress, []>;
153 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
156 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
157 [SDNPHasChain, SDNPOptInFlag]>;
159 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags>;
160 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
161 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags>;
162 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>;
163 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
164 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
166 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
168 //===----------------------------------------------------------------------===//
169 // X86 Operand Definitions.
172 def i32imm_pcrel : Operand<i32> {
173 let PrintMethod = "print_pcrel_imm";
176 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
177 // the index operand of an address, to conform to x86 encoding restrictions.
178 def ptr_rc_nosp : PointerLikeRegClass<1>;
180 // *mem - Operand definitions for the funky X86 addressing mode operands.
182 def X86MemAsmOperand : AsmOperandClass {
186 class X86MemOperand<string printMethod> : Operand<iPTR> {
187 let PrintMethod = printMethod;
188 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
189 let ParserMatchClass = X86MemAsmOperand;
192 def i8mem : X86MemOperand<"printi8mem">;
193 def i16mem : X86MemOperand<"printi16mem">;
194 def i32mem : X86MemOperand<"printi32mem">;
195 def i64mem : X86MemOperand<"printi64mem">;
196 def i128mem : X86MemOperand<"printi128mem">;
197 def i256mem : X86MemOperand<"printi256mem">;
198 def f32mem : X86MemOperand<"printf32mem">;
199 def f64mem : X86MemOperand<"printf64mem">;
200 def f80mem : X86MemOperand<"printf80mem">;
201 def f128mem : X86MemOperand<"printf128mem">;
202 def f256mem : X86MemOperand<"printf256mem">;
204 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
205 // plain GR64, so that it doesn't potentially require a REX prefix.
206 def i8mem_NOREX : Operand<i64> {
207 let PrintMethod = "printi8mem";
208 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
209 let ParserMatchClass = X86MemAsmOperand;
212 def lea32mem : Operand<i32> {
213 let PrintMethod = "printlea32mem";
214 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
215 let ParserMatchClass = X86MemAsmOperand;
218 def SSECC : Operand<i8> {
219 let PrintMethod = "printSSECC";
222 def piclabel: Operand<i32> {
223 let PrintMethod = "printPICLabel";
226 def ImmSExt8AsmOperand : AsmOperandClass {
227 let Name = "ImmSExt8";
228 let SuperClass = ImmAsmOperand;
231 // A couple of more descriptive operand definitions.
232 // 16-bits but only 8 bits are significant.
233 def i16i8imm : Operand<i16> {
234 let ParserMatchClass = ImmSExt8AsmOperand;
236 // 32-bits but only 8 bits are significant.
237 def i32i8imm : Operand<i32> {
238 let ParserMatchClass = ImmSExt8AsmOperand;
241 // Branch targets have OtherVT type and print as pc-relative values.
242 def brtarget : Operand<OtherVT> {
243 let PrintMethod = "print_pcrel_imm";
246 def brtarget8 : Operand<OtherVT> {
247 let PrintMethod = "print_pcrel_imm";
250 //===----------------------------------------------------------------------===//
251 // X86 Complex Pattern Definitions.
254 // Define X86 specific addressing mode.
255 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
256 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
257 [add, sub, mul, X86mul_imm, shl, or, frameindex],
259 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
260 [tglobaltlsaddr], []>;
262 //===----------------------------------------------------------------------===//
263 // X86 Instruction Predicate Definitions.
264 def HasMMX : Predicate<"Subtarget->hasMMX()">;
265 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
266 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
267 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
268 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
269 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
270 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
271 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
272 def HasAVX : Predicate<"Subtarget->hasAVX()">;
273 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
274 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
275 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
276 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
277 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
278 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
279 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
280 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
281 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
282 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
283 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
284 "TM.getCodeModel() != CodeModel::Kernel">;
285 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
286 "TM.getCodeModel() == CodeModel::Kernel">;
287 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
288 def OptForSpeed : Predicate<"!OptForSize">;
289 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
290 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
292 //===----------------------------------------------------------------------===//
293 // X86 Instruction Format Definitions.
296 include "X86InstrFormats.td"
298 //===----------------------------------------------------------------------===//
299 // Pattern fragments...
302 // X86 specific condition code. These correspond to CondCode in
303 // X86InstrInfo.h. They must be kept in synch.
304 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
305 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
306 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
307 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
308 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
309 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
310 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
311 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
312 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
313 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
314 def X86_COND_NO : PatLeaf<(i8 10)>;
315 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
316 def X86_COND_NS : PatLeaf<(i8 12)>;
317 def X86_COND_O : PatLeaf<(i8 13)>;
318 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
319 def X86_COND_S : PatLeaf<(i8 15)>;
321 def i16immSExt8 : PatLeaf<(i16 imm), [{
322 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
323 // sign extended field.
324 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
327 def i32immSExt8 : PatLeaf<(i32 imm), [{
328 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
329 // sign extended field.
330 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
333 // Helper fragments for loads.
334 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
335 // known to be 32-bit aligned or better. Ditto for i8 to i16.
336 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
337 LoadSDNode *LD = cast<LoadSDNode>(N);
338 if (const Value *Src = LD->getSrcValue())
339 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
340 if (PT->getAddressSpace() > 255)
342 ISD::LoadExtType ExtType = LD->getExtensionType();
343 if (ExtType == ISD::NON_EXTLOAD)
345 if (ExtType == ISD::EXTLOAD)
346 return LD->getAlignment() >= 2 && !LD->isVolatile();
350 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
351 LoadSDNode *LD = cast<LoadSDNode>(N);
352 if (const Value *Src = LD->getSrcValue())
353 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
354 if (PT->getAddressSpace() > 255)
356 ISD::LoadExtType ExtType = LD->getExtensionType();
357 if (ExtType == ISD::EXTLOAD)
358 return LD->getAlignment() >= 2 && !LD->isVolatile();
362 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
363 LoadSDNode *LD = cast<LoadSDNode>(N);
364 if (const Value *Src = LD->getSrcValue())
365 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
366 if (PT->getAddressSpace() > 255)
368 ISD::LoadExtType ExtType = LD->getExtensionType();
369 if (ExtType == ISD::NON_EXTLOAD)
371 if (ExtType == ISD::EXTLOAD)
372 return LD->getAlignment() >= 4 && !LD->isVolatile();
376 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
377 LoadSDNode *LD = cast<LoadSDNode>(N);
378 if (const Value *Src = LD->getSrcValue())
379 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
380 if (PT->getAddressSpace() > 255)
382 if (LD->isVolatile())
384 ISD::LoadExtType ExtType = LD->getExtensionType();
385 if (ExtType == ISD::NON_EXTLOAD)
387 if (ExtType == ISD::EXTLOAD)
388 return LD->getAlignment() >= 4;
392 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
393 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
394 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
395 return PT->getAddressSpace() == 256;
399 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
400 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
401 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
402 return PT->getAddressSpace() == 257;
406 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{
407 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
408 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
409 if (PT->getAddressSpace() > 255)
413 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{
414 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
415 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
416 if (PT->getAddressSpace() > 255)
421 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{
422 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
423 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
424 if (PT->getAddressSpace() > 255)
428 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{
429 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
430 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
431 if (PT->getAddressSpace() > 255)
435 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{
436 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
437 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
438 if (PT->getAddressSpace() > 255)
443 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
444 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
445 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
447 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
448 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
449 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
450 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
451 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
452 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
454 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
455 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
456 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
457 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
458 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
459 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
462 // An 'and' node with a single use.
463 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
464 return N->hasOneUse();
466 // An 'srl' node with a single use.
467 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
468 return N->hasOneUse();
470 // An 'trunc' node with a single use.
471 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
472 return N->hasOneUse();
475 // 'shld' and 'shrd' instruction patterns. Note that even though these have
476 // the srl and shl in their patterns, the C++ code must still check for them,
477 // because predicates are tested before children nodes are explored.
479 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
480 (or (srl node:$src1, node:$amt1),
481 (shl node:$src2, node:$amt2)), [{
482 assert(N->getOpcode() == ISD::OR);
483 return N->getOperand(0).getOpcode() == ISD::SRL &&
484 N->getOperand(1).getOpcode() == ISD::SHL &&
485 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
486 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
487 N->getOperand(0).getConstantOperandVal(1) ==
488 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
491 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
492 (or (shl node:$src1, node:$amt1),
493 (srl node:$src2, node:$amt2)), [{
494 assert(N->getOpcode() == ISD::OR);
495 return N->getOperand(0).getOpcode() == ISD::SHL &&
496 N->getOperand(1).getOpcode() == ISD::SRL &&
497 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
498 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
499 N->getOperand(0).getConstantOperandVal(1) ==
500 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
503 //===----------------------------------------------------------------------===//
504 // Instruction list...
507 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
508 // a stack adjustment and the codegen must know that they may modify the stack
509 // pointer before prolog-epilog rewriting occurs.
510 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
511 // sub / add which can clobber EFLAGS.
512 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
513 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
515 [(X86callseq_start timm:$amt)]>,
516 Requires<[In32BitMode]>;
517 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
519 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
520 Requires<[In32BitMode]>;
523 // x86-64 va_start lowering magic.
524 let usesCustomDAGSchedInserter = 1 in
525 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
528 i64imm:$regsavefi, i64imm:$offset,
530 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
531 [(X86vastart_save_xmm_regs GR8:$al,
536 let neverHasSideEffects = 1 in {
537 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
538 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
539 "nopl\t$zero", []>, TB;
543 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int 3", []>;
544 def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
547 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
548 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
552 //===----------------------------------------------------------------------===//
553 // Control Flow Instructions...
556 // Return instructions.
557 let isTerminator = 1, isReturn = 1, isBarrier = 1,
558 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
559 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
562 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
564 [(X86retflag imm:$amt)]>;
567 // All branches are RawFrm, Void, Branch, and Terminators
568 let isBranch = 1, isTerminator = 1 in
569 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
570 I<opcode, RawFrm, (outs), ins, asm, pattern>;
572 let isBranch = 1, isBarrier = 1 in {
573 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
574 def JMP8 : IBr<0xEB, (ins brtarget8:$dst), "jmp\t$dst", []>;
578 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
579 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
580 [(brind GR32:$dst)]>;
581 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
582 [(brind (loadi32 addr:$dst))]>;
585 // Conditional branches
586 let Uses = [EFLAGS] in {
587 // Short conditional jumps
588 def JO8 : IBr<0x70, (ins brtarget8:$dst), "jo\t$dst", []>;
589 def JNO8 : IBr<0x71, (ins brtarget8:$dst), "jno\t$dst", []>;
590 def JB8 : IBr<0x72, (ins brtarget8:$dst), "jb\t$dst", []>;
591 def JAE8 : IBr<0x73, (ins brtarget8:$dst), "jae\t$dst", []>;
592 def JE8 : IBr<0x74, (ins brtarget8:$dst), "je\t$dst", []>;
593 def JNE8 : IBr<0x75, (ins brtarget8:$dst), "jne\t$dst", []>;
594 def JBE8 : IBr<0x76, (ins brtarget8:$dst), "jbe\t$dst", []>;
595 def JA8 : IBr<0x77, (ins brtarget8:$dst), "ja\t$dst", []>;
596 def JS8 : IBr<0x78, (ins brtarget8:$dst), "js\t$dst", []>;
597 def JNS8 : IBr<0x79, (ins brtarget8:$dst), "jns\t$dst", []>;
598 def JP8 : IBr<0x7A, (ins brtarget8:$dst), "jp\t$dst", []>;
599 def JNP8 : IBr<0x7B, (ins brtarget8:$dst), "jnp\t$dst", []>;
600 def JL8 : IBr<0x7C, (ins brtarget8:$dst), "jl\t$dst", []>;
601 def JGE8 : IBr<0x7D, (ins brtarget8:$dst), "jge\t$dst", []>;
602 def JLE8 : IBr<0x7E, (ins brtarget8:$dst), "jle\t$dst", []>;
603 def JG8 : IBr<0x7F, (ins brtarget8:$dst), "jg\t$dst", []>;
605 def JCXZ8 : IBr<0xE3, (ins brtarget8:$dst), "jcxz\t$dst", []>;
607 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
608 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
609 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
610 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
611 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
612 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
613 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
614 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
615 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
616 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
617 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
618 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
620 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
621 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
622 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
623 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
624 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
625 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
626 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
627 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
629 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
630 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
631 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
632 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
633 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
634 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
635 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
636 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
637 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
638 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
639 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
640 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
643 //===----------------------------------------------------------------------===//
644 // Call Instructions...
647 // All calls clobber the non-callee saved registers. ESP is marked as
648 // a use to prevent stack-pointer assignments that appear immediately
649 // before calls from potentially appearing dead. Uses for argument
650 // registers are added manually.
651 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
652 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
653 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
654 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
656 def CALLpcrel32 : Ii32<0xE8, RawFrm,
657 (outs), (ins i32imm_pcrel:$dst,variable_ops),
659 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
660 "call\t{*}$dst", [(X86call GR32:$dst)]>;
661 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
662 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
667 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
668 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
669 "#TC_RETURN $dst $offset",
672 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
673 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
674 "#TC_RETURN $dst $offset",
677 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
679 def TAILJMPd : IBr<0xE9, (ins i32imm_pcrel:$dst), "jmp\t$dst # TAILCALL",
681 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
682 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
684 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
685 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
686 "jmp\t{*}$dst # TAILCALL", []>;
688 //===----------------------------------------------------------------------===//
689 // Miscellaneous Instructions...
691 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
692 def LEAVE : I<0xC9, RawFrm,
693 (outs), (ins), "leave", []>;
695 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
697 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
700 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
703 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
704 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
705 "push{l}\t$imm", []>;
706 def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
707 "push{l}\t$imm", []>;
708 def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
709 "push{l}\t$imm", []>;
712 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
713 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
714 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
715 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
717 let isTwoAddress = 1 in // GR32 = bswap GR32
718 def BSWAP32r : I<0xC8, AddRegFrm,
719 (outs GR32:$dst), (ins GR32:$src),
721 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
724 // Bit scan instructions.
725 let Defs = [EFLAGS] in {
726 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
727 "bsf{w}\t{$src, $dst|$dst, $src}",
728 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
729 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
730 "bsf{w}\t{$src, $dst|$dst, $src}",
731 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
732 (implicit EFLAGS)]>, TB;
733 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
734 "bsf{l}\t{$src, $dst|$dst, $src}",
735 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
736 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
737 "bsf{l}\t{$src, $dst|$dst, $src}",
738 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
739 (implicit EFLAGS)]>, TB;
741 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
742 "bsr{w}\t{$src, $dst|$dst, $src}",
743 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
744 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
745 "bsr{w}\t{$src, $dst|$dst, $src}",
746 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
747 (implicit EFLAGS)]>, TB;
748 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
749 "bsr{l}\t{$src, $dst|$dst, $src}",
750 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
751 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
752 "bsr{l}\t{$src, $dst|$dst, $src}",
753 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
754 (implicit EFLAGS)]>, TB;
757 let neverHasSideEffects = 1 in
758 def LEA16r : I<0x8D, MRMSrcMem,
759 (outs GR16:$dst), (ins i32mem:$src),
760 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
761 let isReMaterializable = 1 in
762 def LEA32r : I<0x8D, MRMSrcMem,
763 (outs GR32:$dst), (ins lea32mem:$src),
764 "lea{l}\t{$src|$dst}, {$dst|$src}",
765 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
767 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
768 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
769 [(X86rep_movs i8)]>, REP;
770 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
771 [(X86rep_movs i16)]>, REP, OpSize;
772 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
773 [(X86rep_movs i32)]>, REP;
776 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
777 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
778 [(X86rep_stos i8)]>, REP;
779 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
780 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
781 [(X86rep_stos i16)]>, REP, OpSize;
782 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
783 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
784 [(X86rep_stos i32)]>, REP;
786 let Defs = [RAX, RDX] in
787 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
790 let isBarrier = 1, hasCtrlDep = 1 in {
791 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
794 def SYSCALL : I<0x05, RawFrm,
795 (outs), (ins), "syscall", []>, TB;
796 def SYSRET : I<0x07, RawFrm,
797 (outs), (ins), "sysret", []>, TB;
798 def SYSENTER : I<0x34, RawFrm,
799 (outs), (ins), "sysenter", []>, TB;
800 def SYSEXIT : I<0x35, RawFrm,
801 (outs), (ins), "sysexit", []>, TB;
805 //===----------------------------------------------------------------------===//
806 // Input/Output Instructions...
808 let Defs = [AL], Uses = [DX] in
809 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
810 "in{b}\t{%dx, %al|%AL, %DX}", []>;
811 let Defs = [AX], Uses = [DX] in
812 def IN16rr : I<0xED, RawFrm, (outs), (ins),
813 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
814 let Defs = [EAX], Uses = [DX] in
815 def IN32rr : I<0xED, RawFrm, (outs), (ins),
816 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
819 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
820 "in{b}\t{$port, %al|%AL, $port}", []>;
822 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
823 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
825 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
826 "in{l}\t{$port, %eax|%EAX, $port}", []>;
828 let Uses = [DX, AL] in
829 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
830 "out{b}\t{%al, %dx|%DX, %AL}", []>;
831 let Uses = [DX, AX] in
832 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
833 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
834 let Uses = [DX, EAX] in
835 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
836 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
839 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
840 "out{b}\t{%al, $port|$port, %AL}", []>;
842 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
843 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
845 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
846 "out{l}\t{%eax, $port|$port, %EAX}", []>;
848 //===----------------------------------------------------------------------===//
849 // Move Instructions...
851 let neverHasSideEffects = 1 in {
852 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
853 "mov{b}\t{$src, $dst|$dst, $src}", []>;
854 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
855 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
856 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
857 "mov{l}\t{$src, $dst|$dst, $src}", []>;
859 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
860 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
861 "mov{b}\t{$src, $dst|$dst, $src}",
862 [(set GR8:$dst, imm:$src)]>;
863 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
864 "mov{w}\t{$src, $dst|$dst, $src}",
865 [(set GR16:$dst, imm:$src)]>, OpSize;
866 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
867 "mov{l}\t{$src, $dst|$dst, $src}",
868 [(set GR32:$dst, imm:$src)]>;
870 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
871 "mov{b}\t{$src, $dst|$dst, $src}",
872 [(store (i8 imm:$src), addr:$dst)]>;
873 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
874 "mov{w}\t{$src, $dst|$dst, $src}",
875 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
876 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
877 "mov{l}\t{$src, $dst|$dst, $src}",
878 [(store (i32 imm:$src), addr:$dst)]>;
880 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
881 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
882 "mov{b}\t{$src, $dst|$dst, $src}",
883 [(set GR8:$dst, (loadi8 addr:$src))]>;
884 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
885 "mov{w}\t{$src, $dst|$dst, $src}",
886 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
887 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
888 "mov{l}\t{$src, $dst|$dst, $src}",
889 [(set GR32:$dst, (loadi32 addr:$src))]>;
892 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
893 "mov{b}\t{$src, $dst|$dst, $src}",
894 [(store GR8:$src, addr:$dst)]>;
895 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
896 "mov{w}\t{$src, $dst|$dst, $src}",
897 [(store GR16:$src, addr:$dst)]>, OpSize;
898 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
899 "mov{l}\t{$src, $dst|$dst, $src}",
900 [(store GR32:$src, addr:$dst)]>;
902 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
903 // that they can be used for copying and storing h registers, which can't be
904 // encoded when a REX prefix is present.
905 let neverHasSideEffects = 1 in
906 def MOV8rr_NOREX : I<0x88, MRMDestReg,
907 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
908 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
910 def MOV8mr_NOREX : I<0x88, MRMDestMem,
911 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
912 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
914 canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
915 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
916 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
917 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
919 //===----------------------------------------------------------------------===//
920 // Fixed-Register Multiplication and Division Instructions...
923 // Extra precision multiplication
924 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
925 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
926 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
927 // This probably ought to be moved to a def : Pat<> if the
928 // syntax can be accepted.
929 [(set AL, (mul AL, GR8:$src)),
930 (implicit EFLAGS)]>; // AL,AH = AL*GR8
932 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
933 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
935 []>, OpSize; // AX,DX = AX*GR16
937 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
938 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
940 []>; // EAX,EDX = EAX*GR32
942 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
943 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
945 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
946 // This probably ought to be moved to a def : Pat<> if the
947 // syntax can be accepted.
948 [(set AL, (mul AL, (loadi8 addr:$src))),
949 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
951 let mayLoad = 1, neverHasSideEffects = 1 in {
952 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
953 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
955 []>, OpSize; // AX,DX = AX*[mem16]
957 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
958 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
960 []>; // EAX,EDX = EAX*[mem32]
963 let neverHasSideEffects = 1 in {
964 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
965 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
967 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
968 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
969 OpSize; // AX,DX = AX*GR16
970 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
971 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
972 // EAX,EDX = EAX*GR32
974 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
975 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
976 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
977 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
978 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
979 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
980 let Defs = [EAX,EDX], Uses = [EAX] in
981 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
982 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
984 } // neverHasSideEffects
986 // unsigned division/remainder
987 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
988 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
990 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
991 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
992 "div{w}\t$src", []>, OpSize;
993 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
994 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
997 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
998 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1000 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1001 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1002 "div{w}\t$src", []>, OpSize;
1003 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1004 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
1005 "div{l}\t$src", []>;
1008 // Signed division/remainder.
1009 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1010 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1011 "idiv{b}\t$src", []>;
1012 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1013 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1014 "idiv{w}\t$src", []>, OpSize;
1015 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1016 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1017 "idiv{l}\t$src", []>;
1018 let mayLoad = 1, mayLoad = 1 in {
1019 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1020 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1021 "idiv{b}\t$src", []>;
1022 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1023 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1024 "idiv{w}\t$src", []>, OpSize;
1025 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1026 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
1027 "idiv{l}\t$src", []>;
1030 //===----------------------------------------------------------------------===//
1031 // Two address Instructions.
1033 let isTwoAddress = 1 in {
1035 // Conditional moves
1036 let Uses = [EFLAGS] in {
1038 // X86 doesn't have 8-bit conditional moves. Use a customDAGSchedInserter to
1039 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1040 // however that requires promoting the operands, and can induce additional
1041 // i8 register pressure.
1042 let usesCustomDAGSchedInserter = 1, isTwoAddress = 0 in
1043 def CMOV_GR8 : I<0, Pseudo,
1044 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1045 "#CMOV_GR8 PSEUDO!",
1046 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1047 imm:$cond, EFLAGS))]>;
1049 let isCommutable = 1 in {
1050 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1051 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1052 "cmovb\t{$src2, $dst|$dst, $src2}",
1053 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1054 X86_COND_B, EFLAGS))]>,
1056 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1057 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1058 "cmovb\t{$src2, $dst|$dst, $src2}",
1059 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1060 X86_COND_B, EFLAGS))]>,
1062 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1063 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1064 "cmovae\t{$src2, $dst|$dst, $src2}",
1065 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1066 X86_COND_AE, EFLAGS))]>,
1068 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1069 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1070 "cmovae\t{$src2, $dst|$dst, $src2}",
1071 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1072 X86_COND_AE, EFLAGS))]>,
1074 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1075 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1076 "cmove\t{$src2, $dst|$dst, $src2}",
1077 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1078 X86_COND_E, EFLAGS))]>,
1080 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1081 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1082 "cmove\t{$src2, $dst|$dst, $src2}",
1083 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1084 X86_COND_E, EFLAGS))]>,
1086 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1087 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1088 "cmovne\t{$src2, $dst|$dst, $src2}",
1089 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1090 X86_COND_NE, EFLAGS))]>,
1092 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1093 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1094 "cmovne\t{$src2, $dst|$dst, $src2}",
1095 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1096 X86_COND_NE, EFLAGS))]>,
1098 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1099 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1100 "cmovbe\t{$src2, $dst|$dst, $src2}",
1101 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1102 X86_COND_BE, EFLAGS))]>,
1104 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1105 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1106 "cmovbe\t{$src2, $dst|$dst, $src2}",
1107 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1108 X86_COND_BE, EFLAGS))]>,
1110 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1111 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1112 "cmova\t{$src2, $dst|$dst, $src2}",
1113 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1114 X86_COND_A, EFLAGS))]>,
1116 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1117 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1118 "cmova\t{$src2, $dst|$dst, $src2}",
1119 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1120 X86_COND_A, EFLAGS))]>,
1122 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1123 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1124 "cmovl\t{$src2, $dst|$dst, $src2}",
1125 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1126 X86_COND_L, EFLAGS))]>,
1128 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1129 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1130 "cmovl\t{$src2, $dst|$dst, $src2}",
1131 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1132 X86_COND_L, EFLAGS))]>,
1134 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1135 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1136 "cmovge\t{$src2, $dst|$dst, $src2}",
1137 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1138 X86_COND_GE, EFLAGS))]>,
1140 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1141 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1142 "cmovge\t{$src2, $dst|$dst, $src2}",
1143 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1144 X86_COND_GE, EFLAGS))]>,
1146 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1147 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1148 "cmovle\t{$src2, $dst|$dst, $src2}",
1149 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1150 X86_COND_LE, EFLAGS))]>,
1152 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1153 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1154 "cmovle\t{$src2, $dst|$dst, $src2}",
1155 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1156 X86_COND_LE, EFLAGS))]>,
1158 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1159 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1160 "cmovg\t{$src2, $dst|$dst, $src2}",
1161 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1162 X86_COND_G, EFLAGS))]>,
1164 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1165 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1166 "cmovg\t{$src2, $dst|$dst, $src2}",
1167 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1168 X86_COND_G, EFLAGS))]>,
1170 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1171 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1172 "cmovs\t{$src2, $dst|$dst, $src2}",
1173 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1174 X86_COND_S, EFLAGS))]>,
1176 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1177 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1178 "cmovs\t{$src2, $dst|$dst, $src2}",
1179 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1180 X86_COND_S, EFLAGS))]>,
1182 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1183 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1184 "cmovns\t{$src2, $dst|$dst, $src2}",
1185 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1186 X86_COND_NS, EFLAGS))]>,
1188 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1189 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1190 "cmovns\t{$src2, $dst|$dst, $src2}",
1191 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1192 X86_COND_NS, EFLAGS))]>,
1194 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1195 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1196 "cmovp\t{$src2, $dst|$dst, $src2}",
1197 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1198 X86_COND_P, EFLAGS))]>,
1200 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1201 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1202 "cmovp\t{$src2, $dst|$dst, $src2}",
1203 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1204 X86_COND_P, EFLAGS))]>,
1206 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1207 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1208 "cmovnp\t{$src2, $dst|$dst, $src2}",
1209 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1210 X86_COND_NP, EFLAGS))]>,
1212 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1213 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1214 "cmovnp\t{$src2, $dst|$dst, $src2}",
1215 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1216 X86_COND_NP, EFLAGS))]>,
1218 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1219 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1220 "cmovo\t{$src2, $dst|$dst, $src2}",
1221 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1222 X86_COND_O, EFLAGS))]>,
1224 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1225 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1226 "cmovo\t{$src2, $dst|$dst, $src2}",
1227 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1228 X86_COND_O, EFLAGS))]>,
1230 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1231 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1232 "cmovno\t{$src2, $dst|$dst, $src2}",
1233 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1234 X86_COND_NO, EFLAGS))]>,
1236 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1237 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1238 "cmovno\t{$src2, $dst|$dst, $src2}",
1239 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1240 X86_COND_NO, EFLAGS))]>,
1242 } // isCommutable = 1
1244 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1245 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1246 "cmovb\t{$src2, $dst|$dst, $src2}",
1247 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1248 X86_COND_B, EFLAGS))]>,
1250 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1251 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1252 "cmovb\t{$src2, $dst|$dst, $src2}",
1253 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1254 X86_COND_B, EFLAGS))]>,
1256 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1257 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1258 "cmovae\t{$src2, $dst|$dst, $src2}",
1259 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1260 X86_COND_AE, EFLAGS))]>,
1262 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1263 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1264 "cmovae\t{$src2, $dst|$dst, $src2}",
1265 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1266 X86_COND_AE, EFLAGS))]>,
1268 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1269 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1270 "cmove\t{$src2, $dst|$dst, $src2}",
1271 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1272 X86_COND_E, EFLAGS))]>,
1274 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1275 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1276 "cmove\t{$src2, $dst|$dst, $src2}",
1277 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1278 X86_COND_E, EFLAGS))]>,
1280 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1281 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1282 "cmovne\t{$src2, $dst|$dst, $src2}",
1283 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1284 X86_COND_NE, EFLAGS))]>,
1286 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1287 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1288 "cmovne\t{$src2, $dst|$dst, $src2}",
1289 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1290 X86_COND_NE, EFLAGS))]>,
1292 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1293 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1294 "cmovbe\t{$src2, $dst|$dst, $src2}",
1295 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1296 X86_COND_BE, EFLAGS))]>,
1298 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1299 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1300 "cmovbe\t{$src2, $dst|$dst, $src2}",
1301 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1302 X86_COND_BE, EFLAGS))]>,
1304 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1305 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1306 "cmova\t{$src2, $dst|$dst, $src2}",
1307 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1308 X86_COND_A, EFLAGS))]>,
1310 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1311 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1312 "cmova\t{$src2, $dst|$dst, $src2}",
1313 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1314 X86_COND_A, EFLAGS))]>,
1316 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1317 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1318 "cmovl\t{$src2, $dst|$dst, $src2}",
1319 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1320 X86_COND_L, EFLAGS))]>,
1322 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1323 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1324 "cmovl\t{$src2, $dst|$dst, $src2}",
1325 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1326 X86_COND_L, EFLAGS))]>,
1328 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1329 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1330 "cmovge\t{$src2, $dst|$dst, $src2}",
1331 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1332 X86_COND_GE, EFLAGS))]>,
1334 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1335 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1336 "cmovge\t{$src2, $dst|$dst, $src2}",
1337 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1338 X86_COND_GE, EFLAGS))]>,
1340 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1341 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1342 "cmovle\t{$src2, $dst|$dst, $src2}",
1343 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1344 X86_COND_LE, EFLAGS))]>,
1346 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1347 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1348 "cmovle\t{$src2, $dst|$dst, $src2}",
1349 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1350 X86_COND_LE, EFLAGS))]>,
1352 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1353 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1354 "cmovg\t{$src2, $dst|$dst, $src2}",
1355 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1356 X86_COND_G, EFLAGS))]>,
1358 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1359 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1360 "cmovg\t{$src2, $dst|$dst, $src2}",
1361 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1362 X86_COND_G, EFLAGS))]>,
1364 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1365 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1366 "cmovs\t{$src2, $dst|$dst, $src2}",
1367 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1368 X86_COND_S, EFLAGS))]>,
1370 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1371 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1372 "cmovs\t{$src2, $dst|$dst, $src2}",
1373 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1374 X86_COND_S, EFLAGS))]>,
1376 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1377 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1378 "cmovns\t{$src2, $dst|$dst, $src2}",
1379 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1380 X86_COND_NS, EFLAGS))]>,
1382 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1383 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1384 "cmovns\t{$src2, $dst|$dst, $src2}",
1385 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1386 X86_COND_NS, EFLAGS))]>,
1388 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1389 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1390 "cmovp\t{$src2, $dst|$dst, $src2}",
1391 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1392 X86_COND_P, EFLAGS))]>,
1394 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1395 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1396 "cmovp\t{$src2, $dst|$dst, $src2}",
1397 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1398 X86_COND_P, EFLAGS))]>,
1400 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1401 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1402 "cmovnp\t{$src2, $dst|$dst, $src2}",
1403 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1404 X86_COND_NP, EFLAGS))]>,
1406 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1407 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1408 "cmovnp\t{$src2, $dst|$dst, $src2}",
1409 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1410 X86_COND_NP, EFLAGS))]>,
1412 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1413 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1414 "cmovo\t{$src2, $dst|$dst, $src2}",
1415 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1416 X86_COND_O, EFLAGS))]>,
1418 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1419 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1420 "cmovo\t{$src2, $dst|$dst, $src2}",
1421 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1422 X86_COND_O, EFLAGS))]>,
1424 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1425 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1426 "cmovno\t{$src2, $dst|$dst, $src2}",
1427 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1428 X86_COND_NO, EFLAGS))]>,
1430 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1431 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1432 "cmovno\t{$src2, $dst|$dst, $src2}",
1433 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1434 X86_COND_NO, EFLAGS))]>,
1436 } // Uses = [EFLAGS]
1439 // unary instructions
1440 let CodeSize = 2 in {
1441 let Defs = [EFLAGS] in {
1442 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1443 [(set GR8:$dst, (ineg GR8:$src)),
1444 (implicit EFLAGS)]>;
1445 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1446 [(set GR16:$dst, (ineg GR16:$src)),
1447 (implicit EFLAGS)]>, OpSize;
1448 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1449 [(set GR32:$dst, (ineg GR32:$src)),
1450 (implicit EFLAGS)]>;
1451 let isTwoAddress = 0 in {
1452 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1453 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1454 (implicit EFLAGS)]>;
1455 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1456 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1457 (implicit EFLAGS)]>, OpSize;
1458 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1459 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1460 (implicit EFLAGS)]>;
1462 } // Defs = [EFLAGS]
1464 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1465 let AddedComplexity = 15 in {
1466 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1467 [(set GR8:$dst, (not GR8:$src))]>;
1468 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1469 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1470 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1471 [(set GR32:$dst, (not GR32:$src))]>;
1473 let isTwoAddress = 0 in {
1474 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1475 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1476 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1477 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1478 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1479 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1483 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1484 let Defs = [EFLAGS] in {
1486 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1487 [(set GR8:$dst, (add GR8:$src, 1)),
1488 (implicit EFLAGS)]>;
1489 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1490 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1491 [(set GR16:$dst, (add GR16:$src, 1)),
1492 (implicit EFLAGS)]>,
1493 OpSize, Requires<[In32BitMode]>;
1494 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1495 [(set GR32:$dst, (add GR32:$src, 1)),
1496 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1498 let isTwoAddress = 0, CodeSize = 2 in {
1499 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1500 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1501 (implicit EFLAGS)]>;
1502 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1503 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1504 (implicit EFLAGS)]>,
1505 OpSize, Requires<[In32BitMode]>;
1506 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1507 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1508 (implicit EFLAGS)]>,
1509 Requires<[In32BitMode]>;
1513 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1514 [(set GR8:$dst, (add GR8:$src, -1)),
1515 (implicit EFLAGS)]>;
1516 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1517 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1518 [(set GR16:$dst, (add GR16:$src, -1)),
1519 (implicit EFLAGS)]>,
1520 OpSize, Requires<[In32BitMode]>;
1521 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1522 [(set GR32:$dst, (add GR32:$src, -1)),
1523 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1526 let isTwoAddress = 0, CodeSize = 2 in {
1527 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1528 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1529 (implicit EFLAGS)]>;
1530 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1531 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1532 (implicit EFLAGS)]>,
1533 OpSize, Requires<[In32BitMode]>;
1534 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1535 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1536 (implicit EFLAGS)]>,
1537 Requires<[In32BitMode]>;
1539 } // Defs = [EFLAGS]
1541 // Logical operators...
1542 let Defs = [EFLAGS] in {
1543 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1544 def AND8rr : I<0x20, MRMDestReg,
1545 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1546 "and{b}\t{$src2, $dst|$dst, $src2}",
1547 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1548 (implicit EFLAGS)]>;
1549 def AND16rr : I<0x21, MRMDestReg,
1550 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1551 "and{w}\t{$src2, $dst|$dst, $src2}",
1552 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1553 (implicit EFLAGS)]>, OpSize;
1554 def AND32rr : I<0x21, MRMDestReg,
1555 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1556 "and{l}\t{$src2, $dst|$dst, $src2}",
1557 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1558 (implicit EFLAGS)]>;
1561 def AND8rm : I<0x22, MRMSrcMem,
1562 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1563 "and{b}\t{$src2, $dst|$dst, $src2}",
1564 [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
1565 (implicit EFLAGS)]>;
1566 def AND16rm : I<0x23, MRMSrcMem,
1567 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1568 "and{w}\t{$src2, $dst|$dst, $src2}",
1569 [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
1570 (implicit EFLAGS)]>, OpSize;
1571 def AND32rm : I<0x23, MRMSrcMem,
1572 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1573 "and{l}\t{$src2, $dst|$dst, $src2}",
1574 [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
1575 (implicit EFLAGS)]>;
1577 def AND8ri : Ii8<0x80, MRM4r,
1578 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1579 "and{b}\t{$src2, $dst|$dst, $src2}",
1580 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1581 (implicit EFLAGS)]>;
1582 def AND16ri : Ii16<0x81, MRM4r,
1583 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1584 "and{w}\t{$src2, $dst|$dst, $src2}",
1585 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1586 (implicit EFLAGS)]>, OpSize;
1587 def AND32ri : Ii32<0x81, MRM4r,
1588 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1589 "and{l}\t{$src2, $dst|$dst, $src2}",
1590 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1591 (implicit EFLAGS)]>;
1592 def AND16ri8 : Ii8<0x83, MRM4r,
1593 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1594 "and{w}\t{$src2, $dst|$dst, $src2}",
1595 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1596 (implicit EFLAGS)]>,
1598 def AND32ri8 : Ii8<0x83, MRM4r,
1599 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1600 "and{l}\t{$src2, $dst|$dst, $src2}",
1601 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1602 (implicit EFLAGS)]>;
1604 let isTwoAddress = 0 in {
1605 def AND8mr : I<0x20, MRMDestMem,
1606 (outs), (ins i8mem :$dst, GR8 :$src),
1607 "and{b}\t{$src, $dst|$dst, $src}",
1608 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1609 (implicit EFLAGS)]>;
1610 def AND16mr : I<0x21, MRMDestMem,
1611 (outs), (ins i16mem:$dst, GR16:$src),
1612 "and{w}\t{$src, $dst|$dst, $src}",
1613 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1614 (implicit EFLAGS)]>,
1616 def AND32mr : I<0x21, MRMDestMem,
1617 (outs), (ins i32mem:$dst, GR32:$src),
1618 "and{l}\t{$src, $dst|$dst, $src}",
1619 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1620 (implicit EFLAGS)]>;
1621 def AND8mi : Ii8<0x80, MRM4m,
1622 (outs), (ins i8mem :$dst, i8imm :$src),
1623 "and{b}\t{$src, $dst|$dst, $src}",
1624 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1625 (implicit EFLAGS)]>;
1626 def AND16mi : Ii16<0x81, MRM4m,
1627 (outs), (ins i16mem:$dst, i16imm:$src),
1628 "and{w}\t{$src, $dst|$dst, $src}",
1629 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1630 (implicit EFLAGS)]>,
1632 def AND32mi : Ii32<0x81, MRM4m,
1633 (outs), (ins i32mem:$dst, i32imm:$src),
1634 "and{l}\t{$src, $dst|$dst, $src}",
1635 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1636 (implicit EFLAGS)]>;
1637 def AND16mi8 : Ii8<0x83, MRM4m,
1638 (outs), (ins i16mem:$dst, i16i8imm :$src),
1639 "and{w}\t{$src, $dst|$dst, $src}",
1640 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1641 (implicit EFLAGS)]>,
1643 def AND32mi8 : Ii8<0x83, MRM4m,
1644 (outs), (ins i32mem:$dst, i32i8imm :$src),
1645 "and{l}\t{$src, $dst|$dst, $src}",
1646 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1647 (implicit EFLAGS)]>;
1651 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1652 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1653 "or{b}\t{$src2, $dst|$dst, $src2}",
1654 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1655 (implicit EFLAGS)]>;
1656 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1657 "or{w}\t{$src2, $dst|$dst, $src2}",
1658 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1659 (implicit EFLAGS)]>, OpSize;
1660 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1661 "or{l}\t{$src2, $dst|$dst, $src2}",
1662 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1663 (implicit EFLAGS)]>;
1665 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1666 "or{b}\t{$src2, $dst|$dst, $src2}",
1667 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1668 (implicit EFLAGS)]>;
1669 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1670 "or{w}\t{$src2, $dst|$dst, $src2}",
1671 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1672 (implicit EFLAGS)]>, OpSize;
1673 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1674 "or{l}\t{$src2, $dst|$dst, $src2}",
1675 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1676 (implicit EFLAGS)]>;
1678 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1679 "or{b}\t{$src2, $dst|$dst, $src2}",
1680 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
1681 (implicit EFLAGS)]>;
1682 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1683 "or{w}\t{$src2, $dst|$dst, $src2}",
1684 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
1685 (implicit EFLAGS)]>, OpSize;
1686 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1687 "or{l}\t{$src2, $dst|$dst, $src2}",
1688 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
1689 (implicit EFLAGS)]>;
1691 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1692 "or{w}\t{$src2, $dst|$dst, $src2}",
1693 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
1694 (implicit EFLAGS)]>, OpSize;
1695 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1696 "or{l}\t{$src2, $dst|$dst, $src2}",
1697 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
1698 (implicit EFLAGS)]>;
1699 let isTwoAddress = 0 in {
1700 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1701 "or{b}\t{$src, $dst|$dst, $src}",
1702 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1703 (implicit EFLAGS)]>;
1704 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1705 "or{w}\t{$src, $dst|$dst, $src}",
1706 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1707 (implicit EFLAGS)]>, OpSize;
1708 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1709 "or{l}\t{$src, $dst|$dst, $src}",
1710 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1711 (implicit EFLAGS)]>;
1712 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1713 "or{b}\t{$src, $dst|$dst, $src}",
1714 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1715 (implicit EFLAGS)]>;
1716 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1717 "or{w}\t{$src, $dst|$dst, $src}",
1718 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1719 (implicit EFLAGS)]>,
1721 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1722 "or{l}\t{$src, $dst|$dst, $src}",
1723 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1724 (implicit EFLAGS)]>;
1725 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1726 "or{w}\t{$src, $dst|$dst, $src}",
1727 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1728 (implicit EFLAGS)]>,
1730 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1731 "or{l}\t{$src, $dst|$dst, $src}",
1732 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1733 (implicit EFLAGS)]>;
1734 } // isTwoAddress = 0
1737 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1738 def XOR8rr : I<0x30, MRMDestReg,
1739 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1740 "xor{b}\t{$src2, $dst|$dst, $src2}",
1741 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
1742 (implicit EFLAGS)]>;
1743 def XOR16rr : I<0x31, MRMDestReg,
1744 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1745 "xor{w}\t{$src2, $dst|$dst, $src2}",
1746 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
1747 (implicit EFLAGS)]>, OpSize;
1748 def XOR32rr : I<0x31, MRMDestReg,
1749 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1750 "xor{l}\t{$src2, $dst|$dst, $src2}",
1751 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
1752 (implicit EFLAGS)]>;
1753 } // isCommutable = 1
1755 def XOR8rm : I<0x32, MRMSrcMem ,
1756 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1757 "xor{b}\t{$src2, $dst|$dst, $src2}",
1758 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
1759 (implicit EFLAGS)]>;
1760 def XOR16rm : I<0x33, MRMSrcMem ,
1761 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1762 "xor{w}\t{$src2, $dst|$dst, $src2}",
1763 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
1764 (implicit EFLAGS)]>,
1766 def XOR32rm : I<0x33, MRMSrcMem ,
1767 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1768 "xor{l}\t{$src2, $dst|$dst, $src2}",
1769 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
1770 (implicit EFLAGS)]>;
1772 def XOR8ri : Ii8<0x80, MRM6r,
1773 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1774 "xor{b}\t{$src2, $dst|$dst, $src2}",
1775 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
1776 (implicit EFLAGS)]>;
1777 def XOR16ri : Ii16<0x81, MRM6r,
1778 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1779 "xor{w}\t{$src2, $dst|$dst, $src2}",
1780 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
1781 (implicit EFLAGS)]>, OpSize;
1782 def XOR32ri : Ii32<0x81, MRM6r,
1783 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1784 "xor{l}\t{$src2, $dst|$dst, $src2}",
1785 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
1786 (implicit EFLAGS)]>;
1787 def XOR16ri8 : Ii8<0x83, MRM6r,
1788 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1789 "xor{w}\t{$src2, $dst|$dst, $src2}",
1790 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
1791 (implicit EFLAGS)]>,
1793 def XOR32ri8 : Ii8<0x83, MRM6r,
1794 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1795 "xor{l}\t{$src2, $dst|$dst, $src2}",
1796 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
1797 (implicit EFLAGS)]>;
1799 let isTwoAddress = 0 in {
1800 def XOR8mr : I<0x30, MRMDestMem,
1801 (outs), (ins i8mem :$dst, GR8 :$src),
1802 "xor{b}\t{$src, $dst|$dst, $src}",
1803 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
1804 (implicit EFLAGS)]>;
1805 def XOR16mr : I<0x31, MRMDestMem,
1806 (outs), (ins i16mem:$dst, GR16:$src),
1807 "xor{w}\t{$src, $dst|$dst, $src}",
1808 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
1809 (implicit EFLAGS)]>,
1811 def XOR32mr : I<0x31, MRMDestMem,
1812 (outs), (ins i32mem:$dst, GR32:$src),
1813 "xor{l}\t{$src, $dst|$dst, $src}",
1814 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
1815 (implicit EFLAGS)]>;
1816 def XOR8mi : Ii8<0x80, MRM6m,
1817 (outs), (ins i8mem :$dst, i8imm :$src),
1818 "xor{b}\t{$src, $dst|$dst, $src}",
1819 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
1820 (implicit EFLAGS)]>;
1821 def XOR16mi : Ii16<0x81, MRM6m,
1822 (outs), (ins i16mem:$dst, i16imm:$src),
1823 "xor{w}\t{$src, $dst|$dst, $src}",
1824 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
1825 (implicit EFLAGS)]>,
1827 def XOR32mi : Ii32<0x81, MRM6m,
1828 (outs), (ins i32mem:$dst, i32imm:$src),
1829 "xor{l}\t{$src, $dst|$dst, $src}",
1830 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
1831 (implicit EFLAGS)]>;
1832 def XOR16mi8 : Ii8<0x83, MRM6m,
1833 (outs), (ins i16mem:$dst, i16i8imm :$src),
1834 "xor{w}\t{$src, $dst|$dst, $src}",
1835 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
1836 (implicit EFLAGS)]>,
1838 def XOR32mi8 : Ii8<0x83, MRM6m,
1839 (outs), (ins i32mem:$dst, i32i8imm :$src),
1840 "xor{l}\t{$src, $dst|$dst, $src}",
1841 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
1842 (implicit EFLAGS)]>;
1843 } // isTwoAddress = 0
1844 } // Defs = [EFLAGS]
1846 // Shift instructions
1847 let Defs = [EFLAGS] in {
1848 let Uses = [CL] in {
1849 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1850 "shl{b}\t{%cl, $dst|$dst, CL}",
1851 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1852 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1853 "shl{w}\t{%cl, $dst|$dst, CL}",
1854 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1855 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1856 "shl{l}\t{%cl, $dst|$dst, CL}",
1857 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1860 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1861 "shl{b}\t{$src2, $dst|$dst, $src2}",
1862 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1863 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1864 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1865 "shl{w}\t{$src2, $dst|$dst, $src2}",
1866 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1867 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1868 "shl{l}\t{$src2, $dst|$dst, $src2}",
1869 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1870 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1872 } // isConvertibleToThreeAddress = 1
1874 let isTwoAddress = 0 in {
1875 let Uses = [CL] in {
1876 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1877 "shl{b}\t{%cl, $dst|$dst, CL}",
1878 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1879 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1880 "shl{w}\t{%cl, $dst|$dst, CL}",
1881 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1882 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1883 "shl{l}\t{%cl, $dst|$dst, CL}",
1884 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1886 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1887 "shl{b}\t{$src, $dst|$dst, $src}",
1888 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1889 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1890 "shl{w}\t{$src, $dst|$dst, $src}",
1891 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1893 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1894 "shl{l}\t{$src, $dst|$dst, $src}",
1895 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1898 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1900 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1901 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1903 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1905 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1907 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1910 let Uses = [CL] in {
1911 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1912 "shr{b}\t{%cl, $dst|$dst, CL}",
1913 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1914 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1915 "shr{w}\t{%cl, $dst|$dst, CL}",
1916 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1917 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1918 "shr{l}\t{%cl, $dst|$dst, CL}",
1919 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1922 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1923 "shr{b}\t{$src2, $dst|$dst, $src2}",
1924 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1925 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1926 "shr{w}\t{$src2, $dst|$dst, $src2}",
1927 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1928 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1929 "shr{l}\t{$src2, $dst|$dst, $src2}",
1930 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1933 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1935 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1936 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1938 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1939 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1941 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1943 let isTwoAddress = 0 in {
1944 let Uses = [CL] in {
1945 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1946 "shr{b}\t{%cl, $dst|$dst, CL}",
1947 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1948 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1949 "shr{w}\t{%cl, $dst|$dst, CL}",
1950 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1952 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1953 "shr{l}\t{%cl, $dst|$dst, CL}",
1954 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1956 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1957 "shr{b}\t{$src, $dst|$dst, $src}",
1958 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1959 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1960 "shr{w}\t{$src, $dst|$dst, $src}",
1961 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1963 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1964 "shr{l}\t{$src, $dst|$dst, $src}",
1965 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1968 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1970 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1971 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1973 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1974 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1976 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1979 let Uses = [CL] in {
1980 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1981 "sar{b}\t{%cl, $dst|$dst, CL}",
1982 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1983 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1984 "sar{w}\t{%cl, $dst|$dst, CL}",
1985 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1986 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1987 "sar{l}\t{%cl, $dst|$dst, CL}",
1988 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1991 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1992 "sar{b}\t{$src2, $dst|$dst, $src2}",
1993 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1994 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1995 "sar{w}\t{$src2, $dst|$dst, $src2}",
1996 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1998 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1999 "sar{l}\t{$src2, $dst|$dst, $src2}",
2000 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2003 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2005 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2006 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2008 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2009 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2011 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2013 let isTwoAddress = 0 in {
2014 let Uses = [CL] in {
2015 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2016 "sar{b}\t{%cl, $dst|$dst, CL}",
2017 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2018 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2019 "sar{w}\t{%cl, $dst|$dst, CL}",
2020 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2021 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2022 "sar{l}\t{%cl, $dst|$dst, CL}",
2023 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2025 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2026 "sar{b}\t{$src, $dst|$dst, $src}",
2027 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2028 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2029 "sar{w}\t{$src, $dst|$dst, $src}",
2030 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2032 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2033 "sar{l}\t{$src, $dst|$dst, $src}",
2034 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2037 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2039 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2040 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2042 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2044 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2046 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2049 // Rotate instructions
2050 // FIXME: provide shorter instructions when imm8 == 1
2051 let Uses = [CL] in {
2052 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
2053 "rol{b}\t{%cl, $dst|$dst, CL}",
2054 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2055 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2056 "rol{w}\t{%cl, $dst|$dst, CL}",
2057 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2058 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2059 "rol{l}\t{%cl, $dst|$dst, CL}",
2060 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2063 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2064 "rol{b}\t{$src2, $dst|$dst, $src2}",
2065 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2066 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2067 "rol{w}\t{$src2, $dst|$dst, $src2}",
2068 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2069 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2070 "rol{l}\t{$src2, $dst|$dst, $src2}",
2071 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2074 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2076 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2077 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2079 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2080 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2082 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2084 let isTwoAddress = 0 in {
2085 let Uses = [CL] in {
2086 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2087 "rol{b}\t{%cl, $dst|$dst, CL}",
2088 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2089 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2090 "rol{w}\t{%cl, $dst|$dst, CL}",
2091 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2092 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2093 "rol{l}\t{%cl, $dst|$dst, CL}",
2094 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2096 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2097 "rol{b}\t{$src, $dst|$dst, $src}",
2098 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2099 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2100 "rol{w}\t{$src, $dst|$dst, $src}",
2101 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2103 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2104 "rol{l}\t{$src, $dst|$dst, $src}",
2105 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2108 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2110 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2111 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2113 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2115 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2117 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2120 let Uses = [CL] in {
2121 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2122 "ror{b}\t{%cl, $dst|$dst, CL}",
2123 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2124 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2125 "ror{w}\t{%cl, $dst|$dst, CL}",
2126 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2127 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2128 "ror{l}\t{%cl, $dst|$dst, CL}",
2129 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2132 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2133 "ror{b}\t{$src2, $dst|$dst, $src2}",
2134 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2135 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2136 "ror{w}\t{$src2, $dst|$dst, $src2}",
2137 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2138 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2139 "ror{l}\t{$src2, $dst|$dst, $src2}",
2140 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2143 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2145 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2146 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2148 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2149 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2151 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2153 let isTwoAddress = 0 in {
2154 let Uses = [CL] in {
2155 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2156 "ror{b}\t{%cl, $dst|$dst, CL}",
2157 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2158 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2159 "ror{w}\t{%cl, $dst|$dst, CL}",
2160 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2161 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2162 "ror{l}\t{%cl, $dst|$dst, CL}",
2163 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2165 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2166 "ror{b}\t{$src, $dst|$dst, $src}",
2167 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2168 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2169 "ror{w}\t{$src, $dst|$dst, $src}",
2170 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2172 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2173 "ror{l}\t{$src, $dst|$dst, $src}",
2174 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2177 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2179 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2180 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2182 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2184 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2186 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2191 // Double shift instructions (generalizations of rotate)
2192 let Uses = [CL] in {
2193 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2194 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2195 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2196 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2197 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2198 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2199 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2200 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2201 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2203 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2204 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2205 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2209 let isCommutable = 1 in { // These instructions commute to each other.
2210 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2211 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2212 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2213 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2216 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2217 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2218 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2219 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2222 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2223 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2224 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2225 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2228 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2229 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2230 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2231 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2236 let isTwoAddress = 0 in {
2237 let Uses = [CL] in {
2238 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2239 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2240 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2242 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2243 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2244 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2247 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2248 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2249 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2250 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2251 (i8 imm:$src3)), addr:$dst)]>,
2253 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2254 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2255 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2256 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2257 (i8 imm:$src3)), addr:$dst)]>,
2260 let Uses = [CL] in {
2261 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2262 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2263 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2264 addr:$dst)]>, TB, OpSize;
2265 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2266 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2267 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2268 addr:$dst)]>, TB, OpSize;
2270 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2271 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2272 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2273 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2274 (i8 imm:$src3)), addr:$dst)]>,
2276 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2277 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2278 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2279 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2280 (i8 imm:$src3)), addr:$dst)]>,
2283 } // Defs = [EFLAGS]
2287 let Defs = [EFLAGS] in {
2288 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2289 // Register-Register Addition
2290 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2291 (ins GR8 :$src1, GR8 :$src2),
2292 "add{b}\t{$src2, $dst|$dst, $src2}",
2293 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
2294 (implicit EFLAGS)]>;
2296 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2297 // Register-Register Addition
2298 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2299 (ins GR16:$src1, GR16:$src2),
2300 "add{w}\t{$src2, $dst|$dst, $src2}",
2301 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2302 (implicit EFLAGS)]>, OpSize;
2303 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2304 (ins GR32:$src1, GR32:$src2),
2305 "add{l}\t{$src2, $dst|$dst, $src2}",
2306 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2307 (implicit EFLAGS)]>;
2308 } // end isConvertibleToThreeAddress
2309 } // end isCommutable
2311 // Register-Memory Addition
2312 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2313 (ins GR8 :$src1, i8mem :$src2),
2314 "add{b}\t{$src2, $dst|$dst, $src2}",
2315 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2316 (implicit EFLAGS)]>;
2317 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2318 (ins GR16:$src1, i16mem:$src2),
2319 "add{w}\t{$src2, $dst|$dst, $src2}",
2320 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2321 (implicit EFLAGS)]>, OpSize;
2322 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2323 (ins GR32:$src1, i32mem:$src2),
2324 "add{l}\t{$src2, $dst|$dst, $src2}",
2325 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2326 (implicit EFLAGS)]>;
2328 // Register-Integer Addition
2329 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2330 "add{b}\t{$src2, $dst|$dst, $src2}",
2331 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2332 (implicit EFLAGS)]>;
2334 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2335 // Register-Integer Addition
2336 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2337 (ins GR16:$src1, i16imm:$src2),
2338 "add{w}\t{$src2, $dst|$dst, $src2}",
2339 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2340 (implicit EFLAGS)]>, OpSize;
2341 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2342 (ins GR32:$src1, i32imm:$src2),
2343 "add{l}\t{$src2, $dst|$dst, $src2}",
2344 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2345 (implicit EFLAGS)]>;
2346 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2347 (ins GR16:$src1, i16i8imm:$src2),
2348 "add{w}\t{$src2, $dst|$dst, $src2}",
2349 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2350 (implicit EFLAGS)]>, OpSize;
2351 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2352 (ins GR32:$src1, i32i8imm:$src2),
2353 "add{l}\t{$src2, $dst|$dst, $src2}",
2354 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2355 (implicit EFLAGS)]>;
2358 let isTwoAddress = 0 in {
2359 // Memory-Register Addition
2360 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2361 "add{b}\t{$src2, $dst|$dst, $src2}",
2362 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2363 (implicit EFLAGS)]>;
2364 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2365 "add{w}\t{$src2, $dst|$dst, $src2}",
2366 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2367 (implicit EFLAGS)]>, OpSize;
2368 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2369 "add{l}\t{$src2, $dst|$dst, $src2}",
2370 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2371 (implicit EFLAGS)]>;
2372 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2373 "add{b}\t{$src2, $dst|$dst, $src2}",
2374 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2375 (implicit EFLAGS)]>;
2376 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2377 "add{w}\t{$src2, $dst|$dst, $src2}",
2378 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2379 (implicit EFLAGS)]>, OpSize;
2380 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2381 "add{l}\t{$src2, $dst|$dst, $src2}",
2382 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2383 (implicit EFLAGS)]>;
2384 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2385 "add{w}\t{$src2, $dst|$dst, $src2}",
2386 [(store (add (load addr:$dst), i16immSExt8:$src2),
2388 (implicit EFLAGS)]>, OpSize;
2389 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2390 "add{l}\t{$src2, $dst|$dst, $src2}",
2391 [(store (add (load addr:$dst), i32immSExt8:$src2),
2393 (implicit EFLAGS)]>;
2396 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2397 "add\t{$src, %al|%al, $src}", []>;
2398 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2399 "add\t{$src, %ax|%ax, $src}", []>, OpSize;
2400 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2401 "add\t{$src, %eax|%eax, $src}", []>;
2404 let Uses = [EFLAGS] in {
2405 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2406 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2407 "adc{b}\t{$src2, $dst|$dst, $src2}",
2408 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2409 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2410 (ins GR16:$src1, GR16:$src2),
2411 "adc{w}\t{$src2, $dst|$dst, $src2}",
2412 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2413 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2414 (ins GR32:$src1, GR32:$src2),
2415 "adc{l}\t{$src2, $dst|$dst, $src2}",
2416 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2418 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2419 (ins GR8:$src1, i8mem:$src2),
2420 "adc{b}\t{$src2, $dst|$dst, $src2}",
2421 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2422 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2423 (ins GR16:$src1, i16mem:$src2),
2424 "adc{w}\t{$src2, $dst|$dst, $src2}",
2425 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2427 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2428 (ins GR32:$src1, i32mem:$src2),
2429 "adc{l}\t{$src2, $dst|$dst, $src2}",
2430 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2431 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2432 "adc{b}\t{$src2, $dst|$dst, $src2}",
2433 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2434 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2435 (ins GR16:$src1, i16imm:$src2),
2436 "adc{w}\t{$src2, $dst|$dst, $src2}",
2437 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2438 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2439 (ins GR16:$src1, i16i8imm:$src2),
2440 "adc{w}\t{$src2, $dst|$dst, $src2}",
2441 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2443 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2444 (ins GR32:$src1, i32imm:$src2),
2445 "adc{l}\t{$src2, $dst|$dst, $src2}",
2446 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2447 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2448 (ins GR32:$src1, i32i8imm:$src2),
2449 "adc{l}\t{$src2, $dst|$dst, $src2}",
2450 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2452 let isTwoAddress = 0 in {
2453 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2454 "adc{b}\t{$src2, $dst|$dst, $src2}",
2455 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2456 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2457 "adc{w}\t{$src2, $dst|$dst, $src2}",
2458 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2460 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2461 "adc{l}\t{$src2, $dst|$dst, $src2}",
2462 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2463 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2464 "adc{b}\t{$src2, $dst|$dst, $src2}",
2465 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2466 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2467 "adc{w}\t{$src2, $dst|$dst, $src2}",
2468 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2470 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2471 "adc{w}\t{$src2, $dst|$dst, $src2}",
2472 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2474 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2475 "adc{l}\t{$src2, $dst|$dst, $src2}",
2476 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2477 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2478 "adc{l}\t{$src2, $dst|$dst, $src2}",
2479 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2481 } // Uses = [EFLAGS]
2483 // Register-Register Subtraction
2484 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2485 "sub{b}\t{$src2, $dst|$dst, $src2}",
2486 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2487 (implicit EFLAGS)]>;
2488 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2489 "sub{w}\t{$src2, $dst|$dst, $src2}",
2490 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2491 (implicit EFLAGS)]>, OpSize;
2492 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2493 "sub{l}\t{$src2, $dst|$dst, $src2}",
2494 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2495 (implicit EFLAGS)]>;
2497 // Register-Memory Subtraction
2498 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2499 (ins GR8 :$src1, i8mem :$src2),
2500 "sub{b}\t{$src2, $dst|$dst, $src2}",
2501 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2502 (implicit EFLAGS)]>;
2503 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2504 (ins GR16:$src1, i16mem:$src2),
2505 "sub{w}\t{$src2, $dst|$dst, $src2}",
2506 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2507 (implicit EFLAGS)]>, OpSize;
2508 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2509 (ins GR32:$src1, i32mem:$src2),
2510 "sub{l}\t{$src2, $dst|$dst, $src2}",
2511 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2512 (implicit EFLAGS)]>;
2514 // Register-Integer Subtraction
2515 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2516 (ins GR8:$src1, i8imm:$src2),
2517 "sub{b}\t{$src2, $dst|$dst, $src2}",
2518 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2519 (implicit EFLAGS)]>;
2520 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2521 (ins GR16:$src1, i16imm:$src2),
2522 "sub{w}\t{$src2, $dst|$dst, $src2}",
2523 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2524 (implicit EFLAGS)]>, OpSize;
2525 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2526 (ins GR32:$src1, i32imm:$src2),
2527 "sub{l}\t{$src2, $dst|$dst, $src2}",
2528 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2529 (implicit EFLAGS)]>;
2530 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2531 (ins GR16:$src1, i16i8imm:$src2),
2532 "sub{w}\t{$src2, $dst|$dst, $src2}",
2533 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2534 (implicit EFLAGS)]>, OpSize;
2535 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2536 (ins GR32:$src1, i32i8imm:$src2),
2537 "sub{l}\t{$src2, $dst|$dst, $src2}",
2538 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2539 (implicit EFLAGS)]>;
2541 let isTwoAddress = 0 in {
2542 // Memory-Register Subtraction
2543 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2544 "sub{b}\t{$src2, $dst|$dst, $src2}",
2545 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2546 (implicit EFLAGS)]>;
2547 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2548 "sub{w}\t{$src2, $dst|$dst, $src2}",
2549 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2550 (implicit EFLAGS)]>, OpSize;
2551 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2552 "sub{l}\t{$src2, $dst|$dst, $src2}",
2553 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2554 (implicit EFLAGS)]>;
2556 // Memory-Integer Subtraction
2557 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2558 "sub{b}\t{$src2, $dst|$dst, $src2}",
2559 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2560 (implicit EFLAGS)]>;
2561 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2562 "sub{w}\t{$src2, $dst|$dst, $src2}",
2563 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2564 (implicit EFLAGS)]>, OpSize;
2565 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2566 "sub{l}\t{$src2, $dst|$dst, $src2}",
2567 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2568 (implicit EFLAGS)]>;
2569 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2570 "sub{w}\t{$src2, $dst|$dst, $src2}",
2571 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2573 (implicit EFLAGS)]>, OpSize;
2574 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2575 "sub{l}\t{$src2, $dst|$dst, $src2}",
2576 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2578 (implicit EFLAGS)]>;
2581 let Uses = [EFLAGS] in {
2582 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2583 (ins GR8:$src1, GR8:$src2),
2584 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2585 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
2586 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2587 (ins GR16:$src1, GR16:$src2),
2588 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2589 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
2590 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
2591 (ins GR32:$src1, GR32:$src2),
2592 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2593 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2595 let isTwoAddress = 0 in {
2596 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2597 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2598 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
2599 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2600 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2601 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
2603 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2604 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2605 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2606 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2607 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2608 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2609 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
2610 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2611 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2613 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2614 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2615 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2617 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2618 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2619 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2620 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2621 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2622 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2624 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
2625 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2626 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
2627 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
2628 (ins GR16:$src1, i16mem:$src2),
2629 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2630 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
2632 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
2633 (ins GR32:$src1, i32mem:$src2),
2634 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2635 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2636 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2637 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2638 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
2639 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
2640 (ins GR16:$src1, i16imm:$src2),
2641 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2642 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
2643 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
2644 (ins GR16:$src1, i16i8imm:$src2),
2645 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2646 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
2648 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
2649 (ins GR32:$src1, i32imm:$src2),
2650 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2651 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2652 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
2653 (ins GR32:$src1, i32i8imm:$src2),
2654 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2655 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2656 } // Uses = [EFLAGS]
2657 } // Defs = [EFLAGS]
2659 let Defs = [EFLAGS] in {
2660 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2661 // Register-Register Signed Integer Multiply
2662 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2663 "imul{w}\t{$src2, $dst|$dst, $src2}",
2664 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
2665 (implicit EFLAGS)]>, TB, OpSize;
2666 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2667 "imul{l}\t{$src2, $dst|$dst, $src2}",
2668 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
2669 (implicit EFLAGS)]>, TB;
2672 // Register-Memory Signed Integer Multiply
2673 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
2674 (ins GR16:$src1, i16mem:$src2),
2675 "imul{w}\t{$src2, $dst|$dst, $src2}",
2676 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
2677 (implicit EFLAGS)]>, TB, OpSize;
2678 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2679 "imul{l}\t{$src2, $dst|$dst, $src2}",
2680 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
2681 (implicit EFLAGS)]>, TB;
2682 } // Defs = [EFLAGS]
2683 } // end Two Address instructions
2685 // Suprisingly enough, these are not two address instructions!
2686 let Defs = [EFLAGS] in {
2687 // Register-Integer Signed Integer Multiply
2688 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2689 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2690 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2691 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
2692 (implicit EFLAGS)]>, OpSize;
2693 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2694 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2695 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2696 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
2697 (implicit EFLAGS)]>;
2698 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2699 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2700 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2701 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
2702 (implicit EFLAGS)]>, OpSize;
2703 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2704 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2705 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2706 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
2707 (implicit EFLAGS)]>;
2709 // Memory-Integer Signed Integer Multiply
2710 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2711 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2712 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2713 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
2714 (implicit EFLAGS)]>, OpSize;
2715 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2716 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2717 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2718 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
2719 (implicit EFLAGS)]>;
2720 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2721 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2722 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2723 [(set GR16:$dst, (mul (load addr:$src1),
2724 i16immSExt8:$src2)),
2725 (implicit EFLAGS)]>, OpSize;
2726 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2727 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2728 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2729 [(set GR32:$dst, (mul (load addr:$src1),
2730 i32immSExt8:$src2)),
2731 (implicit EFLAGS)]>;
2732 } // Defs = [EFLAGS]
2734 //===----------------------------------------------------------------------===//
2735 // Test instructions are just like AND, except they don't generate a result.
2737 let Defs = [EFLAGS] in {
2738 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2739 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2740 "test{b}\t{$src2, $src1|$src1, $src2}",
2741 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
2742 (implicit EFLAGS)]>;
2743 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2744 "test{w}\t{$src2, $src1|$src1, $src2}",
2745 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
2746 (implicit EFLAGS)]>,
2748 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2749 "test{l}\t{$src2, $src1|$src1, $src2}",
2750 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
2751 (implicit EFLAGS)]>;
2754 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2755 "test{b}\t{$src2, $src1|$src1, $src2}",
2756 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2757 (implicit EFLAGS)]>;
2758 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2759 "test{w}\t{$src2, $src1|$src1, $src2}",
2760 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2761 (implicit EFLAGS)]>, OpSize;
2762 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2763 "test{l}\t{$src2, $src1|$src1, $src2}",
2764 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2765 (implicit EFLAGS)]>;
2767 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2768 (outs), (ins GR8:$src1, i8imm:$src2),
2769 "test{b}\t{$src2, $src1|$src1, $src2}",
2770 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
2771 (implicit EFLAGS)]>;
2772 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2773 (outs), (ins GR16:$src1, i16imm:$src2),
2774 "test{w}\t{$src2, $src1|$src1, $src2}",
2775 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
2776 (implicit EFLAGS)]>, OpSize;
2777 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2778 (outs), (ins GR32:$src1, i32imm:$src2),
2779 "test{l}\t{$src2, $src1|$src1, $src2}",
2780 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
2781 (implicit EFLAGS)]>;
2783 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2784 (outs), (ins i8mem:$src1, i8imm:$src2),
2785 "test{b}\t{$src2, $src1|$src1, $src2}",
2786 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2787 (implicit EFLAGS)]>;
2788 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2789 (outs), (ins i16mem:$src1, i16imm:$src2),
2790 "test{w}\t{$src2, $src1|$src1, $src2}",
2791 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2792 (implicit EFLAGS)]>, OpSize;
2793 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2794 (outs), (ins i32mem:$src1, i32imm:$src2),
2795 "test{l}\t{$src2, $src1|$src1, $src2}",
2796 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2797 (implicit EFLAGS)]>;
2798 } // Defs = [EFLAGS]
2801 // Condition code ops, incl. set if equal/not equal/...
2802 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2803 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2804 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2805 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2807 let Uses = [EFLAGS] in {
2808 def SETEr : I<0x94, MRM0r,
2809 (outs GR8 :$dst), (ins),
2811 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2813 def SETEm : I<0x94, MRM0m,
2814 (outs), (ins i8mem:$dst),
2816 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2819 def SETNEr : I<0x95, MRM0r,
2820 (outs GR8 :$dst), (ins),
2822 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2824 def SETNEm : I<0x95, MRM0m,
2825 (outs), (ins i8mem:$dst),
2827 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2830 def SETLr : I<0x9C, MRM0r,
2831 (outs GR8 :$dst), (ins),
2833 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2834 TB; // GR8 = < signed
2835 def SETLm : I<0x9C, MRM0m,
2836 (outs), (ins i8mem:$dst),
2838 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2839 TB; // [mem8] = < signed
2841 def SETGEr : I<0x9D, MRM0r,
2842 (outs GR8 :$dst), (ins),
2844 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2845 TB; // GR8 = >= signed
2846 def SETGEm : I<0x9D, MRM0m,
2847 (outs), (ins i8mem:$dst),
2849 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2850 TB; // [mem8] = >= signed
2852 def SETLEr : I<0x9E, MRM0r,
2853 (outs GR8 :$dst), (ins),
2855 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2856 TB; // GR8 = <= signed
2857 def SETLEm : I<0x9E, MRM0m,
2858 (outs), (ins i8mem:$dst),
2860 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2861 TB; // [mem8] = <= signed
2863 def SETGr : I<0x9F, MRM0r,
2864 (outs GR8 :$dst), (ins),
2866 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2867 TB; // GR8 = > signed
2868 def SETGm : I<0x9F, MRM0m,
2869 (outs), (ins i8mem:$dst),
2871 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2872 TB; // [mem8] = > signed
2874 def SETBr : I<0x92, MRM0r,
2875 (outs GR8 :$dst), (ins),
2877 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2878 TB; // GR8 = < unsign
2879 def SETBm : I<0x92, MRM0m,
2880 (outs), (ins i8mem:$dst),
2882 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2883 TB; // [mem8] = < unsign
2885 def SETAEr : I<0x93, MRM0r,
2886 (outs GR8 :$dst), (ins),
2888 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2889 TB; // GR8 = >= unsign
2890 def SETAEm : I<0x93, MRM0m,
2891 (outs), (ins i8mem:$dst),
2893 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2894 TB; // [mem8] = >= unsign
2896 def SETBEr : I<0x96, MRM0r,
2897 (outs GR8 :$dst), (ins),
2899 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2900 TB; // GR8 = <= unsign
2901 def SETBEm : I<0x96, MRM0m,
2902 (outs), (ins i8mem:$dst),
2904 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2905 TB; // [mem8] = <= unsign
2907 def SETAr : I<0x97, MRM0r,
2908 (outs GR8 :$dst), (ins),
2910 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2911 TB; // GR8 = > signed
2912 def SETAm : I<0x97, MRM0m,
2913 (outs), (ins i8mem:$dst),
2915 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2916 TB; // [mem8] = > signed
2918 def SETSr : I<0x98, MRM0r,
2919 (outs GR8 :$dst), (ins),
2921 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2922 TB; // GR8 = <sign bit>
2923 def SETSm : I<0x98, MRM0m,
2924 (outs), (ins i8mem:$dst),
2926 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2927 TB; // [mem8] = <sign bit>
2928 def SETNSr : I<0x99, MRM0r,
2929 (outs GR8 :$dst), (ins),
2931 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2932 TB; // GR8 = !<sign bit>
2933 def SETNSm : I<0x99, MRM0m,
2934 (outs), (ins i8mem:$dst),
2936 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2937 TB; // [mem8] = !<sign bit>
2939 def SETPr : I<0x9A, MRM0r,
2940 (outs GR8 :$dst), (ins),
2942 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2944 def SETPm : I<0x9A, MRM0m,
2945 (outs), (ins i8mem:$dst),
2947 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2948 TB; // [mem8] = parity
2949 def SETNPr : I<0x9B, MRM0r,
2950 (outs GR8 :$dst), (ins),
2952 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2953 TB; // GR8 = not parity
2954 def SETNPm : I<0x9B, MRM0m,
2955 (outs), (ins i8mem:$dst),
2957 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2958 TB; // [mem8] = not parity
2960 def SETOr : I<0x90, MRM0r,
2961 (outs GR8 :$dst), (ins),
2963 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
2964 TB; // GR8 = overflow
2965 def SETOm : I<0x90, MRM0m,
2966 (outs), (ins i8mem:$dst),
2968 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
2969 TB; // [mem8] = overflow
2970 def SETNOr : I<0x91, MRM0r,
2971 (outs GR8 :$dst), (ins),
2973 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
2974 TB; // GR8 = not overflow
2975 def SETNOm : I<0x91, MRM0m,
2976 (outs), (ins i8mem:$dst),
2978 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
2979 TB; // [mem8] = not overflow
2980 } // Uses = [EFLAGS]
2983 // Integer comparisons
2984 let Defs = [EFLAGS] in {
2985 def CMP8rr : I<0x38, MRMDestReg,
2986 (outs), (ins GR8 :$src1, GR8 :$src2),
2987 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2988 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2989 def CMP16rr : I<0x39, MRMDestReg,
2990 (outs), (ins GR16:$src1, GR16:$src2),
2991 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2992 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2993 def CMP32rr : I<0x39, MRMDestReg,
2994 (outs), (ins GR32:$src1, GR32:$src2),
2995 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2996 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2997 def CMP8mr : I<0x38, MRMDestMem,
2998 (outs), (ins i8mem :$src1, GR8 :$src2),
2999 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3000 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
3001 (implicit EFLAGS)]>;
3002 def CMP16mr : I<0x39, MRMDestMem,
3003 (outs), (ins i16mem:$src1, GR16:$src2),
3004 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3005 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
3006 (implicit EFLAGS)]>, OpSize;
3007 def CMP32mr : I<0x39, MRMDestMem,
3008 (outs), (ins i32mem:$src1, GR32:$src2),
3009 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3010 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
3011 (implicit EFLAGS)]>;
3012 def CMP8rm : I<0x3A, MRMSrcMem,
3013 (outs), (ins GR8 :$src1, i8mem :$src2),
3014 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3015 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
3016 (implicit EFLAGS)]>;
3017 def CMP16rm : I<0x3B, MRMSrcMem,
3018 (outs), (ins GR16:$src1, i16mem:$src2),
3019 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3020 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
3021 (implicit EFLAGS)]>, OpSize;
3022 def CMP32rm : I<0x3B, MRMSrcMem,
3023 (outs), (ins GR32:$src1, i32mem:$src2),
3024 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3025 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
3026 (implicit EFLAGS)]>;
3027 def CMP8ri : Ii8<0x80, MRM7r,
3028 (outs), (ins GR8:$src1, i8imm:$src2),
3029 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3030 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
3031 def CMP16ri : Ii16<0x81, MRM7r,
3032 (outs), (ins GR16:$src1, i16imm:$src2),
3033 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3034 [(X86cmp GR16:$src1, imm:$src2),
3035 (implicit EFLAGS)]>, OpSize;
3036 def CMP32ri : Ii32<0x81, MRM7r,
3037 (outs), (ins GR32:$src1, i32imm:$src2),
3038 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3039 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
3040 def CMP8mi : Ii8 <0x80, MRM7m,
3041 (outs), (ins i8mem :$src1, i8imm :$src2),
3042 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3043 [(X86cmp (loadi8 addr:$src1), imm:$src2),
3044 (implicit EFLAGS)]>;
3045 def CMP16mi : Ii16<0x81, MRM7m,
3046 (outs), (ins i16mem:$src1, i16imm:$src2),
3047 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3048 [(X86cmp (loadi16 addr:$src1), imm:$src2),
3049 (implicit EFLAGS)]>, OpSize;
3050 def CMP32mi : Ii32<0x81, MRM7m,
3051 (outs), (ins i32mem:$src1, i32imm:$src2),
3052 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3053 [(X86cmp (loadi32 addr:$src1), imm:$src2),
3054 (implicit EFLAGS)]>;
3055 def CMP16ri8 : Ii8<0x83, MRM7r,
3056 (outs), (ins GR16:$src1, i16i8imm:$src2),
3057 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3058 [(X86cmp GR16:$src1, i16immSExt8:$src2),
3059 (implicit EFLAGS)]>, OpSize;
3060 def CMP16mi8 : Ii8<0x83, MRM7m,
3061 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3062 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3063 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
3064 (implicit EFLAGS)]>, OpSize;
3065 def CMP32mi8 : Ii8<0x83, MRM7m,
3066 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3067 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3068 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
3069 (implicit EFLAGS)]>;
3070 def CMP32ri8 : Ii8<0x83, MRM7r,
3071 (outs), (ins GR32:$src1, i32i8imm:$src2),
3072 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3073 [(X86cmp GR32:$src1, i32immSExt8:$src2),
3074 (implicit EFLAGS)]>;
3075 } // Defs = [EFLAGS]
3078 // TODO: BTC, BTR, and BTS
3079 let Defs = [EFLAGS] in {
3080 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3081 "bt{w}\t{$src2, $src1|$src1, $src2}",
3082 [(X86bt GR16:$src1, GR16:$src2),
3083 (implicit EFLAGS)]>, OpSize, TB;
3084 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3085 "bt{l}\t{$src2, $src1|$src1, $src2}",
3086 [(X86bt GR32:$src1, GR32:$src2),
3087 (implicit EFLAGS)]>, TB;
3089 // Unlike with the register+register form, the memory+register form of the
3090 // bt instruction does not ignore the high bits of the index. From ISel's
3091 // perspective, this is pretty bizarre. Disable these instructions for now.
3092 //def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3093 // "bt{w}\t{$src2, $src1|$src1, $src2}",
3094 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3095 // (implicit EFLAGS)]>, OpSize, TB, Requires<[FastBTMem]>;
3096 //def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3097 // "bt{l}\t{$src2, $src1|$src1, $src2}",
3098 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3099 // (implicit EFLAGS)]>, TB, Requires<[FastBTMem]>;
3101 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3102 "bt{w}\t{$src2, $src1|$src1, $src2}",
3103 [(X86bt GR16:$src1, i16immSExt8:$src2),
3104 (implicit EFLAGS)]>, OpSize, TB;
3105 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3106 "bt{l}\t{$src2, $src1|$src1, $src2}",
3107 [(X86bt GR32:$src1, i32immSExt8:$src2),
3108 (implicit EFLAGS)]>, TB;
3109 // Note that these instructions don't need FastBTMem because that
3110 // only applies when the other operand is in a register. When it's
3111 // an immediate, bt is still fast.
3112 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3113 "bt{w}\t{$src2, $src1|$src1, $src2}",
3114 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
3115 (implicit EFLAGS)]>, OpSize, TB;
3116 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3117 "bt{l}\t{$src2, $src1|$src1, $src2}",
3118 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
3119 (implicit EFLAGS)]>, TB;
3120 } // Defs = [EFLAGS]
3122 // Sign/Zero extenders
3123 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3124 // of the register here. This has a smaller encoding and avoids a
3125 // partial-register update.
3126 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3127 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3128 [(set GR16:$dst, (sext GR8:$src))]>, TB;
3129 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3130 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3131 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3132 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3133 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3134 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3135 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3136 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3137 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3138 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3139 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3140 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3141 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3142 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3143 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3145 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3146 // of the register here. This has a smaller encoding and avoids a
3147 // partial-register update.
3148 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3149 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3150 [(set GR16:$dst, (zext GR8:$src))]>, TB;
3151 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3152 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3153 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3154 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3155 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3156 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3157 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3158 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3159 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3160 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3161 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3162 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3163 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3164 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3165 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3167 // These are the same as the regular regular MOVZX32rr8 and MOVZX32rm8
3168 // except that they use GR32_NOREX for the output operand register class
3169 // instead of GR32. This allows them to operate on h registers on x86-64.
3170 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3171 (outs GR32_NOREX:$dst), (ins GR8:$src),
3172 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3175 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3176 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3177 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3180 let neverHasSideEffects = 1 in {
3181 let Defs = [AX], Uses = [AL] in
3182 def CBW : I<0x98, RawFrm, (outs), (ins),
3183 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3184 let Defs = [EAX], Uses = [AX] in
3185 def CWDE : I<0x98, RawFrm, (outs), (ins),
3186 "{cwtl|cwde}", []>; // EAX = signext(AX)
3188 let Defs = [AX,DX], Uses = [AX] in
3189 def CWD : I<0x99, RawFrm, (outs), (ins),
3190 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3191 let Defs = [EAX,EDX], Uses = [EAX] in
3192 def CDQ : I<0x99, RawFrm, (outs), (ins),
3193 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3196 //===----------------------------------------------------------------------===//
3197 // Alias Instructions
3198 //===----------------------------------------------------------------------===//
3200 // Alias instructions that map movr0 to xor.
3201 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3202 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3203 isCodeGenOnly = 1 in {
3204 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
3205 "xor{b}\t$dst, $dst",
3206 [(set GR8:$dst, 0)]>;
3207 // Use xorl instead of xorw since we don't care about the high 16 bits,
3208 // it's smaller, and it avoids a partial-register update.
3209 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3210 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
3211 [(set GR16:$dst, 0)]>;
3212 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
3213 "xor{l}\t$dst, $dst",
3214 [(set GR32:$dst, 0)]>;
3217 //===----------------------------------------------------------------------===//
3218 // Thread Local Storage Instructions
3221 // All calls clobber the non-callee saved registers. ESP is marked as
3222 // a use to prevent stack-pointer assignments that appear immediately
3223 // before calls from potentially appearing dead.
3224 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3225 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3226 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3227 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3229 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3230 "leal\t$sym, %eax; "
3231 "call\t___tls_get_addr@PLT",
3232 [(X86tlsaddr tls32addr:$sym)]>,
3233 Requires<[In32BitMode]>;
3235 let AddedComplexity = 5, isCodeGenOnly = 1 in
3236 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3237 "movl\t%gs:$src, $dst",
3238 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3240 let AddedComplexity = 5, isCodeGenOnly = 1 in
3241 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3242 "movl\t%fs:$src, $dst",
3243 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3245 //===----------------------------------------------------------------------===//
3246 // DWARF Pseudo Instructions
3249 def DWARF_LOC : I<0, Pseudo, (outs),
3250 (ins i32imm:$line, i32imm:$col, i32imm:$file),
3251 ".loc\t$file $line $col",
3252 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
3255 //===----------------------------------------------------------------------===//
3256 // EH Pseudo Instructions
3258 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3259 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3260 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3261 "ret\t#eh_return, addr: $addr",
3262 [(X86ehret GR32:$addr)]>;
3266 //===----------------------------------------------------------------------===//
3270 // Atomic swap. These are just normal xchg instructions. But since a memory
3271 // operand is referenced, the atomicity is ensured.
3272 let Constraints = "$val = $dst" in {
3273 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3274 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3275 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3276 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3277 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3278 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3280 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3281 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3282 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3285 // Atomic compare and swap.
3286 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3287 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3289 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3290 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3292 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3293 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
3296 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3299 let Defs = [AX, EFLAGS], Uses = [AX] in {
3300 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3302 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3303 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3305 let Defs = [AL, EFLAGS], Uses = [AL] in {
3306 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3308 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3309 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3312 // Atomic exchange and add
3313 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3314 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3316 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3317 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3319 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3321 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3322 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3324 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3326 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3327 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3331 // Optimized codegen when the non-memory output is not used.
3332 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3333 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3335 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3336 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3338 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3339 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3341 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3342 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3344 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3345 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3347 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3348 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3350 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3351 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3353 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3354 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3356 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3358 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3360 "inc{b}\t$dst", []>, LOCK;
3361 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3363 "inc{w}\t$dst", []>, OpSize, LOCK;
3364 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3366 "inc{l}\t$dst", []>, LOCK;
3368 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3370 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3371 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3373 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3374 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3376 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3377 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3379 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3380 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3382 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3383 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3385 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3386 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3388 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3389 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3391 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3393 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3395 "dec{b}\t$dst", []>, LOCK;
3396 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3398 "dec{w}\t$dst", []>, OpSize, LOCK;
3399 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3401 "dec{l}\t$dst", []>, LOCK;
3403 // Atomic exchange, and, or, xor
3404 let Constraints = "$val = $dst", Defs = [EFLAGS],
3405 usesCustomDAGSchedInserter = 1 in {
3406 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3407 "#ATOMAND32 PSEUDO!",
3408 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3409 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3410 "#ATOMOR32 PSEUDO!",
3411 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3412 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3413 "#ATOMXOR32 PSEUDO!",
3414 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3415 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3416 "#ATOMNAND32 PSEUDO!",
3417 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
3418 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3419 "#ATOMMIN32 PSEUDO!",
3420 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
3421 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3422 "#ATOMMAX32 PSEUDO!",
3423 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
3424 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3425 "#ATOMUMIN32 PSEUDO!",
3426 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
3427 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3428 "#ATOMUMAX32 PSEUDO!",
3429 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
3431 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3432 "#ATOMAND16 PSEUDO!",
3433 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
3434 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3435 "#ATOMOR16 PSEUDO!",
3436 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
3437 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3438 "#ATOMXOR16 PSEUDO!",
3439 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
3440 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3441 "#ATOMNAND16 PSEUDO!",
3442 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
3443 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3444 "#ATOMMIN16 PSEUDO!",
3445 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
3446 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3447 "#ATOMMAX16 PSEUDO!",
3448 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
3449 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3450 "#ATOMUMIN16 PSEUDO!",
3451 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
3452 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3453 "#ATOMUMAX16 PSEUDO!",
3454 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
3456 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3457 "#ATOMAND8 PSEUDO!",
3458 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
3459 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3461 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
3462 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3463 "#ATOMXOR8 PSEUDO!",
3464 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
3465 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3466 "#ATOMNAND8 PSEUDO!",
3467 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
3470 let Constraints = "$val1 = $dst1, $val2 = $dst2",
3471 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
3472 Uses = [EAX, EBX, ECX, EDX],
3473 mayLoad = 1, mayStore = 1,
3474 usesCustomDAGSchedInserter = 1 in {
3475 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3476 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3477 "#ATOMAND6432 PSEUDO!", []>;
3478 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3479 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3480 "#ATOMOR6432 PSEUDO!", []>;
3481 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3482 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3483 "#ATOMXOR6432 PSEUDO!", []>;
3484 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3485 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3486 "#ATOMNAND6432 PSEUDO!", []>;
3487 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3488 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3489 "#ATOMADD6432 PSEUDO!", []>;
3490 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3491 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3492 "#ATOMSUB6432 PSEUDO!", []>;
3493 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3494 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3495 "#ATOMSWAP6432 PSEUDO!", []>;
3498 //===----------------------------------------------------------------------===//
3499 // Non-Instruction Patterns
3500 //===----------------------------------------------------------------------===//
3502 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
3503 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
3504 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
3505 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
3506 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
3507 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
3509 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
3510 (ADD32ri GR32:$src1, tconstpool:$src2)>;
3511 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
3512 (ADD32ri GR32:$src1, tjumptable:$src2)>;
3513 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
3514 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
3515 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
3516 (ADD32ri GR32:$src1, texternalsym:$src2)>;
3518 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
3519 (MOV32mi addr:$dst, tglobaladdr:$src)>;
3520 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
3521 (MOV32mi addr:$dst, texternalsym:$src)>;
3525 def : Pat<(X86tcret GR32:$dst, imm:$off),
3526 (TCRETURNri GR32:$dst, imm:$off)>;
3528 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
3529 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3531 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
3532 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3534 // Normal calls, with various flavors of addresses.
3535 def : Pat<(X86call (i32 tglobaladdr:$dst)),
3536 (CALLpcrel32 tglobaladdr:$dst)>;
3537 def : Pat<(X86call (i32 texternalsym:$dst)),
3538 (CALLpcrel32 texternalsym:$dst)>;
3539 def : Pat<(X86call (i32 imm:$dst)),
3540 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
3542 // X86 specific add which produces a flag.
3543 def : Pat<(addc GR32:$src1, GR32:$src2),
3544 (ADD32rr GR32:$src1, GR32:$src2)>;
3545 def : Pat<(addc GR32:$src1, (load addr:$src2)),
3546 (ADD32rm GR32:$src1, addr:$src2)>;
3547 def : Pat<(addc GR32:$src1, imm:$src2),
3548 (ADD32ri GR32:$src1, imm:$src2)>;
3549 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
3550 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3552 def : Pat<(subc GR32:$src1, GR32:$src2),
3553 (SUB32rr GR32:$src1, GR32:$src2)>;
3554 def : Pat<(subc GR32:$src1, (load addr:$src2)),
3555 (SUB32rm GR32:$src1, addr:$src2)>;
3556 def : Pat<(subc GR32:$src1, imm:$src2),
3557 (SUB32ri GR32:$src1, imm:$src2)>;
3558 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
3559 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3563 // TEST R,R is smaller than CMP R,0
3564 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
3565 (TEST8rr GR8:$src1, GR8:$src1)>;
3566 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
3567 (TEST16rr GR16:$src1, GR16:$src1)>;
3568 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
3569 (TEST32rr GR32:$src1, GR32:$src1)>;
3571 // Conditional moves with folded loads with operands swapped and conditions
3573 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
3574 (CMOVAE16rm GR16:$src2, addr:$src1)>;
3575 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
3576 (CMOVAE32rm GR32:$src2, addr:$src1)>;
3577 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
3578 (CMOVB16rm GR16:$src2, addr:$src1)>;
3579 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
3580 (CMOVB32rm GR32:$src2, addr:$src1)>;
3581 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
3582 (CMOVNE16rm GR16:$src2, addr:$src1)>;
3583 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
3584 (CMOVNE32rm GR32:$src2, addr:$src1)>;
3585 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
3586 (CMOVE16rm GR16:$src2, addr:$src1)>;
3587 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
3588 (CMOVE32rm GR32:$src2, addr:$src1)>;
3589 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
3590 (CMOVA16rm GR16:$src2, addr:$src1)>;
3591 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
3592 (CMOVA32rm GR32:$src2, addr:$src1)>;
3593 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
3594 (CMOVBE16rm GR16:$src2, addr:$src1)>;
3595 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
3596 (CMOVBE32rm GR32:$src2, addr:$src1)>;
3597 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
3598 (CMOVGE16rm GR16:$src2, addr:$src1)>;
3599 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
3600 (CMOVGE32rm GR32:$src2, addr:$src1)>;
3601 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
3602 (CMOVL16rm GR16:$src2, addr:$src1)>;
3603 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
3604 (CMOVL32rm GR32:$src2, addr:$src1)>;
3605 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
3606 (CMOVG16rm GR16:$src2, addr:$src1)>;
3607 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
3608 (CMOVG32rm GR32:$src2, addr:$src1)>;
3609 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
3610 (CMOVLE16rm GR16:$src2, addr:$src1)>;
3611 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
3612 (CMOVLE32rm GR32:$src2, addr:$src1)>;
3613 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
3614 (CMOVNP16rm GR16:$src2, addr:$src1)>;
3615 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
3616 (CMOVNP32rm GR32:$src2, addr:$src1)>;
3617 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
3618 (CMOVP16rm GR16:$src2, addr:$src1)>;
3619 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
3620 (CMOVP32rm GR32:$src2, addr:$src1)>;
3621 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
3622 (CMOVNS16rm GR16:$src2, addr:$src1)>;
3623 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
3624 (CMOVNS32rm GR32:$src2, addr:$src1)>;
3625 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
3626 (CMOVS16rm GR16:$src2, addr:$src1)>;
3627 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
3628 (CMOVS32rm GR32:$src2, addr:$src1)>;
3629 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
3630 (CMOVNO16rm GR16:$src2, addr:$src1)>;
3631 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
3632 (CMOVNO32rm GR32:$src2, addr:$src1)>;
3633 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
3634 (CMOVO16rm GR16:$src2, addr:$src1)>;
3635 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
3636 (CMOVO32rm GR32:$src2, addr:$src1)>;
3638 // zextload bool -> zextload byte
3639 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3640 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3641 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3643 // extload bool -> extload byte
3644 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3645 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3646 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3647 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
3648 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
3649 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
3651 // anyext. Define these to do an explicit zero-extend to
3652 // avoid partial-register updates.
3653 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
3654 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
3655 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
3657 // (and (i32 load), 255) -> (zextload i8)
3658 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
3659 (MOVZX32rm8 addr:$src)>;
3660 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
3661 (MOVZX32rm16 addr:$src)>;
3663 //===----------------------------------------------------------------------===//
3665 //===----------------------------------------------------------------------===//
3667 // Odd encoding trick: -128 fits into an 8-bit immediate field while
3668 // +128 doesn't, so in this special case use a sub instead of an add.
3669 def : Pat<(add GR16:$src1, 128),
3670 (SUB16ri8 GR16:$src1, -128)>;
3671 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
3672 (SUB16mi8 addr:$dst, -128)>;
3673 def : Pat<(add GR32:$src1, 128),
3674 (SUB32ri8 GR32:$src1, -128)>;
3675 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
3676 (SUB32mi8 addr:$dst, -128)>;
3678 // r & (2^16-1) ==> movz
3679 def : Pat<(and GR32:$src1, 0xffff),
3680 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
3681 // r & (2^8-1) ==> movz
3682 def : Pat<(and GR32:$src1, 0xff),
3683 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src1, GR32_ABCD),
3685 Requires<[In32BitMode]>;
3686 // r & (2^8-1) ==> movz
3687 def : Pat<(and GR16:$src1, 0xff),
3688 (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD),
3690 Requires<[In32BitMode]>;
3692 // sext_inreg patterns
3693 def : Pat<(sext_inreg GR32:$src, i16),
3694 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
3695 def : Pat<(sext_inreg GR32:$src, i8),
3696 (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3698 Requires<[In32BitMode]>;
3699 def : Pat<(sext_inreg GR16:$src, i8),
3700 (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3702 Requires<[In32BitMode]>;
3705 def : Pat<(i16 (trunc GR32:$src)),
3706 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
3707 def : Pat<(i8 (trunc GR32:$src)),
3708 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3710 Requires<[In32BitMode]>;
3711 def : Pat<(i8 (trunc GR16:$src)),
3712 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3714 Requires<[In32BitMode]>;
3716 // h-register tricks
3717 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
3718 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3719 x86_subreg_8bit_hi)>,
3720 Requires<[In32BitMode]>;
3721 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
3722 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3723 x86_subreg_8bit_hi)>,
3724 Requires<[In32BitMode]>;
3725 def : Pat<(srl_su GR16:$src, (i8 8)),
3728 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3729 x86_subreg_8bit_hi)),
3731 Requires<[In32BitMode]>;
3732 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
3733 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3734 x86_subreg_8bit_hi))>,
3735 Requires<[In32BitMode]>;
3736 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
3737 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3738 x86_subreg_8bit_hi))>,
3739 Requires<[In32BitMode]>;
3740 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
3741 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3742 x86_subreg_8bit_hi))>,
3743 Requires<[In32BitMode]>;
3745 // (shl x, 1) ==> (add x, x)
3746 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
3747 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
3748 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
3750 // (shl x (and y, 31)) ==> (shl x, y)
3751 def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
3752 (SHL8rCL GR8:$src1)>;
3753 def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
3754 (SHL16rCL GR16:$src1)>;
3755 def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
3756 (SHL32rCL GR32:$src1)>;
3757 def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3758 (SHL8mCL addr:$dst)>;
3759 def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3760 (SHL16mCL addr:$dst)>;
3761 def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3762 (SHL32mCL addr:$dst)>;
3764 def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
3765 (SHR8rCL GR8:$src1)>;
3766 def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
3767 (SHR16rCL GR16:$src1)>;
3768 def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
3769 (SHR32rCL GR32:$src1)>;
3770 def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3771 (SHR8mCL addr:$dst)>;
3772 def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3773 (SHR16mCL addr:$dst)>;
3774 def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3775 (SHR32mCL addr:$dst)>;
3777 def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
3778 (SAR8rCL GR8:$src1)>;
3779 def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
3780 (SAR16rCL GR16:$src1)>;
3781 def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
3782 (SAR32rCL GR32:$src1)>;
3783 def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3784 (SAR8mCL addr:$dst)>;
3785 def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3786 (SAR16mCL addr:$dst)>;
3787 def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3788 (SAR32mCL addr:$dst)>;
3790 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
3791 def : Pat<(or (srl GR32:$src1, CL:$amt),
3792 (shl GR32:$src2, (sub 32, CL:$amt))),
3793 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3795 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
3796 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3797 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3799 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
3800 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3801 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3803 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3804 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3806 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3808 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3809 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3811 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
3812 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3813 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3815 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
3816 def : Pat<(or (shl GR32:$src1, CL:$amt),
3817 (srl GR32:$src2, (sub 32, CL:$amt))),
3818 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3820 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
3821 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3822 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3824 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
3825 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3826 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3828 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3829 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3831 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3833 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3834 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3836 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
3837 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3838 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3840 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
3841 def : Pat<(or (srl GR16:$src1, CL:$amt),
3842 (shl GR16:$src2, (sub 16, CL:$amt))),
3843 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3845 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
3846 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3847 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3849 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
3850 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3851 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3853 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3854 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3856 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3858 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3859 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3861 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
3862 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3863 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3865 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
3866 def : Pat<(or (shl GR16:$src1, CL:$amt),
3867 (srl GR16:$src2, (sub 16, CL:$amt))),
3868 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3870 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
3871 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3872 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3874 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
3875 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3876 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3878 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3879 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3881 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3883 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3884 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3886 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
3887 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3888 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3890 //===----------------------------------------------------------------------===//
3891 // EFLAGS-defining Patterns
3892 //===----------------------------------------------------------------------===//
3894 // Register-Register Addition with EFLAGS result
3895 def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
3897 (ADD8rr GR8:$src1, GR8:$src2)>;
3898 def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
3900 (ADD16rr GR16:$src1, GR16:$src2)>;
3901 def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
3903 (ADD32rr GR32:$src1, GR32:$src2)>;
3905 // Register-Memory Addition with EFLAGS result
3906 def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
3908 (ADD8rm GR8:$src1, addr:$src2)>;
3909 def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
3911 (ADD16rm GR16:$src1, addr:$src2)>;
3912 def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
3914 (ADD32rm GR32:$src1, addr:$src2)>;
3916 // Register-Integer Addition with EFLAGS result
3917 def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
3919 (ADD8ri GR8:$src1, imm:$src2)>;
3920 def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
3922 (ADD16ri GR16:$src1, imm:$src2)>;
3923 def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
3925 (ADD32ri GR32:$src1, imm:$src2)>;
3926 def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
3928 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
3929 def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
3931 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3933 // Memory-Register Addition with EFLAGS result
3934 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
3937 (ADD8mr addr:$dst, GR8:$src2)>;
3938 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
3941 (ADD16mr addr:$dst, GR16:$src2)>;
3942 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
3945 (ADD32mr addr:$dst, GR32:$src2)>;
3947 // Memory-Integer Addition with EFLAGS result
3948 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
3951 (ADD8mi addr:$dst, imm:$src2)>;
3952 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
3955 (ADD16mi addr:$dst, imm:$src2)>;
3956 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
3959 (ADD32mi addr:$dst, imm:$src2)>;
3960 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
3963 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
3964 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
3967 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
3969 // Register-Register Subtraction with EFLAGS result
3970 def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
3972 (SUB8rr GR8:$src1, GR8:$src2)>;
3973 def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
3975 (SUB16rr GR16:$src1, GR16:$src2)>;
3976 def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
3978 (SUB32rr GR32:$src1, GR32:$src2)>;
3980 // Register-Memory Subtraction with EFLAGS result
3981 def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
3983 (SUB8rm GR8:$src1, addr:$src2)>;
3984 def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
3986 (SUB16rm GR16:$src1, addr:$src2)>;
3987 def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
3989 (SUB32rm GR32:$src1, addr:$src2)>;
3991 // Register-Integer Subtraction with EFLAGS result
3992 def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
3994 (SUB8ri GR8:$src1, imm:$src2)>;
3995 def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
3997 (SUB16ri GR16:$src1, imm:$src2)>;
3998 def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
4000 (SUB32ri GR32:$src1, imm:$src2)>;
4001 def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
4003 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4004 def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
4006 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4008 // Memory-Register Subtraction with EFLAGS result
4009 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
4012 (SUB8mr addr:$dst, GR8:$src2)>;
4013 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
4016 (SUB16mr addr:$dst, GR16:$src2)>;
4017 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
4020 (SUB32mr addr:$dst, GR32:$src2)>;
4022 // Memory-Integer Subtraction with EFLAGS result
4023 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
4026 (SUB8mi addr:$dst, imm:$src2)>;
4027 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
4030 (SUB16mi addr:$dst, imm:$src2)>;
4031 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
4034 (SUB32mi addr:$dst, imm:$src2)>;
4035 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4038 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
4039 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4042 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
4045 // Register-Register Signed Integer Multiply with EFLAGS result
4046 def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
4048 (IMUL16rr GR16:$src1, GR16:$src2)>;
4049 def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
4051 (IMUL32rr GR32:$src1, GR32:$src2)>;
4053 // Register-Memory Signed Integer Multiply with EFLAGS result
4054 def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
4056 (IMUL16rm GR16:$src1, addr:$src2)>;
4057 def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
4059 (IMUL32rm GR32:$src1, addr:$src2)>;
4061 // Register-Integer Signed Integer Multiply with EFLAGS result
4062 def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
4064 (IMUL16rri GR16:$src1, imm:$src2)>;
4065 def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
4067 (IMUL32rri GR32:$src1, imm:$src2)>;
4068 def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
4070 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4071 def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
4073 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4075 // Memory-Integer Signed Integer Multiply with EFLAGS result
4076 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
4078 (IMUL16rmi addr:$src1, imm:$src2)>;
4079 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
4081 (IMUL32rmi addr:$src1, imm:$src2)>;
4082 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
4084 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4085 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
4087 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4089 // Optimize multiply by 2 with EFLAGS result.
4090 let AddedComplexity = 2 in {
4091 def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
4093 (ADD16rr GR16:$src1, GR16:$src1)>;
4095 def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
4097 (ADD32rr GR32:$src1, GR32:$src1)>;
4100 // INC and DEC with EFLAGS result. Note that these do not set CF.
4101 def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
4103 def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
4106 def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
4108 def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
4112 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
4113 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4114 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
4116 (INC16m addr:$dst)>, Requires<[In32BitMode]>;
4117 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
4118 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4119 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
4121 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;
4123 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
4124 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4125 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
4127 (INC32m addr:$dst)>, Requires<[In32BitMode]>;
4128 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
4129 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4130 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
4132 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
4134 //===----------------------------------------------------------------------===//
4135 // Floating Point Stack Support
4136 //===----------------------------------------------------------------------===//
4138 include "X86InstrFPStack.td"
4140 //===----------------------------------------------------------------------===//
4142 //===----------------------------------------------------------------------===//
4144 include "X86Instr64bit.td"
4146 //===----------------------------------------------------------------------===//
4147 // XMM Floating point support (requires SSE / SSE2)
4148 //===----------------------------------------------------------------------===//
4150 include "X86InstrSSE.td"
4152 //===----------------------------------------------------------------------===//
4153 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
4154 //===----------------------------------------------------------------------===//
4156 include "X86InstrMMX.td"