1 //===- X86InstrInfo.td - Main X86 Instruction Definition ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 // RES1, RES2, FLAGS = op LHS, RHS
50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
54 SDTCisInt<0>, SDTCisVT<1, i32>]>;
55 def SDTX86BrCond : SDTypeProfile<0, 3,
56 [SDTCisVT<0, OtherVT>,
57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62 def SDTX86SetCC_C : SDTypeProfile<1, 2,
64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
66 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
68 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
71 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
72 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
74 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
75 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
78 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
80 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
84 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
90 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
92 def SDTX86Void : SDTypeProfile<0, 0, []>;
94 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
96 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
98 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
100 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
102 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
104 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
106 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
107 def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
109 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
111 def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE,
113 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
115 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
117 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
121 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
122 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
123 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
124 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
126 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
127 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
129 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
130 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
132 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
133 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
135 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
136 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
137 SDNPMayLoad, SDNPMemOperand]>;
138 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
139 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
140 SDNPMayLoad, SDNPMemOperand]>;
141 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
142 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
143 SDNPMayLoad, SDNPMemOperand]>;
145 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
146 [SDNPHasChain, SDNPMayStore,
147 SDNPMayLoad, SDNPMemOperand]>;
148 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
149 [SDNPHasChain, SDNPMayStore,
150 SDNPMayLoad, SDNPMemOperand]>;
151 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
152 [SDNPHasChain, SDNPMayStore,
153 SDNPMayLoad, SDNPMemOperand]>;
154 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
155 [SDNPHasChain, SDNPMayStore,
156 SDNPMayLoad, SDNPMemOperand]>;
157 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
158 [SDNPHasChain, SDNPMayStore,
159 SDNPMayLoad, SDNPMemOperand]>;
160 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
161 [SDNPHasChain, SDNPMayStore,
162 SDNPMayLoad, SDNPMemOperand]>;
163 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
164 [SDNPHasChain, SDNPMayStore,
165 SDNPMayLoad, SDNPMemOperand]>;
166 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
167 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
169 def X86vastart_save_xmm_regs :
170 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
171 SDT_X86VASTART_SAVE_XMM_REGS,
172 [SDNPHasChain, SDNPVariadic]>;
174 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
175 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
177 def X86callseq_start :
178 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
179 [SDNPHasChain, SDNPOutGlue]>;
181 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
182 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
184 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
185 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
188 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
189 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
190 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
191 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
194 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
195 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
197 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
198 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
200 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
201 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
203 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
206 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
207 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
209 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
211 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
212 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
214 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
216 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
217 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
219 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
220 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
221 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
223 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
225 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
227 def X86andn_flag : SDNode<"X86ISD::ANDN", SDTBinaryArithWithFlags>;
229 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
231 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
232 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
234 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
237 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
238 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
240 //===----------------------------------------------------------------------===//
241 // X86 Operand Definitions.
244 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
245 // the index operand of an address, to conform to x86 encoding restrictions.
246 def ptr_rc_nosp : PointerLikeRegClass<1>;
248 // *mem - Operand definitions for the funky X86 addressing mode operands.
250 def X86MemAsmOperand : AsmOperandClass {
252 let SuperClasses = [];
254 def X86AbsMemAsmOperand : AsmOperandClass {
256 let SuperClasses = [X86MemAsmOperand];
258 class X86MemOperand<string printMethod> : Operand<iPTR> {
259 let PrintMethod = printMethod;
260 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
261 let ParserMatchClass = X86MemAsmOperand;
264 let OperandType = "OPERAND_MEMORY" in {
265 def opaque32mem : X86MemOperand<"printopaquemem">;
266 def opaque48mem : X86MemOperand<"printopaquemem">;
267 def opaque80mem : X86MemOperand<"printopaquemem">;
268 def opaque512mem : X86MemOperand<"printopaquemem">;
270 def i8mem : X86MemOperand<"printi8mem">;
271 def i16mem : X86MemOperand<"printi16mem">;
272 def i32mem : X86MemOperand<"printi32mem">;
273 def i64mem : X86MemOperand<"printi64mem">;
274 def i128mem : X86MemOperand<"printi128mem">;
275 def i256mem : X86MemOperand<"printi256mem">;
276 def f32mem : X86MemOperand<"printf32mem">;
277 def f64mem : X86MemOperand<"printf64mem">;
278 def f80mem : X86MemOperand<"printf80mem">;
279 def f128mem : X86MemOperand<"printf128mem">;
280 def f256mem : X86MemOperand<"printf256mem">;
283 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
284 // plain GR64, so that it doesn't potentially require a REX prefix.
285 def i8mem_NOREX : Operand<i64> {
286 let PrintMethod = "printi8mem";
287 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
288 let ParserMatchClass = X86MemAsmOperand;
289 let OperandType = "OPERAND_MEMORY";
292 // GPRs available for tailcall.
293 // It represents GR64_TC or GR64_TCW64.
294 def ptr_rc_tailcall : PointerLikeRegClass<2>;
296 // Special i32mem for addresses of load folding tail calls. These are not
297 // allowed to use callee-saved registers since they must be scheduled
298 // after callee-saved register are popped.
299 def i32mem_TC : Operand<i32> {
300 let PrintMethod = "printi32mem";
301 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
302 let ParserMatchClass = X86MemAsmOperand;
303 let OperandType = "OPERAND_MEMORY";
306 // Special i64mem for addresses of load folding tail calls. These are not
307 // allowed to use callee-saved registers since they must be scheduled
308 // after callee-saved register are popped.
309 def i64mem_TC : Operand<i64> {
310 let PrintMethod = "printi64mem";
311 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
312 ptr_rc_tailcall, i32imm, i8imm);
313 let ParserMatchClass = X86MemAsmOperand;
314 let OperandType = "OPERAND_MEMORY";
317 let OperandType = "OPERAND_PCREL",
318 ParserMatchClass = X86AbsMemAsmOperand,
319 PrintMethod = "print_pcrel_imm" in {
320 def i32imm_pcrel : Operand<i32>;
321 def i16imm_pcrel : Operand<i16>;
323 def offset8 : Operand<i64>;
324 def offset16 : Operand<i64>;
325 def offset32 : Operand<i64>;
326 def offset64 : Operand<i64>;
328 // Branch targets have OtherVT type and print as pc-relative values.
329 def brtarget : Operand<OtherVT>;
330 def brtarget8 : Operand<OtherVT>;
334 def SSECC : Operand<i8> {
335 let PrintMethod = "printSSECC";
336 let OperandType = "OPERAND_IMMEDIATE";
339 class ImmSExtAsmOperandClass : AsmOperandClass {
340 let SuperClasses = [ImmAsmOperand];
341 let RenderMethod = "addImmOperands";
344 class ImmZExtAsmOperandClass : AsmOperandClass {
345 let SuperClasses = [ImmAsmOperand];
346 let RenderMethod = "addImmOperands";
349 // Sign-extended immediate classes. We don't need to define the full lattice
350 // here because there is no instruction with an ambiguity between ImmSExti64i32
353 // The strange ranges come from the fact that the assembler always works with
354 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
355 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
358 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
359 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
360 let Name = "ImmSExti64i32";
363 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
364 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
365 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
366 let Name = "ImmSExti16i8";
367 let SuperClasses = [ImmSExti64i32AsmOperand];
370 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
371 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
372 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
373 let Name = "ImmSExti32i8";
377 def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass {
378 let Name = "ImmZExtu32u8";
383 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
384 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
385 let Name = "ImmSExti64i8";
386 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
387 ImmSExti64i32AsmOperand];
390 // A couple of more descriptive operand definitions.
391 // 16-bits but only 8 bits are significant.
392 def i16i8imm : Operand<i16> {
393 let ParserMatchClass = ImmSExti16i8AsmOperand;
394 let OperandType = "OPERAND_IMMEDIATE";
396 // 32-bits but only 8 bits are significant.
397 def i32i8imm : Operand<i32> {
398 let ParserMatchClass = ImmSExti32i8AsmOperand;
399 let OperandType = "OPERAND_IMMEDIATE";
401 // 32-bits but only 8 bits are significant, and those 8 bits are unsigned.
402 def u32u8imm : Operand<i32> {
403 let ParserMatchClass = ImmZExtu32u8AsmOperand;
404 let OperandType = "OPERAND_IMMEDIATE";
407 // 64-bits but only 32 bits are significant.
408 def i64i32imm : Operand<i64> {
409 let ParserMatchClass = ImmSExti64i32AsmOperand;
410 let OperandType = "OPERAND_IMMEDIATE";
413 // 64-bits but only 32 bits are significant, and those bits are treated as being
415 def i64i32imm_pcrel : Operand<i64> {
416 let PrintMethod = "print_pcrel_imm";
417 let ParserMatchClass = X86AbsMemAsmOperand;
418 let OperandType = "OPERAND_PCREL";
421 // 64-bits but only 8 bits are significant.
422 def i64i8imm : Operand<i64> {
423 let ParserMatchClass = ImmSExti64i8AsmOperand;
424 let OperandType = "OPERAND_IMMEDIATE";
427 def lea64_32mem : Operand<i32> {
428 let PrintMethod = "printi32mem";
429 let AsmOperandLowerMethod = "lower_lea64_32mem";
430 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm);
431 let ParserMatchClass = X86MemAsmOperand;
435 //===----------------------------------------------------------------------===//
436 // X86 Complex Pattern Definitions.
439 // Define X86 specific addressing mode.
440 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
441 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
442 [add, sub, mul, X86mul_imm, shl, or, frameindex],
444 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
445 [tglobaltlsaddr], []>;
447 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
448 [add, sub, mul, X86mul_imm, shl, or, frameindex,
451 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
452 [tglobaltlsaddr], []>;
454 //===----------------------------------------------------------------------===//
455 // X86 Instruction Predicate Definitions.
456 def HasCMov : Predicate<"Subtarget->hasCMov()">;
457 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
459 def HasMMX : Predicate<"Subtarget->hasMMX()">;
460 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
461 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
462 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
463 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
464 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
465 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
466 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
467 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
468 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
470 def HasAVX : Predicate<"Subtarget->hasAVX()">;
471 def HasXMMInt : Predicate<"Subtarget->hasXMMInt()">;
473 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
474 def HasAES : Predicate<"Subtarget->hasAES()">;
475 def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">;
476 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
477 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
478 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
479 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
480 def HasF16C : Predicate<"Subtarget->hasF16C()">;
481 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
482 def HasBMI : Predicate<"Subtarget->hasBMI()">;
483 def FPStackf32 : Predicate<"!Subtarget->hasXMM()">;
484 def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">;
485 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
486 def In32BitMode : Predicate<"!Subtarget->is64Bit()">,
487 AssemblerPredicate<"!Mode64Bit">;
488 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
489 AssemblerPredicate<"Mode64Bit">;
490 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
491 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
492 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">,
493 AssemblerPredicate<"ModeNaCl">;
494 def IsNaCl32 : Predicate<"Subtarget->isTargetNaCl32()">,
495 AssemblerPredicate<"ModeNaCl,!Mode64Bit">;
496 def IsNaCl64 : Predicate<"Subtarget->isTargetNaCl64()">,
497 AssemblerPredicate<"ModeNaCl,Mode64Bit">;
498 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">,
499 AssemblerPredicate<"!ModeNaCl">;
500 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
501 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
502 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
503 "TM.getCodeModel() != CodeModel::Kernel">;
504 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
505 "TM.getCodeModel() == CodeModel::Kernel">;
506 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
507 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
508 def OptForSize : Predicate<"OptForSize">;
509 def OptForSpeed : Predicate<"!OptForSize">;
510 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
511 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
513 //===----------------------------------------------------------------------===//
514 // X86 Instruction Format Definitions.
517 include "X86InstrFormats.td"
519 //===----------------------------------------------------------------------===//
520 // Pattern fragments.
523 // X86 specific condition code. These correspond to CondCode in
524 // X86InstrInfo.h. They must be kept in synch.
525 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
526 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
527 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
528 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
529 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
530 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
531 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
532 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
533 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
534 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
535 def X86_COND_NO : PatLeaf<(i8 10)>;
536 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
537 def X86_COND_NS : PatLeaf<(i8 12)>;
538 def X86_COND_O : PatLeaf<(i8 13)>;
539 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
540 def X86_COND_S : PatLeaf<(i8 15)>;
542 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
543 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
544 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
545 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
548 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
551 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
553 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
555 def i64immZExt32SExt8 : ImmLeaf<i64, [{
556 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
559 // Helper fragments for loads.
560 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
561 // known to be 32-bit aligned or better. Ditto for i8 to i16.
562 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
563 LoadSDNode *LD = cast<LoadSDNode>(N);
564 ISD::LoadExtType ExtType = LD->getExtensionType();
565 if (ExtType == ISD::NON_EXTLOAD)
567 if (ExtType == ISD::EXTLOAD)
568 return LD->getAlignment() >= 2 && !LD->isVolatile();
572 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
573 LoadSDNode *LD = cast<LoadSDNode>(N);
574 ISD::LoadExtType ExtType = LD->getExtensionType();
575 if (ExtType == ISD::EXTLOAD)
576 return LD->getAlignment() >= 2 && !LD->isVolatile();
580 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
581 LoadSDNode *LD = cast<LoadSDNode>(N);
582 ISD::LoadExtType ExtType = LD->getExtensionType();
583 if (ExtType == ISD::NON_EXTLOAD)
585 if (ExtType == ISD::EXTLOAD)
586 return LD->getAlignment() >= 4 && !LD->isVolatile();
590 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
591 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
592 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
593 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
594 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
596 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
597 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
598 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
599 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
600 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
601 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
603 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
604 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
605 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
606 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
607 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
608 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
609 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
610 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
611 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
612 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
614 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
615 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
616 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
617 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
618 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
619 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
620 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
621 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
622 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
623 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
626 // An 'and' node with a single use.
627 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
628 return N->hasOneUse();
630 // An 'srl' node with a single use.
631 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
632 return N->hasOneUse();
634 // An 'trunc' node with a single use.
635 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
636 return N->hasOneUse();
639 //===----------------------------------------------------------------------===//
644 let neverHasSideEffects = 1 in {
645 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
646 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
647 "nop{w}\t$zero", []>, TB, OpSize;
648 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
649 "nop{l}\t$zero", []>, TB;
653 // Constructing a stack frame.
654 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
655 "enter\t$len, $lvl", []>;
657 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
658 def LEAVE : I<0xC9, RawFrm,
659 (outs), (ins), "leave", []>, Requires<[In32BitMode]>;
661 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
662 def LEAVE64 : I<0xC9, RawFrm,
663 (outs), (ins), "leave", []>, Requires<[In64BitMode]>;
665 //===----------------------------------------------------------------------===//
666 // Miscellaneous Instructions.
669 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
671 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
673 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
674 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
676 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
678 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
679 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
681 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
682 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
683 Requires<[In32BitMode]>;
686 let mayStore = 1 in {
687 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
689 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
690 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
692 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
694 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
695 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
697 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
698 "push{l}\t$imm", []>;
699 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
700 "push{w}\t$imm", []>, OpSize;
701 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
702 "push{l}\t$imm", []>;
704 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
705 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
706 Requires<[In32BitMode]>;
711 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
713 def POP64r : I<0x58, AddRegFrm,
714 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
715 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
716 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
718 let mayStore = 1 in {
719 def PUSH64r : I<0x50, AddRegFrm,
720 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
721 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
722 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
726 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
727 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
728 "push{q}\t$imm", []>;
729 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
730 "push{q}\t$imm", []>;
731 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
732 "push{q}\t$imm", []>;
735 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
736 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>,
737 Requires<[In64BitMode]>;
738 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
739 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>,
740 Requires<[In64BitMode]>;
744 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
745 mayLoad=1, neverHasSideEffects=1 in {
746 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>,
747 Requires<[In32BitMode]>;
749 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
750 mayStore=1, neverHasSideEffects=1 in {
751 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>,
752 Requires<[In32BitMode]>;
755 let Constraints = "$src = $dst" in { // GR32 = bswap GR32
756 def BSWAP32r : I<0xC8, AddRegFrm,
757 (outs GR32:$dst), (ins GR32:$src),
759 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
761 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
763 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
764 } // Constraints = "$src = $dst"
766 // Bit scan instructions.
767 let Defs = [EFLAGS] in {
768 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
769 "bsf{w}\t{$src, $dst|$dst, $src}",
770 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
771 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
772 "bsf{w}\t{$src, $dst|$dst, $src}",
773 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
775 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
776 "bsf{l}\t{$src, $dst|$dst, $src}",
777 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
778 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
779 "bsf{l}\t{$src, $dst|$dst, $src}",
780 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
781 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
782 "bsf{q}\t{$src, $dst|$dst, $src}",
783 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB;
784 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
785 "bsf{q}\t{$src, $dst|$dst, $src}",
786 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, TB;
788 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
789 "bsr{w}\t{$src, $dst|$dst, $src}",
790 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
791 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
792 "bsr{w}\t{$src, $dst|$dst, $src}",
793 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
795 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
796 "bsr{l}\t{$src, $dst|$dst, $src}",
797 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
798 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
799 "bsr{l}\t{$src, $dst|$dst, $src}",
800 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
801 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
802 "bsr{q}\t{$src, $dst|$dst, $src}",
803 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, TB;
804 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
805 "bsr{q}\t{$src, $dst|$dst, $src}",
806 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, TB;
810 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
811 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
812 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", []>;
813 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", []>, OpSize;
814 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", []>;
815 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", []>;
818 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
819 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
820 def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", []>;
821 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
822 def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", []>, OpSize;
823 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
824 def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", []>;
825 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
826 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", []>;
828 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", []>;
829 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", []>, OpSize;
830 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", []>;
831 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", []>;
833 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", []>;
834 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", []>, OpSize;
835 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", []>;
836 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", []>;
839 //===----------------------------------------------------------------------===//
840 // Move Instructions.
843 let neverHasSideEffects = 1 in {
844 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
845 "mov{b}\t{$src, $dst|$dst, $src}", []>;
846 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
847 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
848 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
849 "mov{l}\t{$src, $dst|$dst, $src}", []>;
850 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
851 "mov{q}\t{$src, $dst|$dst, $src}", []>;
853 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
854 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
855 "mov{b}\t{$src, $dst|$dst, $src}",
856 [(set GR8:$dst, imm:$src)]>;
857 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
858 "mov{w}\t{$src, $dst|$dst, $src}",
859 [(set GR16:$dst, imm:$src)]>, OpSize;
860 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
861 "mov{l}\t{$src, $dst|$dst, $src}",
862 [(set GR32:$dst, imm:$src)]>;
863 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
864 "movabs{q}\t{$src, $dst|$dst, $src}",
865 [(set GR64:$dst, imm:$src)]>;
866 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
867 "mov{q}\t{$src, $dst|$dst, $src}",
868 [(set GR64:$dst, i64immSExt32:$src)]>;
871 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
872 "mov{b}\t{$src, $dst|$dst, $src}",
873 [(store (i8 imm:$src), addr:$dst)]>;
874 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
875 "mov{w}\t{$src, $dst|$dst, $src}",
876 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
877 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
878 "mov{l}\t{$src, $dst|$dst, $src}",
879 [(store (i32 imm:$src), addr:$dst)]>;
880 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
881 "mov{q}\t{$src, $dst|$dst, $src}",
882 [(store i64immSExt32:$src, addr:$dst)]>;
884 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
885 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
886 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
887 "mov{b}\t{$src, %al|AL, $src}", []>,
888 Requires<[In32BitMode]>;
889 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
890 "mov{w}\t{$src, %ax|AL, $src}", []>, OpSize,
891 Requires<[In32BitMode]>;
892 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
893 "mov{l}\t{$src, %eax|EAX, $src}", []>,
894 Requires<[In32BitMode]>;
895 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
896 "mov{b}\t{%al, $dst|$dst, AL}", []>,
897 Requires<[In32BitMode]>;
898 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
899 "mov{w}\t{%ax, $dst|$dst, AL}", []>, OpSize,
900 Requires<[In32BitMode]>;
901 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
902 "mov{l}\t{%eax, $dst|$dst, EAX}", []>,
903 Requires<[In32BitMode]>;
905 // FIXME: These definitions are utterly broken
906 // Just leave them commented out for now because they're useless outside
907 // of the large code model, and most compilers won't generate the instructions
910 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
911 "mov{q}\t{$src, %rax|RAX, $src}", []>;
912 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
913 "mov{q}\t{$src, %rax|RAX, $src}", []>;
914 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
915 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
916 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
917 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
921 let isCodeGenOnly = 1 in {
922 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
923 "mov{b}\t{$src, $dst|$dst, $src}", []>;
924 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
925 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
926 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
927 "mov{l}\t{$src, $dst|$dst, $src}", []>;
928 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
929 "mov{q}\t{$src, $dst|$dst, $src}", []>;
932 let canFoldAsLoad = 1, isReMaterializable = 1 in {
933 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
934 "mov{b}\t{$src, $dst|$dst, $src}",
935 [(set GR8:$dst, (loadi8 addr:$src))]>;
936 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
937 "mov{w}\t{$src, $dst|$dst, $src}",
938 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
939 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
940 "mov{l}\t{$src, $dst|$dst, $src}",
941 [(set GR32:$dst, (loadi32 addr:$src))]>;
942 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
943 "mov{q}\t{$src, $dst|$dst, $src}",
944 [(set GR64:$dst, (load addr:$src))]>;
947 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
948 "mov{b}\t{$src, $dst|$dst, $src}",
949 [(store GR8:$src, addr:$dst)]>;
950 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
951 "mov{w}\t{$src, $dst|$dst, $src}",
952 [(store GR16:$src, addr:$dst)]>, OpSize;
953 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
954 "mov{l}\t{$src, $dst|$dst, $src}",
955 [(store GR32:$src, addr:$dst)]>;
956 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
957 "mov{q}\t{$src, $dst|$dst, $src}",
958 [(store GR64:$src, addr:$dst)]>;
960 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
961 // that they can be used for copying and storing h registers, which can't be
962 // encoded when a REX prefix is present.
963 let isCodeGenOnly = 1 in {
964 let neverHasSideEffects = 1 in
965 def MOV8rr_NOREX : I<0x88, MRMDestReg,
966 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
967 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
969 def MOV8mr_NOREX : I<0x88, MRMDestMem,
970 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
971 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
972 let mayLoad = 1, neverHasSideEffects = 1,
973 canFoldAsLoad = 1, isReMaterializable = 1 in
974 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
975 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
976 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
980 // Condition code ops, incl. set if equal/not equal/...
981 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
982 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
983 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
984 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
987 //===----------------------------------------------------------------------===//
988 // Bit tests instructions: BT, BTS, BTR, BTC.
990 let Defs = [EFLAGS] in {
991 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
992 "bt{w}\t{$src2, $src1|$src1, $src2}",
993 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
994 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
995 "bt{l}\t{$src2, $src1|$src1, $src2}",
996 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
997 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
998 "bt{q}\t{$src2, $src1|$src1, $src2}",
999 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB;
1001 // Unlike with the register+register form, the memory+register form of the
1002 // bt instruction does not ignore the high bits of the index. From ISel's
1003 // perspective, this is pretty bizarre. Make these instructions disassembly
1006 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1007 "bt{w}\t{$src2, $src1|$src1, $src2}",
1008 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1009 // (implicit EFLAGS)]
1011 >, OpSize, TB, Requires<[FastBTMem]>;
1012 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1013 "bt{l}\t{$src2, $src1|$src1, $src2}",
1014 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1015 // (implicit EFLAGS)]
1017 >, TB, Requires<[FastBTMem]>;
1018 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1019 "bt{q}\t{$src2, $src1|$src1, $src2}",
1020 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1021 // (implicit EFLAGS)]
1025 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1026 "bt{w}\t{$src2, $src1|$src1, $src2}",
1027 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
1029 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1030 "bt{l}\t{$src2, $src1|$src1, $src2}",
1031 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
1032 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1033 "bt{q}\t{$src2, $src1|$src1, $src2}",
1034 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB;
1036 // Note that these instructions don't need FastBTMem because that
1037 // only applies when the other operand is in a register. When it's
1038 // an immediate, bt is still fast.
1039 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1040 "bt{w}\t{$src2, $src1|$src1, $src2}",
1041 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1043 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1044 "bt{l}\t{$src2, $src1|$src1, $src2}",
1045 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1047 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1048 "bt{q}\t{$src2, $src1|$src1, $src2}",
1049 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1050 i64immSExt8:$src2))]>, TB;
1053 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1054 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1055 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1056 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1057 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1058 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1059 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1060 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1061 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1062 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1063 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1064 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1065 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1066 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1067 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1068 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1069 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1070 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1071 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1072 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1073 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1074 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1075 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1076 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1078 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1079 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1080 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1081 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1082 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1083 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1084 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1085 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1086 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1087 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1088 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1089 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1090 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1091 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1092 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1093 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1094 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1095 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1096 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1097 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1098 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1099 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1100 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1101 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1103 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1104 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1105 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1106 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1107 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1108 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1109 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1110 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1111 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1112 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1113 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1114 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1115 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1116 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1117 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1118 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1119 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1120 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1121 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1122 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1123 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1124 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1125 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1126 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1127 } // Defs = [EFLAGS]
1130 //===----------------------------------------------------------------------===//
1135 // Atomic swap. These are just normal xchg instructions. But since a memory
1136 // operand is referenced, the atomicity is ensured.
1137 let Constraints = "$val = $dst" in {
1138 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
1139 "xchg{b}\t{$val, $ptr|$ptr, $val}",
1140 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
1141 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),(ins GR16:$val, i16mem:$ptr),
1142 "xchg{w}\t{$val, $ptr|$ptr, $val}",
1143 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
1145 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),(ins GR32:$val, i32mem:$ptr),
1146 "xchg{l}\t{$val, $ptr|$ptr, $val}",
1147 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
1148 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),(ins GR64:$val,i64mem:$ptr),
1149 "xchg{q}\t{$val, $ptr|$ptr, $val}",
1150 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1152 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1153 "xchg{b}\t{$val, $src|$src, $val}", []>;
1154 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1155 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
1156 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1157 "xchg{l}\t{$val, $src|$src, $val}", []>;
1158 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1159 "xchg{q}\t{$val, $src|$src, $val}", []>;
1162 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1163 "xchg{w}\t{$src, %ax|AX, $src}", []>, OpSize;
1164 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1165 "xchg{l}\t{$src, %eax|EAX, $src}", []>, Requires<[In32BitMode]>;
1166 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1167 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1168 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1169 "xchg{l}\t{$src, %eax|EAX, $src}", []>, Requires<[In64BitMode]>;
1170 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1171 "xchg{q}\t{$src, %rax|RAX, $src}", []>;
1175 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1176 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
1177 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1178 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1179 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1180 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
1181 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1182 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1184 let mayLoad = 1, mayStore = 1 in {
1185 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1186 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
1187 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1188 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1189 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1190 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
1191 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1192 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1196 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1197 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
1198 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1199 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1200 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1201 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
1202 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1203 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1205 let mayLoad = 1, mayStore = 1 in {
1206 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1207 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
1208 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1209 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1210 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1211 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
1212 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1213 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1216 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1217 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1218 "cmpxchg8b\t$dst", []>, TB;
1220 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1221 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1222 "cmpxchg16b\t$dst", []>, TB, Requires<[HasCmpxchg16b]>;
1226 // Lock instruction prefix
1227 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1229 // Rex64 instruction prefix
1230 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>;
1232 // Data16 instruction prefix
1233 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1235 // Repeat string operation instruction prefixes
1236 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1237 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1238 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1239 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1240 // Repeat while not equal (used with CMPS and SCAS)
1241 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1245 // String manipulation instructions
1246 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
1247 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
1248 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
1249 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
1251 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
1252 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
1253 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
1256 // Flag instructions
1257 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
1258 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
1259 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
1260 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
1261 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
1262 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
1263 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
1265 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
1267 // Table lookup instructions
1268 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
1270 // ASCII Adjust After Addition
1271 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1272 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>, Requires<[In32BitMode]>;
1274 // ASCII Adjust AX Before Division
1275 // sets AL, AH and EFLAGS and uses AL and AH
1276 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1277 "aad\t$src", []>, Requires<[In32BitMode]>;
1279 // ASCII Adjust AX After Multiply
1280 // sets AL, AH and EFLAGS and uses AL
1281 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1282 "aam\t$src", []>, Requires<[In32BitMode]>;
1284 // ASCII Adjust AL After Subtraction - sets
1285 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1286 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, Requires<[In32BitMode]>;
1288 // Decimal Adjust AL after Addition
1289 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1290 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>, Requires<[In32BitMode]>;
1292 // Decimal Adjust AL after Subtraction
1293 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1294 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, Requires<[In32BitMode]>;
1296 // Check Array Index Against Bounds
1297 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1298 "bound\t{$src, $dst|$dst, $src}", []>, OpSize,
1299 Requires<[In32BitMode]>;
1300 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1301 "bound\t{$src, $dst|$dst, $src}", []>,
1302 Requires<[In32BitMode]>;
1304 // Adjust RPL Field of Segment Selector
1305 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$src), (ins GR16:$dst),
1306 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
1307 def ARPL16mr : I<0x63, MRMSrcMem, (outs GR16:$src), (ins i16mem:$dst),
1308 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
1310 //===----------------------------------------------------------------------===//
1311 // MOVBE Instructions
1313 let Predicates = [HasMOVBE] in {
1314 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1315 "movbe{w}\t{$src, $dst|$dst, $src}",
1316 [(set GR16:$dst, (bswap (loadi16 addr:$src)))]>, OpSize, T8;
1317 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1318 "movbe{l}\t{$src, $dst|$dst, $src}",
1319 [(set GR32:$dst, (bswap (loadi32 addr:$src)))]>, T8;
1320 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1321 "movbe{q}\t{$src, $dst|$dst, $src}",
1322 [(set GR64:$dst, (bswap (loadi64 addr:$src)))]>, T8;
1323 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1324 "movbe{w}\t{$src, $dst|$dst, $src}",
1325 [(store (bswap GR16:$src), addr:$dst)]>, OpSize, T8;
1326 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1327 "movbe{l}\t{$src, $dst|$dst, $src}",
1328 [(store (bswap GR32:$src), addr:$dst)]>, T8;
1329 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1330 "movbe{q}\t{$src, $dst|$dst, $src}",
1331 [(store (bswap GR64:$src), addr:$dst)]>, T8;
1334 //===----------------------------------------------------------------------===//
1335 // RDRAND Instruction
1337 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1338 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1339 "rdrand{w}\t$dst", []>, OpSize, TB;
1340 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1341 "rdrand{l}\t$dst", []>, TB;
1342 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1343 "rdrand{q}\t$dst", []>, TB;
1346 //===----------------------------------------------------------------------===//
1347 // LZCNT Instruction
1349 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
1350 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1351 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1352 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1354 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1355 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1356 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1357 (implicit EFLAGS)]>, XS, OpSize;
1359 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1360 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1361 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS;
1362 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1363 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1364 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1365 (implicit EFLAGS)]>, XS;
1367 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1368 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1369 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
1371 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1372 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1373 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
1374 (implicit EFLAGS)]>, XS;
1377 //===----------------------------------------------------------------------===//
1378 // TZCNT Instruction
1380 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1381 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1382 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1383 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
1385 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1386 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1387 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
1388 (implicit EFLAGS)]>, XS, OpSize;
1390 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1391 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1392 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS;
1393 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1394 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1395 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
1396 (implicit EFLAGS)]>, XS;
1398 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1399 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1400 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
1402 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1403 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1404 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
1405 (implicit EFLAGS)]>, XS;
1408 //===----------------------------------------------------------------------===//
1410 //===----------------------------------------------------------------------===//
1412 include "X86InstrArithmetic.td"
1413 include "X86InstrCMovSetCC.td"
1414 include "X86InstrExtension.td"
1415 include "X86InstrControl.td"
1416 include "X86InstrShiftRotate.td"
1418 // X87 Floating Point Stack.
1419 include "X86InstrFPStack.td"
1421 // SIMD support (SSE, MMX and AVX)
1422 include "X86InstrFragmentsSIMD.td"
1424 // FMA - Fused Multiply-Add support (requires FMA)
1425 include "X86InstrFMA.td"
1427 // SSE, MMX and 3DNow! vector support.
1428 include "X86InstrSSE.td"
1429 include "X86InstrMMX.td"
1430 include "X86Instr3DNow.td"
1432 include "X86InstrVMX.td"
1434 // System instructions.
1435 include "X86InstrSystem.td"
1437 // Compiler Pseudo Instructions and Pat Patterns
1438 include "X86InstrCompiler.td"
1440 //===----------------------------------------------------------------------===//
1441 // Assembler Mnemonic Aliases
1442 //===----------------------------------------------------------------------===//
1444 def : MnemonicAlias<"call", "calll">, Requires<[In32BitMode]>;
1445 def : MnemonicAlias<"call", "callq">, Requires<[In64BitMode]>;
1447 def : MnemonicAlias<"cbw", "cbtw">;
1448 def : MnemonicAlias<"cwd", "cwtd">;
1449 def : MnemonicAlias<"cdq", "cltd">;
1450 def : MnemonicAlias<"cwde", "cwtl">;
1451 def : MnemonicAlias<"cdqe", "cltq">;
1453 // lret maps to lretl, it is not ambiguous with lretq.
1454 def : MnemonicAlias<"lret", "lretl">;
1456 def : MnemonicAlias<"leavel", "leave">, Requires<[In32BitMode]>;
1457 def : MnemonicAlias<"leaveq", "leave">, Requires<[In64BitMode]>;
1459 def : MnemonicAlias<"loopz", "loope">;
1460 def : MnemonicAlias<"loopnz", "loopne">;
1462 def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
1463 def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
1464 def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>;
1465 def : MnemonicAlias<"popf", "popfq">, Requires<[In64BitMode]>;
1466 def : MnemonicAlias<"popfd", "popfl">;
1468 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
1469 // all modes. However: "push (addr)" and "push $42" should default to
1470 // pushl/pushq depending on the current mode. Similar for "pop %bx"
1471 def : MnemonicAlias<"push", "pushl">, Requires<[In32BitMode]>;
1472 def : MnemonicAlias<"push", "pushq">, Requires<[In64BitMode]>;
1473 def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
1474 def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1475 def : MnemonicAlias<"pushfd", "pushfl">;
1477 def : MnemonicAlias<"repe", "rep">;
1478 def : MnemonicAlias<"repz", "rep">;
1479 def : MnemonicAlias<"repnz", "repne">;
1481 def : MnemonicAlias<"retl", "ret">, Requires<[In32BitMode]>;
1482 def : MnemonicAlias<"retq", "ret">, Requires<[In64BitMode]>;
1484 def : MnemonicAlias<"salb", "shlb">;
1485 def : MnemonicAlias<"salw", "shlw">;
1486 def : MnemonicAlias<"sall", "shll">;
1487 def : MnemonicAlias<"salq", "shlq">;
1489 def : MnemonicAlias<"smovb", "movsb">;
1490 def : MnemonicAlias<"smovw", "movsw">;
1491 def : MnemonicAlias<"smovl", "movsl">;
1492 def : MnemonicAlias<"smovq", "movsq">;
1494 def : MnemonicAlias<"ud2a", "ud2">;
1495 def : MnemonicAlias<"verrw", "verr">;
1497 // System instruction aliases.
1498 def : MnemonicAlias<"iret", "iretl">;
1499 def : MnemonicAlias<"sysret", "sysretl">;
1501 def : MnemonicAlias<"lgdtl", "lgdt">, Requires<[In32BitMode]>;
1502 def : MnemonicAlias<"lgdtq", "lgdt">, Requires<[In64BitMode]>;
1503 def : MnemonicAlias<"lidtl", "lidt">, Requires<[In32BitMode]>;
1504 def : MnemonicAlias<"lidtq", "lidt">, Requires<[In64BitMode]>;
1505 def : MnemonicAlias<"sgdtl", "sgdt">, Requires<[In32BitMode]>;
1506 def : MnemonicAlias<"sgdtq", "sgdt">, Requires<[In64BitMode]>;
1507 def : MnemonicAlias<"sidtl", "sidt">, Requires<[In32BitMode]>;
1508 def : MnemonicAlias<"sidtq", "sidt">, Requires<[In64BitMode]>;
1511 // Floating point stack aliases.
1512 def : MnemonicAlias<"fcmovz", "fcmove">;
1513 def : MnemonicAlias<"fcmova", "fcmovnbe">;
1514 def : MnemonicAlias<"fcmovnae", "fcmovb">;
1515 def : MnemonicAlias<"fcmovna", "fcmovbe">;
1516 def : MnemonicAlias<"fcmovae", "fcmovnb">;
1517 def : MnemonicAlias<"fcomip", "fcompi">;
1518 def : MnemonicAlias<"fildq", "fildll">;
1519 def : MnemonicAlias<"fldcww", "fldcw">;
1520 def : MnemonicAlias<"fnstcww", "fnstcw">;
1521 def : MnemonicAlias<"fnstsww", "fnstsw">;
1522 def : MnemonicAlias<"fucomip", "fucompi">;
1523 def : MnemonicAlias<"fwait", "wait">;
1526 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond>
1527 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
1528 !strconcat(Prefix, NewCond, Suffix)>;
1530 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
1531 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
1532 /// example "setz" -> "sete".
1533 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix> {
1534 def C : CondCodeAlias<Prefix, Suffix, "c", "b">; // setc -> setb
1535 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e">; // setz -> sete
1536 def NA : CondCodeAlias<Prefix, Suffix, "na", "be">; // setna -> setbe
1537 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae">; // setnb -> setae
1538 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae">; // setnc -> setae
1539 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le">; // setng -> setle
1540 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge">; // setnl -> setge
1541 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne">; // setnz -> setne
1542 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p">; // setpe -> setp
1543 def PO : CondCodeAlias<Prefix, Suffix, "po", "np">; // setpo -> setnp
1545 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b">; // setnae -> setb
1546 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a">; // setnbe -> seta
1547 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l">; // setnge -> setl
1548 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g">; // setnle -> setg
1551 // Aliases for set<CC>
1552 defm : IntegerCondCodeMnemonicAlias<"set", "">;
1553 // Aliases for j<CC>
1554 defm : IntegerCondCodeMnemonicAlias<"j", "">;
1555 // Aliases for cmov<CC>{w,l,q}
1556 defm : IntegerCondCodeMnemonicAlias<"cmov", "w">;
1557 defm : IntegerCondCodeMnemonicAlias<"cmov", "l">;
1558 defm : IntegerCondCodeMnemonicAlias<"cmov", "q">;
1561 //===----------------------------------------------------------------------===//
1562 // Assembler Instruction Aliases
1563 //===----------------------------------------------------------------------===//
1565 // aad/aam default to base 10 if no operand is specified.
1566 def : InstAlias<"aad", (AAD8i8 10)>;
1567 def : InstAlias<"aam", (AAM8i8 10)>;
1569 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
1570 def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>;
1573 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>;
1574 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
1575 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
1576 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
1578 // div and idiv aliases for explicit A register.
1579 def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>;
1580 def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>;
1581 def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>;
1582 def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>;
1583 def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>;
1584 def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>;
1585 def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>;
1586 def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>;
1587 def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>;
1588 def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>;
1589 def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>;
1590 def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>;
1591 def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>;
1592 def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>;
1593 def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>;
1594 def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>;
1598 // Various unary fpstack operations default to operating on on ST1.
1599 // For example, "fxch" -> "fxch %st(1)"
1600 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
1601 def : InstAlias<"fsubp", (SUBR_FPrST0 ST1)>;
1602 def : InstAlias<"fsubrp", (SUB_FPrST0 ST1)>;
1603 def : InstAlias<"fmulp", (MUL_FPrST0 ST1)>;
1604 def : InstAlias<"fdivp", (DIVR_FPrST0 ST1)>;
1605 def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>;
1606 def : InstAlias<"fxch", (XCH_F ST1)>;
1607 def : InstAlias<"fcomi", (COM_FIr ST1)>;
1608 def : InstAlias<"fcompi", (COM_FIPr ST1)>;
1609 def : InstAlias<"fucom", (UCOM_Fr ST1)>;
1610 def : InstAlias<"fucomp", (UCOM_FPr ST1)>;
1611 def : InstAlias<"fucomi", (UCOM_FIr ST1)>;
1612 def : InstAlias<"fucompi", (UCOM_FIPr ST1)>;
1614 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
1615 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
1616 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
1618 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
1619 def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"),
1620 (Inst RST:$op), EmitAlias>;
1621 def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"),
1622 (Inst ST0), EmitAlias>;
1625 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
1626 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
1627 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
1628 defm : FpUnaryAlias<"fsubp", SUBR_FPrST0>;
1629 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
1630 defm : FpUnaryAlias<"fsubrp", SUB_FPrST0>;
1631 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
1632 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
1633 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
1634 defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>;
1635 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
1636 defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>;
1637 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
1638 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
1639 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
1640 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
1643 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
1644 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
1645 // solely because gas supports it.
1646 def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op), 0>;
1647 def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>;
1648 def : InstAlias<"fsubp %st(0), $op", (SUBR_FPrST0 RST:$op)>;
1649 def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>;
1650 def : InstAlias<"fdivp %st(0), $op", (DIVR_FPrST0 RST:$op)>;
1651 def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>;
1653 // We accept "fnstsw %eax" even though it only writes %ax.
1654 def : InstAlias<"fnstsw %eax", (FNSTSW8r)>;
1655 def : InstAlias<"fnstsw %al" , (FNSTSW8r)>;
1656 def : InstAlias<"fnstsw" , (FNSTSW8r)>;
1658 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
1659 // this is compatible with what GAS does.
1660 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1661 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1662 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>;
1663 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>;
1665 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
1666 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
1667 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
1668 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
1669 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
1670 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
1671 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
1673 // inb %dx -> inb %al, %dx
1674 def : InstAlias<"inb %dx", (IN8rr)>;
1675 def : InstAlias<"inw %dx", (IN16rr)>;
1676 def : InstAlias<"inl %dx", (IN32rr)>;
1677 def : InstAlias<"inb $port", (IN8ri i8imm:$port)>;
1678 def : InstAlias<"inw $port", (IN16ri i8imm:$port)>;
1679 def : InstAlias<"inl $port", (IN32ri i8imm:$port)>;
1682 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
1683 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1684 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1685 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
1686 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
1687 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1688 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1690 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
1691 // the move. All segment/mem forms are equivalent, this has the shortest
1693 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
1694 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
1696 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
1697 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
1699 // Match 'movq GR64, MMX' as an alias for movd.
1700 def : InstAlias<"movq $src, $dst",
1701 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
1702 def : InstAlias<"movq $src, $dst",
1703 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
1705 // movsd with no operands (as opposed to the SSE scalar move of a double) is an
1706 // alias for movsl. (as in rep; movsd)
1707 def : InstAlias<"movsd", (MOVSD)>;
1710 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
1711 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
1712 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
1713 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
1714 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
1715 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
1716 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
1719 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
1720 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
1721 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
1722 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
1723 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
1724 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
1725 // Note: No GR32->GR64 movzx form.
1727 // outb %dx -> outb %al, %dx
1728 def : InstAlias<"outb %dx", (OUT8rr)>;
1729 def : InstAlias<"outw %dx", (OUT16rr)>;
1730 def : InstAlias<"outl %dx", (OUT32rr)>;
1731 def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>;
1732 def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>;
1733 def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>;
1735 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
1736 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
1737 // errors, since its encoding is the most compact.
1738 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
1740 // shld/shrd op,op -> shld op, op, 1
1741 def : InstAlias<"shldw $r1, $r2", (SHLD16rri8 GR16:$r1, GR16:$r2, 1)>;
1742 def : InstAlias<"shldl $r1, $r2", (SHLD32rri8 GR32:$r1, GR32:$r2, 1)>;
1743 def : InstAlias<"shldq $r1, $r2", (SHLD64rri8 GR64:$r1, GR64:$r2, 1)>;
1744 def : InstAlias<"shrdw $r1, $r2", (SHRD16rri8 GR16:$r1, GR16:$r2, 1)>;
1745 def : InstAlias<"shrdl $r1, $r2", (SHRD32rri8 GR32:$r1, GR32:$r2, 1)>;
1746 def : InstAlias<"shrdq $r1, $r2", (SHRD64rri8 GR64:$r1, GR64:$r2, 1)>;
1748 def : InstAlias<"shldw $mem, $reg", (SHLD16mri8 i16mem:$mem, GR16:$reg, 1)>;
1749 def : InstAlias<"shldl $mem, $reg", (SHLD32mri8 i32mem:$mem, GR32:$reg, 1)>;
1750 def : InstAlias<"shldq $mem, $reg", (SHLD64mri8 i64mem:$mem, GR64:$reg, 1)>;
1751 def : InstAlias<"shrdw $mem, $reg", (SHRD16mri8 i16mem:$mem, GR16:$reg, 1)>;
1752 def : InstAlias<"shrdl $mem, $reg", (SHRD32mri8 i32mem:$mem, GR32:$reg, 1)>;
1753 def : InstAlias<"shrdq $mem, $reg", (SHRD64mri8 i64mem:$mem, GR64:$reg, 1)>;
1755 /* FIXME: This is disabled because the asm matcher is currently incapable of
1756 * matching a fixed immediate like $1.
1757 // "shl X, $1" is an alias for "shl X".
1758 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
1759 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1760 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
1761 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1762 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
1763 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1764 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
1765 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1766 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
1767 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1768 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
1769 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1770 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
1771 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1772 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
1773 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1774 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
1777 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
1778 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
1779 defm : ShiftRotateByOneAlias<"rol", "ROL">;
1780 defm : ShiftRotateByOneAlias<"ror", "ROR">;
1783 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
1784 def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>;
1785 def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>;
1786 def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>;
1787 def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>;
1789 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
1790 def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>;
1791 def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>;
1792 def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>;
1793 def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>;
1795 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
1796 def : InstAlias<"xchgw %ax, $src", (XCHG16ar GR16:$src)>;
1797 def : InstAlias<"xchgl %eax, $src", (XCHG32ar GR32:$src)>, Requires<[In32BitMode]>;
1798 def : InstAlias<"xchgl %eax, $src", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
1799 def : InstAlias<"xchgq %rax, $src", (XCHG64ar GR64:$src)>;