1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 def SDTX86BrCond : SDTypeProfile<0, 3,
31 [SDTCisVT<0, OtherVT>,
32 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
34 def SDTX86SetCC : SDTypeProfile<1, 2,
36 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
38 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
41 def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>;
43 def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
44 def SDT_X86CallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
47 def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
49 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
51 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
53 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
55 def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
57 def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
59 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
61 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
63 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
64 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
65 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
66 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
68 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
70 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
71 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
73 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
75 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
76 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
79 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
80 [SDNPHasChain, SDNPOptInFlag]>;
82 def X86callseq_start :
83 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
84 [SDNPHasChain, SDNPOutFlag]>;
86 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
87 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
89 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
90 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
92 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
93 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
95 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
96 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
97 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
98 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
101 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
102 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
104 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
105 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
107 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
108 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
109 def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
111 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
114 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
115 [SDNPHasChain, SDNPOptInFlag]>;
117 //===----------------------------------------------------------------------===//
118 // X86 Operand Definitions.
121 // *mem - Operand definitions for the funky X86 addressing mode operands.
123 class X86MemOperand<string printMethod> : Operand<iPTR> {
124 let PrintMethod = printMethod;
125 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
128 def i8mem : X86MemOperand<"printi8mem">;
129 def i16mem : X86MemOperand<"printi16mem">;
130 def i32mem : X86MemOperand<"printi32mem">;
131 def i64mem : X86MemOperand<"printi64mem">;
132 def i128mem : X86MemOperand<"printi128mem">;
133 def f32mem : X86MemOperand<"printf32mem">;
134 def f64mem : X86MemOperand<"printf64mem">;
135 def f80mem : X86MemOperand<"printf80mem">;
136 def f128mem : X86MemOperand<"printf128mem">;
138 def lea32mem : Operand<i32> {
139 let PrintMethod = "printi32mem";
140 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
143 def SSECC : Operand<i8> {
144 let PrintMethod = "printSSECC";
147 def piclabel: Operand<i32> {
148 let PrintMethod = "printPICLabel";
151 // A couple of more descriptive operand definitions.
152 // 16-bits but only 8 bits are significant.
153 def i16i8imm : Operand<i16>;
154 // 32-bits but only 8 bits are significant.
155 def i32i8imm : Operand<i32>;
157 // Branch targets have OtherVT type.
158 def brtarget : Operand<OtherVT>;
160 //===----------------------------------------------------------------------===//
161 // X86 Complex Pattern Definitions.
164 // Define X86 specific addressing mode.
165 def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
166 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
167 [add, mul, shl, or, frameindex], []>;
169 //===----------------------------------------------------------------------===//
170 // X86 Instruction Predicate Definitions.
171 def HasMMX : Predicate<"Subtarget->hasMMX()">;
172 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
173 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
174 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
175 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
176 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
177 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
178 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
179 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
180 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
181 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
182 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
183 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
184 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
186 //===----------------------------------------------------------------------===//
187 // X86 Instruction Format Definitions.
190 include "X86InstrFormats.td"
192 //===----------------------------------------------------------------------===//
193 // Pattern fragments...
196 // X86 specific condition code. These correspond to CondCode in
197 // X86InstrInfo.h. They must be kept in synch.
198 def X86_COND_A : PatLeaf<(i8 0)>;
199 def X86_COND_AE : PatLeaf<(i8 1)>;
200 def X86_COND_B : PatLeaf<(i8 2)>;
201 def X86_COND_BE : PatLeaf<(i8 3)>;
202 def X86_COND_E : PatLeaf<(i8 4)>;
203 def X86_COND_G : PatLeaf<(i8 5)>;
204 def X86_COND_GE : PatLeaf<(i8 6)>;
205 def X86_COND_L : PatLeaf<(i8 7)>;
206 def X86_COND_LE : PatLeaf<(i8 8)>;
207 def X86_COND_NE : PatLeaf<(i8 9)>;
208 def X86_COND_NO : PatLeaf<(i8 10)>;
209 def X86_COND_NP : PatLeaf<(i8 11)>;
210 def X86_COND_NS : PatLeaf<(i8 12)>;
211 def X86_COND_O : PatLeaf<(i8 13)>;
212 def X86_COND_P : PatLeaf<(i8 14)>;
213 def X86_COND_S : PatLeaf<(i8 15)>;
215 def i16immSExt8 : PatLeaf<(i16 imm), [{
216 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
217 // sign extended field.
218 return (int16_t)N->getValue() == (int8_t)N->getValue();
221 def i32immSExt8 : PatLeaf<(i32 imm), [{
222 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
223 // sign extended field.
224 return (int32_t)N->getValue() == (int8_t)N->getValue();
227 // Helper fragments for loads.
228 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
229 def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>;
230 def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>;
231 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
233 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
234 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
235 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
237 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
238 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
239 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
241 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
242 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
243 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
244 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
245 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
246 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
248 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
249 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
250 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
251 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
252 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
253 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
256 // An 'and' node with a single use.
257 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
258 return N->hasOneUse();
261 //===----------------------------------------------------------------------===//
262 // Instruction list...
265 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
266 // a stack adjustment and the codegen must know that they may modify the stack
267 // pointer before prolog-epilog rewriting occurs.
268 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become sub / add
269 // which can clobber EFLAGS.
270 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
271 def ADJCALLSTACKDOWN : I<0, Pseudo, (outs), (ins i32imm:$amt),
273 [(X86callseq_start imm:$amt)]>;
274 def ADJCALLSTACKUP : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
276 [(X86callseq_end imm:$amt1, imm:$amt2)]>;
278 let isImplicitDef = 1 in {
279 def IMPLICIT_DEF_GR8 : I<0, Pseudo, (outs GR8:$dst), (ins),
280 "#IMPLICIT_DEF $dst",
281 [(set GR8:$dst, (undef))]>;
282 def IMPLICIT_DEF_GR16 : I<0, Pseudo, (outs GR16:$dst), (ins),
283 "#IMPLICIT_DEF $dst",
284 [(set GR16:$dst, (undef))]>;
285 def IMPLICIT_DEF_GR32 : I<0, Pseudo, (outs GR32:$dst), (ins),
286 "#IMPLICIT_DEF $dst",
287 [(set GR32:$dst, (undef))]>;
291 let neverHasSideEffects = 1 in
292 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
295 let neverHasSideEffects = 1, isNotDuplicable = 1 in
296 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
297 "call\t$label\n\tpop{l}\t$reg", []>;
299 //===----------------------------------------------------------------------===//
300 // Control Flow Instructions...
303 // Return instructions.
304 let isTerminator = 1, isReturn = 1, isBarrier = 1,
306 def RET : I<0xC3, RawFrm, (outs), (ins), "ret", [(X86retflag 0)]>;
307 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), "ret\t$amt",
308 [(X86retflag imm:$amt)]>;
311 // All branches are RawFrm, Void, Branch, and Terminators
312 let isBranch = 1, isTerminator = 1 in
313 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
314 I<opcode, RawFrm, (outs), ins, asm, pattern>;
316 let isBranch = 1, isBarrier = 1 in
317 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
320 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
321 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
322 [(brind GR32:$dst)]>;
323 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
324 [(brind (loadi32 addr:$dst))]>;
327 // Conditional branches
328 let Uses = [EFLAGS] in {
329 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
330 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
331 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
332 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
333 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
334 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
335 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
336 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
337 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
338 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
339 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
340 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
342 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
343 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
344 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
345 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
346 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
347 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
348 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
349 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
351 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
352 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
353 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
354 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
355 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
356 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
357 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
358 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
359 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
360 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
361 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
362 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
365 //===----------------------------------------------------------------------===//
366 // Call Instructions...
369 // All calls clobber the non-callee saved registers...
370 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
371 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
372 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, EFLAGS] in {
373 def CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops),
374 "call\t${dst:call}", []>;
375 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
376 "call\t{*}$dst", [(X86call GR32:$dst)]>;
377 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
378 "call\t{*}$dst", []>;
383 def TAILCALL : I<0, Pseudo, (outs), (ins ),
387 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
388 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset),
389 "#TC_RETURN $dst $offset",
392 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
393 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset),
394 "#TC_RETURN $dst $offset",
397 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
398 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL",
400 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
401 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
403 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
404 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
405 "jmp\t{*}$dst # TAILCALL", []>;
407 //===----------------------------------------------------------------------===//
408 // Miscellaneous Instructions...
410 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
411 def LEAVE : I<0xC9, RawFrm,
412 (outs), (ins), "leave", []>;
414 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
416 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
419 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
422 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
423 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
424 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
425 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
427 let isTwoAddress = 1 in // GR32 = bswap GR32
428 def BSWAP32r : I<0xC8, AddRegFrm,
429 (outs GR32:$dst), (ins GR32:$src),
431 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
434 // Bit scan instructions.
435 let Defs = [EFLAGS] in {
436 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
437 "bsf{w}\t{$src, $dst|$dst, $src}",
438 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
439 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
440 "bsf{w}\t{$src, $dst|$dst, $src}",
441 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
442 (implicit EFLAGS)]>, TB;
443 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
444 "bsf{l}\t{$src, $dst|$dst, $src}",
445 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
446 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
447 "bsf{l}\t{$src, $dst|$dst, $src}",
448 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
449 (implicit EFLAGS)]>, TB;
451 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
452 "bsr{w}\t{$src, $dst|$dst, $src}",
453 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
454 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
455 "bsr{w}\t{$src, $dst|$dst, $src}",
456 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
457 (implicit EFLAGS)]>, TB;
458 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
459 "bsr{l}\t{$src, $dst|$dst, $src}",
460 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
461 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
462 "bsr{l}\t{$src, $dst|$dst, $src}",
463 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
464 (implicit EFLAGS)]>, TB;
467 let neverHasSideEffects = 1 in
468 def LEA16r : I<0x8D, MRMSrcMem,
469 (outs GR16:$dst), (ins i32mem:$src),
470 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
471 def LEA32r : I<0x8D, MRMSrcMem,
472 (outs GR32:$dst), (ins lea32mem:$src),
473 "lea{l}\t{$src|$dst}, {$dst|$src}",
474 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
476 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
477 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
478 [(X86rep_movs i8)]>, REP;
479 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
480 [(X86rep_movs i16)]>, REP, OpSize;
481 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
482 [(X86rep_movs i32)]>, REP;
485 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
486 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
487 [(X86rep_stos i8)]>, REP;
488 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
489 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
490 [(X86rep_stos i16)]>, REP, OpSize;
491 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
492 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
493 [(X86rep_stos i32)]>, REP;
495 let Defs = [RAX, RDX] in
496 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
499 let isBarrier = 1, hasCtrlDep = 1 in {
500 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
503 //===----------------------------------------------------------------------===//
504 // Input/Output Instructions...
506 let Defs = [AL], Uses = [DX] in
507 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
508 "in{b}\t{%dx, %al|%AL, %DX}", []>;
509 let Defs = [AX], Uses = [DX] in
510 def IN16rr : I<0xED, RawFrm, (outs), (ins),
511 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
512 let Defs = [EAX], Uses = [DX] in
513 def IN32rr : I<0xED, RawFrm, (outs), (ins),
514 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
517 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
518 "in{b}\t{$port, %al|%AL, $port}", []>;
520 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
521 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
523 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
524 "in{l}\t{$port, %eax|%EAX, $port}", []>;
526 let Uses = [DX, AL] in
527 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
528 "out{b}\t{%al, %dx|%DX, %AL}", []>;
529 let Uses = [DX, AX] in
530 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
531 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
532 let Uses = [DX, EAX] in
533 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
534 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
537 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
538 "out{b}\t{%al, $port|$port, %AL}", []>;
540 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
541 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
543 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
544 "out{l}\t{%eax, $port|$port, %EAX}", []>;
546 //===----------------------------------------------------------------------===//
547 // Move Instructions...
549 let neverHasSideEffects = 1 in {
550 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
551 "mov{b}\t{$src, $dst|$dst, $src}", []>;
552 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
553 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
554 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
555 "mov{l}\t{$src, $dst|$dst, $src}", []>;
557 let isReMaterializable = 1 in {
558 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
559 "mov{b}\t{$src, $dst|$dst, $src}",
560 [(set GR8:$dst, imm:$src)]>;
561 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
562 "mov{w}\t{$src, $dst|$dst, $src}",
563 [(set GR16:$dst, imm:$src)]>, OpSize;
564 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
565 "mov{l}\t{$src, $dst|$dst, $src}",
566 [(set GR32:$dst, imm:$src)]>;
568 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
569 "mov{b}\t{$src, $dst|$dst, $src}",
570 [(store (i8 imm:$src), addr:$dst)]>;
571 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
572 "mov{w}\t{$src, $dst|$dst, $src}",
573 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
574 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
575 "mov{l}\t{$src, $dst|$dst, $src}",
576 [(store (i32 imm:$src), addr:$dst)]>;
578 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
579 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
580 "mov{b}\t{$src, $dst|$dst, $src}",
581 [(set GR8:$dst, (load addr:$src))]>;
582 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
583 "mov{w}\t{$src, $dst|$dst, $src}",
584 [(set GR16:$dst, (load addr:$src))]>, OpSize;
585 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
586 "mov{l}\t{$src, $dst|$dst, $src}",
587 [(set GR32:$dst, (load addr:$src))]>;
590 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
591 "mov{b}\t{$src, $dst|$dst, $src}",
592 [(store GR8:$src, addr:$dst)]>;
593 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
594 "mov{w}\t{$src, $dst|$dst, $src}",
595 [(store GR16:$src, addr:$dst)]>, OpSize;
596 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
597 "mov{l}\t{$src, $dst|$dst, $src}",
598 [(store GR32:$src, addr:$dst)]>;
600 //===----------------------------------------------------------------------===//
601 // Fixed-Register Multiplication and Division Instructions...
604 // Extra precision multiplication
605 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
606 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
607 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
608 // This probably ought to be moved to a def : Pat<> if the
609 // syntax can be accepted.
610 [(set AL, (mul AL, GR8:$src))]>; // AL,AH = AL*GR8
611 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
612 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>,
613 OpSize; // AX,DX = AX*GR16
614 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
615 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l}\t$src", []>;
616 // EAX,EDX = EAX*GR32
617 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
618 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
620 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
621 // This probably ought to be moved to a def : Pat<> if the
622 // syntax can be accepted.
623 [(set AL, (mul AL, (loadi8 addr:$src)))]>; // AL,AH = AL*[mem8]
624 let mayLoad = 1, neverHasSideEffects = 1 in {
625 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
626 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
627 "mul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
628 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
629 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
630 "mul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
633 let neverHasSideEffects = 1 in {
634 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
635 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
637 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
638 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
639 OpSize; // AX,DX = AX*GR16
640 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
641 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
642 // EAX,EDX = EAX*GR32
644 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
645 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
646 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
647 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
648 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
649 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
650 let Defs = [EAX,EDX], Uses = [EAX] in
651 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
652 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
655 // unsigned division/remainder
656 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
657 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
659 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
660 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
661 "div{w}\t$src", []>, OpSize;
662 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
663 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
666 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
667 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
669 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
670 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
671 "div{w}\t$src", []>, OpSize;
672 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
673 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
677 // Signed division/remainder.
678 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
679 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
680 "idiv{b}\t$src", []>;
681 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
682 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
683 "idiv{w}\t$src", []>, OpSize;
684 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
685 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
686 "idiv{l}\t$src", []>;
687 let mayLoad = 1, mayLoad = 1 in {
688 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
689 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
690 "idiv{b}\t$src", []>;
691 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
692 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
693 "idiv{w}\t$src", []>, OpSize;
694 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
695 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
696 "idiv{l}\t$src", []>;
698 } // neverHasSideEffects
700 //===----------------------------------------------------------------------===//
701 // Two address Instructions.
703 let isTwoAddress = 1 in {
706 let Uses = [EFLAGS] in {
707 let isCommutable = 1 in {
708 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
709 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
710 "cmovb\t{$src2, $dst|$dst, $src2}",
711 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
712 X86_COND_B, EFLAGS))]>,
714 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
715 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
716 "cmovb\t{$src2, $dst|$dst, $src2}",
717 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
718 X86_COND_B, EFLAGS))]>,
721 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
722 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
723 "cmovae\t{$src2, $dst|$dst, $src2}",
724 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
725 X86_COND_AE, EFLAGS))]>,
727 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
728 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
729 "cmovae\t{$src2, $dst|$dst, $src2}",
730 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
731 X86_COND_AE, EFLAGS))]>,
733 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
734 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
735 "cmove\t{$src2, $dst|$dst, $src2}",
736 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
737 X86_COND_E, EFLAGS))]>,
739 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
740 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
741 "cmove\t{$src2, $dst|$dst, $src2}",
742 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
743 X86_COND_E, EFLAGS))]>,
745 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
746 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
747 "cmovne\t{$src2, $dst|$dst, $src2}",
748 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
749 X86_COND_NE, EFLAGS))]>,
751 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
752 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
753 "cmovne\t{$src2, $dst|$dst, $src2}",
754 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
755 X86_COND_NE, EFLAGS))]>,
757 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
758 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
759 "cmovbe\t{$src2, $dst|$dst, $src2}",
760 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
761 X86_COND_BE, EFLAGS))]>,
763 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
764 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
765 "cmovbe\t{$src2, $dst|$dst, $src2}",
766 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
767 X86_COND_BE, EFLAGS))]>,
769 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
770 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
771 "cmova\t{$src2, $dst|$dst, $src2}",
772 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
773 X86_COND_A, EFLAGS))]>,
775 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
776 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
777 "cmova\t{$src2, $dst|$dst, $src2}",
778 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
779 X86_COND_A, EFLAGS))]>,
781 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
782 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
783 "cmovl\t{$src2, $dst|$dst, $src2}",
784 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
785 X86_COND_L, EFLAGS))]>,
787 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
788 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
789 "cmovl\t{$src2, $dst|$dst, $src2}",
790 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
791 X86_COND_L, EFLAGS))]>,
793 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
794 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
795 "cmovge\t{$src2, $dst|$dst, $src2}",
796 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
797 X86_COND_GE, EFLAGS))]>,
799 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
800 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
801 "cmovge\t{$src2, $dst|$dst, $src2}",
802 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
803 X86_COND_GE, EFLAGS))]>,
805 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
806 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
807 "cmovle\t{$src2, $dst|$dst, $src2}",
808 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
809 X86_COND_LE, EFLAGS))]>,
811 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
812 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
813 "cmovle\t{$src2, $dst|$dst, $src2}",
814 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
815 X86_COND_LE, EFLAGS))]>,
817 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
818 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
819 "cmovg\t{$src2, $dst|$dst, $src2}",
820 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
821 X86_COND_G, EFLAGS))]>,
823 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
824 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
825 "cmovg\t{$src2, $dst|$dst, $src2}",
826 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
827 X86_COND_G, EFLAGS))]>,
829 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
830 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
831 "cmovs\t{$src2, $dst|$dst, $src2}",
832 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
833 X86_COND_S, EFLAGS))]>,
835 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
836 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
837 "cmovs\t{$src2, $dst|$dst, $src2}",
838 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
839 X86_COND_S, EFLAGS))]>,
841 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
842 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
843 "cmovns\t{$src2, $dst|$dst, $src2}",
844 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
845 X86_COND_NS, EFLAGS))]>,
847 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
848 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
849 "cmovns\t{$src2, $dst|$dst, $src2}",
850 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
851 X86_COND_NS, EFLAGS))]>,
853 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
854 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
855 "cmovp\t{$src2, $dst|$dst, $src2}",
856 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
857 X86_COND_P, EFLAGS))]>,
859 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
860 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
861 "cmovp\t{$src2, $dst|$dst, $src2}",
862 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
863 X86_COND_P, EFLAGS))]>,
865 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
866 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
867 "cmovnp\t{$src2, $dst|$dst, $src2}",
868 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
869 X86_COND_NP, EFLAGS))]>,
871 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
872 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
873 "cmovnp\t{$src2, $dst|$dst, $src2}",
874 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
875 X86_COND_NP, EFLAGS))]>,
877 } // isCommutable = 1
879 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
880 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
881 "cmovnp\t{$src2, $dst|$dst, $src2}",
882 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
883 X86_COND_NP, EFLAGS))]>,
886 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
887 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
888 "cmovb\t{$src2, $dst|$dst, $src2}",
889 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
890 X86_COND_B, EFLAGS))]>,
892 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
893 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
894 "cmovb\t{$src2, $dst|$dst, $src2}",
895 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
896 X86_COND_B, EFLAGS))]>,
898 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
899 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
900 "cmovae\t{$src2, $dst|$dst, $src2}",
901 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
902 X86_COND_AE, EFLAGS))]>,
904 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
905 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
906 "cmovae\t{$src2, $dst|$dst, $src2}",
907 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
908 X86_COND_AE, EFLAGS))]>,
910 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
911 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
912 "cmove\t{$src2, $dst|$dst, $src2}",
913 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
914 X86_COND_E, EFLAGS))]>,
916 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
917 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
918 "cmove\t{$src2, $dst|$dst, $src2}",
919 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
920 X86_COND_E, EFLAGS))]>,
922 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
923 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
924 "cmovne\t{$src2, $dst|$dst, $src2}",
925 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
926 X86_COND_NE, EFLAGS))]>,
928 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
929 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
930 "cmovne\t{$src2, $dst|$dst, $src2}",
931 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
932 X86_COND_NE, EFLAGS))]>,
934 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
935 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
936 "cmovbe\t{$src2, $dst|$dst, $src2}",
937 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
938 X86_COND_BE, EFLAGS))]>,
940 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
941 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
942 "cmovbe\t{$src2, $dst|$dst, $src2}",
943 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
944 X86_COND_BE, EFLAGS))]>,
946 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
947 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
948 "cmova\t{$src2, $dst|$dst, $src2}",
949 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
950 X86_COND_A, EFLAGS))]>,
952 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
953 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
954 "cmova\t{$src2, $dst|$dst, $src2}",
955 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
956 X86_COND_A, EFLAGS))]>,
958 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
959 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
960 "cmovl\t{$src2, $dst|$dst, $src2}",
961 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
962 X86_COND_L, EFLAGS))]>,
964 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
965 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
966 "cmovl\t{$src2, $dst|$dst, $src2}",
967 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
968 X86_COND_L, EFLAGS))]>,
970 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
971 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
972 "cmovge\t{$src2, $dst|$dst, $src2}",
973 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
974 X86_COND_GE, EFLAGS))]>,
976 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
977 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
978 "cmovge\t{$src2, $dst|$dst, $src2}",
979 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
980 X86_COND_GE, EFLAGS))]>,
982 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
983 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
984 "cmovle\t{$src2, $dst|$dst, $src2}",
985 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
986 X86_COND_LE, EFLAGS))]>,
988 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
989 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
990 "cmovle\t{$src2, $dst|$dst, $src2}",
991 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
992 X86_COND_LE, EFLAGS))]>,
994 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
995 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
996 "cmovg\t{$src2, $dst|$dst, $src2}",
997 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
998 X86_COND_G, EFLAGS))]>,
1000 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1001 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1002 "cmovg\t{$src2, $dst|$dst, $src2}",
1003 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1004 X86_COND_G, EFLAGS))]>,
1006 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1007 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1008 "cmovs\t{$src2, $dst|$dst, $src2}",
1009 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1010 X86_COND_S, EFLAGS))]>,
1012 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1013 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1014 "cmovs\t{$src2, $dst|$dst, $src2}",
1015 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1016 X86_COND_S, EFLAGS))]>,
1018 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1019 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1020 "cmovns\t{$src2, $dst|$dst, $src2}",
1021 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1022 X86_COND_NS, EFLAGS))]>,
1024 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1025 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1026 "cmovns\t{$src2, $dst|$dst, $src2}",
1027 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1028 X86_COND_NS, EFLAGS))]>,
1030 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1031 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1032 "cmovp\t{$src2, $dst|$dst, $src2}",
1033 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1034 X86_COND_P, EFLAGS))]>,
1036 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1037 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1038 "cmovp\t{$src2, $dst|$dst, $src2}",
1039 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1040 X86_COND_P, EFLAGS))]>,
1042 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1043 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1044 "cmovnp\t{$src2, $dst|$dst, $src2}",
1045 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1046 X86_COND_NP, EFLAGS))]>,
1048 } // Uses = [EFLAGS]
1051 // unary instructions
1052 let CodeSize = 2 in {
1053 let Defs = [EFLAGS] in {
1054 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1055 [(set GR8:$dst, (ineg GR8:$src))]>;
1056 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1057 [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
1058 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1059 [(set GR32:$dst, (ineg GR32:$src))]>;
1060 let isTwoAddress = 0 in {
1061 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1062 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
1063 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1064 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1065 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1066 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
1069 } // Defs = [EFLAGS]
1071 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1072 [(set GR8:$dst, (not GR8:$src))]>;
1073 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1074 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1075 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1076 [(set GR32:$dst, (not GR32:$src))]>;
1077 let isTwoAddress = 0 in {
1078 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1079 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1080 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1081 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1082 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1083 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1087 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1088 let Defs = [EFLAGS] in {
1090 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1091 [(set GR8:$dst, (add GR8:$src, 1))]>;
1092 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1093 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1094 [(set GR16:$dst, (add GR16:$src, 1))]>,
1095 OpSize, Requires<[In32BitMode]>;
1096 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1097 [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
1099 let isTwoAddress = 0, CodeSize = 2 in {
1100 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1101 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1102 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1103 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>,
1104 OpSize, Requires<[In32BitMode]>;
1105 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1106 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>,
1107 Requires<[In32BitMode]>;
1111 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1112 [(set GR8:$dst, (add GR8:$src, -1))]>;
1113 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1114 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1115 [(set GR16:$dst, (add GR16:$src, -1))]>,
1116 OpSize, Requires<[In32BitMode]>;
1117 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1118 [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
1121 let isTwoAddress = 0, CodeSize = 2 in {
1122 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1123 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1124 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1125 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>,
1126 OpSize, Requires<[In32BitMode]>;
1127 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1128 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>,
1129 Requires<[In32BitMode]>;
1131 } // Defs = [EFLAGS]
1133 // Logical operators...
1134 let Defs = [EFLAGS] in {
1135 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1136 def AND8rr : I<0x20, MRMDestReg,
1137 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1138 "and{b}\t{$src2, $dst|$dst, $src2}",
1139 [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
1140 def AND16rr : I<0x21, MRMDestReg,
1141 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1142 "and{w}\t{$src2, $dst|$dst, $src2}",
1143 [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
1144 def AND32rr : I<0x21, MRMDestReg,
1145 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1146 "and{l}\t{$src2, $dst|$dst, $src2}",
1147 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
1150 def AND8rm : I<0x22, MRMSrcMem,
1151 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1152 "and{b}\t{$src2, $dst|$dst, $src2}",
1153 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
1154 def AND16rm : I<0x23, MRMSrcMem,
1155 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1156 "and{w}\t{$src2, $dst|$dst, $src2}",
1157 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
1158 def AND32rm : I<0x23, MRMSrcMem,
1159 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1160 "and{l}\t{$src2, $dst|$dst, $src2}",
1161 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
1163 def AND8ri : Ii8<0x80, MRM4r,
1164 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1165 "and{b}\t{$src2, $dst|$dst, $src2}",
1166 [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
1167 def AND16ri : Ii16<0x81, MRM4r,
1168 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1169 "and{w}\t{$src2, $dst|$dst, $src2}",
1170 [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
1171 def AND32ri : Ii32<0x81, MRM4r,
1172 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1173 "and{l}\t{$src2, $dst|$dst, $src2}",
1174 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
1175 def AND16ri8 : Ii8<0x83, MRM4r,
1176 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1177 "and{w}\t{$src2, $dst|$dst, $src2}",
1178 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
1180 def AND32ri8 : Ii8<0x83, MRM4r,
1181 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1182 "and{l}\t{$src2, $dst|$dst, $src2}",
1183 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
1185 let isTwoAddress = 0 in {
1186 def AND8mr : I<0x20, MRMDestMem,
1187 (outs), (ins i8mem :$dst, GR8 :$src),
1188 "and{b}\t{$src, $dst|$dst, $src}",
1189 [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
1190 def AND16mr : I<0x21, MRMDestMem,
1191 (outs), (ins i16mem:$dst, GR16:$src),
1192 "and{w}\t{$src, $dst|$dst, $src}",
1193 [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
1195 def AND32mr : I<0x21, MRMDestMem,
1196 (outs), (ins i32mem:$dst, GR32:$src),
1197 "and{l}\t{$src, $dst|$dst, $src}",
1198 [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
1199 def AND8mi : Ii8<0x80, MRM4m,
1200 (outs), (ins i8mem :$dst, i8imm :$src),
1201 "and{b}\t{$src, $dst|$dst, $src}",
1202 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1203 def AND16mi : Ii16<0x81, MRM4m,
1204 (outs), (ins i16mem:$dst, i16imm:$src),
1205 "and{w}\t{$src, $dst|$dst, $src}",
1206 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1208 def AND32mi : Ii32<0x81, MRM4m,
1209 (outs), (ins i32mem:$dst, i32imm:$src),
1210 "and{l}\t{$src, $dst|$dst, $src}",
1211 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1212 def AND16mi8 : Ii8<0x83, MRM4m,
1213 (outs), (ins i16mem:$dst, i16i8imm :$src),
1214 "and{w}\t{$src, $dst|$dst, $src}",
1215 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1217 def AND32mi8 : Ii8<0x83, MRM4m,
1218 (outs), (ins i32mem:$dst, i32i8imm :$src),
1219 "and{l}\t{$src, $dst|$dst, $src}",
1220 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1224 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1225 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1226 "or{b}\t{$src2, $dst|$dst, $src2}",
1227 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
1228 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1229 "or{w}\t{$src2, $dst|$dst, $src2}",
1230 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
1231 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1232 "or{l}\t{$src2, $dst|$dst, $src2}",
1233 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
1235 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1236 "or{b}\t{$src2, $dst|$dst, $src2}",
1237 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
1238 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1239 "or{w}\t{$src2, $dst|$dst, $src2}",
1240 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
1241 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1242 "or{l}\t{$src2, $dst|$dst, $src2}",
1243 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
1245 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1246 "or{b}\t{$src2, $dst|$dst, $src2}",
1247 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
1248 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1249 "or{w}\t{$src2, $dst|$dst, $src2}",
1250 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
1251 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1252 "or{l}\t{$src2, $dst|$dst, $src2}",
1253 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
1255 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1256 "or{w}\t{$src2, $dst|$dst, $src2}",
1257 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1258 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1259 "or{l}\t{$src2, $dst|$dst, $src2}",
1260 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
1261 let isTwoAddress = 0 in {
1262 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1263 "or{b}\t{$src, $dst|$dst, $src}",
1264 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
1265 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1266 "or{w}\t{$src, $dst|$dst, $src}",
1267 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
1268 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1269 "or{l}\t{$src, $dst|$dst, $src}",
1270 [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
1271 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1272 "or{b}\t{$src, $dst|$dst, $src}",
1273 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1274 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1275 "or{w}\t{$src, $dst|$dst, $src}",
1276 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1278 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1279 "or{l}\t{$src, $dst|$dst, $src}",
1280 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1281 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1282 "or{w}\t{$src, $dst|$dst, $src}",
1283 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1285 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1286 "or{l}\t{$src, $dst|$dst, $src}",
1287 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1291 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1292 def XOR8rr : I<0x30, MRMDestReg,
1293 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1294 "xor{b}\t{$src2, $dst|$dst, $src2}",
1295 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
1296 def XOR16rr : I<0x31, MRMDestReg,
1297 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1298 "xor{w}\t{$src2, $dst|$dst, $src2}",
1299 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
1300 def XOR32rr : I<0x31, MRMDestReg,
1301 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1302 "xor{l}\t{$src2, $dst|$dst, $src2}",
1303 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
1306 def XOR8rm : I<0x32, MRMSrcMem ,
1307 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1308 "xor{b}\t{$src2, $dst|$dst, $src2}",
1309 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
1310 def XOR16rm : I<0x33, MRMSrcMem ,
1311 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1312 "xor{w}\t{$src2, $dst|$dst, $src2}",
1313 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>, OpSize;
1314 def XOR32rm : I<0x33, MRMSrcMem ,
1315 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1316 "xor{l}\t{$src2, $dst|$dst, $src2}",
1317 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
1319 def XOR8ri : Ii8<0x80, MRM6r,
1320 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1321 "xor{b}\t{$src2, $dst|$dst, $src2}",
1322 [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
1323 def XOR16ri : Ii16<0x81, MRM6r,
1324 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1325 "xor{w}\t{$src2, $dst|$dst, $src2}",
1326 [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
1327 def XOR32ri : Ii32<0x81, MRM6r,
1328 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1329 "xor{l}\t{$src2, $dst|$dst, $src2}",
1330 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
1331 def XOR16ri8 : Ii8<0x83, MRM6r,
1332 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1333 "xor{w}\t{$src2, $dst|$dst, $src2}",
1334 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
1336 def XOR32ri8 : Ii8<0x83, MRM6r,
1337 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1338 "xor{l}\t{$src2, $dst|$dst, $src2}",
1339 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
1340 let isTwoAddress = 0 in {
1341 def XOR8mr : I<0x30, MRMDestMem,
1342 (outs), (ins i8mem :$dst, GR8 :$src),
1343 "xor{b}\t{$src, $dst|$dst, $src}",
1344 [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
1345 def XOR16mr : I<0x31, MRMDestMem,
1346 (outs), (ins i16mem:$dst, GR16:$src),
1347 "xor{w}\t{$src, $dst|$dst, $src}",
1348 [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
1350 def XOR32mr : I<0x31, MRMDestMem,
1351 (outs), (ins i32mem:$dst, GR32:$src),
1352 "xor{l}\t{$src, $dst|$dst, $src}",
1353 [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
1354 def XOR8mi : Ii8<0x80, MRM6m,
1355 (outs), (ins i8mem :$dst, i8imm :$src),
1356 "xor{b}\t{$src, $dst|$dst, $src}",
1357 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1358 def XOR16mi : Ii16<0x81, MRM6m,
1359 (outs), (ins i16mem:$dst, i16imm:$src),
1360 "xor{w}\t{$src, $dst|$dst, $src}",
1361 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1363 def XOR32mi : Ii32<0x81, MRM6m,
1364 (outs), (ins i32mem:$dst, i32imm:$src),
1365 "xor{l}\t{$src, $dst|$dst, $src}",
1366 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1367 def XOR16mi8 : Ii8<0x83, MRM6m,
1368 (outs), (ins i16mem:$dst, i16i8imm :$src),
1369 "xor{w}\t{$src, $dst|$dst, $src}",
1370 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1372 def XOR32mi8 : Ii8<0x83, MRM6m,
1373 (outs), (ins i32mem:$dst, i32i8imm :$src),
1374 "xor{l}\t{$src, $dst|$dst, $src}",
1375 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1377 } // Defs = [EFLAGS]
1379 // Shift instructions
1380 let Defs = [EFLAGS] in {
1381 let Uses = [CL] in {
1382 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1383 "shl{b}\t{%cl, $dst|$dst, %CL}",
1384 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1385 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1386 "shl{w}\t{%cl, $dst|$dst, %CL}",
1387 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1388 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1389 "shl{l}\t{%cl, $dst|$dst, %CL}",
1390 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1393 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1394 "shl{b}\t{$src2, $dst|$dst, $src2}",
1395 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1396 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1397 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1398 "shl{w}\t{$src2, $dst|$dst, $src2}",
1399 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1400 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1401 "shl{l}\t{$src2, $dst|$dst, $src2}",
1402 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1403 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1407 let isTwoAddress = 0 in {
1408 let Uses = [CL] in {
1409 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1410 "shl{b}\t{%cl, $dst|$dst, %CL}",
1411 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1412 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1413 "shl{w}\t{%cl, $dst|$dst, %CL}",
1414 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1415 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1416 "shl{l}\t{%cl, $dst|$dst, %CL}",
1417 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1419 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1420 "shl{b}\t{$src, $dst|$dst, $src}",
1421 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1422 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1423 "shl{w}\t{$src, $dst|$dst, $src}",
1424 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1426 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1427 "shl{l}\t{$src, $dst|$dst, $src}",
1428 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1431 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1433 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1434 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1436 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1438 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1440 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1443 let Uses = [CL] in {
1444 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1445 "shr{b}\t{%cl, $dst|$dst, %CL}",
1446 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1447 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1448 "shr{w}\t{%cl, $dst|$dst, %CL}",
1449 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1450 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1451 "shr{l}\t{%cl, $dst|$dst, %CL}",
1452 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1455 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1456 "shr{b}\t{$src2, $dst|$dst, $src2}",
1457 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1458 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1459 "shr{w}\t{$src2, $dst|$dst, $src2}",
1460 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1461 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1462 "shr{l}\t{$src2, $dst|$dst, $src2}",
1463 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1466 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1468 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1469 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1471 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1472 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1474 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1476 let isTwoAddress = 0 in {
1477 let Uses = [CL] in {
1478 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1479 "shr{b}\t{%cl, $dst|$dst, %CL}",
1480 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1481 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1482 "shr{w}\t{%cl, $dst|$dst, %CL}",
1483 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1485 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1486 "shr{l}\t{%cl, $dst|$dst, %CL}",
1487 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1489 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1490 "shr{b}\t{$src, $dst|$dst, $src}",
1491 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1492 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1493 "shr{w}\t{$src, $dst|$dst, $src}",
1494 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1496 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1497 "shr{l}\t{$src, $dst|$dst, $src}",
1498 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1501 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1503 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1504 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1506 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1507 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1509 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1512 let Uses = [CL] in {
1513 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1514 "sar{b}\t{%cl, $dst|$dst, %CL}",
1515 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1516 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1517 "sar{w}\t{%cl, $dst|$dst, %CL}",
1518 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1519 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1520 "sar{l}\t{%cl, $dst|$dst, %CL}",
1521 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1524 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1525 "sar{b}\t{$src2, $dst|$dst, $src2}",
1526 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1527 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1528 "sar{w}\t{$src2, $dst|$dst, $src2}",
1529 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1531 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1532 "sar{l}\t{$src2, $dst|$dst, $src2}",
1533 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1536 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1538 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1539 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1541 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1542 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1544 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1546 let isTwoAddress = 0 in {
1547 let Uses = [CL] in {
1548 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1549 "sar{b}\t{%cl, $dst|$dst, %CL}",
1550 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1551 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1552 "sar{w}\t{%cl, $dst|$dst, %CL}",
1553 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1554 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1555 "sar{l}\t{%cl, $dst|$dst, %CL}",
1556 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1558 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1559 "sar{b}\t{$src, $dst|$dst, $src}",
1560 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1561 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1562 "sar{w}\t{$src, $dst|$dst, $src}",
1563 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1565 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1566 "sar{l}\t{$src, $dst|$dst, $src}",
1567 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1570 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1572 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1573 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1575 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1577 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1579 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1582 // Rotate instructions
1583 // FIXME: provide shorter instructions when imm8 == 1
1584 let Uses = [CL] in {
1585 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
1586 "rol{b}\t{%cl, $dst|$dst, %CL}",
1587 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
1588 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
1589 "rol{w}\t{%cl, $dst|$dst, %CL}",
1590 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
1591 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
1592 "rol{l}\t{%cl, $dst|$dst, %CL}",
1593 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
1596 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1597 "rol{b}\t{$src2, $dst|$dst, $src2}",
1598 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1599 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1600 "rol{w}\t{$src2, $dst|$dst, $src2}",
1601 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1602 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1603 "rol{l}\t{$src2, $dst|$dst, $src2}",
1604 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1607 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1609 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1610 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1612 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1613 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1615 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1617 let isTwoAddress = 0 in {
1618 let Uses = [CL] in {
1619 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
1620 "rol{b}\t{%cl, $dst|$dst, %CL}",
1621 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
1622 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
1623 "rol{w}\t{%cl, $dst|$dst, %CL}",
1624 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1625 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
1626 "rol{l}\t{%cl, $dst|$dst, %CL}",
1627 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1629 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
1630 "rol{b}\t{$src, $dst|$dst, $src}",
1631 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1632 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
1633 "rol{w}\t{$src, $dst|$dst, $src}",
1634 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1636 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
1637 "rol{l}\t{$src, $dst|$dst, $src}",
1638 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1641 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
1643 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1644 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
1646 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1648 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
1650 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1653 let Uses = [CL] in {
1654 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
1655 "ror{b}\t{%cl, $dst|$dst, %CL}",
1656 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
1657 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
1658 "ror{w}\t{%cl, $dst|$dst, %CL}",
1659 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
1660 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
1661 "ror{l}\t{%cl, $dst|$dst, %CL}",
1662 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
1665 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1666 "ror{b}\t{$src2, $dst|$dst, $src2}",
1667 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
1668 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1669 "ror{w}\t{$src2, $dst|$dst, $src2}",
1670 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1671 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1672 "ror{l}\t{$src2, $dst|$dst, $src2}",
1673 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
1676 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1678 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
1679 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
1681 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
1682 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
1684 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
1686 let isTwoAddress = 0 in {
1687 let Uses = [CL] in {
1688 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
1689 "ror{b}\t{%cl, $dst|$dst, %CL}",
1690 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
1691 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
1692 "ror{w}\t{%cl, $dst|$dst, %CL}",
1693 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1694 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
1695 "ror{l}\t{%cl, $dst|$dst, %CL}",
1696 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
1698 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1699 "ror{b}\t{$src, $dst|$dst, $src}",
1700 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1701 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
1702 "ror{w}\t{$src, $dst|$dst, $src}",
1703 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1705 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
1706 "ror{l}\t{$src, $dst|$dst, $src}",
1707 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1710 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
1712 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1713 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
1715 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1717 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
1719 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1724 // Double shift instructions (generalizations of rotate)
1725 let Uses = [CL] in {
1726 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1727 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1728 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
1729 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1730 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1731 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
1732 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1733 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1734 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
1736 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1737 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1738 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
1742 let isCommutable = 1 in { // These instructions commute to each other.
1743 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
1744 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1745 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1746 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
1749 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
1750 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1751 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1752 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
1755 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
1756 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1757 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1758 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
1761 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1762 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1763 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1764 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
1769 let isTwoAddress = 0 in {
1770 let Uses = [CL] in {
1771 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1772 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1773 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
1775 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1776 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1777 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
1780 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1781 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1782 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1783 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
1784 (i8 imm:$src3)), addr:$dst)]>,
1786 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1787 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1788 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1789 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
1790 (i8 imm:$src3)), addr:$dst)]>,
1793 let Uses = [CL] in {
1794 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1795 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1796 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
1797 addr:$dst)]>, TB, OpSize;
1798 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1799 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1800 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
1801 addr:$dst)]>, TB, OpSize;
1803 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1804 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1805 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1806 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
1807 (i8 imm:$src3)), addr:$dst)]>,
1809 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1810 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1811 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1812 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
1813 (i8 imm:$src3)), addr:$dst)]>,
1816 } // Defs = [EFLAGS]
1820 let Defs = [EFLAGS] in {
1821 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1822 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
1823 (ins GR8 :$src1, GR8 :$src2),
1824 "add{b}\t{$src2, $dst|$dst, $src2}",
1825 [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>;
1826 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1827 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
1828 (ins GR16:$src1, GR16:$src2),
1829 "add{w}\t{$src2, $dst|$dst, $src2}",
1830 [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize;
1831 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
1832 (ins GR32:$src1, GR32:$src2),
1833 "add{l}\t{$src2, $dst|$dst, $src2}",
1834 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
1835 } // end isConvertibleToThreeAddress
1836 } // end isCommutable
1837 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
1838 (ins GR8 :$src1, i8mem :$src2),
1839 "add{b}\t{$src2, $dst|$dst, $src2}",
1840 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>;
1841 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
1842 (ins GR16:$src1, i16mem:$src2),
1843 "add{w}\t{$src2, $dst|$dst, $src2}",
1844 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>,OpSize;
1845 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
1846 (ins GR32:$src1, i32mem:$src2),
1847 "add{l}\t{$src2, $dst|$dst, $src2}",
1848 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>;
1850 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1851 "add{b}\t{$src2, $dst|$dst, $src2}",
1852 [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>;
1854 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1855 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
1856 (ins GR16:$src1, i16imm:$src2),
1857 "add{w}\t{$src2, $dst|$dst, $src2}",
1858 [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize;
1859 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
1860 (ins GR32:$src1, i32imm:$src2),
1861 "add{l}\t{$src2, $dst|$dst, $src2}",
1862 [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>;
1863 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
1864 (ins GR16:$src1, i16i8imm:$src2),
1865 "add{w}\t{$src2, $dst|$dst, $src2}",
1866 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1867 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
1868 (ins GR32:$src1, i32i8imm:$src2),
1869 "add{l}\t{$src2, $dst|$dst, $src2}",
1870 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>;
1873 let isTwoAddress = 0 in {
1874 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1875 "add{b}\t{$src2, $dst|$dst, $src2}",
1876 [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>;
1877 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1878 "add{w}\t{$src2, $dst|$dst, $src2}",
1879 [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>,
1881 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1882 "add{l}\t{$src2, $dst|$dst, $src2}",
1883 [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>;
1884 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
1885 "add{b}\t{$src2, $dst|$dst, $src2}",
1886 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1887 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
1888 "add{w}\t{$src2, $dst|$dst, $src2}",
1889 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1891 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
1892 "add{l}\t{$src2, $dst|$dst, $src2}",
1893 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1894 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1895 "add{w}\t{$src2, $dst|$dst, $src2}",
1896 [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1898 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1899 "add{l}\t{$src2, $dst|$dst, $src2}",
1900 [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1903 let Uses = [EFLAGS] in {
1904 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1905 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1906 "adc{l}\t{$src2, $dst|$dst, $src2}",
1907 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
1909 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1910 "adc{l}\t{$src2, $dst|$dst, $src2}",
1911 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
1912 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1913 "adc{l}\t{$src2, $dst|$dst, $src2}",
1914 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
1915 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1916 "adc{l}\t{$src2, $dst|$dst, $src2}",
1917 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
1919 let isTwoAddress = 0 in {
1920 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1921 "adc{l}\t{$src2, $dst|$dst, $src2}",
1922 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
1923 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
1924 "adc{l}\t{$src2, $dst|$dst, $src2}",
1925 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1926 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1927 "adc{l}\t{$src2, $dst|$dst, $src2}",
1928 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1930 } // Uses = [EFLAGS]
1932 def SUB8rr : I<0x28, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1933 "sub{b}\t{$src2, $dst|$dst, $src2}",
1934 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>;
1935 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1936 "sub{w}\t{$src2, $dst|$dst, $src2}",
1937 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize;
1938 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1939 "sub{l}\t{$src2, $dst|$dst, $src2}",
1940 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
1941 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1942 "sub{b}\t{$src2, $dst|$dst, $src2}",
1943 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>;
1944 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1945 "sub{w}\t{$src2, $dst|$dst, $src2}",
1946 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize;
1947 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1948 "sub{l}\t{$src2, $dst|$dst, $src2}",
1949 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>;
1951 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1952 "sub{b}\t{$src2, $dst|$dst, $src2}",
1953 [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>;
1954 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1955 "sub{w}\t{$src2, $dst|$dst, $src2}",
1956 [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize;
1957 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1958 "sub{l}\t{$src2, $dst|$dst, $src2}",
1959 [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>;
1960 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1961 "sub{w}\t{$src2, $dst|$dst, $src2}",
1962 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>,
1964 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1965 "sub{l}\t{$src2, $dst|$dst, $src2}",
1966 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>;
1967 let isTwoAddress = 0 in {
1968 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1969 "sub{b}\t{$src2, $dst|$dst, $src2}",
1970 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>;
1971 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1972 "sub{w}\t{$src2, $dst|$dst, $src2}",
1973 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>,
1975 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1976 "sub{l}\t{$src2, $dst|$dst, $src2}",
1977 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>;
1978 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
1979 "sub{b}\t{$src2, $dst|$dst, $src2}",
1980 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1981 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
1982 "sub{w}\t{$src2, $dst|$dst, $src2}",
1983 [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1985 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
1986 "sub{l}\t{$src2, $dst|$dst, $src2}",
1987 [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1988 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1989 "sub{w}\t{$src2, $dst|$dst, $src2}",
1990 [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1992 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1993 "sub{l}\t{$src2, $dst|$dst, $src2}",
1994 [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1997 let Uses = [EFLAGS] in {
1998 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1999 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2000 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2002 let isTwoAddress = 0 in {
2003 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2004 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2005 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2006 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2007 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2008 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2009 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2010 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2011 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2012 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2013 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2014 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2016 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2017 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2018 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2019 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2020 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2021 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2022 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2023 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2024 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2025 } // Uses = [EFLAGS]
2026 } // Defs = [EFLAGS]
2028 let Defs = [EFLAGS] in {
2029 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2030 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2031 "imul{w}\t{$src2, $dst|$dst, $src2}",
2032 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize;
2033 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2034 "imul{l}\t{$src2, $dst|$dst, $src2}",
2035 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB;
2037 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2038 "imul{w}\t{$src2, $dst|$dst, $src2}",
2039 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>,
2041 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2042 "imul{l}\t{$src2, $dst|$dst, $src2}",
2043 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB;
2044 } // Defs = [EFLAGS]
2045 } // end Two Address instructions
2047 // Suprisingly enough, these are not two address instructions!
2048 let Defs = [EFLAGS] in {
2049 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2050 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2051 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2052 [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize;
2053 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2054 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2055 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2056 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
2057 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2058 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2059 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2060 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>,
2062 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2063 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2064 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2065 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>;
2067 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2068 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2069 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2070 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>,
2072 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2073 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2074 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2075 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>;
2076 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2077 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2078 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2079 [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>,
2081 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2082 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2083 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2084 [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>;
2085 } // Defs = [EFLAGS]
2087 //===----------------------------------------------------------------------===//
2088 // Test instructions are just like AND, except they don't generate a result.
2090 let Defs = [EFLAGS] in {
2091 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2092 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2093 "test{b}\t{$src2, $src1|$src1, $src2}",
2094 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
2095 (implicit EFLAGS)]>;
2096 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2097 "test{w}\t{$src2, $src1|$src1, $src2}",
2098 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
2099 (implicit EFLAGS)]>,
2101 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2102 "test{l}\t{$src2, $src1|$src1, $src2}",
2103 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
2104 (implicit EFLAGS)]>;
2107 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2108 "test{b}\t{$src2, $src1|$src1, $src2}",
2109 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2110 (implicit EFLAGS)]>;
2111 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2112 "test{w}\t{$src2, $src1|$src1, $src2}",
2113 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2114 (implicit EFLAGS)]>, OpSize;
2115 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2116 "test{l}\t{$src2, $src1|$src1, $src2}",
2117 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2118 (implicit EFLAGS)]>;
2120 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2121 (outs), (ins GR8:$src1, i8imm:$src2),
2122 "test{b}\t{$src2, $src1|$src1, $src2}",
2123 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
2124 (implicit EFLAGS)]>;
2125 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2126 (outs), (ins GR16:$src1, i16imm:$src2),
2127 "test{w}\t{$src2, $src1|$src1, $src2}",
2128 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
2129 (implicit EFLAGS)]>, OpSize;
2130 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2131 (outs), (ins GR32:$src1, i32imm:$src2),
2132 "test{l}\t{$src2, $src1|$src1, $src2}",
2133 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
2134 (implicit EFLAGS)]>;
2136 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2137 (outs), (ins i8mem:$src1, i8imm:$src2),
2138 "test{b}\t{$src2, $src1|$src1, $src2}",
2139 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2140 (implicit EFLAGS)]>;
2141 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2142 (outs), (ins i16mem:$src1, i16imm:$src2),
2143 "test{w}\t{$src2, $src1|$src1, $src2}",
2144 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2145 (implicit EFLAGS)]>, OpSize;
2146 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2147 (outs), (ins i32mem:$src1, i32imm:$src2),
2148 "test{l}\t{$src2, $src1|$src1, $src2}",
2149 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2150 (implicit EFLAGS)]>;
2151 } // Defs = [EFLAGS]
2154 // Condition code ops, incl. set if equal/not equal/...
2155 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2156 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2157 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2158 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2160 let Uses = [EFLAGS] in {
2161 def SETEr : I<0x94, MRM0r,
2162 (outs GR8 :$dst), (ins),
2164 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2166 def SETEm : I<0x94, MRM0m,
2167 (outs), (ins i8mem:$dst),
2169 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2171 def SETNEr : I<0x95, MRM0r,
2172 (outs GR8 :$dst), (ins),
2174 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2176 def SETNEm : I<0x95, MRM0m,
2177 (outs), (ins i8mem:$dst),
2179 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2181 def SETLr : I<0x9C, MRM0r,
2182 (outs GR8 :$dst), (ins),
2184 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2185 TB; // GR8 = < signed
2186 def SETLm : I<0x9C, MRM0m,
2187 (outs), (ins i8mem:$dst),
2189 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2190 TB; // [mem8] = < signed
2191 def SETGEr : I<0x9D, MRM0r,
2192 (outs GR8 :$dst), (ins),
2194 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2195 TB; // GR8 = >= signed
2196 def SETGEm : I<0x9D, MRM0m,
2197 (outs), (ins i8mem:$dst),
2199 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2200 TB; // [mem8] = >= signed
2201 def SETLEr : I<0x9E, MRM0r,
2202 (outs GR8 :$dst), (ins),
2204 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2205 TB; // GR8 = <= signed
2206 def SETLEm : I<0x9E, MRM0m,
2207 (outs), (ins i8mem:$dst),
2209 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2210 TB; // [mem8] = <= signed
2211 def SETGr : I<0x9F, MRM0r,
2212 (outs GR8 :$dst), (ins),
2214 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2215 TB; // GR8 = > signed
2216 def SETGm : I<0x9F, MRM0m,
2217 (outs), (ins i8mem:$dst),
2219 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2220 TB; // [mem8] = > signed
2222 def SETBr : I<0x92, MRM0r,
2223 (outs GR8 :$dst), (ins),
2225 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2226 TB; // GR8 = < unsign
2227 def SETBm : I<0x92, MRM0m,
2228 (outs), (ins i8mem:$dst),
2230 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2231 TB; // [mem8] = < unsign
2232 def SETAEr : I<0x93, MRM0r,
2233 (outs GR8 :$dst), (ins),
2235 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2236 TB; // GR8 = >= unsign
2237 def SETAEm : I<0x93, MRM0m,
2238 (outs), (ins i8mem:$dst),
2240 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2241 TB; // [mem8] = >= unsign
2242 def SETBEr : I<0x96, MRM0r,
2243 (outs GR8 :$dst), (ins),
2245 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2246 TB; // GR8 = <= unsign
2247 def SETBEm : I<0x96, MRM0m,
2248 (outs), (ins i8mem:$dst),
2250 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2251 TB; // [mem8] = <= unsign
2252 def SETAr : I<0x97, MRM0r,
2253 (outs GR8 :$dst), (ins),
2255 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2256 TB; // GR8 = > signed
2257 def SETAm : I<0x97, MRM0m,
2258 (outs), (ins i8mem:$dst),
2260 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2261 TB; // [mem8] = > signed
2263 def SETSr : I<0x98, MRM0r,
2264 (outs GR8 :$dst), (ins),
2266 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2267 TB; // GR8 = <sign bit>
2268 def SETSm : I<0x98, MRM0m,
2269 (outs), (ins i8mem:$dst),
2271 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2272 TB; // [mem8] = <sign bit>
2273 def SETNSr : I<0x99, MRM0r,
2274 (outs GR8 :$dst), (ins),
2276 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2277 TB; // GR8 = !<sign bit>
2278 def SETNSm : I<0x99, MRM0m,
2279 (outs), (ins i8mem:$dst),
2281 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2282 TB; // [mem8] = !<sign bit>
2283 def SETPr : I<0x9A, MRM0r,
2284 (outs GR8 :$dst), (ins),
2286 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2288 def SETPm : I<0x9A, MRM0m,
2289 (outs), (ins i8mem:$dst),
2291 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2292 TB; // [mem8] = parity
2293 def SETNPr : I<0x9B, MRM0r,
2294 (outs GR8 :$dst), (ins),
2296 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2297 TB; // GR8 = not parity
2298 def SETNPm : I<0x9B, MRM0m,
2299 (outs), (ins i8mem:$dst),
2301 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2302 TB; // [mem8] = not parity
2303 } // Uses = [EFLAGS]
2306 // Integer comparisons
2307 let Defs = [EFLAGS] in {
2308 def CMP8rr : I<0x38, MRMDestReg,
2309 (outs), (ins GR8 :$src1, GR8 :$src2),
2310 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2311 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2312 def CMP16rr : I<0x39, MRMDestReg,
2313 (outs), (ins GR16:$src1, GR16:$src2),
2314 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2315 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2316 def CMP32rr : I<0x39, MRMDestReg,
2317 (outs), (ins GR32:$src1, GR32:$src2),
2318 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2319 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2320 def CMP8mr : I<0x38, MRMDestMem,
2321 (outs), (ins i8mem :$src1, GR8 :$src2),
2322 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2323 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2324 (implicit EFLAGS)]>;
2325 def CMP16mr : I<0x39, MRMDestMem,
2326 (outs), (ins i16mem:$src1, GR16:$src2),
2327 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2328 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2329 (implicit EFLAGS)]>, OpSize;
2330 def CMP32mr : I<0x39, MRMDestMem,
2331 (outs), (ins i32mem:$src1, GR32:$src2),
2332 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2333 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2334 (implicit EFLAGS)]>;
2335 def CMP8rm : I<0x3A, MRMSrcMem,
2336 (outs), (ins GR8 :$src1, i8mem :$src2),
2337 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2338 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2339 (implicit EFLAGS)]>;
2340 def CMP16rm : I<0x3B, MRMSrcMem,
2341 (outs), (ins GR16:$src1, i16mem:$src2),
2342 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2343 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2344 (implicit EFLAGS)]>, OpSize;
2345 def CMP32rm : I<0x3B, MRMSrcMem,
2346 (outs), (ins GR32:$src1, i32mem:$src2),
2347 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2348 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2349 (implicit EFLAGS)]>;
2350 def CMP8ri : Ii8<0x80, MRM7r,
2351 (outs), (ins GR8:$src1, i8imm:$src2),
2352 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2353 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
2354 def CMP16ri : Ii16<0x81, MRM7r,
2355 (outs), (ins GR16:$src1, i16imm:$src2),
2356 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2357 [(X86cmp GR16:$src1, imm:$src2),
2358 (implicit EFLAGS)]>, OpSize;
2359 def CMP32ri : Ii32<0x81, MRM7r,
2360 (outs), (ins GR32:$src1, i32imm:$src2),
2361 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2362 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
2363 def CMP8mi : Ii8 <0x80, MRM7m,
2364 (outs), (ins i8mem :$src1, i8imm :$src2),
2365 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2366 [(X86cmp (loadi8 addr:$src1), imm:$src2),
2367 (implicit EFLAGS)]>;
2368 def CMP16mi : Ii16<0x81, MRM7m,
2369 (outs), (ins i16mem:$src1, i16imm:$src2),
2370 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2371 [(X86cmp (loadi16 addr:$src1), imm:$src2),
2372 (implicit EFLAGS)]>, OpSize;
2373 def CMP32mi : Ii32<0x81, MRM7m,
2374 (outs), (ins i32mem:$src1, i32imm:$src2),
2375 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2376 [(X86cmp (loadi32 addr:$src1), imm:$src2),
2377 (implicit EFLAGS)]>;
2378 def CMP16ri8 : Ii8<0x83, MRM7r,
2379 (outs), (ins GR16:$src1, i16i8imm:$src2),
2380 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2381 [(X86cmp GR16:$src1, i16immSExt8:$src2),
2382 (implicit EFLAGS)]>, OpSize;
2383 def CMP16mi8 : Ii8<0x83, MRM7m,
2384 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2385 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2386 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
2387 (implicit EFLAGS)]>, OpSize;
2388 def CMP32mi8 : Ii8<0x83, MRM7m,
2389 (outs), (ins i32mem:$src1, i32i8imm:$src2),
2390 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2391 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
2392 (implicit EFLAGS)]>;
2393 def CMP32ri8 : Ii8<0x83, MRM7r,
2394 (outs), (ins GR32:$src1, i32i8imm:$src2),
2395 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2396 [(X86cmp GR32:$src1, i32immSExt8:$src2),
2397 (implicit EFLAGS)]>;
2398 } // Defs = [EFLAGS]
2400 // Sign/Zero extenders
2401 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2402 "movs{bw|x}\t{$src, $dst|$dst, $src}",
2403 [(set GR16:$dst, (sext GR8:$src))]>, TB, OpSize;
2404 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2405 "movs{bw|x}\t{$src, $dst|$dst, $src}",
2406 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize;
2407 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2408 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2409 [(set GR32:$dst, (sext GR8:$src))]>, TB;
2410 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2411 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2412 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
2413 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2414 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2415 [(set GR32:$dst, (sext GR16:$src))]>, TB;
2416 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2417 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2418 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
2420 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2421 "movz{bw|x}\t{$src, $dst|$dst, $src}",
2422 [(set GR16:$dst, (zext GR8:$src))]>, TB, OpSize;
2423 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2424 "movz{bw|x}\t{$src, $dst|$dst, $src}",
2425 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize;
2426 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2427 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2428 [(set GR32:$dst, (zext GR8:$src))]>, TB;
2429 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2430 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2431 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
2432 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2433 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2434 [(set GR32:$dst, (zext GR16:$src))]>, TB;
2435 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2436 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2437 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
2439 let neverHasSideEffects = 1 in {
2440 let Defs = [AX], Uses = [AL] in
2441 def CBW : I<0x98, RawFrm, (outs), (ins),
2442 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
2443 let Defs = [EAX], Uses = [AX] in
2444 def CWDE : I<0x98, RawFrm, (outs), (ins),
2445 "{cwtl|cwde}", []>; // EAX = signext(AX)
2447 let Defs = [AX,DX], Uses = [AX] in
2448 def CWD : I<0x99, RawFrm, (outs), (ins),
2449 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
2450 let Defs = [EAX,EDX], Uses = [EAX] in
2451 def CDQ : I<0x99, RawFrm, (outs), (ins),
2452 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
2455 //===----------------------------------------------------------------------===//
2456 // Alias Instructions
2457 //===----------------------------------------------------------------------===//
2459 // Alias instructions that map movr0 to xor.
2460 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2461 let Defs = [EFLAGS], isReMaterializable = 1 in {
2462 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
2463 "xor{b}\t$dst, $dst",
2464 [(set GR8:$dst, 0)]>;
2465 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
2466 "xor{w}\t$dst, $dst",
2467 [(set GR16:$dst, 0)]>, OpSize;
2468 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
2469 "xor{l}\t$dst, $dst",
2470 [(set GR32:$dst, 0)]>;
2473 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
2474 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
2475 let neverHasSideEffects = 1 in {
2476 def MOV16to16_ : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16:$src),
2477 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2478 def MOV32to32_ : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32:$src),
2479 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2481 def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src),
2482 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2483 def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src),
2484 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2485 } // neverHasSideEffects
2487 let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
2488 def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src),
2489 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2490 def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src),
2491 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2493 let mayStore = 1, neverHasSideEffects = 1 in {
2494 def MOV16_mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16_:$src),
2495 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2496 def MOV32_mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32_:$src),
2497 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2500 //===----------------------------------------------------------------------===//
2501 // Thread Local Storage Instructions
2505 def TLS_addr : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
2506 "leal\t${sym:mem}(,%ebx,1), $dst",
2507 [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
2509 let AddedComplexity = 10 in
2510 def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
2511 "movl\t%gs:($src), $dst",
2512 [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
2514 let AddedComplexity = 15 in
2515 def TLS_gs_ri : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
2516 "movl\t%gs:${src:mem}, $dst",
2518 (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>;
2520 def TLS_tp : I<0, Pseudo, (outs GR32:$dst), (ins),
2521 "movl\t%gs:0, $dst",
2522 [(set GR32:$dst, X86TLStp)]>;
2524 //===----------------------------------------------------------------------===//
2525 // DWARF Pseudo Instructions
2528 def DWARF_LOC : I<0, Pseudo, (outs),
2529 (ins i32imm:$line, i32imm:$col, i32imm:$file),
2530 ".loc\t${file:debug} ${line:debug} ${col:debug}",
2531 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
2534 //===----------------------------------------------------------------------===//
2535 // EH Pseudo Instructions
2537 let isTerminator = 1, isReturn = 1, isBarrier = 1,
2539 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
2540 "ret\t#eh_return, addr: $addr",
2541 [(X86ehret GR32:$addr)]>;
2545 //===----------------------------------------------------------------------===//
2549 //FIXME: Please check the format Pseudo is certainly wrong, but the opcode and
2550 // prefixes should be correct
2552 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
2553 def CMPXCHG32 : I<0xB1, Pseudo, (outs), (ins i32mem:$ptr, GR32:$swap),
2554 "cmpxchgl $swap,$ptr", []>, TB;
2555 def LCMPXCHG32 : I<0xB1, Pseudo, (outs), (ins i32mem:$ptr, GR32:$swap),
2556 "lock cmpxchgl $swap,$ptr",
2557 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
2560 let Defs = [AX, EFLAGS], Uses = [AX] in {
2561 def CMPXCHG16 : I<0xB1, Pseudo, (outs), (ins i16mem:$ptr, GR16:$swap),
2562 "cmpxchgw $swap,($ptr)", []>, TB, OpSize;
2563 def LCMPXCHG16 : I<0xB1, Pseudo, (outs), (ins i16mem:$ptr, GR16:$swap),
2564 "lock cmpxchgw $swap,$ptr",
2565 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
2567 let Defs = [AL, EFLAGS], Uses = [AL] in {
2568 def CMPXCHG8 : I<0xB0, Pseudo, (outs), (ins i8mem:$ptr, GR8:$swap),
2569 "cmpxchgb $swap,($ptr)", []>, TB;
2570 def LCMPXCHG8 : I<0xB0, Pseudo, (outs), (ins i8mem:$ptr, GR8:$swap),
2571 "lock cmpxchgb $swap,$ptr",
2572 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
2575 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
2576 def LXADD32 : I<0xC1, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2577 "lock xadd $val, $ptr",
2578 [(set GR32:$dst, (atomic_las_32 addr:$ptr, GR32:$val))]>,
2580 def LXADD16 : I<0xC1, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2581 "lock xadd $val, $ptr",
2582 [(set GR16:$dst, (atomic_las_16 addr:$ptr, GR16:$val))]>,
2584 def LXADD8 : I<0xC0, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2585 "lock xadd $val, $ptr",
2586 [(set GR8:$dst, (atomic_las_8 addr:$ptr, GR8:$val))]>,
2588 def XADD32 : I<0xC1, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2589 "xadd $val, $ptr", []>, TB;
2590 def XADD16 : I<0xC1, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2591 "xadd $val, $ptr", []>, TB, OpSize;
2592 def XADD8 : I<0xC0, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2593 "xadd $val, $ptr", []>, TB;
2595 def LXCHG32 : I<0x87, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2596 "lock xchg $val, $ptr",
2597 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>, LOCK;
2598 def LXCHG16 : I<0x87, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2599 "lock xchg $val, $ptr",
2600 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
2602 def LXCHG8 : I<0x86, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2603 "lock xchg $val, $ptr",
2604 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>, LOCK;
2605 def XCHG32 : I<0x87, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2606 "xchg $val, $ptr", []>;
2607 def XCHG16 : I<0x87, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2608 "xchg $val, $ptr", []>, OpSize;
2609 def XCHG8 : I<0x86, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2610 "xchg $val, $ptr", []>;
2613 //===----------------------------------------------------------------------===//
2614 // Non-Instruction Patterns
2615 //===----------------------------------------------------------------------===//
2617 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
2618 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
2619 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
2620 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)), (MOV32ri tglobaltlsaddr:$dst)>;
2621 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
2622 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
2624 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
2625 (ADD32ri GR32:$src1, tconstpool:$src2)>;
2626 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
2627 (ADD32ri GR32:$src1, tjumptable:$src2)>;
2628 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
2629 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
2630 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
2631 (ADD32ri GR32:$src1, texternalsym:$src2)>;
2633 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
2634 (MOV32mi addr:$dst, tglobaladdr:$src)>;
2635 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
2636 (MOV32mi addr:$dst, texternalsym:$src)>;
2640 def : Pat<(X86tailcall GR32:$dst),
2643 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
2645 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
2648 def : Pat<(X86tcret GR32:$dst, imm:$off),
2649 (TCRETURNri GR32:$dst, imm:$off)>;
2651 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
2652 (TCRETURNdi texternalsym:$dst, imm:$off)>;
2654 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
2655 (TCRETURNdi texternalsym:$dst, imm:$off)>;
2657 def : Pat<(X86call (i32 tglobaladdr:$dst)),
2658 (CALLpcrel32 tglobaladdr:$dst)>;
2659 def : Pat<(X86call (i32 texternalsym:$dst)),
2660 (CALLpcrel32 texternalsym:$dst)>;
2662 // X86 specific add which produces a flag.
2663 def : Pat<(addc GR32:$src1, GR32:$src2),
2664 (ADD32rr GR32:$src1, GR32:$src2)>;
2665 def : Pat<(addc GR32:$src1, (load addr:$src2)),
2666 (ADD32rm GR32:$src1, addr:$src2)>;
2667 def : Pat<(addc GR32:$src1, imm:$src2),
2668 (ADD32ri GR32:$src1, imm:$src2)>;
2669 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
2670 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
2672 def : Pat<(subc GR32:$src1, GR32:$src2),
2673 (SUB32rr GR32:$src1, GR32:$src2)>;
2674 def : Pat<(subc GR32:$src1, (load addr:$src2)),
2675 (SUB32rm GR32:$src1, addr:$src2)>;
2676 def : Pat<(subc GR32:$src1, imm:$src2),
2677 (SUB32ri GR32:$src1, imm:$src2)>;
2678 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
2679 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
2683 // TEST R,R is smaller than CMP R,0
2684 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
2685 (TEST8rr GR8:$src1, GR8:$src1)>;
2686 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
2687 (TEST16rr GR16:$src1, GR16:$src1)>;
2688 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
2689 (TEST32rr GR32:$src1, GR32:$src1)>;
2691 // zextload bool -> zextload byte
2692 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2693 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2694 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2696 // extload bool -> extload byte
2697 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2698 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2699 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2700 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
2701 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
2702 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
2705 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
2706 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
2707 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
2708 def : Pat<(i16 (anyext (loadi8 addr:$src))), (MOVZX16rm8 addr:$src)>;
2709 def : Pat<(i32 (anyext (loadi8 addr:$src))), (MOVZX32rm8 addr:$src)>;
2710 def : Pat<(i32 (anyext (loadi16 addr:$src))), (MOVZX32rm16 addr:$src)>;
2712 // (and (i32 load), 255) -> (zextload i8)
2713 def : Pat<(i32 (and (loadi32 addr:$src), (i32 255))), (MOVZX32rm8 addr:$src)>;
2714 def : Pat<(i32 (and (loadi32 addr:$src), (i32 65535))),(MOVZX32rm16 addr:$src)>;
2716 //===----------------------------------------------------------------------===//
2718 //===----------------------------------------------------------------------===//
2720 // (shl x, 1) ==> (add x, x)
2721 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
2722 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
2723 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
2725 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
2726 def : Pat<(or (srl GR32:$src1, CL:$amt),
2727 (shl GR32:$src2, (sub 32, CL:$amt))),
2728 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
2730 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
2731 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2732 (SHRD32mrCL addr:$dst, GR32:$src2)>;
2734 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
2735 def : Pat<(or (shl GR32:$src1, CL:$amt),
2736 (srl GR32:$src2, (sub 32, CL:$amt))),
2737 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
2739 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
2740 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2741 (SHLD32mrCL addr:$dst, GR32:$src2)>;
2743 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
2744 def : Pat<(or (srl GR16:$src1, CL:$amt),
2745 (shl GR16:$src2, (sub 16, CL:$amt))),
2746 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
2748 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
2749 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2750 (SHRD16mrCL addr:$dst, GR16:$src2)>;
2752 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
2753 def : Pat<(or (shl GR16:$src1, CL:$amt),
2754 (srl GR16:$src2, (sub 16, CL:$amt))),
2755 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
2757 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
2758 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2759 (SHLD16mrCL addr:$dst, GR16:$src2)>;
2761 //===----------------------------------------------------------------------===//
2762 // Floating Point Stack Support
2763 //===----------------------------------------------------------------------===//
2765 include "X86InstrFPStack.td"
2767 //===----------------------------------------------------------------------===//
2769 //===----------------------------------------------------------------------===//
2771 include "X86Instr64bit.td"
2773 //===----------------------------------------------------------------------===//
2774 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
2775 //===----------------------------------------------------------------------===//
2777 include "X86InstrMMX.td"
2779 //===----------------------------------------------------------------------===//
2780 // XMM Floating point support (requires SSE / SSE2)
2781 //===----------------------------------------------------------------------===//
2783 include "X86InstrSSE.td"