1 //===- X86InstrInfo.td - Main X86 Instruction Definition ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 // RES1, RES2, FLAGS = op LHS, RHS
50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
54 SDTCisInt<0>, SDTCisVT<1, i32>]>;
55 def SDTX86BrCond : SDTypeProfile<0, 3,
56 [SDTCisVT<0, OtherVT>,
57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62 def SDTX86SetCC_C : SDTypeProfile<1, 2,
64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
66 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
68 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
71 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
72 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
74 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
75 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
78 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
80 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
84 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
90 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
92 def SDTX86Void : SDTypeProfile<0, 0, []>;
94 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
96 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
98 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
100 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
102 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
104 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
105 def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
107 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
109 def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE,
111 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
113 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
115 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
119 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
120 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
121 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
122 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
124 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
125 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
127 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
128 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
130 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
131 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
133 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
134 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
135 SDNPMayLoad, SDNPMemOperand]>;
136 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
137 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
138 SDNPMayLoad, SDNPMemOperand]>;
139 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
140 [SDNPHasChain, SDNPMayStore,
141 SDNPMayLoad, SDNPMemOperand]>;
142 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
143 [SDNPHasChain, SDNPMayStore,
144 SDNPMayLoad, SDNPMemOperand]>;
145 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
146 [SDNPHasChain, SDNPMayStore,
147 SDNPMayLoad, SDNPMemOperand]>;
148 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
149 [SDNPHasChain, SDNPMayStore,
150 SDNPMayLoad, SDNPMemOperand]>;
151 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
152 [SDNPHasChain, SDNPMayStore,
153 SDNPMayLoad, SDNPMemOperand]>;
154 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
155 [SDNPHasChain, SDNPMayStore,
156 SDNPMayLoad, SDNPMemOperand]>;
157 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
158 [SDNPHasChain, SDNPMayStore,
159 SDNPMayLoad, SDNPMemOperand]>;
160 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
161 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
163 def X86vastart_save_xmm_regs :
164 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
165 SDT_X86VASTART_SAVE_XMM_REGS,
166 [SDNPHasChain, SDNPVariadic]>;
168 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
169 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
171 def X86callseq_start :
172 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
173 [SDNPHasChain, SDNPOutGlue]>;
175 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
176 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
178 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
179 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
182 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
183 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
184 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
185 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
188 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
189 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
191 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
192 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
194 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
195 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
197 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
200 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
201 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
203 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
205 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
206 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
208 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
210 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
211 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
213 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
214 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
215 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
217 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
219 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
222 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
224 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
225 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
227 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
228 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
230 //===----------------------------------------------------------------------===//
231 // X86 Operand Definitions.
234 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
235 // the index operand of an address, to conform to x86 encoding restrictions.
236 def ptr_rc_nosp : PointerLikeRegClass<1>;
238 // *mem - Operand definitions for the funky X86 addressing mode operands.
240 def X86MemAsmOperand : AsmOperandClass {
242 let SuperClasses = [];
244 def X86AbsMemAsmOperand : AsmOperandClass {
246 let SuperClasses = [X86MemAsmOperand];
248 class X86MemOperand<string printMethod> : Operand<iPTR> {
249 let PrintMethod = printMethod;
250 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
251 let ParserMatchClass = X86MemAsmOperand;
254 def opaque32mem : X86MemOperand<"printopaquemem">;
255 def opaque48mem : X86MemOperand<"printopaquemem">;
256 def opaque80mem : X86MemOperand<"printopaquemem">;
257 def opaque512mem : X86MemOperand<"printopaquemem">;
259 def i8mem : X86MemOperand<"printi8mem">;
260 def i16mem : X86MemOperand<"printi16mem">;
261 def i32mem : X86MemOperand<"printi32mem">;
262 def i64mem : X86MemOperand<"printi64mem">;
263 def i128mem : X86MemOperand<"printi128mem">;
264 def i256mem : X86MemOperand<"printi256mem">;
265 def f32mem : X86MemOperand<"printf32mem">;
266 def f64mem : X86MemOperand<"printf64mem">;
267 def f80mem : X86MemOperand<"printf80mem">;
268 def f128mem : X86MemOperand<"printf128mem">;
269 def f256mem : X86MemOperand<"printf256mem">;
271 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
272 // plain GR64, so that it doesn't potentially require a REX prefix.
273 def i8mem_NOREX : Operand<i64> {
274 let PrintMethod = "printi8mem";
275 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
276 let ParserMatchClass = X86MemAsmOperand;
279 // GPRs available for tailcall.
280 // It represents GR64_TC or GR64_TCW64.
281 def ptr_rc_tailcall : PointerLikeRegClass<2>;
283 // Special i32mem for addresses of load folding tail calls. These are not
284 // allowed to use callee-saved registers since they must be scheduled
285 // after callee-saved register are popped.
286 def i32mem_TC : Operand<i32> {
287 let PrintMethod = "printi32mem";
288 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
289 let ParserMatchClass = X86MemAsmOperand;
292 // Special i64mem for addresses of load folding tail calls. These are not
293 // allowed to use callee-saved registers since they must be scheduled
294 // after callee-saved register are popped.
295 def i64mem_TC : Operand<i64> {
296 let PrintMethod = "printi64mem";
297 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
298 ptr_rc_tailcall, i32imm, i8imm);
299 let ParserMatchClass = X86MemAsmOperand;
302 let ParserMatchClass = X86AbsMemAsmOperand,
303 PrintMethod = "print_pcrel_imm" in {
304 def i32imm_pcrel : Operand<i32>;
305 def i16imm_pcrel : Operand<i16>;
307 def offset8 : Operand<i64>;
308 def offset16 : Operand<i64>;
309 def offset32 : Operand<i64>;
310 def offset64 : Operand<i64>;
312 // Branch targets have OtherVT type and print as pc-relative values.
313 def brtarget : Operand<OtherVT>;
314 def brtarget8 : Operand<OtherVT>;
318 def SSECC : Operand<i8> {
319 let PrintMethod = "printSSECC";
322 class ImmSExtAsmOperandClass : AsmOperandClass {
323 let SuperClasses = [ImmAsmOperand];
324 let RenderMethod = "addImmOperands";
327 // Sign-extended immediate classes. We don't need to define the full lattice
328 // here because there is no instruction with an ambiguity between ImmSExti64i32
331 // The strange ranges come from the fact that the assembler always works with
332 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
333 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
336 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
337 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
338 let Name = "ImmSExti64i32";
341 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
342 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
343 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
344 let Name = "ImmSExti16i8";
345 let SuperClasses = [ImmSExti64i32AsmOperand];
348 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
349 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
350 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
351 let Name = "ImmSExti32i8";
355 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
356 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
357 let Name = "ImmSExti64i8";
358 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
359 ImmSExti64i32AsmOperand];
362 // A couple of more descriptive operand definitions.
363 // 16-bits but only 8 bits are significant.
364 def i16i8imm : Operand<i16> {
365 let ParserMatchClass = ImmSExti16i8AsmOperand;
367 // 32-bits but only 8 bits are significant.
368 def i32i8imm : Operand<i32> {
369 let ParserMatchClass = ImmSExti32i8AsmOperand;
372 // 64-bits but only 32 bits are significant.
373 def i64i32imm : Operand<i64> {
374 let ParserMatchClass = ImmSExti64i32AsmOperand;
377 // 64-bits but only 32 bits are significant, and those bits are treated as being
379 def i64i32imm_pcrel : Operand<i64> {
380 let PrintMethod = "print_pcrel_imm";
381 let ParserMatchClass = X86AbsMemAsmOperand;
384 // 64-bits but only 8 bits are significant.
385 def i64i8imm : Operand<i64> {
386 let ParserMatchClass = ImmSExti64i8AsmOperand;
389 def lea64_32mem : Operand<i32> {
390 let PrintMethod = "printi32mem";
391 let AsmOperandLowerMethod = "lower_lea64_32mem";
392 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm);
393 let ParserMatchClass = X86MemAsmOperand;
397 //===----------------------------------------------------------------------===//
398 // X86 Complex Pattern Definitions.
401 // Define X86 specific addressing mode.
402 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
403 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
404 [add, sub, mul, X86mul_imm, shl, or, frameindex],
406 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
407 [tglobaltlsaddr], []>;
409 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
410 [add, sub, mul, X86mul_imm, shl, or, frameindex,
413 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
414 [tglobaltlsaddr], []>;
416 //===----------------------------------------------------------------------===//
417 // X86 Instruction Predicate Definitions.
418 def HasCMov : Predicate<"Subtarget->hasCMov()">;
419 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
421 def HasMMX : Predicate<"Subtarget->hasMMX()">;
422 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
423 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
424 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
425 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
426 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
427 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
428 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
429 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
430 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
432 def HasAVX : Predicate<"Subtarget->hasAVX()">;
433 def HasXMMInt : Predicate<"Subtarget->hasXMMInt()">;
435 def HasAES : Predicate<"Subtarget->hasAES()">;
436 def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">;
437 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
438 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
439 def FPStackf32 : Predicate<"!Subtarget->hasXMM()">;
440 def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">;
441 def In32BitMode : Predicate<"!Subtarget->is64Bit()">, AssemblerPredicate;
442 def In64BitMode : Predicate<"Subtarget->is64Bit()">, AssemblerPredicate;
443 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
444 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
445 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
446 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
447 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
448 "TM.getCodeModel() != CodeModel::Kernel">;
449 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
450 "TM.getCodeModel() == CodeModel::Kernel">;
451 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
452 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
453 def OptForSize : Predicate<"OptForSize">;
454 def OptForSpeed : Predicate<"!OptForSize">;
455 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
456 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
458 //===----------------------------------------------------------------------===//
459 // X86 Instruction Format Definitions.
462 include "X86InstrFormats.td"
464 //===----------------------------------------------------------------------===//
465 // Pattern fragments.
468 // X86 specific condition code. These correspond to CondCode in
469 // X86InstrInfo.h. They must be kept in synch.
470 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
471 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
472 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
473 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
474 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
475 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
476 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
477 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
478 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
479 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
480 def X86_COND_NO : PatLeaf<(i8 10)>;
481 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
482 def X86_COND_NS : PatLeaf<(i8 12)>;
483 def X86_COND_O : PatLeaf<(i8 13)>;
484 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
485 def X86_COND_S : PatLeaf<(i8 15)>;
487 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
488 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
489 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
490 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
493 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
496 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
498 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
500 def i64immZExt32SExt8 : ImmLeaf<i64, [{
501 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
504 // Helper fragments for loads.
505 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
506 // known to be 32-bit aligned or better. Ditto for i8 to i16.
507 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
508 LoadSDNode *LD = cast<LoadSDNode>(N);
509 ISD::LoadExtType ExtType = LD->getExtensionType();
510 if (ExtType == ISD::NON_EXTLOAD)
512 if (ExtType == ISD::EXTLOAD)
513 return LD->getAlignment() >= 2 && !LD->isVolatile();
517 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
518 LoadSDNode *LD = cast<LoadSDNode>(N);
519 ISD::LoadExtType ExtType = LD->getExtensionType();
520 if (ExtType == ISD::EXTLOAD)
521 return LD->getAlignment() >= 2 && !LD->isVolatile();
525 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
526 LoadSDNode *LD = cast<LoadSDNode>(N);
527 ISD::LoadExtType ExtType = LD->getExtensionType();
528 if (ExtType == ISD::NON_EXTLOAD)
530 if (ExtType == ISD::EXTLOAD)
531 return LD->getAlignment() >= 4 && !LD->isVolatile();
535 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
536 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
537 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
538 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
539 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
541 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
542 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
543 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
544 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
545 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
546 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
548 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
549 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
550 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
551 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
552 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
553 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
554 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
555 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
556 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
557 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
559 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
560 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
561 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
562 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
563 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
564 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
565 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
566 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
567 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
568 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
571 // An 'and' node with a single use.
572 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
573 return N->hasOneUse();
575 // An 'srl' node with a single use.
576 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
577 return N->hasOneUse();
579 // An 'trunc' node with a single use.
580 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
581 return N->hasOneUse();
584 //===----------------------------------------------------------------------===//
589 let neverHasSideEffects = 1 in {
590 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
591 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
592 "nop{w}\t$zero", []>, TB, OpSize;
593 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
594 "nop{l}\t$zero", []>, TB;
598 // Constructing a stack frame.
599 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
600 "enter\t$len, $lvl", []>;
602 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
603 def LEAVE : I<0xC9, RawFrm,
604 (outs), (ins), "leave", []>, Requires<[In32BitMode]>;
606 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
607 def LEAVE64 : I<0xC9, RawFrm,
608 (outs), (ins), "leave", []>, Requires<[In64BitMode]>;
610 //===----------------------------------------------------------------------===//
611 // Miscellaneous Instructions.
614 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
616 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
618 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
619 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
621 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
623 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
624 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
626 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
627 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
628 Requires<[In32BitMode]>;
631 let mayStore = 1 in {
632 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
634 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
635 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
637 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
639 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
640 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
642 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
643 "push{l}\t$imm", []>;
644 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
645 "push{w}\t$imm", []>, OpSize;
646 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
647 "push{l}\t$imm", []>;
649 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
650 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
651 Requires<[In32BitMode]>;
656 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
658 def POP64r : I<0x58, AddRegFrm,
659 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
660 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
661 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
663 let mayStore = 1 in {
664 def PUSH64r : I<0x50, AddRegFrm,
665 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
666 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
667 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
671 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
672 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
673 "push{q}\t$imm", []>;
674 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
675 "push{q}\t$imm", []>;
676 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
677 "push{q}\t$imm", []>;
680 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
681 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>,
682 Requires<[In64BitMode]>;
683 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
684 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>,
685 Requires<[In64BitMode]>;
689 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
690 mayLoad=1, neverHasSideEffects=1 in {
691 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>,
692 Requires<[In32BitMode]>;
694 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
695 mayStore=1, neverHasSideEffects=1 in {
696 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>,
697 Requires<[In32BitMode]>;
700 let Constraints = "$src = $dst" in { // GR32 = bswap GR32
701 def BSWAP32r : I<0xC8, AddRegFrm,
702 (outs GR32:$dst), (ins GR32:$src),
704 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
706 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
708 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
709 } // Constraints = "$src = $dst"
711 // Bit scan instructions.
712 let Defs = [EFLAGS] in {
713 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
714 "bsf{w}\t{$src, $dst|$dst, $src}",
715 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
716 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
717 "bsf{w}\t{$src, $dst|$dst, $src}",
718 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
720 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
721 "bsf{l}\t{$src, $dst|$dst, $src}",
722 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
723 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
724 "bsf{l}\t{$src, $dst|$dst, $src}",
725 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
726 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
727 "bsf{q}\t{$src, $dst|$dst, $src}",
728 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB;
729 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
730 "bsf{q}\t{$src, $dst|$dst, $src}",
731 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, TB;
733 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
734 "bsr{w}\t{$src, $dst|$dst, $src}",
735 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
736 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
737 "bsr{w}\t{$src, $dst|$dst, $src}",
738 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
740 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
741 "bsr{l}\t{$src, $dst|$dst, $src}",
742 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
743 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
744 "bsr{l}\t{$src, $dst|$dst, $src}",
745 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
746 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
747 "bsr{q}\t{$src, $dst|$dst, $src}",
748 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, TB;
749 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
750 "bsr{q}\t{$src, $dst|$dst, $src}",
751 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, TB;
755 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
756 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
757 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
758 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
759 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
760 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", []>;
763 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
764 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
765 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
766 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
767 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
768 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
769 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
770 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
771 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", []>;
773 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
774 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
775 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
776 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", []>;
778 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
779 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
780 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
781 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", []>;
784 //===----------------------------------------------------------------------===//
785 // Move Instructions.
788 let neverHasSideEffects = 1 in {
789 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
790 "mov{b}\t{$src, $dst|$dst, $src}", []>;
791 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
792 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
793 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
794 "mov{l}\t{$src, $dst|$dst, $src}", []>;
795 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
796 "mov{q}\t{$src, $dst|$dst, $src}", []>;
798 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
799 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
800 "mov{b}\t{$src, $dst|$dst, $src}",
801 [(set GR8:$dst, imm:$src)]>;
802 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
803 "mov{w}\t{$src, $dst|$dst, $src}",
804 [(set GR16:$dst, imm:$src)]>, OpSize;
805 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
806 "mov{l}\t{$src, $dst|$dst, $src}",
807 [(set GR32:$dst, imm:$src)]>;
808 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
809 "movabs{q}\t{$src, $dst|$dst, $src}",
810 [(set GR64:$dst, imm:$src)]>;
811 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
812 "mov{q}\t{$src, $dst|$dst, $src}",
813 [(set GR64:$dst, i64immSExt32:$src)]>;
816 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
817 "mov{b}\t{$src, $dst|$dst, $src}",
818 [(store (i8 imm:$src), addr:$dst)]>;
819 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
820 "mov{w}\t{$src, $dst|$dst, $src}",
821 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
822 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
823 "mov{l}\t{$src, $dst|$dst, $src}",
824 [(store (i32 imm:$src), addr:$dst)]>;
825 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
826 "mov{q}\t{$src, $dst|$dst, $src}",
827 [(store i64immSExt32:$src, addr:$dst)]>;
829 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
830 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
831 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
832 "mov{b}\t{$src, %al|%al, $src}", []>,
833 Requires<[In32BitMode]>;
834 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
835 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize,
836 Requires<[In32BitMode]>;
837 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
838 "mov{l}\t{$src, %eax|%eax, $src}", []>,
839 Requires<[In32BitMode]>;
840 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
841 "mov{b}\t{%al, $dst|$dst, %al}", []>,
842 Requires<[In32BitMode]>;
843 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
844 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize,
845 Requires<[In32BitMode]>;
846 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
847 "mov{l}\t{%eax, $dst|$dst, %eax}", []>,
848 Requires<[In32BitMode]>;
850 // FIXME: These definitions are utterly broken
851 // Just leave them commented out for now because they're useless outside
852 // of the large code model, and most compilers won't generate the instructions
855 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
856 "mov{q}\t{$src, %rax|%rax, $src}", []>;
857 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
858 "mov{q}\t{$src, %rax|%rax, $src}", []>;
859 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
860 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
861 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
862 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
866 let isCodeGenOnly = 1 in {
867 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
868 "mov{b}\t{$src, $dst|$dst, $src}", []>;
869 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
870 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
871 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
872 "mov{l}\t{$src, $dst|$dst, $src}", []>;
873 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
874 "mov{q}\t{$src, $dst|$dst, $src}", []>;
877 let canFoldAsLoad = 1, isReMaterializable = 1 in {
878 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
879 "mov{b}\t{$src, $dst|$dst, $src}",
880 [(set GR8:$dst, (loadi8 addr:$src))]>;
881 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
882 "mov{w}\t{$src, $dst|$dst, $src}",
883 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
884 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
885 "mov{l}\t{$src, $dst|$dst, $src}",
886 [(set GR32:$dst, (loadi32 addr:$src))]>;
887 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
888 "mov{q}\t{$src, $dst|$dst, $src}",
889 [(set GR64:$dst, (load addr:$src))]>;
892 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
893 "mov{b}\t{$src, $dst|$dst, $src}",
894 [(store GR8:$src, addr:$dst)]>;
895 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
896 "mov{w}\t{$src, $dst|$dst, $src}",
897 [(store GR16:$src, addr:$dst)]>, OpSize;
898 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
899 "mov{l}\t{$src, $dst|$dst, $src}",
900 [(store GR32:$src, addr:$dst)]>;
901 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
902 "mov{q}\t{$src, $dst|$dst, $src}",
903 [(store GR64:$src, addr:$dst)]>;
905 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
906 // that they can be used for copying and storing h registers, which can't be
907 // encoded when a REX prefix is present.
908 let isCodeGenOnly = 1 in {
909 let neverHasSideEffects = 1 in
910 def MOV8rr_NOREX : I<0x88, MRMDestReg,
911 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
912 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
914 def MOV8mr_NOREX : I<0x88, MRMDestMem,
915 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
916 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
918 canFoldAsLoad = 1, isReMaterializable = 1 in
919 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
920 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
921 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
925 // Condition code ops, incl. set if equal/not equal/...
926 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
927 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
928 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
929 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
932 //===----------------------------------------------------------------------===//
933 // Bit tests instructions: BT, BTS, BTR, BTC.
935 let Defs = [EFLAGS] in {
936 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
937 "bt{w}\t{$src2, $src1|$src1, $src2}",
938 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
939 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
940 "bt{l}\t{$src2, $src1|$src1, $src2}",
941 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
942 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
943 "bt{q}\t{$src2, $src1|$src1, $src2}",
944 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB;
946 // Unlike with the register+register form, the memory+register form of the
947 // bt instruction does not ignore the high bits of the index. From ISel's
948 // perspective, this is pretty bizarre. Make these instructions disassembly
951 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
952 "bt{w}\t{$src2, $src1|$src1, $src2}",
953 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
954 // (implicit EFLAGS)]
956 >, OpSize, TB, Requires<[FastBTMem]>;
957 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
958 "bt{l}\t{$src2, $src1|$src1, $src2}",
959 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
960 // (implicit EFLAGS)]
962 >, TB, Requires<[FastBTMem]>;
963 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
964 "bt{q}\t{$src2, $src1|$src1, $src2}",
965 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
966 // (implicit EFLAGS)]
970 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
971 "bt{w}\t{$src2, $src1|$src1, $src2}",
972 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
974 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
975 "bt{l}\t{$src2, $src1|$src1, $src2}",
976 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
977 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
978 "bt{q}\t{$src2, $src1|$src1, $src2}",
979 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB;
981 // Note that these instructions don't need FastBTMem because that
982 // only applies when the other operand is in a register. When it's
983 // an immediate, bt is still fast.
984 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
985 "bt{w}\t{$src2, $src1|$src1, $src2}",
986 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
988 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
989 "bt{l}\t{$src2, $src1|$src1, $src2}",
990 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
992 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
993 "bt{q}\t{$src2, $src1|$src1, $src2}",
994 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
995 i64immSExt8:$src2))]>, TB;
998 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
999 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1000 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1001 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1002 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1003 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1004 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1005 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1006 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1007 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1008 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1009 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1010 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1011 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1012 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1013 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1014 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1015 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1016 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1017 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1018 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1019 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1020 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1021 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1023 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1024 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1025 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1026 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1027 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1028 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1029 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1030 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1031 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1032 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1033 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1034 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1035 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1036 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1037 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1038 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1039 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1040 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1041 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1042 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1043 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1044 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1045 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1046 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1048 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1049 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1050 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1051 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1052 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1053 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1054 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1055 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1056 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1057 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1058 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1059 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1060 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1061 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1062 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1063 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1064 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1065 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1066 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1067 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1068 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1069 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1070 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1071 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1072 } // Defs = [EFLAGS]
1075 //===----------------------------------------------------------------------===//
1080 // Atomic swap. These are just normal xchg instructions. But since a memory
1081 // operand is referenced, the atomicity is ensured.
1082 let Constraints = "$val = $dst" in {
1083 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
1084 "xchg{b}\t{$val, $ptr|$ptr, $val}",
1085 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
1086 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),(ins GR16:$val, i16mem:$ptr),
1087 "xchg{w}\t{$val, $ptr|$ptr, $val}",
1088 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
1090 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),(ins GR32:$val, i32mem:$ptr),
1091 "xchg{l}\t{$val, $ptr|$ptr, $val}",
1092 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
1093 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),(ins GR64:$val,i64mem:$ptr),
1094 "xchg{q}\t{$val, $ptr|$ptr, $val}",
1095 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1097 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1098 "xchg{b}\t{$val, $src|$src, $val}", []>;
1099 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1100 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
1101 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1102 "xchg{l}\t{$val, $src|$src, $val}", []>;
1103 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1104 "xchg{q}\t{$val, $src|$src, $val}", []>;
1107 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1108 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1109 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1110 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
1111 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1112 "xchg{q}\t{$src, %rax|%rax, $src}", []>;
1116 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1117 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
1118 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1119 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1120 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1121 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
1122 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1123 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1125 let mayLoad = 1, mayStore = 1 in {
1126 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1127 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
1128 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1129 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1130 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1131 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
1132 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1133 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1137 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1138 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
1139 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1140 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1141 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1142 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
1143 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1144 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1146 let mayLoad = 1, mayStore = 1 in {
1147 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1148 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
1149 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1150 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1151 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1152 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
1153 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1154 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1157 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1158 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1159 "cmpxchg8b\t$dst", []>, TB;
1161 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1162 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1163 "cmpxchg16b\t$dst", []>, TB;
1167 // Lock instruction prefix
1168 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1170 // Rex64 instruction prefix
1171 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>;
1173 // Data16 instruction prefix
1174 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1176 // Repeat string operation instruction prefixes
1177 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1178 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1179 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1180 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1181 // Repeat while not equal (used with CMPS and SCAS)
1182 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1186 // String manipulation instructions
1187 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
1188 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
1189 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
1190 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
1192 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
1193 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
1194 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
1197 // Flag instructions
1198 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
1199 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
1200 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
1201 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
1202 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
1203 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
1204 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
1206 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
1208 // Table lookup instructions
1209 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
1211 // ASCII Adjust After Addition
1212 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1213 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>, Requires<[In32BitMode]>;
1215 // ASCII Adjust AX Before Division
1216 // sets AL, AH and EFLAGS and uses AL and AH
1217 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1218 "aad\t$src", []>, Requires<[In32BitMode]>;
1220 // ASCII Adjust AX After Multiply
1221 // sets AL, AH and EFLAGS and uses AL
1222 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1223 "aam\t$src", []>, Requires<[In32BitMode]>;
1225 // ASCII Adjust AL After Subtraction - sets
1226 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1227 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, Requires<[In32BitMode]>;
1229 // Decimal Adjust AL after Addition
1230 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1231 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>, Requires<[In32BitMode]>;
1233 // Decimal Adjust AL after Subtraction
1234 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1235 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, Requires<[In32BitMode]>;
1237 // Check Array Index Against Bounds
1238 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1239 "bound\t{$src, $dst|$dst, $src}", []>, OpSize,
1240 Requires<[In32BitMode]>;
1241 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1242 "bound\t{$src, $dst|$dst, $src}", []>,
1243 Requires<[In32BitMode]>;
1245 // Adjust RPL Field of Segment Selector
1246 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$src), (ins GR16:$dst),
1247 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
1248 def ARPL16mr : I<0x63, MRMSrcMem, (outs GR16:$src), (ins i16mem:$dst),
1249 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
1251 //===----------------------------------------------------------------------===//
1253 //===----------------------------------------------------------------------===//
1255 include "X86InstrArithmetic.td"
1256 include "X86InstrCMovSetCC.td"
1257 include "X86InstrExtension.td"
1258 include "X86InstrControl.td"
1259 include "X86InstrShiftRotate.td"
1261 // X87 Floating Point Stack.
1262 include "X86InstrFPStack.td"
1264 // SIMD support (SSE, MMX and AVX)
1265 include "X86InstrFragmentsSIMD.td"
1267 // FMA - Fused Multiply-Add support (requires FMA)
1268 include "X86InstrFMA.td"
1270 // SSE, MMX and 3DNow! vector support.
1271 include "X86InstrSSE.td"
1272 include "X86InstrMMX.td"
1273 include "X86Instr3DNow.td"
1275 include "X86InstrVMX.td"
1277 // System instructions.
1278 include "X86InstrSystem.td"
1280 // Compiler Pseudo Instructions and Pat Patterns
1281 include "X86InstrCompiler.td"
1283 //===----------------------------------------------------------------------===//
1284 // Assembler Mnemonic Aliases
1285 //===----------------------------------------------------------------------===//
1287 def : MnemonicAlias<"call", "calll">, Requires<[In32BitMode]>;
1288 def : MnemonicAlias<"call", "callq">, Requires<[In64BitMode]>;
1290 def : MnemonicAlias<"cbw", "cbtw">;
1291 def : MnemonicAlias<"cwd", "cwtd">;
1292 def : MnemonicAlias<"cdq", "cltd">;
1293 def : MnemonicAlias<"cwde", "cwtl">;
1294 def : MnemonicAlias<"cdqe", "cltq">;
1296 // lret maps to lretl, it is not ambiguous with lretq.
1297 def : MnemonicAlias<"lret", "lretl">;
1299 def : MnemonicAlias<"leavel", "leave">, Requires<[In32BitMode]>;
1300 def : MnemonicAlias<"leaveq", "leave">, Requires<[In64BitMode]>;
1302 def : MnemonicAlias<"loopz", "loope">;
1303 def : MnemonicAlias<"loopnz", "loopne">;
1305 def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
1306 def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
1307 def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>;
1308 def : MnemonicAlias<"popf", "popfq">, Requires<[In64BitMode]>;
1309 def : MnemonicAlias<"popfd", "popfl">;
1311 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
1312 // all modes. However: "push (addr)" and "push $42" should default to
1313 // pushl/pushq depending on the current mode. Similar for "pop %bx"
1314 def : MnemonicAlias<"push", "pushl">, Requires<[In32BitMode]>;
1315 def : MnemonicAlias<"push", "pushq">, Requires<[In64BitMode]>;
1316 def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
1317 def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1318 def : MnemonicAlias<"pushfd", "pushfl">;
1320 def : MnemonicAlias<"repe", "rep">;
1321 def : MnemonicAlias<"repz", "rep">;
1322 def : MnemonicAlias<"repnz", "repne">;
1324 def : MnemonicAlias<"retl", "ret">, Requires<[In32BitMode]>;
1325 def : MnemonicAlias<"retq", "ret">, Requires<[In64BitMode]>;
1327 def : MnemonicAlias<"salb", "shlb">;
1328 def : MnemonicAlias<"salw", "shlw">;
1329 def : MnemonicAlias<"sall", "shll">;
1330 def : MnemonicAlias<"salq", "shlq">;
1332 def : MnemonicAlias<"smovb", "movsb">;
1333 def : MnemonicAlias<"smovw", "movsw">;
1334 def : MnemonicAlias<"smovl", "movsl">;
1335 def : MnemonicAlias<"smovq", "movsq">;
1337 def : MnemonicAlias<"ud2a", "ud2">;
1338 def : MnemonicAlias<"verrw", "verr">;
1340 // System instruction aliases.
1341 def : MnemonicAlias<"iret", "iretl">;
1342 def : MnemonicAlias<"sysret", "sysretl">;
1344 def : MnemonicAlias<"lgdtl", "lgdt">, Requires<[In32BitMode]>;
1345 def : MnemonicAlias<"lgdtq", "lgdt">, Requires<[In64BitMode]>;
1346 def : MnemonicAlias<"lidtl", "lidt">, Requires<[In32BitMode]>;
1347 def : MnemonicAlias<"lidtq", "lidt">, Requires<[In64BitMode]>;
1348 def : MnemonicAlias<"sgdtl", "sgdt">, Requires<[In32BitMode]>;
1349 def : MnemonicAlias<"sgdtq", "sgdt">, Requires<[In64BitMode]>;
1350 def : MnemonicAlias<"sidtl", "sidt">, Requires<[In32BitMode]>;
1351 def : MnemonicAlias<"sidtq", "sidt">, Requires<[In64BitMode]>;
1354 // Floating point stack aliases.
1355 def : MnemonicAlias<"fcmovz", "fcmove">;
1356 def : MnemonicAlias<"fcmova", "fcmovnbe">;
1357 def : MnemonicAlias<"fcmovnae", "fcmovb">;
1358 def : MnemonicAlias<"fcmovna", "fcmovbe">;
1359 def : MnemonicAlias<"fcmovae", "fcmovnb">;
1360 def : MnemonicAlias<"fcomip", "fcompi">;
1361 def : MnemonicAlias<"fildq", "fildll">;
1362 def : MnemonicAlias<"fldcww", "fldcw">;
1363 def : MnemonicAlias<"fnstcww", "fnstcw">;
1364 def : MnemonicAlias<"fnstsww", "fnstsw">;
1365 def : MnemonicAlias<"fucomip", "fucompi">;
1366 def : MnemonicAlias<"fwait", "wait">;
1369 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond>
1370 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
1371 !strconcat(Prefix, NewCond, Suffix)>;
1373 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
1374 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
1375 /// example "setz" -> "sete".
1376 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix> {
1377 def C : CondCodeAlias<Prefix, Suffix, "c", "b">; // setc -> setb
1378 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e">; // setz -> sete
1379 def NA : CondCodeAlias<Prefix, Suffix, "na", "be">; // setna -> setbe
1380 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae">; // setnb -> setae
1381 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae">; // setnc -> setae
1382 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le">; // setng -> setle
1383 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge">; // setnl -> setge
1384 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne">; // setnz -> setne
1385 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p">; // setpe -> setp
1386 def PO : CondCodeAlias<Prefix, Suffix, "po", "np">; // setpo -> setnp
1388 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b">; // setnae -> setb
1389 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a">; // setnbe -> seta
1390 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l">; // setnge -> setl
1391 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g">; // setnle -> setg
1394 // Aliases for set<CC>
1395 defm : IntegerCondCodeMnemonicAlias<"set", "">;
1396 // Aliases for j<CC>
1397 defm : IntegerCondCodeMnemonicAlias<"j", "">;
1398 // Aliases for cmov<CC>{w,l,q}
1399 defm : IntegerCondCodeMnemonicAlias<"cmov", "w">;
1400 defm : IntegerCondCodeMnemonicAlias<"cmov", "l">;
1401 defm : IntegerCondCodeMnemonicAlias<"cmov", "q">;
1404 //===----------------------------------------------------------------------===//
1405 // Assembler Instruction Aliases
1406 //===----------------------------------------------------------------------===//
1408 // aad/aam default to base 10 if no operand is specified.
1409 def : InstAlias<"aad", (AAD8i8 10)>;
1410 def : InstAlias<"aam", (AAM8i8 10)>;
1412 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
1413 def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>;
1416 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>;
1417 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
1418 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
1419 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
1421 // div and idiv aliases for explicit A register.
1422 def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>;
1423 def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>;
1424 def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>;
1425 def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>;
1426 def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>;
1427 def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>;
1428 def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>;
1429 def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>;
1430 def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>;
1431 def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>;
1432 def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>;
1433 def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>;
1434 def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>;
1435 def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>;
1436 def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>;
1437 def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>;
1441 // Various unary fpstack operations default to operating on on ST1.
1442 // For example, "fxch" -> "fxch %st(1)"
1443 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
1444 def : InstAlias<"fsubp", (SUBR_FPrST0 ST1)>;
1445 def : InstAlias<"fsubrp", (SUB_FPrST0 ST1)>;
1446 def : InstAlias<"fmulp", (MUL_FPrST0 ST1)>;
1447 def : InstAlias<"fdivp", (DIVR_FPrST0 ST1)>;
1448 def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>;
1449 def : InstAlias<"fxch", (XCH_F ST1)>;
1450 def : InstAlias<"fcomi", (COM_FIr ST1)>;
1451 def : InstAlias<"fcompi", (COM_FIPr ST1)>;
1452 def : InstAlias<"fucom", (UCOM_Fr ST1)>;
1453 def : InstAlias<"fucomp", (UCOM_FPr ST1)>;
1454 def : InstAlias<"fucomi", (UCOM_FIr ST1)>;
1455 def : InstAlias<"fucompi", (UCOM_FIPr ST1)>;
1457 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
1458 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
1459 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
1461 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
1462 def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"),
1463 (Inst RST:$op), EmitAlias>;
1464 def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"),
1465 (Inst ST0), EmitAlias>;
1468 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
1469 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
1470 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
1471 defm : FpUnaryAlias<"fsubp", SUBR_FPrST0>;
1472 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
1473 defm : FpUnaryAlias<"fsubrp", SUB_FPrST0>;
1474 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
1475 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
1476 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
1477 defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>;
1478 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
1479 defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>;
1480 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
1481 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
1482 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
1483 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
1486 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
1487 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
1488 // solely because gas supports it.
1489 def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op), 0>;
1490 def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>;
1491 def : InstAlias<"fsubp %st(0), $op", (SUBR_FPrST0 RST:$op)>;
1492 def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>;
1493 def : InstAlias<"fdivp %st(0), $op", (DIVR_FPrST0 RST:$op)>;
1494 def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>;
1496 // We accept "fnstsw %eax" even though it only writes %ax.
1497 def : InstAlias<"fnstsw %eax", (FNSTSW8r)>;
1498 def : InstAlias<"fnstsw %al" , (FNSTSW8r)>;
1499 def : InstAlias<"fnstsw" , (FNSTSW8r)>;
1501 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
1502 // this is compatible with what GAS does.
1503 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1504 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1505 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>;
1506 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>;
1508 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
1509 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
1510 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
1511 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
1512 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
1513 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
1514 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
1516 // inb %dx -> inb %al, %dx
1517 def : InstAlias<"inb %dx", (IN8rr)>;
1518 def : InstAlias<"inw %dx", (IN16rr)>;
1519 def : InstAlias<"inl %dx", (IN32rr)>;
1520 def : InstAlias<"inb $port", (IN8ri i8imm:$port)>;
1521 def : InstAlias<"inw $port", (IN16ri i8imm:$port)>;
1522 def : InstAlias<"inl $port", (IN32ri i8imm:$port)>;
1525 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
1526 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1527 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1528 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
1529 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
1530 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1531 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1533 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
1534 // the move. All segment/mem forms are equivalent, this has the shortest
1536 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
1537 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
1539 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
1540 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
1542 // Match 'movq GR64, MMX' as an alias for movd.
1543 def : InstAlias<"movq $src, $dst",
1544 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
1545 def : InstAlias<"movq $src, $dst",
1546 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
1548 // movsd with no operands (as opposed to the SSE scalar move of a double) is an
1549 // alias for movsl. (as in rep; movsd)
1550 def : InstAlias<"movsd", (MOVSD)>;
1553 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
1554 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
1555 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
1556 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
1557 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
1558 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
1559 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
1562 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
1563 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
1564 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
1565 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
1566 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
1567 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
1568 // Note: No GR32->GR64 movzx form.
1570 // outb %dx -> outb %al, %dx
1571 def : InstAlias<"outb %dx", (OUT8rr)>;
1572 def : InstAlias<"outw %dx", (OUT16rr)>;
1573 def : InstAlias<"outl %dx", (OUT32rr)>;
1574 def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>;
1575 def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>;
1576 def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>;
1578 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
1579 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
1580 // errors, since its encoding is the most compact.
1581 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
1583 // shld/shrd op,op -> shld op, op, 1
1584 def : InstAlias<"shldw $r1, $r2", (SHLD16rri8 GR16:$r1, GR16:$r2, 1)>;
1585 def : InstAlias<"shldl $r1, $r2", (SHLD32rri8 GR32:$r1, GR32:$r2, 1)>;
1586 def : InstAlias<"shldq $r1, $r2", (SHLD64rri8 GR64:$r1, GR64:$r2, 1)>;
1587 def : InstAlias<"shrdw $r1, $r2", (SHRD16rri8 GR16:$r1, GR16:$r2, 1)>;
1588 def : InstAlias<"shrdl $r1, $r2", (SHRD32rri8 GR32:$r1, GR32:$r2, 1)>;
1589 def : InstAlias<"shrdq $r1, $r2", (SHRD64rri8 GR64:$r1, GR64:$r2, 1)>;
1591 def : InstAlias<"shldw $mem, $reg", (SHLD16mri8 i16mem:$mem, GR16:$reg, 1)>;
1592 def : InstAlias<"shldl $mem, $reg", (SHLD32mri8 i32mem:$mem, GR32:$reg, 1)>;
1593 def : InstAlias<"shldq $mem, $reg", (SHLD64mri8 i64mem:$mem, GR64:$reg, 1)>;
1594 def : InstAlias<"shrdw $mem, $reg", (SHRD16mri8 i16mem:$mem, GR16:$reg, 1)>;
1595 def : InstAlias<"shrdl $mem, $reg", (SHRD32mri8 i32mem:$mem, GR32:$reg, 1)>;
1596 def : InstAlias<"shrdq $mem, $reg", (SHRD64mri8 i64mem:$mem, GR64:$reg, 1)>;
1598 /* FIXME: This is disabled because the asm matcher is currently incapable of
1599 * matching a fixed immediate like $1.
1600 // "shl X, $1" is an alias for "shl X".
1601 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
1602 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1603 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
1604 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1605 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
1606 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1607 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
1608 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1609 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
1610 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1611 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
1612 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1613 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
1614 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1615 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
1616 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1617 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
1620 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
1621 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
1622 defm : ShiftRotateByOneAlias<"rol", "ROL">;
1623 defm : ShiftRotateByOneAlias<"ror", "ROR">;
1626 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
1627 def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>;
1628 def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>;
1629 def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>;
1630 def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>;
1632 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
1633 def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>;
1634 def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>;
1635 def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>;
1636 def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>;