1 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
30 def SDTX86BrCond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>;
33 def SDTX86SetCC : SDTypeProfile<1, 1,
34 [SDTCisVT<0, i8>, SDTCisVT<1, i8>]>;
36 def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>;
38 def SDT_X86CallSeqStart : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
39 def SDT_X86CallSeqEnd : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>,
42 def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
44 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
46 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
48 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
50 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
51 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
53 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest,
55 def X86test : SDNode<"X86ISD::TEST", SDTX86CmpTest,
58 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov,
59 [SDNPInFlag, SDNPOutFlag]>;
60 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
61 [SDNPHasChain, SDNPInFlag]>;
62 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC,
63 [SDNPInFlag, SDNPOutFlag]>;
65 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
66 [SDNPHasChain, SDNPOptInFlag]>;
68 def X86callseq_start :
69 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
70 [SDNPHasChain, SDNPOutFlag]>;
72 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
73 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
75 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
76 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
78 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
79 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
81 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
82 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
83 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
84 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
86 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
87 [SDNPHasChain, SDNPOutFlag]>;
89 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
91 //===----------------------------------------------------------------------===//
92 // X86 Operand Definitions.
95 // *mem - Operand definitions for the funky X86 addressing mode operands.
97 class X86MemOperand<string printMethod> : Operand<iPTR> {
98 let PrintMethod = printMethod;
99 let NumMIOperands = 4;
100 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
103 def i8mem : X86MemOperand<"printi8mem">;
104 def i16mem : X86MemOperand<"printi16mem">;
105 def i32mem : X86MemOperand<"printi32mem">;
106 def i64mem : X86MemOperand<"printi64mem">;
107 def i128mem : X86MemOperand<"printi128mem">;
108 def f32mem : X86MemOperand<"printf32mem">;
109 def f64mem : X86MemOperand<"printf64mem">;
110 def f128mem : X86MemOperand<"printf128mem">;
112 def SSECC : Operand<i8> {
113 let PrintMethod = "printSSECC";
116 def piclabel: Operand<i32> {
117 let PrintMethod = "printPICLabel";
120 // A couple of more descriptive operand definitions.
121 // 16-bits but only 8 bits are significant.
122 def i16i8imm : Operand<i16>;
123 // 32-bits but only 8 bits are significant.
124 def i32i8imm : Operand<i32>;
126 // Branch targets have OtherVT type.
127 def brtarget : Operand<OtherVT>;
129 //===----------------------------------------------------------------------===//
130 // X86 Complex Pattern Definitions.
133 // Define X86 specific addressing mode.
134 def addr : ComplexPattern<iPTR, 4, "SelectAddr", []>;
135 def leaaddr : ComplexPattern<iPTR, 4, "SelectLEAAddr",
136 [add, mul, shl, or, frameindex]>;
138 //===----------------------------------------------------------------------===//
139 // X86 Instruction Format Definitions.
142 // Format specifies the encoding used by the instruction. This is part of the
143 // ad-hoc solution used to emit machine instruction encodings by our machine
145 class Format<bits<6> val> {
149 def Pseudo : Format<0>; def RawFrm : Format<1>;
150 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
151 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
152 def MRMSrcMem : Format<6>;
153 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
154 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
155 def MRM6r : Format<22>; def MRM7r : Format<23>;
156 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
157 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
158 def MRM6m : Format<30>; def MRM7m : Format<31>;
159 def MRMInitReg : Format<32>;
161 //===----------------------------------------------------------------------===//
162 // X86 Instruction Predicate Definitions.
163 def HasMMX : Predicate<"Subtarget->hasMMX()">;
164 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
165 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
166 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
167 def FPStack : Predicate<"!Subtarget->hasSSE2()">;
169 //===----------------------------------------------------------------------===//
170 // X86 specific pattern fragments.
173 // ImmType - This specifies the immediate type used by an instruction. This is
174 // part of the ad-hoc solution used to emit machine instruction encodings by our
175 // machine code emitter.
176 class ImmType<bits<2> val> {
179 def NoImm : ImmType<0>;
180 def Imm8 : ImmType<1>;
181 def Imm16 : ImmType<2>;
182 def Imm32 : ImmType<3>;
184 // FPFormat - This specifies what form this FP instruction has. This is used by
185 // the Floating-Point stackifier pass.
186 class FPFormat<bits<3> val> {
189 def NotFP : FPFormat<0>;
190 def ZeroArgFP : FPFormat<1>;
191 def OneArgFP : FPFormat<2>;
192 def OneArgFPRW : FPFormat<3>;
193 def TwoArgFP : FPFormat<4>;
194 def CompareFP : FPFormat<5>;
195 def CondMovFP : FPFormat<6>;
196 def SpecialFP : FPFormat<7>;
199 class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr>
201 let Namespace = "X86";
203 bits<8> Opcode = opcod;
205 bits<6> FormBits = Form.Value;
207 bits<2> ImmTypeBits = ImmT.Value;
209 dag OperandList = ops;
210 string AsmString = AsmStr;
213 // Attributes specific to X86 instructions...
215 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
217 bits<4> Prefix = 0; // Which prefix byte does this inst have?
218 FPFormat FPForm; // What flavor of FP instruction is this?
219 bits<3> FPFormBits = 0;
222 class Imp<list<Register> uses, list<Register> defs> {
223 list<Register> Uses = uses;
224 list<Register> Defs = defs;
228 // Prefix byte classes which are used to indicate to the ad-hoc machine code
229 // emitter that various prefix bytes are required.
230 class OpSize { bit hasOpSizePrefix = 1; }
231 class TB { bits<4> Prefix = 1; }
232 class REP { bits<4> Prefix = 2; }
233 class D8 { bits<4> Prefix = 3; }
234 class D9 { bits<4> Prefix = 4; }
235 class DA { bits<4> Prefix = 5; }
236 class DB { bits<4> Prefix = 6; }
237 class DC { bits<4> Prefix = 7; }
238 class DD { bits<4> Prefix = 8; }
239 class DE { bits<4> Prefix = 9; }
240 class DF { bits<4> Prefix = 10; }
241 class XD { bits<4> Prefix = 11; }
242 class XS { bits<4> Prefix = 12; }
245 //===----------------------------------------------------------------------===//
246 // Pattern fragments...
249 // X86 specific condition code. These correspond to CondCode in
250 // X86ISelLowering.h. They must be kept in synch.
251 def X86_COND_A : PatLeaf<(i8 0)>;
252 def X86_COND_AE : PatLeaf<(i8 1)>;
253 def X86_COND_B : PatLeaf<(i8 2)>;
254 def X86_COND_BE : PatLeaf<(i8 3)>;
255 def X86_COND_E : PatLeaf<(i8 4)>;
256 def X86_COND_G : PatLeaf<(i8 5)>;
257 def X86_COND_GE : PatLeaf<(i8 6)>;
258 def X86_COND_L : PatLeaf<(i8 7)>;
259 def X86_COND_LE : PatLeaf<(i8 8)>;
260 def X86_COND_NE : PatLeaf<(i8 9)>;
261 def X86_COND_NO : PatLeaf<(i8 10)>;
262 def X86_COND_NP : PatLeaf<(i8 11)>;
263 def X86_COND_NS : PatLeaf<(i8 12)>;
264 def X86_COND_O : PatLeaf<(i8 13)>;
265 def X86_COND_P : PatLeaf<(i8 14)>;
266 def X86_COND_S : PatLeaf<(i8 15)>;
268 def i16immSExt8 : PatLeaf<(i16 imm), [{
269 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
270 // sign extended field.
271 return (int16_t)N->getValue() == (int8_t)N->getValue();
274 def i32immSExt8 : PatLeaf<(i32 imm), [{
275 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
276 // sign extended field.
277 return (int32_t)N->getValue() == (int8_t)N->getValue();
280 // Helper fragments for loads.
281 def loadiPTR : PatFrag<(ops node:$ptr), (iPTR (load node:$ptr))>;
283 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
284 def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>;
285 def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>;
286 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
288 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
289 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
291 def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i1))>;
292 def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i1))>;
293 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i8))>;
294 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i8))>;
295 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i16))>;
297 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextload node:$ptr, i1))>;
298 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextload node:$ptr, i1))>;
299 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i1))>;
300 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextload node:$ptr, i8))>;
301 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i8))>;
302 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i16))>;
304 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extload node:$ptr, i1))>;
305 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extload node:$ptr, i1))>;
306 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extload node:$ptr, i1))>;
307 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extload node:$ptr, i8))>;
308 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extload node:$ptr, i8))>;
309 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extload node:$ptr, i16))>;
311 //===----------------------------------------------------------------------===//
312 // Instruction templates...
314 class I<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
315 : X86Inst<o, f, NoImm, ops, asm> {
316 let Pattern = pattern;
319 class Ii8 <bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
320 : X86Inst<o, f, Imm8 , ops, asm> {
321 let Pattern = pattern;
324 class Ii16<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
325 : X86Inst<o, f, Imm16, ops, asm> {
326 let Pattern = pattern;
329 class Ii32<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
330 : X86Inst<o, f, Imm32, ops, asm> {
331 let Pattern = pattern;
335 //===----------------------------------------------------------------------===//
336 // Instruction list...
339 def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN",
340 [(X86callseq_start imm:$amt)]>;
341 def ADJCALLSTACKUP : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2),
343 [(X86callseq_end imm:$amt1, imm:$amt2)]>;
344 def IMPLICIT_USE : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE", []>;
345 def IMPLICIT_DEF : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF", []>;
346 def IMPLICIT_DEF_GR8 : I<0, Pseudo, (ops GR8:$dst),
347 "#IMPLICIT_DEF $dst",
348 [(set GR8:$dst, (undef))]>;
349 def IMPLICIT_DEF_GR16 : I<0, Pseudo, (ops GR16:$dst),
350 "#IMPLICIT_DEF $dst",
351 [(set GR16:$dst, (undef))]>;
352 def IMPLICIT_DEF_GR32 : I<0, Pseudo, (ops GR32:$dst),
353 "#IMPLICIT_DEF $dst",
354 [(set GR32:$dst, (undef))]>;
357 def NOOP : I<0x90, RawFrm, (ops), "nop", []>;
360 def TRUNC_GR32_GR8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR32_:$src),
361 "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}", []>;
362 def TRUNC_GR16_GR8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR16_:$src),
363 "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}}", []>;
364 def TRUNC_GR32_GR16 : I<0x89, MRMDestReg, (ops GR16:$dst, GR32:$src),
365 "mov{w} {${src:subreg16}, $dst|$dst, ${src:subreg16}}",
366 [(set GR16:$dst, (trunc GR32:$src))]>;
368 //===----------------------------------------------------------------------===//
369 // Control Flow Instructions...
372 // Return instructions.
373 let isTerminator = 1, isReturn = 1, isBarrier = 1,
374 hasCtrlDep = 1, noResults = 1 in {
375 def RET : I<0xC3, RawFrm, (ops), "ret", [(X86retflag 0)]>;
376 def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt",
377 [(X86retflag imm:$amt)]>;
380 // All branches are RawFrm, Void, Branch, and Terminators
381 let isBranch = 1, isTerminator = 1, noResults = 1 in
382 class IBr<bits<8> opcode, dag ops, string asm, list<dag> pattern> :
383 I<opcode, RawFrm, ops, asm, pattern>;
386 let isBranch = 1, isBarrier = 1 in
387 def JMP : IBr<0xE9, (ops brtarget:$dst), "jmp $dst", [(br bb:$dst)]>;
389 let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in {
390 def JMP32r : I<0xFF, MRM4r, (ops GR32:$dst), "jmp{l} {*}$dst",
391 [(brind GR32:$dst)]>;
392 def JMP32m : I<0xFF, MRM4m, (ops i32mem:$dst), "jmp{l} {*}$dst",
393 [(brind (loadiPTR addr:$dst))]>;
396 // Conditional branches
397 def JE : IBr<0x84, (ops brtarget:$dst), "je $dst",
398 [(X86brcond bb:$dst, X86_COND_E)]>, TB;
399 def JNE : IBr<0x85, (ops brtarget:$dst), "jne $dst",
400 [(X86brcond bb:$dst, X86_COND_NE)]>, TB;
401 def JL : IBr<0x8C, (ops brtarget:$dst), "jl $dst",
402 [(X86brcond bb:$dst, X86_COND_L)]>, TB;
403 def JLE : IBr<0x8E, (ops brtarget:$dst), "jle $dst",
404 [(X86brcond bb:$dst, X86_COND_LE)]>, TB;
405 def JG : IBr<0x8F, (ops brtarget:$dst), "jg $dst",
406 [(X86brcond bb:$dst, X86_COND_G)]>, TB;
407 def JGE : IBr<0x8D, (ops brtarget:$dst), "jge $dst",
408 [(X86brcond bb:$dst, X86_COND_GE)]>, TB;
410 def JB : IBr<0x82, (ops brtarget:$dst), "jb $dst",
411 [(X86brcond bb:$dst, X86_COND_B)]>, TB;
412 def JBE : IBr<0x86, (ops brtarget:$dst), "jbe $dst",
413 [(X86brcond bb:$dst, X86_COND_BE)]>, TB;
414 def JA : IBr<0x87, (ops brtarget:$dst), "ja $dst",
415 [(X86brcond bb:$dst, X86_COND_A)]>, TB;
416 def JAE : IBr<0x83, (ops brtarget:$dst), "jae $dst",
417 [(X86brcond bb:$dst, X86_COND_AE)]>, TB;
419 def JS : IBr<0x88, (ops brtarget:$dst), "js $dst",
420 [(X86brcond bb:$dst, X86_COND_S)]>, TB;
421 def JNS : IBr<0x89, (ops brtarget:$dst), "jns $dst",
422 [(X86brcond bb:$dst, X86_COND_NS)]>, TB;
423 def JP : IBr<0x8A, (ops brtarget:$dst), "jp $dst",
424 [(X86brcond bb:$dst, X86_COND_P)]>, TB;
425 def JNP : IBr<0x8B, (ops brtarget:$dst), "jnp $dst",
426 [(X86brcond bb:$dst, X86_COND_NP)]>, TB;
427 def JO : IBr<0x80, (ops brtarget:$dst), "jo $dst",
428 [(X86brcond bb:$dst, X86_COND_O)]>, TB;
429 def JNO : IBr<0x81, (ops brtarget:$dst), "jno $dst",
430 [(X86brcond bb:$dst, X86_COND_NO)]>, TB;
432 //===----------------------------------------------------------------------===//
433 // Call Instructions...
435 let isCall = 1, noResults = 1 in
436 // All calls clobber the non-callee saved registers...
437 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
438 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in {
439 def CALLpcrel32 : I<0xE8, RawFrm, (ops i32imm:$dst, variable_ops),
440 "call ${dst:call}", []>;
441 def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
442 "call {*}$dst", [(X86call GR32:$dst)]>;
443 def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst, variable_ops),
448 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
449 def TAILJMPd : IBr<0xE9, (ops i32imm:$dst), "jmp ${dst:call} # TAIL CALL", []>;
450 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
451 def TAILJMPr : I<0xFF, MRM4r, (ops GR32:$dst), "jmp {*}$dst # TAIL CALL", []>;
452 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
453 def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst),
454 "jmp {*}$dst # TAIL CALL", []>;
456 // ADJSTACKPTRri - This is a standard ADD32ri instruction, identical in every
457 // way, except that it is marked as being a terminator. This causes the epilog
458 // inserter to insert reloads of callee saved registers BEFORE this. We need
459 // this until we have a more accurate way of tracking where the stack pointer is
460 // within a function.
461 let isTerminator = 1, isTwoAddress = 1 in
462 def ADJSTACKPTRri : Ii32<0x81, MRM0r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
463 "add{l} {$src2, $dst|$dst, $src2}", []>;
465 //===----------------------------------------------------------------------===//
466 // Miscellaneous Instructions...
468 def LEAVE : I<0xC9, RawFrm,
469 (ops), "leave", []>, Imp<[EBP,ESP],[EBP,ESP]>;
470 def POP32r : I<0x58, AddRegFrm,
471 (ops GR32:$reg), "pop{l} $reg", []>, Imp<[ESP],[ESP]>;
473 def MovePCtoStack : I<0, Pseudo, (ops piclabel:$label),
476 let isTwoAddress = 1 in // GR32 = bswap GR32
477 def BSWAP32r : I<0xC8, AddRegFrm,
478 (ops GR32:$dst, GR32:$src),
480 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
482 def XCHG8rr : I<0x86, MRMDestReg, // xchg GR8, GR8
483 (ops GR8:$src1, GR8:$src2),
484 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
485 def XCHG16rr : I<0x87, MRMDestReg, // xchg GR16, GR16
486 (ops GR16:$src1, GR16:$src2),
487 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
488 def XCHG32rr : I<0x87, MRMDestReg, // xchg GR32, GR32
489 (ops GR32:$src1, GR32:$src2),
490 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
492 def XCHG8mr : I<0x86, MRMDestMem,
493 (ops i8mem:$src1, GR8:$src2),
494 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
495 def XCHG16mr : I<0x87, MRMDestMem,
496 (ops i16mem:$src1, GR16:$src2),
497 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
498 def XCHG32mr : I<0x87, MRMDestMem,
499 (ops i32mem:$src1, GR32:$src2),
500 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
501 def XCHG8rm : I<0x86, MRMSrcMem,
502 (ops GR8:$src1, i8mem:$src2),
503 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
504 def XCHG16rm : I<0x87, MRMSrcMem,
505 (ops GR16:$src1, i16mem:$src2),
506 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
507 def XCHG32rm : I<0x87, MRMSrcMem,
508 (ops GR32:$src1, i32mem:$src2),
509 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
511 def LEA16r : I<0x8D, MRMSrcMem,
512 (ops GR16:$dst, i32mem:$src),
513 "lea{w} {$src|$dst}, {$dst|$src}", []>, OpSize;
514 def LEA32r : I<0x8D, MRMSrcMem,
515 (ops GR32:$dst, i32mem:$src),
516 "lea{l} {$src|$dst}, {$dst|$src}",
517 [(set GR32:$dst, leaaddr:$src)]>;
519 def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}",
521 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
522 def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}",
523 [(X86rep_movs i16)]>,
524 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize;
525 def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsl|rep movsd}",
526 [(X86rep_movs i32)]>,
527 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
529 def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}",
531 Imp<[AL,ECX,EDI], [ECX,EDI]>, REP;
532 def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}",
533 [(X86rep_stos i16)]>,
534 Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize;
535 def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}",
536 [(X86rep_stos i32)]>,
537 Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP;
540 //===----------------------------------------------------------------------===//
541 // Input/Output Instructions...
543 def IN8rr : I<0xEC, RawFrm, (ops),
544 "in{b} {%dx, %al|%AL, %DX}",
545 []>, Imp<[DX], [AL]>;
546 def IN16rr : I<0xED, RawFrm, (ops),
547 "in{w} {%dx, %ax|%AX, %DX}",
548 []>, Imp<[DX], [AX]>, OpSize;
549 def IN32rr : I<0xED, RawFrm, (ops),
550 "in{l} {%dx, %eax|%EAX, %DX}",
551 []>, Imp<[DX],[EAX]>;
553 def IN8ri : Ii8<0xE4, RawFrm, (ops i16i8imm:$port),
554 "in{b} {$port, %al|%AL, $port}",
557 def IN16ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port),
558 "in{w} {$port, %ax|%AX, $port}",
560 Imp<[], [AX]>, OpSize;
561 def IN32ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port),
562 "in{l} {$port, %eax|%EAX, $port}",
566 def OUT8rr : I<0xEE, RawFrm, (ops),
567 "out{b} {%al, %dx|%DX, %AL}",
568 []>, Imp<[DX, AL], []>;
569 def OUT16rr : I<0xEF, RawFrm, (ops),
570 "out{w} {%ax, %dx|%DX, %AX}",
571 []>, Imp<[DX, AX], []>, OpSize;
572 def OUT32rr : I<0xEF, RawFrm, (ops),
573 "out{l} {%eax, %dx|%DX, %EAX}",
574 []>, Imp<[DX, EAX], []>;
576 def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port),
577 "out{b} {%al, $port|$port, %AL}",
580 def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
581 "out{w} {%ax, $port|$port, %AX}",
583 Imp<[AX], []>, OpSize;
584 def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
585 "out{l} {%eax, $port|$port, %EAX}",
589 //===----------------------------------------------------------------------===//
590 // Move Instructions...
592 def MOV8rr : I<0x88, MRMDestReg, (ops GR8 :$dst, GR8 :$src),
593 "mov{b} {$src, $dst|$dst, $src}", []>;
594 def MOV16rr : I<0x89, MRMDestReg, (ops GR16:$dst, GR16:$src),
595 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
596 def MOV32rr : I<0x89, MRMDestReg, (ops GR32:$dst, GR32:$src),
597 "mov{l} {$src, $dst|$dst, $src}", []>;
598 def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops GR8 :$dst, i8imm :$src),
599 "mov{b} {$src, $dst|$dst, $src}",
600 [(set GR8:$dst, imm:$src)]>;
601 def MOV16ri : Ii16<0xB8, AddRegFrm, (ops GR16:$dst, i16imm:$src),
602 "mov{w} {$src, $dst|$dst, $src}",
603 [(set GR16:$dst, imm:$src)]>, OpSize;
604 def MOV32ri : Ii32<0xB8, AddRegFrm, (ops GR32:$dst, i32imm:$src),
605 "mov{l} {$src, $dst|$dst, $src}",
606 [(set GR32:$dst, imm:$src)]>;
607 def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src),
608 "mov{b} {$src, $dst|$dst, $src}",
609 [(store (i8 imm:$src), addr:$dst)]>;
610 def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src),
611 "mov{w} {$src, $dst|$dst, $src}",
612 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
613 def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src),
614 "mov{l} {$src, $dst|$dst, $src}",
615 [(store (i32 imm:$src), addr:$dst)]>;
617 def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src),
618 "mov{b} {$src, $dst|$dst, $src}",
619 [(set GR8:$dst, (load addr:$src))]>;
620 def MOV16rm : I<0x8B, MRMSrcMem, (ops GR16:$dst, i16mem:$src),
621 "mov{w} {$src, $dst|$dst, $src}",
622 [(set GR16:$dst, (load addr:$src))]>, OpSize;
623 def MOV32rm : I<0x8B, MRMSrcMem, (ops GR32:$dst, i32mem:$src),
624 "mov{l} {$src, $dst|$dst, $src}",
625 [(set GR32:$dst, (load addr:$src))]>;
627 def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, GR8 :$src),
628 "mov{b} {$src, $dst|$dst, $src}",
629 [(store GR8:$src, addr:$dst)]>;
630 def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, GR16:$src),
631 "mov{w} {$src, $dst|$dst, $src}",
632 [(store GR16:$src, addr:$dst)]>, OpSize;
633 def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, GR32:$src),
634 "mov{l} {$src, $dst|$dst, $src}",
635 [(store GR32:$src, addr:$dst)]>;
637 //===----------------------------------------------------------------------===//
638 // Fixed-Register Multiplication and Division Instructions...
641 // Extra precision multiplication
642 def MUL8r : I<0xF6, MRM4r, (ops GR8:$src), "mul{b} $src",
643 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
644 // This probably ought to be moved to a def : Pat<> if the
645 // syntax can be accepted.
646 [(set AL, (mul AL, GR8:$src))]>,
647 Imp<[AL],[AX]>; // AL,AH = AL*GR8
648 def MUL16r : I<0xF7, MRM4r, (ops GR16:$src), "mul{w} $src", []>,
649 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16
650 def MUL32r : I<0xF7, MRM4r, (ops GR32:$src), "mul{l} $src", []>,
651 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32
652 def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src),
654 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
655 // This probably ought to be moved to a def : Pat<> if the
656 // syntax can be accepted.
657 [(set AL, (mul AL, (loadi8 addr:$src)))]>,
658 Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
659 def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src),
660 "mul{w} $src", []>, Imp<[AX],[AX,DX]>,
661 OpSize; // AX,DX = AX*[mem16]
662 def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src),
663 "mul{l} $src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32]
665 def IMUL8r : I<0xF6, MRM5r, (ops GR8:$src), "imul{b} $src", []>,
666 Imp<[AL],[AX]>; // AL,AH = AL*GR8
667 def IMUL16r : I<0xF7, MRM5r, (ops GR16:$src), "imul{w} $src", []>,
668 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16
669 def IMUL32r : I<0xF7, MRM5r, (ops GR32:$src), "imul{l} $src", []>,
670 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32
671 def IMUL8m : I<0xF6, MRM5m, (ops i8mem :$src),
672 "imul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
673 def IMUL16m : I<0xF7, MRM5m, (ops i16mem:$src),
674 "imul{w} $src", []>, Imp<[AX],[AX,DX]>,
675 OpSize; // AX,DX = AX*[mem16]
676 def IMUL32m : I<0xF7, MRM5m, (ops i32mem:$src),
678 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
680 // unsigned division/remainder
681 def DIV8r : I<0xF6, MRM6r, (ops GR8:$src), // AX/r8 = AL,AH
682 "div{b} $src", []>, Imp<[AX],[AX]>;
683 def DIV16r : I<0xF7, MRM6r, (ops GR16:$src), // DX:AX/r16 = AX,DX
684 "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
685 def DIV32r : I<0xF7, MRM6r, (ops GR32:$src), // EDX:EAX/r32 = EAX,EDX
686 "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
687 def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), // AX/[mem8] = AL,AH
688 "div{b} $src", []>, Imp<[AX],[AX]>;
689 def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX
690 "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
691 def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
692 "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
694 // Signed division/remainder.
695 def IDIV8r : I<0xF6, MRM7r, (ops GR8:$src), // AX/r8 = AL,AH
696 "idiv{b} $src", []>, Imp<[AX],[AX]>;
697 def IDIV16r: I<0xF7, MRM7r, (ops GR16:$src), // DX:AX/r16 = AX,DX
698 "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
699 def IDIV32r: I<0xF7, MRM7r, (ops GR32:$src), // EDX:EAX/r32 = EAX,EDX
700 "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
701 def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), // AX/[mem8] = AL,AH
702 "idiv{b} $src", []>, Imp<[AX],[AX]>;
703 def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX
704 "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
705 def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
706 "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
709 //===----------------------------------------------------------------------===//
710 // Two address Instructions...
712 let isTwoAddress = 1 in {
715 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
716 (ops GR16:$dst, GR16:$src1, GR16:$src2),
717 "cmovb {$src2, $dst|$dst, $src2}",
718 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
721 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
722 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
723 "cmovb {$src2, $dst|$dst, $src2}",
724 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
727 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
728 (ops GR32:$dst, GR32:$src1, GR32:$src2),
729 "cmovb {$src2, $dst|$dst, $src2}",
730 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
733 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
734 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
735 "cmovb {$src2, $dst|$dst, $src2}",
736 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
740 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
741 (ops GR16:$dst, GR16:$src1, GR16:$src2),
742 "cmovae {$src2, $dst|$dst, $src2}",
743 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
746 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
747 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
748 "cmovae {$src2, $dst|$dst, $src2}",
749 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
752 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
753 (ops GR32:$dst, GR32:$src1, GR32:$src2),
754 "cmovae {$src2, $dst|$dst, $src2}",
755 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
758 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
759 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
760 "cmovae {$src2, $dst|$dst, $src2}",
761 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
765 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
766 (ops GR16:$dst, GR16:$src1, GR16:$src2),
767 "cmove {$src2, $dst|$dst, $src2}",
768 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
771 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
772 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
773 "cmove {$src2, $dst|$dst, $src2}",
774 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
777 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
778 (ops GR32:$dst, GR32:$src1, GR32:$src2),
779 "cmove {$src2, $dst|$dst, $src2}",
780 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
783 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
784 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
785 "cmove {$src2, $dst|$dst, $src2}",
786 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
790 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
791 (ops GR16:$dst, GR16:$src1, GR16:$src2),
792 "cmovne {$src2, $dst|$dst, $src2}",
793 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
796 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
797 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
798 "cmovne {$src2, $dst|$dst, $src2}",
799 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
802 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
803 (ops GR32:$dst, GR32:$src1, GR32:$src2),
804 "cmovne {$src2, $dst|$dst, $src2}",
805 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
808 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
809 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
810 "cmovne {$src2, $dst|$dst, $src2}",
811 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
815 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
816 (ops GR16:$dst, GR16:$src1, GR16:$src2),
817 "cmovbe {$src2, $dst|$dst, $src2}",
818 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
821 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
822 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
823 "cmovbe {$src2, $dst|$dst, $src2}",
824 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
827 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
828 (ops GR32:$dst, GR32:$src1, GR32:$src2),
829 "cmovbe {$src2, $dst|$dst, $src2}",
830 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
833 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
834 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
835 "cmovbe {$src2, $dst|$dst, $src2}",
836 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
840 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
841 (ops GR16:$dst, GR16:$src1, GR16:$src2),
842 "cmova {$src2, $dst|$dst, $src2}",
843 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
846 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
847 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
848 "cmova {$src2, $dst|$dst, $src2}",
849 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
852 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
853 (ops GR32:$dst, GR32:$src1, GR32:$src2),
854 "cmova {$src2, $dst|$dst, $src2}",
855 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
858 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
859 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
860 "cmova {$src2, $dst|$dst, $src2}",
861 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
865 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
866 (ops GR16:$dst, GR16:$src1, GR16:$src2),
867 "cmovl {$src2, $dst|$dst, $src2}",
868 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
871 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
872 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
873 "cmovl {$src2, $dst|$dst, $src2}",
874 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
877 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
878 (ops GR32:$dst, GR32:$src1, GR32:$src2),
879 "cmovl {$src2, $dst|$dst, $src2}",
880 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
883 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
884 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
885 "cmovl {$src2, $dst|$dst, $src2}",
886 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
890 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
891 (ops GR16:$dst, GR16:$src1, GR16:$src2),
892 "cmovge {$src2, $dst|$dst, $src2}",
893 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
896 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
897 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
898 "cmovge {$src2, $dst|$dst, $src2}",
899 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
902 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
903 (ops GR32:$dst, GR32:$src1, GR32:$src2),
904 "cmovge {$src2, $dst|$dst, $src2}",
905 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
908 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
909 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
910 "cmovge {$src2, $dst|$dst, $src2}",
911 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
915 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
916 (ops GR16:$dst, GR16:$src1, GR16:$src2),
917 "cmovle {$src2, $dst|$dst, $src2}",
918 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
921 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
922 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
923 "cmovle {$src2, $dst|$dst, $src2}",
924 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
927 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
928 (ops GR32:$dst, GR32:$src1, GR32:$src2),
929 "cmovle {$src2, $dst|$dst, $src2}",
930 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
933 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
934 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
935 "cmovle {$src2, $dst|$dst, $src2}",
936 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
940 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
941 (ops GR16:$dst, GR16:$src1, GR16:$src2),
942 "cmovg {$src2, $dst|$dst, $src2}",
943 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
946 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
947 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
948 "cmovg {$src2, $dst|$dst, $src2}",
949 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
952 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
953 (ops GR32:$dst, GR32:$src1, GR32:$src2),
954 "cmovg {$src2, $dst|$dst, $src2}",
955 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
958 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
959 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
960 "cmovg {$src2, $dst|$dst, $src2}",
961 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
965 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
966 (ops GR16:$dst, GR16:$src1, GR16:$src2),
967 "cmovs {$src2, $dst|$dst, $src2}",
968 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
971 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
972 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
973 "cmovs {$src2, $dst|$dst, $src2}",
974 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
977 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
978 (ops GR32:$dst, GR32:$src1, GR32:$src2),
979 "cmovs {$src2, $dst|$dst, $src2}",
980 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
983 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
984 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
985 "cmovs {$src2, $dst|$dst, $src2}",
986 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
990 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
991 (ops GR16:$dst, GR16:$src1, GR16:$src2),
992 "cmovns {$src2, $dst|$dst, $src2}",
993 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
996 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
997 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
998 "cmovns {$src2, $dst|$dst, $src2}",
999 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1002 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1003 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1004 "cmovns {$src2, $dst|$dst, $src2}",
1005 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1008 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1009 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1010 "cmovns {$src2, $dst|$dst, $src2}",
1011 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1015 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1016 (ops GR16:$dst, GR16:$src1, GR16:$src2),
1017 "cmovp {$src2, $dst|$dst, $src2}",
1018 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1021 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1022 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1023 "cmovp {$src2, $dst|$dst, $src2}",
1024 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1027 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1028 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1029 "cmovp {$src2, $dst|$dst, $src2}",
1030 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1033 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1034 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1035 "cmovp {$src2, $dst|$dst, $src2}",
1036 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1040 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1041 (ops GR16:$dst, GR16:$src1, GR16:$src2),
1042 "cmovnp {$src2, $dst|$dst, $src2}",
1043 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1046 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1047 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1048 "cmovnp {$src2, $dst|$dst, $src2}",
1049 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1052 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1053 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1054 "cmovnp {$src2, $dst|$dst, $src2}",
1055 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1058 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1059 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1060 "cmovnp {$src2, $dst|$dst, $src2}",
1061 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1066 // unary instructions
1067 let CodeSize = 2 in {
1068 def NEG8r : I<0xF6, MRM3r, (ops GR8 :$dst, GR8 :$src), "neg{b} $dst",
1069 [(set GR8:$dst, (ineg GR8:$src))]>;
1070 def NEG16r : I<0xF7, MRM3r, (ops GR16:$dst, GR16:$src), "neg{w} $dst",
1071 [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
1072 def NEG32r : I<0xF7, MRM3r, (ops GR32:$dst, GR32:$src), "neg{l} $dst",
1073 [(set GR32:$dst, (ineg GR32:$src))]>;
1074 let isTwoAddress = 0 in {
1075 def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst",
1076 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
1077 def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst",
1078 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1079 def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst",
1080 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
1084 def NOT8r : I<0xF6, MRM2r, (ops GR8 :$dst, GR8 :$src), "not{b} $dst",
1085 [(set GR8:$dst, (not GR8:$src))]>;
1086 def NOT16r : I<0xF7, MRM2r, (ops GR16:$dst, GR16:$src), "not{w} $dst",
1087 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1088 def NOT32r : I<0xF7, MRM2r, (ops GR32:$dst, GR32:$src), "not{l} $dst",
1089 [(set GR32:$dst, (not GR32:$src))]>;
1090 let isTwoAddress = 0 in {
1091 def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst",
1092 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1093 def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst",
1094 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1095 def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst",
1096 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1100 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1102 def INC8r : I<0xFE, MRM0r, (ops GR8 :$dst, GR8 :$src), "inc{b} $dst",
1103 [(set GR8:$dst, (add GR8:$src, 1))]>;
1104 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1105 def INC16r : I<0x40, AddRegFrm, (ops GR16:$dst, GR16:$src), "inc{w} $dst",
1106 [(set GR16:$dst, (add GR16:$src, 1))]>, OpSize;
1107 def INC32r : I<0x40, AddRegFrm, (ops GR32:$dst, GR32:$src), "inc{l} $dst",
1108 [(set GR32:$dst, (add GR32:$src, 1))]>;
1110 let isTwoAddress = 0, CodeSize = 2 in {
1111 def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst",
1112 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1113 def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst",
1114 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>, OpSize;
1115 def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst",
1116 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>;
1120 def DEC8r : I<0xFE, MRM1r, (ops GR8 :$dst, GR8 :$src), "dec{b} $dst",
1121 [(set GR8:$dst, (add GR8:$src, -1))]>;
1122 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1123 def DEC16r : I<0x48, AddRegFrm, (ops GR16:$dst, GR16:$src), "dec{w} $dst",
1124 [(set GR16:$dst, (add GR16:$src, -1))]>, OpSize;
1125 def DEC32r : I<0x48, AddRegFrm, (ops GR32:$dst, GR32:$src), "dec{l} $dst",
1126 [(set GR32:$dst, (add GR32:$src, -1))]>;
1129 let isTwoAddress = 0, CodeSize = 2 in {
1130 def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst",
1131 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1132 def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst",
1133 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>, OpSize;
1134 def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst",
1135 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>;
1138 // Logical operators...
1139 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1140 def AND8rr : I<0x20, MRMDestReg,
1141 (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1142 "and{b} {$src2, $dst|$dst, $src2}",
1143 [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
1144 def AND16rr : I<0x21, MRMDestReg,
1145 (ops GR16:$dst, GR16:$src1, GR16:$src2),
1146 "and{w} {$src2, $dst|$dst, $src2}",
1147 [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
1148 def AND32rr : I<0x21, MRMDestReg,
1149 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1150 "and{l} {$src2, $dst|$dst, $src2}",
1151 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
1154 def AND8rm : I<0x22, MRMSrcMem,
1155 (ops GR8 :$dst, GR8 :$src1, i8mem :$src2),
1156 "and{b} {$src2, $dst|$dst, $src2}",
1157 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
1158 def AND16rm : I<0x23, MRMSrcMem,
1159 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1160 "and{w} {$src2, $dst|$dst, $src2}",
1161 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
1162 def AND32rm : I<0x23, MRMSrcMem,
1163 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1164 "and{l} {$src2, $dst|$dst, $src2}",
1165 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
1167 def AND8ri : Ii8<0x80, MRM4r,
1168 (ops GR8 :$dst, GR8 :$src1, i8imm :$src2),
1169 "and{b} {$src2, $dst|$dst, $src2}",
1170 [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
1171 def AND16ri : Ii16<0x81, MRM4r,
1172 (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1173 "and{w} {$src2, $dst|$dst, $src2}",
1174 [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
1175 def AND32ri : Ii32<0x81, MRM4r,
1176 (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1177 "and{l} {$src2, $dst|$dst, $src2}",
1178 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
1179 def AND16ri8 : Ii8<0x83, MRM4r,
1180 (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1181 "and{w} {$src2, $dst|$dst, $src2}",
1182 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
1184 def AND32ri8 : Ii8<0x83, MRM4r,
1185 (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1186 "and{l} {$src2, $dst|$dst, $src2}",
1187 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
1189 let isTwoAddress = 0 in {
1190 def AND8mr : I<0x20, MRMDestMem,
1191 (ops i8mem :$dst, GR8 :$src),
1192 "and{b} {$src, $dst|$dst, $src}",
1193 [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
1194 def AND16mr : I<0x21, MRMDestMem,
1195 (ops i16mem:$dst, GR16:$src),
1196 "and{w} {$src, $dst|$dst, $src}",
1197 [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
1199 def AND32mr : I<0x21, MRMDestMem,
1200 (ops i32mem:$dst, GR32:$src),
1201 "and{l} {$src, $dst|$dst, $src}",
1202 [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
1203 def AND8mi : Ii8<0x80, MRM4m,
1204 (ops i8mem :$dst, i8imm :$src),
1205 "and{b} {$src, $dst|$dst, $src}",
1206 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1207 def AND16mi : Ii16<0x81, MRM4m,
1208 (ops i16mem:$dst, i16imm:$src),
1209 "and{w} {$src, $dst|$dst, $src}",
1210 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1212 def AND32mi : Ii32<0x81, MRM4m,
1213 (ops i32mem:$dst, i32imm:$src),
1214 "and{l} {$src, $dst|$dst, $src}",
1215 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1216 def AND16mi8 : Ii8<0x83, MRM4m,
1217 (ops i16mem:$dst, i16i8imm :$src),
1218 "and{w} {$src, $dst|$dst, $src}",
1219 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1221 def AND32mi8 : Ii8<0x83, MRM4m,
1222 (ops i32mem:$dst, i32i8imm :$src),
1223 "and{l} {$src, $dst|$dst, $src}",
1224 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1228 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1229 def OR8rr : I<0x08, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1230 "or{b} {$src2, $dst|$dst, $src2}",
1231 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
1232 def OR16rr : I<0x09, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1233 "or{w} {$src2, $dst|$dst, $src2}",
1234 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
1235 def OR32rr : I<0x09, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1236 "or{l} {$src2, $dst|$dst, $src2}",
1237 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
1239 def OR8rm : I<0x0A, MRMSrcMem , (ops GR8 :$dst, GR8 :$src1, i8mem :$src2),
1240 "or{b} {$src2, $dst|$dst, $src2}",
1241 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
1242 def OR16rm : I<0x0B, MRMSrcMem , (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1243 "or{w} {$src2, $dst|$dst, $src2}",
1244 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
1245 def OR32rm : I<0x0B, MRMSrcMem , (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1246 "or{l} {$src2, $dst|$dst, $src2}",
1247 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
1249 def OR8ri : Ii8 <0x80, MRM1r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1250 "or{b} {$src2, $dst|$dst, $src2}",
1251 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
1252 def OR16ri : Ii16<0x81, MRM1r, (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1253 "or{w} {$src2, $dst|$dst, $src2}",
1254 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
1255 def OR32ri : Ii32<0x81, MRM1r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1256 "or{l} {$src2, $dst|$dst, $src2}",
1257 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
1259 def OR16ri8 : Ii8<0x83, MRM1r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1260 "or{w} {$src2, $dst|$dst, $src2}",
1261 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1262 def OR32ri8 : Ii8<0x83, MRM1r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1263 "or{l} {$src2, $dst|$dst, $src2}",
1264 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
1265 let isTwoAddress = 0 in {
1266 def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, GR8:$src),
1267 "or{b} {$src, $dst|$dst, $src}",
1268 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
1269 def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, GR16:$src),
1270 "or{w} {$src, $dst|$dst, $src}",
1271 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
1272 def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, GR32:$src),
1273 "or{l} {$src, $dst|$dst, $src}",
1274 [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
1275 def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src),
1276 "or{b} {$src, $dst|$dst, $src}",
1277 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1278 def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src),
1279 "or{w} {$src, $dst|$dst, $src}",
1280 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1282 def OR32mi : Ii32<0x81, MRM1m, (ops i32mem:$dst, i32imm:$src),
1283 "or{l} {$src, $dst|$dst, $src}",
1284 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1285 def OR16mi8 : Ii8<0x83, MRM1m, (ops i16mem:$dst, i16i8imm:$src),
1286 "or{w} {$src, $dst|$dst, $src}",
1287 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1289 def OR32mi8 : Ii8<0x83, MRM1m, (ops i32mem:$dst, i32i8imm:$src),
1290 "or{l} {$src, $dst|$dst, $src}",
1291 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1295 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1296 def XOR8rr : I<0x30, MRMDestReg,
1297 (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1298 "xor{b} {$src2, $dst|$dst, $src2}",
1299 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
1300 def XOR16rr : I<0x31, MRMDestReg,
1301 (ops GR16:$dst, GR16:$src1, GR16:$src2),
1302 "xor{w} {$src2, $dst|$dst, $src2}",
1303 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
1304 def XOR32rr : I<0x31, MRMDestReg,
1305 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1306 "xor{l} {$src2, $dst|$dst, $src2}",
1307 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
1310 def XOR8rm : I<0x32, MRMSrcMem ,
1311 (ops GR8 :$dst, GR8:$src1, i8mem :$src2),
1312 "xor{b} {$src2, $dst|$dst, $src2}",
1313 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
1314 def XOR16rm : I<0x33, MRMSrcMem ,
1315 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1316 "xor{w} {$src2, $dst|$dst, $src2}",
1317 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>, OpSize;
1318 def XOR32rm : I<0x33, MRMSrcMem ,
1319 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1320 "xor{l} {$src2, $dst|$dst, $src2}",
1321 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
1323 def XOR8ri : Ii8<0x80, MRM6r,
1324 (ops GR8:$dst, GR8:$src1, i8imm:$src2),
1325 "xor{b} {$src2, $dst|$dst, $src2}",
1326 [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
1327 def XOR16ri : Ii16<0x81, MRM6r,
1328 (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1329 "xor{w} {$src2, $dst|$dst, $src2}",
1330 [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
1331 def XOR32ri : Ii32<0x81, MRM6r,
1332 (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1333 "xor{l} {$src2, $dst|$dst, $src2}",
1334 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
1335 def XOR16ri8 : Ii8<0x83, MRM6r,
1336 (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1337 "xor{w} {$src2, $dst|$dst, $src2}",
1338 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
1340 def XOR32ri8 : Ii8<0x83, MRM6r,
1341 (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1342 "xor{l} {$src2, $dst|$dst, $src2}",
1343 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
1344 let isTwoAddress = 0 in {
1345 def XOR8mr : I<0x30, MRMDestMem,
1346 (ops i8mem :$dst, GR8 :$src),
1347 "xor{b} {$src, $dst|$dst, $src}",
1348 [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
1349 def XOR16mr : I<0x31, MRMDestMem,
1350 (ops i16mem:$dst, GR16:$src),
1351 "xor{w} {$src, $dst|$dst, $src}",
1352 [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
1354 def XOR32mr : I<0x31, MRMDestMem,
1355 (ops i32mem:$dst, GR32:$src),
1356 "xor{l} {$src, $dst|$dst, $src}",
1357 [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
1358 def XOR8mi : Ii8<0x80, MRM6m,
1359 (ops i8mem :$dst, i8imm :$src),
1360 "xor{b} {$src, $dst|$dst, $src}",
1361 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1362 def XOR16mi : Ii16<0x81, MRM6m,
1363 (ops i16mem:$dst, i16imm:$src),
1364 "xor{w} {$src, $dst|$dst, $src}",
1365 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1367 def XOR32mi : Ii32<0x81, MRM6m,
1368 (ops i32mem:$dst, i32imm:$src),
1369 "xor{l} {$src, $dst|$dst, $src}",
1370 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1371 def XOR16mi8 : Ii8<0x83, MRM6m,
1372 (ops i16mem:$dst, i16i8imm :$src),
1373 "xor{w} {$src, $dst|$dst, $src}",
1374 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1376 def XOR32mi8 : Ii8<0x83, MRM6m,
1377 (ops i32mem:$dst, i32i8imm :$src),
1378 "xor{l} {$src, $dst|$dst, $src}",
1379 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1382 // Shift instructions
1383 def SHL8rCL : I<0xD2, MRM4r, (ops GR8 :$dst, GR8 :$src),
1384 "shl{b} {%cl, $dst|$dst, %CL}",
1385 [(set GR8:$dst, (shl GR8:$src, CL))]>, Imp<[CL],[]>;
1386 def SHL16rCL : I<0xD3, MRM4r, (ops GR16:$dst, GR16:$src),
1387 "shl{w} {%cl, $dst|$dst, %CL}",
1388 [(set GR16:$dst, (shl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1389 def SHL32rCL : I<0xD3, MRM4r, (ops GR32:$dst, GR32:$src),
1390 "shl{l} {%cl, $dst|$dst, %CL}",
1391 [(set GR32:$dst, (shl GR32:$src, CL))]>, Imp<[CL],[]>;
1393 def SHL8ri : Ii8<0xC0, MRM4r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1394 "shl{b} {$src2, $dst|$dst, $src2}",
1395 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1396 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1397 def SHL16ri : Ii8<0xC1, MRM4r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1398 "shl{w} {$src2, $dst|$dst, $src2}",
1399 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1400 def SHL32ri : Ii8<0xC1, MRM4r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1401 "shl{l} {$src2, $dst|$dst, $src2}",
1402 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1405 // Shift left by one. Not used because (add x, x) is slightly cheaper.
1406 def SHL8r1 : I<0xD0, MRM4r, (ops GR8 :$dst, GR8 :$src1),
1408 def SHL16r1 : I<0xD1, MRM4r, (ops GR16:$dst, GR16:$src1),
1409 "shl{w} $dst", []>, OpSize;
1410 def SHL32r1 : I<0xD1, MRM4r, (ops GR32:$dst, GR32:$src1),
1413 let isTwoAddress = 0 in {
1414 def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst),
1415 "shl{b} {%cl, $dst|$dst, %CL}",
1416 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>,
1418 def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst),
1419 "shl{w} {%cl, $dst|$dst, %CL}",
1420 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>,
1421 Imp<[CL],[]>, OpSize;
1422 def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst),
1423 "shl{l} {%cl, $dst|$dst, %CL}",
1424 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>,
1426 def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src),
1427 "shl{b} {$src, $dst|$dst, $src}",
1428 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1429 def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src),
1430 "shl{w} {$src, $dst|$dst, $src}",
1431 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1433 def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src),
1434 "shl{l} {$src, $dst|$dst, $src}",
1435 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1438 def SHL8m1 : I<0xD0, MRM4m, (ops i8mem :$dst),
1440 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1441 def SHL16m1 : I<0xD1, MRM4m, (ops i16mem:$dst),
1443 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1445 def SHL32m1 : I<0xD1, MRM4m, (ops i32mem:$dst),
1447 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1450 def SHR8rCL : I<0xD2, MRM5r, (ops GR8 :$dst, GR8 :$src),
1451 "shr{b} {%cl, $dst|$dst, %CL}",
1452 [(set GR8:$dst, (srl GR8:$src, CL))]>, Imp<[CL],[]>;
1453 def SHR16rCL : I<0xD3, MRM5r, (ops GR16:$dst, GR16:$src),
1454 "shr{w} {%cl, $dst|$dst, %CL}",
1455 [(set GR16:$dst, (srl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1456 def SHR32rCL : I<0xD3, MRM5r, (ops GR32:$dst, GR32:$src),
1457 "shr{l} {%cl, $dst|$dst, %CL}",
1458 [(set GR32:$dst, (srl GR32:$src, CL))]>, Imp<[CL],[]>;
1460 def SHR8ri : Ii8<0xC0, MRM5r, (ops GR8:$dst, GR8:$src1, i8imm:$src2),
1461 "shr{b} {$src2, $dst|$dst, $src2}",
1462 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1463 def SHR16ri : Ii8<0xC1, MRM5r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1464 "shr{w} {$src2, $dst|$dst, $src2}",
1465 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1466 def SHR32ri : Ii8<0xC1, MRM5r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1467 "shr{l} {$src2, $dst|$dst, $src2}",
1468 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1471 def SHR8r1 : I<0xD0, MRM5r, (ops GR8:$dst, GR8:$src1),
1473 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1474 def SHR16r1 : I<0xD1, MRM5r, (ops GR16:$dst, GR16:$src1),
1476 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1477 def SHR32r1 : I<0xD1, MRM5r, (ops GR32:$dst, GR32:$src1),
1479 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1481 let isTwoAddress = 0 in {
1482 def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst),
1483 "shr{b} {%cl, $dst|$dst, %CL}",
1484 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>,
1486 def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst),
1487 "shr{w} {%cl, $dst|$dst, %CL}",
1488 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1489 Imp<[CL],[]>, OpSize;
1490 def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst),
1491 "shr{l} {%cl, $dst|$dst, %CL}",
1492 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>,
1494 def SHR8mi : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src),
1495 "shr{b} {$src, $dst|$dst, $src}",
1496 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1497 def SHR16mi : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src),
1498 "shr{w} {$src, $dst|$dst, $src}",
1499 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1501 def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src),
1502 "shr{l} {$src, $dst|$dst, $src}",
1503 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1506 def SHR8m1 : I<0xD0, MRM5m, (ops i8mem :$dst),
1508 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1509 def SHR16m1 : I<0xD1, MRM5m, (ops i16mem:$dst),
1511 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1512 def SHR32m1 : I<0xD1, MRM5m, (ops i32mem:$dst),
1514 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1517 def SAR8rCL : I<0xD2, MRM7r, (ops GR8 :$dst, GR8 :$src),
1518 "sar{b} {%cl, $dst|$dst, %CL}",
1519 [(set GR8:$dst, (sra GR8:$src, CL))]>, Imp<[CL],[]>;
1520 def SAR16rCL : I<0xD3, MRM7r, (ops GR16:$dst, GR16:$src),
1521 "sar{w} {%cl, $dst|$dst, %CL}",
1522 [(set GR16:$dst, (sra GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1523 def SAR32rCL : I<0xD3, MRM7r, (ops GR32:$dst, GR32:$src),
1524 "sar{l} {%cl, $dst|$dst, %CL}",
1525 [(set GR32:$dst, (sra GR32:$src, CL))]>, Imp<[CL],[]>;
1527 def SAR8ri : Ii8<0xC0, MRM7r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1528 "sar{b} {$src2, $dst|$dst, $src2}",
1529 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1530 def SAR16ri : Ii8<0xC1, MRM7r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1531 "sar{w} {$src2, $dst|$dst, $src2}",
1532 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1534 def SAR32ri : Ii8<0xC1, MRM7r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1535 "sar{l} {$src2, $dst|$dst, $src2}",
1536 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1539 def SAR8r1 : I<0xD0, MRM7r, (ops GR8 :$dst, GR8 :$src1),
1541 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1542 def SAR16r1 : I<0xD1, MRM7r, (ops GR16:$dst, GR16:$src1),
1544 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1545 def SAR32r1 : I<0xD1, MRM7r, (ops GR32:$dst, GR32:$src1),
1547 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1549 let isTwoAddress = 0 in {
1550 def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst),
1551 "sar{b} {%cl, $dst|$dst, %CL}",
1552 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>,
1554 def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst),
1555 "sar{w} {%cl, $dst|$dst, %CL}",
1556 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>,
1557 Imp<[CL],[]>, OpSize;
1558 def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst),
1559 "sar{l} {%cl, $dst|$dst, %CL}",
1560 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>,
1562 def SAR8mi : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src),
1563 "sar{b} {$src, $dst|$dst, $src}",
1564 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1565 def SAR16mi : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src),
1566 "sar{w} {$src, $dst|$dst, $src}",
1567 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1569 def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src),
1570 "sar{l} {$src, $dst|$dst, $src}",
1571 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1574 def SAR8m1 : I<0xD0, MRM7m, (ops i8mem :$dst),
1576 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1577 def SAR16m1 : I<0xD1, MRM7m, (ops i16mem:$dst),
1579 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1581 def SAR32m1 : I<0xD1, MRM7m, (ops i32mem:$dst),
1583 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1586 // Rotate instructions
1587 // FIXME: provide shorter instructions when imm8 == 1
1588 def ROL8rCL : I<0xD2, MRM0r, (ops GR8 :$dst, GR8 :$src),
1589 "rol{b} {%cl, $dst|$dst, %CL}",
1590 [(set GR8:$dst, (rotl GR8:$src, CL))]>, Imp<[CL],[]>;
1591 def ROL16rCL : I<0xD3, MRM0r, (ops GR16:$dst, GR16:$src),
1592 "rol{w} {%cl, $dst|$dst, %CL}",
1593 [(set GR16:$dst, (rotl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1594 def ROL32rCL : I<0xD3, MRM0r, (ops GR32:$dst, GR32:$src),
1595 "rol{l} {%cl, $dst|$dst, %CL}",
1596 [(set GR32:$dst, (rotl GR32:$src, CL))]>, Imp<[CL],[]>;
1598 def ROL8ri : Ii8<0xC0, MRM0r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1599 "rol{b} {$src2, $dst|$dst, $src2}",
1600 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1601 def ROL16ri : Ii8<0xC1, MRM0r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1602 "rol{w} {$src2, $dst|$dst, $src2}",
1603 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1604 def ROL32ri : Ii8<0xC1, MRM0r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1605 "rol{l} {$src2, $dst|$dst, $src2}",
1606 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1609 def ROL8r1 : I<0xD0, MRM0r, (ops GR8 :$dst, GR8 :$src1),
1611 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1612 def ROL16r1 : I<0xD1, MRM0r, (ops GR16:$dst, GR16:$src1),
1614 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1615 def ROL32r1 : I<0xD1, MRM0r, (ops GR32:$dst, GR32:$src1),
1617 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1619 let isTwoAddress = 0 in {
1620 def ROL8mCL : I<0xD2, MRM0m, (ops i8mem :$dst),
1621 "rol{b} {%cl, $dst|$dst, %CL}",
1622 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>,
1624 def ROL16mCL : I<0xD3, MRM0m, (ops i16mem:$dst),
1625 "rol{w} {%cl, $dst|$dst, %CL}",
1626 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>,
1627 Imp<[CL],[]>, OpSize;
1628 def ROL32mCL : I<0xD3, MRM0m, (ops i32mem:$dst),
1629 "rol{l} {%cl, $dst|$dst, %CL}",
1630 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>,
1632 def ROL8mi : Ii8<0xC0, MRM0m, (ops i8mem :$dst, i8imm:$src),
1633 "rol{b} {$src, $dst|$dst, $src}",
1634 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1635 def ROL16mi : Ii8<0xC1, MRM0m, (ops i16mem:$dst, i8imm:$src),
1636 "rol{w} {$src, $dst|$dst, $src}",
1637 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1639 def ROL32mi : Ii8<0xC1, MRM0m, (ops i32mem:$dst, i8imm:$src),
1640 "rol{l} {$src, $dst|$dst, $src}",
1641 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1644 def ROL8m1 : I<0xD0, MRM0m, (ops i8mem :$dst),
1646 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1647 def ROL16m1 : I<0xD1, MRM0m, (ops i16mem:$dst),
1649 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1651 def ROL32m1 : I<0xD1, MRM0m, (ops i32mem:$dst),
1653 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1656 def ROR8rCL : I<0xD2, MRM1r, (ops GR8 :$dst, GR8 :$src),
1657 "ror{b} {%cl, $dst|$dst, %CL}",
1658 [(set GR8:$dst, (rotr GR8:$src, CL))]>, Imp<[CL],[]>;
1659 def ROR16rCL : I<0xD3, MRM1r, (ops GR16:$dst, GR16:$src),
1660 "ror{w} {%cl, $dst|$dst, %CL}",
1661 [(set GR16:$dst, (rotr GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1662 def ROR32rCL : I<0xD3, MRM1r, (ops GR32:$dst, GR32:$src),
1663 "ror{l} {%cl, $dst|$dst, %CL}",
1664 [(set GR32:$dst, (rotr GR32:$src, CL))]>, Imp<[CL],[]>;
1666 def ROR8ri : Ii8<0xC0, MRM1r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1667 "ror{b} {$src2, $dst|$dst, $src2}",
1668 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
1669 def ROR16ri : Ii8<0xC1, MRM1r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1670 "ror{w} {$src2, $dst|$dst, $src2}",
1671 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1672 def ROR32ri : Ii8<0xC1, MRM1r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1673 "ror{l} {$src2, $dst|$dst, $src2}",
1674 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
1677 def ROR8r1 : I<0xD0, MRM1r, (ops GR8 :$dst, GR8 :$src1),
1679 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
1680 def ROR16r1 : I<0xD1, MRM1r, (ops GR16:$dst, GR16:$src1),
1682 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
1683 def ROR32r1 : I<0xD1, MRM1r, (ops GR32:$dst, GR32:$src1),
1685 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
1687 let isTwoAddress = 0 in {
1688 def ROR8mCL : I<0xD2, MRM1m, (ops i8mem :$dst),
1689 "ror{b} {%cl, $dst|$dst, %CL}",
1690 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>,
1692 def ROR16mCL : I<0xD3, MRM1m, (ops i16mem:$dst),
1693 "ror{w} {%cl, $dst|$dst, %CL}",
1694 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>,
1695 Imp<[CL],[]>, OpSize;
1696 def ROR32mCL : I<0xD3, MRM1m, (ops i32mem:$dst),
1697 "ror{l} {%cl, $dst|$dst, %CL}",
1698 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>,
1700 def ROR8mi : Ii8<0xC0, MRM1m, (ops i8mem :$dst, i8imm:$src),
1701 "ror{b} {$src, $dst|$dst, $src}",
1702 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1703 def ROR16mi : Ii8<0xC1, MRM1m, (ops i16mem:$dst, i8imm:$src),
1704 "ror{w} {$src, $dst|$dst, $src}",
1705 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1707 def ROR32mi : Ii8<0xC1, MRM1m, (ops i32mem:$dst, i8imm:$src),
1708 "ror{l} {$src, $dst|$dst, $src}",
1709 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1712 def ROR8m1 : I<0xD0, MRM1m, (ops i8mem :$dst),
1714 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1715 def ROR16m1 : I<0xD1, MRM1m, (ops i16mem:$dst),
1717 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1719 def ROR32m1 : I<0xD1, MRM1m, (ops i32mem:$dst),
1721 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1726 // Double shift instructions (generalizations of rotate)
1727 def SHLD32rrCL : I<0xA5, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1728 "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1729 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>,
1731 def SHRD32rrCL : I<0xAD, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1732 "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1733 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>,
1735 def SHLD16rrCL : I<0xA5, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1736 "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1737 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
1738 Imp<[CL],[]>, TB, OpSize;
1739 def SHRD16rrCL : I<0xAD, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1740 "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1741 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
1742 Imp<[CL],[]>, TB, OpSize;
1744 let isCommutable = 1 in { // These instructions commute to each other.
1745 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
1746 (ops GR32:$dst, GR32:$src1, GR32:$src2, i8imm:$src3),
1747 "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1748 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
1751 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
1752 (ops GR32:$dst, GR32:$src1, GR32:$src2, i8imm:$src3),
1753 "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1754 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
1757 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
1758 (ops GR16:$dst, GR16:$src1, GR16:$src2, i8imm:$src3),
1759 "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1760 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
1763 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1764 (ops GR16:$dst, GR16:$src1, GR16:$src2, i8imm:$src3),
1765 "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1766 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
1771 let isTwoAddress = 0 in {
1772 def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1773 "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1774 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
1777 def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1778 "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1779 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
1782 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1783 (ops i32mem:$dst, GR32:$src2, i8imm:$src3),
1784 "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1785 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
1786 (i8 imm:$src3)), addr:$dst)]>,
1788 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1789 (ops i32mem:$dst, GR32:$src2, i8imm:$src3),
1790 "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1791 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
1792 (i8 imm:$src3)), addr:$dst)]>,
1795 def SHLD16mrCL : I<0xA5, MRMDestMem, (ops i16mem:$dst, GR16:$src2),
1796 "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1797 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
1799 Imp<[CL],[]>, TB, OpSize;
1800 def SHRD16mrCL : I<0xAD, MRMDestMem, (ops i16mem:$dst, GR16:$src2),
1801 "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1802 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
1804 Imp<[CL],[]>, TB, OpSize;
1805 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1806 (ops i16mem:$dst, GR16:$src2, i8imm:$src3),
1807 "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1808 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
1809 (i8 imm:$src3)), addr:$dst)]>,
1811 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1812 (ops i16mem:$dst, GR16:$src2, i8imm:$src3),
1813 "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1814 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
1815 (i8 imm:$src3)), addr:$dst)]>,
1821 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1822 def ADD8rr : I<0x00, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1823 "add{b} {$src2, $dst|$dst, $src2}",
1824 [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>;
1825 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1826 def ADD16rr : I<0x01, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1827 "add{w} {$src2, $dst|$dst, $src2}",
1828 [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize;
1829 def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1830 "add{l} {$src2, $dst|$dst, $src2}",
1831 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
1832 } // end isConvertibleToThreeAddress
1833 } // end isCommutable
1834 def ADD8rm : I<0x02, MRMSrcMem, (ops GR8 :$dst, GR8 :$src1, i8mem :$src2),
1835 "add{b} {$src2, $dst|$dst, $src2}",
1836 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>;
1837 def ADD16rm : I<0x03, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1838 "add{w} {$src2, $dst|$dst, $src2}",
1839 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>, OpSize;
1840 def ADD32rm : I<0x03, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1841 "add{l} {$src2, $dst|$dst, $src2}",
1842 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>;
1844 def ADD8ri : Ii8<0x80, MRM0r, (ops GR8:$dst, GR8:$src1, i8imm:$src2),
1845 "add{b} {$src2, $dst|$dst, $src2}",
1846 [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>;
1848 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1849 def ADD16ri : Ii16<0x81, MRM0r, (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1850 "add{w} {$src2, $dst|$dst, $src2}",
1851 [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize;
1852 def ADD32ri : Ii32<0x81, MRM0r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1853 "add{l} {$src2, $dst|$dst, $src2}",
1854 [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>;
1855 def ADD16ri8 : Ii8<0x83, MRM0r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1856 "add{w} {$src2, $dst|$dst, $src2}",
1857 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>,
1859 def ADD32ri8 : Ii8<0x83, MRM0r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1860 "add{l} {$src2, $dst|$dst, $src2}",
1861 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>;
1864 let isTwoAddress = 0 in {
1865 def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, GR8 :$src2),
1866 "add{b} {$src2, $dst|$dst, $src2}",
1867 [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>;
1868 def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, GR16:$src2),
1869 "add{w} {$src2, $dst|$dst, $src2}",
1870 [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>,
1872 def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1873 "add{l} {$src2, $dst|$dst, $src2}",
1874 [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>;
1875 def ADD8mi : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2),
1876 "add{b} {$src2, $dst|$dst, $src2}",
1877 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1878 def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2),
1879 "add{w} {$src2, $dst|$dst, $src2}",
1880 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1882 def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2),
1883 "add{l} {$src2, $dst|$dst, $src2}",
1884 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1885 def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i16i8imm :$src2),
1886 "add{w} {$src2, $dst|$dst, $src2}",
1887 [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1889 def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i32i8imm :$src2),
1890 "add{l} {$src2, $dst|$dst, $src2}",
1891 [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1894 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1895 def ADC32rr : I<0x11, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1896 "adc{l} {$src2, $dst|$dst, $src2}",
1897 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
1899 def ADC32rm : I<0x13, MRMSrcMem , (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1900 "adc{l} {$src2, $dst|$dst, $src2}",
1901 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
1902 def ADC32ri : Ii32<0x81, MRM2r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1903 "adc{l} {$src2, $dst|$dst, $src2}",
1904 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
1905 def ADC32ri8 : Ii8<0x83, MRM2r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1906 "adc{l} {$src2, $dst|$dst, $src2}",
1907 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
1909 let isTwoAddress = 0 in {
1910 def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1911 "adc{l} {$src2, $dst|$dst, $src2}",
1912 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
1913 def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2),
1914 "adc{l} {$src2, $dst|$dst, $src2}",
1915 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1916 def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i32i8imm :$src2),
1917 "adc{l} {$src2, $dst|$dst, $src2}",
1918 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1921 def SUB8rr : I<0x28, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1922 "sub{b} {$src2, $dst|$dst, $src2}",
1923 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>;
1924 def SUB16rr : I<0x29, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1925 "sub{w} {$src2, $dst|$dst, $src2}",
1926 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize;
1927 def SUB32rr : I<0x29, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1928 "sub{l} {$src2, $dst|$dst, $src2}",
1929 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
1930 def SUB8rm : I<0x2A, MRMSrcMem, (ops GR8 :$dst, GR8 :$src1, i8mem :$src2),
1931 "sub{b} {$src2, $dst|$dst, $src2}",
1932 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>;
1933 def SUB16rm : I<0x2B, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1934 "sub{w} {$src2, $dst|$dst, $src2}",
1935 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize;
1936 def SUB32rm : I<0x2B, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1937 "sub{l} {$src2, $dst|$dst, $src2}",
1938 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>;
1940 def SUB8ri : Ii8 <0x80, MRM5r, (ops GR8:$dst, GR8:$src1, i8imm:$src2),
1941 "sub{b} {$src2, $dst|$dst, $src2}",
1942 [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>;
1943 def SUB16ri : Ii16<0x81, MRM5r, (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1944 "sub{w} {$src2, $dst|$dst, $src2}",
1945 [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize;
1946 def SUB32ri : Ii32<0x81, MRM5r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1947 "sub{l} {$src2, $dst|$dst, $src2}",
1948 [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>;
1949 def SUB16ri8 : Ii8<0x83, MRM5r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1950 "sub{w} {$src2, $dst|$dst, $src2}",
1951 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>,
1953 def SUB32ri8 : Ii8<0x83, MRM5r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1954 "sub{l} {$src2, $dst|$dst, $src2}",
1955 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>;
1956 let isTwoAddress = 0 in {
1957 def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, GR8 :$src2),
1958 "sub{b} {$src2, $dst|$dst, $src2}",
1959 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>;
1960 def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, GR16:$src2),
1961 "sub{w} {$src2, $dst|$dst, $src2}",
1962 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>,
1964 def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1965 "sub{l} {$src2, $dst|$dst, $src2}",
1966 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>;
1967 def SUB8mi : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2),
1968 "sub{b} {$src2, $dst|$dst, $src2}",
1969 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1970 def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2),
1971 "sub{w} {$src2, $dst|$dst, $src2}",
1972 [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1974 def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2),
1975 "sub{l} {$src2, $dst|$dst, $src2}",
1976 [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1977 def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i16i8imm :$src2),
1978 "sub{w} {$src2, $dst|$dst, $src2}",
1979 [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1981 def SUB32mi8 : Ii8<0x83, MRM5m, (ops i32mem:$dst, i32i8imm :$src2),
1982 "sub{l} {$src2, $dst|$dst, $src2}",
1983 [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1986 def SBB32rr : I<0x19, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1987 "sbb{l} {$src2, $dst|$dst, $src2}",
1988 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
1990 let isTwoAddress = 0 in {
1991 def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1992 "sbb{l} {$src2, $dst|$dst, $src2}",
1993 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
1994 def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2),
1995 "sbb{b} {$src2, $dst|$dst, $src2}",
1996 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1997 def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2),
1998 "sbb{l} {$src2, $dst|$dst, $src2}",
1999 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2000 def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i32i8imm :$src2),
2001 "sbb{l} {$src2, $dst|$dst, $src2}",
2002 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2004 def SBB32rm : I<0x1B, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2),
2005 "sbb{l} {$src2, $dst|$dst, $src2}",
2006 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2007 def SBB32ri : Ii32<0x81, MRM3r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
2008 "sbb{l} {$src2, $dst|$dst, $src2}",
2009 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2010 def SBB32ri8 : Ii8<0x83, MRM3r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
2011 "sbb{l} {$src2, $dst|$dst, $src2}",
2012 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2014 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2015 def IMUL16rr : I<0xAF, MRMSrcReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
2016 "imul{w} {$src2, $dst|$dst, $src2}",
2017 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize;
2018 def IMUL32rr : I<0xAF, MRMSrcReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
2019 "imul{l} {$src2, $dst|$dst, $src2}",
2020 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB;
2022 def IMUL16rm : I<0xAF, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2),
2023 "imul{w} {$src2, $dst|$dst, $src2}",
2024 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>,
2026 def IMUL32rm : I<0xAF, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2),
2027 "imul{l} {$src2, $dst|$dst, $src2}",
2028 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB;
2030 } // end Two Address instructions
2032 // Suprisingly enough, these are not two address instructions!
2033 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2034 (ops GR16:$dst, GR16:$src1, i16imm:$src2),
2035 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
2036 [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize;
2037 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2038 (ops GR32:$dst, GR32:$src1, i32imm:$src2),
2039 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
2040 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
2041 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2042 (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
2043 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
2044 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>,
2046 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2047 (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
2048 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
2049 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>;
2051 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2052 (ops GR16:$dst, i16mem:$src1, i16imm:$src2),
2053 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
2054 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>,
2056 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2057 (ops GR32:$dst, i32mem:$src1, i32imm:$src2),
2058 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
2059 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>;
2060 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2061 (ops GR16:$dst, i16mem:$src1, i16i8imm :$src2),
2062 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
2063 [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>,
2065 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2066 (ops GR32:$dst, i32mem:$src1, i32i8imm: $src2),
2067 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
2068 [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>;
2070 //===----------------------------------------------------------------------===//
2071 // Test instructions are just like AND, except they don't generate a result.
2073 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2074 def TEST8rr : I<0x84, MRMDestReg, (ops GR8:$src1, GR8:$src2),
2075 "test{b} {$src2, $src1|$src1, $src2}",
2076 [(X86test GR8:$src1, GR8:$src2)]>;
2077 def TEST16rr : I<0x85, MRMDestReg, (ops GR16:$src1, GR16:$src2),
2078 "test{w} {$src2, $src1|$src1, $src2}",
2079 [(X86test GR16:$src1, GR16:$src2)]>, OpSize;
2080 def TEST32rr : I<0x85, MRMDestReg, (ops GR32:$src1, GR32:$src2),
2081 "test{l} {$src2, $src1|$src1, $src2}",
2082 [(X86test GR32:$src1, GR32:$src2)]>;
2084 def TEST8mr : I<0x84, MRMDestMem, (ops i8mem :$src1, GR8 :$src2),
2085 "test{b} {$src2, $src1|$src1, $src2}",
2086 [(X86test (loadi8 addr:$src1), GR8:$src2)]>;
2087 def TEST16mr : I<0x85, MRMDestMem, (ops i16mem:$src1, GR16:$src2),
2088 "test{w} {$src2, $src1|$src1, $src2}",
2089 [(X86test (loadi16 addr:$src1), GR16:$src2)]>,
2091 def TEST32mr : I<0x85, MRMDestMem, (ops i32mem:$src1, GR32:$src2),
2092 "test{l} {$src2, $src1|$src1, $src2}",
2093 [(X86test (loadi32 addr:$src1), GR32:$src2)]>;
2094 def TEST8rm : I<0x84, MRMSrcMem, (ops GR8 :$src1, i8mem :$src2),
2095 "test{b} {$src2, $src1|$src1, $src2}",
2096 [(X86test GR8:$src1, (loadi8 addr:$src2))]>;
2097 def TEST16rm : I<0x85, MRMSrcMem, (ops GR16:$src1, i16mem:$src2),
2098 "test{w} {$src2, $src1|$src1, $src2}",
2099 [(X86test GR16:$src1, (loadi16 addr:$src2))]>,
2101 def TEST32rm : I<0x85, MRMSrcMem, (ops GR32:$src1, i32mem:$src2),
2102 "test{l} {$src2, $src1|$src1, $src2}",
2103 [(X86test GR32:$src1, (loadi32 addr:$src2))]>;
2105 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2106 (ops GR8:$src1, i8imm:$src2),
2107 "test{b} {$src2, $src1|$src1, $src2}",
2108 [(X86test GR8:$src1, imm:$src2)]>;
2109 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2110 (ops GR16:$src1, i16imm:$src2),
2111 "test{w} {$src2, $src1|$src1, $src2}",
2112 [(X86test GR16:$src1, imm:$src2)]>, OpSize;
2113 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2114 (ops GR32:$src1, i32imm:$src2),
2115 "test{l} {$src2, $src1|$src1, $src2}",
2116 [(X86test GR32:$src1, imm:$src2)]>;
2117 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2118 (ops i8mem:$src1, i8imm:$src2),
2119 "test{b} {$src2, $src1|$src1, $src2}",
2120 [(X86test (loadi8 addr:$src1), imm:$src2)]>;
2121 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2122 (ops i16mem:$src1, i16imm:$src2),
2123 "test{w} {$src2, $src1|$src1, $src2}",
2124 [(X86test (loadi16 addr:$src1), imm:$src2)]>,
2126 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2127 (ops i32mem:$src1, i32imm:$src2),
2128 "test{l} {$src2, $src1|$src1, $src2}",
2129 [(X86test (loadi32 addr:$src1), imm:$src2)]>;
2132 // Condition code ops, incl. set if equal/not equal/...
2133 def SAHF : I<0x9E, RawFrm, (ops), "sahf", []>, Imp<[AH],[]>; // flags = AH
2134 def LAHF : I<0x9F, RawFrm, (ops), "lahf", []>, Imp<[],[AH]>; // AH = flags
2136 def SETEr : I<0x94, MRM0r,
2139 [(set GR8:$dst, (X86setcc X86_COND_E))]>,
2141 def SETEm : I<0x94, MRM0m,
2144 [(store (X86setcc X86_COND_E), addr:$dst)]>,
2146 def SETNEr : I<0x95, MRM0r,
2149 [(set GR8:$dst, (X86setcc X86_COND_NE))]>,
2151 def SETNEm : I<0x95, MRM0m,
2154 [(store (X86setcc X86_COND_NE), addr:$dst)]>,
2156 def SETLr : I<0x9C, MRM0r,
2159 [(set GR8:$dst, (X86setcc X86_COND_L))]>,
2160 TB; // GR8 = < signed
2161 def SETLm : I<0x9C, MRM0m,
2164 [(store (X86setcc X86_COND_L), addr:$dst)]>,
2165 TB; // [mem8] = < signed
2166 def SETGEr : I<0x9D, MRM0r,
2169 [(set GR8:$dst, (X86setcc X86_COND_GE))]>,
2170 TB; // GR8 = >= signed
2171 def SETGEm : I<0x9D, MRM0m,
2174 [(store (X86setcc X86_COND_GE), addr:$dst)]>,
2175 TB; // [mem8] = >= signed
2176 def SETLEr : I<0x9E, MRM0r,
2179 [(set GR8:$dst, (X86setcc X86_COND_LE))]>,
2180 TB; // GR8 = <= signed
2181 def SETLEm : I<0x9E, MRM0m,
2184 [(store (X86setcc X86_COND_LE), addr:$dst)]>,
2185 TB; // [mem8] = <= signed
2186 def SETGr : I<0x9F, MRM0r,
2189 [(set GR8:$dst, (X86setcc X86_COND_G))]>,
2190 TB; // GR8 = > signed
2191 def SETGm : I<0x9F, MRM0m,
2194 [(store (X86setcc X86_COND_G), addr:$dst)]>,
2195 TB; // [mem8] = > signed
2197 def SETBr : I<0x92, MRM0r,
2200 [(set GR8:$dst, (X86setcc X86_COND_B))]>,
2201 TB; // GR8 = < unsign
2202 def SETBm : I<0x92, MRM0m,
2205 [(store (X86setcc X86_COND_B), addr:$dst)]>,
2206 TB; // [mem8] = < unsign
2207 def SETAEr : I<0x93, MRM0r,
2210 [(set GR8:$dst, (X86setcc X86_COND_AE))]>,
2211 TB; // GR8 = >= unsign
2212 def SETAEm : I<0x93, MRM0m,
2215 [(store (X86setcc X86_COND_AE), addr:$dst)]>,
2216 TB; // [mem8] = >= unsign
2217 def SETBEr : I<0x96, MRM0r,
2220 [(set GR8:$dst, (X86setcc X86_COND_BE))]>,
2221 TB; // GR8 = <= unsign
2222 def SETBEm : I<0x96, MRM0m,
2225 [(store (X86setcc X86_COND_BE), addr:$dst)]>,
2226 TB; // [mem8] = <= unsign
2227 def SETAr : I<0x97, MRM0r,
2230 [(set GR8:$dst, (X86setcc X86_COND_A))]>,
2231 TB; // GR8 = > signed
2232 def SETAm : I<0x97, MRM0m,
2235 [(store (X86setcc X86_COND_A), addr:$dst)]>,
2236 TB; // [mem8] = > signed
2238 def SETSr : I<0x98, MRM0r,
2241 [(set GR8:$dst, (X86setcc X86_COND_S))]>,
2242 TB; // GR8 = <sign bit>
2243 def SETSm : I<0x98, MRM0m,
2246 [(store (X86setcc X86_COND_S), addr:$dst)]>,
2247 TB; // [mem8] = <sign bit>
2248 def SETNSr : I<0x99, MRM0r,
2251 [(set GR8:$dst, (X86setcc X86_COND_NS))]>,
2252 TB; // GR8 = !<sign bit>
2253 def SETNSm : I<0x99, MRM0m,
2256 [(store (X86setcc X86_COND_NS), addr:$dst)]>,
2257 TB; // [mem8] = !<sign bit>
2258 def SETPr : I<0x9A, MRM0r,
2261 [(set GR8:$dst, (X86setcc X86_COND_P))]>,
2263 def SETPm : I<0x9A, MRM0m,
2266 [(store (X86setcc X86_COND_P), addr:$dst)]>,
2267 TB; // [mem8] = parity
2268 def SETNPr : I<0x9B, MRM0r,
2271 [(set GR8:$dst, (X86setcc X86_COND_NP))]>,
2272 TB; // GR8 = not parity
2273 def SETNPm : I<0x9B, MRM0m,
2276 [(store (X86setcc X86_COND_NP), addr:$dst)]>,
2277 TB; // [mem8] = not parity
2279 // Integer comparisons
2280 def CMP8rr : I<0x38, MRMDestReg,
2281 (ops GR8 :$src1, GR8 :$src2),
2282 "cmp{b} {$src2, $src1|$src1, $src2}",
2283 [(X86cmp GR8:$src1, GR8:$src2)]>;
2284 def CMP16rr : I<0x39, MRMDestReg,
2285 (ops GR16:$src1, GR16:$src2),
2286 "cmp{w} {$src2, $src1|$src1, $src2}",
2287 [(X86cmp GR16:$src1, GR16:$src2)]>, OpSize;
2288 def CMP32rr : I<0x39, MRMDestReg,
2289 (ops GR32:$src1, GR32:$src2),
2290 "cmp{l} {$src2, $src1|$src1, $src2}",
2291 [(X86cmp GR32:$src1, GR32:$src2)]>;
2292 def CMP8mr : I<0x38, MRMDestMem,
2293 (ops i8mem :$src1, GR8 :$src2),
2294 "cmp{b} {$src2, $src1|$src1, $src2}",
2295 [(X86cmp (loadi8 addr:$src1), GR8:$src2)]>;
2296 def CMP16mr : I<0x39, MRMDestMem,
2297 (ops i16mem:$src1, GR16:$src2),
2298 "cmp{w} {$src2, $src1|$src1, $src2}",
2299 [(X86cmp (loadi16 addr:$src1), GR16:$src2)]>, OpSize;
2300 def CMP32mr : I<0x39, MRMDestMem,
2301 (ops i32mem:$src1, GR32:$src2),
2302 "cmp{l} {$src2, $src1|$src1, $src2}",
2303 [(X86cmp (loadi32 addr:$src1), GR32:$src2)]>;
2304 def CMP8rm : I<0x3A, MRMSrcMem,
2305 (ops GR8 :$src1, i8mem :$src2),
2306 "cmp{b} {$src2, $src1|$src1, $src2}",
2307 [(X86cmp GR8:$src1, (loadi8 addr:$src2))]>;
2308 def CMP16rm : I<0x3B, MRMSrcMem,
2309 (ops GR16:$src1, i16mem:$src2),
2310 "cmp{w} {$src2, $src1|$src1, $src2}",
2311 [(X86cmp GR16:$src1, (loadi16 addr:$src2))]>, OpSize;
2312 def CMP32rm : I<0x3B, MRMSrcMem,
2313 (ops GR32:$src1, i32mem:$src2),
2314 "cmp{l} {$src2, $src1|$src1, $src2}",
2315 [(X86cmp GR32:$src1, (loadi32 addr:$src2))]>;
2316 def CMP8ri : Ii8<0x80, MRM7r,
2317 (ops GR8:$src1, i8imm:$src2),
2318 "cmp{b} {$src2, $src1|$src1, $src2}",
2319 [(X86cmp GR8:$src1, imm:$src2)]>;
2320 def CMP16ri : Ii16<0x81, MRM7r,
2321 (ops GR16:$src1, i16imm:$src2),
2322 "cmp{w} {$src2, $src1|$src1, $src2}",
2323 [(X86cmp GR16:$src1, imm:$src2)]>, OpSize;
2324 def CMP32ri : Ii32<0x81, MRM7r,
2325 (ops GR32:$src1, i32imm:$src2),
2326 "cmp{l} {$src2, $src1|$src1, $src2}",
2327 [(X86cmp GR32:$src1, imm:$src2)]>;
2328 def CMP8mi : Ii8 <0x80, MRM7m,
2329 (ops i8mem :$src1, i8imm :$src2),
2330 "cmp{b} {$src2, $src1|$src1, $src2}",
2331 [(X86cmp (loadi8 addr:$src1), imm:$src2)]>;
2332 def CMP16mi : Ii16<0x81, MRM7m,
2333 (ops i16mem:$src1, i16imm:$src2),
2334 "cmp{w} {$src2, $src1|$src1, $src2}",
2335 [(X86cmp (loadi16 addr:$src1), imm:$src2)]>, OpSize;
2336 def CMP32mi : Ii32<0x81, MRM7m,
2337 (ops i32mem:$src1, i32imm:$src2),
2338 "cmp{l} {$src2, $src1|$src1, $src2}",
2339 [(X86cmp (loadi32 addr:$src1), imm:$src2)]>;
2340 def CMP16ri8 : Ii8<0x83, MRM7r,
2341 (ops GR16:$src1, i16i8imm:$src2),
2342 "cmp{w} {$src2, $src1|$src1, $src2}",
2343 [(X86cmp GR16:$src1, i16immSExt8:$src2)]>, OpSize;
2344 def CMP16mi8 : Ii8<0x83, MRM7m,
2345 (ops i16mem:$src1, i16i8imm:$src2),
2346 "cmp{w} {$src2, $src1|$src1, $src2}",
2347 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2)]>, OpSize;
2348 def CMP32mi8 : Ii8<0x83, MRM7m,
2349 (ops i32mem:$src1, i32i8imm:$src2),
2350 "cmp{l} {$src2, $src1|$src1, $src2}",
2351 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2)]>;
2352 def CMP32ri8 : Ii8<0x83, MRM7r,
2353 (ops GR32:$src1, i32i8imm:$src2),
2354 "cmp{l} {$src2, $src1|$src1, $src2}",
2355 [(X86cmp GR32:$src1, i32immSExt8:$src2)]>;
2357 // Sign/Zero extenders
2358 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops GR16:$dst, GR8 :$src),
2359 "movs{bw|x} {$src, $dst|$dst, $src}",
2360 [(set GR16:$dst, (sext GR8:$src))]>, TB, OpSize;
2361 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops GR16:$dst, i8mem :$src),
2362 "movs{bw|x} {$src, $dst|$dst, $src}",
2363 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize;
2364 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops GR32:$dst, GR8 :$src),
2365 "movs{bl|x} {$src, $dst|$dst, $src}",
2366 [(set GR32:$dst, (sext GR8:$src))]>, TB;
2367 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops GR32:$dst, i8mem :$src),
2368 "movs{bl|x} {$src, $dst|$dst, $src}",
2369 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
2370 def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops GR32:$dst, GR16:$src),
2371 "movs{wl|x} {$src, $dst|$dst, $src}",
2372 [(set GR32:$dst, (sext GR16:$src))]>, TB;
2373 def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops GR32:$dst, i16mem:$src),
2374 "movs{wl|x} {$src, $dst|$dst, $src}",
2375 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
2377 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops GR16:$dst, GR8 :$src),
2378 "movz{bw|x} {$src, $dst|$dst, $src}",
2379 [(set GR16:$dst, (zext GR8:$src))]>, TB, OpSize;
2380 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops GR16:$dst, i8mem :$src),
2381 "movz{bw|x} {$src, $dst|$dst, $src}",
2382 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize;
2383 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops GR32:$dst, GR8 :$src),
2384 "movz{bl|x} {$src, $dst|$dst, $src}",
2385 [(set GR32:$dst, (zext GR8:$src))]>, TB;
2386 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops GR32:$dst, i8mem :$src),
2387 "movz{bl|x} {$src, $dst|$dst, $src}",
2388 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
2389 def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops GR32:$dst, GR16:$src),
2390 "movz{wl|x} {$src, $dst|$dst, $src}",
2391 [(set GR32:$dst, (zext GR16:$src))]>, TB;
2392 def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops GR32:$dst, i16mem:$src),
2393 "movz{wl|x} {$src, $dst|$dst, $src}",
2394 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
2396 def CBW : I<0x98, RawFrm, (ops),
2397 "{cbtw|cbw}", []>, Imp<[AL],[AX]>; // AX = signext(AL)
2398 def CWDE : I<0x98, RawFrm, (ops),
2399 "{cwtl|cwde}", []>, Imp<[AX],[EAX]>; // EAX = signext(AX)
2401 def CWD : I<0x99, RawFrm, (ops),
2402 "{cwtd|cwd}", []>, Imp<[AX],[AX,DX]>; // DX:AX = signext(AX)
2403 def CDQ : I<0x99, RawFrm, (ops),
2404 "{cltd|cdq}", []>, Imp<[EAX],[EAX,EDX]>; // EDX:EAX = signext(EAX)
2406 //===----------------------------------------------------------------------===//
2407 // Miscellaneous Instructions
2408 //===----------------------------------------------------------------------===//
2410 def RDTSC : I<0x31, RawFrm, (ops), "rdtsc", [(X86rdtsc)]>,
2411 TB, Imp<[],[EAX,EDX]>;
2413 //===----------------------------------------------------------------------===//
2414 // Alias Instructions
2415 //===----------------------------------------------------------------------===//
2417 // Alias instructions that map movr0 to xor.
2418 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2419 def MOV8r0 : I<0x30, MRMInitReg, (ops GR8 :$dst),
2420 "xor{b} $dst, $dst",
2421 [(set GR8:$dst, 0)]>;
2422 def MOV16r0 : I<0x31, MRMInitReg, (ops GR16:$dst),
2423 "xor{w} $dst, $dst",
2424 [(set GR16:$dst, 0)]>, OpSize;
2425 def MOV32r0 : I<0x31, MRMInitReg, (ops GR32:$dst),
2426 "xor{l} $dst, $dst",
2427 [(set GR32:$dst, 0)]>;
2429 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
2430 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
2431 def MOV16to16_ : I<0x89, MRMDestReg, (ops GR16_:$dst, GR16:$src),
2432 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2433 def MOV32to32_ : I<0x89, MRMDestReg, (ops GR32_:$dst, GR32:$src),
2434 "mov{l} {$src, $dst|$dst, $src}", []>;
2436 def MOV16_rr : I<0x89, MRMDestReg, (ops GR16_:$dst, GR16_:$src),
2437 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2438 def MOV32_rr : I<0x89, MRMDestReg, (ops GR32_:$dst, GR32_:$src),
2439 "mov{l} {$src, $dst|$dst, $src}", []>;
2440 def MOV16_rm : I<0x8B, MRMSrcMem, (ops GR16_:$dst, i16mem:$src),
2441 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2442 def MOV32_rm : I<0x8B, MRMSrcMem, (ops GR32_:$dst, i32mem:$src),
2443 "mov{l} {$src, $dst|$dst, $src}", []>;
2444 def MOV16_mr : I<0x89, MRMDestMem, (ops i16mem:$dst, GR16_:$src),
2445 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2446 def MOV32_mr : I<0x89, MRMDestMem, (ops i32mem:$dst, GR32_:$src),
2447 "mov{l} {$src, $dst|$dst, $src}", []>;
2449 //===----------------------------------------------------------------------===//
2450 // DWARF Pseudo Instructions
2453 def DWARF_LOC : I<0, Pseudo, (ops i32imm:$line, i32imm:$col, i32imm:$file),
2454 "; .loc $file, $line, $col",
2455 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
2458 def DWARF_LABEL : I<0, Pseudo, (ops i32imm:$id),
2459 "\nLdebug_loc${id:debug}:",
2460 [(dwarf_label (i32 imm:$id))]>;
2462 //===----------------------------------------------------------------------===//
2463 // Non-Instruction Patterns
2464 //===----------------------------------------------------------------------===//
2466 // ConstantPool GlobalAddress, ExternalSymbol
2467 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
2468 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
2469 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
2470 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
2472 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
2473 (ADD32ri GR32:$src1, tconstpool:$src2)>;
2474 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
2475 (ADD32ri GR32:$src1, tjumptable:$src2)>;
2476 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
2477 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
2478 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
2479 (ADD32ri GR32:$src1, texternalsym:$src2)>;
2481 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
2482 (MOV32mi addr:$dst, tglobaladdr:$src)>;
2483 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
2484 (MOV32mi addr:$dst, texternalsym:$src)>;
2487 def : Pat<(X86tailcall GR32:$dst),
2488 (CALL32r GR32:$dst)>;
2490 def : Pat<(X86tailcall tglobaladdr:$dst),
2491 (CALLpcrel32 tglobaladdr:$dst)>;
2492 def : Pat<(X86tailcall texternalsym:$dst),
2493 (CALLpcrel32 texternalsym:$dst)>;
2497 def : Pat<(X86call tglobaladdr:$dst),
2498 (CALLpcrel32 tglobaladdr:$dst)>;
2499 def : Pat<(X86call texternalsym:$dst),
2500 (CALLpcrel32 texternalsym:$dst)>;
2502 // X86 specific add which produces a flag.
2503 def : Pat<(addc GR32:$src1, GR32:$src2),
2504 (ADD32rr GR32:$src1, GR32:$src2)>;
2505 def : Pat<(addc GR32:$src1, (load addr:$src2)),
2506 (ADD32rm GR32:$src1, addr:$src2)>;
2507 def : Pat<(addc GR32:$src1, imm:$src2),
2508 (ADD32ri GR32:$src1, imm:$src2)>;
2509 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
2510 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
2512 def : Pat<(subc GR32:$src1, GR32:$src2),
2513 (SUB32rr GR32:$src1, GR32:$src2)>;
2514 def : Pat<(subc GR32:$src1, (load addr:$src2)),
2515 (SUB32rm GR32:$src1, addr:$src2)>;
2516 def : Pat<(subc GR32:$src1, imm:$src2),
2517 (SUB32ri GR32:$src1, imm:$src2)>;
2518 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
2519 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
2521 def : Pat<(truncstore (i8 imm:$src), addr:$dst, i1),
2522 (MOV8mi addr:$dst, imm:$src)>;
2523 def : Pat<(truncstore GR8:$src, addr:$dst, i1),
2524 (MOV8mr addr:$dst, GR8:$src)>;
2526 // {s|z}extload bool -> {s|z}extload byte
2527 def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>;
2528 def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>;
2529 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2530 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2531 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2533 // extload bool -> extload byte
2534 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2535 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2536 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2537 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
2538 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
2539 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
2542 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
2543 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
2544 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
2545 def : Pat<(i16 (anyext (loadi8 addr:$src))), (MOVZX16rm8 addr:$src)>;
2546 def : Pat<(i32 (anyext (loadi8 addr:$src))), (MOVZX32rm8 addr:$src)>;
2547 def : Pat<(i32 (anyext (loadi16 addr:$src))), (MOVZX32rm16 addr:$src)>;
2549 //===----------------------------------------------------------------------===//
2551 //===----------------------------------------------------------------------===//
2553 // (shl x, 1) ==> (add x, x)
2554 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
2555 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
2556 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
2558 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
2559 def : Pat<(or (srl GR32:$src1, CL:$amt),
2560 (shl GR32:$src2, (sub 32, CL:$amt))),
2561 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
2563 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
2564 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2565 (SHRD32mrCL addr:$dst, GR32:$src2)>;
2567 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
2568 def : Pat<(or (shl GR32:$src1, CL:$amt),
2569 (srl GR32:$src2, (sub 32, CL:$amt))),
2570 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
2572 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
2573 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2574 (SHLD32mrCL addr:$dst, GR32:$src2)>;
2576 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
2577 def : Pat<(or (srl GR16:$src1, CL:$amt),
2578 (shl GR16:$src2, (sub 16, CL:$amt))),
2579 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
2581 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
2582 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2583 (SHRD16mrCL addr:$dst, GR16:$src2)>;
2585 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
2586 def : Pat<(or (shl GR16:$src1, CL:$amt),
2587 (srl GR16:$src2, (sub 16, CL:$amt))),
2588 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
2590 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
2591 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2592 (SHLD16mrCL addr:$dst, GR16:$src2)>;
2595 //===----------------------------------------------------------------------===//
2596 // Floating Point Stack Support
2597 //===----------------------------------------------------------------------===//
2599 include "X86InstrFPStack.td"
2601 //===----------------------------------------------------------------------===//
2602 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
2603 //===----------------------------------------------------------------------===//
2605 include "X86InstrMMX.td"
2607 //===----------------------------------------------------------------------===//
2608 // XMM Floating point support (requires SSE / SSE2)
2609 //===----------------------------------------------------------------------===//
2611 include "X86InstrSSE.td"