1 //===----------------------------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
32 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
34 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTX86BrCond : SDTypeProfile<0, 3,
39 [SDTCisVT<0, OtherVT>,
40 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
42 def SDTX86SetCC : SDTypeProfile<1, 2,
44 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86SetCC_C : SDTypeProfile<1, 2,
47 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
49 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
51 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
53 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
54 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
55 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
57 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
58 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
61 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
63 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
67 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
69 def SDTX86Void : SDTypeProfile<0, 0, []>;
71 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
73 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
75 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
77 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
79 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
81 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
83 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
84 def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
86 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
88 def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE,
90 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
92 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
94 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
98 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
99 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
100 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
101 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
103 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
104 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
106 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
107 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
109 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
110 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
112 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
113 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
115 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
116 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
118 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
119 [SDNPHasChain, SDNPMayStore,
120 SDNPMayLoad, SDNPMemOperand]>;
121 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
122 [SDNPHasChain, SDNPMayStore,
123 SDNPMayLoad, SDNPMemOperand]>;
124 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
125 [SDNPHasChain, SDNPMayStore,
126 SDNPMayLoad, SDNPMemOperand]>;
127 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
128 [SDNPHasChain, SDNPMayStore,
129 SDNPMayLoad, SDNPMemOperand]>;
130 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
131 [SDNPHasChain, SDNPMayStore,
132 SDNPMayLoad, SDNPMemOperand]>;
133 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
134 [SDNPHasChain, SDNPMayStore,
135 SDNPMayLoad, SDNPMemOperand]>;
136 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
137 [SDNPHasChain, SDNPMayStore,
138 SDNPMayLoad, SDNPMemOperand]>;
139 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
140 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
142 def X86vastart_save_xmm_regs :
143 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
144 SDT_X86VASTART_SAVE_XMM_REGS,
145 [SDNPHasChain, SDNPVariadic]>;
147 def X86callseq_start :
148 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
149 [SDNPHasChain, SDNPOutFlag]>;
151 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
152 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
154 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
155 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
158 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
159 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
160 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
161 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
164 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
165 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
167 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
168 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
170 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
171 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
172 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
173 SDT_X86SegmentBaseAddress, []>;
175 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
178 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
179 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
181 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
183 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
184 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
186 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
189 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
190 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
191 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
193 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
195 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
198 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
200 def X86MingwAlloca : SDNode<"X86ISD::MINGW_ALLOCA", SDTX86Void,
201 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
203 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
206 //===----------------------------------------------------------------------===//
207 // X86 Operand Definitions.
210 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
211 // the index operand of an address, to conform to x86 encoding restrictions.
212 def ptr_rc_nosp : PointerLikeRegClass<1>;
214 // *mem - Operand definitions for the funky X86 addressing mode operands.
216 def X86MemAsmOperand : AsmOperandClass {
218 let SuperClasses = [];
220 def X86AbsMemAsmOperand : AsmOperandClass {
222 let SuperClasses = [X86MemAsmOperand];
224 class X86MemOperand<string printMethod> : Operand<iPTR> {
225 let PrintMethod = printMethod;
226 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
227 let ParserMatchClass = X86MemAsmOperand;
230 def opaque32mem : X86MemOperand<"printopaquemem">;
231 def opaque48mem : X86MemOperand<"printopaquemem">;
232 def opaque80mem : X86MemOperand<"printopaquemem">;
233 def opaque512mem : X86MemOperand<"printopaquemem">;
235 def i8mem : X86MemOperand<"printi8mem">;
236 def i16mem : X86MemOperand<"printi16mem">;
237 def i32mem : X86MemOperand<"printi32mem">;
238 def i64mem : X86MemOperand<"printi64mem">;
239 def i128mem : X86MemOperand<"printi128mem">;
240 def i256mem : X86MemOperand<"printi256mem">;
241 def f32mem : X86MemOperand<"printf32mem">;
242 def f64mem : X86MemOperand<"printf64mem">;
243 def f80mem : X86MemOperand<"printf80mem">;
244 def f128mem : X86MemOperand<"printf128mem">;
245 def f256mem : X86MemOperand<"printf256mem">;
247 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
248 // plain GR64, so that it doesn't potentially require a REX prefix.
249 def i8mem_NOREX : Operand<i64> {
250 let PrintMethod = "printi8mem";
251 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
252 let ParserMatchClass = X86MemAsmOperand;
255 // Special i32mem for addresses of load folding tail calls. These are not
256 // allowed to use callee-saved registers since they must be scheduled
257 // after callee-saved register are popped.
258 def i32mem_TC : Operand<i32> {
259 let PrintMethod = "printi32mem";
260 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
261 let ParserMatchClass = X86MemAsmOperand;
265 let ParserMatchClass = X86AbsMemAsmOperand,
266 PrintMethod = "print_pcrel_imm" in {
267 def i32imm_pcrel : Operand<i32>;
268 def i16imm_pcrel : Operand<i16>;
270 def offset8 : Operand<i64>;
271 def offset16 : Operand<i64>;
272 def offset32 : Operand<i64>;
273 def offset64 : Operand<i64>;
275 // Branch targets have OtherVT type and print as pc-relative values.
276 def brtarget : Operand<OtherVT>;
277 def brtarget8 : Operand<OtherVT>;
281 def SSECC : Operand<i8> {
282 let PrintMethod = "printSSECC";
285 class ImmSExtAsmOperandClass : AsmOperandClass {
286 let SuperClasses = [ImmAsmOperand];
287 let RenderMethod = "addImmOperands";
290 // Sign-extended immediate classes. We don't need to define the full lattice
291 // here because there is no instruction with an ambiguity between ImmSExti64i32
294 // The strange ranges come from the fact that the assembler always works with
295 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
296 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
299 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
300 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
301 let Name = "ImmSExti64i32";
304 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
305 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
306 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
307 let Name = "ImmSExti16i8";
308 let SuperClasses = [ImmSExti64i32AsmOperand];
311 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
312 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
313 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
314 let Name = "ImmSExti32i8";
318 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
319 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
320 let Name = "ImmSExti64i8";
321 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
322 ImmSExti64i32AsmOperand];
325 // A couple of more descriptive operand definitions.
326 // 16-bits but only 8 bits are significant.
327 def i16i8imm : Operand<i16> {
328 let ParserMatchClass = ImmSExti16i8AsmOperand;
330 // 32-bits but only 8 bits are significant.
331 def i32i8imm : Operand<i32> {
332 let ParserMatchClass = ImmSExti32i8AsmOperand;
335 //===----------------------------------------------------------------------===//
336 // X86 Complex Pattern Definitions.
339 // Define X86 specific addressing mode.
340 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
341 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
342 [add, sub, mul, X86mul_imm, shl, or, frameindex],
344 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
345 [tglobaltlsaddr], []>;
347 //===----------------------------------------------------------------------===//
348 // X86 Instruction Predicate Definitions.
349 def HasCMov : Predicate<"Subtarget->hasCMov()">;
350 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
351 def HasMMX : Predicate<"Subtarget->hasMMX()">;
352 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
353 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
354 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
355 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
356 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
357 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
358 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
359 def HasAVX : Predicate<"Subtarget->hasAVX()">;
360 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
361 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
362 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
363 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
364 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
365 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
366 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
367 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
368 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
369 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
370 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
371 "TM.getCodeModel() != CodeModel::Kernel">;
372 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
373 "TM.getCodeModel() == CodeModel::Kernel">;
374 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
375 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
376 def OptForSize : Predicate<"OptForSize">;
377 def OptForSpeed : Predicate<"!OptForSize">;
378 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
379 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
380 def HasAES : Predicate<"Subtarget->hasAES()">;
382 //===----------------------------------------------------------------------===//
383 // X86 Instruction Format Definitions.
386 include "X86InstrFormats.td"
388 //===----------------------------------------------------------------------===//
389 // Pattern fragments...
392 // X86 specific condition code. These correspond to CondCode in
393 // X86InstrInfo.h. They must be kept in synch.
394 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
395 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
396 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
397 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
398 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
399 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
400 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
401 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
402 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
403 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
404 def X86_COND_NO : PatLeaf<(i8 10)>;
405 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
406 def X86_COND_NS : PatLeaf<(i8 12)>;
407 def X86_COND_O : PatLeaf<(i8 13)>;
408 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
409 def X86_COND_S : PatLeaf<(i8 15)>;
411 def immSext8 : PatLeaf<(imm), [{
412 return N->getSExtValue() == (int8_t)N->getSExtValue();
415 def i16immSExt8 : PatLeaf<(i16 immSext8)>;
416 def i32immSExt8 : PatLeaf<(i32 immSext8)>;
418 /// Load patterns: these constraint the match to the right address space.
419 def dsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
420 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
421 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
422 if (PT->getAddressSpace() > 255)
427 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
428 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
429 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
430 return PT->getAddressSpace() == 256;
434 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
435 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
436 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
437 return PT->getAddressSpace() == 257;
442 // Helper fragments for loads.
443 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
444 // known to be 32-bit aligned or better. Ditto for i8 to i16.
445 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
446 LoadSDNode *LD = cast<LoadSDNode>(N);
447 if (const Value *Src = LD->getSrcValue())
448 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
449 if (PT->getAddressSpace() > 255)
451 ISD::LoadExtType ExtType = LD->getExtensionType();
452 if (ExtType == ISD::NON_EXTLOAD)
454 if (ExtType == ISD::EXTLOAD)
455 return LD->getAlignment() >= 2 && !LD->isVolatile();
459 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
460 LoadSDNode *LD = cast<LoadSDNode>(N);
461 if (const Value *Src = LD->getSrcValue())
462 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
463 if (PT->getAddressSpace() > 255)
465 ISD::LoadExtType ExtType = LD->getExtensionType();
466 if (ExtType == ISD::EXTLOAD)
467 return LD->getAlignment() >= 2 && !LD->isVolatile();
471 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
472 LoadSDNode *LD = cast<LoadSDNode>(N);
473 if (const Value *Src = LD->getSrcValue())
474 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
475 if (PT->getAddressSpace() > 255)
477 ISD::LoadExtType ExtType = LD->getExtensionType();
478 if (ExtType == ISD::NON_EXTLOAD)
480 if (ExtType == ISD::EXTLOAD)
481 return LD->getAlignment() >= 4 && !LD->isVolatile();
485 def loadi8 : PatFrag<(ops node:$ptr), (i8 (dsload node:$ptr))>;
486 def loadi64 : PatFrag<(ops node:$ptr), (i64 (dsload node:$ptr))>;
487 def loadf32 : PatFrag<(ops node:$ptr), (f32 (dsload node:$ptr))>;
488 def loadf64 : PatFrag<(ops node:$ptr), (f64 (dsload node:$ptr))>;
489 def loadf80 : PatFrag<(ops node:$ptr), (f80 (dsload node:$ptr))>;
491 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
492 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
493 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
495 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
496 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
497 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
498 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
499 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
500 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
502 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
503 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
504 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
505 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
506 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
507 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
510 // An 'and' node with a single use.
511 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
512 return N->hasOneUse();
514 // An 'srl' node with a single use.
515 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
516 return N->hasOneUse();
518 // An 'trunc' node with a single use.
519 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
520 return N->hasOneUse();
523 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
524 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
525 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
526 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
528 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
529 APInt Mask = APInt::getAllOnesValue(BitWidth);
530 APInt KnownZero0, KnownOne0;
531 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
532 APInt KnownZero1, KnownOne1;
533 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
534 return (~KnownZero0 & ~KnownZero1) == 0;
537 //===----------------------------------------------------------------------===//
538 // Instruction list...
541 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
542 // a stack adjustment and the codegen must know that they may modify the stack
543 // pointer before prolog-epilog rewriting occurs.
544 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
545 // sub / add which can clobber EFLAGS.
546 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
547 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
549 [(X86callseq_start timm:$amt)]>,
550 Requires<[In32BitMode]>;
551 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
553 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
554 Requires<[In32BitMode]>;
557 // x86-64 va_start lowering magic.
558 let usesCustomInserter = 1 in {
559 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
562 i64imm:$regsavefi, i64imm:$offset,
564 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
565 [(X86vastart_save_xmm_regs GR8:$al,
569 // Dynamic stack allocation yields _alloca call for Cygwin/Mingw targets. Calls
570 // to _alloca is needed to probe the stack when allocating more than 4k bytes in
571 // one go. Touching the stack at 4K increments is necessary to ensure that the
572 // guard pages used by the OS virtual memory manager are allocated in correct
574 // The main point of having separate instruction are extra unmodelled effects
575 // (compared to ordinary calls) like stack pointer change.
577 def MINGW_ALLOCA : I<0, Pseudo, (outs), (ins),
578 "# dynamic stack allocation",
583 let neverHasSideEffects = 1 in {
584 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
585 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
586 "nop{w}\t$zero", []>, TB, OpSize;
587 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
588 "nop{l}\t$zero", []>, TB;
592 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
593 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", []>;
594 // FIXME: need to make sure that "int $3" matches int3
595 def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
596 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
597 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>;
599 // PIC base construction. This expands to code that looks like this:
602 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
603 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
606 //===----------------------------------------------------------------------===//
607 // Control Flow Instructions.
610 // Return instructions.
611 let isTerminator = 1, isReturn = 1, isBarrier = 1,
612 hasCtrlDep = 1, FPForm = SpecialFP in {
613 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
616 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
618 [(X86retflag timm:$amt)]>;
619 def LRET : I <0xCB, RawFrm, (outs), (ins),
621 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
625 // Unconditional branches.
626 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
627 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
628 "jmp\t$dst", [(br bb:$dst)]>;
629 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
633 // Conditional Branches.
634 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
635 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
636 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
637 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
638 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
642 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
643 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
644 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
645 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
646 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
647 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
648 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
649 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
650 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
651 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
652 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
653 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
654 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
655 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
656 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
657 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
659 // FIXME: What about the CX/RCX versions of this instruction?
660 let Uses = [ECX], isBranch = 1, isTerminator = 1 in
661 def JCXZ8 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
666 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
667 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
668 [(brind GR32:$dst)]>, Requires<[In32BitMode]>;
669 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
670 [(brind (loadi32 addr:$dst))]>, Requires<[In32BitMode]>;
672 def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
673 (ins i16imm:$seg, i16imm:$off),
674 "ljmp{w}\t$seg, $off", []>, OpSize;
675 def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
676 (ins i16imm:$seg, i32imm:$off),
677 "ljmp{l}\t$seg, $off", []>;
679 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
680 "ljmp{w}\t{*}$dst", []>, OpSize;
681 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
682 "ljmp{l}\t{*}$dst", []>;
688 def LOOP : I<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>;
689 def LOOPE : I<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>;
690 def LOOPNE : I<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>;
692 //===----------------------------------------------------------------------===//
693 // Call Instructions...
696 // All calls clobber the non-callee saved registers. ESP is marked as
697 // a use to prevent stack-pointer assignments that appear immediately
698 // before calls from potentially appearing dead. Uses for argument
699 // registers are added manually.
700 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
701 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
702 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
703 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
705 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
706 (outs), (ins i32imm_pcrel:$dst,variable_ops),
708 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
709 "call\t{*}$dst", [(X86call GR32:$dst)]>;
710 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
711 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
713 def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
714 (ins i16imm:$seg, i16imm:$off),
715 "lcall{w}\t$seg, $off", []>, OpSize;
716 def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
717 (ins i16imm:$seg, i32imm:$off),
718 "lcall{l}\t$seg, $off", []>;
720 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
721 "lcall{w}\t{*}$dst", []>, OpSize;
722 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
723 "lcall{l}\t{*}$dst", []>;
725 // callw for 16 bit code for the assembler.
726 let isAsmParserOnly = 1 in
727 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
728 (outs), (ins i16imm_pcrel:$dst, variable_ops),
729 "callw\t$dst", []>, OpSize;
732 // Constructing a stack frame.
734 def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
735 "enter\t$len, $lvl", []>;
739 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
741 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
742 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
743 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
744 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
746 def TCRETURNdi : I<0, Pseudo, (outs),
747 (ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
748 "#TC_RETURN $dst $offset", []>;
749 def TCRETURNri : I<0, Pseudo, (outs),
750 (ins GR32_TC:$dst, i32imm:$offset, variable_ops),
751 "#TC_RETURN $dst $offset", []>;
753 def TCRETURNmi : I<0, Pseudo, (outs),
754 (ins i32mem_TC:$dst, i32imm:$offset, variable_ops),
755 "#TC_RETURN $dst $offset", []>;
757 // FIXME: The should be pseudo instructions that are lowered when going to
759 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
760 (ins i32imm_pcrel:$dst, variable_ops),
761 "jmp\t$dst # TAILCALL",
763 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
764 "", []>; // FIXME: Remove encoding when JIT is dead.
766 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops),
767 "jmp{l}\t{*}$dst # TAILCALL", []>;
770 //===----------------------------------------------------------------------===//
771 // Miscellaneous Instructions...
773 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
774 def LEAVE : I<0xC9, RawFrm,
775 (outs), (ins), "leave", []>, Requires<[In32BitMode]>;
777 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
778 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
780 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
781 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
782 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
783 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
785 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
786 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
788 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
790 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
792 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
793 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
795 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
797 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
798 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
801 let mayStore = 1 in {
802 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
804 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
805 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
807 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
809 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
810 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
814 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
815 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
816 "push{l}\t$imm", []>;
817 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
818 "push{w}\t$imm", []>, OpSize;
819 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
820 "push{l}\t$imm", []>;
823 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
824 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
825 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
826 Requires<[In32BitMode]>;
828 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
829 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
830 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
831 Requires<[In32BitMode]>;
834 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
835 mayLoad=1, neverHasSideEffects=1 in {
836 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>,
837 Requires<[In32BitMode]>;
839 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
840 mayStore=1, neverHasSideEffects=1 in {
841 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>,
842 Requires<[In32BitMode]>;
845 let Uses = [EFLAGS], Constraints = "$src = $dst" in // GR32 = bswap GR32
846 def BSWAP32r : I<0xC8, AddRegFrm,
847 (outs GR32:$dst), (ins GR32:$src),
849 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
852 // Bit scan instructions.
853 let Defs = [EFLAGS] in {
854 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
855 "bsf{w}\t{$src, $dst|$dst, $src}",
856 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
857 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
858 "bsf{w}\t{$src, $dst|$dst, $src}",
859 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
861 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
862 "bsf{l}\t{$src, $dst|$dst, $src}",
863 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
864 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
865 "bsf{l}\t{$src, $dst|$dst, $src}",
866 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
868 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
869 "bsr{w}\t{$src, $dst|$dst, $src}",
870 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
871 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
872 "bsr{w}\t{$src, $dst|$dst, $src}",
873 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
875 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
876 "bsr{l}\t{$src, $dst|$dst, $src}",
877 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
878 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
879 "bsr{l}\t{$src, $dst|$dst, $src}",
880 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
883 let neverHasSideEffects = 1 in
884 def LEA16r : I<0x8D, MRMSrcMem,
885 (outs GR16:$dst), (ins i32mem:$src),
886 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
887 let isReMaterializable = 1 in
888 def LEA32r : I<0x8D, MRMSrcMem,
889 (outs GR32:$dst), (ins i32mem:$src),
890 "lea{l}\t{$src|$dst}, {$dst|$src}",
891 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
893 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
894 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
895 [(X86rep_movs i8)]>, REP;
896 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
897 [(X86rep_movs i16)]>, REP, OpSize;
898 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
899 [(X86rep_movs i32)]>, REP;
902 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
903 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
904 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
905 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
906 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
909 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
910 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
911 [(X86rep_stos i8)]>, REP;
912 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
913 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
914 [(X86rep_stos i16)]>, REP, OpSize;
915 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
916 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
917 [(X86rep_stos i32)]>, REP;
919 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
920 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
921 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
922 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
923 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
924 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
925 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
927 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
928 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
929 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
931 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
932 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
933 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
935 let Defs = [RAX, RDX] in
936 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
939 let Defs = [RAX, RCX, RDX] in
940 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
942 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
943 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
946 def SYSCALL : I<0x05, RawFrm,
947 (outs), (ins), "syscall", []>, TB;
948 def SYSRET : I<0x07, RawFrm,
949 (outs), (ins), "sysret", []>, TB;
950 def SYSENTER : I<0x34, RawFrm,
951 (outs), (ins), "sysenter", []>, TB;
952 def SYSEXIT : I<0x35, RawFrm,
953 (outs), (ins), "sysexit", []>, TB, Requires<[In32BitMode]>;
955 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
958 //===----------------------------------------------------------------------===//
959 // Input/Output Instructions...
961 let Defs = [AL], Uses = [DX] in
962 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
963 "in{b}\t{%dx, %al|%AL, %DX}", []>;
964 let Defs = [AX], Uses = [DX] in
965 def IN16rr : I<0xED, RawFrm, (outs), (ins),
966 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
967 let Defs = [EAX], Uses = [DX] in
968 def IN32rr : I<0xED, RawFrm, (outs), (ins),
969 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
972 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
973 "in{b}\t{$port, %al|%AL, $port}", []>;
975 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
976 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
978 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
979 "in{l}\t{$port, %eax|%EAX, $port}", []>;
981 let Uses = [DX, AL] in
982 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
983 "out{b}\t{%al, %dx|%DX, %AL}", []>;
984 let Uses = [DX, AX] in
985 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
986 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
987 let Uses = [DX, EAX] in
988 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
989 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
992 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
993 "out{b}\t{%al, $port|$port, %AL}", []>;
995 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
996 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
998 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
999 "out{l}\t{%eax, $port|$port, %EAX}", []>;
1001 def IN8 : I<0x6C, RawFrm, (outs), (ins),
1003 def IN16 : I<0x6D, RawFrm, (outs), (ins),
1004 "ins{w}", []>, OpSize;
1005 def IN32 : I<0x6D, RawFrm, (outs), (ins),
1008 //===----------------------------------------------------------------------===//
1009 // Move Instructions...
1011 let neverHasSideEffects = 1 in {
1012 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1013 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1014 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1015 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1016 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1017 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1019 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1020 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1021 "mov{b}\t{$src, $dst|$dst, $src}",
1022 [(set GR8:$dst, imm:$src)]>;
1023 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1024 "mov{w}\t{$src, $dst|$dst, $src}",
1025 [(set GR16:$dst, imm:$src)]>, OpSize;
1026 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1027 "mov{l}\t{$src, $dst|$dst, $src}",
1028 [(set GR32:$dst, imm:$src)]>;
1031 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1032 "mov{b}\t{$src, $dst|$dst, $src}",
1033 [(store (i8 imm:$src), addr:$dst)]>;
1034 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1035 "mov{w}\t{$src, $dst|$dst, $src}",
1036 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
1037 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1038 "mov{l}\t{$src, $dst|$dst, $src}",
1039 [(store (i32 imm:$src), addr:$dst)]>;
1041 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
1042 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
1043 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
1044 "mov{b}\t{$src, %al|%al, $src}", []>,
1045 Requires<[In32BitMode]>;
1046 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
1047 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize,
1048 Requires<[In32BitMode]>;
1049 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1050 "mov{l}\t{$src, %eax|%eax, $src}", []>,
1051 Requires<[In32BitMode]>;
1052 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1053 "mov{b}\t{%al, $dst|$dst, %al}", []>,
1054 Requires<[In32BitMode]>;
1055 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1056 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize,
1057 Requires<[In32BitMode]>;
1058 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1059 "mov{l}\t{%eax, $dst|$dst, %eax}", []>,
1060 Requires<[In32BitMode]>;
1062 // Moves to and from segment registers
1063 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
1064 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1065 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
1066 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1067 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
1068 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1069 def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
1070 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1071 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
1072 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1073 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
1074 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1075 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
1076 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1077 def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
1078 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1080 let isCodeGenOnly = 1 in {
1081 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1082 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1083 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1084 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1085 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1086 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1089 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1090 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1091 "mov{b}\t{$src, $dst|$dst, $src}",
1092 [(set GR8:$dst, (loadi8 addr:$src))]>;
1093 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1094 "mov{w}\t{$src, $dst|$dst, $src}",
1095 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
1096 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1097 "mov{l}\t{$src, $dst|$dst, $src}",
1098 [(set GR32:$dst, (loadi32 addr:$src))]>;
1101 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1102 "mov{b}\t{$src, $dst|$dst, $src}",
1103 [(store GR8:$src, addr:$dst)]>;
1104 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1105 "mov{w}\t{$src, $dst|$dst, $src}",
1106 [(store GR16:$src, addr:$dst)]>, OpSize;
1107 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1108 "mov{l}\t{$src, $dst|$dst, $src}",
1109 [(store GR32:$src, addr:$dst)]>;
1111 /// Versions of MOV32rr, MOV32rm, and MOV32mr for i32mem_TC and GR32_TC.
1112 let isCodeGenOnly = 1 in {
1113 let neverHasSideEffects = 1 in
1114 def MOV32rr_TC : I<0x89, MRMDestReg, (outs GR32_TC:$dst), (ins GR32_TC:$src),
1115 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1118 canFoldAsLoad = 1, isReMaterializable = 1 in
1119 def MOV32rm_TC : I<0x8B, MRMSrcMem, (outs GR32_TC:$dst), (ins i32mem_TC:$src),
1120 "mov{l}\t{$src, $dst|$dst, $src}",
1124 def MOV32mr_TC : I<0x89, MRMDestMem, (outs), (ins i32mem_TC:$dst, GR32_TC:$src),
1125 "mov{l}\t{$src, $dst|$dst, $src}",
1129 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1130 // that they can be used for copying and storing h registers, which can't be
1131 // encoded when a REX prefix is present.
1132 let isCodeGenOnly = 1 in {
1133 let neverHasSideEffects = 1 in
1134 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1135 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1136 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1138 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1139 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1140 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1142 canFoldAsLoad = 1, isReMaterializable = 1 in
1143 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1144 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1145 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1148 // Moves to and from debug registers
1149 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1150 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1151 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1152 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1154 // Moves to and from control registers
1155 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
1156 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1157 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
1158 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1160 //===----------------------------------------------------------------------===//
1161 // Fixed-Register Multiplication and Division Instructions...
1164 // Extra precision multiplication
1166 // AL is really implied by AX, by the registers in Defs must match the
1167 // SDNode results (i8, i32).
1168 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1169 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1170 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1171 // This probably ought to be moved to a def : Pat<> if the
1172 // syntax can be accepted.
1173 [(set AL, (mul AL, GR8:$src)),
1174 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1176 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1177 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1179 []>, OpSize; // AX,DX = AX*GR16
1181 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1182 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1184 []>; // EAX,EDX = EAX*GR32
1186 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1187 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1189 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1190 // This probably ought to be moved to a def : Pat<> if the
1191 // syntax can be accepted.
1192 [(set AL, (mul AL, (loadi8 addr:$src))),
1193 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1195 let mayLoad = 1, neverHasSideEffects = 1 in {
1196 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1197 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1199 []>, OpSize; // AX,DX = AX*[mem16]
1201 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1202 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1204 []>; // EAX,EDX = EAX*[mem32]
1207 let neverHasSideEffects = 1 in {
1208 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1209 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1211 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1212 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1213 OpSize; // AX,DX = AX*GR16
1214 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1215 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1216 // EAX,EDX = EAX*GR32
1217 let mayLoad = 1 in {
1218 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1219 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1220 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1221 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1222 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1223 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1224 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1225 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1226 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1228 } // neverHasSideEffects
1230 // unsigned division/remainder
1231 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1232 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1233 "div{b}\t$src", []>;
1234 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1235 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1236 "div{w}\t$src", []>, OpSize;
1237 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1238 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1239 "div{l}\t$src", []>;
1240 let mayLoad = 1 in {
1241 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1242 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1243 "div{b}\t$src", []>;
1244 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1245 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1246 "div{w}\t$src", []>, OpSize;
1247 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1248 // EDX:EAX/[mem32] = EAX,EDX
1249 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
1250 "div{l}\t$src", []>;
1253 // Signed division/remainder.
1254 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1255 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1256 "idiv{b}\t$src", []>;
1257 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1258 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1259 "idiv{w}\t$src", []>, OpSize;
1260 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1261 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1262 "idiv{l}\t$src", []>;
1263 let mayLoad = 1, mayLoad = 1 in {
1264 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1265 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1266 "idiv{b}\t$src", []>;
1267 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1268 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1269 "idiv{w}\t$src", []>, OpSize;
1270 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1271 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1272 // EDX:EAX/[mem32] = EAX,EDX
1273 "idiv{l}\t$src", []>;
1276 //===----------------------------------------------------------------------===//
1277 // Two address Instructions.
1279 let Constraints = "$src1 = $dst" in {
1281 // Conditional moves
1282 let Uses = [EFLAGS] in {
1284 let Predicates = [HasCMov] in {
1285 let isCommutable = 1 in {
1286 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1287 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1288 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1289 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1290 X86_COND_B, EFLAGS))]>,
1292 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1293 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1294 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1295 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1296 X86_COND_B, EFLAGS))]>,
1298 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1299 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1300 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1301 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1302 X86_COND_AE, EFLAGS))]>,
1304 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1305 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1306 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1307 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1308 X86_COND_AE, EFLAGS))]>,
1310 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1311 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1312 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1313 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1314 X86_COND_E, EFLAGS))]>,
1316 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1317 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1318 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1319 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1320 X86_COND_E, EFLAGS))]>,
1322 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1323 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1324 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1325 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1326 X86_COND_NE, EFLAGS))]>,
1328 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1329 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1330 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1331 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1332 X86_COND_NE, EFLAGS))]>,
1334 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1335 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1336 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1337 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1338 X86_COND_BE, EFLAGS))]>,
1340 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1341 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1342 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1343 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1344 X86_COND_BE, EFLAGS))]>,
1346 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1347 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1348 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1349 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1350 X86_COND_A, EFLAGS))]>,
1352 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1353 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1354 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1355 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1356 X86_COND_A, EFLAGS))]>,
1358 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1359 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1360 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1361 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1362 X86_COND_L, EFLAGS))]>,
1364 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1365 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1366 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1367 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1368 X86_COND_L, EFLAGS))]>,
1370 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1371 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1372 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1373 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1374 X86_COND_GE, EFLAGS))]>,
1376 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1377 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1378 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1379 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1380 X86_COND_GE, EFLAGS))]>,
1382 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1383 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1384 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1385 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1386 X86_COND_LE, EFLAGS))]>,
1388 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1389 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1390 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1391 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1392 X86_COND_LE, EFLAGS))]>,
1394 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1395 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1396 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1397 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1398 X86_COND_G, EFLAGS))]>,
1400 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1401 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1402 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1403 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1404 X86_COND_G, EFLAGS))]>,
1406 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1407 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1408 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1409 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1410 X86_COND_S, EFLAGS))]>,
1412 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1413 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1414 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1415 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1416 X86_COND_S, EFLAGS))]>,
1418 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1419 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1420 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1421 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1422 X86_COND_NS, EFLAGS))]>,
1424 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1425 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1426 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1427 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1428 X86_COND_NS, EFLAGS))]>,
1430 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1431 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1432 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1433 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1434 X86_COND_P, EFLAGS))]>,
1436 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1437 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1438 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1439 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1440 X86_COND_P, EFLAGS))]>,
1442 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1443 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1444 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1445 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1446 X86_COND_NP, EFLAGS))]>,
1448 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1449 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1450 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1451 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1452 X86_COND_NP, EFLAGS))]>,
1454 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1455 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1456 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1457 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1458 X86_COND_O, EFLAGS))]>,
1460 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1461 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1462 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1463 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1464 X86_COND_O, EFLAGS))]>,
1466 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1467 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1468 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1469 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1470 X86_COND_NO, EFLAGS))]>,
1472 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1473 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1474 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1475 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1476 X86_COND_NO, EFLAGS))]>,
1478 } // isCommutable = 1
1480 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1481 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1482 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1483 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1484 X86_COND_B, EFLAGS))]>,
1486 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1487 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1488 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1489 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1490 X86_COND_B, EFLAGS))]>,
1492 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1493 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1494 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1495 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1496 X86_COND_AE, EFLAGS))]>,
1498 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1499 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1500 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1501 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1502 X86_COND_AE, EFLAGS))]>,
1504 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1505 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1506 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1507 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1508 X86_COND_E, EFLAGS))]>,
1510 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1511 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1512 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1513 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1514 X86_COND_E, EFLAGS))]>,
1516 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1517 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1518 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1519 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1520 X86_COND_NE, EFLAGS))]>,
1522 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1523 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1524 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1525 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1526 X86_COND_NE, EFLAGS))]>,
1528 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1529 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1530 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1531 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1532 X86_COND_BE, EFLAGS))]>,
1534 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1535 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1536 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1537 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1538 X86_COND_BE, EFLAGS))]>,
1540 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1541 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1542 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1543 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1544 X86_COND_A, EFLAGS))]>,
1546 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1547 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1548 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1549 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1550 X86_COND_A, EFLAGS))]>,
1552 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1553 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1554 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1555 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1556 X86_COND_L, EFLAGS))]>,
1558 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1559 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1560 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1561 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1562 X86_COND_L, EFLAGS))]>,
1564 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1565 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1566 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1567 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1568 X86_COND_GE, EFLAGS))]>,
1570 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1571 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1572 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1573 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1574 X86_COND_GE, EFLAGS))]>,
1576 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1577 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1578 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1579 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1580 X86_COND_LE, EFLAGS))]>,
1582 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1583 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1584 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1585 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1586 X86_COND_LE, EFLAGS))]>,
1588 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1589 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1590 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1591 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1592 X86_COND_G, EFLAGS))]>,
1594 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1595 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1596 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1597 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1598 X86_COND_G, EFLAGS))]>,
1600 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1601 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1602 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1603 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1604 X86_COND_S, EFLAGS))]>,
1606 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1607 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1608 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1609 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1610 X86_COND_S, EFLAGS))]>,
1612 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1613 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1614 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1615 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1616 X86_COND_NS, EFLAGS))]>,
1618 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1619 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1620 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1621 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1622 X86_COND_NS, EFLAGS))]>,
1624 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1625 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1626 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1627 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1628 X86_COND_P, EFLAGS))]>,
1630 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1631 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1632 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1633 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1634 X86_COND_P, EFLAGS))]>,
1636 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1637 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1638 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1639 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1640 X86_COND_NP, EFLAGS))]>,
1642 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1643 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1644 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1645 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1646 X86_COND_NP, EFLAGS))]>,
1648 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1649 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1650 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1651 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1652 X86_COND_O, EFLAGS))]>,
1654 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1655 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1656 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1657 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1658 X86_COND_O, EFLAGS))]>,
1660 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1661 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1662 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1663 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1664 X86_COND_NO, EFLAGS))]>,
1666 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1667 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1668 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1669 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1670 X86_COND_NO, EFLAGS))]>,
1672 } // Predicates = [HasCMov]
1674 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1675 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1676 // however that requires promoting the operands, and can induce additional
1677 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1678 // clobber EFLAGS, because if one of the operands is zero, the expansion
1679 // could involve an xor.
1680 let usesCustomInserter = 1, Constraints = "", Defs = [EFLAGS] in {
1681 def CMOV_GR8 : I<0, Pseudo,
1682 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1683 "#CMOV_GR8 PSEUDO!",
1684 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1685 imm:$cond, EFLAGS))]>;
1687 let Predicates = [NoCMov] in {
1688 def CMOV_GR32 : I<0, Pseudo,
1689 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
1690 "#CMOV_GR32* PSEUDO!",
1692 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
1693 def CMOV_GR16 : I<0, Pseudo,
1694 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
1695 "#CMOV_GR16* PSEUDO!",
1697 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
1698 def CMOV_RFP32 : I<0, Pseudo,
1700 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
1701 "#CMOV_RFP32 PSEUDO!",
1703 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
1705 def CMOV_RFP64 : I<0, Pseudo,
1707 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
1708 "#CMOV_RFP64 PSEUDO!",
1710 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
1712 def CMOV_RFP80 : I<0, Pseudo,
1714 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
1715 "#CMOV_RFP80 PSEUDO!",
1717 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
1719 } // Predicates = [NoCMov]
1720 } // UsesCustomInserter = 1, Constraints = "", Defs = [EFLAGS]
1721 } // Uses = [EFLAGS]
1724 // unary instructions
1725 let CodeSize = 2 in {
1726 let Defs = [EFLAGS] in {
1727 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
1729 [(set GR8:$dst, (ineg GR8:$src1)),
1730 (implicit EFLAGS)]>;
1731 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
1733 [(set GR16:$dst, (ineg GR16:$src1)),
1734 (implicit EFLAGS)]>, OpSize;
1735 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
1737 [(set GR32:$dst, (ineg GR32:$src1)),
1738 (implicit EFLAGS)]>;
1740 let Constraints = "" in {
1741 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
1743 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1744 (implicit EFLAGS)]>;
1745 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
1747 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1748 (implicit EFLAGS)]>, OpSize;
1749 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
1751 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1752 (implicit EFLAGS)]>;
1753 } // Constraints = ""
1754 } // Defs = [EFLAGS]
1756 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1757 let AddedComplexity = 15 in {
1758 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
1760 [(set GR8:$dst, (not GR8:$src1))]>;
1761 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
1763 [(set GR16:$dst, (not GR16:$src1))]>, OpSize;
1764 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
1766 [(set GR32:$dst, (not GR32:$src1))]>;
1768 let Constraints = "" in {
1769 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
1771 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1772 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
1774 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1775 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
1777 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1778 } // Constraints = ""
1781 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1782 let Defs = [EFLAGS] in {
1784 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1786 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>;
1788 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1789 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
1791 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
1792 OpSize, Requires<[In32BitMode]>;
1793 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
1795 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
1796 Requires<[In32BitMode]>;
1798 let Constraints = "", CodeSize = 2 in {
1799 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1800 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1801 (implicit EFLAGS)]>;
1802 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1803 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1804 (implicit EFLAGS)]>,
1805 OpSize, Requires<[In32BitMode]>;
1806 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1807 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1808 (implicit EFLAGS)]>,
1809 Requires<[In32BitMode]>;
1810 } // Constraints = "", CodeSize = 2
1813 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1815 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>;
1816 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1817 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
1819 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
1820 OpSize, Requires<[In32BitMode]>;
1821 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
1823 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
1824 Requires<[In32BitMode]>;
1827 let Constraints = "", CodeSize = 2 in {
1828 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1829 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1830 (implicit EFLAGS)]>;
1831 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1832 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1833 (implicit EFLAGS)]>,
1834 OpSize, Requires<[In32BitMode]>;
1835 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1836 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1837 (implicit EFLAGS)]>,
1838 Requires<[In32BitMode]>;
1839 } // Constraints = "", CodeSize = 2
1840 } // Defs = [EFLAGS]
1842 // Logical operators...
1843 let Defs = [EFLAGS] in {
1844 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1845 def AND8rr : I<0x20, MRMDestReg,
1846 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1847 "and{b}\t{$src2, $dst|$dst, $src2}",
1848 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, GR8:$src2))]>;
1849 def AND16rr : I<0x21, MRMDestReg,
1850 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1851 "and{w}\t{$src2, $dst|$dst, $src2}",
1852 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1853 GR16:$src2))]>, OpSize;
1854 def AND32rr : I<0x21, MRMDestReg,
1855 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1856 "and{l}\t{$src2, $dst|$dst, $src2}",
1857 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1861 // AND instructions with the destination register in REG and the source register
1862 // in R/M. Included for the disassembler.
1863 let isCodeGenOnly = 1 in {
1864 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1865 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1866 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1867 (ins GR16:$src1, GR16:$src2),
1868 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1869 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1870 (ins GR32:$src1, GR32:$src2),
1871 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1874 def AND8rm : I<0x22, MRMSrcMem,
1875 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1876 "and{b}\t{$src2, $dst|$dst, $src2}",
1877 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1878 (loadi8 addr:$src2)))]>;
1879 def AND16rm : I<0x23, MRMSrcMem,
1880 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1881 "and{w}\t{$src2, $dst|$dst, $src2}",
1882 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1883 (loadi16 addr:$src2)))]>,
1885 def AND32rm : I<0x23, MRMSrcMem,
1886 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1887 "and{l}\t{$src2, $dst|$dst, $src2}",
1888 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1889 (loadi32 addr:$src2)))]>;
1891 def AND8ri : Ii8<0x80, MRM4r,
1892 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1893 "and{b}\t{$src2, $dst|$dst, $src2}",
1894 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1896 def AND16ri : Ii16<0x81, MRM4r,
1897 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1898 "and{w}\t{$src2, $dst|$dst, $src2}",
1899 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1900 imm:$src2))]>, OpSize;
1901 def AND32ri : Ii32<0x81, MRM4r,
1902 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1903 "and{l}\t{$src2, $dst|$dst, $src2}",
1904 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1906 def AND16ri8 : Ii8<0x83, MRM4r,
1907 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1908 "and{w}\t{$src2, $dst|$dst, $src2}",
1909 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1910 i16immSExt8:$src2))]>,
1912 def AND32ri8 : Ii8<0x83, MRM4r,
1913 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1914 "and{l}\t{$src2, $dst|$dst, $src2}",
1915 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1916 i32immSExt8:$src2))]>;
1918 let Constraints = "" in {
1919 def AND8mr : I<0x20, MRMDestMem,
1920 (outs), (ins i8mem :$dst, GR8 :$src),
1921 "and{b}\t{$src, $dst|$dst, $src}",
1922 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1923 (implicit EFLAGS)]>;
1924 def AND16mr : I<0x21, MRMDestMem,
1925 (outs), (ins i16mem:$dst, GR16:$src),
1926 "and{w}\t{$src, $dst|$dst, $src}",
1927 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1928 (implicit EFLAGS)]>,
1930 def AND32mr : I<0x21, MRMDestMem,
1931 (outs), (ins i32mem:$dst, GR32:$src),
1932 "and{l}\t{$src, $dst|$dst, $src}",
1933 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1934 (implicit EFLAGS)]>;
1935 def AND8mi : Ii8<0x80, MRM4m,
1936 (outs), (ins i8mem :$dst, i8imm :$src),
1937 "and{b}\t{$src, $dst|$dst, $src}",
1938 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1939 (implicit EFLAGS)]>;
1940 def AND16mi : Ii16<0x81, MRM4m,
1941 (outs), (ins i16mem:$dst, i16imm:$src),
1942 "and{w}\t{$src, $dst|$dst, $src}",
1943 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1944 (implicit EFLAGS)]>,
1946 def AND32mi : Ii32<0x81, MRM4m,
1947 (outs), (ins i32mem:$dst, i32imm:$src),
1948 "and{l}\t{$src, $dst|$dst, $src}",
1949 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1950 (implicit EFLAGS)]>;
1951 def AND16mi8 : Ii8<0x83, MRM4m,
1952 (outs), (ins i16mem:$dst, i16i8imm :$src),
1953 "and{w}\t{$src, $dst|$dst, $src}",
1954 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1955 (implicit EFLAGS)]>,
1957 def AND32mi8 : Ii8<0x83, MRM4m,
1958 (outs), (ins i32mem:$dst, i32i8imm :$src),
1959 "and{l}\t{$src, $dst|$dst, $src}",
1960 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1961 (implicit EFLAGS)]>;
1963 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1964 "and{b}\t{$src, %al|%al, $src}", []>;
1965 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1966 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1967 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1968 "and{l}\t{$src, %eax|%eax, $src}", []>;
1970 } // Constraints = ""
1973 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1974 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1975 (ins GR8 :$src1, GR8 :$src2),
1976 "or{b}\t{$src2, $dst|$dst, $src2}",
1977 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
1978 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1979 (ins GR16:$src1, GR16:$src2),
1980 "or{w}\t{$src2, $dst|$dst, $src2}",
1981 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
1983 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1984 (ins GR32:$src1, GR32:$src2),
1985 "or{l}\t{$src2, $dst|$dst, $src2}",
1986 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
1989 // OR instructions with the destination register in REG and the source register
1990 // in R/M. Included for the disassembler.
1991 let isCodeGenOnly = 1 in {
1992 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1993 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1994 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1995 (ins GR16:$src1, GR16:$src2),
1996 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1997 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1998 (ins GR32:$src1, GR32:$src2),
1999 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
2002 def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
2003 (ins GR8 :$src1, i8mem :$src2),
2004 "or{b}\t{$src2, $dst|$dst, $src2}",
2005 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
2006 (load addr:$src2)))]>;
2007 def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
2008 (ins GR16:$src1, i16mem:$src2),
2009 "or{w}\t{$src2, $dst|$dst, $src2}",
2010 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
2011 (load addr:$src2)))]>,
2013 def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
2014 (ins GR32:$src1, i32mem:$src2),
2015 "or{l}\t{$src2, $dst|$dst, $src2}",
2016 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
2017 (load addr:$src2)))]>;
2019 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
2020 (ins GR8 :$src1, i8imm:$src2),
2021 "or{b}\t{$src2, $dst|$dst, $src2}",
2022 [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
2023 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
2024 (ins GR16:$src1, i16imm:$src2),
2025 "or{w}\t{$src2, $dst|$dst, $src2}",
2026 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
2027 imm:$src2))]>, OpSize;
2028 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
2029 (ins GR32:$src1, i32imm:$src2),
2030 "or{l}\t{$src2, $dst|$dst, $src2}",
2031 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
2034 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
2035 (ins GR16:$src1, i16i8imm:$src2),
2036 "or{w}\t{$src2, $dst|$dst, $src2}",
2037 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
2038 i16immSExt8:$src2))]>, OpSize;
2039 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
2040 (ins GR32:$src1, i32i8imm:$src2),
2041 "or{l}\t{$src2, $dst|$dst, $src2}",
2042 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
2043 i32immSExt8:$src2))]>;
2044 let Constraints = "" in {
2045 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
2046 "or{b}\t{$src, $dst|$dst, $src}",
2047 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
2048 (implicit EFLAGS)]>;
2049 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
2050 "or{w}\t{$src, $dst|$dst, $src}",
2051 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
2052 (implicit EFLAGS)]>, OpSize;
2053 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2054 "or{l}\t{$src, $dst|$dst, $src}",
2055 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
2056 (implicit EFLAGS)]>;
2057 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2058 "or{b}\t{$src, $dst|$dst, $src}",
2059 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
2060 (implicit EFLAGS)]>;
2061 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
2062 "or{w}\t{$src, $dst|$dst, $src}",
2063 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
2064 (implicit EFLAGS)]>,
2066 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
2067 "or{l}\t{$src, $dst|$dst, $src}",
2068 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
2069 (implicit EFLAGS)]>;
2070 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
2071 "or{w}\t{$src, $dst|$dst, $src}",
2072 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
2073 (implicit EFLAGS)]>,
2075 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
2076 "or{l}\t{$src, $dst|$dst, $src}",
2077 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
2078 (implicit EFLAGS)]>;
2080 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
2081 "or{b}\t{$src, %al|%al, $src}", []>;
2082 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
2083 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2084 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
2085 "or{l}\t{$src, %eax|%eax, $src}", []>;
2086 } // Constraints = ""
2089 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
2090 def XOR8rr : I<0x30, MRMDestReg,
2091 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
2092 "xor{b}\t{$src2, $dst|$dst, $src2}",
2093 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2095 def XOR16rr : I<0x31, MRMDestReg,
2096 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2097 "xor{w}\t{$src2, $dst|$dst, $src2}",
2098 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2099 GR16:$src2))]>, OpSize;
2100 def XOR32rr : I<0x31, MRMDestReg,
2101 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2102 "xor{l}\t{$src2, $dst|$dst, $src2}",
2103 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2105 } // isCommutable = 1
2107 // XOR instructions with the destination register in REG and the source register
2108 // in R/M. Included for the disassembler.
2109 let isCodeGenOnly = 1 in {
2110 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2111 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
2112 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
2113 (ins GR16:$src1, GR16:$src2),
2114 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2115 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
2116 (ins GR32:$src1, GR32:$src2),
2117 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
2120 def XOR8rm : I<0x32, MRMSrcMem,
2121 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
2122 "xor{b}\t{$src2, $dst|$dst, $src2}",
2123 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2124 (load addr:$src2)))]>;
2125 def XOR16rm : I<0x33, MRMSrcMem,
2126 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2127 "xor{w}\t{$src2, $dst|$dst, $src2}",
2128 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2129 (load addr:$src2)))]>,
2131 def XOR32rm : I<0x33, MRMSrcMem,
2132 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2133 "xor{l}\t{$src2, $dst|$dst, $src2}",
2134 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2135 (load addr:$src2)))]>;
2137 def XOR8ri : Ii8<0x80, MRM6r,
2138 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2139 "xor{b}\t{$src2, $dst|$dst, $src2}",
2140 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
2141 def XOR16ri : Ii16<0x81, MRM6r,
2142 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2143 "xor{w}\t{$src2, $dst|$dst, $src2}",
2144 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2145 imm:$src2))]>, OpSize;
2146 def XOR32ri : Ii32<0x81, MRM6r,
2147 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2148 "xor{l}\t{$src2, $dst|$dst, $src2}",
2149 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2151 def XOR16ri8 : Ii8<0x83, MRM6r,
2152 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2153 "xor{w}\t{$src2, $dst|$dst, $src2}",
2154 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2155 i16immSExt8:$src2))]>,
2157 def XOR32ri8 : Ii8<0x83, MRM6r,
2158 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2159 "xor{l}\t{$src2, $dst|$dst, $src2}",
2160 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2161 i32immSExt8:$src2))]>;
2163 let Constraints = "" in {
2164 def XOR8mr : I<0x30, MRMDestMem,
2165 (outs), (ins i8mem :$dst, GR8 :$src),
2166 "xor{b}\t{$src, $dst|$dst, $src}",
2167 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
2168 (implicit EFLAGS)]>;
2169 def XOR16mr : I<0x31, MRMDestMem,
2170 (outs), (ins i16mem:$dst, GR16:$src),
2171 "xor{w}\t{$src, $dst|$dst, $src}",
2172 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
2173 (implicit EFLAGS)]>,
2175 def XOR32mr : I<0x31, MRMDestMem,
2176 (outs), (ins i32mem:$dst, GR32:$src),
2177 "xor{l}\t{$src, $dst|$dst, $src}",
2178 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
2179 (implicit EFLAGS)]>;
2180 def XOR8mi : Ii8<0x80, MRM6m,
2181 (outs), (ins i8mem :$dst, i8imm :$src),
2182 "xor{b}\t{$src, $dst|$dst, $src}",
2183 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
2184 (implicit EFLAGS)]>;
2185 def XOR16mi : Ii16<0x81, MRM6m,
2186 (outs), (ins i16mem:$dst, i16imm:$src),
2187 "xor{w}\t{$src, $dst|$dst, $src}",
2188 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
2189 (implicit EFLAGS)]>,
2191 def XOR32mi : Ii32<0x81, MRM6m,
2192 (outs), (ins i32mem:$dst, i32imm:$src),
2193 "xor{l}\t{$src, $dst|$dst, $src}",
2194 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
2195 (implicit EFLAGS)]>;
2196 def XOR16mi8 : Ii8<0x83, MRM6m,
2197 (outs), (ins i16mem:$dst, i16i8imm :$src),
2198 "xor{w}\t{$src, $dst|$dst, $src}",
2199 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
2200 (implicit EFLAGS)]>,
2202 def XOR32mi8 : Ii8<0x83, MRM6m,
2203 (outs), (ins i32mem:$dst, i32i8imm :$src),
2204 "xor{l}\t{$src, $dst|$dst, $src}",
2205 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
2206 (implicit EFLAGS)]>;
2208 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
2209 "xor{b}\t{$src, %al|%al, $src}", []>;
2210 def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
2211 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2212 def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
2213 "xor{l}\t{$src, %eax|%eax, $src}", []>;
2214 } // Constraints = ""
2215 } // Defs = [EFLAGS]
2217 // Shift instructions
2218 let Defs = [EFLAGS] in {
2219 let Uses = [CL] in {
2220 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
2221 "shl{b}\t{%cl, $dst|$dst, CL}",
2222 [(set GR8:$dst, (shl GR8:$src1, CL))]>;
2223 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2224 "shl{w}\t{%cl, $dst|$dst, CL}",
2225 [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize;
2226 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2227 "shl{l}\t{%cl, $dst|$dst, CL}",
2228 [(set GR32:$dst, (shl GR32:$src1, CL))]>;
2231 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2232 "shl{b}\t{$src2, $dst|$dst, $src2}",
2233 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
2235 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2236 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2237 "shl{w}\t{$src2, $dst|$dst, $src2}",
2238 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2239 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2240 "shl{l}\t{$src2, $dst|$dst, $src2}",
2241 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
2243 // NOTE: We don't include patterns for shifts of a register by one, because
2244 // 'add reg,reg' is cheaper.
2246 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
2247 "shl{b}\t$dst", []>;
2248 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2249 "shl{w}\t$dst", []>, OpSize;
2250 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2251 "shl{l}\t$dst", []>;
2253 } // isConvertibleToThreeAddress = 1
2255 let Constraints = "" in {
2256 let Uses = [CL] in {
2257 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2258 "shl{b}\t{%cl, $dst|$dst, CL}",
2259 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2260 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2261 "shl{w}\t{%cl, $dst|$dst, CL}",
2262 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2263 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2264 "shl{l}\t{%cl, $dst|$dst, CL}",
2265 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2267 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2268 "shl{b}\t{$src, $dst|$dst, $src}",
2269 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2270 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2271 "shl{w}\t{$src, $dst|$dst, $src}",
2272 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2274 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2275 "shl{l}\t{$src, $dst|$dst, $src}",
2276 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2279 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2281 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2282 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2284 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2286 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2288 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2289 } // Constraints = ""
2291 let Uses = [CL] in {
2292 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
2293 "shr{b}\t{%cl, $dst|$dst, CL}",
2294 [(set GR8:$dst, (srl GR8:$src1, CL))]>;
2295 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2296 "shr{w}\t{%cl, $dst|$dst, CL}",
2297 [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize;
2298 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2299 "shr{l}\t{%cl, $dst|$dst, CL}",
2300 [(set GR32:$dst, (srl GR32:$src1, CL))]>;
2303 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2304 "shr{b}\t{$src2, $dst|$dst, $src2}",
2305 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2306 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2307 "shr{w}\t{$src2, $dst|$dst, $src2}",
2308 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2309 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2310 "shr{l}\t{$src2, $dst|$dst, $src2}",
2311 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2314 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2316 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2317 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2319 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2320 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2322 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2324 let Constraints = "" in {
2325 let Uses = [CL] in {
2326 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2327 "shr{b}\t{%cl, $dst|$dst, CL}",
2328 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2329 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2330 "shr{w}\t{%cl, $dst|$dst, CL}",
2331 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2333 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2334 "shr{l}\t{%cl, $dst|$dst, CL}",
2335 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2337 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2338 "shr{b}\t{$src, $dst|$dst, $src}",
2339 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2340 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2341 "shr{w}\t{$src, $dst|$dst, $src}",
2342 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2344 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2345 "shr{l}\t{$src, $dst|$dst, $src}",
2346 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2349 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2351 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2352 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2354 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2355 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2357 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2358 } // Constraints = ""
2360 let Uses = [CL] in {
2361 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2362 "sar{b}\t{%cl, $dst|$dst, CL}",
2363 [(set GR8:$dst, (sra GR8:$src1, CL))]>;
2364 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2365 "sar{w}\t{%cl, $dst|$dst, CL}",
2366 [(set GR16:$dst, (sra GR16:$src1, CL))]>, OpSize;
2367 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2368 "sar{l}\t{%cl, $dst|$dst, CL}",
2369 [(set GR32:$dst, (sra GR32:$src1, CL))]>;
2372 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2373 "sar{b}\t{$src2, $dst|$dst, $src2}",
2374 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2375 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2376 "sar{w}\t{$src2, $dst|$dst, $src2}",
2377 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2379 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2380 "sar{l}\t{$src2, $dst|$dst, $src2}",
2381 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2384 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2386 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2387 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2389 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2390 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2392 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2394 let Constraints = "" in {
2395 let Uses = [CL] in {
2396 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2397 "sar{b}\t{%cl, $dst|$dst, CL}",
2398 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2399 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2400 "sar{w}\t{%cl, $dst|$dst, CL}",
2401 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2402 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2403 "sar{l}\t{%cl, $dst|$dst, CL}",
2404 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2406 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2407 "sar{b}\t{$src, $dst|$dst, $src}",
2408 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2409 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2410 "sar{w}\t{$src, $dst|$dst, $src}",
2411 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2413 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2414 "sar{l}\t{$src, $dst|$dst, $src}",
2415 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2418 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2420 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2421 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2423 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2425 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2427 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2428 } // Constraints = ""
2430 // Rotate instructions
2432 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
2433 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2434 let Uses = [CL] in {
2435 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
2436 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2438 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
2439 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2441 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
2442 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2443 let Uses = [CL] in {
2444 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
2445 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2447 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
2448 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2450 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
2451 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2452 let Uses = [CL] in {
2453 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
2454 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2456 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
2457 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2459 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
2460 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2461 let Uses = [CL] in {
2462 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
2463 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2465 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
2466 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2468 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
2469 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2470 let Uses = [CL] in {
2471 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
2472 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2474 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
2475 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2477 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
2478 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2479 let Uses = [CL] in {
2480 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
2481 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2483 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
2484 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2486 let Constraints = "" in {
2487 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
2488 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2489 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2490 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2491 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
2492 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2493 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2494 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2495 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
2496 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2497 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2498 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2499 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
2500 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2501 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2502 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2503 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
2504 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2505 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2506 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2507 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
2508 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2509 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2510 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2512 let Uses = [CL] in {
2513 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
2514 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2515 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
2516 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2517 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
2518 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2519 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
2520 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2521 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
2522 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2523 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
2524 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2526 } // Constraints = ""
2528 // FIXME: provide shorter instructions when imm8 == 1
2529 let Uses = [CL] in {
2530 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2531 "rol{b}\t{%cl, $dst|$dst, CL}",
2532 [(set GR8:$dst, (rotl GR8:$src1, CL))]>;
2533 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2534 "rol{w}\t{%cl, $dst|$dst, CL}",
2535 [(set GR16:$dst, (rotl GR16:$src1, CL))]>, OpSize;
2536 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2537 "rol{l}\t{%cl, $dst|$dst, CL}",
2538 [(set GR32:$dst, (rotl GR32:$src1, CL))]>;
2541 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2542 "rol{b}\t{$src2, $dst|$dst, $src2}",
2543 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2544 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2545 "rol{w}\t{$src2, $dst|$dst, $src2}",
2546 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2548 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2549 "rol{l}\t{$src2, $dst|$dst, $src2}",
2550 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2553 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2555 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2556 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2558 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2559 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2561 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2563 let Constraints = "" in {
2564 let Uses = [CL] in {
2565 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2566 "rol{b}\t{%cl, $dst|$dst, CL}",
2567 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2568 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2569 "rol{w}\t{%cl, $dst|$dst, CL}",
2570 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2571 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2572 "rol{l}\t{%cl, $dst|$dst, CL}",
2573 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2575 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2576 "rol{b}\t{$src, $dst|$dst, $src}",
2577 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2578 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2579 "rol{w}\t{$src, $dst|$dst, $src}",
2580 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2582 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2583 "rol{l}\t{$src, $dst|$dst, $src}",
2584 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2587 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2589 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2590 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2592 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2594 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2596 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2597 } // Constraints = ""
2599 let Uses = [CL] in {
2600 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2601 "ror{b}\t{%cl, $dst|$dst, CL}",
2602 [(set GR8:$dst, (rotr GR8:$src1, CL))]>;
2603 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2604 "ror{w}\t{%cl, $dst|$dst, CL}",
2605 [(set GR16:$dst, (rotr GR16:$src1, CL))]>, OpSize;
2606 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2607 "ror{l}\t{%cl, $dst|$dst, CL}",
2608 [(set GR32:$dst, (rotr GR32:$src1, CL))]>;
2611 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2612 "ror{b}\t{$src2, $dst|$dst, $src2}",
2613 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2614 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2615 "ror{w}\t{$src2, $dst|$dst, $src2}",
2616 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2618 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2619 "ror{l}\t{$src2, $dst|$dst, $src2}",
2620 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2623 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2625 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2626 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2628 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2629 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2631 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2633 let Constraints = "" in {
2634 let Uses = [CL] in {
2635 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2636 "ror{b}\t{%cl, $dst|$dst, CL}",
2637 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2638 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2639 "ror{w}\t{%cl, $dst|$dst, CL}",
2640 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2641 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2642 "ror{l}\t{%cl, $dst|$dst, CL}",
2643 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2645 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2646 "ror{b}\t{$src, $dst|$dst, $src}",
2647 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2648 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2649 "ror{w}\t{$src, $dst|$dst, $src}",
2650 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2652 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2653 "ror{l}\t{$src, $dst|$dst, $src}",
2654 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2657 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2659 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2660 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2662 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2664 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2666 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2667 } // Constraints = ""
2670 // Double shift instructions (generalizations of rotate)
2671 let Uses = [CL] in {
2672 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2673 (ins GR32:$src1, GR32:$src2),
2674 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2675 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2676 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2677 (ins GR32:$src1, GR32:$src2),
2678 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2679 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2680 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2681 (ins GR16:$src1, GR16:$src2),
2682 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2683 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2685 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2686 (ins GR16:$src1, GR16:$src2),
2687 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2688 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2692 let isCommutable = 1 in { // These instructions commute to each other.
2693 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2695 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2696 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2697 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2700 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2702 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2703 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2704 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2707 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2709 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2710 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2711 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2714 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2716 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2717 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2718 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2723 let Constraints = "" in {
2724 let Uses = [CL] in {
2725 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2726 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2727 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2729 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2730 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2731 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2734 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2735 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2736 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2737 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2738 (i8 imm:$src3)), addr:$dst)]>,
2740 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2741 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2742 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2743 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2744 (i8 imm:$src3)), addr:$dst)]>,
2747 let Uses = [CL] in {
2748 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2749 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2750 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2751 addr:$dst)]>, TB, OpSize;
2752 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2753 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2754 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2755 addr:$dst)]>, TB, OpSize;
2757 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2758 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2759 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2760 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2761 (i8 imm:$src3)), addr:$dst)]>,
2763 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2764 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2765 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2766 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2767 (i8 imm:$src3)), addr:$dst)]>,
2769 } // Constraints = ""
2770 } // Defs = [EFLAGS]
2774 let Defs = [EFLAGS] in {
2775 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2776 // Register-Register Addition
2777 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2778 (ins GR8 :$src1, GR8 :$src2),
2779 "add{b}\t{$src2, $dst|$dst, $src2}",
2780 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
2782 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2783 // Register-Register Addition
2784 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2785 (ins GR16:$src1, GR16:$src2),
2786 "add{w}\t{$src2, $dst|$dst, $src2}",
2787 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2788 GR16:$src2))]>, OpSize;
2789 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2790 (ins GR32:$src1, GR32:$src2),
2791 "add{l}\t{$src2, $dst|$dst, $src2}",
2792 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2794 } // end isConvertibleToThreeAddress
2795 } // end isCommutable
2797 // These are alternate spellings for use by the disassembler, we mark them as
2798 // code gen only to ensure they aren't matched by the assembler.
2799 let isCodeGenOnly = 1 in {
2800 def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2801 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2802 def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2803 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2804 def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR32:$dst),(ins GR32:$src1, GR32:$src2),
2805 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2808 // Register-Memory Addition
2809 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2810 (ins GR8 :$src1, i8mem :$src2),
2811 "add{b}\t{$src2, $dst|$dst, $src2}",
2812 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
2813 (load addr:$src2)))]>;
2814 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2815 (ins GR16:$src1, i16mem:$src2),
2816 "add{w}\t{$src2, $dst|$dst, $src2}",
2817 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2818 (load addr:$src2)))]>, OpSize;
2819 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2820 (ins GR32:$src1, i32mem:$src2),
2821 "add{l}\t{$src2, $dst|$dst, $src2}",
2822 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2823 (load addr:$src2)))]>;
2825 // Register-Integer Addition
2826 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2827 "add{b}\t{$src2, $dst|$dst, $src2}",
2828 [(set GR8:$dst, EFLAGS,
2829 (X86add_flag GR8:$src1, imm:$src2))]>;
2831 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2832 // Register-Integer Addition
2833 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2834 (ins GR16:$src1, i16imm:$src2),
2835 "add{w}\t{$src2, $dst|$dst, $src2}",
2836 [(set GR16:$dst, EFLAGS,
2837 (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
2838 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2839 (ins GR32:$src1, i32imm:$src2),
2840 "add{l}\t{$src2, $dst|$dst, $src2}",
2841 [(set GR32:$dst, EFLAGS,
2842 (X86add_flag GR32:$src1, imm:$src2))]>;
2843 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2844 (ins GR16:$src1, i16i8imm:$src2),
2845 "add{w}\t{$src2, $dst|$dst, $src2}",
2846 [(set GR16:$dst, EFLAGS,
2847 (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2848 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2849 (ins GR32:$src1, i32i8imm:$src2),
2850 "add{l}\t{$src2, $dst|$dst, $src2}",
2851 [(set GR32:$dst, EFLAGS,
2852 (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
2855 let Constraints = "" in {
2856 // Memory-Register Addition
2857 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2858 "add{b}\t{$src2, $dst|$dst, $src2}",
2859 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2860 (implicit EFLAGS)]>;
2861 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2862 "add{w}\t{$src2, $dst|$dst, $src2}",
2863 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2864 (implicit EFLAGS)]>, OpSize;
2865 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2866 "add{l}\t{$src2, $dst|$dst, $src2}",
2867 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2868 (implicit EFLAGS)]>;
2869 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2870 "add{b}\t{$src2, $dst|$dst, $src2}",
2871 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2872 (implicit EFLAGS)]>;
2873 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2874 "add{w}\t{$src2, $dst|$dst, $src2}",
2875 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2876 (implicit EFLAGS)]>, OpSize;
2877 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2878 "add{l}\t{$src2, $dst|$dst, $src2}",
2879 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2880 (implicit EFLAGS)]>;
2881 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2882 "add{w}\t{$src2, $dst|$dst, $src2}",
2883 [(store (add (load addr:$dst), i16immSExt8:$src2),
2885 (implicit EFLAGS)]>, OpSize;
2886 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2887 "add{l}\t{$src2, $dst|$dst, $src2}",
2888 [(store (add (load addr:$dst), i32immSExt8:$src2),
2890 (implicit EFLAGS)]>;
2893 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2894 "add{b}\t{$src, %al|%al, $src}", []>;
2895 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2896 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2897 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2898 "add{l}\t{$src, %eax|%eax, $src}", []>;
2899 } // Constraints = ""
2901 let Uses = [EFLAGS] in {
2902 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2903 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2904 "adc{b}\t{$src2, $dst|$dst, $src2}",
2905 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2906 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2907 (ins GR16:$src1, GR16:$src2),
2908 "adc{w}\t{$src2, $dst|$dst, $src2}",
2909 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2910 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2911 (ins GR32:$src1, GR32:$src2),
2912 "adc{l}\t{$src2, $dst|$dst, $src2}",
2913 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2916 let isCodeGenOnly = 1 in {
2917 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2918 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2919 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2920 (ins GR16:$src1, GR16:$src2),
2921 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2922 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2923 (ins GR32:$src1, GR32:$src2),
2924 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2927 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2928 (ins GR8:$src1, i8mem:$src2),
2929 "adc{b}\t{$src2, $dst|$dst, $src2}",
2930 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2931 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2932 (ins GR16:$src1, i16mem:$src2),
2933 "adc{w}\t{$src2, $dst|$dst, $src2}",
2934 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2936 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2937 (ins GR32:$src1, i32mem:$src2),
2938 "adc{l}\t{$src2, $dst|$dst, $src2}",
2939 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2940 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2941 "adc{b}\t{$src2, $dst|$dst, $src2}",
2942 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2943 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2944 (ins GR16:$src1, i16imm:$src2),
2945 "adc{w}\t{$src2, $dst|$dst, $src2}",
2946 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2947 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2948 (ins GR16:$src1, i16i8imm:$src2),
2949 "adc{w}\t{$src2, $dst|$dst, $src2}",
2950 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2952 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2953 (ins GR32:$src1, i32imm:$src2),
2954 "adc{l}\t{$src2, $dst|$dst, $src2}",
2955 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2956 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2957 (ins GR32:$src1, i32i8imm:$src2),
2958 "adc{l}\t{$src2, $dst|$dst, $src2}",
2959 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2961 let Constraints = "" in {
2962 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2963 "adc{b}\t{$src2, $dst|$dst, $src2}",
2964 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2965 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2966 "adc{w}\t{$src2, $dst|$dst, $src2}",
2967 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2969 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2970 "adc{l}\t{$src2, $dst|$dst, $src2}",
2971 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2972 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2973 "adc{b}\t{$src2, $dst|$dst, $src2}",
2974 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2975 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2976 "adc{w}\t{$src2, $dst|$dst, $src2}",
2977 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2979 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2980 "adc{w}\t{$src2, $dst|$dst, $src2}",
2981 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2983 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2984 "adc{l}\t{$src2, $dst|$dst, $src2}",
2985 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2986 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2987 "adc{l}\t{$src2, $dst|$dst, $src2}",
2988 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2990 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2991 "adc{b}\t{$src, %al|%al, $src}", []>;
2992 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2993 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2994 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2995 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2996 } // Constraints = ""
2997 } // Uses = [EFLAGS]
2999 // Register-Register Subtraction
3000 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3001 "sub{b}\t{$src2, $dst|$dst, $src2}",
3002 [(set GR8:$dst, EFLAGS,
3003 (X86sub_flag GR8:$src1, GR8:$src2))]>;
3004 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3005 "sub{w}\t{$src2, $dst|$dst, $src2}",
3006 [(set GR16:$dst, EFLAGS,
3007 (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
3008 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3009 "sub{l}\t{$src2, $dst|$dst, $src2}",
3010 [(set GR32:$dst, EFLAGS,
3011 (X86sub_flag GR32:$src1, GR32:$src2))]>;
3013 let isCodeGenOnly = 1 in {
3014 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3015 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
3016 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
3017 (ins GR16:$src1, GR16:$src2),
3018 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3019 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
3020 (ins GR32:$src1, GR32:$src2),
3021 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
3024 // Register-Memory Subtraction
3025 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
3026 (ins GR8 :$src1, i8mem :$src2),
3027 "sub{b}\t{$src2, $dst|$dst, $src2}",
3028 [(set GR8:$dst, EFLAGS,
3029 (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
3030 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
3031 (ins GR16:$src1, i16mem:$src2),
3032 "sub{w}\t{$src2, $dst|$dst, $src2}",
3033 [(set GR16:$dst, EFLAGS,
3034 (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
3035 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
3036 (ins GR32:$src1, i32mem:$src2),
3037 "sub{l}\t{$src2, $dst|$dst, $src2}",
3038 [(set GR32:$dst, EFLAGS,
3039 (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
3041 // Register-Integer Subtraction
3042 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
3043 (ins GR8:$src1, i8imm:$src2),
3044 "sub{b}\t{$src2, $dst|$dst, $src2}",
3045 [(set GR8:$dst, EFLAGS,
3046 (X86sub_flag GR8:$src1, imm:$src2))]>;
3047 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
3048 (ins GR16:$src1, i16imm:$src2),
3049 "sub{w}\t{$src2, $dst|$dst, $src2}",
3050 [(set GR16:$dst, EFLAGS,
3051 (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
3052 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
3053 (ins GR32:$src1, i32imm:$src2),
3054 "sub{l}\t{$src2, $dst|$dst, $src2}",
3055 [(set GR32:$dst, EFLAGS,
3056 (X86sub_flag GR32:$src1, imm:$src2))]>;
3057 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
3058 (ins GR16:$src1, i16i8imm:$src2),
3059 "sub{w}\t{$src2, $dst|$dst, $src2}",
3060 [(set GR16:$dst, EFLAGS,
3061 (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
3062 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
3063 (ins GR32:$src1, i32i8imm:$src2),
3064 "sub{l}\t{$src2, $dst|$dst, $src2}",
3065 [(set GR32:$dst, EFLAGS,
3066 (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
3068 let Constraints = "" in {
3069 // Memory-Register Subtraction
3070 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3071 "sub{b}\t{$src2, $dst|$dst, $src2}",
3072 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
3073 (implicit EFLAGS)]>;
3074 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3075 "sub{w}\t{$src2, $dst|$dst, $src2}",
3076 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
3077 (implicit EFLAGS)]>, OpSize;
3078 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3079 "sub{l}\t{$src2, $dst|$dst, $src2}",
3080 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
3081 (implicit EFLAGS)]>;
3083 // Memory-Integer Subtraction
3084 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3085 "sub{b}\t{$src2, $dst|$dst, $src2}",
3086 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
3087 (implicit EFLAGS)]>;
3088 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3089 "sub{w}\t{$src2, $dst|$dst, $src2}",
3090 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
3091 (implicit EFLAGS)]>, OpSize;
3092 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3093 "sub{l}\t{$src2, $dst|$dst, $src2}",
3094 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
3095 (implicit EFLAGS)]>;
3096 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3097 "sub{w}\t{$src2, $dst|$dst, $src2}",
3098 [(store (sub (load addr:$dst), i16immSExt8:$src2),
3100 (implicit EFLAGS)]>, OpSize;
3101 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3102 "sub{l}\t{$src2, $dst|$dst, $src2}",
3103 [(store (sub (load addr:$dst), i32immSExt8:$src2),
3105 (implicit EFLAGS)]>;
3107 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
3108 "sub{b}\t{$src, %al|%al, $src}", []>;
3109 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
3110 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3111 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
3112 "sub{l}\t{$src, %eax|%eax, $src}", []>;
3113 } // Constraints = ""
3115 let Uses = [EFLAGS] in {
3116 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
3117 (ins GR8:$src1, GR8:$src2),
3118 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3119 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
3120 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
3121 (ins GR16:$src1, GR16:$src2),
3122 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3123 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
3124 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
3125 (ins GR32:$src1, GR32:$src2),
3126 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3127 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
3129 let Constraints = "" in {
3130 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3131 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3132 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
3133 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3134 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3135 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
3137 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3138 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3139 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
3140 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
3141 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3142 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
3143 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
3144 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3145 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
3147 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3148 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3149 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
3151 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
3152 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3153 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
3154 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3155 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3156 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
3158 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
3159 "sbb{b}\t{$src, %al|%al, $src}", []>;
3160 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
3161 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3162 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
3163 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
3164 } // Constraints = ""
3166 let isCodeGenOnly = 1 in {
3167 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3168 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
3169 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3170 (ins GR16:$src1, GR16:$src2),
3171 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3172 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3173 (ins GR32:$src1, GR32:$src2),
3174 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3177 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
3178 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3179 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
3180 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
3181 (ins GR16:$src1, i16mem:$src2),
3182 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3183 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
3185 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
3186 (ins GR32:$src1, i32mem:$src2),
3187 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3188 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
3189 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
3190 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3191 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
3192 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
3193 (ins GR16:$src1, i16imm:$src2),
3194 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3195 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
3196 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
3197 (ins GR16:$src1, i16i8imm:$src2),
3198 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3199 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
3201 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
3202 (ins GR32:$src1, i32imm:$src2),
3203 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3204 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
3205 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
3206 (ins GR32:$src1, i32i8imm:$src2),
3207 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3208 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
3209 } // Uses = [EFLAGS]
3210 } // Defs = [EFLAGS]
3212 let Defs = [EFLAGS] in {
3213 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
3214 // Register-Register Signed Integer Multiply
3215 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3216 "imul{w}\t{$src2, $dst|$dst, $src2}",
3217 [(set GR16:$dst, EFLAGS,
3218 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
3219 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3220 "imul{l}\t{$src2, $dst|$dst, $src2}",
3221 [(set GR32:$dst, EFLAGS,
3222 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
3225 // Register-Memory Signed Integer Multiply
3226 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
3227 (ins GR16:$src1, i16mem:$src2),
3228 "imul{w}\t{$src2, $dst|$dst, $src2}",
3229 [(set GR16:$dst, EFLAGS,
3230 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
3232 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3233 (ins GR32:$src1, i32mem:$src2),
3234 "imul{l}\t{$src2, $dst|$dst, $src2}",
3235 [(set GR32:$dst, EFLAGS,
3236 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
3237 } // Defs = [EFLAGS]
3238 } // end Two Address instructions
3240 // Suprisingly enough, these are not two address instructions!
3241 let Defs = [EFLAGS] in {
3242 // Register-Integer Signed Integer Multiply
3243 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
3244 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
3245 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3246 [(set GR16:$dst, EFLAGS,
3247 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
3248 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
3249 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
3250 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3251 [(set GR32:$dst, EFLAGS,
3252 (X86smul_flag GR32:$src1, imm:$src2))]>;
3253 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
3254 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
3255 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3256 [(set GR16:$dst, EFLAGS,
3257 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
3259 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
3260 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
3261 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3262 [(set GR32:$dst, EFLAGS,
3263 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
3265 // Memory-Integer Signed Integer Multiply
3266 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3267 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
3268 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3269 [(set GR16:$dst, EFLAGS,
3270 (X86smul_flag (load addr:$src1), imm:$src2))]>,
3272 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3273 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
3274 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3275 [(set GR32:$dst, EFLAGS,
3276 (X86smul_flag (load addr:$src1), imm:$src2))]>;
3277 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
3278 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
3279 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3280 [(set GR16:$dst, EFLAGS,
3281 (X86smul_flag (load addr:$src1),
3282 i16immSExt8:$src2))]>, OpSize;
3283 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
3284 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
3285 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3286 [(set GR32:$dst, EFLAGS,
3287 (X86smul_flag (load addr:$src1),
3288 i32immSExt8:$src2))]>;
3289 } // Defs = [EFLAGS]
3291 //===----------------------------------------------------------------------===//
3292 // Test instructions are just like AND, except they don't generate a result.
3294 let Defs = [EFLAGS] in {
3295 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
3296 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3297 "test{b}\t{$src2, $src1|$src1, $src2}",
3298 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
3299 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3300 "test{w}\t{$src2, $src1|$src1, $src2}",
3301 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
3304 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3305 "test{l}\t{$src2, $src1|$src1, $src2}",
3306 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
3310 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3311 "test{b}\t{$src, %al|%al, $src}", []>;
3312 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3313 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3314 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3315 "test{l}\t{$src, %eax|%eax, $src}", []>;
3317 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3318 "test{b}\t{$src2, $src1|$src1, $src2}",
3319 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
3321 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3322 "test{w}\t{$src2, $src1|$src1, $src2}",
3323 [(set EFLAGS, (X86cmp (and GR16:$src1,
3324 (loadi16 addr:$src2)), 0))]>, OpSize;
3325 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3326 "test{l}\t{$src2, $src1|$src1, $src2}",
3327 [(set EFLAGS, (X86cmp (and GR32:$src1,
3328 (loadi32 addr:$src2)), 0))]>;
3330 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3331 (outs), (ins GR8:$src1, i8imm:$src2),
3332 "test{b}\t{$src2, $src1|$src1, $src2}",
3333 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
3334 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3335 (outs), (ins GR16:$src1, i16imm:$src2),
3336 "test{w}\t{$src2, $src1|$src1, $src2}",
3337 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
3339 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3340 (outs), (ins GR32:$src1, i32imm:$src2),
3341 "test{l}\t{$src2, $src1|$src1, $src2}",
3342 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
3344 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3345 (outs), (ins i8mem:$src1, i8imm:$src2),
3346 "test{b}\t{$src2, $src1|$src1, $src2}",
3347 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
3349 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3350 (outs), (ins i16mem:$src1, i16imm:$src2),
3351 "test{w}\t{$src2, $src1|$src1, $src2}",
3352 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
3354 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3355 (outs), (ins i32mem:$src1, i32imm:$src2),
3356 "test{l}\t{$src2, $src1|$src1, $src2}",
3357 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
3359 } // Defs = [EFLAGS]
3362 // Condition code ops, incl. set if equal/not equal/...
3363 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3364 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3365 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3366 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3368 let Uses = [EFLAGS] in {
3369 // Use sbb to materialize carry bit.
3370 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3371 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
3372 // However, Pat<> can't replicate the destination reg into the inputs of the
3374 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
3376 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
3377 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3378 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
3379 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3381 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
3382 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3385 def SETEr : I<0x94, MRM0r,
3386 (outs GR8 :$dst), (ins),
3388 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3390 def SETEm : I<0x94, MRM0m,
3391 (outs), (ins i8mem:$dst),
3393 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3396 def SETNEr : I<0x95, MRM0r,
3397 (outs GR8 :$dst), (ins),
3399 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3401 def SETNEm : I<0x95, MRM0m,
3402 (outs), (ins i8mem:$dst),
3404 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3407 def SETLr : I<0x9C, MRM0r,
3408 (outs GR8 :$dst), (ins),
3410 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3411 TB; // GR8 = < signed
3412 def SETLm : I<0x9C, MRM0m,
3413 (outs), (ins i8mem:$dst),
3415 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3416 TB; // [mem8] = < signed
3418 def SETGEr : I<0x9D, MRM0r,
3419 (outs GR8 :$dst), (ins),
3421 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3422 TB; // GR8 = >= signed
3423 def SETGEm : I<0x9D, MRM0m,
3424 (outs), (ins i8mem:$dst),
3426 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3427 TB; // [mem8] = >= signed
3429 def SETLEr : I<0x9E, MRM0r,
3430 (outs GR8 :$dst), (ins),
3432 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3433 TB; // GR8 = <= signed
3434 def SETLEm : I<0x9E, MRM0m,
3435 (outs), (ins i8mem:$dst),
3437 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3438 TB; // [mem8] = <= signed
3440 def SETGr : I<0x9F, MRM0r,
3441 (outs GR8 :$dst), (ins),
3443 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3444 TB; // GR8 = > signed
3445 def SETGm : I<0x9F, MRM0m,
3446 (outs), (ins i8mem:$dst),
3448 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3449 TB; // [mem8] = > signed
3451 def SETBr : I<0x92, MRM0r,
3452 (outs GR8 :$dst), (ins),
3454 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3455 TB; // GR8 = < unsign
3456 def SETBm : I<0x92, MRM0m,
3457 (outs), (ins i8mem:$dst),
3459 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3460 TB; // [mem8] = < unsign
3462 def SETAEr : I<0x93, MRM0r,
3463 (outs GR8 :$dst), (ins),
3465 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3466 TB; // GR8 = >= unsign
3467 def SETAEm : I<0x93, MRM0m,
3468 (outs), (ins i8mem:$dst),
3470 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3471 TB; // [mem8] = >= unsign
3473 def SETBEr : I<0x96, MRM0r,
3474 (outs GR8 :$dst), (ins),
3476 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3477 TB; // GR8 = <= unsign
3478 def SETBEm : I<0x96, MRM0m,
3479 (outs), (ins i8mem:$dst),
3481 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3482 TB; // [mem8] = <= unsign
3484 def SETAr : I<0x97, MRM0r,
3485 (outs GR8 :$dst), (ins),
3487 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3488 TB; // GR8 = > signed
3489 def SETAm : I<0x97, MRM0m,
3490 (outs), (ins i8mem:$dst),
3492 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3493 TB; // [mem8] = > signed
3495 def SETSr : I<0x98, MRM0r,
3496 (outs GR8 :$dst), (ins),
3498 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3499 TB; // GR8 = <sign bit>
3500 def SETSm : I<0x98, MRM0m,
3501 (outs), (ins i8mem:$dst),
3503 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3504 TB; // [mem8] = <sign bit>
3505 def SETNSr : I<0x99, MRM0r,
3506 (outs GR8 :$dst), (ins),
3508 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3509 TB; // GR8 = !<sign bit>
3510 def SETNSm : I<0x99, MRM0m,
3511 (outs), (ins i8mem:$dst),
3513 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3514 TB; // [mem8] = !<sign bit>
3516 def SETPr : I<0x9A, MRM0r,
3517 (outs GR8 :$dst), (ins),
3519 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3521 def SETPm : I<0x9A, MRM0m,
3522 (outs), (ins i8mem:$dst),
3524 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3525 TB; // [mem8] = parity
3526 def SETNPr : I<0x9B, MRM0r,
3527 (outs GR8 :$dst), (ins),
3529 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3530 TB; // GR8 = not parity
3531 def SETNPm : I<0x9B, MRM0m,
3532 (outs), (ins i8mem:$dst),
3534 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3535 TB; // [mem8] = not parity
3537 def SETOr : I<0x90, MRM0r,
3538 (outs GR8 :$dst), (ins),
3540 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3541 TB; // GR8 = overflow
3542 def SETOm : I<0x90, MRM0m,
3543 (outs), (ins i8mem:$dst),
3545 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3546 TB; // [mem8] = overflow
3547 def SETNOr : I<0x91, MRM0r,
3548 (outs GR8 :$dst), (ins),
3550 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3551 TB; // GR8 = not overflow
3552 def SETNOm : I<0x91, MRM0m,
3553 (outs), (ins i8mem:$dst),
3555 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3556 TB; // [mem8] = not overflow
3557 } // Uses = [EFLAGS]
3560 // Integer comparisons
3561 let Defs = [EFLAGS] in {
3562 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3563 "cmp{b}\t{$src, %al|%al, $src}", []>;
3564 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3565 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3566 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3567 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3569 def CMP8rr : I<0x38, MRMDestReg,
3570 (outs), (ins GR8 :$src1, GR8 :$src2),
3571 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3572 [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
3573 def CMP16rr : I<0x39, MRMDestReg,
3574 (outs), (ins GR16:$src1, GR16:$src2),
3575 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3576 [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
3577 def CMP32rr : I<0x39, MRMDestReg,
3578 (outs), (ins GR32:$src1, GR32:$src2),
3579 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3580 [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
3581 def CMP8mr : I<0x38, MRMDestMem,
3582 (outs), (ins i8mem :$src1, GR8 :$src2),
3583 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3584 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
3585 def CMP16mr : I<0x39, MRMDestMem,
3586 (outs), (ins i16mem:$src1, GR16:$src2),
3587 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3588 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
3590 def CMP32mr : I<0x39, MRMDestMem,
3591 (outs), (ins i32mem:$src1, GR32:$src2),
3592 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3593 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
3594 def CMP8rm : I<0x3A, MRMSrcMem,
3595 (outs), (ins GR8 :$src1, i8mem :$src2),
3596 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3597 [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
3598 def CMP16rm : I<0x3B, MRMSrcMem,
3599 (outs), (ins GR16:$src1, i16mem:$src2),
3600 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3601 [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
3603 def CMP32rm : I<0x3B, MRMSrcMem,
3604 (outs), (ins GR32:$src1, i32mem:$src2),
3605 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3606 [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
3608 // These are alternate spellings for use by the disassembler, we mark them as
3609 // code gen only to ensure they aren't matched by the assembler.
3610 let isCodeGenOnly = 1 in {
3611 def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3612 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3613 def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3614 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3615 def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3616 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3619 def CMP8ri : Ii8<0x80, MRM7r,
3620 (outs), (ins GR8:$src1, i8imm:$src2),
3621 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3622 [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
3623 def CMP16ri : Ii16<0x81, MRM7r,
3624 (outs), (ins GR16:$src1, i16imm:$src2),
3625 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3626 [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
3627 def CMP32ri : Ii32<0x81, MRM7r,
3628 (outs), (ins GR32:$src1, i32imm:$src2),
3629 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3630 [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
3631 def CMP8mi : Ii8 <0x80, MRM7m,
3632 (outs), (ins i8mem :$src1, i8imm :$src2),
3633 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3634 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
3635 def CMP16mi : Ii16<0x81, MRM7m,
3636 (outs), (ins i16mem:$src1, i16imm:$src2),
3637 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3638 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
3640 def CMP32mi : Ii32<0x81, MRM7m,
3641 (outs), (ins i32mem:$src1, i32imm:$src2),
3642 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3643 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
3644 def CMP16ri8 : Ii8<0x83, MRM7r,
3645 (outs), (ins GR16:$src1, i16i8imm:$src2),
3646 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3647 [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
3649 def CMP16mi8 : Ii8<0x83, MRM7m,
3650 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3651 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3652 [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
3653 i16immSExt8:$src2))]>, OpSize;
3654 def CMP32mi8 : Ii8<0x83, MRM7m,
3655 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3656 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3657 [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
3658 i32immSExt8:$src2))]>;
3659 def CMP32ri8 : Ii8<0x83, MRM7r,
3660 (outs), (ins GR32:$src1, i32i8imm:$src2),
3661 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3662 [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
3663 } // Defs = [EFLAGS]
3666 // TODO: BTC, BTR, and BTS
3667 let Defs = [EFLAGS] in {
3668 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3669 "bt{w}\t{$src2, $src1|$src1, $src2}",
3670 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
3671 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3672 "bt{l}\t{$src2, $src1|$src1, $src2}",
3673 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
3675 // Unlike with the register+register form, the memory+register form of the
3676 // bt instruction does not ignore the high bits of the index. From ISel's
3677 // perspective, this is pretty bizarre. Make these instructions disassembly
3680 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3681 "bt{w}\t{$src2, $src1|$src1, $src2}",
3682 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3683 // (implicit EFLAGS)]
3685 >, OpSize, TB, Requires<[FastBTMem]>;
3686 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3687 "bt{l}\t{$src2, $src1|$src1, $src2}",
3688 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3689 // (implicit EFLAGS)]
3691 >, TB, Requires<[FastBTMem]>;
3693 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3694 "bt{w}\t{$src2, $src1|$src1, $src2}",
3695 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
3697 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3698 "bt{l}\t{$src2, $src1|$src1, $src2}",
3699 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
3700 // Note that these instructions don't need FastBTMem because that
3701 // only applies when the other operand is in a register. When it's
3702 // an immediate, bt is still fast.
3703 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3704 "bt{w}\t{$src2, $src1|$src1, $src2}",
3705 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
3707 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3708 "bt{l}\t{$src2, $src1|$src1, $src2}",
3709 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
3712 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3713 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3714 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3715 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3716 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3717 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3718 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3719 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3720 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3721 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3722 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3723 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3724 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3725 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3726 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3727 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3729 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3730 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3731 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3732 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3733 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3734 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3735 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3736 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3737 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3738 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3739 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3740 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3741 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3742 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3743 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3744 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3746 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3747 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3748 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3749 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3750 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3751 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3752 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3753 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3754 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3755 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3756 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3757 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3758 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3759 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3760 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3761 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3762 } // Defs = [EFLAGS]
3764 // Sign/Zero extenders
3765 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3766 // of the register here. This has a smaller encoding and avoids a
3767 // partial-register update. Actual movsbw included for the disassembler.
3768 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3769 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3770 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3771 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3772 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3773 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3774 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3775 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3776 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3777 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3778 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3779 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3780 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3781 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3782 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3783 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3784 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3785 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3786 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3787 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3789 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3790 // of the register here. This has a smaller encoding and avoids a
3791 // partial-register update. Actual movzbw included for the disassembler.
3792 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3793 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3794 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3795 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3796 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3797 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3798 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3799 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3800 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3801 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3802 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3803 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3804 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3805 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3806 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3807 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3808 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3809 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3810 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3811 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3813 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
3814 // except that they use GR32_NOREX for the output operand register class
3815 // instead of GR32. This allows them to operate on h registers on x86-64.
3816 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3817 (outs GR32_NOREX:$dst), (ins GR8:$src),
3818 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3821 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3822 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3823 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3826 let neverHasSideEffects = 1 in {
3827 let Defs = [AX], Uses = [AL] in
3828 def CBW : I<0x98, RawFrm, (outs), (ins),
3829 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3830 let Defs = [EAX], Uses = [AX] in
3831 def CWDE : I<0x98, RawFrm, (outs), (ins),
3832 "{cwtl|cwde}", []>; // EAX = signext(AX)
3834 let Defs = [AX,DX], Uses = [AX] in
3835 def CWD : I<0x99, RawFrm, (outs), (ins),
3836 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3837 let Defs = [EAX,EDX], Uses = [EAX] in
3838 def CDQ : I<0x99, RawFrm, (outs), (ins),
3839 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3842 //===----------------------------------------------------------------------===//
3843 // Alias Instructions
3844 //===----------------------------------------------------------------------===//
3846 // Alias instructions that map movr0 to xor.
3847 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3848 // FIXME: Set encoding to pseudo.
3849 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3850 isCodeGenOnly = 1 in {
3851 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
3852 [(set GR8:$dst, 0)]>;
3854 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
3855 // encoding and avoids a partial-register update sometimes, but doing so
3856 // at isel time interferes with rematerialization in the current register
3857 // allocator. For now, this is rewritten when the instruction is lowered
3859 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3861 [(set GR16:$dst, 0)]>, OpSize;
3863 // FIXME: Set encoding to pseudo.
3864 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
3865 [(set GR32:$dst, 0)]>;
3868 //===----------------------------------------------------------------------===//
3869 // Thread Local Storage Instructions
3873 // All calls clobber the non-callee saved registers. ESP is marked as
3874 // a use to prevent stack-pointer assignments that appear immediately
3875 // before calls from potentially appearing dead.
3876 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3877 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3878 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3879 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3881 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
3882 "leal\t$sym, %eax; "
3883 "call\t___tls_get_addr@PLT",
3884 [(X86tlsaddr tls32addr:$sym)]>,
3885 Requires<[In32BitMode]>;
3887 // Darwin TLS Support
3888 // For i386, the address of the thunk is passed on the stack, on return the
3889 // address of the variable is in %eax. %ecx is trashed during the function
3890 // call. All other registers are preserved.
3891 let Defs = [EAX, ECX],
3893 usesCustomInserter = 1 in
3894 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
3896 [(X86TLSCall addr:$sym)]>,
3897 Requires<[In32BitMode]>;
3899 let AddedComplexity = 5, isCodeGenOnly = 1 in
3900 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3901 "movl\t%gs:$src, $dst",
3902 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3904 let AddedComplexity = 5, isCodeGenOnly = 1 in
3905 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3906 "movl\t%fs:$src, $dst",
3907 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3909 //===----------------------------------------------------------------------===//
3910 // EH Pseudo Instructions
3912 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3913 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3914 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3915 "ret\t#eh_return, addr: $addr",
3916 [(X86ehret GR32:$addr)]>;
3920 //===----------------------------------------------------------------------===//
3925 let hasSideEffects = 1 in {
3926 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
3928 [(X86MemBarrier)]>, Requires<[HasSSE2]>;
3930 // TODO: Get this to fold the constant into the instruction.
3932 def Int_MemBarrierNoSSE : I<0x0B, Pseudo, (outs), (ins GR32:$zero),
3934 "or{l}\t{$zero, (%esp)|(%esp), $zero}",
3935 [(X86MemBarrierNoSSE GR32:$zero)]>, LOCK;
3938 // Atomic swap. These are just normal xchg instructions. But since a memory
3939 // operand is referenced, the atomicity is ensured.
3940 let Constraints = "$val = $dst" in {
3941 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3942 (ins GR32:$val, i32mem:$ptr),
3943 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3944 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3945 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3946 (ins GR16:$val, i16mem:$ptr),
3947 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3948 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3950 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3951 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3952 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3954 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3955 "xchg{l}\t{$val, $src|$src, $val}", []>;
3956 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3957 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3958 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3959 "xchg{b}\t{$val, $src|$src, $val}", []>;
3962 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3963 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3964 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3965 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3967 // Atomic compare and swap.
3968 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3969 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3971 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3972 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3974 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3975 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
3978 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3981 let Defs = [AX, EFLAGS], Uses = [AX] in {
3982 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3984 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3985 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3987 let Defs = [AL, EFLAGS], Uses = [AL] in {
3988 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3990 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3991 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3994 // Atomic exchange and add
3995 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3996 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
3998 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3999 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
4001 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
4003 "xadd{w}\t{$val, $ptr|$ptr, $val}",
4004 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
4006 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
4008 "xadd{b}\t{$val, $ptr|$ptr, $val}",
4009 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
4013 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
4014 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
4015 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
4016 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4017 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4018 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
4020 let mayLoad = 1, mayStore = 1 in {
4021 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
4022 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
4023 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
4024 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4025 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
4026 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
4029 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
4030 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
4031 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
4032 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4033 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4034 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
4036 let mayLoad = 1, mayStore = 1 in {
4037 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
4038 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
4039 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
4040 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4041 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
4042 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
4045 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
4046 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
4047 "cmpxchg8b\t$dst", []>, TB;
4049 // Optimized codegen when the non-memory output is not used.
4050 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
4051 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1 in {
4052 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
4054 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4055 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
4057 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4058 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
4060 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4061 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
4063 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4064 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
4066 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4067 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
4069 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4070 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
4072 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4073 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
4075 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4077 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
4079 "inc{b}\t$dst", []>, LOCK;
4080 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
4082 "inc{w}\t$dst", []>, OpSize, LOCK;
4083 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
4085 "inc{l}\t$dst", []>, LOCK;
4087 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
4089 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4090 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
4092 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4093 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
4095 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4096 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
4098 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4099 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
4101 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4102 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
4104 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4105 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
4107 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4108 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
4110 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4112 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
4114 "dec{b}\t$dst", []>, LOCK;
4115 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
4117 "dec{w}\t$dst", []>, OpSize, LOCK;
4118 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
4120 "dec{l}\t$dst", []>, LOCK;
4123 // Atomic exchange, and, or, xor
4124 let Constraints = "$val = $dst", Defs = [EFLAGS],
4125 usesCustomInserter = 1 in {
4126 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4127 "#ATOMAND32 PSEUDO!",
4128 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
4129 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4130 "#ATOMOR32 PSEUDO!",
4131 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
4132 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4133 "#ATOMXOR32 PSEUDO!",
4134 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
4135 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4136 "#ATOMNAND32 PSEUDO!",
4137 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
4138 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
4139 "#ATOMMIN32 PSEUDO!",
4140 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
4141 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4142 "#ATOMMAX32 PSEUDO!",
4143 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
4144 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4145 "#ATOMUMIN32 PSEUDO!",
4146 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
4147 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4148 "#ATOMUMAX32 PSEUDO!",
4149 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
4151 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4152 "#ATOMAND16 PSEUDO!",
4153 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
4154 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4155 "#ATOMOR16 PSEUDO!",
4156 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
4157 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4158 "#ATOMXOR16 PSEUDO!",
4159 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
4160 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4161 "#ATOMNAND16 PSEUDO!",
4162 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
4163 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
4164 "#ATOMMIN16 PSEUDO!",
4165 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
4166 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4167 "#ATOMMAX16 PSEUDO!",
4168 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
4169 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4170 "#ATOMUMIN16 PSEUDO!",
4171 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
4172 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4173 "#ATOMUMAX16 PSEUDO!",
4174 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
4176 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4177 "#ATOMAND8 PSEUDO!",
4178 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
4179 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4181 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
4182 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4183 "#ATOMXOR8 PSEUDO!",
4184 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
4185 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4186 "#ATOMNAND8 PSEUDO!",
4187 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
4190 let Constraints = "$val1 = $dst1, $val2 = $dst2",
4191 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
4192 Uses = [EAX, EBX, ECX, EDX],
4193 mayLoad = 1, mayStore = 1,
4194 usesCustomInserter = 1 in {
4195 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4196 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4197 "#ATOMAND6432 PSEUDO!", []>;
4198 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4199 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4200 "#ATOMOR6432 PSEUDO!", []>;
4201 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4202 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4203 "#ATOMXOR6432 PSEUDO!", []>;
4204 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4205 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4206 "#ATOMNAND6432 PSEUDO!", []>;
4207 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4208 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4209 "#ATOMADD6432 PSEUDO!", []>;
4210 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4211 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4212 "#ATOMSUB6432 PSEUDO!", []>;
4213 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4214 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4215 "#ATOMSWAP6432 PSEUDO!", []>;
4218 // Segmentation support instructions.
4220 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4221 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4222 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4223 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4225 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
4226 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
4227 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4228 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4229 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4231 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4232 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4233 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4234 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4235 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4236 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4237 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4238 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4240 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
4242 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4243 "str{w}\t{$dst}", []>, TB;
4244 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4245 "str{w}\t{$dst}", []>, TB;
4246 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4247 "ltr{w}\t{$src}", []>, TB;
4248 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4249 "ltr{w}\t{$src}", []>, TB;
4251 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4252 "push{w}\t%fs", []>, OpSize, TB;
4253 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4254 "push{l}\t%fs", []>, TB;
4255 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4256 "push{w}\t%gs", []>, OpSize, TB;
4257 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4258 "push{l}\t%gs", []>, TB;
4260 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4261 "pop{w}\t%fs", []>, OpSize, TB;
4262 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4263 "pop{l}\t%fs", []>, TB;
4264 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4265 "pop{w}\t%gs", []>, OpSize, TB;
4266 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4267 "pop{l}\t%gs", []>, TB;
4269 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4270 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4271 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4272 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4273 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4274 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4275 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4276 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4277 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4278 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4279 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4280 "les{l}\t{$src, $dst|$dst, $src}", []>;
4281 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4282 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4283 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4284 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4285 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4286 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4287 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4288 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4290 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4291 "verr\t$seg", []>, TB;
4292 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4293 "verr\t$seg", []>, TB;
4294 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4295 "verw\t$seg", []>, TB;
4296 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4297 "verw\t$seg", []>, TB;
4299 // Descriptor-table support instructions
4301 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4302 "sgdt\t$dst", []>, TB;
4303 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4304 "sidt\t$dst", []>, TB;
4305 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4306 "sldt{w}\t$dst", []>, TB;
4307 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4308 "sldt{w}\t$dst", []>, TB;
4309 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4310 "lgdt\t$src", []>, TB;
4311 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4312 "lidt\t$src", []>, TB;
4313 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4314 "lldt{w}\t$src", []>, TB;
4315 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4316 "lldt{w}\t$src", []>, TB;
4318 // Lock instruction prefix
4319 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
4321 // Repeat string operation instruction prefixes
4322 // These uses the DF flag in the EFLAGS register to inc or dec ECX
4323 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
4324 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
4325 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
4326 // Repeat while not equal (used with CMPS and SCAS)
4327 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
4330 // Segment override instruction prefixes
4331 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
4332 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
4333 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
4334 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
4335 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
4336 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
4338 // String manipulation instructions
4340 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
4341 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
4342 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4344 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4345 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4346 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4348 // CPU flow control instructions
4350 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4351 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4353 // FPU control instructions
4355 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4357 // Flag instructions
4359 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4360 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4361 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4362 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4363 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4364 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4365 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4367 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4369 // Table lookup instructions
4371 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4373 // Specialized register support
4375 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4376 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4377 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4379 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4380 "smsw{w}\t$dst", []>, OpSize, TB;
4381 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4382 "smsw{l}\t$dst", []>, TB;
4383 // For memory operands, there is only a 16-bit form
4384 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4385 "smsw{w}\t$dst", []>, TB;
4387 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4388 "lmsw{w}\t$src", []>, TB;
4389 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4390 "lmsw{w}\t$src", []>, TB;
4392 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4394 // Cache instructions
4396 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4397 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4402 def INVEPT : I<0x80, RawFrm, (outs), (ins), "invept", []>, OpSize, T8;
4404 def INVVPID : I<0x81, RawFrm, (outs), (ins), "invvpid", []>, OpSize, T8;
4406 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
4407 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4408 "vmclear\t$vmcs", []>, OpSize, TB;
4410 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
4412 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
4413 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4414 "vmptrld\t$vmcs", []>, TB;
4415 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4416 "vmptrst\t$vmcs", []>, TB;
4417 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4418 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4419 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4420 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4421 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4422 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4423 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4424 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4425 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4426 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4427 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4428 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4429 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4430 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4431 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4432 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4434 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
4435 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4436 "vmxon\t{$vmxon}", []>, XS;
4438 //===----------------------------------------------------------------------===//
4439 // Non-Instruction Patterns
4440 //===----------------------------------------------------------------------===//
4442 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
4443 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
4444 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
4445 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
4446 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
4447 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
4448 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
4450 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
4451 (ADD32ri GR32:$src1, tconstpool:$src2)>;
4452 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
4453 (ADD32ri GR32:$src1, tjumptable:$src2)>;
4454 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
4455 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
4456 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
4457 (ADD32ri GR32:$src1, texternalsym:$src2)>;
4458 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
4459 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
4461 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
4462 (MOV32mi addr:$dst, tglobaladdr:$src)>;
4463 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
4464 (MOV32mi addr:$dst, texternalsym:$src)>;
4465 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
4466 (MOV32mi addr:$dst, tblockaddress:$src)>;
4470 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
4471 (TCRETURNri GR32_TC:$dst, imm:$off)>,
4472 Requires<[In32BitMode]>;
4474 // FIXME: This is disabled for 32-bit PIC mode because the global base
4475 // register which is part of the address mode may be assigned a
4476 // callee-saved register.
4477 def : Pat<(X86tcret (load addr:$dst), imm:$off),
4478 (TCRETURNmi addr:$dst, imm:$off)>,
4479 Requires<[In32BitMode, IsNotPIC]>;
4481 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
4482 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4483 Requires<[In32BitMode]>;
4485 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
4486 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4487 Requires<[In32BitMode]>;
4489 // Normal calls, with various flavors of addresses.
4490 def : Pat<(X86call (i32 tglobaladdr:$dst)),
4491 (CALLpcrel32 tglobaladdr:$dst)>;
4492 def : Pat<(X86call (i32 texternalsym:$dst)),
4493 (CALLpcrel32 texternalsym:$dst)>;
4494 def : Pat<(X86call (i32 imm:$dst)),
4495 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
4497 // X86 specific add which produces a flag.
4498 def : Pat<(addc GR32:$src1, GR32:$src2),
4499 (ADD32rr GR32:$src1, GR32:$src2)>;
4500 def : Pat<(addc GR32:$src1, (load addr:$src2)),
4501 (ADD32rm GR32:$src1, addr:$src2)>;
4502 def : Pat<(addc GR32:$src1, imm:$src2),
4503 (ADD32ri GR32:$src1, imm:$src2)>;
4504 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
4505 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4507 def : Pat<(subc GR32:$src1, GR32:$src2),
4508 (SUB32rr GR32:$src1, GR32:$src2)>;
4509 def : Pat<(subc GR32:$src1, (load addr:$src2)),
4510 (SUB32rm GR32:$src1, addr:$src2)>;
4511 def : Pat<(subc GR32:$src1, imm:$src2),
4512 (SUB32ri GR32:$src1, imm:$src2)>;
4513 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
4514 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4518 // TEST R,R is smaller than CMP R,0
4519 def : Pat<(X86cmp GR8:$src1, 0),
4520 (TEST8rr GR8:$src1, GR8:$src1)>;
4521 def : Pat<(X86cmp GR16:$src1, 0),
4522 (TEST16rr GR16:$src1, GR16:$src1)>;
4523 def : Pat<(X86cmp GR32:$src1, 0),
4524 (TEST32rr GR32:$src1, GR32:$src1)>;
4526 // Conditional moves with folded loads with operands swapped and conditions
4528 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
4529 (CMOVAE16rm GR16:$src2, addr:$src1)>;
4530 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
4531 (CMOVAE32rm GR32:$src2, addr:$src1)>;
4532 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
4533 (CMOVB16rm GR16:$src2, addr:$src1)>;
4534 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
4535 (CMOVB32rm GR32:$src2, addr:$src1)>;
4536 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
4537 (CMOVNE16rm GR16:$src2, addr:$src1)>;
4538 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
4539 (CMOVNE32rm GR32:$src2, addr:$src1)>;
4540 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
4541 (CMOVE16rm GR16:$src2, addr:$src1)>;
4542 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
4543 (CMOVE32rm GR32:$src2, addr:$src1)>;
4544 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
4545 (CMOVA16rm GR16:$src2, addr:$src1)>;
4546 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
4547 (CMOVA32rm GR32:$src2, addr:$src1)>;
4548 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
4549 (CMOVBE16rm GR16:$src2, addr:$src1)>;
4550 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
4551 (CMOVBE32rm GR32:$src2, addr:$src1)>;
4552 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
4553 (CMOVGE16rm GR16:$src2, addr:$src1)>;
4554 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
4555 (CMOVGE32rm GR32:$src2, addr:$src1)>;
4556 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
4557 (CMOVL16rm GR16:$src2, addr:$src1)>;
4558 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
4559 (CMOVL32rm GR32:$src2, addr:$src1)>;
4560 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
4561 (CMOVG16rm GR16:$src2, addr:$src1)>;
4562 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
4563 (CMOVG32rm GR32:$src2, addr:$src1)>;
4564 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
4565 (CMOVLE16rm GR16:$src2, addr:$src1)>;
4566 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
4567 (CMOVLE32rm GR32:$src2, addr:$src1)>;
4568 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
4569 (CMOVNP16rm GR16:$src2, addr:$src1)>;
4570 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
4571 (CMOVNP32rm GR32:$src2, addr:$src1)>;
4572 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
4573 (CMOVP16rm GR16:$src2, addr:$src1)>;
4574 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
4575 (CMOVP32rm GR32:$src2, addr:$src1)>;
4576 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
4577 (CMOVNS16rm GR16:$src2, addr:$src1)>;
4578 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
4579 (CMOVNS32rm GR32:$src2, addr:$src1)>;
4580 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
4581 (CMOVS16rm GR16:$src2, addr:$src1)>;
4582 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
4583 (CMOVS32rm GR32:$src2, addr:$src1)>;
4584 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
4585 (CMOVNO16rm GR16:$src2, addr:$src1)>;
4586 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
4587 (CMOVNO32rm GR32:$src2, addr:$src1)>;
4588 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
4589 (CMOVO16rm GR16:$src2, addr:$src1)>;
4590 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
4591 (CMOVO32rm GR32:$src2, addr:$src1)>;
4593 // zextload bool -> zextload byte
4594 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4595 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4596 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4598 // extload bool -> extload byte
4599 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4600 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4601 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4602 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
4603 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
4604 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
4606 // anyext. Define these to do an explicit zero-extend to
4607 // avoid partial-register updates.
4608 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
4609 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
4611 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
4612 def : Pat<(i32 (anyext GR16:$src)),
4613 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
4616 //===----------------------------------------------------------------------===//
4618 //===----------------------------------------------------------------------===//
4620 // Odd encoding trick: -128 fits into an 8-bit immediate field while
4621 // +128 doesn't, so in this special case use a sub instead of an add.
4622 def : Pat<(add GR16:$src1, 128),
4623 (SUB16ri8 GR16:$src1, -128)>;
4624 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
4625 (SUB16mi8 addr:$dst, -128)>;
4626 def : Pat<(add GR32:$src1, 128),
4627 (SUB32ri8 GR32:$src1, -128)>;
4628 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
4629 (SUB32mi8 addr:$dst, -128)>;
4631 // r & (2^16-1) ==> movz
4632 def : Pat<(and GR32:$src1, 0xffff),
4633 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
4634 // r & (2^8-1) ==> movz
4635 def : Pat<(and GR32:$src1, 0xff),
4636 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
4639 Requires<[In32BitMode]>;
4640 // r & (2^8-1) ==> movz
4641 def : Pat<(and GR16:$src1, 0xff),
4642 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
4645 Requires<[In32BitMode]>;
4647 // sext_inreg patterns
4648 def : Pat<(sext_inreg GR32:$src, i16),
4649 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
4650 def : Pat<(sext_inreg GR32:$src, i8),
4651 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4654 Requires<[In32BitMode]>;
4655 def : Pat<(sext_inreg GR16:$src, i8),
4656 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4659 Requires<[In32BitMode]>;
4662 def : Pat<(i16 (trunc GR32:$src)),
4663 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
4664 def : Pat<(i8 (trunc GR32:$src)),
4665 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4667 Requires<[In32BitMode]>;
4668 def : Pat<(i8 (trunc GR16:$src)),
4669 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4671 Requires<[In32BitMode]>;
4673 // h-register tricks
4674 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4675 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4677 Requires<[In32BitMode]>;
4678 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4679 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4681 Requires<[In32BitMode]>;
4682 def : Pat<(srl GR16:$src, (i8 8)),
4685 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4688 Requires<[In32BitMode]>;
4689 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4690 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4693 Requires<[In32BitMode]>;
4694 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4695 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4698 Requires<[In32BitMode]>;
4699 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4700 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4703 Requires<[In32BitMode]>;
4704 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
4705 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4708 Requires<[In32BitMode]>;
4710 // (shl x, 1) ==> (add x, x)
4711 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4712 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4713 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4715 // (shl x (and y, 31)) ==> (shl x, y)
4716 def : Pat<(shl GR8:$src1, (and CL, 31)),
4717 (SHL8rCL GR8:$src1)>;
4718 def : Pat<(shl GR16:$src1, (and CL, 31)),
4719 (SHL16rCL GR16:$src1)>;
4720 def : Pat<(shl GR32:$src1, (and CL, 31)),
4721 (SHL32rCL GR32:$src1)>;
4722 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4723 (SHL8mCL addr:$dst)>;
4724 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4725 (SHL16mCL addr:$dst)>;
4726 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4727 (SHL32mCL addr:$dst)>;
4729 def : Pat<(srl GR8:$src1, (and CL, 31)),
4730 (SHR8rCL GR8:$src1)>;
4731 def : Pat<(srl GR16:$src1, (and CL, 31)),
4732 (SHR16rCL GR16:$src1)>;
4733 def : Pat<(srl GR32:$src1, (and CL, 31)),
4734 (SHR32rCL GR32:$src1)>;
4735 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4736 (SHR8mCL addr:$dst)>;
4737 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4738 (SHR16mCL addr:$dst)>;
4739 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4740 (SHR32mCL addr:$dst)>;
4742 def : Pat<(sra GR8:$src1, (and CL, 31)),
4743 (SAR8rCL GR8:$src1)>;
4744 def : Pat<(sra GR16:$src1, (and CL, 31)),
4745 (SAR16rCL GR16:$src1)>;
4746 def : Pat<(sra GR32:$src1, (and CL, 31)),
4747 (SAR32rCL GR32:$src1)>;
4748 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4749 (SAR8mCL addr:$dst)>;
4750 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4751 (SAR16mCL addr:$dst)>;
4752 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4753 (SAR32mCL addr:$dst)>;
4755 // (anyext (setcc_carry)) -> (setcc_carry)
4756 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4758 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4760 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
4763 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
4764 let AddedComplexity = 5 in { // Try this before the selecting to OR
4765 def : Pat<(or_is_add GR16:$src1, imm:$src2),
4766 (ADD16ri GR16:$src1, imm:$src2)>;
4767 def : Pat<(or_is_add GR32:$src1, imm:$src2),
4768 (ADD32ri GR32:$src1, imm:$src2)>;
4769 def : Pat<(or_is_add GR16:$src1, i16immSExt8:$src2),
4770 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4771 def : Pat<(or_is_add GR32:$src1, i32immSExt8:$src2),
4772 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4773 def : Pat<(or_is_add GR16:$src1, GR16:$src2),
4774 (ADD16rr GR16:$src1, GR16:$src2)>;
4775 def : Pat<(or_is_add GR32:$src1, GR32:$src2),
4776 (ADD32rr GR32:$src1, GR32:$src2)>;
4777 } // AddedComplexity
4779 //===----------------------------------------------------------------------===//
4780 // EFLAGS-defining Patterns
4781 //===----------------------------------------------------------------------===//
4784 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
4785 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
4786 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
4789 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
4790 (ADD8rm GR8:$src1, addr:$src2)>;
4791 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
4792 (ADD16rm GR16:$src1, addr:$src2)>;
4793 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
4794 (ADD32rm GR32:$src1, addr:$src2)>;
4797 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
4798 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
4799 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
4800 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
4801 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4802 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
4803 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4806 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
4807 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
4808 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
4811 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
4812 (SUB8rm GR8:$src1, addr:$src2)>;
4813 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
4814 (SUB16rm GR16:$src1, addr:$src2)>;
4815 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
4816 (SUB32rm GR32:$src1, addr:$src2)>;
4819 def : Pat<(sub GR8:$src1, imm:$src2),
4820 (SUB8ri GR8:$src1, imm:$src2)>;
4821 def : Pat<(sub GR16:$src1, imm:$src2),
4822 (SUB16ri GR16:$src1, imm:$src2)>;
4823 def : Pat<(sub GR32:$src1, imm:$src2),
4824 (SUB32ri GR32:$src1, imm:$src2)>;
4825 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
4826 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4827 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
4828 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4831 def : Pat<(mul GR16:$src1, GR16:$src2),
4832 (IMUL16rr GR16:$src1, GR16:$src2)>;
4833 def : Pat<(mul GR32:$src1, GR32:$src2),
4834 (IMUL32rr GR32:$src1, GR32:$src2)>;
4837 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
4838 (IMUL16rm GR16:$src1, addr:$src2)>;
4839 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
4840 (IMUL32rm GR32:$src1, addr:$src2)>;
4843 def : Pat<(mul GR16:$src1, imm:$src2),
4844 (IMUL16rri GR16:$src1, imm:$src2)>;
4845 def : Pat<(mul GR32:$src1, imm:$src2),
4846 (IMUL32rri GR32:$src1, imm:$src2)>;
4847 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
4848 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4849 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
4850 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4852 // reg = mul mem, imm
4853 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
4854 (IMUL16rmi addr:$src1, imm:$src2)>;
4855 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
4856 (IMUL32rmi addr:$src1, imm:$src2)>;
4857 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
4858 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4859 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
4860 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4862 // Optimize multiply by 2 with EFLAGS result.
4863 let AddedComplexity = 2 in {
4864 def : Pat<(X86smul_flag GR16:$src1, 2), (ADD16rr GR16:$src1, GR16:$src1)>;
4865 def : Pat<(X86smul_flag GR32:$src1, 2), (ADD32rr GR32:$src1, GR32:$src1)>;
4868 // Patterns for nodes that do not produce flags, for instructions that do.
4871 def : Pat<(add GR8:$src1 , 1), (INC8r GR8:$src1)>;
4872 def : Pat<(add GR16:$src1, 1), (INC16r GR16:$src1)>, Requires<[In32BitMode]>;
4873 def : Pat<(add GR32:$src1, 1), (INC32r GR32:$src1)>, Requires<[In32BitMode]>;
4876 def : Pat<(add GR8:$src1 , -1), (DEC8r GR8:$src1)>;
4877 def : Pat<(add GR16:$src1, -1), (DEC16r GR16:$src1)>, Requires<[In32BitMode]>;
4878 def : Pat<(add GR32:$src1, -1), (DEC32r GR32:$src1)>, Requires<[In32BitMode]>;
4881 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
4882 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
4883 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
4886 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
4887 (OR8rm GR8:$src1, addr:$src2)>;
4888 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
4889 (OR16rm GR16:$src1, addr:$src2)>;
4890 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
4891 (OR32rm GR32:$src1, addr:$src2)>;
4894 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
4895 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
4896 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
4897 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
4898 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4899 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
4900 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4903 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
4904 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
4905 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
4908 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
4909 (XOR8rm GR8:$src1, addr:$src2)>;
4910 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
4911 (XOR16rm GR16:$src1, addr:$src2)>;
4912 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
4913 (XOR32rm GR32:$src1, addr:$src2)>;
4916 def : Pat<(xor GR8:$src1, imm:$src2),
4917 (XOR8ri GR8:$src1, imm:$src2)>;
4918 def : Pat<(xor GR16:$src1, imm:$src2),
4919 (XOR16ri GR16:$src1, imm:$src2)>;
4920 def : Pat<(xor GR32:$src1, imm:$src2),
4921 (XOR32ri GR32:$src1, imm:$src2)>;
4922 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
4923 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4924 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
4925 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4928 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
4929 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
4930 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
4933 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
4934 (AND8rm GR8:$src1, addr:$src2)>;
4935 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
4936 (AND16rm GR16:$src1, addr:$src2)>;
4937 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
4938 (AND32rm GR32:$src1, addr:$src2)>;
4941 def : Pat<(and GR8:$src1, imm:$src2),
4942 (AND8ri GR8:$src1, imm:$src2)>;
4943 def : Pat<(and GR16:$src1, imm:$src2),
4944 (AND16ri GR16:$src1, imm:$src2)>;
4945 def : Pat<(and GR32:$src1, imm:$src2),
4946 (AND32ri GR32:$src1, imm:$src2)>;
4947 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
4948 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
4949 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
4950 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
4952 //===----------------------------------------------------------------------===//
4953 // Floating Point Stack Support
4954 //===----------------------------------------------------------------------===//
4956 include "X86InstrFPStack.td"
4958 //===----------------------------------------------------------------------===//
4960 //===----------------------------------------------------------------------===//
4962 include "X86Instr64bit.td"
4964 //===----------------------------------------------------------------------===//
4965 // SIMD support (SSE, MMX and AVX)
4966 //===----------------------------------------------------------------------===//
4968 include "X86InstrFragmentsSIMD.td"
4970 //===----------------------------------------------------------------------===//
4971 // XMM Floating point support (requires SSE / SSE2)
4972 //===----------------------------------------------------------------------===//
4974 include "X86InstrSSE.td"
4976 //===----------------------------------------------------------------------===//
4977 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
4978 //===----------------------------------------------------------------------===//
4980 include "X86InstrMMX.td"