1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
33 def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
37 def SDTX86BrCond : SDTypeProfile<0, 3,
38 [SDTCisVT<0, OtherVT>,
39 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
41 def SDTX86SetCC : SDTypeProfile<1, 2,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
47 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
49 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
50 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
51 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
53 def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
54 def SDT_X86CallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
57 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
59 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
61 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
63 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
65 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
67 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
69 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
71 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
73 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
74 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
75 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
76 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
78 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
80 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
82 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
83 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
85 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
87 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
88 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
90 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
91 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
93 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
94 [SDNPHasChain, SDNPMayStore,
95 SDNPMayLoad, SDNPMemOperand]>;
96 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
97 [SDNPHasChain, SDNPMayStore,
98 SDNPMayLoad, SDNPMemOperand]>;
99 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
100 [SDNPHasChain, SDNPMayStore,
101 SDNPMayLoad, SDNPMemOperand]>;
102 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
103 [SDNPHasChain, SDNPMayStore,
104 SDNPMayLoad, SDNPMemOperand]>;
105 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
106 [SDNPHasChain, SDNPMayStore,
107 SDNPMayLoad, SDNPMemOperand]>;
108 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
109 [SDNPHasChain, SDNPMayStore,
110 SDNPMayLoad, SDNPMemOperand]>;
111 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
112 [SDNPHasChain, SDNPMayStore,
113 SDNPMayLoad, SDNPMemOperand]>;
114 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
115 [SDNPHasChain, SDNPOptInFlag]>;
117 def X86callseq_start :
118 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
119 [SDNPHasChain, SDNPOutFlag]>;
121 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
122 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
124 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
125 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
127 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
128 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
130 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
131 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
132 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
133 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
136 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
137 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
139 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
140 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
142 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
143 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
144 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
145 SDT_X86SegmentBaseAddress, []>;
147 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
150 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
151 [SDNPHasChain, SDNPOptInFlag]>;
153 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags>;
154 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
155 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags>;
156 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>;
157 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
158 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
160 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
162 //===----------------------------------------------------------------------===//
163 // X86 Operand Definitions.
166 // *mem - Operand definitions for the funky X86 addressing mode operands.
168 class X86MemOperand<string printMethod> : Operand<iPTR> {
169 let PrintMethod = printMethod;
170 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm);
173 def i8mem : X86MemOperand<"printi8mem">;
174 def i16mem : X86MemOperand<"printi16mem">;
175 def i32mem : X86MemOperand<"printi32mem">;
176 def i64mem : X86MemOperand<"printi64mem">;
177 def i128mem : X86MemOperand<"printi128mem">;
178 def f32mem : X86MemOperand<"printf32mem">;
179 def f64mem : X86MemOperand<"printf64mem">;
180 def f80mem : X86MemOperand<"printf80mem">;
181 def f128mem : X86MemOperand<"printf128mem">;
183 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
184 // plain GR64, so that it doesn't potentially require a REX prefix.
185 def i8mem_NOREX : Operand<i64> {
186 let PrintMethod = "printi8mem";
187 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX, i32imm, i8imm);
190 def lea32mem : Operand<i32> {
191 let PrintMethod = "printlea32mem";
192 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
195 def SSECC : Operand<i8> {
196 let PrintMethod = "printSSECC";
199 def piclabel: Operand<i32> {
200 let PrintMethod = "printPICLabel";
203 // A couple of more descriptive operand definitions.
204 // 16-bits but only 8 bits are significant.
205 def i16i8imm : Operand<i16>;
206 // 32-bits but only 8 bits are significant.
207 def i32i8imm : Operand<i32>;
209 // Branch targets have OtherVT type.
210 def brtarget : Operand<OtherVT>;
212 //===----------------------------------------------------------------------===//
213 // X86 Complex Pattern Definitions.
216 // Define X86 specific addressing mode.
217 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
218 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
219 [add, sub, mul, shl, or, frameindex], []>;
221 //===----------------------------------------------------------------------===//
222 // X86 Instruction Predicate Definitions.
223 def HasMMX : Predicate<"Subtarget->hasMMX()">;
224 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
225 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
226 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
227 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
228 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
229 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
230 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
231 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
232 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
233 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
234 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
235 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
236 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
237 def OptForSpeed : Predicate<"!OptForSize">;
238 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
239 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
241 //===----------------------------------------------------------------------===//
242 // X86 Instruction Format Definitions.
245 include "X86InstrFormats.td"
247 //===----------------------------------------------------------------------===//
248 // Pattern fragments...
251 // X86 specific condition code. These correspond to CondCode in
252 // X86InstrInfo.h. They must be kept in synch.
253 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
254 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
255 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
256 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
257 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
258 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
259 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
260 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
261 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
262 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
263 def X86_COND_NO : PatLeaf<(i8 10)>;
264 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
265 def X86_COND_NS : PatLeaf<(i8 12)>;
266 def X86_COND_O : PatLeaf<(i8 13)>;
267 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
268 def X86_COND_S : PatLeaf<(i8 15)>;
270 def i16immSExt8 : PatLeaf<(i16 imm), [{
271 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
272 // sign extended field.
273 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
276 def i32immSExt8 : PatLeaf<(i32 imm), [{
277 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
278 // sign extended field.
279 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
282 // Helper fragments for loads.
283 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
284 // known to be 32-bit aligned or better. Ditto for i8 to i16.
285 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
286 LoadSDNode *LD = cast<LoadSDNode>(N);
287 if (const Value *Src = LD->getSrcValue())
288 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
289 if (PT->getAddressSpace() > 255)
291 ISD::LoadExtType ExtType = LD->getExtensionType();
292 if (ExtType == ISD::NON_EXTLOAD)
294 if (ExtType == ISD::EXTLOAD)
295 return LD->getAlignment() >= 2 && !LD->isVolatile();
299 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
300 LoadSDNode *LD = cast<LoadSDNode>(N);
301 if (const Value *Src = LD->getSrcValue())
302 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
303 if (PT->getAddressSpace() > 255)
305 ISD::LoadExtType ExtType = LD->getExtensionType();
306 if (ExtType == ISD::EXTLOAD)
307 return LD->getAlignment() >= 2 && !LD->isVolatile();
311 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
312 LoadSDNode *LD = cast<LoadSDNode>(N);
313 if (const Value *Src = LD->getSrcValue())
314 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
315 if (PT->getAddressSpace() > 255)
317 ISD::LoadExtType ExtType = LD->getExtensionType();
318 if (ExtType == ISD::NON_EXTLOAD)
320 if (ExtType == ISD::EXTLOAD)
321 return LD->getAlignment() >= 4 && !LD->isVolatile();
325 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
326 LoadSDNode *LD = cast<LoadSDNode>(N);
327 if (const Value *Src = LD->getSrcValue())
328 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
329 if (PT->getAddressSpace() > 255)
331 if (LD->isVolatile())
333 ISD::LoadExtType ExtType = LD->getExtensionType();
334 if (ExtType == ISD::NON_EXTLOAD)
336 if (ExtType == ISD::EXTLOAD)
337 return LD->getAlignment() >= 4;
341 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
342 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
343 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
344 return PT->getAddressSpace() == 256;
348 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
349 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
350 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
351 return PT->getAddressSpace() == 257;
355 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{
356 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
357 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
358 if (PT->getAddressSpace() > 255)
362 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{
363 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
364 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
365 if (PT->getAddressSpace() > 255)
370 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{
371 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
372 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
373 if (PT->getAddressSpace() > 255)
377 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{
378 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
379 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
380 if (PT->getAddressSpace() > 255)
384 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{
385 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
386 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
387 if (PT->getAddressSpace() > 255)
392 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
393 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
394 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
396 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
397 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
398 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
399 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
400 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
401 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
403 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
404 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
405 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
406 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
407 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
408 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
411 // An 'and' node with a single use.
412 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
413 return N->hasOneUse();
415 // An 'srl' node with a single use.
416 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
417 return N->hasOneUse();
419 // An 'trunc' node with a single use.
420 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
421 return N->hasOneUse();
424 // 'shld' and 'shrd' instruction patterns. Note that even though these have
425 // the srl and shl in their patterns, the C++ code must still check for them,
426 // because predicates are tested before children nodes are explored.
428 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
429 (or (srl node:$src1, node:$amt1),
430 (shl node:$src2, node:$amt2)), [{
431 assert(N->getOpcode() == ISD::OR);
432 return N->getOperand(0).getOpcode() == ISD::SRL &&
433 N->getOperand(1).getOpcode() == ISD::SHL &&
434 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
435 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
436 N->getOperand(0).getConstantOperandVal(1) ==
437 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
440 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
441 (or (shl node:$src1, node:$amt1),
442 (srl node:$src2, node:$amt2)), [{
443 assert(N->getOpcode() == ISD::OR);
444 return N->getOperand(0).getOpcode() == ISD::SHL &&
445 N->getOperand(1).getOpcode() == ISD::SRL &&
446 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
447 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
448 N->getOperand(0).getConstantOperandVal(1) ==
449 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
452 //===----------------------------------------------------------------------===//
453 // Instruction list...
456 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
457 // a stack adjustment and the codegen must know that they may modify the stack
458 // pointer before prolog-epilog rewriting occurs.
459 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
460 // sub / add which can clobber EFLAGS.
461 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
462 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
464 [(X86callseq_start timm:$amt)]>,
465 Requires<[In32BitMode]>;
466 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
468 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
469 Requires<[In32BitMode]>;
473 let neverHasSideEffects = 1 in
474 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
477 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
478 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
482 //===----------------------------------------------------------------------===//
483 // Control Flow Instructions...
486 // Return instructions.
487 let isTerminator = 1, isReturn = 1, isBarrier = 1,
488 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
489 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
492 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
494 [(X86retflag imm:$amt)]>;
497 // All branches are RawFrm, Void, Branch, and Terminators
498 let isBranch = 1, isTerminator = 1 in
499 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
500 I<opcode, RawFrm, (outs), ins, asm, pattern>;
502 let isBranch = 1, isBarrier = 1 in
503 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
506 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
507 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
508 [(brind GR32:$dst)]>;
509 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
510 [(brind (loadi32 addr:$dst))]>;
513 // Conditional branches
514 let Uses = [EFLAGS] in {
515 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
516 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
517 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
518 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
519 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
520 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
521 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
522 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
523 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
524 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
525 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
526 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
528 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
529 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
530 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
531 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
532 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
533 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
534 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
535 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
537 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
538 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
539 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
540 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
541 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
542 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
543 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
544 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
545 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
546 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
547 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
548 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
551 //===----------------------------------------------------------------------===//
552 // Call Instructions...
555 // All calls clobber the non-callee saved registers. ESP is marked as
556 // a use to prevent stack-pointer assignments that appear immediately
557 // before calls from potentially appearing dead. Uses for argument
558 // registers are added manually.
559 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
560 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
561 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
562 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
564 def CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops),
565 "call\t${dst:call}", []>;
566 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
567 "call\t{*}$dst", [(X86call GR32:$dst)]>;
568 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
569 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
574 def TAILCALL : I<0, Pseudo, (outs), (ins),
578 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
579 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
580 "#TC_RETURN $dst $offset",
583 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
584 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
585 "#TC_RETURN $dst $offset",
588 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
590 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL",
592 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
593 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
595 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
596 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
597 "jmp\t{*}$dst # TAILCALL", []>;
599 //===----------------------------------------------------------------------===//
600 // Miscellaneous Instructions...
602 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
603 def LEAVE : I<0xC9, RawFrm,
604 (outs), (ins), "leave", []>;
606 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
608 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
611 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
614 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
615 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
616 "push{l}\t$imm", []>;
617 def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
618 "push{l}\t$imm", []>;
619 def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
620 "push{l}\t$imm", []>;
623 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
624 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
625 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
626 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
628 let isTwoAddress = 1 in // GR32 = bswap GR32
629 def BSWAP32r : I<0xC8, AddRegFrm,
630 (outs GR32:$dst), (ins GR32:$src),
632 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
635 // Bit scan instructions.
636 let Defs = [EFLAGS] in {
637 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
638 "bsf{w}\t{$src, $dst|$dst, $src}",
639 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
640 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
641 "bsf{w}\t{$src, $dst|$dst, $src}",
642 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
643 (implicit EFLAGS)]>, TB;
644 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
645 "bsf{l}\t{$src, $dst|$dst, $src}",
646 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
647 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
648 "bsf{l}\t{$src, $dst|$dst, $src}",
649 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
650 (implicit EFLAGS)]>, TB;
652 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
653 "bsr{w}\t{$src, $dst|$dst, $src}",
654 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
655 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
656 "bsr{w}\t{$src, $dst|$dst, $src}",
657 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
658 (implicit EFLAGS)]>, TB;
659 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
660 "bsr{l}\t{$src, $dst|$dst, $src}",
661 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
662 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
663 "bsr{l}\t{$src, $dst|$dst, $src}",
664 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
665 (implicit EFLAGS)]>, TB;
668 let neverHasSideEffects = 1 in
669 def LEA16r : I<0x8D, MRMSrcMem,
670 (outs GR16:$dst), (ins i32mem:$src),
671 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
672 let isReMaterializable = 1 in
673 def LEA32r : I<0x8D, MRMSrcMem,
674 (outs GR32:$dst), (ins lea32mem:$src),
675 "lea{l}\t{$src|$dst}, {$dst|$src}",
676 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
678 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
679 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
680 [(X86rep_movs i8)]>, REP;
681 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
682 [(X86rep_movs i16)]>, REP, OpSize;
683 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
684 [(X86rep_movs i32)]>, REP;
687 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
688 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
689 [(X86rep_stos i8)]>, REP;
690 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
691 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
692 [(X86rep_stos i16)]>, REP, OpSize;
693 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
694 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
695 [(X86rep_stos i32)]>, REP;
697 let Defs = [RAX, RDX] in
698 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
701 let isBarrier = 1, hasCtrlDep = 1 in {
702 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
705 //===----------------------------------------------------------------------===//
706 // Input/Output Instructions...
708 let Defs = [AL], Uses = [DX] in
709 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
710 "in{b}\t{%dx, %al|%AL, %DX}", []>;
711 let Defs = [AX], Uses = [DX] in
712 def IN16rr : I<0xED, RawFrm, (outs), (ins),
713 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
714 let Defs = [EAX], Uses = [DX] in
715 def IN32rr : I<0xED, RawFrm, (outs), (ins),
716 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
719 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
720 "in{b}\t{$port, %al|%AL, $port}", []>;
722 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
723 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
725 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
726 "in{l}\t{$port, %eax|%EAX, $port}", []>;
728 let Uses = [DX, AL] in
729 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
730 "out{b}\t{%al, %dx|%DX, %AL}", []>;
731 let Uses = [DX, AX] in
732 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
733 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
734 let Uses = [DX, EAX] in
735 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
736 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
739 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
740 "out{b}\t{%al, $port|$port, %AL}", []>;
742 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
743 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
745 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
746 "out{l}\t{%eax, $port|$port, %EAX}", []>;
748 //===----------------------------------------------------------------------===//
749 // Move Instructions...
751 let neverHasSideEffects = 1 in {
752 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
753 "mov{b}\t{$src, $dst|$dst, $src}", []>;
754 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
755 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
756 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
757 "mov{l}\t{$src, $dst|$dst, $src}", []>;
759 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
760 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
761 "mov{b}\t{$src, $dst|$dst, $src}",
762 [(set GR8:$dst, imm:$src)]>;
763 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
764 "mov{w}\t{$src, $dst|$dst, $src}",
765 [(set GR16:$dst, imm:$src)]>, OpSize;
766 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
767 "mov{l}\t{$src, $dst|$dst, $src}",
768 [(set GR32:$dst, imm:$src)]>;
770 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
771 "mov{b}\t{$src, $dst|$dst, $src}",
772 [(store (i8 imm:$src), addr:$dst)]>;
773 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
774 "mov{w}\t{$src, $dst|$dst, $src}",
775 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
776 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
777 "mov{l}\t{$src, $dst|$dst, $src}",
778 [(store (i32 imm:$src), addr:$dst)]>;
780 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
781 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
782 "mov{b}\t{$src, $dst|$dst, $src}",
783 [(set GR8:$dst, (loadi8 addr:$src))]>;
784 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
785 "mov{w}\t{$src, $dst|$dst, $src}",
786 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
787 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
788 "mov{l}\t{$src, $dst|$dst, $src}",
789 [(set GR32:$dst, (loadi32 addr:$src))]>;
792 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
793 "mov{b}\t{$src, $dst|$dst, $src}",
794 [(store GR8:$src, addr:$dst)]>;
795 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
796 "mov{w}\t{$src, $dst|$dst, $src}",
797 [(store GR16:$src, addr:$dst)]>, OpSize;
798 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
799 "mov{l}\t{$src, $dst|$dst, $src}",
800 [(store GR32:$src, addr:$dst)]>;
802 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
803 // that they can be used for copying and storing h registers, which can't be
804 // encoded when a REX prefix is present.
805 let neverHasSideEffects = 1 in
806 def MOV8rr_NOREX : I<0x88, MRMDestReg,
807 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
808 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
810 def MOV8mr_NOREX : I<0x88, MRMDestMem,
811 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
812 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
814 canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
815 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
816 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
817 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
819 //===----------------------------------------------------------------------===//
820 // Fixed-Register Multiplication and Division Instructions...
823 // Extra precision multiplication
824 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
825 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
826 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
827 // This probably ought to be moved to a def : Pat<> if the
828 // syntax can be accepted.
829 [(set AL, (mul AL, GR8:$src)),
830 (implicit EFLAGS)]>; // AL,AH = AL*GR8
832 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
833 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
835 []>, OpSize; // AX,DX = AX*GR16
837 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
838 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
840 []>; // EAX,EDX = EAX*GR32
842 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
843 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
845 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
846 // This probably ought to be moved to a def : Pat<> if the
847 // syntax can be accepted.
848 [(set AL, (mul AL, (loadi8 addr:$src))),
849 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
851 let mayLoad = 1, neverHasSideEffects = 1 in {
852 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
853 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
855 []>, OpSize; // AX,DX = AX*[mem16]
857 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
858 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
860 []>; // EAX,EDX = EAX*[mem32]
863 let neverHasSideEffects = 1 in {
864 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
865 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
867 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
868 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
869 OpSize; // AX,DX = AX*GR16
870 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
871 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
872 // EAX,EDX = EAX*GR32
874 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
875 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
876 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
877 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
878 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
879 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
880 let Defs = [EAX,EDX], Uses = [EAX] in
881 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
882 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
884 } // neverHasSideEffects
886 // unsigned division/remainder
887 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
888 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
890 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
891 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
892 "div{w}\t$src", []>, OpSize;
893 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
894 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
897 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
898 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
900 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
901 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
902 "div{w}\t$src", []>, OpSize;
903 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
904 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
908 // Signed division/remainder.
909 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
910 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
911 "idiv{b}\t$src", []>;
912 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
913 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
914 "idiv{w}\t$src", []>, OpSize;
915 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
916 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
917 "idiv{l}\t$src", []>;
918 let mayLoad = 1, mayLoad = 1 in {
919 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
920 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
921 "idiv{b}\t$src", []>;
922 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
923 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
924 "idiv{w}\t$src", []>, OpSize;
925 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
926 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
927 "idiv{l}\t$src", []>;
930 //===----------------------------------------------------------------------===//
931 // Two address Instructions.
933 let isTwoAddress = 1 in {
936 let Uses = [EFLAGS] in {
937 let isCommutable = 1 in {
938 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
939 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
940 "cmovb\t{$src2, $dst|$dst, $src2}",
941 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
942 X86_COND_B, EFLAGS))]>,
944 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
945 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
946 "cmovb\t{$src2, $dst|$dst, $src2}",
947 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
948 X86_COND_B, EFLAGS))]>,
950 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
951 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
952 "cmovae\t{$src2, $dst|$dst, $src2}",
953 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
954 X86_COND_AE, EFLAGS))]>,
956 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
957 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
958 "cmovae\t{$src2, $dst|$dst, $src2}",
959 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
960 X86_COND_AE, EFLAGS))]>,
962 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
963 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
964 "cmove\t{$src2, $dst|$dst, $src2}",
965 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
966 X86_COND_E, EFLAGS))]>,
968 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
969 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
970 "cmove\t{$src2, $dst|$dst, $src2}",
971 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
972 X86_COND_E, EFLAGS))]>,
974 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
975 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
976 "cmovne\t{$src2, $dst|$dst, $src2}",
977 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
978 X86_COND_NE, EFLAGS))]>,
980 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
981 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
982 "cmovne\t{$src2, $dst|$dst, $src2}",
983 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
984 X86_COND_NE, EFLAGS))]>,
986 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
987 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
988 "cmovbe\t{$src2, $dst|$dst, $src2}",
989 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
990 X86_COND_BE, EFLAGS))]>,
992 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
993 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
994 "cmovbe\t{$src2, $dst|$dst, $src2}",
995 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
996 X86_COND_BE, EFLAGS))]>,
998 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
999 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1000 "cmova\t{$src2, $dst|$dst, $src2}",
1001 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1002 X86_COND_A, EFLAGS))]>,
1004 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1005 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1006 "cmova\t{$src2, $dst|$dst, $src2}",
1007 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1008 X86_COND_A, EFLAGS))]>,
1010 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1011 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1012 "cmovl\t{$src2, $dst|$dst, $src2}",
1013 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1014 X86_COND_L, EFLAGS))]>,
1016 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1017 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1018 "cmovl\t{$src2, $dst|$dst, $src2}",
1019 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1020 X86_COND_L, EFLAGS))]>,
1022 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1023 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1024 "cmovge\t{$src2, $dst|$dst, $src2}",
1025 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1026 X86_COND_GE, EFLAGS))]>,
1028 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1029 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1030 "cmovge\t{$src2, $dst|$dst, $src2}",
1031 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1032 X86_COND_GE, EFLAGS))]>,
1034 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1035 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1036 "cmovle\t{$src2, $dst|$dst, $src2}",
1037 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1038 X86_COND_LE, EFLAGS))]>,
1040 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1041 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1042 "cmovle\t{$src2, $dst|$dst, $src2}",
1043 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1044 X86_COND_LE, EFLAGS))]>,
1046 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1047 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1048 "cmovg\t{$src2, $dst|$dst, $src2}",
1049 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1050 X86_COND_G, EFLAGS))]>,
1052 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1053 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1054 "cmovg\t{$src2, $dst|$dst, $src2}",
1055 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1056 X86_COND_G, EFLAGS))]>,
1058 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1059 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1060 "cmovs\t{$src2, $dst|$dst, $src2}",
1061 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1062 X86_COND_S, EFLAGS))]>,
1064 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1065 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1066 "cmovs\t{$src2, $dst|$dst, $src2}",
1067 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1068 X86_COND_S, EFLAGS))]>,
1070 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1071 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1072 "cmovns\t{$src2, $dst|$dst, $src2}",
1073 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1074 X86_COND_NS, EFLAGS))]>,
1076 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1077 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1078 "cmovns\t{$src2, $dst|$dst, $src2}",
1079 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1080 X86_COND_NS, EFLAGS))]>,
1082 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1083 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1084 "cmovp\t{$src2, $dst|$dst, $src2}",
1085 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1086 X86_COND_P, EFLAGS))]>,
1088 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1089 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1090 "cmovp\t{$src2, $dst|$dst, $src2}",
1091 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1092 X86_COND_P, EFLAGS))]>,
1094 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1095 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1096 "cmovnp\t{$src2, $dst|$dst, $src2}",
1097 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1098 X86_COND_NP, EFLAGS))]>,
1100 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1101 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1102 "cmovnp\t{$src2, $dst|$dst, $src2}",
1103 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1104 X86_COND_NP, EFLAGS))]>,
1106 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1107 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1108 "cmovo\t{$src2, $dst|$dst, $src2}",
1109 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1110 X86_COND_O, EFLAGS))]>,
1112 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1113 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1114 "cmovo\t{$src2, $dst|$dst, $src2}",
1115 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1116 X86_COND_O, EFLAGS))]>,
1118 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1119 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1120 "cmovno\t{$src2, $dst|$dst, $src2}",
1121 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1122 X86_COND_NO, EFLAGS))]>,
1124 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1125 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1126 "cmovno\t{$src2, $dst|$dst, $src2}",
1127 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1128 X86_COND_NO, EFLAGS))]>,
1130 } // isCommutable = 1
1132 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1133 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1134 "cmovb\t{$src2, $dst|$dst, $src2}",
1135 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1136 X86_COND_B, EFLAGS))]>,
1138 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1139 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1140 "cmovb\t{$src2, $dst|$dst, $src2}",
1141 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1142 X86_COND_B, EFLAGS))]>,
1144 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1145 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1146 "cmovae\t{$src2, $dst|$dst, $src2}",
1147 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1148 X86_COND_AE, EFLAGS))]>,
1150 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1151 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1152 "cmovae\t{$src2, $dst|$dst, $src2}",
1153 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1154 X86_COND_AE, EFLAGS))]>,
1156 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1157 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1158 "cmove\t{$src2, $dst|$dst, $src2}",
1159 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1160 X86_COND_E, EFLAGS))]>,
1162 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1163 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1164 "cmove\t{$src2, $dst|$dst, $src2}",
1165 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1166 X86_COND_E, EFLAGS))]>,
1168 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1169 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1170 "cmovne\t{$src2, $dst|$dst, $src2}",
1171 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1172 X86_COND_NE, EFLAGS))]>,
1174 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1175 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1176 "cmovne\t{$src2, $dst|$dst, $src2}",
1177 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1178 X86_COND_NE, EFLAGS))]>,
1180 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1181 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1182 "cmovbe\t{$src2, $dst|$dst, $src2}",
1183 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1184 X86_COND_BE, EFLAGS))]>,
1186 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1187 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1188 "cmovbe\t{$src2, $dst|$dst, $src2}",
1189 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1190 X86_COND_BE, EFLAGS))]>,
1192 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1193 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1194 "cmova\t{$src2, $dst|$dst, $src2}",
1195 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1196 X86_COND_A, EFLAGS))]>,
1198 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1199 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1200 "cmova\t{$src2, $dst|$dst, $src2}",
1201 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1202 X86_COND_A, EFLAGS))]>,
1204 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1205 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1206 "cmovl\t{$src2, $dst|$dst, $src2}",
1207 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1208 X86_COND_L, EFLAGS))]>,
1210 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1211 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1212 "cmovl\t{$src2, $dst|$dst, $src2}",
1213 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1214 X86_COND_L, EFLAGS))]>,
1216 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1217 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1218 "cmovge\t{$src2, $dst|$dst, $src2}",
1219 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1220 X86_COND_GE, EFLAGS))]>,
1222 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1223 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1224 "cmovge\t{$src2, $dst|$dst, $src2}",
1225 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1226 X86_COND_GE, EFLAGS))]>,
1228 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1229 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1230 "cmovle\t{$src2, $dst|$dst, $src2}",
1231 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1232 X86_COND_LE, EFLAGS))]>,
1234 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1235 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1236 "cmovle\t{$src2, $dst|$dst, $src2}",
1237 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1238 X86_COND_LE, EFLAGS))]>,
1240 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1241 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1242 "cmovg\t{$src2, $dst|$dst, $src2}",
1243 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1244 X86_COND_G, EFLAGS))]>,
1246 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1247 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1248 "cmovg\t{$src2, $dst|$dst, $src2}",
1249 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1250 X86_COND_G, EFLAGS))]>,
1252 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1253 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1254 "cmovs\t{$src2, $dst|$dst, $src2}",
1255 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1256 X86_COND_S, EFLAGS))]>,
1258 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1259 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1260 "cmovs\t{$src2, $dst|$dst, $src2}",
1261 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1262 X86_COND_S, EFLAGS))]>,
1264 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1265 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1266 "cmovns\t{$src2, $dst|$dst, $src2}",
1267 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1268 X86_COND_NS, EFLAGS))]>,
1270 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1271 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1272 "cmovns\t{$src2, $dst|$dst, $src2}",
1273 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1274 X86_COND_NS, EFLAGS))]>,
1276 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1277 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1278 "cmovp\t{$src2, $dst|$dst, $src2}",
1279 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1280 X86_COND_P, EFLAGS))]>,
1282 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1283 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1284 "cmovp\t{$src2, $dst|$dst, $src2}",
1285 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1286 X86_COND_P, EFLAGS))]>,
1288 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1289 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1290 "cmovnp\t{$src2, $dst|$dst, $src2}",
1291 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1292 X86_COND_NP, EFLAGS))]>,
1294 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1295 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1296 "cmovnp\t{$src2, $dst|$dst, $src2}",
1297 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1298 X86_COND_NP, EFLAGS))]>,
1300 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1301 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1302 "cmovo\t{$src2, $dst|$dst, $src2}",
1303 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1304 X86_COND_O, EFLAGS))]>,
1306 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1307 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1308 "cmovo\t{$src2, $dst|$dst, $src2}",
1309 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1310 X86_COND_O, EFLAGS))]>,
1312 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1313 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1314 "cmovno\t{$src2, $dst|$dst, $src2}",
1315 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1316 X86_COND_NO, EFLAGS))]>,
1318 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1319 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1320 "cmovno\t{$src2, $dst|$dst, $src2}",
1321 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1322 X86_COND_NO, EFLAGS))]>,
1324 } // Uses = [EFLAGS]
1327 // unary instructions
1328 let CodeSize = 2 in {
1329 let Defs = [EFLAGS] in {
1330 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1331 [(set GR8:$dst, (ineg GR8:$src)),
1332 (implicit EFLAGS)]>;
1333 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1334 [(set GR16:$dst, (ineg GR16:$src)),
1335 (implicit EFLAGS)]>, OpSize;
1336 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1337 [(set GR32:$dst, (ineg GR32:$src)),
1338 (implicit EFLAGS)]>;
1339 let isTwoAddress = 0 in {
1340 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1341 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1342 (implicit EFLAGS)]>;
1343 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1344 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1345 (implicit EFLAGS)]>, OpSize;
1346 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1347 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1348 (implicit EFLAGS)]>;
1350 } // Defs = [EFLAGS]
1352 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1353 let AddedComplexity = 15 in {
1354 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1355 [(set GR8:$dst, (not GR8:$src))]>;
1356 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1357 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1358 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1359 [(set GR32:$dst, (not GR32:$src))]>;
1361 let isTwoAddress = 0 in {
1362 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1363 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1364 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1365 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1366 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1367 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1371 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1372 let Defs = [EFLAGS] in {
1374 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1375 [(set GR8:$dst, (add GR8:$src, 1)),
1376 (implicit EFLAGS)]>;
1377 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1378 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1379 [(set GR16:$dst, (add GR16:$src, 1)),
1380 (implicit EFLAGS)]>,
1381 OpSize, Requires<[In32BitMode]>;
1382 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1383 [(set GR32:$dst, (add GR32:$src, 1)),
1384 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1386 let isTwoAddress = 0, CodeSize = 2 in {
1387 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1388 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1389 (implicit EFLAGS)]>;
1390 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1391 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1392 (implicit EFLAGS)]>,
1393 OpSize, Requires<[In32BitMode]>;
1394 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1395 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1396 (implicit EFLAGS)]>,
1397 Requires<[In32BitMode]>;
1401 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1402 [(set GR8:$dst, (add GR8:$src, -1)),
1403 (implicit EFLAGS)]>;
1404 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1405 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1406 [(set GR16:$dst, (add GR16:$src, -1)),
1407 (implicit EFLAGS)]>,
1408 OpSize, Requires<[In32BitMode]>;
1409 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1410 [(set GR32:$dst, (add GR32:$src, -1)),
1411 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1414 let isTwoAddress = 0, CodeSize = 2 in {
1415 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1416 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1417 (implicit EFLAGS)]>;
1418 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1419 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1420 (implicit EFLAGS)]>,
1421 OpSize, Requires<[In32BitMode]>;
1422 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1423 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1424 (implicit EFLAGS)]>,
1425 Requires<[In32BitMode]>;
1427 } // Defs = [EFLAGS]
1429 // Logical operators...
1430 let Defs = [EFLAGS] in {
1431 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1432 def AND8rr : I<0x20, MRMDestReg,
1433 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1434 "and{b}\t{$src2, $dst|$dst, $src2}",
1435 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1436 (implicit EFLAGS)]>;
1437 def AND16rr : I<0x21, MRMDestReg,
1438 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1439 "and{w}\t{$src2, $dst|$dst, $src2}",
1440 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1441 (implicit EFLAGS)]>, OpSize;
1442 def AND32rr : I<0x21, MRMDestReg,
1443 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1444 "and{l}\t{$src2, $dst|$dst, $src2}",
1445 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1446 (implicit EFLAGS)]>;
1449 def AND8rm : I<0x22, MRMSrcMem,
1450 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1451 "and{b}\t{$src2, $dst|$dst, $src2}",
1452 [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
1453 (implicit EFLAGS)]>;
1454 def AND16rm : I<0x23, MRMSrcMem,
1455 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1456 "and{w}\t{$src2, $dst|$dst, $src2}",
1457 [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
1458 (implicit EFLAGS)]>, OpSize;
1459 def AND32rm : I<0x23, MRMSrcMem,
1460 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1461 "and{l}\t{$src2, $dst|$dst, $src2}",
1462 [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
1463 (implicit EFLAGS)]>;
1465 def AND8ri : Ii8<0x80, MRM4r,
1466 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1467 "and{b}\t{$src2, $dst|$dst, $src2}",
1468 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1469 (implicit EFLAGS)]>;
1470 def AND16ri : Ii16<0x81, MRM4r,
1471 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1472 "and{w}\t{$src2, $dst|$dst, $src2}",
1473 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1474 (implicit EFLAGS)]>, OpSize;
1475 def AND32ri : Ii32<0x81, MRM4r,
1476 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1477 "and{l}\t{$src2, $dst|$dst, $src2}",
1478 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1479 (implicit EFLAGS)]>;
1480 def AND16ri8 : Ii8<0x83, MRM4r,
1481 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1482 "and{w}\t{$src2, $dst|$dst, $src2}",
1483 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1484 (implicit EFLAGS)]>,
1486 def AND32ri8 : Ii8<0x83, MRM4r,
1487 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1488 "and{l}\t{$src2, $dst|$dst, $src2}",
1489 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1490 (implicit EFLAGS)]>;
1492 let isTwoAddress = 0 in {
1493 def AND8mr : I<0x20, MRMDestMem,
1494 (outs), (ins i8mem :$dst, GR8 :$src),
1495 "and{b}\t{$src, $dst|$dst, $src}",
1496 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1497 (implicit EFLAGS)]>;
1498 def AND16mr : I<0x21, MRMDestMem,
1499 (outs), (ins i16mem:$dst, GR16:$src),
1500 "and{w}\t{$src, $dst|$dst, $src}",
1501 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1502 (implicit EFLAGS)]>,
1504 def AND32mr : I<0x21, MRMDestMem,
1505 (outs), (ins i32mem:$dst, GR32:$src),
1506 "and{l}\t{$src, $dst|$dst, $src}",
1507 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1508 (implicit EFLAGS)]>;
1509 def AND8mi : Ii8<0x80, MRM4m,
1510 (outs), (ins i8mem :$dst, i8imm :$src),
1511 "and{b}\t{$src, $dst|$dst, $src}",
1512 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1513 (implicit EFLAGS)]>;
1514 def AND16mi : Ii16<0x81, MRM4m,
1515 (outs), (ins i16mem:$dst, i16imm:$src),
1516 "and{w}\t{$src, $dst|$dst, $src}",
1517 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1518 (implicit EFLAGS)]>,
1520 def AND32mi : Ii32<0x81, MRM4m,
1521 (outs), (ins i32mem:$dst, i32imm:$src),
1522 "and{l}\t{$src, $dst|$dst, $src}",
1523 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1524 (implicit EFLAGS)]>;
1525 def AND16mi8 : Ii8<0x83, MRM4m,
1526 (outs), (ins i16mem:$dst, i16i8imm :$src),
1527 "and{w}\t{$src, $dst|$dst, $src}",
1528 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1529 (implicit EFLAGS)]>,
1531 def AND32mi8 : Ii8<0x83, MRM4m,
1532 (outs), (ins i32mem:$dst, i32i8imm :$src),
1533 "and{l}\t{$src, $dst|$dst, $src}",
1534 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1535 (implicit EFLAGS)]>;
1539 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1540 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1541 "or{b}\t{$src2, $dst|$dst, $src2}",
1542 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1543 (implicit EFLAGS)]>;
1544 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1545 "or{w}\t{$src2, $dst|$dst, $src2}",
1546 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1547 (implicit EFLAGS)]>, OpSize;
1548 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1549 "or{l}\t{$src2, $dst|$dst, $src2}",
1550 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1551 (implicit EFLAGS)]>;
1553 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1554 "or{b}\t{$src2, $dst|$dst, $src2}",
1555 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1556 (implicit EFLAGS)]>;
1557 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1558 "or{w}\t{$src2, $dst|$dst, $src2}",
1559 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1560 (implicit EFLAGS)]>, OpSize;
1561 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1562 "or{l}\t{$src2, $dst|$dst, $src2}",
1563 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1564 (implicit EFLAGS)]>;
1566 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1567 "or{b}\t{$src2, $dst|$dst, $src2}",
1568 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
1569 (implicit EFLAGS)]>;
1570 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1571 "or{w}\t{$src2, $dst|$dst, $src2}",
1572 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
1573 (implicit EFLAGS)]>, OpSize;
1574 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1575 "or{l}\t{$src2, $dst|$dst, $src2}",
1576 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
1577 (implicit EFLAGS)]>;
1579 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1580 "or{w}\t{$src2, $dst|$dst, $src2}",
1581 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
1582 (implicit EFLAGS)]>, OpSize;
1583 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1584 "or{l}\t{$src2, $dst|$dst, $src2}",
1585 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
1586 (implicit EFLAGS)]>;
1587 let isTwoAddress = 0 in {
1588 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1589 "or{b}\t{$src, $dst|$dst, $src}",
1590 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1591 (implicit EFLAGS)]>;
1592 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1593 "or{w}\t{$src, $dst|$dst, $src}",
1594 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1595 (implicit EFLAGS)]>, OpSize;
1596 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1597 "or{l}\t{$src, $dst|$dst, $src}",
1598 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1599 (implicit EFLAGS)]>;
1600 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1601 "or{b}\t{$src, $dst|$dst, $src}",
1602 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1603 (implicit EFLAGS)]>;
1604 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1605 "or{w}\t{$src, $dst|$dst, $src}",
1606 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1607 (implicit EFLAGS)]>,
1609 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1610 "or{l}\t{$src, $dst|$dst, $src}",
1611 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1612 (implicit EFLAGS)]>;
1613 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1614 "or{w}\t{$src, $dst|$dst, $src}",
1615 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1616 (implicit EFLAGS)]>,
1618 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1619 "or{l}\t{$src, $dst|$dst, $src}",
1620 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1621 (implicit EFLAGS)]>;
1622 } // isTwoAddress = 0
1625 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1626 def XOR8rr : I<0x30, MRMDestReg,
1627 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1628 "xor{b}\t{$src2, $dst|$dst, $src2}",
1629 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
1630 (implicit EFLAGS)]>;
1631 def XOR16rr : I<0x31, MRMDestReg,
1632 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1633 "xor{w}\t{$src2, $dst|$dst, $src2}",
1634 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
1635 (implicit EFLAGS)]>, OpSize;
1636 def XOR32rr : I<0x31, MRMDestReg,
1637 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1638 "xor{l}\t{$src2, $dst|$dst, $src2}",
1639 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
1640 (implicit EFLAGS)]>;
1641 } // isCommutable = 1
1643 def XOR8rm : I<0x32, MRMSrcMem ,
1644 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1645 "xor{b}\t{$src2, $dst|$dst, $src2}",
1646 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
1647 (implicit EFLAGS)]>;
1648 def XOR16rm : I<0x33, MRMSrcMem ,
1649 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1650 "xor{w}\t{$src2, $dst|$dst, $src2}",
1651 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
1652 (implicit EFLAGS)]>,
1654 def XOR32rm : I<0x33, MRMSrcMem ,
1655 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1656 "xor{l}\t{$src2, $dst|$dst, $src2}",
1657 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
1658 (implicit EFLAGS)]>;
1660 def XOR8ri : Ii8<0x80, MRM6r,
1661 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1662 "xor{b}\t{$src2, $dst|$dst, $src2}",
1663 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
1664 (implicit EFLAGS)]>;
1665 def XOR16ri : Ii16<0x81, MRM6r,
1666 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1667 "xor{w}\t{$src2, $dst|$dst, $src2}",
1668 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
1669 (implicit EFLAGS)]>, OpSize;
1670 def XOR32ri : Ii32<0x81, MRM6r,
1671 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1672 "xor{l}\t{$src2, $dst|$dst, $src2}",
1673 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
1674 (implicit EFLAGS)]>;
1675 def XOR16ri8 : Ii8<0x83, MRM6r,
1676 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1677 "xor{w}\t{$src2, $dst|$dst, $src2}",
1678 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
1679 (implicit EFLAGS)]>,
1681 def XOR32ri8 : Ii8<0x83, MRM6r,
1682 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1683 "xor{l}\t{$src2, $dst|$dst, $src2}",
1684 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
1685 (implicit EFLAGS)]>;
1687 let isTwoAddress = 0 in {
1688 def XOR8mr : I<0x30, MRMDestMem,
1689 (outs), (ins i8mem :$dst, GR8 :$src),
1690 "xor{b}\t{$src, $dst|$dst, $src}",
1691 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
1692 (implicit EFLAGS)]>;
1693 def XOR16mr : I<0x31, MRMDestMem,
1694 (outs), (ins i16mem:$dst, GR16:$src),
1695 "xor{w}\t{$src, $dst|$dst, $src}",
1696 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
1697 (implicit EFLAGS)]>,
1699 def XOR32mr : I<0x31, MRMDestMem,
1700 (outs), (ins i32mem:$dst, GR32:$src),
1701 "xor{l}\t{$src, $dst|$dst, $src}",
1702 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
1703 (implicit EFLAGS)]>;
1704 def XOR8mi : Ii8<0x80, MRM6m,
1705 (outs), (ins i8mem :$dst, i8imm :$src),
1706 "xor{b}\t{$src, $dst|$dst, $src}",
1707 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
1708 (implicit EFLAGS)]>;
1709 def XOR16mi : Ii16<0x81, MRM6m,
1710 (outs), (ins i16mem:$dst, i16imm:$src),
1711 "xor{w}\t{$src, $dst|$dst, $src}",
1712 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
1713 (implicit EFLAGS)]>,
1715 def XOR32mi : Ii32<0x81, MRM6m,
1716 (outs), (ins i32mem:$dst, i32imm:$src),
1717 "xor{l}\t{$src, $dst|$dst, $src}",
1718 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
1719 (implicit EFLAGS)]>;
1720 def XOR16mi8 : Ii8<0x83, MRM6m,
1721 (outs), (ins i16mem:$dst, i16i8imm :$src),
1722 "xor{w}\t{$src, $dst|$dst, $src}",
1723 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
1724 (implicit EFLAGS)]>,
1726 def XOR32mi8 : Ii8<0x83, MRM6m,
1727 (outs), (ins i32mem:$dst, i32i8imm :$src),
1728 "xor{l}\t{$src, $dst|$dst, $src}",
1729 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
1730 (implicit EFLAGS)]>;
1731 } // isTwoAddress = 0
1732 } // Defs = [EFLAGS]
1734 // Shift instructions
1735 let Defs = [EFLAGS] in {
1736 let Uses = [CL] in {
1737 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1738 "shl{b}\t{%cl, $dst|$dst, %CL}",
1739 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1740 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1741 "shl{w}\t{%cl, $dst|$dst, %CL}",
1742 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1743 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1744 "shl{l}\t{%cl, $dst|$dst, %CL}",
1745 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1748 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1749 "shl{b}\t{$src2, $dst|$dst, $src2}",
1750 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1751 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1752 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1753 "shl{w}\t{$src2, $dst|$dst, $src2}",
1754 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1755 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1756 "shl{l}\t{$src2, $dst|$dst, $src2}",
1757 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1758 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1760 } // isConvertibleToThreeAddress = 1
1762 let isTwoAddress = 0 in {
1763 let Uses = [CL] in {
1764 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1765 "shl{b}\t{%cl, $dst|$dst, %CL}",
1766 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1767 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1768 "shl{w}\t{%cl, $dst|$dst, %CL}",
1769 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1770 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1771 "shl{l}\t{%cl, $dst|$dst, %CL}",
1772 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1774 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1775 "shl{b}\t{$src, $dst|$dst, $src}",
1776 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1777 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1778 "shl{w}\t{$src, $dst|$dst, $src}",
1779 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1781 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1782 "shl{l}\t{$src, $dst|$dst, $src}",
1783 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1786 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1788 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1789 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1791 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1793 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1795 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1798 let Uses = [CL] in {
1799 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1800 "shr{b}\t{%cl, $dst|$dst, %CL}",
1801 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1802 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1803 "shr{w}\t{%cl, $dst|$dst, %CL}",
1804 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1805 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1806 "shr{l}\t{%cl, $dst|$dst, %CL}",
1807 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1810 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1811 "shr{b}\t{$src2, $dst|$dst, $src2}",
1812 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1813 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1814 "shr{w}\t{$src2, $dst|$dst, $src2}",
1815 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1816 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1817 "shr{l}\t{$src2, $dst|$dst, $src2}",
1818 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1821 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1823 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1824 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1826 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1827 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1829 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1831 let isTwoAddress = 0 in {
1832 let Uses = [CL] in {
1833 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1834 "shr{b}\t{%cl, $dst|$dst, %CL}",
1835 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1836 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1837 "shr{w}\t{%cl, $dst|$dst, %CL}",
1838 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1840 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1841 "shr{l}\t{%cl, $dst|$dst, %CL}",
1842 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1844 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1845 "shr{b}\t{$src, $dst|$dst, $src}",
1846 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1847 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1848 "shr{w}\t{$src, $dst|$dst, $src}",
1849 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1851 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1852 "shr{l}\t{$src, $dst|$dst, $src}",
1853 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1856 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1858 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1859 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1861 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1862 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1864 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1867 let Uses = [CL] in {
1868 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1869 "sar{b}\t{%cl, $dst|$dst, %CL}",
1870 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1871 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1872 "sar{w}\t{%cl, $dst|$dst, %CL}",
1873 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1874 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1875 "sar{l}\t{%cl, $dst|$dst, %CL}",
1876 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1879 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1880 "sar{b}\t{$src2, $dst|$dst, $src2}",
1881 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1882 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1883 "sar{w}\t{$src2, $dst|$dst, $src2}",
1884 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1886 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1887 "sar{l}\t{$src2, $dst|$dst, $src2}",
1888 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1891 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1893 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1894 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1896 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1897 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1899 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1901 let isTwoAddress = 0 in {
1902 let Uses = [CL] in {
1903 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1904 "sar{b}\t{%cl, $dst|$dst, %CL}",
1905 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1906 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1907 "sar{w}\t{%cl, $dst|$dst, %CL}",
1908 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1909 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1910 "sar{l}\t{%cl, $dst|$dst, %CL}",
1911 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1913 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1914 "sar{b}\t{$src, $dst|$dst, $src}",
1915 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1916 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1917 "sar{w}\t{$src, $dst|$dst, $src}",
1918 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1920 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1921 "sar{l}\t{$src, $dst|$dst, $src}",
1922 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1925 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1927 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1928 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1930 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1932 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1934 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1937 // Rotate instructions
1938 // FIXME: provide shorter instructions when imm8 == 1
1939 let Uses = [CL] in {
1940 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
1941 "rol{b}\t{%cl, $dst|$dst, %CL}",
1942 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
1943 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
1944 "rol{w}\t{%cl, $dst|$dst, %CL}",
1945 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
1946 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
1947 "rol{l}\t{%cl, $dst|$dst, %CL}",
1948 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
1951 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1952 "rol{b}\t{$src2, $dst|$dst, $src2}",
1953 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1954 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1955 "rol{w}\t{$src2, $dst|$dst, $src2}",
1956 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1957 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1958 "rol{l}\t{$src2, $dst|$dst, $src2}",
1959 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1962 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1964 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1965 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1967 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1968 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1970 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1972 let isTwoAddress = 0 in {
1973 let Uses = [CL] in {
1974 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
1975 "rol{b}\t{%cl, $dst|$dst, %CL}",
1976 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
1977 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
1978 "rol{w}\t{%cl, $dst|$dst, %CL}",
1979 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1980 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
1981 "rol{l}\t{%cl, $dst|$dst, %CL}",
1982 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1984 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
1985 "rol{b}\t{$src, $dst|$dst, $src}",
1986 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1987 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
1988 "rol{w}\t{$src, $dst|$dst, $src}",
1989 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1991 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
1992 "rol{l}\t{$src, $dst|$dst, $src}",
1993 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1996 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
1998 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1999 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2001 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2003 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2005 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2008 let Uses = [CL] in {
2009 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2010 "ror{b}\t{%cl, $dst|$dst, %CL}",
2011 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2012 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2013 "ror{w}\t{%cl, $dst|$dst, %CL}",
2014 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2015 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2016 "ror{l}\t{%cl, $dst|$dst, %CL}",
2017 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2020 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2021 "ror{b}\t{$src2, $dst|$dst, $src2}",
2022 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2023 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2024 "ror{w}\t{$src2, $dst|$dst, $src2}",
2025 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2026 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2027 "ror{l}\t{$src2, $dst|$dst, $src2}",
2028 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2031 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2033 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2034 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2036 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2037 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2039 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2041 let isTwoAddress = 0 in {
2042 let Uses = [CL] in {
2043 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2044 "ror{b}\t{%cl, $dst|$dst, %CL}",
2045 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2046 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2047 "ror{w}\t{%cl, $dst|$dst, %CL}",
2048 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2049 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2050 "ror{l}\t{%cl, $dst|$dst, %CL}",
2051 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2053 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2054 "ror{b}\t{$src, $dst|$dst, $src}",
2055 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2056 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2057 "ror{w}\t{$src, $dst|$dst, $src}",
2058 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2060 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2061 "ror{l}\t{$src, $dst|$dst, $src}",
2062 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2065 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2067 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2068 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2070 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2072 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2074 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2079 // Double shift instructions (generalizations of rotate)
2080 let Uses = [CL] in {
2081 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2082 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2083 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2084 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2085 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2086 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2087 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2088 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2089 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2091 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2092 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2093 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2097 let isCommutable = 1 in { // These instructions commute to each other.
2098 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2099 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2100 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2101 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2104 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2105 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2106 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2107 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2110 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2111 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2112 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2113 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2116 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2117 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2118 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2119 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2124 let isTwoAddress = 0 in {
2125 let Uses = [CL] in {
2126 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2127 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2128 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2130 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2131 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2132 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2135 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2136 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2137 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2138 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2139 (i8 imm:$src3)), addr:$dst)]>,
2141 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2142 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2143 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2144 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2145 (i8 imm:$src3)), addr:$dst)]>,
2148 let Uses = [CL] in {
2149 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2150 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2151 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2152 addr:$dst)]>, TB, OpSize;
2153 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2154 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2155 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2156 addr:$dst)]>, TB, OpSize;
2158 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2159 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2160 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2161 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2162 (i8 imm:$src3)), addr:$dst)]>,
2164 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2165 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2166 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2167 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2168 (i8 imm:$src3)), addr:$dst)]>,
2171 } // Defs = [EFLAGS]
2175 let Defs = [EFLAGS] in {
2176 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2177 // Register-Register Addition
2178 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2179 (ins GR8 :$src1, GR8 :$src2),
2180 "add{b}\t{$src2, $dst|$dst, $src2}",
2181 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
2182 (implicit EFLAGS)]>;
2184 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2185 // Register-Register Addition
2186 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2187 (ins GR16:$src1, GR16:$src2),
2188 "add{w}\t{$src2, $dst|$dst, $src2}",
2189 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2190 (implicit EFLAGS)]>, OpSize;
2191 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2192 (ins GR32:$src1, GR32:$src2),
2193 "add{l}\t{$src2, $dst|$dst, $src2}",
2194 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2195 (implicit EFLAGS)]>;
2196 } // end isConvertibleToThreeAddress
2197 } // end isCommutable
2199 // Register-Memory Addition
2200 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2201 (ins GR8 :$src1, i8mem :$src2),
2202 "add{b}\t{$src2, $dst|$dst, $src2}",
2203 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2204 (implicit EFLAGS)]>;
2205 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2206 (ins GR16:$src1, i16mem:$src2),
2207 "add{w}\t{$src2, $dst|$dst, $src2}",
2208 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2209 (implicit EFLAGS)]>, OpSize;
2210 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2211 (ins GR32:$src1, i32mem:$src2),
2212 "add{l}\t{$src2, $dst|$dst, $src2}",
2213 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2214 (implicit EFLAGS)]>;
2216 // Register-Integer Addition
2217 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2218 "add{b}\t{$src2, $dst|$dst, $src2}",
2219 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2220 (implicit EFLAGS)]>;
2222 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2223 // Register-Integer Addition
2224 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2225 (ins GR16:$src1, i16imm:$src2),
2226 "add{w}\t{$src2, $dst|$dst, $src2}",
2227 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2228 (implicit EFLAGS)]>, OpSize;
2229 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2230 (ins GR32:$src1, i32imm:$src2),
2231 "add{l}\t{$src2, $dst|$dst, $src2}",
2232 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2233 (implicit EFLAGS)]>;
2234 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2235 (ins GR16:$src1, i16i8imm:$src2),
2236 "add{w}\t{$src2, $dst|$dst, $src2}",
2237 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2238 (implicit EFLAGS)]>, OpSize;
2239 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2240 (ins GR32:$src1, i32i8imm:$src2),
2241 "add{l}\t{$src2, $dst|$dst, $src2}",
2242 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2243 (implicit EFLAGS)]>;
2246 let isTwoAddress = 0 in {
2247 // Memory-Register Addition
2248 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2249 "add{b}\t{$src2, $dst|$dst, $src2}",
2250 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2251 (implicit EFLAGS)]>;
2252 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2253 "add{w}\t{$src2, $dst|$dst, $src2}",
2254 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2255 (implicit EFLAGS)]>, OpSize;
2256 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2257 "add{l}\t{$src2, $dst|$dst, $src2}",
2258 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2259 (implicit EFLAGS)]>;
2260 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2261 "add{b}\t{$src2, $dst|$dst, $src2}",
2262 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2263 (implicit EFLAGS)]>;
2264 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2265 "add{w}\t{$src2, $dst|$dst, $src2}",
2266 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2267 (implicit EFLAGS)]>, OpSize;
2268 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2269 "add{l}\t{$src2, $dst|$dst, $src2}",
2270 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2271 (implicit EFLAGS)]>;
2272 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2273 "add{w}\t{$src2, $dst|$dst, $src2}",
2274 [(store (add (load addr:$dst), i16immSExt8:$src2),
2276 (implicit EFLAGS)]>, OpSize;
2277 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2278 "add{l}\t{$src2, $dst|$dst, $src2}",
2279 [(store (add (load addr:$dst), i32immSExt8:$src2),
2281 (implicit EFLAGS)]>;
2284 let Uses = [EFLAGS] in {
2285 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2286 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2287 "adc{b}\t{$src2, $dst|$dst, $src2}",
2288 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2289 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2290 (ins GR16:$src1, GR16:$src2),
2291 "adc{w}\t{$src2, $dst|$dst, $src2}",
2292 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2293 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2294 (ins GR32:$src1, GR32:$src2),
2295 "adc{l}\t{$src2, $dst|$dst, $src2}",
2296 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2298 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2299 (ins GR8:$src1, i8mem:$src2),
2300 "adc{b}\t{$src2, $dst|$dst, $src2}",
2301 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2302 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2303 (ins GR16:$src1, i16mem:$src2),
2304 "adc{w}\t{$src2, $dst|$dst, $src2}",
2305 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2307 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2308 (ins GR32:$src1, i32mem:$src2),
2309 "adc{l}\t{$src2, $dst|$dst, $src2}",
2310 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2311 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2312 "adc{b}\t{$src2, $dst|$dst, $src2}",
2313 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2314 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2315 (ins GR16:$src1, i16imm:$src2),
2316 "adc{w}\t{$src2, $dst|$dst, $src2}",
2317 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2318 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2319 (ins GR16:$src1, i16i8imm:$src2),
2320 "adc{w}\t{$src2, $dst|$dst, $src2}",
2321 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2323 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2324 (ins GR32:$src1, i32imm:$src2),
2325 "adc{l}\t{$src2, $dst|$dst, $src2}",
2326 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2327 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2328 (ins GR32:$src1, i32i8imm:$src2),
2329 "adc{l}\t{$src2, $dst|$dst, $src2}",
2330 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2332 let isTwoAddress = 0 in {
2333 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2334 "adc{b}\t{$src2, $dst|$dst, $src2}",
2335 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2336 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2337 "adc{w}\t{$src2, $dst|$dst, $src2}",
2338 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2340 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2341 "adc{l}\t{$src2, $dst|$dst, $src2}",
2342 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2343 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2344 "adc{b}\t{$src2, $dst|$dst, $src2}",
2345 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2346 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2347 "adc{w}\t{$src2, $dst|$dst, $src2}",
2348 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2350 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2351 "adc{w}\t{$src2, $dst|$dst, $src2}",
2352 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2354 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2355 "adc{l}\t{$src2, $dst|$dst, $src2}",
2356 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2357 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2358 "adc{l}\t{$src2, $dst|$dst, $src2}",
2359 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2361 } // Uses = [EFLAGS]
2363 // Register-Register Subtraction
2364 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2365 "sub{b}\t{$src2, $dst|$dst, $src2}",
2366 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2367 (implicit EFLAGS)]>;
2368 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2369 "sub{w}\t{$src2, $dst|$dst, $src2}",
2370 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2371 (implicit EFLAGS)]>, OpSize;
2372 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2373 "sub{l}\t{$src2, $dst|$dst, $src2}",
2374 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2375 (implicit EFLAGS)]>;
2377 // Register-Memory Subtraction
2378 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2379 (ins GR8 :$src1, i8mem :$src2),
2380 "sub{b}\t{$src2, $dst|$dst, $src2}",
2381 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2382 (implicit EFLAGS)]>;
2383 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2384 (ins GR16:$src1, i16mem:$src2),
2385 "sub{w}\t{$src2, $dst|$dst, $src2}",
2386 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2387 (implicit EFLAGS)]>, OpSize;
2388 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2389 (ins GR32:$src1, i32mem:$src2),
2390 "sub{l}\t{$src2, $dst|$dst, $src2}",
2391 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2392 (implicit EFLAGS)]>;
2394 // Register-Integer Subtraction
2395 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2396 (ins GR8:$src1, i8imm:$src2),
2397 "sub{b}\t{$src2, $dst|$dst, $src2}",
2398 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2399 (implicit EFLAGS)]>;
2400 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2401 (ins GR16:$src1, i16imm:$src2),
2402 "sub{w}\t{$src2, $dst|$dst, $src2}",
2403 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2404 (implicit EFLAGS)]>, OpSize;
2405 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2406 (ins GR32:$src1, i32imm:$src2),
2407 "sub{l}\t{$src2, $dst|$dst, $src2}",
2408 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2409 (implicit EFLAGS)]>;
2410 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2411 (ins GR16:$src1, i16i8imm:$src2),
2412 "sub{w}\t{$src2, $dst|$dst, $src2}",
2413 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2414 (implicit EFLAGS)]>, OpSize;
2415 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2416 (ins GR32:$src1, i32i8imm:$src2),
2417 "sub{l}\t{$src2, $dst|$dst, $src2}",
2418 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2419 (implicit EFLAGS)]>;
2421 let isTwoAddress = 0 in {
2422 // Memory-Register Subtraction
2423 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2424 "sub{b}\t{$src2, $dst|$dst, $src2}",
2425 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2426 (implicit EFLAGS)]>;
2427 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2428 "sub{w}\t{$src2, $dst|$dst, $src2}",
2429 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2430 (implicit EFLAGS)]>, OpSize;
2431 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2432 "sub{l}\t{$src2, $dst|$dst, $src2}",
2433 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2434 (implicit EFLAGS)]>;
2436 // Memory-Integer Subtraction
2437 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2438 "sub{b}\t{$src2, $dst|$dst, $src2}",
2439 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2440 (implicit EFLAGS)]>;
2441 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2442 "sub{w}\t{$src2, $dst|$dst, $src2}",
2443 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2444 (implicit EFLAGS)]>, OpSize;
2445 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2446 "sub{l}\t{$src2, $dst|$dst, $src2}",
2447 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2448 (implicit EFLAGS)]>;
2449 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2450 "sub{w}\t{$src2, $dst|$dst, $src2}",
2451 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2453 (implicit EFLAGS)]>, OpSize;
2454 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2455 "sub{l}\t{$src2, $dst|$dst, $src2}",
2456 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2458 (implicit EFLAGS)]>;
2461 let Uses = [EFLAGS] in {
2462 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2463 (ins GR8:$src1, GR8:$src2),
2464 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2465 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
2466 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2467 (ins GR16:$src1, GR16:$src2),
2468 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2469 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
2470 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
2471 (ins GR32:$src1, GR32:$src2),
2472 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2473 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2475 let isTwoAddress = 0 in {
2476 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2477 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2478 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
2479 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2480 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2481 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
2483 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2484 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2485 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2486 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2487 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2488 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2489 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
2490 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2491 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2493 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2494 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2495 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2497 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2498 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2499 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2500 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2501 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2502 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2504 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
2505 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2506 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
2507 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
2508 (ins GR16:$src1, i16mem:$src2),
2509 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2510 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
2512 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
2513 (ins GR32:$src1, i32mem:$src2),
2514 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2515 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2516 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2517 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2518 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
2519 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
2520 (ins GR16:$src1, i16imm:$src2),
2521 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2522 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
2523 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
2524 (ins GR16:$src1, i16i8imm:$src2),
2525 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2526 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
2528 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
2529 (ins GR32:$src1, i32imm:$src2),
2530 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2531 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2532 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
2533 (ins GR32:$src1, i32i8imm:$src2),
2534 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2535 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2536 } // Uses = [EFLAGS]
2537 } // Defs = [EFLAGS]
2539 let Defs = [EFLAGS] in {
2540 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2541 // Register-Register Signed Integer Multiply
2542 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2543 "imul{w}\t{$src2, $dst|$dst, $src2}",
2544 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
2545 (implicit EFLAGS)]>, TB, OpSize;
2546 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2547 "imul{l}\t{$src2, $dst|$dst, $src2}",
2548 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
2549 (implicit EFLAGS)]>, TB;
2552 // Register-Memory Signed Integer Multiply
2553 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
2554 (ins GR16:$src1, i16mem:$src2),
2555 "imul{w}\t{$src2, $dst|$dst, $src2}",
2556 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
2557 (implicit EFLAGS)]>, TB, OpSize;
2558 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2559 "imul{l}\t{$src2, $dst|$dst, $src2}",
2560 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
2561 (implicit EFLAGS)]>, TB;
2562 } // Defs = [EFLAGS]
2563 } // end Two Address instructions
2565 // Suprisingly enough, these are not two address instructions!
2566 let Defs = [EFLAGS] in {
2567 // Register-Integer Signed Integer Multiply
2568 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2569 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2570 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2571 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
2572 (implicit EFLAGS)]>, OpSize;
2573 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2574 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2575 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2576 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
2577 (implicit EFLAGS)]>;
2578 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2579 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2580 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2581 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
2582 (implicit EFLAGS)]>, OpSize;
2583 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2584 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2585 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2586 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
2587 (implicit EFLAGS)]>;
2589 // Memory-Integer Signed Integer Multiply
2590 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2591 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2592 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2593 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
2594 (implicit EFLAGS)]>, OpSize;
2595 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2596 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2597 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2598 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
2599 (implicit EFLAGS)]>;
2600 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2601 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2602 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2603 [(set GR16:$dst, (mul (load addr:$src1),
2604 i16immSExt8:$src2)),
2605 (implicit EFLAGS)]>, OpSize;
2606 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2607 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2608 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2609 [(set GR32:$dst, (mul (load addr:$src1),
2610 i32immSExt8:$src2)),
2611 (implicit EFLAGS)]>;
2612 } // Defs = [EFLAGS]
2614 //===----------------------------------------------------------------------===//
2615 // Test instructions are just like AND, except they don't generate a result.
2617 let Defs = [EFLAGS] in {
2618 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2619 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2620 "test{b}\t{$src2, $src1|$src1, $src2}",
2621 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
2622 (implicit EFLAGS)]>;
2623 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2624 "test{w}\t{$src2, $src1|$src1, $src2}",
2625 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
2626 (implicit EFLAGS)]>,
2628 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2629 "test{l}\t{$src2, $src1|$src1, $src2}",
2630 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
2631 (implicit EFLAGS)]>;
2634 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2635 "test{b}\t{$src2, $src1|$src1, $src2}",
2636 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2637 (implicit EFLAGS)]>;
2638 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2639 "test{w}\t{$src2, $src1|$src1, $src2}",
2640 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2641 (implicit EFLAGS)]>, OpSize;
2642 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2643 "test{l}\t{$src2, $src1|$src1, $src2}",
2644 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2645 (implicit EFLAGS)]>;
2647 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2648 (outs), (ins GR8:$src1, i8imm:$src2),
2649 "test{b}\t{$src2, $src1|$src1, $src2}",
2650 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
2651 (implicit EFLAGS)]>;
2652 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2653 (outs), (ins GR16:$src1, i16imm:$src2),
2654 "test{w}\t{$src2, $src1|$src1, $src2}",
2655 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
2656 (implicit EFLAGS)]>, OpSize;
2657 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2658 (outs), (ins GR32:$src1, i32imm:$src2),
2659 "test{l}\t{$src2, $src1|$src1, $src2}",
2660 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
2661 (implicit EFLAGS)]>;
2663 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2664 (outs), (ins i8mem:$src1, i8imm:$src2),
2665 "test{b}\t{$src2, $src1|$src1, $src2}",
2666 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2667 (implicit EFLAGS)]>;
2668 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2669 (outs), (ins i16mem:$src1, i16imm:$src2),
2670 "test{w}\t{$src2, $src1|$src1, $src2}",
2671 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2672 (implicit EFLAGS)]>, OpSize;
2673 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2674 (outs), (ins i32mem:$src1, i32imm:$src2),
2675 "test{l}\t{$src2, $src1|$src1, $src2}",
2676 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2677 (implicit EFLAGS)]>;
2678 } // Defs = [EFLAGS]
2681 // Condition code ops, incl. set if equal/not equal/...
2682 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2683 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2684 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2685 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2687 let Uses = [EFLAGS] in {
2688 def SETEr : I<0x94, MRM0r,
2689 (outs GR8 :$dst), (ins),
2691 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2693 def SETEm : I<0x94, MRM0m,
2694 (outs), (ins i8mem:$dst),
2696 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2699 def SETNEr : I<0x95, MRM0r,
2700 (outs GR8 :$dst), (ins),
2702 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2704 def SETNEm : I<0x95, MRM0m,
2705 (outs), (ins i8mem:$dst),
2707 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2710 def SETLr : I<0x9C, MRM0r,
2711 (outs GR8 :$dst), (ins),
2713 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2714 TB; // GR8 = < signed
2715 def SETLm : I<0x9C, MRM0m,
2716 (outs), (ins i8mem:$dst),
2718 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2719 TB; // [mem8] = < signed
2721 def SETGEr : I<0x9D, MRM0r,
2722 (outs GR8 :$dst), (ins),
2724 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2725 TB; // GR8 = >= signed
2726 def SETGEm : I<0x9D, MRM0m,
2727 (outs), (ins i8mem:$dst),
2729 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2730 TB; // [mem8] = >= signed
2732 def SETLEr : I<0x9E, MRM0r,
2733 (outs GR8 :$dst), (ins),
2735 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2736 TB; // GR8 = <= signed
2737 def SETLEm : I<0x9E, MRM0m,
2738 (outs), (ins i8mem:$dst),
2740 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2741 TB; // [mem8] = <= signed
2743 def SETGr : I<0x9F, MRM0r,
2744 (outs GR8 :$dst), (ins),
2746 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2747 TB; // GR8 = > signed
2748 def SETGm : I<0x9F, MRM0m,
2749 (outs), (ins i8mem:$dst),
2751 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2752 TB; // [mem8] = > signed
2754 def SETBr : I<0x92, MRM0r,
2755 (outs GR8 :$dst), (ins),
2757 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2758 TB; // GR8 = < unsign
2759 def SETBm : I<0x92, MRM0m,
2760 (outs), (ins i8mem:$dst),
2762 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2763 TB; // [mem8] = < unsign
2765 def SETAEr : I<0x93, MRM0r,
2766 (outs GR8 :$dst), (ins),
2768 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2769 TB; // GR8 = >= unsign
2770 def SETAEm : I<0x93, MRM0m,
2771 (outs), (ins i8mem:$dst),
2773 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2774 TB; // [mem8] = >= unsign
2776 def SETBEr : I<0x96, MRM0r,
2777 (outs GR8 :$dst), (ins),
2779 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2780 TB; // GR8 = <= unsign
2781 def SETBEm : I<0x96, MRM0m,
2782 (outs), (ins i8mem:$dst),
2784 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2785 TB; // [mem8] = <= unsign
2787 def SETAr : I<0x97, MRM0r,
2788 (outs GR8 :$dst), (ins),
2790 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2791 TB; // GR8 = > signed
2792 def SETAm : I<0x97, MRM0m,
2793 (outs), (ins i8mem:$dst),
2795 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2796 TB; // [mem8] = > signed
2798 def SETSr : I<0x98, MRM0r,
2799 (outs GR8 :$dst), (ins),
2801 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2802 TB; // GR8 = <sign bit>
2803 def SETSm : I<0x98, MRM0m,
2804 (outs), (ins i8mem:$dst),
2806 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2807 TB; // [mem8] = <sign bit>
2808 def SETNSr : I<0x99, MRM0r,
2809 (outs GR8 :$dst), (ins),
2811 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2812 TB; // GR8 = !<sign bit>
2813 def SETNSm : I<0x99, MRM0m,
2814 (outs), (ins i8mem:$dst),
2816 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2817 TB; // [mem8] = !<sign bit>
2819 def SETPr : I<0x9A, MRM0r,
2820 (outs GR8 :$dst), (ins),
2822 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2824 def SETPm : I<0x9A, MRM0m,
2825 (outs), (ins i8mem:$dst),
2827 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2828 TB; // [mem8] = parity
2829 def SETNPr : I<0x9B, MRM0r,
2830 (outs GR8 :$dst), (ins),
2832 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2833 TB; // GR8 = not parity
2834 def SETNPm : I<0x9B, MRM0m,
2835 (outs), (ins i8mem:$dst),
2837 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2838 TB; // [mem8] = not parity
2840 def SETOr : I<0x90, MRM0r,
2841 (outs GR8 :$dst), (ins),
2843 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
2844 TB; // GR8 = overflow
2845 def SETOm : I<0x90, MRM0m,
2846 (outs), (ins i8mem:$dst),
2848 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
2849 TB; // [mem8] = overflow
2850 def SETNOr : I<0x91, MRM0r,
2851 (outs GR8 :$dst), (ins),
2853 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
2854 TB; // GR8 = not overflow
2855 def SETNOm : I<0x91, MRM0m,
2856 (outs), (ins i8mem:$dst),
2858 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
2859 TB; // [mem8] = not overflow
2860 } // Uses = [EFLAGS]
2863 // Integer comparisons
2864 let Defs = [EFLAGS] in {
2865 def CMP8rr : I<0x38, MRMDestReg,
2866 (outs), (ins GR8 :$src1, GR8 :$src2),
2867 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2868 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2869 def CMP16rr : I<0x39, MRMDestReg,
2870 (outs), (ins GR16:$src1, GR16:$src2),
2871 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2872 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2873 def CMP32rr : I<0x39, MRMDestReg,
2874 (outs), (ins GR32:$src1, GR32:$src2),
2875 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2876 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2877 def CMP8mr : I<0x38, MRMDestMem,
2878 (outs), (ins i8mem :$src1, GR8 :$src2),
2879 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2880 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2881 (implicit EFLAGS)]>;
2882 def CMP16mr : I<0x39, MRMDestMem,
2883 (outs), (ins i16mem:$src1, GR16:$src2),
2884 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2885 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2886 (implicit EFLAGS)]>, OpSize;
2887 def CMP32mr : I<0x39, MRMDestMem,
2888 (outs), (ins i32mem:$src1, GR32:$src2),
2889 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2890 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2891 (implicit EFLAGS)]>;
2892 def CMP8rm : I<0x3A, MRMSrcMem,
2893 (outs), (ins GR8 :$src1, i8mem :$src2),
2894 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2895 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2896 (implicit EFLAGS)]>;
2897 def CMP16rm : I<0x3B, MRMSrcMem,
2898 (outs), (ins GR16:$src1, i16mem:$src2),
2899 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2900 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2901 (implicit EFLAGS)]>, OpSize;
2902 def CMP32rm : I<0x3B, MRMSrcMem,
2903 (outs), (ins GR32:$src1, i32mem:$src2),
2904 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2905 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2906 (implicit EFLAGS)]>;
2907 def CMP8ri : Ii8<0x80, MRM7r,
2908 (outs), (ins GR8:$src1, i8imm:$src2),
2909 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2910 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
2911 def CMP16ri : Ii16<0x81, MRM7r,
2912 (outs), (ins GR16:$src1, i16imm:$src2),
2913 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2914 [(X86cmp GR16:$src1, imm:$src2),
2915 (implicit EFLAGS)]>, OpSize;
2916 def CMP32ri : Ii32<0x81, MRM7r,
2917 (outs), (ins GR32:$src1, i32imm:$src2),
2918 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2919 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
2920 def CMP8mi : Ii8 <0x80, MRM7m,
2921 (outs), (ins i8mem :$src1, i8imm :$src2),
2922 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2923 [(X86cmp (loadi8 addr:$src1), imm:$src2),
2924 (implicit EFLAGS)]>;
2925 def CMP16mi : Ii16<0x81, MRM7m,
2926 (outs), (ins i16mem:$src1, i16imm:$src2),
2927 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2928 [(X86cmp (loadi16 addr:$src1), imm:$src2),
2929 (implicit EFLAGS)]>, OpSize;
2930 def CMP32mi : Ii32<0x81, MRM7m,
2931 (outs), (ins i32mem:$src1, i32imm:$src2),
2932 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2933 [(X86cmp (loadi32 addr:$src1), imm:$src2),
2934 (implicit EFLAGS)]>;
2935 def CMP16ri8 : Ii8<0x83, MRM7r,
2936 (outs), (ins GR16:$src1, i16i8imm:$src2),
2937 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2938 [(X86cmp GR16:$src1, i16immSExt8:$src2),
2939 (implicit EFLAGS)]>, OpSize;
2940 def CMP16mi8 : Ii8<0x83, MRM7m,
2941 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2942 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2943 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
2944 (implicit EFLAGS)]>, OpSize;
2945 def CMP32mi8 : Ii8<0x83, MRM7m,
2946 (outs), (ins i32mem:$src1, i32i8imm:$src2),
2947 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2948 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
2949 (implicit EFLAGS)]>;
2950 def CMP32ri8 : Ii8<0x83, MRM7r,
2951 (outs), (ins GR32:$src1, i32i8imm:$src2),
2952 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2953 [(X86cmp GR32:$src1, i32immSExt8:$src2),
2954 (implicit EFLAGS)]>;
2955 } // Defs = [EFLAGS]
2958 // TODO: BTC, BTR, and BTS
2959 let Defs = [EFLAGS] in {
2960 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2961 "bt{w}\t{$src2, $src1|$src1, $src2}",
2962 [(X86bt GR16:$src1, GR16:$src2),
2963 (implicit EFLAGS)]>, OpSize, TB;
2964 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2965 "bt{l}\t{$src2, $src1|$src1, $src2}",
2966 [(X86bt GR32:$src1, GR32:$src2),
2967 (implicit EFLAGS)]>, TB;
2969 // Unlike with the register+register form, the memory+register form of the
2970 // bt instruction does not ignore the high bits of the index. From ISel's
2971 // perspective, this is pretty bizarre. Disable these instructions for now.
2972 //def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
2973 // "bt{w}\t{$src2, $src1|$src1, $src2}",
2974 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
2975 // (implicit EFLAGS)]>, OpSize, TB, Requires<[FastBTMem]>;
2976 //def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
2977 // "bt{l}\t{$src2, $src1|$src1, $src2}",
2978 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
2979 // (implicit EFLAGS)]>, TB, Requires<[FastBTMem]>;
2981 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
2982 "bt{w}\t{$src2, $src1|$src1, $src2}",
2983 [(X86bt GR16:$src1, i16immSExt8:$src2),
2984 (implicit EFLAGS)]>, OpSize, TB;
2985 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
2986 "bt{l}\t{$src2, $src1|$src1, $src2}",
2987 [(X86bt GR32:$src1, i32immSExt8:$src2),
2988 (implicit EFLAGS)]>, TB;
2989 // Note that these instructions don't need FastBTMem because that
2990 // only applies when the other operand is in a register. When it's
2991 // an immediate, bt is still fast.
2992 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
2993 "bt{w}\t{$src2, $src1|$src1, $src2}",
2994 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
2995 (implicit EFLAGS)]>, OpSize, TB;
2996 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
2997 "bt{l}\t{$src2, $src1|$src1, $src2}",
2998 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
2999 (implicit EFLAGS)]>, TB;
3000 } // Defs = [EFLAGS]
3002 // Sign/Zero extenders
3003 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3004 // of the register here. This has a smaller encoding and avoids a
3005 // partial-register update.
3006 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3007 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3008 [(set GR16:$dst, (sext GR8:$src))]>, TB;
3009 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3010 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3011 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3012 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3013 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3014 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3015 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3016 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3017 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3018 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3019 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3020 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3021 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3022 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3023 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3025 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3026 // of the register here. This has a smaller encoding and avoids a
3027 // partial-register update.
3028 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3029 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3030 [(set GR16:$dst, (zext GR8:$src))]>, TB;
3031 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3032 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3033 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3034 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3035 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3036 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3037 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3038 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3039 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3040 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3041 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3042 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3043 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3044 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3045 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3047 // These are the same as the regular regular MOVZX32rr8 and MOVZX32rm8
3048 // except that they use GR32_NOREX for the output operand register class
3049 // instead of GR32. This allows them to operate on h registers on x86-64.
3050 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3051 (outs GR32_NOREX:$dst), (ins GR8:$src),
3052 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3055 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3056 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3057 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3060 let neverHasSideEffects = 1 in {
3061 let Defs = [AX], Uses = [AL] in
3062 def CBW : I<0x98, RawFrm, (outs), (ins),
3063 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3064 let Defs = [EAX], Uses = [AX] in
3065 def CWDE : I<0x98, RawFrm, (outs), (ins),
3066 "{cwtl|cwde}", []>; // EAX = signext(AX)
3068 let Defs = [AX,DX], Uses = [AX] in
3069 def CWD : I<0x99, RawFrm, (outs), (ins),
3070 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3071 let Defs = [EAX,EDX], Uses = [EAX] in
3072 def CDQ : I<0x99, RawFrm, (outs), (ins),
3073 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3076 //===----------------------------------------------------------------------===//
3077 // Alias Instructions
3078 //===----------------------------------------------------------------------===//
3080 // Alias instructions that map movr0 to xor.
3081 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3082 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1 in {
3083 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
3084 "xor{b}\t$dst, $dst",
3085 [(set GR8:$dst, 0)]>;
3086 // Use xorl instead of xorw since we don't care about the high 16 bits,
3087 // it's smaller, and it avoids a partial-register update.
3088 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3089 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
3090 [(set GR16:$dst, 0)]>;
3091 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
3092 "xor{l}\t$dst, $dst",
3093 [(set GR32:$dst, 0)]>;
3096 //===----------------------------------------------------------------------===//
3097 // Thread Local Storage Instructions
3100 // All calls clobber the non-callee saved registers. ESP is marked as
3101 // a use to prevent stack-pointer assignments that appear immediately
3102 // before calls from potentially appearing dead.
3103 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3104 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3105 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3106 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3107 Uses = [ESP, EBX] in
3108 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32imm:$sym),
3109 "leal\t${sym:mem}(,%ebx,1), %eax; "
3110 "call\t___tls_get_addr@PLT",
3111 [(X86tlsaddr tglobaltlsaddr:$sym)]>,
3112 Requires<[In32BitMode]>;
3114 let AddedComplexity = 5 in
3115 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3116 "movl\t%gs:$src, $dst",
3117 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3119 let AddedComplexity = 5 in
3120 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3121 "movl\t%fs:$src, $dst",
3122 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3124 //===----------------------------------------------------------------------===//
3125 // DWARF Pseudo Instructions
3128 def DWARF_LOC : I<0, Pseudo, (outs),
3129 (ins i32imm:$line, i32imm:$col, i32imm:$file),
3130 ".loc\t${file:debug} ${line:debug} ${col:debug}",
3131 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
3134 //===----------------------------------------------------------------------===//
3135 // EH Pseudo Instructions
3137 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3139 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3140 "ret\t#eh_return, addr: $addr",
3141 [(X86ehret GR32:$addr)]>;
3145 //===----------------------------------------------------------------------===//
3149 // Atomic swap. These are just normal xchg instructions. But since a memory
3150 // operand is referenced, the atomicity is ensured.
3151 let Constraints = "$val = $dst" in {
3152 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3153 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3154 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3155 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3156 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3157 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3159 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3160 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3161 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3164 // Atomic compare and swap.
3165 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3166 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3168 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3169 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3171 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3172 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
3175 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3178 let Defs = [AX, EFLAGS], Uses = [AX] in {
3179 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3181 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3182 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3184 let Defs = [AL, EFLAGS], Uses = [AL] in {
3185 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3187 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3188 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3191 // Atomic exchange and add
3192 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3193 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3195 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3196 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3198 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3200 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3201 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3203 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3205 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3206 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3210 // Atomic exchange, and, or, xor
3211 let Constraints = "$val = $dst", Defs = [EFLAGS],
3212 usesCustomDAGSchedInserter = 1 in {
3213 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3214 "#ATOMAND32 PSEUDO!",
3215 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3216 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3217 "#ATOMOR32 PSEUDO!",
3218 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3219 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3220 "#ATOMXOR32 PSEUDO!",
3221 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3222 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3223 "#ATOMNAND32 PSEUDO!",
3224 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
3225 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3226 "#ATOMMIN32 PSEUDO!",
3227 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
3228 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3229 "#ATOMMAX32 PSEUDO!",
3230 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
3231 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3232 "#ATOMUMIN32 PSEUDO!",
3233 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
3234 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3235 "#ATOMUMAX32 PSEUDO!",
3236 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
3238 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3239 "#ATOMAND16 PSEUDO!",
3240 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
3241 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3242 "#ATOMOR16 PSEUDO!",
3243 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
3244 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3245 "#ATOMXOR16 PSEUDO!",
3246 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
3247 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3248 "#ATOMNAND16 PSEUDO!",
3249 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
3250 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3251 "#ATOMMIN16 PSEUDO!",
3252 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
3253 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3254 "#ATOMMAX16 PSEUDO!",
3255 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
3256 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3257 "#ATOMUMIN16 PSEUDO!",
3258 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
3259 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3260 "#ATOMUMAX16 PSEUDO!",
3261 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
3263 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3264 "#ATOMAND8 PSEUDO!",
3265 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
3266 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3268 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
3269 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3270 "#ATOMXOR8 PSEUDO!",
3271 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
3272 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3273 "#ATOMNAND8 PSEUDO!",
3274 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
3277 let Constraints = "$val1 = $dst1, $val2 = $dst2",
3278 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
3279 Uses = [EAX, EBX, ECX, EDX],
3280 mayLoad = 1, mayStore = 1,
3281 usesCustomDAGSchedInserter = 1 in {
3282 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3283 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3284 "#ATOMAND6432 PSEUDO!", []>;
3285 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3286 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3287 "#ATOMOR6432 PSEUDO!", []>;
3288 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3289 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3290 "#ATOMXOR6432 PSEUDO!", []>;
3291 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3292 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3293 "#ATOMNAND6432 PSEUDO!", []>;
3294 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3295 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3296 "#ATOMADD6432 PSEUDO!", []>;
3297 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3298 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3299 "#ATOMSUB6432 PSEUDO!", []>;
3300 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3301 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3302 "#ATOMSWAP6432 PSEUDO!", []>;
3305 //===----------------------------------------------------------------------===//
3306 // Non-Instruction Patterns
3307 //===----------------------------------------------------------------------===//
3309 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
3310 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
3311 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
3312 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
3313 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
3314 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
3316 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
3317 (ADD32ri GR32:$src1, tconstpool:$src2)>;
3318 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
3319 (ADD32ri GR32:$src1, tjumptable:$src2)>;
3320 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
3321 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
3322 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
3323 (ADD32ri GR32:$src1, texternalsym:$src2)>;
3325 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
3326 (MOV32mi addr:$dst, tglobaladdr:$src)>;
3327 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
3328 (MOV32mi addr:$dst, texternalsym:$src)>;
3332 def : Pat<(X86tailcall GR32:$dst),
3335 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
3337 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
3340 def : Pat<(X86tcret GR32:$dst, imm:$off),
3341 (TCRETURNri GR32:$dst, imm:$off)>;
3343 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
3344 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3346 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
3347 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3349 def : Pat<(X86call (i32 tglobaladdr:$dst)),
3350 (CALLpcrel32 tglobaladdr:$dst)>;
3351 def : Pat<(X86call (i32 texternalsym:$dst)),
3352 (CALLpcrel32 texternalsym:$dst)>;
3353 def : Pat<(X86call (i32 imm:$dst)),
3354 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
3356 // X86 specific add which produces a flag.
3357 def : Pat<(addc GR32:$src1, GR32:$src2),
3358 (ADD32rr GR32:$src1, GR32:$src2)>;
3359 def : Pat<(addc GR32:$src1, (load addr:$src2)),
3360 (ADD32rm GR32:$src1, addr:$src2)>;
3361 def : Pat<(addc GR32:$src1, imm:$src2),
3362 (ADD32ri GR32:$src1, imm:$src2)>;
3363 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
3364 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3366 def : Pat<(subc GR32:$src1, GR32:$src2),
3367 (SUB32rr GR32:$src1, GR32:$src2)>;
3368 def : Pat<(subc GR32:$src1, (load addr:$src2)),
3369 (SUB32rm GR32:$src1, addr:$src2)>;
3370 def : Pat<(subc GR32:$src1, imm:$src2),
3371 (SUB32ri GR32:$src1, imm:$src2)>;
3372 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
3373 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3377 // TEST R,R is smaller than CMP R,0
3378 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
3379 (TEST8rr GR8:$src1, GR8:$src1)>;
3380 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
3381 (TEST16rr GR16:$src1, GR16:$src1)>;
3382 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
3383 (TEST32rr GR32:$src1, GR32:$src1)>;
3385 // Conditional moves with folded loads with operands swapped and conditions
3387 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
3388 (CMOVAE16rm GR16:$src2, addr:$src1)>;
3389 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
3390 (CMOVAE32rm GR32:$src2, addr:$src1)>;
3391 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
3392 (CMOVB16rm GR16:$src2, addr:$src1)>;
3393 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
3394 (CMOVB32rm GR32:$src2, addr:$src1)>;
3395 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
3396 (CMOVNE16rm GR16:$src2, addr:$src1)>;
3397 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
3398 (CMOVNE32rm GR32:$src2, addr:$src1)>;
3399 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
3400 (CMOVE16rm GR16:$src2, addr:$src1)>;
3401 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
3402 (CMOVE32rm GR32:$src2, addr:$src1)>;
3403 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
3404 (CMOVA16rm GR16:$src2, addr:$src1)>;
3405 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
3406 (CMOVA32rm GR32:$src2, addr:$src1)>;
3407 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
3408 (CMOVBE16rm GR16:$src2, addr:$src1)>;
3409 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
3410 (CMOVBE32rm GR32:$src2, addr:$src1)>;
3411 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
3412 (CMOVGE16rm GR16:$src2, addr:$src1)>;
3413 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
3414 (CMOVGE32rm GR32:$src2, addr:$src1)>;
3415 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
3416 (CMOVL16rm GR16:$src2, addr:$src1)>;
3417 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
3418 (CMOVL32rm GR32:$src2, addr:$src1)>;
3419 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
3420 (CMOVG16rm GR16:$src2, addr:$src1)>;
3421 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
3422 (CMOVG32rm GR32:$src2, addr:$src1)>;
3423 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
3424 (CMOVLE16rm GR16:$src2, addr:$src1)>;
3425 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
3426 (CMOVLE32rm GR32:$src2, addr:$src1)>;
3427 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
3428 (CMOVNP16rm GR16:$src2, addr:$src1)>;
3429 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
3430 (CMOVNP32rm GR32:$src2, addr:$src1)>;
3431 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
3432 (CMOVP16rm GR16:$src2, addr:$src1)>;
3433 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
3434 (CMOVP32rm GR32:$src2, addr:$src1)>;
3435 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
3436 (CMOVNS16rm GR16:$src2, addr:$src1)>;
3437 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
3438 (CMOVNS32rm GR32:$src2, addr:$src1)>;
3439 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
3440 (CMOVS16rm GR16:$src2, addr:$src1)>;
3441 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
3442 (CMOVS32rm GR32:$src2, addr:$src1)>;
3443 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
3444 (CMOVNO16rm GR16:$src2, addr:$src1)>;
3445 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
3446 (CMOVNO32rm GR32:$src2, addr:$src1)>;
3447 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
3448 (CMOVO16rm GR16:$src2, addr:$src1)>;
3449 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
3450 (CMOVO32rm GR32:$src2, addr:$src1)>;
3452 // zextload bool -> zextload byte
3453 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3454 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3455 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3457 // extload bool -> extload byte
3458 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3459 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>,
3460 Requires<[In32BitMode]>;
3461 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3462 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>,
3463 Requires<[In32BitMode]>;
3464 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
3465 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
3468 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>,
3469 Requires<[In32BitMode]>;
3470 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>,
3471 Requires<[In32BitMode]>;
3472 def : Pat<(i32 (anyext GR16:$src)),
3473 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
3475 // (and (i32 load), 255) -> (zextload i8)
3476 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
3477 (MOVZX32rm8 addr:$src)>;
3478 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
3479 (MOVZX32rm16 addr:$src)>;
3481 //===----------------------------------------------------------------------===//
3483 //===----------------------------------------------------------------------===//
3485 // Odd encoding trick: -128 fits into an 8-bit immediate field while
3486 // +128 doesn't, so in this special case use a sub instead of an add.
3487 def : Pat<(add GR16:$src1, 128),
3488 (SUB16ri8 GR16:$src1, -128)>;
3489 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
3490 (SUB16mi8 addr:$dst, -128)>;
3491 def : Pat<(add GR32:$src1, 128),
3492 (SUB32ri8 GR32:$src1, -128)>;
3493 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
3494 (SUB32mi8 addr:$dst, -128)>;
3496 // r & (2^16-1) ==> movz
3497 def : Pat<(and GR32:$src1, 0xffff),
3498 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
3499 // r & (2^8-1) ==> movz
3500 def : Pat<(and GR32:$src1, 0xff),
3501 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src1, GR32_ABCD),
3503 Requires<[In32BitMode]>;
3504 // r & (2^8-1) ==> movz
3505 def : Pat<(and GR16:$src1, 0xff),
3506 (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD),
3508 Requires<[In32BitMode]>;
3510 // sext_inreg patterns
3511 def : Pat<(sext_inreg GR32:$src, i16),
3512 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
3513 def : Pat<(sext_inreg GR32:$src, i8),
3514 (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3516 Requires<[In32BitMode]>;
3517 def : Pat<(sext_inreg GR16:$src, i8),
3518 (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3520 Requires<[In32BitMode]>;
3523 def : Pat<(i16 (trunc GR32:$src)),
3524 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
3525 def : Pat<(i8 (trunc GR32:$src)),
3526 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3528 Requires<[In32BitMode]>;
3529 def : Pat<(i8 (trunc GR16:$src)),
3530 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3532 Requires<[In32BitMode]>;
3534 // h-register tricks
3535 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
3536 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3537 x86_subreg_8bit_hi)>,
3538 Requires<[In32BitMode]>;
3539 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
3540 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3541 x86_subreg_8bit_hi)>,
3542 Requires<[In32BitMode]>;
3543 def : Pat<(srl_su GR16:$src, (i8 8)),
3546 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3547 x86_subreg_8bit_hi)),
3549 Requires<[In32BitMode]>;
3550 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
3551 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3552 x86_subreg_8bit_hi))>,
3553 Requires<[In32BitMode]>;
3554 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
3555 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3556 x86_subreg_8bit_hi))>,
3557 Requires<[In32BitMode]>;
3559 // (shl x, 1) ==> (add x, x)
3560 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
3561 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
3562 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
3564 // (shl x (and y, 31)) ==> (shl x, y)
3565 def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
3566 (SHL8rCL GR8:$src1)>;
3567 def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
3568 (SHL16rCL GR16:$src1)>;
3569 def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
3570 (SHL32rCL GR32:$src1)>;
3571 def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3572 (SHL8mCL addr:$dst)>;
3573 def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3574 (SHL16mCL addr:$dst)>;
3575 def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3576 (SHL32mCL addr:$dst)>;
3578 def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
3579 (SHR8rCL GR8:$src1)>;
3580 def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
3581 (SHR16rCL GR16:$src1)>;
3582 def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
3583 (SHR32rCL GR32:$src1)>;
3584 def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3585 (SHR8mCL addr:$dst)>;
3586 def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3587 (SHR16mCL addr:$dst)>;
3588 def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3589 (SHR32mCL addr:$dst)>;
3591 def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
3592 (SAR8rCL GR8:$src1)>;
3593 def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
3594 (SAR16rCL GR16:$src1)>;
3595 def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
3596 (SAR32rCL GR32:$src1)>;
3597 def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3598 (SAR8mCL addr:$dst)>;
3599 def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3600 (SAR16mCL addr:$dst)>;
3601 def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3602 (SAR32mCL addr:$dst)>;
3604 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
3605 def : Pat<(or (srl GR32:$src1, CL:$amt),
3606 (shl GR32:$src2, (sub 32, CL:$amt))),
3607 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3609 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
3610 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3611 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3613 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
3614 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3615 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3617 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3618 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3620 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3622 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3623 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3625 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
3626 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3627 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3629 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
3630 def : Pat<(or (shl GR32:$src1, CL:$amt),
3631 (srl GR32:$src2, (sub 32, CL:$amt))),
3632 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3634 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
3635 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3636 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3638 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
3639 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3640 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3642 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3643 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3645 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3647 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3648 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3650 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
3651 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3652 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3654 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
3655 def : Pat<(or (srl GR16:$src1, CL:$amt),
3656 (shl GR16:$src2, (sub 16, CL:$amt))),
3657 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3659 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
3660 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3661 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3663 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
3664 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3665 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3667 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3668 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3670 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3672 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3673 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3675 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
3676 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3677 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3679 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
3680 def : Pat<(or (shl GR16:$src1, CL:$amt),
3681 (srl GR16:$src2, (sub 16, CL:$amt))),
3682 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3684 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
3685 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3686 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3688 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
3689 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3690 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3692 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3693 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3695 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3697 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3698 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3700 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
3701 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3702 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3704 //===----------------------------------------------------------------------===//
3705 // EFLAGS-defining Patterns
3706 //===----------------------------------------------------------------------===//
3708 // Register-Register Addition with EFLAGS result
3709 def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
3711 (ADD8rr GR8:$src1, GR8:$src2)>;
3712 def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
3714 (ADD16rr GR16:$src1, GR16:$src2)>;
3715 def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
3717 (ADD32rr GR32:$src1, GR32:$src2)>;
3719 // Register-Memory Addition with EFLAGS result
3720 def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
3722 (ADD8rm GR8:$src1, addr:$src2)>;
3723 def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
3725 (ADD16rm GR16:$src1, addr:$src2)>;
3726 def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
3728 (ADD32rm GR32:$src1, addr:$src2)>;
3730 // Register-Integer Addition with EFLAGS result
3731 def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
3733 (ADD8ri GR8:$src1, imm:$src2)>;
3734 def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
3736 (ADD16ri GR16:$src1, imm:$src2)>;
3737 def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
3739 (ADD32ri GR32:$src1, imm:$src2)>;
3740 def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
3742 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
3743 def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
3745 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3747 // Memory-Register Addition with EFLAGS result
3748 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
3751 (ADD8mr addr:$dst, GR8:$src2)>;
3752 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
3755 (ADD16mr addr:$dst, GR16:$src2)>;
3756 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
3759 (ADD32mr addr:$dst, GR32:$src2)>;
3761 // Memory-Integer Addition with EFLAGS result
3762 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
3765 (ADD8mi addr:$dst, imm:$src2)>;
3766 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
3769 (ADD16mi addr:$dst, imm:$src2)>;
3770 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
3773 (ADD32mi addr:$dst, imm:$src2)>;
3774 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
3777 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
3778 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
3781 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
3783 // Register-Register Subtraction with EFLAGS result
3784 def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
3786 (SUB8rr GR8:$src1, GR8:$src2)>;
3787 def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
3789 (SUB16rr GR16:$src1, GR16:$src2)>;
3790 def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
3792 (SUB32rr GR32:$src1, GR32:$src2)>;
3794 // Register-Memory Subtraction with EFLAGS result
3795 def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
3797 (SUB8rm GR8:$src1, addr:$src2)>;
3798 def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
3800 (SUB16rm GR16:$src1, addr:$src2)>;
3801 def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
3803 (SUB32rm GR32:$src1, addr:$src2)>;
3805 // Register-Integer Subtraction with EFLAGS result
3806 def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
3808 (SUB8ri GR8:$src1, imm:$src2)>;
3809 def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
3811 (SUB16ri GR16:$src1, imm:$src2)>;
3812 def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
3814 (SUB32ri GR32:$src1, imm:$src2)>;
3815 def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
3817 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
3818 def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
3820 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3822 // Memory-Register Subtraction with EFLAGS result
3823 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
3826 (SUB8mr addr:$dst, GR8:$src2)>;
3827 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
3830 (SUB16mr addr:$dst, GR16:$src2)>;
3831 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
3834 (SUB32mr addr:$dst, GR32:$src2)>;
3836 // Memory-Integer Subtraction with EFLAGS result
3837 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
3840 (SUB8mi addr:$dst, imm:$src2)>;
3841 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
3844 (SUB16mi addr:$dst, imm:$src2)>;
3845 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
3848 (SUB32mi addr:$dst, imm:$src2)>;
3849 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
3852 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
3853 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
3856 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
3859 // Register-Register Signed Integer Multiply with EFLAGS result
3860 def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
3862 (IMUL16rr GR16:$src1, GR16:$src2)>;
3863 def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
3865 (IMUL32rr GR32:$src1, GR32:$src2)>;
3867 // Register-Memory Signed Integer Multiply with EFLAGS result
3868 def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
3870 (IMUL16rm GR16:$src1, addr:$src2)>;
3871 def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
3873 (IMUL32rm GR32:$src1, addr:$src2)>;
3875 // Register-Integer Signed Integer Multiply with EFLAGS result
3876 def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
3878 (IMUL16rri GR16:$src1, imm:$src2)>;
3879 def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
3881 (IMUL32rri GR32:$src1, imm:$src2)>;
3882 def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
3884 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
3885 def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
3887 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
3889 // Memory-Integer Signed Integer Multiply with EFLAGS result
3890 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
3892 (IMUL16rmi addr:$src1, imm:$src2)>;
3893 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
3895 (IMUL32rmi addr:$src1, imm:$src2)>;
3896 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
3898 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
3899 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
3901 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
3903 // Optimize multiply by 2 with EFLAGS result.
3904 let AddedComplexity = 2 in {
3905 def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
3907 (ADD16rr GR16:$src1, GR16:$src1)>;
3909 def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
3911 (ADD32rr GR32:$src1, GR32:$src1)>;
3914 // INC and DEC with EFLAGS result. Note that these do not set CF.
3915 def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
3917 def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
3920 def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
3922 def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
3926 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
3927 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
3928 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
3930 (INC16m addr:$dst)>, Requires<[In32BitMode]>;
3931 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
3932 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
3933 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
3935 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;
3937 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
3938 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
3939 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
3941 (INC32m addr:$dst)>, Requires<[In32BitMode]>;
3942 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
3943 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
3944 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
3946 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
3948 //===----------------------------------------------------------------------===//
3949 // Floating Point Stack Support
3950 //===----------------------------------------------------------------------===//
3952 include "X86InstrFPStack.td"
3954 //===----------------------------------------------------------------------===//
3956 //===----------------------------------------------------------------------===//
3958 include "X86Instr64bit.td"
3960 //===----------------------------------------------------------------------===//
3961 // XMM Floating point support (requires SSE / SSE2)
3962 //===----------------------------------------------------------------------===//
3964 include "X86InstrSSE.td"
3966 //===----------------------------------------------------------------------===//
3967 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
3968 //===----------------------------------------------------------------------===//
3970 include "X86InstrMMX.td"