1 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // *mem - Operand definitions for the funky X86 addressing mode operands.
19 class X86MemOperand<ValueType Ty> : Operand<Ty> {
20 let NumMIOperands = 4;
21 let PrintMethod = "printMemoryOperand";
24 def i8mem : X86MemOperand<i8>;
25 def i16mem : X86MemOperand<i16>;
26 def i32mem : X86MemOperand<i32>;
27 def i64mem : X86MemOperand<i64>;
28 def f32mem : X86MemOperand<f32>;
29 def f64mem : X86MemOperand<f64>;
30 def f80mem : X86MemOperand<f80>;
32 // PCRelative calls need special operand formatting.
33 let PrintMethod = "printCallOperand" in
34 def calltarget : Operand<i32>;
36 // Format specifies the encoding used by the instruction. This is part of the
37 // ad-hoc solution used to emit machine instruction encodings by our machine
39 class Format<bits<5> val> {
43 def Pseudo : Format<0>; def RawFrm : Format<1>;
44 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
45 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
46 def MRMSrcMem : Format<6>;
47 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
48 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
49 def MRM6r : Format<22>; def MRM7r : Format<23>;
50 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
51 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
52 def MRM6m : Format<30>; def MRM7m : Format<31>;
54 // ImmType - This specifies the immediate type used by an instruction. This is
55 // part of the ad-hoc solution used to emit machine instruction encodings by our
56 // machine code emitter.
57 class ImmType<bits<2> val> {
60 def NoImm : ImmType<0>;
61 def Imm8 : ImmType<1>;
62 def Imm16 : ImmType<2>;
63 def Imm32 : ImmType<3>;
65 // FPFormat - This specifies what form this FP instruction has. This is used by
66 // the Floating-Point stackifier pass.
67 class FPFormat<bits<3> val> {
70 def NotFP : FPFormat<0>;
71 def ZeroArgFP : FPFormat<1>;
72 def OneArgFP : FPFormat<2>;
73 def OneArgFPRW : FPFormat<3>;
74 def TwoArgFP : FPFormat<4>;
75 def CompareFP : FPFormat<5>;
76 def CondMovFP : FPFormat<6>;
77 def SpecialFP : FPFormat<7>;
80 class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr>
82 let Namespace = "X86";
84 bits<8> Opcode = opcod;
86 bits<5> FormBits = Form.Value;
88 bits<2> ImmTypeBits = ImmT.Value;
90 dag OperandList = ops;
91 string AsmString = AsmStr;
94 // Attributes specific to X86 instructions...
96 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
98 bits<4> Prefix = 0; // Which prefix byte does this inst have?
99 FPFormat FPForm; // What flavor of FP instruction is this?
100 bits<3> FPFormBits = 0;
103 class Imp<list<Register> uses, list<Register> defs> {
104 list<Register> Uses = uses;
105 list<Register> Defs = defs;
109 // Prefix byte classes which are used to indicate to the ad-hoc machine code
110 // emitter that various prefix bytes are required.
111 class OpSize { bit hasOpSizePrefix = 1; }
112 class TB { bits<4> Prefix = 1; }
113 class REP { bits<4> Prefix = 2; }
114 class D8 { bits<4> Prefix = 3; }
115 class D9 { bits<4> Prefix = 4; }
116 class DA { bits<4> Prefix = 5; }
117 class DB { bits<4> Prefix = 6; }
118 class DC { bits<4> Prefix = 7; }
119 class DD { bits<4> Prefix = 8; }
120 class DE { bits<4> Prefix = 9; }
121 class DF { bits<4> Prefix = 10; }
124 //===----------------------------------------------------------------------===//
125 // Instruction templates...
127 class I<bits<8> o, Format f, dag ops, string asm>
128 : X86Inst<o, f, NoImm, ops, asm>;
129 class Ii8 <bits<8> o, Format f, dag ops, string asm>
130 : X86Inst<o, f, Imm8 , ops, asm>;
131 class Ii16<bits<8> o, Format f, dag ops, string asm>
132 : X86Inst<o, f, Imm16, ops, asm>;
133 class Ii32<bits<8> o, Format f, dag ops, string asm>
134 : X86Inst<o, f, Imm32, ops, asm>;
136 //===----------------------------------------------------------------------===//
137 // Instruction list...
140 def PHI : I<0, Pseudo, (ops), "PHINODE">; // PHI node.
141 def NOOP : I<0x90, RawFrm, (ops), "nop">; // nop
143 def ADJCALLSTACKDOWN : I<0, Pseudo, (ops), "#ADJCALLSTACKDOWN">;
144 def ADJCALLSTACKUP : I<0, Pseudo, (ops), "#ADJCALLSTACKUP">;
145 def IMPLICIT_USE : I<0, Pseudo, (ops), "#IMPLICIT_USE">;
146 def IMPLICIT_DEF : I<0, Pseudo, (ops), "#IMPLICIT_DEF">;
147 let isTerminator = 1 in
148 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
149 def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL">;
151 //===----------------------------------------------------------------------===//
152 // Control Flow Instructions...
155 // Return instruction...
156 let isTerminator = 1, isReturn = 1, isBarrier = 1 in
157 def RET : I<0xC3, RawFrm, (ops), "ret">;
159 // All branches are RawFrm, Void, Branch, and Terminators
160 let isBranch = 1, isTerminator = 1 in
161 class IBr<bits<8> opcode, dag ops, string asm> : I<opcode, RawFrm, ops, asm>;
164 def JMP : IBr<0xE9, (ops i32imm:$dst), "jmp $dst">;
165 def JB : IBr<0x82, (ops i32imm:$dst), "jb $dst">, TB;
166 def JAE : IBr<0x83, (ops i32imm:$dst), "jae $dst">, TB;
167 def JE : IBr<0x84, (ops i32imm:$dst), "je $dst">, TB;
168 def JNE : IBr<0x85, (ops i32imm:$dst), "jne $dst">, TB;
169 def JBE : IBr<0x86, (ops i32imm:$dst), "jbe $dst">, TB;
170 def JA : IBr<0x87, (ops i32imm:$dst), "ja $dst">, TB;
171 def JS : IBr<0x88, (ops i32imm:$dst), "js $dst">, TB;
172 def JNS : IBr<0x89, (ops i32imm:$dst), "jns $dst">, TB;
173 def JL : IBr<0x8C, (ops i32imm:$dst), "jl $dst">, TB;
174 def JGE : IBr<0x8D, (ops i32imm:$dst), "jge $dst">, TB;
175 def JLE : IBr<0x8E, (ops i32imm:$dst), "jle $dst">, TB;
176 def JG : IBr<0x8F, (ops i32imm:$dst), "jg $dst">, TB;
179 //===----------------------------------------------------------------------===//
180 // Call Instructions...
183 // All calls clobber the non-callee saved registers...
184 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0] in {
185 def CALLpcrel32 : I<0xE8, RawFrm, (ops calltarget:$dst), "call $dst">;
186 def CALL32r : I<0xFF, MRM2r, (ops R32:$dst), "call {*}$dst">;
187 def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst">;
191 //===----------------------------------------------------------------------===//
192 // Miscellaneous Instructions...
194 def LEAVE : I<0xC9, RawFrm,
195 (ops), "leave">, Imp<[EBP,ESP],[EBP,ESP]>;
196 def POP32r : I<0x58, AddRegFrm,
197 (ops R32:$reg), "pop{l} $reg">, Imp<[ESP],[ESP]>;
199 let isTwoAddress = 1 in // R32 = bswap R32
200 def BSWAP32r : I<0xC8, AddRegFrm,
201 (ops R32:$dst, R32:$src), "bswap{l} $dst">, TB;
203 def XCHG8rr : I<0x86, MRMDestReg, // xchg R8, R8
204 (ops R8:$src1, R8:$src2),
205 "xchg{b} {$src2|$src1}, {$src1|$src2}">;
206 def XCHG16rr : I<0x87, MRMDestReg, // xchg R16, R16
207 (ops R16:$src1, R16:$src2),
208 "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize;
209 def XCHG32rr : I<0x87, MRMDestReg, // xchg R32, R32
210 (ops R32:$src1, R32:$src2),
211 "xchg{l} {$src2|$src1}, {$src1|$src2}">;
213 def XCHG8mr : I<0x86, MRMDestMem,
214 (ops i8mem:$src1, R8:$src2),
215 "xchg{b} {$src2|$src1}, {$src1|$src2}">;
216 def XCHG16mr : I<0x87, MRMDestMem,
217 (ops i16mem:$src1, R16:$src2),
218 "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize;
219 def XCHG32mr : I<0x87, MRMDestMem,
220 (ops i32mem:$src1, R32:$src2),
221 "xchg{l} {$src2|$src1}, {$src1|$src2}">;
222 def XCHG8rm : I<0x86, MRMSrcMem,
223 (ops R8:$src1, i8mem:$src2),
224 "xchg{b} {$src2|$src1}, {$src1|$src2}">;
225 def XCHG16rm : I<0x87, MRMSrcMem,
226 (ops R16:$src1, i16mem:$src2),
227 "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize;
228 def XCHG32rm : I<0x87, MRMSrcMem,
229 (ops R32:$src1, i32mem:$src2),
230 "xchg{l} {$src2|$src1}, {$src1|$src2}">;
232 def LEA16r : I<0x8D, MRMSrcMem,
233 (ops R16:$dst, i32mem:$src),
234 "lea{w} {$src|$dst}, {$dst|$src}">, OpSize;
235 def LEA32r : I<0x8D, MRMSrcMem,
236 (ops R32:$dst, i32mem:$src),
237 "lea{l} {$src|$dst}, {$dst|$src}">;
240 def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}">,
241 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
242 def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}">,
243 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize;
244 def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsd|rep movsd}">,
245 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
247 def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}">,
248 Imp<[AL,ECX,EDI], [ECX,EDI]>, REP;
249 def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}">,
250 Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize;
251 def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosd|rep stosd}">,
252 Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP;
255 //===----------------------------------------------------------------------===//
256 // Input/Output Instructions...
258 def IN8rr : I<0xEC, RawFrm, (ops),
259 "in{b} {%DX, %AL|AL, DX}">, Imp<[DX], [AL]>;
260 def IN16rr : I<0xED, RawFrm, (ops),
261 "in{w} {%DX, %AX|AX, DX}">, Imp<[DX], [AX]>, OpSize;
262 def IN32rr : I<0xED, RawFrm, (ops),
263 "in{l} {%DX, %EAX|EAX, DX}">, Imp<[DX],[EAX]>;
265 def IN8ri : Ii16<0xE4, RawFrm, (ops i16imm:$port),
266 "in{b} {$port, %AL|AL, $port}">, Imp<[], [AL]>;
267 def IN16ri : Ii16<0xE5, RawFrm, (ops i16imm:$port),
268 "in{w} {$port, %AX|AX, $port}">, Imp<[], [AX]>, OpSize;
269 def IN32ri : Ii16<0xE5, RawFrm, (ops i16imm:$port),
270 "in{l} {$port, %EAX|EAX, $port}">, Imp<[],[EAX]>;
272 def OUT8rr : I<0xEE, RawFrm, (ops),
273 "out{b} {%AL, %DX|DX, AL}">, Imp<[DX, AL], []>;
274 def OUT16rr : I<0xEF, RawFrm, (ops),
275 "out{w} {%AX, %DX|DX, AX}">, Imp<[DX, AX], []>, OpSize;
276 def OUT32rr : I<0xEF, RawFrm, (ops),
277 "out{l} {%EAX, %DX|DX, EAX}">, Imp<[DX, EAX], []>;
279 def OUT8ir : Ii16<0xE6, RawFrm, (ops i16imm:$port),
280 "out{b} {%AL, $port|$port, AL}">, Imp<[AL], []>;
281 def OUT16ir : Ii16<0xE7, RawFrm, (ops i16imm:$port),
282 "out{w} {%AX, $port|$port, AX}">, Imp<[AX], []>, OpSize;
283 def OUT32ir : Ii16<0xE7, RawFrm, (ops i16imm:$port),
284 "out{l} {%EAX, $port|$port, %EAX}">, Imp<[EAX], []>;
286 //===----------------------------------------------------------------------===//
287 // Move Instructions...
289 def MOV8rr : I<0x88, MRMDestReg, (ops R8 :$dst, R8 :$src),
290 "mov{b} {$src, $dst|$dst, $src}">;
291 def MOV16rr : I<0x89, MRMDestReg, (ops R16:$dst, R16:$src),
292 "mov{w} {$src, $dst|$dst, $src}">, OpSize;
293 def MOV32rr : I<0x89, MRMDestReg, (ops R32:$dst, R32:$src),
294 "mov{l} {$src, $dst|$dst, $src}">;
295 def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops R8 :$dst, i8imm :$src),
296 "mov{b} {$src, $dst|$dst, $src}">;
297 def MOV16ri : Ii16<0xB8, AddRegFrm, (ops R16:$dst, i16imm:$src),
298 "mov{w} {$src, $dst|$dst, $src}">, OpSize;
299 def MOV32ri : Ii32<0xB8, AddRegFrm, (ops R32:$dst, i32imm:$src),
300 "mov{l} {$src, $dst|$dst, $src}">;
301 def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src),
302 "mov{b} {$src, $dst|$dst, $src}">;
303 def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src),
304 "mov{w} {$src, $dst|$dst, $src}">, OpSize;
305 def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src),
306 "mov{l} {$src, $dst|$dst, $src}">;
308 def MOV8rm : I<0x8A, MRMSrcMem, (ops R8 :$dst, i8mem :$src),
309 "mov{b} {$src, $dst|$dst, $src}">;
310 def MOV16rm : I<0x8B, MRMSrcMem, (ops R16:$dst, i16mem:$src),
311 "mov{w} {$src, $dst|$dst, $src}">, OpSize;
312 def MOV32rm : I<0x8B, MRMSrcMem, (ops R32:$dst, i32mem:$src),
313 "mov{l} {$src, $dst|$dst, $src}">;
315 def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, R8 :$src),
316 "mov{b} {$src, $dst|$dst, $src}">;
317 def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, R16:$src),
318 "mov{w} {$src, $dst|$dst, $src}">, OpSize;
319 def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32:$src),
320 "mov{l} {$src, $dst|$dst, $src}">;
322 //===----------------------------------------------------------------------===//
323 // Fixed-Register Multiplication and Division Instructions...
326 // Extra precision multiplication
327 def MUL8r : I<0xF6, MRM4r, (ops R8:$src), "mul{b} $src">,
328 Imp<[AL],[AX]>; // AL,AH = AL*R8
329 def MUL16r : I<0xF7, MRM4r, (ops R16:$src), "mul{w} $src">,
330 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
331 def MUL32r : I<0xF7, MRM4r, (ops R32:$src), "mul{l} $src">,
332 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
333 def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src),
334 "mul{b} $src">, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
335 def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src),
336 "mul{w} $src">, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*[mem16]
337 def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src),
338 "mul{l} $src">, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
340 // unsigned division/remainder
341 def DIV8r : I<0xF6, MRM6r, (ops R8:$src), // AX/r8 = AL,AH
342 "div{b} $src">, Imp<[AX],[AX]>;
343 def DIV16r : I<0xF7, MRM6r, (ops R16:$src), // DX:AX/r16 = AX,DX
344 "div{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize;
345 def DIV32r : I<0xF7, MRM6r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX
346 "div{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>;
347 def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), // AX/[mem8] = AL,AH
348 "div{b} $src">, Imp<[AX],[AX]>;
349 def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX
350 "div{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize;
351 def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
352 "div{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>;
354 // Signed division/remainder.
355 def IDIV8r : I<0xF6, MRM7r, (ops R8:$src), // AX/r8 = AL,AH
356 "idiv{b} $src">, Imp<[AX],[AX]>;
357 def IDIV16r: I<0xF7, MRM7r, (ops R16:$src), // DX:AX/r16 = AX,DX
358 "idiv{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize;
359 def IDIV32r: I<0xF7, MRM7r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX
360 "idiv{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>;
361 def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), // AX/[mem8] = AL,AH
362 "idiv{b} $src">, Imp<[AX],[AX]>;
363 def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX
364 "idiv{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize;
365 def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
366 "idiv{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>;
368 // Sign-extenders for division.
369 def CBW : I<0x98, RawFrm, (ops),
370 "{cbtw|cbw}">, Imp<[AL],[AH]>; // AX = signext(AL)
371 def CWD : I<0x99, RawFrm, (ops),
372 "{cwtd|cwd}">, Imp<[AX],[DX]>; // DX:AX = signext(AX)
373 def CDQ : I<0x99, RawFrm, (ops),
374 "{cltd|cdq}">, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX)
377 //===----------------------------------------------------------------------===//
378 // Two address Instructions...
380 let isTwoAddress = 1 in {
383 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, R16 = R16
384 (ops R16:$dst, R16:$src1, R16:$src2),
385 "cmovb {$src2, $dst|$dst, $src2}">, TB, OpSize;
386 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, R16 = [mem16]
387 (ops R16:$dst, R16:$src1, i16mem:$src2),
388 "cmovb {$src2, $dst|$dst, $src2}">, TB, OpSize;
389 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, R32 = R32
390 (ops R32:$dst, R32:$src1, R32:$src2),
391 "cmovb {$src2, $dst|$dst, $src2}">, TB;
392 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, R32 = [mem32]
393 (ops R32:$dst, R32:$src1, i32mem:$src2),
394 "cmovb {$src2, $dst|$dst, $src2}">, TB;
396 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, R16 = R16
397 (ops R16:$dst, R16:$src1, R16:$src2),
398 "cmovae {$src2, $dst|$dst, $src2}">, TB, OpSize;
399 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, R16 = [mem16]
400 (ops R16:$dst, R16:$src1, i16mem:$src2),
401 "cmovae {$src2, $dst|$dst, $src2}">, TB, OpSize;
402 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, R32 = R32
403 (ops R32:$dst, R32:$src1, R32:$src2),
404 "cmovae {$src2, $dst|$dst, $src2}">, TB;
405 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, R32 = [mem32]
406 (ops R32:$dst, R32:$src1, i32mem:$src2),
407 "cmovae {$src2, $dst|$dst, $src2}">, TB;
409 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, R16 = R16
410 (ops R16:$dst, R16:$src1, R16:$src2),
411 "cmove {$src2, $dst|$dst, $src2}">, TB, OpSize;
412 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, R16 = [mem16]
413 (ops R16:$dst, R16:$src1, i16mem:$src2),
414 "cmove {$src2, $dst|$dst, $src2}">, TB, OpSize;
415 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, R32 = R32
416 (ops R32:$dst, R32:$src1, R32:$src2),
417 "cmove {$src2, $dst|$dst, $src2}">, TB;
418 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, R32 = [mem32]
419 (ops R32:$dst, R32:$src1, i32mem:$src2),
420 "cmove {$src2, $dst|$dst, $src2}">, TB;
422 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, R16 = R16
423 (ops R16:$dst, R16:$src1, R16:$src2),
424 "cmovne {$src2, $dst|$dst, $src2}">, TB, OpSize;
425 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, R16 = [mem16]
426 (ops R16:$dst, R16:$src1, i16mem:$src2),
427 "cmovne {$src2, $dst|$dst, $src2}">, TB, OpSize;
428 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, R32 = R32
429 (ops R32:$dst, R32:$src1, R32:$src2),
430 "cmovne {$src2, $dst|$dst, $src2}">, TB;
431 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, R32 = [mem32]
432 (ops R32:$dst, R32:$src1, i32mem:$src2),
433 "cmovne {$src2, $dst|$dst, $src2}">, TB;
435 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, R16 = R16
436 (ops R16:$dst, R16:$src1, R16:$src2),
437 "cmovbe {$src2, $dst|$dst, $src2}">, TB, OpSize;
438 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, R16 = [mem16]
439 (ops R16:$dst, R16:$src1, i16mem:$src2),
440 "cmovbe {$src2, $dst|$dst, $src2}">, TB, OpSize;
441 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, R32 = R32
442 (ops R32:$dst, R32:$src1, R32:$src2),
443 "cmovbe {$src2, $dst|$dst, $src2}">, TB;
444 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, R32 = [mem32]
445 (ops R32:$dst, R32:$src1, i32mem:$src2),
446 "cmovbe {$src2, $dst|$dst, $src2}">, TB;
448 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, R16 = R16
449 (ops R16:$dst, R16:$src1, R16:$src2),
450 "cmova {$src2, $dst|$dst, $src2}">, TB, OpSize;
451 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, R16 = [mem16]
452 (ops R16:$dst, R16:$src1, i16mem:$src2),
453 "cmova {$src2, $dst|$dst, $src2}">, TB, OpSize;
454 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, R32 = R32
455 (ops R32:$dst, R32:$src1, R32:$src2),
456 "cmova {$src2, $dst|$dst, $src2}">, TB;
457 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, R32 = [mem32]
458 (ops R32:$dst, R32:$src1, i32mem:$src2),
459 "cmova {$src2, $dst|$dst, $src2}">, TB;
461 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, R16 = R16
462 (ops R16:$dst, R16:$src1, R16:$src2),
463 "cmovs {$src2, $dst|$dst, $src2}">, TB, OpSize;
464 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, R16 = [mem16]
465 (ops R16:$dst, R16:$src1, i16mem:$src2),
466 "cmovs {$src2, $dst|$dst, $src2}">, TB, OpSize;
467 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, R32 = R32
468 (ops R32:$dst, R32:$src1, R32:$src2),
469 "cmovs {$src2, $dst|$dst, $src2}">, TB;
470 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, R32 = [mem32]
471 (ops R32:$dst, R32:$src1, i32mem:$src2),
472 "cmovs {$src2, $dst|$dst, $src2}">, TB;
474 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, R16 = R16
475 (ops R16:$dst, R16:$src1, R16:$src2),
476 "cmovns {$src2, $dst|$dst, $src2}">, TB, OpSize;
477 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, R16 = [mem16]
478 (ops R16:$dst, R16:$src1, i16mem:$src2),
479 "cmovns {$src2, $dst|$dst, $src2}">, TB, OpSize;
480 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, R32 = R32
481 (ops R32:$dst, R32:$src1, R32:$src2),
482 "cmovns {$src2, $dst|$dst, $src2}">, TB;
483 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, R32 = [mem32]
484 (ops R32:$dst, R32:$src1, i32mem:$src2),
485 "cmovns {$src2, $dst|$dst, $src2}">, TB;
487 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, R16 = R16
488 (ops R16:$dst, R16:$src1, R16:$src2),
489 "cmovl {$src2, $dst|$dst, $src2}">, TB, OpSize;
490 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, R16 = [mem16]
491 (ops R16:$dst, R16:$src1, i16mem:$src2),
492 "cmovl {$src2, $dst|$dst, $src2}">, TB, OpSize;
493 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, R32 = R32
494 (ops R32:$dst, R32:$src1, R32:$src2),
495 "cmovl {$src2, $dst|$dst, $src2}">, TB;
496 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, R32 = [mem32]
497 (ops R32:$dst, R32:$src1, i32mem:$src2),
498 "cmovl {$src2, $dst|$dst, $src2}">, TB;
500 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, R16 = R16
501 (ops R16:$dst, R16:$src1, R16:$src2),
502 "cmovge {$src2, $dst|$dst, $src2}">, TB, OpSize;
503 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, R16 = [mem16]
504 (ops R16:$dst, R16:$src1, i16mem:$src2),
505 "cmovge {$src2, $dst|$dst, $src2}">, TB, OpSize;
506 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, R32 = R32
507 (ops R32:$dst, R32:$src1, R32:$src2),
508 "cmovge {$src2, $dst|$dst, $src2}">, TB;
509 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, R32 = [mem32]
510 (ops R32:$dst, R32:$src1, i32mem:$src2),
511 "cmovge {$src2, $dst|$dst, $src2}">, TB;
513 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, R16 = R16
514 (ops R16:$dst, R16:$src1, R16:$src2),
515 "cmovle {$src2, $dst|$dst, $src2}">, TB, OpSize;
516 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, R16 = [mem16]
517 (ops R16:$dst, R16:$src1, i16mem:$src2),
518 "cmovle {$src2, $dst|$dst, $src2}">, TB, OpSize;
519 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, R32 = R32
520 (ops R32:$dst, R32:$src1, R32:$src2),
521 "cmovle {$src2, $dst|$dst, $src2}">, TB;
522 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, R32 = [mem32]
523 (ops R32:$dst, R32:$src1, i32mem:$src2),
524 "cmovle {$src2, $dst|$dst, $src2}">, TB;
526 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, R16 = R16
527 (ops R16:$dst, R16:$src1, R16:$src2),
528 "cmovg {$src2, $dst|$dst, $src2}">, TB, OpSize;
529 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, R16 = [mem16]
530 (ops R16:$dst, R16:$src1, i16mem:$src2),
531 "cmovg {$src2, $dst|$dst, $src2}">, TB, OpSize;
532 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, R32 = R32
533 (ops R32:$dst, R32:$src1, R32:$src2),
534 "cmovg {$src2, $dst|$dst, $src2}">, TB;
535 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, R32 = [mem32]
536 (ops R32:$dst, R32:$src1, i32mem:$src2),
537 "cmovg {$src2, $dst|$dst, $src2}">, TB;
539 // unary instructions
540 def NEG8r : I<0xF6, MRM3r, (ops R8 :$dst, R8 :$src), "neg{b} $dst">;
541 def NEG16r : I<0xF7, MRM3r, (ops R16:$dst, R16:$src), "neg{w} $dst">, OpSize;
542 def NEG32r : I<0xF7, MRM3r, (ops R32:$dst, R32:$src), "neg{l} $dst">;
543 let isTwoAddress = 0 in {
544 def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst">;
545 def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst">, OpSize;
546 def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst">;
549 def NOT8r : I<0xF6, MRM2r, (ops R8 :$dst, R8 :$src), "not{b} $dst">;
550 def NOT16r : I<0xF7, MRM2r, (ops R16:$dst, R16:$src), "not{w} $dst">, OpSize;
551 def NOT32r : I<0xF7, MRM2r, (ops R32:$dst, R32:$src), "not{l} $dst">;
552 let isTwoAddress = 0 in {
553 def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst">;
554 def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst">, OpSize;
555 def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst">;
558 def INC8r : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc{b} $dst">;
559 def INC16r : I<0xFF, MRM0r, (ops R16:$dst, R16:$src), "inc{w} $dst">, OpSize;
560 def INC32r : I<0xFF, MRM0r, (ops R32:$dst, R32:$src), "inc{l} $dst">;
561 let isTwoAddress = 0 in {
562 def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst">;
563 def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst">, OpSize;
564 def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst">;
567 def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec{b} $dst">;
568 def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec{w} $dst">, OpSize;
569 def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec{l} $dst">;
571 let isTwoAddress = 0 in {
572 def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst">;
573 def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst">, OpSize;
574 def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst">;
577 // Logical operators...
578 def AND8rr : I<0x20, MRMDestReg,
579 (ops R8 :$dst, R8 :$src1, R8 :$src2),
580 "and{b} {$src2, $dst|$dst, $src2}">;
581 def AND16rr : I<0x21, MRMDestReg,
582 (ops R16:$dst, R16:$src1, R16:$src2),
583 "and{w} {$src2, $dst|$dst, $src2}">, OpSize;
584 def AND32rr : I<0x21, MRMDestReg,
585 (ops R32:$dst, R32:$src1, R32:$src2),
586 "and{l} {$src2, $dst|$dst, $src2}">;
588 def AND8rm : I<0x22, MRMSrcMem,
589 (ops R8 :$dst, R8 :$src1, i8mem :$src2),
590 "and{b} {$src2, $dst|$dst, $src2}">;
591 def AND16rm : I<0x23, MRMSrcMem,
592 (ops R16:$dst, R16:$src1, i16mem:$src2),
593 "and{w} {$src2, $dst|$dst, $src2}">, OpSize;
594 def AND32rm : I<0x23, MRMSrcMem,
595 (ops R32:$dst, R32:$src1, i32mem:$src2),
596 "and{l} {$src2, $dst|$dst, $src2}">;
598 def AND8ri : Ii8<0x80, MRM4r,
599 (ops R8 :$dst, R8 :$src1, i8imm :$src2),
600 "and{b} {$src2, $dst|$dst, $src2}">;
601 def AND16ri : Ii16<0x81, MRM4r,
602 (ops R16:$dst, R16:$src1, i16imm:$src2),
603 "and{w} {$src2, $dst|$dst, $src2}">, OpSize;
604 def AND32ri : Ii32<0x81, MRM4r,
605 (ops R32:$dst, R32:$src1, i32imm:$src2),
606 "and{l} {$src2, $dst|$dst, $src2}">;
607 def AND16ri8 : Ii8<0x83, MRM4r,
608 (ops R16:$dst, R16:$src1, i8imm:$src2),
609 "and{w} {$src2, $dst|$dst, $src2}" >, OpSize;
610 def AND32ri8 : Ii8<0x83, MRM4r,
611 (ops R32:$dst, R32:$src1, i8imm:$src2),
612 "and{l} {$src2, $dst|$dst, $src2}">;
614 let isTwoAddress = 0 in {
615 def AND8mr : I<0x20, MRMDestMem,
616 (ops i8mem :$dst, R8 :$src),
617 "and{b} {$src, $dst|$dst, $src}">;
618 def AND16mr : I<0x21, MRMDestMem,
619 (ops i16mem:$dst, R16:$src),
620 "and{w} {$src, $dst|$dst, $src}">, OpSize;
621 def AND32mr : I<0x21, MRMDestMem,
622 (ops i32mem:$dst, R32:$src),
623 "and{l} {$src, $dst|$dst, $src}">;
624 def AND8mi : Ii8<0x80, MRM4m,
625 (ops i8mem :$dst, i8imm :$src),
626 "and{b} {$src, $dst|$dst, $src}">;
627 def AND16mi : Ii16<0x81, MRM4m,
628 (ops i16mem:$dst, i16imm:$src),
629 "and{w} {$src, $dst|$dst, $src}">, OpSize;
630 def AND32mi : Ii32<0x81, MRM4m,
631 (ops i32mem:$dst, i32imm:$src),
632 "and{l} {$src, $dst|$dst, $src}">;
633 def AND16mi8 : Ii8<0x83, MRM4m,
634 (ops i16mem:$dst, i8imm :$src),
635 "and{w} {$src, $dst|$dst, $src}">, OpSize;
636 def AND32mi8 : Ii8<0x83, MRM4m,
637 (ops i32mem:$dst, i8imm :$src),
638 "and{l} {$src, $dst|$dst, $src}">;
642 def OR8rr : I<0x08, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
643 "or{b} {$src2, $dst|$dst, $src2}">;
644 def OR16rr : I<0x09, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
645 "or{w} {$src2, $dst|$dst, $src2}">, OpSize;
646 def OR32rr : I<0x09, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
647 "or{l} {$src2, $dst|$dst, $src2}">;
648 def OR8rm : I<0x0A, MRMSrcMem , (ops R8 :$dst, R8 :$src1, i8mem :$src2),
649 "or{b} {$src2, $dst|$dst, $src2}">;
650 def OR16rm : I<0x0B, MRMSrcMem , (ops R16:$dst, R16:$src1, i16mem:$src2),
651 "or{w} {$src2, $dst|$dst, $src2}">, OpSize;
652 def OR32rm : I<0x0B, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2),
653 "or{l} {$src2, $dst|$dst, $src2}">;
655 def OR8ri : Ii8 <0x80, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
656 "or{b} {$src2, $dst|$dst, $src2}">;
657 def OR16ri : Ii16<0x81, MRM1r, (ops R16:$dst, R16:$src1, i16imm:$src2),
658 "or{w} {$src2, $dst|$dst, $src2}">, OpSize;
659 def OR32ri : Ii32<0x81, MRM1r, (ops R32:$dst, R32:$src1, i32imm:$src2),
660 "or{l} {$src2, $dst|$dst, $src2}">;
662 def OR16ri8 : Ii8<0x83, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
663 "or{w} {$src2, $dst|$dst, $src2}">, OpSize;
664 def OR32ri8 : Ii8<0x83, MRM1r, (ops R32:$dst, R32:$src1, i8imm:$src2),
665 "or{l} {$src2, $dst|$dst, $src2}">;
666 let isTwoAddress = 0 in {
667 def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, R8:$src),
668 "or{b} {$src, $dst|$dst, $src}">;
669 def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, R16:$src),
670 "or{w} {$src, $dst|$dst, $src}">, OpSize;
671 def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, R32:$src),
672 "or{l} {$src, $dst|$dst, $src}">;
673 def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src),
674 "or{b} {$src, $dst|$dst, $src}">;
675 def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src),
676 "or{w} {$src, $dst|$dst, $src}">, OpSize;
677 def OR32mi : Ii32<0x81, MRM1m, (ops i32mem:$dst, i32imm:$src),
678 "or{l} {$src, $dst|$dst, $src}">;
679 def OR16mi8 : Ii8<0x83, MRM1m, (ops i16mem:$dst, i8imm:$src),
680 "or{w} {$src, $dst|$dst, $src}">, OpSize;
681 def OR32mi8 : Ii8<0x83, MRM1m, (ops i32mem:$dst, i8imm:$src),
682 "or{l} {$src, $dst|$dst, $src}">;
686 def XOR8rr : I<0x30, MRMDestReg,
687 (ops R8 :$dst, R8 :$src1, R8 :$src2),
688 "xor{b} {$src2, $dst|$dst, $src2}">;
689 def XOR16rr : I<0x31, MRMDestReg,
690 (ops R16:$dst, R16:$src1, R16:$src2),
691 "xor{w} {$src2, $dst|$dst, $src2}">, OpSize;
692 def XOR32rr : I<0x31, MRMDestReg,
693 (ops R32:$dst, R32:$src1, R32:$src2),
694 "xor{l} {$src2, $dst|$dst, $src2}">;
695 def XOR8rm : I<0x32, MRMSrcMem ,
696 (ops R8 :$dst, R8:$src1, i8mem :$src2),
697 "xor{b} {$src2, $dst|$dst, $src2}">;
698 def XOR16rm : I<0x33, MRMSrcMem ,
699 (ops R16:$dst, R8:$src1, i16mem:$src2),
700 "xor{w} {$src2, $dst|$dst, $src2}">, OpSize;
701 def XOR32rm : I<0x33, MRMSrcMem ,
702 (ops R32:$dst, R8:$src1, i32mem:$src2),
703 "xor{l} {$src2, $dst|$dst, $src2}">;
705 def XOR8ri : Ii8<0x80, MRM6r,
706 (ops R8:$dst, R8:$src1, i8imm:$src2),
707 "xor{b} {$src2, $dst|$dst, $src2}">;
708 def XOR16ri : Ii16<0x81, MRM6r,
709 (ops R16:$dst, R16:$src1, i16imm:$src2),
710 "xor{w} {$src2, $dst|$dst, $src2}">, OpSize;
711 def XOR32ri : Ii32<0x81, MRM6r,
712 (ops R32:$dst, R32:$src1, i32imm:$src2),
713 "xor{l} {$src2, $dst|$dst, $src2}">;
714 def XOR16ri8 : Ii8<0x83, MRM6r,
715 (ops R16:$dst, R16:$src1, i8imm:$src2),
716 "xor{w} {$src2, $dst|$dst, $src2}">, OpSize;
717 def XOR32ri8 : Ii8<0x83, MRM6r,
718 (ops R32:$dst, R32:$src1, i8imm:$src2),
719 "xor{l} {$src2, $dst|$dst, $src2}">;
720 let isTwoAddress = 0 in {
721 def XOR8mr : I<0x30, MRMDestMem,
722 (ops i8mem :$dst, R8 :$src),
723 "xor{b} {$src, $dst|$dst, $src}">;
724 def XOR16mr : I<0x31, MRMDestMem,
725 (ops i16mem:$dst, R16:$src),
726 "xor{w} {$src, $dst|$dst, $src}">, OpSize;
727 def XOR32mr : I<0x31, MRMDestMem,
728 (ops i32mem:$dst, R32:$src),
729 "xor{l} {$src, $dst|$dst, $src}">;
730 def XOR8mi : Ii8<0x80, MRM6m,
731 (ops i8mem :$dst, i8imm :$src),
732 "xor{b} {$src, $dst|$dst, $src}">;
733 def XOR16mi : Ii16<0x81, MRM6m,
734 (ops i16mem:$dst, i16imm:$src),
735 "xor{w} {$src, $dst|$dst, $src}">, OpSize;
736 def XOR32mi : Ii32<0x81, MRM6m,
737 (ops i32mem:$dst, i32imm:$src),
738 "xor{l} {$src, $dst|$dst, $src}">;
739 def XOR16mi8 : Ii8<0x83, MRM6m,
740 (ops i16mem:$dst, i8imm :$src),
741 "xor{w} {$src, $dst|$dst, $src}">, OpSize;
742 def XOR32mi8 : Ii8<0x83, MRM6m,
743 (ops i32mem:$dst, i8imm :$src),
744 "xor{l} {$src, $dst|$dst, $src}">;
747 // Shift instructions
748 // FIXME: provide shorter instructions when imm8 == 1
749 def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
750 "shl{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
751 def SHL16rCL : I<0xD3, MRM4r, (ops R16:$dst, R16:$src),
752 "shl{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
753 def SHL32rCL : I<0xD3, MRM4r, (ops R32:$dst, R32:$src),
754 "shl{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
755 def SHL8ri : Ii8<0xC0, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
756 "shl{b} {$src2, $dst|$dst, $src2}">;
757 def SHL16ri : Ii8<0xC1, MRM4r, (ops R16:$dst, R16:$src1, i8imm:$src2),
758 "shl{w} {$src2, $dst|$dst, $src2}">, OpSize;
759 def SHL32ri : Ii8<0xC1, MRM4r, (ops R32:$dst, R32:$src1, i8imm:$src2),
760 "shl{l} {$src2, $dst|$dst, $src2}">;
762 let isTwoAddress = 0 in {
763 def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst),
764 "shl{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
765 def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst),
766 "shl{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
767 def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst),
768 "shl{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
769 def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src),
770 "shl{b} {$src, $dst|$dst, $src}">;
771 def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src),
772 "shl{w} {$src, $dst|$dst, $src}">, OpSize;
773 def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src),
774 "shl{l} {$src, $dst|$dst, $src}">;
777 def SHR8rCL : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src),
778 "shr{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
779 def SHR16rCL : I<0xD3, MRM5r, (ops R16:$dst, R16:$src),
780 "shr{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
781 def SHR32rCL : I<0xD3, MRM5r, (ops R32:$dst, R32:$src),
782 "shr{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
784 def SHR8ri : Ii8<0xC0, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2),
785 "shr{b} {$src2, $dst|$dst, $src2}">;
786 def SHR16ri : Ii8<0xC1, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2),
787 "shr{w} {$src2, $dst|$dst, $src2}">, OpSize;
788 def SHR32ri : Ii8<0xC1, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2),
789 "shr{l} {$src2, $dst|$dst, $src2}">;
791 let isTwoAddress = 0 in {
792 def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst),
793 "shr{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
794 def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst),
795 "shr{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
796 def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst),
797 "shr{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
798 def SHR8mi : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src),
799 "shr{b} {$src, $dst|$dst, $src}">;
800 def SHR16mi : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src),
801 "shr{w} {$src, $dst|$dst, $src}">, OpSize;
802 def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src),
803 "shr{l} {$src, $dst|$dst, $src}">;
806 def SAR8rCL : I<0xD2, MRM7r, (ops R8 :$dst, R8 :$src),
807 "sar{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
808 def SAR16rCL : I<0xD3, MRM7r, (ops R16:$dst, R16:$src),
809 "sar{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
810 def SAR32rCL : I<0xD3, MRM7r, (ops R32:$dst, R32:$src),
811 "sar{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
813 def SAR8ri : Ii8<0xC0, MRM7r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
814 "sar{b} {$src2, $dst|$dst, $src2}">;
815 def SAR16ri : Ii8<0xC1, MRM7r, (ops R16:$dst, R16:$src1, i8imm:$src2),
816 "sar{w} {$src2, $dst|$dst, $src2}">, OpSize;
817 def SAR32ri : Ii8<0xC1, MRM7r, (ops R32:$dst, R32:$src1, i8imm:$src2),
818 "sar{l} {$src2, $dst|$dst, $src2}">;
819 let isTwoAddress = 0 in {
820 def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst),
821 "sar{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
822 def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst),
823 "sar{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
824 def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst),
825 "sar{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
826 def SAR8mi : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src),
827 "sar{b} {$src, $dst|$dst, $src}">;
828 def SAR16mi : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src),
829 "sar{w} {$src, $dst|$dst, $src}">, OpSize;
830 def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src),
831 "sar{l} {$src, $dst|$dst, $src}">;
834 def SHLD32rrCL : I<0xA5, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
835 "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}">,
837 def SHRD32rrCL : I<0xAD, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
838 "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}">,
840 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
841 (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3),
842 "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB;
843 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
844 (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3),
845 "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB;
847 let isTwoAddress = 0 in {
848 def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, R32:$src2),
849 "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}">,
851 def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, R32:$src2),
852 "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}">,
854 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
855 (ops i32mem:$dst, R32:$src2, i8imm:$src3),
856 "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB;
857 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
858 (ops i32mem:$dst, R32:$src2, i8imm:$src3),
859 "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB;
864 def ADD8rr : I<0x00, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
865 "add{b} {$src2, $dst|$dst, $src2}">;
866 def ADD16rr : I<0x01, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
867 "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
868 def ADD32rr : I<0x01, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
869 "add{l} {$src2, $dst|$dst, $src2}">;
870 def ADD8rm : I<0x02, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2),
871 "add{b} {$src2, $dst|$dst, $src2}">;
872 def ADD16rm : I<0x03, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
873 "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
874 def ADD32rm : I<0x03, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
875 "add{l} {$src2, $dst|$dst, $src2}">;
877 def ADD8ri : Ii8<0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2),
878 "add{b} {$src2, $dst|$dst, $src2}">;
879 def ADD16ri : Ii16<0x81, MRM0r, (ops R16:$dst, R16:$src1, i16imm:$src2),
880 "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
881 def ADD32ri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2),
882 "add{l} {$src2, $dst|$dst, $src2}">;
884 def ADD16ri8 : Ii8<0x83, MRM0r, (ops R16:$dst, R16:$src1, i8imm:$src2),
885 "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
886 def ADD32ri8 : Ii8<0x83, MRM0r, (ops R32:$dst, R32:$src1, i8imm:$src2),
887 "add{l} {$src2, $dst|$dst, $src2}">;
889 let isTwoAddress = 0 in {
890 def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, R8 :$src2),
891 "add{b} {$src2, $dst|$dst, $src2}">;
892 def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, R16:$src2),
893 "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
894 def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, R32:$src2),
895 "add{l} {$src2, $dst|$dst, $src2}">;
896 def ADD8mi : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2),
897 "add{b} {$src2, $dst|$dst, $src2}">;
898 def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2),
899 "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
900 def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2),
901 "add{l} {$src2, $dst|$dst, $src2}">;
902 def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i8imm :$src2),
903 "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
904 def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i8imm :$src2),
905 "add{l} {$src2, $dst|$dst, $src2}">;
908 def ADC32rr : I<0x11, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
909 "adc{l} {$src2, $dst|$dst, $src2}">;
910 def ADC32rm : I<0x13, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2),
911 "adc{l} {$src2, $dst|$dst, $src2}">;
912 def ADC32ri : Ii32<0x81, MRM2r, (ops R32:$dst, R32:$src1, i32imm:$src2),
913 "adc{l} {$src2, $dst|$dst, $src2}">;
914 def ADC32ri8 : Ii8<0x83, MRM2r, (ops R32:$dst, R32:$src1, i8imm:$src2),
915 "adc{l} {$src2, $dst|$dst, $src2}">;
917 let isTwoAddress = 0 in {
918 def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, R32:$src2),
919 "adc{l} {$src2, $dst|$dst, $src2}">;
920 def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2),
921 "adc{l} {$src2, $dst|$dst, $src2}">;
922 def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i8imm :$src2),
923 "adc{l} {$src2, $dst|$dst, $src2}">;
926 def SUB8rr : I<0x28, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
927 "sub{b} {$src2, $dst|$dst, $src2}">;
928 def SUB16rr : I<0x29, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
929 "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
930 def SUB32rr : I<0x29, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
931 "sub{l} {$src2, $dst|$dst, $src2}">;
932 def SUB8rm : I<0x2A, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2),
933 "sub{b} {$src2, $dst|$dst, $src2}">;
934 def SUB16rm : I<0x2B, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
935 "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
936 def SUB32rm : I<0x2B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
937 "sub{l} {$src2, $dst|$dst, $src2}">;
939 def SUB8ri : Ii8 <0x80, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2),
940 "sub{b} {$src2, $dst|$dst, $src2}">;
941 def SUB16ri : Ii16<0x81, MRM5r, (ops R16:$dst, R16:$src1, i16imm:$src2),
942 "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
943 def SUB32ri : Ii32<0x81, MRM5r, (ops R32:$dst, R32:$src1, i32imm:$src2),
944 "sub{l} {$src2, $dst|$dst, $src2}">;
945 def SUB16ri8 : Ii8<0x83, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2),
946 "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
947 def SUB32ri8 : Ii8<0x83, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2),
948 "sub{l} {$src2, $dst|$dst, $src2}">;
949 let isTwoAddress = 0 in {
950 def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, R8 :$src2),
951 "sub{b} {$src2, $dst|$dst, $src2}">;
952 def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, R16:$src2),
953 "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
954 def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, R32:$src2),
955 "sub{l} {$src2, $dst|$dst, $src2}">;
956 def SUB8mi : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2),
957 "sub{b} {$src2, $dst|$dst, $src2}">;
958 def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2),
959 "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
960 def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2),
961 "sub{l} {$src2, $dst|$dst, $src2}">;
962 def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i8imm :$src2),
963 "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
964 def SUB32mi8 : Ii8<0x83, MRM5m, (ops i32mem:$dst, i8imm :$src2),
965 "sub{l} {$src2, $dst|$dst, $src2}">;
968 def SBB32rr : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
969 "sbb{l} {$src2, $dst|$dst, $src2}">;
971 let isTwoAddress = 0 in {
972 def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, R32:$src2),
973 "sbb{l} {$src2, $dst|$dst, $src2}">;
974 def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2),
975 "sbb{b} {$src2, $dst|$dst, $src2}">;
976 def SBB16mi : Ii32<0x81, MRM3m, (ops i16mem:$dst, i16imm:$src2),
977 "sbb{w} {$src2, $dst|$dst, $src2}">, OpSize;
978 def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2),
979 "sbb{l} {$src2, $dst|$dst, $src2}">;
980 def SBB16mi8 : Ii8<0x83, MRM3m, (ops i16mem:$dst, i8imm :$src2),
981 "sbb{w} {$src2, $dst|$dst, $src2}">, OpSize;
982 def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i8imm :$src2),
983 "sbb{l} {$src2, $dst|$dst, $src2}">;
985 def SBB8ri : Ii8<0x80, MRM3r, (ops R8:$dst, R8:$src1, i8imm:$src2),
986 "sbb{b} {$src2, $dst|$dst, $src2}">;
987 def SBB16ri : Ii16<0x81, MRM3r, (ops R16:$dst, R16:$src1, i16imm:$src2),
988 "sbb{w} {$src2, $dst|$dst, $src2}">, OpSize;
990 def SBB32rm : I<0x1B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
991 "sbb{l} {$src2, $dst|$dst, $src2}">;
992 def SBB32ri : Ii32<0x81, MRM3r, (ops R32:$dst, R32:$src1, i32imm:$src2),
993 "sbb{l} {$src2, $dst|$dst, $src2}">;
995 def SBB16ri8 : Ii8<0x83, MRM3r, (ops R16:$dst, R16:$src1, i8imm:$src2),
996 "sbb{w} {$src2, $dst|$dst, $src2}">, OpSize;
997 def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i8imm:$src2),
998 "sbb{l} {$src2, $dst|$dst, $src2}">;
1000 def IMUL16rr : I<0xAF, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
1001 "imul{w} {$src2, $dst|$dst, $src2}">, TB, OpSize;
1002 def IMUL32rr : I<0xAF, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
1003 "imul{l} {$src2, $dst|$dst, $src2}">, TB;
1004 def IMUL16rm : I<0xAF, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
1005 "imul{w} {$src2, $dst|$dst, $src2}">, TB, OpSize;
1006 def IMUL32rm : I<0xAF, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
1007 "imul{l} {$src2, $dst|$dst, $src2}">, TB;
1009 } // end Two Address instructions
1011 // Suprisingly enough, these are not two address instructions!
1012 def IMUL16rri : Ii16<0x69, MRMSrcReg, // R16 = R16*I16
1013 (ops R16:$dst, R16:$src1, i16imm:$src2),
1014 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">,
1016 def IMUL32rri : Ii32<0x69, MRMSrcReg, // R32 = R32*I32
1017 (ops R32:$dst, R32:$src1, i32imm:$src2),
1018 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}">;
1019 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // R16 = R16*I8
1020 (ops R16:$dst, R16:$src1, i8imm:$src2),
1021 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">, OpSize;
1022 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // R32 = R32*I8
1023 (ops R32:$dst, R32:$src1, i8imm:$src2),
1024 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}">;
1026 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // R16 = [mem16]*I16
1027 (ops R32:$dst, i16mem:$src1, i16imm:$src2),
1028 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">, OpSize;
1029 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // R32 = [mem32]*I32
1030 (ops R32:$dst, i32mem:$src1, i32imm:$src2),
1031 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}">;
1032 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // R16 = [mem16]*I8
1033 (ops R32:$dst, i16mem:$src1, i8imm :$src2),
1034 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">, OpSize;
1035 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // R32 = [mem32]*I8
1036 (ops R32:$dst, i32mem:$src1, i8imm: $src2),
1037 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}">;
1039 //===----------------------------------------------------------------------===//
1040 // Test instructions are just like AND, except they don't generate a result.
1042 def TEST8rr : I<0x84, MRMDestReg, (ops R8:$src1, R8:$src2),
1043 "test{b} {$src2, $src1|$src1, $src2}">;
1044 def TEST16rr : I<0x85, MRMDestReg, (ops R16:$src1, R16:$src2),
1045 "test{w} {$src2, $src1|$src1, $src2}">, OpSize;
1046 def TEST32rr : I<0x85, MRMDestReg, (ops R32:$src1, R32:$src2),
1047 "test{l} {$src2, $src1|$src1, $src2}">;
1048 def TEST8mr : I<0x84, MRMDestMem, (ops i8mem :$src1, R8 :$src2),
1049 "test{b} {$src2, $src1|$src1, $src2}">;
1050 def TEST16mr : I<0x85, MRMDestMem, (ops i16mem:$src1, R16:$src2),
1051 "test{w} {$src2, $src1|$src1, $src2}">, OpSize;
1052 def TEST32mr : I<0x85, MRMDestMem, (ops i32mem:$src1, R32:$src2),
1053 "test{l} {$src2, $src1|$src1, $src2}">;
1054 def TEST8rm : I<0x84, MRMSrcMem, (ops R8 :$src1, i8mem :$src2),
1055 "test{b} {$src2, $src1|$src1, $src2}">;
1056 def TEST16rm : I<0x85, MRMSrcMem, (ops R16:$src1, i16mem:$src2),
1057 "test{w} {$src2, $src1|$src1, $src2}">, OpSize;
1058 def TEST32rm : I<0x85, MRMSrcMem, (ops R32:$src1, i32mem:$src2),
1059 "test{l} {$src2, $src1|$src1, $src2}">;
1061 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = R8 & imm8
1062 (ops R8:$src1, i8imm:$src2),
1063 "test{b} {$src2, $src1|$src1, $src2}">;
1064 def TEST16ri : Ii16<0xF7, MRM0r, // flags = R16 & imm16
1065 (ops R16:$src1, i16imm:$src2),
1066 "test{w} {$src2, $src1|$src1, $src2}">, OpSize;
1067 def TEST32ri : Ii32<0xF7, MRM0r, // flags = R32 & imm32
1068 (ops R32:$src1, i32imm:$src2),
1069 "test{l} {$src2, $src1|$src1, $src2}">;
1070 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
1071 (ops i32mem:$src1, i8imm:$src2),
1072 "test{b} {$src2, $src1|$src1, $src2}">;
1073 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
1074 (ops i16mem:$src1, i16imm:$src2),
1075 "test{w} {$src2, $src1|$src1, $src2}">, OpSize;
1076 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
1077 (ops i32mem:$src1, i32imm:$src2),
1078 "test{l} {$src2, $src1|$src1, $src2}">;
1082 // Condition code ops, incl. set if equal/not equal/...
1083 def SAHF : I<0x9E, RawFrm, (ops), "sahf">, Imp<[AH],[]>; // flags = AH
1084 def LAHF : I<0x9F, RawFrm, (ops), "lahf">, Imp<[],[AH]>; // AH = flags
1086 def SETBr : I<0x92, MRM0r,
1087 (ops R8 :$dst), "setb $dst">, TB; // R8 = < unsign
1088 def SETBm : I<0x92, MRM0m,
1089 (ops i8mem:$dst), "setb $dst">, TB; // [mem8] = < unsign
1090 def SETAEr : I<0x93, MRM0r,
1091 (ops R8 :$dst), "setae $dst">, TB; // R8 = >= unsign
1092 def SETAEm : I<0x93, MRM0m,
1093 (ops i8mem:$dst), "setae $dst">, TB; // [mem8] = >= unsign
1094 def SETEr : I<0x94, MRM0r,
1095 (ops R8 :$dst), "sete $dst">, TB; // R8 = ==
1096 def SETEm : I<0x94, MRM0m,
1097 (ops i8mem:$dst), "sete $dst">, TB; // [mem8] = ==
1098 def SETNEr : I<0x95, MRM0r,
1099 (ops R8 :$dst), "setne $dst">, TB; // R8 = !=
1100 def SETNEm : I<0x95, MRM0m,
1101 (ops i8mem:$dst), "setne $dst">, TB; // [mem8] = !=
1102 def SETBEr : I<0x96, MRM0r,
1103 (ops R8 :$dst), "setbe $dst">, TB; // R8 = <= unsign
1104 def SETBEm : I<0x96, MRM0m,
1105 (ops i8mem:$dst), "setbe $dst">, TB; // [mem8] = <= unsign
1106 def SETAr : I<0x97, MRM0r,
1107 (ops R8 :$dst), "seta $dst">, TB; // R8 = > signed
1108 def SETAm : I<0x97, MRM0m,
1109 (ops i8mem:$dst), "seta $dst">, TB; // [mem8] = > signed
1110 def SETSr : I<0x98, MRM0r,
1111 (ops R8 :$dst), "sets $dst">, TB; // R8 = <sign bit>
1112 def SETSm : I<0x98, MRM0m,
1113 (ops i8mem:$dst), "sets $dst">, TB; // [mem8] = <sign bit>
1114 def SETNSr : I<0x99, MRM0r,
1115 (ops R8 :$dst), "setns $dst">, TB; // R8 = !<sign bit>
1116 def SETNSm : I<0x99, MRM0m,
1117 (ops i8mem:$dst), "setns $dst">, TB; // [mem8] = !<sign bit>
1118 def SETPr : I<0x9A, MRM0r,
1119 (ops R8 :$dst), "setp $dst">, TB; // R8 = parity
1120 def SETPm : I<0x9A, MRM0m,
1121 (ops i8mem:$dst), "setp $dst">, TB; // [mem8] = parity
1122 def SETLr : I<0x9C, MRM0r,
1123 (ops R8 :$dst), "setl $dst">, TB; // R8 = < signed
1124 def SETLm : I<0x9C, MRM0m,
1125 (ops i8mem:$dst), "setl $dst">, TB; // [mem8] = < signed
1126 def SETGEr : I<0x9D, MRM0r,
1127 (ops R8 :$dst), "setge $dst">, TB; // R8 = >= signed
1128 def SETGEm : I<0x9D, MRM0m,
1129 (ops i8mem:$dst), "setge $dst">, TB; // [mem8] = >= signed
1130 def SETLEr : I<0x9E, MRM0r,
1131 (ops R8 :$dst), "setle $dst">, TB; // R8 = <= signed
1132 def SETLEm : I<0x9E, MRM0m,
1133 (ops i8mem:$dst), "setle $dst">, TB; // [mem8] = <= signed
1134 def SETGr : I<0x9F, MRM0r,
1135 (ops R8 :$dst), "setg $dst">, TB; // R8 = < signed
1136 def SETGm : I<0x9F, MRM0m,
1137 (ops i8mem:$dst), "setg $dst">, TB; // [mem8] = < signed
1139 // Integer comparisons
1140 def CMP8rr : I<0x38, MRMDestReg,
1141 (ops R8 :$src1, R8 :$src2),
1142 "cmp{b} {$src2, $src1|$src1, $src2}">;
1143 def CMP16rr : I<0x39, MRMDestReg,
1144 (ops R16:$src1, R16:$src2),
1145 "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize;
1146 def CMP32rr : I<0x39, MRMDestReg,
1147 (ops R32:$src1, R32:$src2),
1148 "cmp{l} {$src2, $src1|$src1, $src2}">;
1149 def CMP8mr : I<0x38, MRMDestMem,
1150 (ops i8mem :$src1, R8 :$src2),
1151 "cmp{b} {$src2, $src1|$src1, $src2}">;
1152 def CMP16mr : I<0x39, MRMDestMem,
1153 (ops i16mem:$src1, R16:$src2),
1154 "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize;
1155 def CMP32mr : I<0x39, MRMDestMem,
1156 (ops i32mem:$src1, R32:$src2),
1157 "cmp{l} {$src2, $src1|$src1, $src2}">;
1158 def CMP8rm : I<0x3A, MRMSrcMem,
1159 (ops R8 :$src1, i8mem :$src2),
1160 "cmp{b} {$src2, $src1|$src1, $src2}">;
1161 def CMP16rm : I<0x3B, MRMSrcMem,
1162 (ops R16:$src1, i16mem:$src2),
1163 "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize;
1164 def CMP32rm : I<0x3B, MRMSrcMem,
1165 (ops R32:$src1, i32mem:$src2),
1166 "cmp{l} {$src2, $src1|$src1, $src2}">;
1167 def CMP8ri : Ii8<0x80, MRM7r,
1168 (ops R16:$src1, i8imm:$src2),
1169 "cmp{b} {$src2, $src1|$src1, $src2}">;
1170 def CMP16ri : Ii16<0x81, MRM7r,
1171 (ops R16:$src1, i16imm:$src2),
1172 "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize;
1173 def CMP32ri : Ii32<0x81, MRM7r,
1174 (ops R32:$src1, i32imm:$src2),
1175 "cmp{l} {$src2, $src1|$src1, $src2}">;
1176 def CMP8mi : Ii8 <0x80, MRM7m,
1177 (ops i8mem :$src1, i8imm :$src2),
1178 "cmp{b} {$src2, $src1|$src1, $src2}">;
1179 def CMP16mi : Ii16<0x81, MRM7m,
1180 (ops i16mem:$src1, i16imm:$src2),
1181 "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize;
1182 def CMP32mi : Ii32<0x81, MRM7m,
1183 (ops i32mem:$src1, i32imm:$src2),
1184 "cmp{l} {$src2, $src1|$src1, $src2}">;
1186 // Sign/Zero extenders
1187 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops R16:$dst, R8 :$src),
1188 "movs{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize;
1189 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops R16:$dst, i8mem :$src),
1190 "movs{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize;
1191 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops R32:$dst, R8 :$src),
1192 "movs{bl|x} {$src, $dst|$dst, $src}">, TB;
1193 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops R32:$dst, i8mem :$src),
1194 "movs{bl|x} {$src, $dst|$dst, $src}">, TB;
1195 def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops R32:$dst, R16:$src),
1196 "movs{wl|x} {$src, $dst|$dst, $src}">, TB;
1197 def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops R32:$dst, i16mem:$src),
1198 "movs{wl|x} {$src, $dst|$dst, $src}">, TB;
1200 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops R16:$dst, R8 :$src),
1201 "movz{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize;
1202 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops R16:$dst, i8mem :$src),
1203 "movz{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize;
1204 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops R32:$dst, R8 :$src),
1205 "movz{bl|x} {$src, $dst|$dst, $src}">, TB;
1206 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops R32:$dst, i8mem :$src),
1207 "movz{bl|x} {$src, $dst|$dst, $src}">, TB;
1208 def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops R32:$dst, R16:$src),
1209 "movz{wl|x} {$src, $dst|$dst, $src}">, TB;
1210 def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops R32:$dst, i16mem:$src),
1211 "movz{wl|x} {$src, $dst|$dst, $src}">, TB;
1214 //===----------------------------------------------------------------------===//
1215 // Floating point support
1216 //===----------------------------------------------------------------------===//
1218 // FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP'
1220 // Floating point instruction template
1221 class FPI<bits<8> o, Format F, FPFormat fp, dag ops, string asm>
1222 : X86Inst<o, F, NoImm, ops, asm> {
1223 let FPForm = fp; let FPFormBits = FPForm.Value;
1226 // Pseudo instructions for floating point. We use these pseudo instructions
1227 // because they can be expanded by the fp spackifier into one of many different
1228 // forms of instructions for doing these operations. Until the stackifier runs,
1229 // we prefer to be abstract.
1230 def FpMOV : FPI<0, Pseudo, SpecialFP,
1231 (ops RFP, RFP), "">; // f1 = fmov f2
1232 def FpADD : FPI<0, Pseudo, TwoArgFP ,
1233 (ops RFP, RFP, RFP), "">; // f1 = fadd f2, f3
1234 def FpSUB : FPI<0, Pseudo, TwoArgFP ,
1235 (ops RFP, RFP, RFP), "">; // f1 = fsub f2, f3
1236 def FpMUL : FPI<0, Pseudo, TwoArgFP ,
1237 (ops RFP, RFP, RFP), "">; // f1 = fmul f2, f3
1238 def FpDIV : FPI<0, Pseudo, TwoArgFP ,
1239 (ops RFP, RFP, RFP), "">; // f1 = fdiv f2, f3
1241 def FpGETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP), "">,
1242 Imp<[ST0], []>; // FPR = ST(0)
1244 def FpSETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP), "">,
1245 Imp<[], [ST0]>; // ST(0) = FPR
1247 // FADD reg, mem: Before stackification, these are represented by:
1248 // R1 = FADD* R2, [mem]
1249 def FADD32m : FPI<0xD8, MRM0m, OneArgFPRW, // ST(0) = ST(0) + [mem32real]
1250 (ops f32mem:$src), "fadd{s} $src">;
1251 def FADD64m : FPI<0xDC, MRM0m, OneArgFPRW, // ST(0) = ST(0) + [mem64real]
1252 (ops f64mem:$src), "fadd{l} $src">;
1253 //def FIADD16m : FPI<0xDE, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem16int]
1254 //def FIADD32m : FPI<0xDA, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem32int]
1256 // FMUL reg, mem: Before stackification, these are represented by:
1257 // R1 = FMUL* R2, [mem]
1258 def FMUL32m : FPI<0xD8, MRM1m, OneArgFPRW, // ST(0) = ST(0) * [mem32real]
1259 (ops f32mem:$src), "fmul{s} $src">;
1260 def FMUL64m : FPI<0xDC, MRM1m, OneArgFPRW, // ST(0) = ST(0) * [mem64real]
1261 (ops f64mem:$src), "fmul{l} $src">;
1262 // ST(0) = ST(0) * [mem16int]
1263 //def FIMUL16m : FPI16m<"fimul", 0xDE, MRM1m, OneArgFPRW>;
1264 // ST(0) = ST(0) * [mem32int]
1265 //def FIMUL32m : FPI32m<"fimul", 0xDA, MRM1m, OneArgFPRW>;
1267 // FSUB reg, mem: Before stackification, these are represented by:
1268 // R1 = FSUB* R2, [mem]
1269 def FSUB32m : FPI<0xD8, MRM4m, OneArgFPRW, // ST(0) = ST(0) - [mem32real]
1270 (ops f32mem:$src), "fsub{s} $src">;
1271 def FSUB64m : FPI<0xDC, MRM4m, OneArgFPRW, // ST(0) = ST(0) - [mem64real]
1272 (ops f64mem:$src), "fsub{l} $src">;
1273 // ST(0) = ST(0) - [mem16int]
1274 //def FISUB16m : FPI16m<"fisub", 0xDE, MRM4m, OneArgFPRW>;
1275 // ST(0) = ST(0) - [mem32int]
1276 //def FISUB32m : FPI32m<"fisub", 0xDA, MRM4m, OneArgFPRW>;
1278 // FSUBR reg, mem: Before stackification, these are represented by:
1279 // R1 = FSUBR* R2, [mem]
1281 // Note that the order of operands does not reflect the operation being
1283 def FSUBR32m : FPI<0xD8, MRM5m, OneArgFPRW, // ST(0) = [mem32real] - ST(0)
1284 (ops f32mem:$src), "fsubr{s} $src">;
1285 def FSUBR64m : FPI<0xDC, MRM5m, OneArgFPRW, // ST(0) = [mem64real] - ST(0)
1286 (ops f64mem:$src), "fsubr{l} $src">;
1287 // ST(0) = [mem16int] - ST(0)
1288 //def FISUBR16m : FPI16m<"fisubr", 0xDE, MRM5m, OneArgFPRW>;
1289 // ST(0) = [mem32int] - ST(0)
1290 //def FISUBR32m : FPI32m<"fisubr", 0xDA, MRM5m, OneArgFPRW>;
1292 // FDIV reg, mem: Before stackification, these are represented by:
1293 // R1 = FDIV* R2, [mem]
1294 def FDIV32m : FPI<0xD8, MRM6m, OneArgFPRW, // ST(0) = ST(0) / [mem32real]
1295 (ops f32mem:$src), "fdiv{s} $src">;
1296 def FDIV64m : FPI<0xDC, MRM6m, OneArgFPRW, // ST(0) = ST(0) / [mem64real]
1297 (ops f64mem:$src), "fdiv{l} $src">;
1298 // ST(0) = ST(0) / [mem16int]
1299 //def FIDIV16m : FPI16m<"fidiv", 0xDE, MRM6m, OneArgFPRW>;
1300 // ST(0) = ST(0) / [mem32int]
1301 //def FIDIV32m : FPI32m<"fidiv", 0xDA, MRM6m, OneArgFPRW>;
1303 // FDIVR reg, mem: Before stackification, these are represented by:
1304 // R1 = FDIVR* R2, [mem]
1305 // Note that the order of operands does not reflect the operation being
1307 def FDIVR32m : FPI<0xD8, MRM7m, OneArgFPRW, // ST(0) = [mem32real] / ST(0)
1308 (ops f32mem:$src), "fdivr{s} $src">;
1309 def FDIVR64m : FPI<0xDC, MRM7m, OneArgFPRW, // ST(0) = [mem64real] / ST(0)
1310 (ops f64mem:$src), "fdivr{l} $src">;
1311 // ST(0) = [mem16int] / ST(0)
1312 //def FIDIVR16m : FPI16m<"fidivr", 0xDE, MRM7m, OneArgFPRW>;
1313 // ST(0) = [mem32int] / ST(0)
1314 //def FIDIVR32m : FPI32m<"fidivr", 0xDA, MRM7m, OneArgFPRW>;
1317 // Floating point cmovs...
1318 let isTwoAddress = 1, Uses = [ST0], Defs = [ST0] in {
1319 def FCMOVB : FPI<0xC0, AddRegFrm, CondMovFP,
1320 (ops RST:$op), "fcmovb {$op, %ST(0)|%ST(0), $op}">, DA;
1321 def FCMOVBE : FPI<0xD0, AddRegFrm, CondMovFP,
1322 (ops RST:$op), "fcmovbe {$op, %ST(0)|%ST(0), $op}">, DA;
1323 def FCMOVE : FPI<0xC8, AddRegFrm, CondMovFP,
1324 (ops RST:$op), "fcmove {$op, %ST(0)|%ST(0), $op}">, DA;
1325 def FCMOVAE : FPI<0xC0, AddRegFrm, CondMovFP,
1326 (ops RST:$op), "fcmovae {$op, %ST(0)|%ST(0), $op}">, DB;
1327 def FCMOVA : FPI<0xD0, AddRegFrm, CondMovFP,
1328 (ops RST:$op), "fcmova {$op, %ST(0)|%ST(0), $op}">, DB;
1329 def FCMOVNE : FPI<0xC8, AddRegFrm, CondMovFP,
1330 (ops RST:$op), "fcmovne {$op, %ST(0)|%ST(0), $op}">, DB;
1333 // Floating point loads & stores...
1334 def FLDrr : FPI<0xC0, AddRegFrm, NotFP, (ops RST:$src), "fld $src">, D9;
1335 def FLD32m : FPI<0xD9, MRM0m, ZeroArgFP, (ops f32mem:$src), "fld{s} $src">;
1336 def FLD64m : FPI<0xDD, MRM0m, ZeroArgFP, (ops f64mem:$src), "fld{l} $src">;
1337 def FLD80m : FPI<0xDB, MRM5m, ZeroArgFP, (ops f80mem:$src), "fld{t} $src">;
1338 def FILD16m : FPI<0xDF, MRM0m, ZeroArgFP, (ops i16mem:$src), "fild{s} $src">;
1339 def FILD32m : FPI<0xDB, MRM0m, ZeroArgFP, (ops i32mem:$src), "fild{l} $src">;
1340 def FILD64m : FPI<0xDF, MRM5m, ZeroArgFP, (ops i64mem:$src), "fild{ll} $src">;
1342 def FSTrr : FPI<0xD0, AddRegFrm, NotFP, (ops RST:$op), "fst $op">, DD;
1343 def FSTPrr : FPI<0xD8, AddRegFrm, NotFP, (ops RST:$op), "fstp $op">, DD;
1344 def FST32m : FPI<0xD9, MRM2m, OneArgFP, (ops f32mem:$op), "fst{s} $op">;
1345 def FST64m : FPI<0xDD, MRM2m, OneArgFP, (ops f64mem:$op), "fst{l} $op">;
1346 def FSTP32m : FPI<0xD9, MRM3m, OneArgFP, (ops f32mem:$op), "fstp{s} $op">;
1347 def FSTP64m : FPI<0xDD, MRM3m, OneArgFP, (ops f64mem:$op), "fstp{l} $op">;
1348 def FSTP80m : FPI<0xDB, MRM7m, OneArgFP, (ops f80mem:$op), "fstp{t} $op">;
1350 def FIST16m : FPI<0xDF, MRM2m , OneArgFP, (ops i16mem:$op), "fist{s} $op">;
1351 def FIST32m : FPI<0xDB, MRM2m , OneArgFP, (ops i32mem:$op), "fist{l} $op">;
1352 def FISTP16m : FPI<0xDF, MRM3m , NotFP , (ops i16mem:$op), "fistp{s} $op">;
1353 def FISTP32m : FPI<0xDB, MRM3m , NotFP , (ops i32mem:$op), "fistp{l} $op">;
1354 def FISTP64m : FPI<0xDF, MRM7m , OneArgFP, (ops i64mem:$op), "fistp{ll} $op">;
1356 def FXCH : FPI<0xC8, AddRegFrm, NotFP,
1357 (ops RST:$op), "fxch $op">, D9; // fxch ST(i), ST(0)
1359 // Floating point constant loads...
1360 def FLD0 : FPI<0xEE, RawFrm, ZeroArgFP, (ops), "fldz">, D9;
1361 def FLD1 : FPI<0xE8, RawFrm, ZeroArgFP, (ops), "fld1">, D9;
1364 // Unary operations...
1365 def FCHS : FPI<0xE0, RawFrm, OneArgFPRW, (ops), "fchs">, D9; // f1 = fchs f2
1366 def FTST : FPI<0xE4, RawFrm, OneArgFP, (ops), "ftst">, D9; // ftst ST(0)
1368 // Binary arithmetic operations...
1369 class FPST0rInst<bits<8> o, dag ops, string asm>
1370 : I<o, AddRegFrm, ops, asm>, D8 {
1371 list<Register> Uses = [ST0];
1372 list<Register> Defs = [ST0];
1374 class FPrST0Inst<bits<8> o, dag ops, string asm>
1375 : I<o, AddRegFrm, ops, asm>, DC {
1376 list<Register> Uses = [ST0];
1378 class FPrST0PInst<bits<8> o, dag ops, string asm>
1379 : I<o, AddRegFrm, ops, asm>, DE {
1380 list<Register> Uses = [ST0];
1383 def FADDST0r : FPST0rInst <0xC0, (ops RST:$op),
1385 def FADDrST0 : FPrST0Inst <0xC0, (ops RST:$op),
1386 "fadd {%ST(0), $op|$op, %ST(0)}">;
1387 def FADDPrST0 : FPrST0PInst<0xC0, (ops RST:$op),
1390 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
1391 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
1392 // we have to put some 'r's in and take them out of wierd places.
1393 def FSUBRST0r : FPST0rInst <0xE8, (ops RST:$op),
1395 def FSUBrST0 : FPrST0Inst <0xE8, (ops RST:$op),
1396 "fsub{r} {%ST(0), $op|$op, %ST(0)}">;
1397 def FSUBPrST0 : FPrST0PInst<0xE8, (ops RST:$op),
1400 def FSUBST0r : FPST0rInst <0xE0, (ops RST:$op),
1402 def FSUBRrST0 : FPrST0Inst <0xE0, (ops RST:$op),
1403 "fsub{|r} {%ST(0), $op|$op, %ST(0)}">;
1404 def FSUBRPrST0 : FPrST0PInst<0xE0, (ops RST:$op),
1407 def FMULST0r : FPST0rInst <0xC8, (ops RST:$op),
1409 def FMULrST0 : FPrST0Inst <0xC8, (ops RST:$op),
1410 "fmul {%ST(0), $op|$op, %ST(0)}">;
1411 def FMULPrST0 : FPrST0PInst<0xC8, (ops RST:$op),
1414 def FDIVRST0r : FPST0rInst <0xF8, (ops RST:$op),
1416 def FDIVrST0 : FPrST0Inst <0xF8, (ops RST:$op),
1417 "fdiv{r} {%ST(0), $op|$op, %ST(0)}">;
1418 def FDIVPrST0 : FPrST0PInst<0xF8, (ops RST:$op),
1421 def FDIVST0r : FPST0rInst <0xF0, (ops RST:$op), // ST(0) = ST(0) / ST(i)
1423 def FDIVRrST0 : FPrST0Inst <0xF0, (ops RST:$op), // ST(i) = ST(0) / ST(i)
1424 "fdiv{|r} {%ST(0), $op|$op, %ST(0)}">;
1425 def FDIVRPrST0 : FPrST0PInst<0xF0, (ops RST:$op), // ST(i) = ST(0) / ST(i), pop
1428 // Floating point compares
1429 def FUCOMr : FPI<0xE0, AddRegFrm, CompareFP, // FPSW = cmp ST(0) with ST(i)
1431 "fucom $reg">, DD, Imp<[ST0],[]>;
1432 def FUCOMPr : I<0xE8, AddRegFrm,
1433 (ops RST:$reg), // FPSW = cmp ST(0) with ST(i), pop
1434 "fucomp $reg">, DD, Imp<[ST0],[]>;
1435 def FUCOMPPr : I<0xE9, RawFrm,
1436 (ops), // cmp ST(0) with ST(1), pop, pop
1437 "fucompp">, DA, Imp<[ST0],[]>;
1439 def FUCOMIr : FPI<0xE8, AddRegFrm, CompareFP, // CC = cmp ST(0) with ST(i)
1441 "fucomi {$reg, %ST(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
1442 def FUCOMIPr : I<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
1444 "fucomip {$reg, %ST(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>;
1447 // Floating point flag ops
1448 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
1449 (ops), "fnstsw">, DF, Imp<[],[AX]>;
1451 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
1452 (ops i16mem:$dst), "fnstcw $dst">;
1453 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
1454 (ops i16mem:$dst), "fldcw $dst">;