1 //===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86INSTRUCTIONINFO_H
15 #define X86INSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "llvm/ADT/DenseMap.h"
23 class X86RegisterInfo;
24 class X86TargetMachine;
27 // X86 specific condition code. These correspond to X86_*_COND in
28 // X86InstrInfo.td. They must be kept in synch.
47 // Artificial condition codes. These are used by AnalyzeBranch
48 // to indicate a block terminated with two conditional branches to
49 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
50 // which can't be represented on x86 with a single condition. These
51 // are never used in MachineInstrs.
58 // Turn condition code into conditional branch opcode.
59 unsigned GetCondBranchFromCond(CondCode CC);
61 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
62 /// e.g. turning COND_E to COND_NE.
63 CondCode GetOppositeBranchCondition(X86::CondCode CC);
67 /// X86II - This namespace holds all of the target specific flags that
68 /// instruction info tracks.
71 /// Target Operand Flag enum.
73 //===------------------------------------------------------------------===//
74 // X86 Specific MachineOperand flags.
78 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
80 /// SYMBOL_LABEL + [. - PICBASELABEL]
81 MO_GOT_ABSOLUTE_ADDRESS,
83 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
84 /// immediate should get the value of the symbol minus the PIC base label:
85 /// SYMBOL_LABEL - PICBASELABEL
88 /// MO_GOT - On a symbol operand this indicates that the immediate is the
89 /// offset to the GOT entry for the symbol name from the base of the GOT.
91 /// See the X86-64 ELF ABI supplement for more details.
95 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
96 /// the offset to the location of the symbol name from the base of the GOT.
98 /// See the X86-64 ELF ABI supplement for more details.
99 /// SYMBOL_LABEL @GOTOFF
102 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
103 /// offset to the GOT entry for the symbol name from the current code
106 /// See the X86-64 ELF ABI supplement for more details.
107 /// SYMBOL_LABEL @GOTPCREL
110 /// MO_PLT - On a symbol operand this indicates that the immediate is
111 /// offset to the PLT entry of symbol name from the current code location.
113 /// See the X86-64 ELF ABI supplement for more details.
114 /// SYMBOL_LABEL @PLT
117 /// MO_TLSGD - On a symbol operand this indicates that the immediate is
120 /// See 'ELF Handling for Thread-Local Storage' for more details.
121 /// SYMBOL_LABEL @TLSGD
124 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
127 /// See 'ELF Handling for Thread-Local Storage' for more details.
128 /// SYMBOL_LABEL @GOTTPOFF
131 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
134 /// See 'ELF Handling for Thread-Local Storage' for more details.
135 /// SYMBOL_LABEL @INDNTPOFF
138 /// MO_TPOFF - On a symbol operand this indicates that the immediate is
141 /// See 'ELF Handling for Thread-Local Storage' for more details.
142 /// SYMBOL_LABEL @TPOFF
145 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
148 /// See 'ELF Handling for Thread-Local Storage' for more details.
149 /// SYMBOL_LABEL @NTPOFF
152 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
153 /// reference is actually to the "__imp_FOO" symbol. This is used for
154 /// dllimport linkage on windows.
157 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the
158 /// reference is actually to the "FOO$stub" symbol. This is used for calls
159 /// and jumps to external functions on Tiger and before.
162 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
163 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
164 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
167 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
168 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
169 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
170 MO_DARWIN_NONLAZY_PIC_BASE,
172 /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this
173 /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE",
174 /// which is a PIC-base-relative reference to a hidden dyld lazy pointer
176 MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE,
178 /// MO_TLVP - On a symbol operand this indicates that the immediate is
181 /// This is the TLS offset for the Darwin TLS mechanism.
184 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
185 /// is some TLS offset from the picbase.
187 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
192 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
193 /// a reference to a stub for a global, not the global itself.
194 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
195 switch (TargetFlag) {
196 case X86II::MO_DLLIMPORT: // dllimport stub.
197 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
198 case X86II::MO_GOT: // normal GOT reference.
199 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
200 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
201 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
208 /// isGlobalRelativeToPICBase - Return true if the specified global value
209 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
210 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
211 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
212 switch (TargetFlag) {
213 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
214 case X86II::MO_GOT: // isPICStyleGOT: other global.
215 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
216 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
217 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global.
218 case X86II::MO_TLVP: // ??? Pretty sure..
225 /// X86II - This namespace holds all of the target specific flags that
226 /// instruction info tracks.
230 //===------------------------------------------------------------------===//
231 // Instruction encodings. These are the standard/most common forms for X86
235 // PseudoFrm - This represents an instruction that is a pseudo instruction
236 // or one that has not been implemented yet. It is illegal to code generate
237 // it, but tolerated for intermediate implementation stages.
240 /// Raw - This form is for instructions that don't have any operands, so
241 /// they are just a fixed opcode value, like 'leave'.
244 /// AddRegFrm - This form is used for instructions like 'push r32' that have
245 /// their one register operand added to their opcode.
248 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
249 /// to specify a destination, which in this case is a register.
253 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
254 /// to specify a destination, which in this case is memory.
258 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
259 /// to specify a source, which in this case is a register.
263 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
264 /// to specify a source, which in this case is memory.
268 /// MRM[0-7][rm] - These forms are used to represent instructions that use
269 /// a Mod/RM byte, and use the middle field to hold extended opcode
270 /// information. In the intel manual these are represented as /0, /1, ...
273 // First, instructions that operate on a register r/m operand...
274 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3
275 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7
277 // Next, instructions that operate on a memory r/m operand...
278 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3
279 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
281 // MRMInitReg - This form is used for instructions whose source and
282 // destinations are the same register.
285 //// MRM_C1 - A mod/rm byte of exactly 0xC1.
299 //===------------------------------------------------------------------===//
302 // OpSize - Set if this instruction requires an operand size prefix (0x66),
303 // which most often indicates that the instruction operates on 16 bit data
304 // instead of 32 bit data.
307 // AsSize - Set if this instruction requires an operand size prefix (0x67),
308 // which most often indicates that the instruction address 16 bit address
309 // instead of 32 bit address (or 32 bit address in 64 bit mode).
312 //===------------------------------------------------------------------===//
313 // Op0Mask - There are several prefix bytes that are used to form two byte
314 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
315 // used to obtain the setting of this field. If no bits in this field is
316 // set, there is no prefix byte for obtaining a multibyte opcode.
319 Op0Mask = 0xF << Op0Shift,
321 // TB - TwoByte - Set if this instruction has a two byte opcode, which
322 // starts with a 0x0F byte before the real opcode.
325 // REP - The 0xF3 prefix byte indicating repetition of the following
329 // D8-DF - These escape opcodes are used by the floating point unit. These
330 // values must remain sequential.
331 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift,
332 DA = 5 << Op0Shift, DB = 6 << Op0Shift,
333 DC = 7 << Op0Shift, DD = 8 << Op0Shift,
334 DE = 9 << Op0Shift, DF = 10 << Op0Shift,
336 // XS, XD - These prefix codes are for single and double precision scalar
337 // floating point operations performed in the SSE registers.
338 XD = 11 << Op0Shift, XS = 12 << Op0Shift,
340 // T8, TA - Prefix after the 0x0F prefix.
341 T8 = 13 << Op0Shift, TA = 14 << Op0Shift,
343 // TF - Prefix before and after 0x0F
346 //===------------------------------------------------------------------===//
347 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
348 // They are used to specify GPRs and SSE registers, 64-bit operand size,
349 // etc. We only cares about REX.W and REX.R bits and only the former is
350 // statically determined.
353 REX_W = 1 << REXShift,
355 //===------------------------------------------------------------------===//
356 // This three-bit field describes the size of an immediate operand. Zero is
357 // unused so that we can tell if we forgot to set a value.
359 ImmMask = 7 << ImmShift,
360 Imm8 = 1 << ImmShift,
361 Imm8PCRel = 2 << ImmShift,
362 Imm16 = 3 << ImmShift,
363 Imm16PCRel = 4 << ImmShift,
364 Imm32 = 5 << ImmShift,
365 Imm32PCRel = 6 << ImmShift,
366 Imm64 = 7 << ImmShift,
368 //===------------------------------------------------------------------===//
369 // FP Instruction Classification... Zero is non-fp instruction.
371 // FPTypeMask - Mask for all of the FP types...
373 FPTypeMask = 7 << FPTypeShift,
375 // NotFP - The default, set for instructions that do not use FP registers.
376 NotFP = 0 << FPTypeShift,
378 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
379 ZeroArgFP = 1 << FPTypeShift,
381 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
382 OneArgFP = 2 << FPTypeShift,
384 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
385 // result back to ST(0). For example, fcos, fsqrt, etc.
387 OneArgFPRW = 3 << FPTypeShift,
389 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
390 // explicit argument, storing the result to either ST(0) or the implicit
391 // argument. For example: fadd, fsub, fmul, etc...
392 TwoArgFP = 4 << FPTypeShift,
394 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
395 // explicit argument, but have no destination. Example: fucom, fucomi, ...
396 CompareFP = 5 << FPTypeShift,
398 // CondMovFP - "2 operand" floating point conditional move instructions.
399 CondMovFP = 6 << FPTypeShift,
401 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
402 SpecialFP = 7 << FPTypeShift,
406 LOCK = 1 << LOCKShift,
408 // Segment override prefixes. Currently we just need ability to address
409 // stuff in gs and fs segments.
411 SegOvrMask = 3 << SegOvrShift,
412 FS = 1 << SegOvrShift,
413 GS = 2 << SegOvrShift,
415 // Execution domain for SSE instructions in bits 22, 23.
416 // 0 in bits 22-23 means normal, non-SSE instruction.
420 OpcodeMask = 0xFF << OpcodeShift
424 // FIXME: The enum opcode space is over and more bits are needed. Anywhere
425 // those enums below are used, TSFlags must be shifted right by 32 first.
427 //===------------------------------------------------------------------===//
428 // VEX - A prefix used by AVX instructions
431 // VEX_W is has a opcode specific functionality, but is used in the same
432 // way as REX_W is for regular SSE instructions.
435 // VEX_4V is used to specify an additional AVX/SSE register. Several 2
436 // address instructions in SSE are represented as 3 address ones in AVX
437 // and the additional register is encoded in VEX_VVVV prefix.
440 // VEX_I8IMM specifies that the last register used in a AVX instruction,
441 // must be encoded in the i8 immediate field. This usually happens in
442 // instructions with 4 operands.
446 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
447 // specified machine instruction.
449 static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) {
450 return TSFlags >> X86II::OpcodeShift;
453 static inline bool hasImm(uint64_t TSFlags) {
454 return (TSFlags & X86II::ImmMask) != 0;
457 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
458 /// of the specified instruction.
459 static inline unsigned getSizeOfImm(uint64_t TSFlags) {
460 switch (TSFlags & X86II::ImmMask) {
461 default: assert(0 && "Unknown immediate size");
463 case X86II::Imm8PCRel: return 1;
465 case X86II::Imm16PCRel: return 2;
467 case X86II::Imm32PCRel: return 4;
468 case X86II::Imm64: return 8;
472 /// isImmPCRel - Return true if the immediate of the specified instruction's
473 /// TSFlags indicates that it is pc relative.
474 static inline unsigned isImmPCRel(uint64_t TSFlags) {
475 switch (TSFlags & X86II::ImmMask) {
476 default: assert(0 && "Unknown immediate size");
477 case X86II::Imm8PCRel:
478 case X86II::Imm16PCRel:
479 case X86II::Imm32PCRel:
489 /// getMemoryOperandNo - The function returns the MCInst operand # for the
490 /// first field of the memory operand. If the instruction doesn't have a
491 /// memory operand, this returns -1.
493 /// Note that this ignores tied operands. If there is a tied register which
494 /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only
495 /// counted as one operand.
497 static inline int getMemoryOperandNo(uint64_t TSFlags) {
498 switch (TSFlags & X86II::FormMask) {
499 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this form");
500 default: assert(0 && "Unknown FormMask value in getMemoryOperandNo!");
503 case X86II::AddRegFrm:
504 case X86II::MRMDestReg:
505 case X86II::MRMSrcReg:
507 case X86II::MRMDestMem:
509 case X86II::MRMSrcMem: {
510 bool HasVEX_4V = (TSFlags >> 32) & X86II::VEX_4V;
511 unsigned FirstMemOp = 1;
513 ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV).
515 // FIXME: Maybe lea should have its own form? This is a horrible hack.
516 //if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
517 // Opcode == X86::LEA16r || Opcode == X86::LEA32r)
520 case X86II::MRM0r: case X86II::MRM1r:
521 case X86II::MRM2r: case X86II::MRM3r:
522 case X86II::MRM4r: case X86II::MRM5r:
523 case X86II::MRM6r: case X86II::MRM7r:
525 case X86II::MRM0m: case X86II::MRM1m:
526 case X86II::MRM2m: case X86II::MRM3m:
527 case X86II::MRM4m: case X86II::MRM5m:
528 case X86II::MRM6m: case X86II::MRM7m:
545 // FIXME: Move into X86II namespace.
548 X86AddrNumOperands = 5
551 inline static bool isScale(const MachineOperand &MO) {
553 (MO.getImm() == 1 || MO.getImm() == 2 ||
554 MO.getImm() == 4 || MO.getImm() == 8);
557 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
558 if (MI->getOperand(Op).isFI()) return true;
559 return Op+4 <= MI->getNumOperands() &&
560 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
561 MI->getOperand(Op+2).isReg() &&
562 (MI->getOperand(Op+3).isImm() ||
563 MI->getOperand(Op+3).isGlobal() ||
564 MI->getOperand(Op+3).isCPI() ||
565 MI->getOperand(Op+3).isJTI());
568 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
569 if (MI->getOperand(Op).isFI()) return true;
570 return Op+5 <= MI->getNumOperands() &&
571 MI->getOperand(Op+4).isReg() &&
575 class X86InstrInfo : public TargetInstrInfoImpl {
576 X86TargetMachine &TM;
577 const X86RegisterInfo RI;
579 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
580 /// RegOp2MemOpTable2 - Load / store folding opcode maps.
582 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2Addr;
583 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable0;
584 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable1;
585 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2;
587 /// MemOp2RegOpTable - Load / store unfolding opcode map.
589 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable;
592 explicit X86InstrInfo(X86TargetMachine &tm);
594 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
595 /// such, whenever a client has an instance of instruction info, it should
596 /// always be able to get register info as well (through this method).
598 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
600 /// Return true if the instruction is a register to register move and return
601 /// the source and dest operands and their sub-register indices by reference.
602 virtual bool isMoveInstr(const MachineInstr &MI,
603 unsigned &SrcReg, unsigned &DstReg,
604 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
606 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
607 /// extension instruction. That is, it's like a copy where it's legal for the
608 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
609 /// true, then it's expected the pre-extension value is available as a subreg
610 /// of the result register. This also returns the sub-register index in
612 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
613 unsigned &SrcReg, unsigned &DstReg,
614 unsigned &SubIdx) const;
616 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
617 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
618 /// stack locations as well. This uses a heuristic so it isn't
619 /// reliable for correctness.
620 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
621 int &FrameIndex) const;
623 /// hasLoadFromStackSlot - If the specified machine instruction has
624 /// a load from a stack slot, return true along with the FrameIndex
625 /// of the loaded stack slot and the machine mem operand containing
626 /// the reference. If not, return false. Unlike
627 /// isLoadFromStackSlot, this returns true for any instructions that
628 /// loads from the stack. This is a hint only and may not catch all
630 bool hasLoadFromStackSlot(const MachineInstr *MI,
631 const MachineMemOperand *&MMO,
632 int &FrameIndex) const;
634 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
635 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
636 /// stack locations as well. This uses a heuristic so it isn't
637 /// reliable for correctness.
638 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
639 int &FrameIndex) const;
641 /// hasStoreToStackSlot - If the specified machine instruction has a
642 /// store to a stack slot, return true along with the FrameIndex of
643 /// the loaded stack slot and the machine mem operand containing the
644 /// reference. If not, return false. Unlike isStoreToStackSlot,
645 /// this returns true for any instructions that loads from the
646 /// stack. This is a hint only and may not catch all cases.
647 bool hasStoreToStackSlot(const MachineInstr *MI,
648 const MachineMemOperand *&MMO,
649 int &FrameIndex) const;
651 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
652 AliasAnalysis *AA) const;
653 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
654 unsigned DestReg, unsigned SubIdx,
655 const MachineInstr *Orig,
656 const TargetRegisterInfo &TRI) const;
658 /// convertToThreeAddress - This method must be implemented by targets that
659 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
660 /// may be able to convert a two-address instruction into a true
661 /// three-address instruction on demand. This allows the X86 target (for
662 /// example) to convert ADD and SHL instructions into LEA instructions if they
663 /// would require register copies due to two-addressness.
665 /// This method returns a null pointer if the transformation cannot be
666 /// performed, otherwise it returns the new instruction.
668 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
669 MachineBasicBlock::iterator &MBBI,
670 LiveVariables *LV) const;
672 /// commuteInstruction - We have a few instructions that must be hacked on to
675 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
678 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
679 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
680 MachineBasicBlock *&FBB,
681 SmallVectorImpl<MachineOperand> &Cond,
682 bool AllowModify) const;
683 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
684 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
685 MachineBasicBlock *FBB,
686 const SmallVectorImpl<MachineOperand> &Cond,
688 virtual bool copyRegToReg(MachineBasicBlock &MBB,
689 MachineBasicBlock::iterator MI,
690 unsigned DestReg, unsigned SrcReg,
691 const TargetRegisterClass *DestRC,
692 const TargetRegisterClass *SrcRC,
694 virtual void copyPhysReg(MachineBasicBlock &MBB,
695 MachineBasicBlock::iterator MI, DebugLoc DL,
696 unsigned DestReg, unsigned SrcReg,
698 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
699 MachineBasicBlock::iterator MI,
700 unsigned SrcReg, bool isKill, int FrameIndex,
701 const TargetRegisterClass *RC,
702 const TargetRegisterInfo *TRI) const;
704 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
705 SmallVectorImpl<MachineOperand> &Addr,
706 const TargetRegisterClass *RC,
707 MachineInstr::mmo_iterator MMOBegin,
708 MachineInstr::mmo_iterator MMOEnd,
709 SmallVectorImpl<MachineInstr*> &NewMIs) const;
711 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
712 MachineBasicBlock::iterator MI,
713 unsigned DestReg, int FrameIndex,
714 const TargetRegisterClass *RC,
715 const TargetRegisterInfo *TRI) const;
717 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
718 SmallVectorImpl<MachineOperand> &Addr,
719 const TargetRegisterClass *RC,
720 MachineInstr::mmo_iterator MMOBegin,
721 MachineInstr::mmo_iterator MMOEnd,
722 SmallVectorImpl<MachineInstr*> &NewMIs) const;
724 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
725 MachineBasicBlock::iterator MI,
726 const std::vector<CalleeSavedInfo> &CSI,
727 const TargetRegisterInfo *TRI) const;
729 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
730 MachineBasicBlock::iterator MI,
731 const std::vector<CalleeSavedInfo> &CSI,
732 const TargetRegisterInfo *TRI) const;
735 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
736 int FrameIx, uint64_t Offset,
740 /// foldMemoryOperand - If this target supports it, fold a load or store of
741 /// the specified stack slot into the specified machine instruction for the
742 /// specified operand(s). If this is possible, the target should perform the
743 /// folding and return true, otherwise it should return false. If it folds
744 /// the instruction, it is likely that the MachineInstruction the iterator
745 /// references has been changed.
746 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
748 const SmallVectorImpl<unsigned> &Ops,
749 int FrameIndex) const;
751 /// foldMemoryOperand - Same as the previous version except it allows folding
752 /// of any load and store from / to any address, not just from a specific
754 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
756 const SmallVectorImpl<unsigned> &Ops,
757 MachineInstr* LoadMI) const;
759 /// canFoldMemoryOperand - Returns true if the specified load / store is
760 /// folding is possible.
761 virtual bool canFoldMemoryOperand(const MachineInstr*,
762 const SmallVectorImpl<unsigned> &) const;
764 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
765 /// a store or a load and a store into two or more instruction. If this is
766 /// possible, returns true as well as the new instructions by reference.
767 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
768 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
769 SmallVectorImpl<MachineInstr*> &NewMIs) const;
771 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
772 SmallVectorImpl<SDNode*> &NewNodes) const;
774 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
775 /// instruction after load / store are unfolded from an instruction of the
776 /// specified opcode. It returns zero if the specified unfolding is not
777 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
778 /// index of the operand which will hold the register holding the loaded
780 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
781 bool UnfoldLoad, bool UnfoldStore,
782 unsigned *LoadRegIndex = 0) const;
784 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
785 /// to determine if two loads are loading from the same base address. It
786 /// should only return true if the base pointers are the same and the
787 /// only differences between the two addresses are the offset. It also returns
788 /// the offsets by reference.
789 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
790 int64_t &Offset1, int64_t &Offset2) const;
792 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
793 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
794 /// be scheduled togther. On some targets if two loads are loading from
795 /// addresses in the same cache line, it's better if they are scheduled
796 /// together. This function takes two integers that represent the load offsets
797 /// from the common base address. It returns true if it decides it's desirable
798 /// to schedule the two loads together. "NumLoads" is the number of loads that
799 /// have already been scheduled after Load1.
800 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
801 int64_t Offset1, int64_t Offset2,
802 unsigned NumLoads) const;
804 virtual void getNoopForMachoTarget(MCInst &NopInst) const;
807 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
809 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
810 /// instruction that defines the specified register class.
811 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
813 static bool isX86_64NonExtLowByteReg(unsigned reg) {
814 return (reg == X86::SPL || reg == X86::BPL ||
815 reg == X86::SIL || reg == X86::DIL);
818 static bool isX86_64ExtendedReg(const MachineOperand &MO) {
819 if (!MO.isReg()) return false;
820 return isX86_64ExtendedReg(MO.getReg());
822 static unsigned determineREX(const MachineInstr &MI);
824 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or
825 /// higher) register? e.g. r8, xmm8, xmm13, etc.
826 static bool isX86_64ExtendedReg(unsigned RegNo);
828 /// GetInstSize - Returns the size of the specified MachineInstr.
830 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
832 /// getGlobalBaseReg - Return a virtual register initialized with the
833 /// the global base register value. Output instructions required to
834 /// initialize the register in the function entry block, if necessary.
836 unsigned getGlobalBaseReg(MachineFunction *MF) const;
838 /// GetSSEDomain - Return the SSE execution domain of MI as the first element,
839 /// and a bitmask of possible arguments to SetSSEDomain ase the second.
840 std::pair<uint16_t, uint16_t> GetSSEDomain(const MachineInstr *MI) const;
842 /// SetSSEDomain - Set the SSEDomain of MI.
843 void SetSSEDomain(MachineInstr *MI, unsigned Domain) const;
846 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
847 MachineFunction::iterator &MFI,
848 MachineBasicBlock::iterator &MBBI,
849 LiveVariables *LV) const;
851 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
854 const SmallVectorImpl<MachineOperand> &MOs,
855 unsigned Size, unsigned Alignment) const;
857 /// isFrameOperand - Return true and the FrameIndex if the specified
858 /// operand and follow operands form a reference to the stack frame.
859 bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
860 int &FrameIndex) const;
863 } // End llvm namespace