1 //===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86INSTRUCTIONINFO_H
15 #define X86INSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "llvm/ADT/DenseMap.h"
23 class X86RegisterInfo;
24 class X86TargetMachine;
27 // Enums for memory operand decoding. Each memory operand is represented with
28 // a 5 operand sequence in the form:
29 // [BaseReg, ScaleAmt, IndexReg, Disp, Segment]
30 // These enums help decode this.
37 /// AddrSegmentReg - The operand # of the segment in the memory operand.
40 /// AddrNumOperands - Total number of operands in a memory reference.
45 // X86 specific condition code. These correspond to X86_*_COND in
46 // X86InstrInfo.td. They must be kept in synch.
65 // Artificial condition codes. These are used by AnalyzeBranch
66 // to indicate a block terminated with two conditional branches to
67 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
68 // which can't be represented on x86 with a single condition. These
69 // are never used in MachineInstrs.
76 // Turn condition code into conditional branch opcode.
77 unsigned GetCondBranchFromCond(CondCode CC);
79 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
80 /// e.g. turning COND_E to COND_NE.
81 CondCode GetOppositeBranchCondition(X86::CondCode CC);
85 /// X86II - This namespace holds all of the target specific flags that
86 /// instruction info tracks.
89 /// Target Operand Flag enum.
91 //===------------------------------------------------------------------===//
92 // X86 Specific MachineOperand flags.
96 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
98 /// SYMBOL_LABEL + [. - PICBASELABEL]
99 MO_GOT_ABSOLUTE_ADDRESS,
101 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
102 /// immediate should get the value of the symbol minus the PIC base label:
103 /// SYMBOL_LABEL - PICBASELABEL
106 /// MO_GOT - On a symbol operand this indicates that the immediate is the
107 /// offset to the GOT entry for the symbol name from the base of the GOT.
109 /// See the X86-64 ELF ABI supplement for more details.
110 /// SYMBOL_LABEL @GOT
113 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
114 /// the offset to the location of the symbol name from the base of the GOT.
116 /// See the X86-64 ELF ABI supplement for more details.
117 /// SYMBOL_LABEL @GOTOFF
120 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
121 /// offset to the GOT entry for the symbol name from the current code
124 /// See the X86-64 ELF ABI supplement for more details.
125 /// SYMBOL_LABEL @GOTPCREL
128 /// MO_PLT - On a symbol operand this indicates that the immediate is
129 /// offset to the PLT entry of symbol name from the current code location.
131 /// See the X86-64 ELF ABI supplement for more details.
132 /// SYMBOL_LABEL @PLT
135 /// MO_TLSGD - On a symbol operand this indicates that the immediate is
138 /// See 'ELF Handling for Thread-Local Storage' for more details.
139 /// SYMBOL_LABEL @TLSGD
142 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
145 /// See 'ELF Handling for Thread-Local Storage' for more details.
146 /// SYMBOL_LABEL @GOTTPOFF
149 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
152 /// See 'ELF Handling for Thread-Local Storage' for more details.
153 /// SYMBOL_LABEL @INDNTPOFF
156 /// MO_TPOFF - On a symbol operand this indicates that the immediate is
159 /// See 'ELF Handling for Thread-Local Storage' for more details.
160 /// SYMBOL_LABEL @TPOFF
163 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
166 /// See 'ELF Handling for Thread-Local Storage' for more details.
167 /// SYMBOL_LABEL @NTPOFF
170 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
171 /// reference is actually to the "__imp_FOO" symbol. This is used for
172 /// dllimport linkage on windows.
175 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the
176 /// reference is actually to the "FOO$stub" symbol. This is used for calls
177 /// and jumps to external functions on Tiger and before.
180 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
181 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
182 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
185 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
186 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
187 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
188 MO_DARWIN_NONLAZY_PIC_BASE,
190 /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this
191 /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE",
192 /// which is a PIC-base-relative reference to a hidden dyld lazy pointer
194 MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE,
196 /// MO_TLVP - On a symbol operand this indicates that the immediate is
199 /// This is the TLS offset for the Darwin TLS mechanism.
202 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
203 /// is some TLS offset from the picbase.
205 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
210 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
211 /// a reference to a stub for a global, not the global itself.
212 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
213 switch (TargetFlag) {
214 case X86II::MO_DLLIMPORT: // dllimport stub.
215 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
216 case X86II::MO_GOT: // normal GOT reference.
217 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
218 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
219 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
226 /// isGlobalRelativeToPICBase - Return true if the specified global value
227 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
228 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
229 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
230 switch (TargetFlag) {
231 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
232 case X86II::MO_GOT: // isPICStyleGOT: other global.
233 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
234 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
235 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global.
236 case X86II::MO_TLVP: // ??? Pretty sure..
243 /// X86II - This namespace holds all of the target specific flags that
244 /// instruction info tracks.
248 //===------------------------------------------------------------------===//
249 // Instruction encodings. These are the standard/most common forms for X86
253 // PseudoFrm - This represents an instruction that is a pseudo instruction
254 // or one that has not been implemented yet. It is illegal to code generate
255 // it, but tolerated for intermediate implementation stages.
258 /// Raw - This form is for instructions that don't have any operands, so
259 /// they are just a fixed opcode value, like 'leave'.
262 /// AddRegFrm - This form is used for instructions like 'push r32' that have
263 /// their one register operand added to their opcode.
266 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
267 /// to specify a destination, which in this case is a register.
271 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
272 /// to specify a destination, which in this case is memory.
276 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
277 /// to specify a source, which in this case is a register.
281 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
282 /// to specify a source, which in this case is memory.
286 /// MRM[0-7][rm] - These forms are used to represent instructions that use
287 /// a Mod/RM byte, and use the middle field to hold extended opcode
288 /// information. In the intel manual these are represented as /0, /1, ...
291 // First, instructions that operate on a register r/m operand...
292 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3
293 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7
295 // Next, instructions that operate on a memory r/m operand...
296 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3
297 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
299 // MRMInitReg - This form is used for instructions whose source and
300 // destinations are the same register.
303 //// MRM_C1 - A mod/rm byte of exactly 0xC1.
315 /// RawFrmImm16 - This is used for CALL FAR instructions, which have two
316 /// immediates, the first of which is a 16 or 32-bit immediate (specified by
317 /// the imm encoding) and the second is a 16-bit fixed value. In the AMD
318 /// manual, this operand is described as pntr16:32 and pntr16:16
323 //===------------------------------------------------------------------===//
326 // OpSize - Set if this instruction requires an operand size prefix (0x66),
327 // which most often indicates that the instruction operates on 16 bit data
328 // instead of 32 bit data.
331 // AsSize - Set if this instruction requires an operand size prefix (0x67),
332 // which most often indicates that the instruction address 16 bit address
333 // instead of 32 bit address (or 32 bit address in 64 bit mode).
336 //===------------------------------------------------------------------===//
337 // Op0Mask - There are several prefix bytes that are used to form two byte
338 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
339 // used to obtain the setting of this field. If no bits in this field is
340 // set, there is no prefix byte for obtaining a multibyte opcode.
343 Op0Mask = 0xF << Op0Shift,
345 // TB - TwoByte - Set if this instruction has a two byte opcode, which
346 // starts with a 0x0F byte before the real opcode.
349 // REP - The 0xF3 prefix byte indicating repetition of the following
353 // D8-DF - These escape opcodes are used by the floating point unit. These
354 // values must remain sequential.
355 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift,
356 DA = 5 << Op0Shift, DB = 6 << Op0Shift,
357 DC = 7 << Op0Shift, DD = 8 << Op0Shift,
358 DE = 9 << Op0Shift, DF = 10 << Op0Shift,
360 // XS, XD - These prefix codes are for single and double precision scalar
361 // floating point operations performed in the SSE registers.
362 XD = 11 << Op0Shift, XS = 12 << Op0Shift,
364 // T8, TA - Prefix after the 0x0F prefix.
365 T8 = 13 << Op0Shift, TA = 14 << Op0Shift,
367 // TF - Prefix before and after 0x0F
370 //===------------------------------------------------------------------===//
371 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
372 // They are used to specify GPRs and SSE registers, 64-bit operand size,
373 // etc. We only cares about REX.W and REX.R bits and only the former is
374 // statically determined.
377 REX_W = 1 << REXShift,
379 //===------------------------------------------------------------------===//
380 // This three-bit field describes the size of an immediate operand. Zero is
381 // unused so that we can tell if we forgot to set a value.
383 ImmMask = 7 << ImmShift,
384 Imm8 = 1 << ImmShift,
385 Imm8PCRel = 2 << ImmShift,
386 Imm16 = 3 << ImmShift,
387 Imm16PCRel = 4 << ImmShift,
388 Imm32 = 5 << ImmShift,
389 Imm32PCRel = 6 << ImmShift,
390 Imm64 = 7 << ImmShift,
392 //===------------------------------------------------------------------===//
393 // FP Instruction Classification... Zero is non-fp instruction.
395 // FPTypeMask - Mask for all of the FP types...
397 FPTypeMask = 7 << FPTypeShift,
399 // NotFP - The default, set for instructions that do not use FP registers.
400 NotFP = 0 << FPTypeShift,
402 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
403 ZeroArgFP = 1 << FPTypeShift,
405 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
406 OneArgFP = 2 << FPTypeShift,
408 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
409 // result back to ST(0). For example, fcos, fsqrt, etc.
411 OneArgFPRW = 3 << FPTypeShift,
413 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
414 // explicit argument, storing the result to either ST(0) or the implicit
415 // argument. For example: fadd, fsub, fmul, etc...
416 TwoArgFP = 4 << FPTypeShift,
418 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
419 // explicit argument, but have no destination. Example: fucom, fucomi, ...
420 CompareFP = 5 << FPTypeShift,
422 // CondMovFP - "2 operand" floating point conditional move instructions.
423 CondMovFP = 6 << FPTypeShift,
425 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
426 SpecialFP = 7 << FPTypeShift,
430 LOCK = 1 << LOCKShift,
432 // Segment override prefixes. Currently we just need ability to address
433 // stuff in gs and fs segments.
435 SegOvrMask = 3 << SegOvrShift,
436 FS = 1 << SegOvrShift,
437 GS = 2 << SegOvrShift,
439 // Execution domain for SSE instructions in bits 22, 23.
440 // 0 in bits 22-23 means normal, non-SSE instruction.
444 OpcodeMask = 0xFF << OpcodeShift,
446 //===------------------------------------------------------------------===//
447 // VEX - The opcode prefix used by AVX instructions
450 // VEX_W - Has a opcode specific functionality, but is used in the same
451 // way as REX_W is for regular SSE instructions.
454 // VEX_4V - Used to specify an additional AVX/SSE register. Several 2
455 // address instructions in SSE are represented as 3 address ones in AVX
456 // and the additional register is encoded in VEX_VVVV prefix.
459 // VEX_I8IMM - Specifies that the last register used in a AVX instruction,
460 // must be encoded in the i8 immediate field. This usually happens in
461 // instructions with 4 operands.
464 // VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
465 // instruction uses 256-bit wide registers. This is usually auto detected if
466 // a VR256 register is used, but some AVX instructions also have this field
467 // marked when using a f256 memory references.
471 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
472 // specified machine instruction.
474 static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) {
475 return TSFlags >> X86II::OpcodeShift;
478 static inline bool hasImm(uint64_t TSFlags) {
479 return (TSFlags & X86II::ImmMask) != 0;
482 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
483 /// of the specified instruction.
484 static inline unsigned getSizeOfImm(uint64_t TSFlags) {
485 switch (TSFlags & X86II::ImmMask) {
486 default: assert(0 && "Unknown immediate size");
488 case X86II::Imm8PCRel: return 1;
490 case X86II::Imm16PCRel: return 2;
492 case X86II::Imm32PCRel: return 4;
493 case X86II::Imm64: return 8;
497 /// isImmPCRel - Return true if the immediate of the specified instruction's
498 /// TSFlags indicates that it is pc relative.
499 static inline unsigned isImmPCRel(uint64_t TSFlags) {
500 switch (TSFlags & X86II::ImmMask) {
501 default: assert(0 && "Unknown immediate size");
502 case X86II::Imm8PCRel:
503 case X86II::Imm16PCRel:
504 case X86II::Imm32PCRel:
514 /// getMemoryOperandNo - The function returns the MCInst operand # for the
515 /// first field of the memory operand. If the instruction doesn't have a
516 /// memory operand, this returns -1.
518 /// Note that this ignores tied operands. If there is a tied register which
519 /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only
520 /// counted as one operand.
522 static inline int getMemoryOperandNo(uint64_t TSFlags) {
523 switch (TSFlags & X86II::FormMask) {
524 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this form");
525 default: assert(0 && "Unknown FormMask value in getMemoryOperandNo!");
528 case X86II::AddRegFrm:
529 case X86II::MRMDestReg:
530 case X86II::MRMSrcReg:
531 case X86II::RawFrmImm16:
533 case X86II::MRMDestMem:
535 case X86II::MRMSrcMem: {
536 bool HasVEX_4V = (TSFlags >> 32) & X86II::VEX_4V;
537 unsigned FirstMemOp = 1;
539 ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV).
541 // FIXME: Maybe lea should have its own form? This is a horrible hack.
542 //if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
543 // Opcode == X86::LEA16r || Opcode == X86::LEA32r)
546 case X86II::MRM0r: case X86II::MRM1r:
547 case X86II::MRM2r: case X86II::MRM3r:
548 case X86II::MRM4r: case X86II::MRM5r:
549 case X86II::MRM6r: case X86II::MRM7r:
551 case X86II::MRM0m: case X86II::MRM1m:
552 case X86II::MRM2m: case X86II::MRM3m:
553 case X86II::MRM4m: case X86II::MRM5m:
554 case X86II::MRM6m: case X86II::MRM7m:
571 inline static bool isScale(const MachineOperand &MO) {
573 (MO.getImm() == 1 || MO.getImm() == 2 ||
574 MO.getImm() == 4 || MO.getImm() == 8);
577 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
578 if (MI->getOperand(Op).isFI()) return true;
579 return Op+4 <= MI->getNumOperands() &&
580 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
581 MI->getOperand(Op+2).isReg() &&
582 (MI->getOperand(Op+3).isImm() ||
583 MI->getOperand(Op+3).isGlobal() ||
584 MI->getOperand(Op+3).isCPI() ||
585 MI->getOperand(Op+3).isJTI());
588 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
589 if (MI->getOperand(Op).isFI()) return true;
590 return Op+5 <= MI->getNumOperands() &&
591 MI->getOperand(Op+4).isReg() &&
595 class X86InstrInfo : public TargetInstrInfoImpl {
596 X86TargetMachine &TM;
597 const X86RegisterInfo RI;
599 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
600 /// RegOp2MemOpTable2 - Load / store folding opcode maps.
602 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2Addr;
603 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable0;
604 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable1;
605 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2;
607 /// MemOp2RegOpTable - Load / store unfolding opcode map.
609 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable;
612 explicit X86InstrInfo(X86TargetMachine &tm);
614 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
615 /// such, whenever a client has an instance of instruction info, it should
616 /// always be able to get register info as well (through this method).
618 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
620 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
621 /// extension instruction. That is, it's like a copy where it's legal for the
622 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
623 /// true, then it's expected the pre-extension value is available as a subreg
624 /// of the result register. This also returns the sub-register index in
626 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
627 unsigned &SrcReg, unsigned &DstReg,
628 unsigned &SubIdx) const;
630 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
631 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
632 /// stack locations as well. This uses a heuristic so it isn't
633 /// reliable for correctness.
634 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
635 int &FrameIndex) const;
637 /// hasLoadFromStackSlot - If the specified machine instruction has
638 /// a load from a stack slot, return true along with the FrameIndex
639 /// of the loaded stack slot and the machine mem operand containing
640 /// the reference. If not, return false. Unlike
641 /// isLoadFromStackSlot, this returns true for any instructions that
642 /// loads from the stack. This is a hint only and may not catch all
644 bool hasLoadFromStackSlot(const MachineInstr *MI,
645 const MachineMemOperand *&MMO,
646 int &FrameIndex) const;
648 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
649 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
650 /// stack locations as well. This uses a heuristic so it isn't
651 /// reliable for correctness.
652 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
653 int &FrameIndex) const;
655 /// hasStoreToStackSlot - If the specified machine instruction has a
656 /// store to a stack slot, return true along with the FrameIndex of
657 /// the loaded stack slot and the machine mem operand containing the
658 /// reference. If not, return false. Unlike isStoreToStackSlot,
659 /// this returns true for any instructions that loads from the
660 /// stack. This is a hint only and may not catch all cases.
661 bool hasStoreToStackSlot(const MachineInstr *MI,
662 const MachineMemOperand *&MMO,
663 int &FrameIndex) const;
665 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
666 AliasAnalysis *AA) const;
667 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
668 unsigned DestReg, unsigned SubIdx,
669 const MachineInstr *Orig,
670 const TargetRegisterInfo &TRI) const;
672 /// convertToThreeAddress - This method must be implemented by targets that
673 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
674 /// may be able to convert a two-address instruction into a true
675 /// three-address instruction on demand. This allows the X86 target (for
676 /// example) to convert ADD and SHL instructions into LEA instructions if they
677 /// would require register copies due to two-addressness.
679 /// This method returns a null pointer if the transformation cannot be
680 /// performed, otherwise it returns the new instruction.
682 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
683 MachineBasicBlock::iterator &MBBI,
684 LiveVariables *LV) const;
686 /// commuteInstruction - We have a few instructions that must be hacked on to
689 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
692 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
693 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
694 MachineBasicBlock *&FBB,
695 SmallVectorImpl<MachineOperand> &Cond,
696 bool AllowModify) const;
697 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
698 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
699 MachineBasicBlock *FBB,
700 const SmallVectorImpl<MachineOperand> &Cond,
702 virtual void copyPhysReg(MachineBasicBlock &MBB,
703 MachineBasicBlock::iterator MI, DebugLoc DL,
704 unsigned DestReg, unsigned SrcReg,
706 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
707 MachineBasicBlock::iterator MI,
708 unsigned SrcReg, bool isKill, int FrameIndex,
709 const TargetRegisterClass *RC,
710 const TargetRegisterInfo *TRI) const;
712 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
713 SmallVectorImpl<MachineOperand> &Addr,
714 const TargetRegisterClass *RC,
715 MachineInstr::mmo_iterator MMOBegin,
716 MachineInstr::mmo_iterator MMOEnd,
717 SmallVectorImpl<MachineInstr*> &NewMIs) const;
719 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
720 MachineBasicBlock::iterator MI,
721 unsigned DestReg, int FrameIndex,
722 const TargetRegisterClass *RC,
723 const TargetRegisterInfo *TRI) const;
725 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
726 SmallVectorImpl<MachineOperand> &Addr,
727 const TargetRegisterClass *RC,
728 MachineInstr::mmo_iterator MMOBegin,
729 MachineInstr::mmo_iterator MMOEnd,
730 SmallVectorImpl<MachineInstr*> &NewMIs) const;
732 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
733 MachineBasicBlock::iterator MI,
734 const std::vector<CalleeSavedInfo> &CSI,
735 const TargetRegisterInfo *TRI) const;
737 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
738 MachineBasicBlock::iterator MI,
739 const std::vector<CalleeSavedInfo> &CSI,
740 const TargetRegisterInfo *TRI) const;
743 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
744 int FrameIx, uint64_t Offset,
748 /// foldMemoryOperand - If this target supports it, fold a load or store of
749 /// the specified stack slot into the specified machine instruction for the
750 /// specified operand(s). If this is possible, the target should perform the
751 /// folding and return true, otherwise it should return false. If it folds
752 /// the instruction, it is likely that the MachineInstruction the iterator
753 /// references has been changed.
754 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
756 const SmallVectorImpl<unsigned> &Ops,
757 int FrameIndex) const;
759 /// foldMemoryOperand - Same as the previous version except it allows folding
760 /// of any load and store from / to any address, not just from a specific
762 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
764 const SmallVectorImpl<unsigned> &Ops,
765 MachineInstr* LoadMI) const;
767 /// canFoldMemoryOperand - Returns true if the specified load / store is
768 /// folding is possible.
769 virtual bool canFoldMemoryOperand(const MachineInstr*,
770 const SmallVectorImpl<unsigned> &) const;
772 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
773 /// a store or a load and a store into two or more instruction. If this is
774 /// possible, returns true as well as the new instructions by reference.
775 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
776 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
777 SmallVectorImpl<MachineInstr*> &NewMIs) const;
779 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
780 SmallVectorImpl<SDNode*> &NewNodes) const;
782 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
783 /// instruction after load / store are unfolded from an instruction of the
784 /// specified opcode. It returns zero if the specified unfolding is not
785 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
786 /// index of the operand which will hold the register holding the loaded
788 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
789 bool UnfoldLoad, bool UnfoldStore,
790 unsigned *LoadRegIndex = 0) const;
792 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
793 /// to determine if two loads are loading from the same base address. It
794 /// should only return true if the base pointers are the same and the
795 /// only differences between the two addresses are the offset. It also returns
796 /// the offsets by reference.
797 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
798 int64_t &Offset1, int64_t &Offset2) const;
800 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
801 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
802 /// be scheduled togther. On some targets if two loads are loading from
803 /// addresses in the same cache line, it's better if they are scheduled
804 /// together. This function takes two integers that represent the load offsets
805 /// from the common base address. It returns true if it decides it's desirable
806 /// to schedule the two loads together. "NumLoads" is the number of loads that
807 /// have already been scheduled after Load1.
808 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
809 int64_t Offset1, int64_t Offset2,
810 unsigned NumLoads) const;
812 virtual void getNoopForMachoTarget(MCInst &NopInst) const;
815 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
817 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
818 /// instruction that defines the specified register class.
819 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
821 static bool isX86_64NonExtLowByteReg(unsigned reg) {
822 return (reg == X86::SPL || reg == X86::BPL ||
823 reg == X86::SIL || reg == X86::DIL);
826 static bool isX86_64ExtendedReg(const MachineOperand &MO) {
827 if (!MO.isReg()) return false;
828 return isX86_64ExtendedReg(MO.getReg());
831 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or
832 /// higher) register? e.g. r8, xmm8, xmm13, etc.
833 static bool isX86_64ExtendedReg(unsigned RegNo);
835 /// getGlobalBaseReg - Return a virtual register initialized with the
836 /// the global base register value. Output instructions required to
837 /// initialize the register in the function entry block, if necessary.
839 unsigned getGlobalBaseReg(MachineFunction *MF) const;
841 /// GetSSEDomain - Return the SSE execution domain of MI as the first element,
842 /// and a bitmask of possible arguments to SetSSEDomain ase the second.
843 std::pair<uint16_t, uint16_t> GetSSEDomain(const MachineInstr *MI) const;
845 /// SetSSEDomain - Set the SSEDomain of MI.
846 void SetSSEDomain(MachineInstr *MI, unsigned Domain) const;
849 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
850 MachineFunction::iterator &MFI,
851 MachineBasicBlock::iterator &MBBI,
852 LiveVariables *LV) const;
854 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
857 const SmallVectorImpl<MachineOperand> &MOs,
858 unsigned Size, unsigned Alignment) const;
860 /// isFrameOperand - Return true and the FrameIndex if the specified
861 /// operand and follow operands form a reference to the stack frame.
862 bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
863 int &FrameIndex) const;
866 } // End llvm namespace