1 //===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86INSTRUCTIONINFO_H
15 #define X86INSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "llvm/ADT/DenseMap.h"
23 class X86RegisterInfo;
24 class X86TargetMachine;
27 // X86 specific condition code. These correspond to X86_*_COND in
28 // X86InstrInfo.td. They must be kept in synch.
47 // Artificial condition codes. These are used by AnalyzeBranch
48 // to indicate a block terminated with two conditional branches to
49 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
50 // which can't be represented on x86 with a single condition. These
51 // are never used in MachineInstrs.
58 // Turn condition code into conditional branch opcode.
59 unsigned GetCondBranchFromCond(CondCode CC);
61 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
62 /// e.g. turning COND_E to COND_NE.
63 CondCode GetOppositeBranchCondition(X86::CondCode CC);
67 /// X86II - This namespace holds all of the target specific flags that
68 /// instruction info tracks.
71 /// Target Operand Flag enum.
73 //===------------------------------------------------------------------===//
74 // X86 Specific MachineOperand flags.
78 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
80 /// SYMBOL_LABEL + [. - PICBASELABEL]
81 MO_GOT_ABSOLUTE_ADDRESS,
83 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
84 /// immediate should get the value of the symbol minus the PIC base label:
85 /// SYMBOL_LABEL - PICBASELABEL
88 /// MO_GOT - On a symbol operand this indicates that the immediate is the
89 /// offset to the GOT entry for the symbol name from the base of the GOT.
91 /// See the X86-64 ELF ABI supplement for more details.
95 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
96 /// the offset to the location of the symbol name from the base of the GOT.
98 /// See the X86-64 ELF ABI supplement for more details.
99 /// SYMBOL_LABEL @GOTOFF
102 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
103 /// offset to the GOT entry for the symbol name from the current code
106 /// See the X86-64 ELF ABI supplement for more details.
107 /// SYMBOL_LABEL @GOTPCREL
110 /// MO_PLT - On a symbol operand this indicates that the immediate is
111 /// offset to the PLT entry of symbol name from the current code location.
113 /// See the X86-64 ELF ABI supplement for more details.
114 /// SYMBOL_LABEL @PLT
117 /// MO_TLSGD - On a symbol operand this indicates that the immediate is
120 /// See 'ELF Handling for Thread-Local Storage' for more details.
121 /// SYMBOL_LABEL @TLSGD
124 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
127 /// See 'ELF Handling for Thread-Local Storage' for more details.
128 /// SYMBOL_LABEL @GOTTPOFF
131 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
134 /// See 'ELF Handling for Thread-Local Storage' for more details.
135 /// SYMBOL_LABEL @INDNTPOFF
138 /// MO_TPOFF - On a symbol operand this indicates that the immediate is
141 /// See 'ELF Handling for Thread-Local Storage' for more details.
142 /// SYMBOL_LABEL @TPOFF
145 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
148 /// See 'ELF Handling for Thread-Local Storage' for more details.
149 /// SYMBOL_LABEL @NTPOFF
152 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
153 /// reference is actually to the "__imp_FOO" symbol. This is used for
154 /// dllimport linkage on windows.
157 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the
158 /// reference is actually to the "FOO$stub" symbol. This is used for calls
159 /// and jumps to external functions on Tiger and before.
162 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
163 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
164 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
167 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
168 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
169 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
170 MO_DARWIN_NONLAZY_PIC_BASE,
172 /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this
173 /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE",
174 /// which is a PIC-base-relative reference to a hidden dyld lazy pointer
176 MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE,
178 /// MO_TLVP - On a symbol operand this indicates that the immediate is
181 /// This is the TLS offset for the Darwin TLS mechanism.
184 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
185 /// is some TLS offset from the picbase.
187 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
192 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
193 /// a reference to a stub for a global, not the global itself.
194 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
195 switch (TargetFlag) {
196 case X86II::MO_DLLIMPORT: // dllimport stub.
197 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
198 case X86II::MO_GOT: // normal GOT reference.
199 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
200 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
201 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
208 /// isGlobalRelativeToPICBase - Return true if the specified global value
209 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
210 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
211 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
212 switch (TargetFlag) {
213 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
214 case X86II::MO_GOT: // isPICStyleGOT: other global.
215 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
216 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
217 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global.
218 case X86II::MO_TLVP: // ??? Pretty sure..
225 /// X86II - This namespace holds all of the target specific flags that
226 /// instruction info tracks.
230 //===------------------------------------------------------------------===//
231 // Instruction encodings. These are the standard/most common forms for X86
235 // PseudoFrm - This represents an instruction that is a pseudo instruction
236 // or one that has not been implemented yet. It is illegal to code generate
237 // it, but tolerated for intermediate implementation stages.
240 /// Raw - This form is for instructions that don't have any operands, so
241 /// they are just a fixed opcode value, like 'leave'.
244 /// AddRegFrm - This form is used for instructions like 'push r32' that have
245 /// their one register operand added to their opcode.
248 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
249 /// to specify a destination, which in this case is a register.
253 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
254 /// to specify a destination, which in this case is memory.
258 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
259 /// to specify a source, which in this case is a register.
263 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
264 /// to specify a source, which in this case is memory.
268 /// MRM[0-7][rm] - These forms are used to represent instructions that use
269 /// a Mod/RM byte, and use the middle field to hold extended opcode
270 /// information. In the intel manual these are represented as /0, /1, ...
273 // First, instructions that operate on a register r/m operand...
274 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3
275 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7
277 // Next, instructions that operate on a memory r/m operand...
278 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3
279 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
281 // MRMInitReg - This form is used for instructions whose source and
282 // destinations are the same register.
285 //// MRM_C1 - A mod/rm byte of exactly 0xC1.
299 //===------------------------------------------------------------------===//
302 // OpSize - Set if this instruction requires an operand size prefix (0x66),
303 // which most often indicates that the instruction operates on 16 bit data
304 // instead of 32 bit data.
307 // AsSize - Set if this instruction requires an operand size prefix (0x67),
308 // which most often indicates that the instruction address 16 bit address
309 // instead of 32 bit address (or 32 bit address in 64 bit mode).
312 //===------------------------------------------------------------------===//
313 // Op0Mask - There are several prefix bytes that are used to form two byte
314 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
315 // used to obtain the setting of this field. If no bits in this field is
316 // set, there is no prefix byte for obtaining a multibyte opcode.
319 Op0Mask = 0xF << Op0Shift,
321 // TB - TwoByte - Set if this instruction has a two byte opcode, which
322 // starts with a 0x0F byte before the real opcode.
325 // REP - The 0xF3 prefix byte indicating repetition of the following
329 // D8-DF - These escape opcodes are used by the floating point unit. These
330 // values must remain sequential.
331 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift,
332 DA = 5 << Op0Shift, DB = 6 << Op0Shift,
333 DC = 7 << Op0Shift, DD = 8 << Op0Shift,
334 DE = 9 << Op0Shift, DF = 10 << Op0Shift,
336 // XS, XD - These prefix codes are for single and double precision scalar
337 // floating point operations performed in the SSE registers.
338 XD = 11 << Op0Shift, XS = 12 << Op0Shift,
340 // T8, TA - Prefix after the 0x0F prefix.
341 T8 = 13 << Op0Shift, TA = 14 << Op0Shift,
343 // TF - Prefix before and after 0x0F
346 //===------------------------------------------------------------------===//
347 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
348 // They are used to specify GPRs and SSE registers, 64-bit operand size,
349 // etc. We only cares about REX.W and REX.R bits and only the former is
350 // statically determined.
353 REX_W = 1 << REXShift,
355 //===------------------------------------------------------------------===//
356 // This three-bit field describes the size of an immediate operand. Zero is
357 // unused so that we can tell if we forgot to set a value.
359 ImmMask = 7 << ImmShift,
360 Imm8 = 1 << ImmShift,
361 Imm8PCRel = 2 << ImmShift,
362 Imm16 = 3 << ImmShift,
363 Imm32 = 4 << ImmShift,
364 Imm32PCRel = 5 << ImmShift,
365 Imm64 = 6 << ImmShift,
367 //===------------------------------------------------------------------===//
368 // FP Instruction Classification... Zero is non-fp instruction.
370 // FPTypeMask - Mask for all of the FP types...
372 FPTypeMask = 7 << FPTypeShift,
374 // NotFP - The default, set for instructions that do not use FP registers.
375 NotFP = 0 << FPTypeShift,
377 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
378 ZeroArgFP = 1 << FPTypeShift,
380 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
381 OneArgFP = 2 << FPTypeShift,
383 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
384 // result back to ST(0). For example, fcos, fsqrt, etc.
386 OneArgFPRW = 3 << FPTypeShift,
388 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
389 // explicit argument, storing the result to either ST(0) or the implicit
390 // argument. For example: fadd, fsub, fmul, etc...
391 TwoArgFP = 4 << FPTypeShift,
393 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
394 // explicit argument, but have no destination. Example: fucom, fucomi, ...
395 CompareFP = 5 << FPTypeShift,
397 // CondMovFP - "2 operand" floating point conditional move instructions.
398 CondMovFP = 6 << FPTypeShift,
400 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
401 SpecialFP = 7 << FPTypeShift,
405 LOCK = 1 << LOCKShift,
407 // Segment override prefixes. Currently we just need ability to address
408 // stuff in gs and fs segments.
410 SegOvrMask = 3 << SegOvrShift,
411 FS = 1 << SegOvrShift,
412 GS = 2 << SegOvrShift,
414 // Execution domain for SSE instructions in bits 22, 23.
415 // 0 in bits 22-23 means normal, non-SSE instruction.
419 OpcodeMask = 0xFF << OpcodeShift
423 // FIXME: The enum opcode space is over and more bits are needed. Anywhere
424 // those enums below are used, TSFlags must be shifted right by 32 first.
426 //===------------------------------------------------------------------===//
427 // VEX_4V - VEX prefixes are instruction prefixes used in AVX.
428 // VEX_4V is used to specify an additional AVX/SSE register. Several 2
429 // address instructions in SSE are represented as 3 address ones in AVX
430 // and the additional register is encoded in VEX_VVVV prefix.
433 VEX_4V = 1 << VEXShift
436 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
437 // specified machine instruction.
439 static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) {
440 return TSFlags >> X86II::OpcodeShift;
443 static inline bool hasImm(uint64_t TSFlags) {
444 return (TSFlags & X86II::ImmMask) != 0;
447 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
448 /// of the specified instruction.
449 static inline unsigned getSizeOfImm(uint64_t TSFlags) {
450 switch (TSFlags & X86II::ImmMask) {
451 default: assert(0 && "Unknown immediate size");
453 case X86II::Imm8PCRel: return 1;
454 case X86II::Imm16: return 2;
456 case X86II::Imm32PCRel: return 4;
457 case X86II::Imm64: return 8;
461 /// isImmPCRel - Return true if the immediate of the specified instruction's
462 /// TSFlags indicates that it is pc relative.
463 static inline unsigned isImmPCRel(uint64_t TSFlags) {
464 switch (TSFlags & X86II::ImmMask) {
465 default: assert(0 && "Unknown immediate size");
466 case X86II::Imm8PCRel:
467 case X86II::Imm32PCRel:
478 const int X86AddrNumOperands = 5;
480 inline static bool isScale(const MachineOperand &MO) {
482 (MO.getImm() == 1 || MO.getImm() == 2 ||
483 MO.getImm() == 4 || MO.getImm() == 8);
486 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
487 if (MI->getOperand(Op).isFI()) return true;
488 return Op+4 <= MI->getNumOperands() &&
489 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
490 MI->getOperand(Op+2).isReg() &&
491 (MI->getOperand(Op+3).isImm() ||
492 MI->getOperand(Op+3).isGlobal() ||
493 MI->getOperand(Op+3).isCPI() ||
494 MI->getOperand(Op+3).isJTI());
497 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
498 if (MI->getOperand(Op).isFI()) return true;
499 return Op+5 <= MI->getNumOperands() &&
500 MI->getOperand(Op+4).isReg() &&
504 class X86InstrInfo : public TargetInstrInfoImpl {
505 X86TargetMachine &TM;
506 const X86RegisterInfo RI;
508 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
509 /// RegOp2MemOpTable2 - Load / store folding opcode maps.
511 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2Addr;
512 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable0;
513 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable1;
514 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2;
516 /// MemOp2RegOpTable - Load / store unfolding opcode map.
518 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable;
521 explicit X86InstrInfo(X86TargetMachine &tm);
523 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
524 /// such, whenever a client has an instance of instruction info, it should
525 /// always be able to get register info as well (through this method).
527 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
529 /// Return true if the instruction is a register to register move and return
530 /// the source and dest operands and their sub-register indices by reference.
531 virtual bool isMoveInstr(const MachineInstr &MI,
532 unsigned &SrcReg, unsigned &DstReg,
533 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
535 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
536 /// extension instruction. That is, it's like a copy where it's legal for the
537 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
538 /// true, then it's expected the pre-extension value is available as a subreg
539 /// of the result register. This also returns the sub-register index in
541 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
542 unsigned &SrcReg, unsigned &DstReg,
543 unsigned &SubIdx) const;
545 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
546 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
547 /// stack locations as well. This uses a heuristic so it isn't
548 /// reliable for correctness.
549 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
550 int &FrameIndex) const;
552 /// hasLoadFromStackSlot - If the specified machine instruction has
553 /// a load from a stack slot, return true along with the FrameIndex
554 /// of the loaded stack slot and the machine mem operand containing
555 /// the reference. If not, return false. Unlike
556 /// isLoadFromStackSlot, this returns true for any instructions that
557 /// loads from the stack. This is a hint only and may not catch all
559 bool hasLoadFromStackSlot(const MachineInstr *MI,
560 const MachineMemOperand *&MMO,
561 int &FrameIndex) const;
563 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
564 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
565 /// stack locations as well. This uses a heuristic so it isn't
566 /// reliable for correctness.
567 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
568 int &FrameIndex) const;
570 /// hasStoreToStackSlot - If the specified machine instruction has a
571 /// store to a stack slot, return true along with the FrameIndex of
572 /// the loaded stack slot and the machine mem operand containing the
573 /// reference. If not, return false. Unlike isStoreToStackSlot,
574 /// this returns true for any instructions that loads from the
575 /// stack. This is a hint only and may not catch all cases.
576 bool hasStoreToStackSlot(const MachineInstr *MI,
577 const MachineMemOperand *&MMO,
578 int &FrameIndex) const;
580 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
581 AliasAnalysis *AA) const;
582 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
583 unsigned DestReg, unsigned SubIdx,
584 const MachineInstr *Orig,
585 const TargetRegisterInfo &TRI) const;
587 /// convertToThreeAddress - This method must be implemented by targets that
588 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
589 /// may be able to convert a two-address instruction into a true
590 /// three-address instruction on demand. This allows the X86 target (for
591 /// example) to convert ADD and SHL instructions into LEA instructions if they
592 /// would require register copies due to two-addressness.
594 /// This method returns a null pointer if the transformation cannot be
595 /// performed, otherwise it returns the new instruction.
597 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
598 MachineBasicBlock::iterator &MBBI,
599 LiveVariables *LV) const;
601 /// commuteInstruction - We have a few instructions that must be hacked on to
604 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
607 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
608 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
609 MachineBasicBlock *&FBB,
610 SmallVectorImpl<MachineOperand> &Cond,
611 bool AllowModify) const;
612 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
613 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
614 MachineBasicBlock *FBB,
615 const SmallVectorImpl<MachineOperand> &Cond) const;
616 virtual bool copyRegToReg(MachineBasicBlock &MBB,
617 MachineBasicBlock::iterator MI,
618 unsigned DestReg, unsigned SrcReg,
619 const TargetRegisterClass *DestRC,
620 const TargetRegisterClass *SrcRC,
622 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
623 MachineBasicBlock::iterator MI,
624 unsigned SrcReg, bool isKill, int FrameIndex,
625 const TargetRegisterClass *RC,
626 const TargetRegisterInfo *TRI) const;
628 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
629 SmallVectorImpl<MachineOperand> &Addr,
630 const TargetRegisterClass *RC,
631 MachineInstr::mmo_iterator MMOBegin,
632 MachineInstr::mmo_iterator MMOEnd,
633 SmallVectorImpl<MachineInstr*> &NewMIs) const;
635 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
636 MachineBasicBlock::iterator MI,
637 unsigned DestReg, int FrameIndex,
638 const TargetRegisterClass *RC,
639 const TargetRegisterInfo *TRI) const;
641 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
642 SmallVectorImpl<MachineOperand> &Addr,
643 const TargetRegisterClass *RC,
644 MachineInstr::mmo_iterator MMOBegin,
645 MachineInstr::mmo_iterator MMOEnd,
646 SmallVectorImpl<MachineInstr*> &NewMIs) const;
648 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
649 MachineBasicBlock::iterator MI,
650 const std::vector<CalleeSavedInfo> &CSI,
651 const TargetRegisterInfo *TRI) const;
653 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
654 MachineBasicBlock::iterator MI,
655 const std::vector<CalleeSavedInfo> &CSI,
656 const TargetRegisterInfo *TRI) const;
659 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
660 int FrameIx, uint64_t Offset,
664 /// foldMemoryOperand - If this target supports it, fold a load or store of
665 /// the specified stack slot into the specified machine instruction for the
666 /// specified operand(s). If this is possible, the target should perform the
667 /// folding and return true, otherwise it should return false. If it folds
668 /// the instruction, it is likely that the MachineInstruction the iterator
669 /// references has been changed.
670 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
672 const SmallVectorImpl<unsigned> &Ops,
673 int FrameIndex) const;
675 /// foldMemoryOperand - Same as the previous version except it allows folding
676 /// of any load and store from / to any address, not just from a specific
678 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
680 const SmallVectorImpl<unsigned> &Ops,
681 MachineInstr* LoadMI) const;
683 /// canFoldMemoryOperand - Returns true if the specified load / store is
684 /// folding is possible.
685 virtual bool canFoldMemoryOperand(const MachineInstr*,
686 const SmallVectorImpl<unsigned> &) const;
688 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
689 /// a store or a load and a store into two or more instruction. If this is
690 /// possible, returns true as well as the new instructions by reference.
691 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
692 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
693 SmallVectorImpl<MachineInstr*> &NewMIs) const;
695 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
696 SmallVectorImpl<SDNode*> &NewNodes) const;
698 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
699 /// instruction after load / store are unfolded from an instruction of the
700 /// specified opcode. It returns zero if the specified unfolding is not
701 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
702 /// index of the operand which will hold the register holding the loaded
704 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
705 bool UnfoldLoad, bool UnfoldStore,
706 unsigned *LoadRegIndex = 0) const;
708 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
709 /// to determine if two loads are loading from the same base address. It
710 /// should only return true if the base pointers are the same and the
711 /// only differences between the two addresses are the offset. It also returns
712 /// the offsets by reference.
713 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
714 int64_t &Offset1, int64_t &Offset2) const;
716 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
717 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
718 /// be scheduled togther. On some targets if two loads are loading from
719 /// addresses in the same cache line, it's better if they are scheduled
720 /// together. This function takes two integers that represent the load offsets
721 /// from the common base address. It returns true if it decides it's desirable
722 /// to schedule the two loads together. "NumLoads" is the number of loads that
723 /// have already been scheduled after Load1.
724 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
725 int64_t Offset1, int64_t Offset2,
726 unsigned NumLoads) const;
728 virtual void getNoopForMachoTarget(MCInst &NopInst) const;
731 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
733 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
734 /// instruction that defines the specified register class.
735 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
737 static bool isX86_64NonExtLowByteReg(unsigned reg) {
738 return (reg == X86::SPL || reg == X86::BPL ||
739 reg == X86::SIL || reg == X86::DIL);
742 static bool isX86_64ExtendedReg(const MachineOperand &MO) {
743 if (!MO.isReg()) return false;
744 return isX86_64ExtendedReg(MO.getReg());
746 static unsigned determineREX(const MachineInstr &MI);
748 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or
749 /// higher) register? e.g. r8, xmm8, xmm13, etc.
750 static bool isX86_64ExtendedReg(unsigned RegNo);
752 /// GetInstSize - Returns the size of the specified MachineInstr.
754 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
756 /// getGlobalBaseReg - Return a virtual register initialized with the
757 /// the global base register value. Output instructions required to
758 /// initialize the register in the function entry block, if necessary.
760 unsigned getGlobalBaseReg(MachineFunction *MF) const;
762 /// GetSSEDomain - Return the SSE execution domain of MI as the first element,
763 /// and a bitmask of possible arguments to SetSSEDomain ase the second.
764 std::pair<uint16_t, uint16_t> GetSSEDomain(const MachineInstr *MI) const;
766 /// SetSSEDomain - Set the SSEDomain of MI.
767 void SetSSEDomain(MachineInstr *MI, unsigned Domain) const;
770 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
771 MachineFunction::iterator &MFI,
772 MachineBasicBlock::iterator &MBBI,
773 LiveVariables *LV) const;
775 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
778 const SmallVectorImpl<MachineOperand> &MOs,
779 unsigned Size, unsigned Alignment) const;
781 /// isFrameOperand - Return true and the FrameIndex if the specified
782 /// operand and follow operands form a reference to the stack frame.
783 bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
784 int &FrameIndex) const;
787 } // End llvm namespace