1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Target/TargetOptions.h"
27 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
28 : TargetInstrInfo(X86Insts, array_lengthof(X86Insts)),
29 TM(tm), RI(tm, *this) {
32 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
34 unsigned& destReg) const {
35 MachineOpCode oc = MI.getOpcode();
36 if (oc == X86::MOV8rr || oc == X86::MOV16rr ||
37 oc == X86::MOV32rr || oc == X86::MOV64rr ||
38 oc == X86::MOV16to16_ || oc == X86::MOV32to32_ ||
39 oc == X86::MOV_Fp3232 || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
40 oc == X86::MOV_Fp3264 || oc == X86::MOV_Fp6432 || oc == X86::MOV_Fp6464 ||
41 oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
42 oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
43 oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
44 oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
45 oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) {
46 assert(MI.getNumOperands() >= 2 &&
47 MI.getOperand(0).isRegister() &&
48 MI.getOperand(1).isRegister() &&
49 "invalid register-register move instruction");
50 sourceReg = MI.getOperand(1).getReg();
51 destReg = MI.getOperand(0).getReg();
57 unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
58 int &FrameIndex) const {
59 switch (MI->getOpcode()) {
72 case X86::MMX_MOVD64rm:
73 case X86::MMX_MOVQ64rm:
74 if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
75 MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
76 MI->getOperand(2).getImmedValue() == 1 &&
77 MI->getOperand(3).getReg() == 0 &&
78 MI->getOperand(4).getImmedValue() == 0) {
79 FrameIndex = MI->getOperand(1).getFrameIndex();
80 return MI->getOperand(0).getReg();
87 unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
88 int &FrameIndex) const {
89 switch (MI->getOpcode()) {
102 case X86::MMX_MOVD64mr:
103 case X86::MMX_MOVQ64mr:
104 case X86::MMX_MOVNTQmr:
105 if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
106 MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
107 MI->getOperand(1).getImmedValue() == 1 &&
108 MI->getOperand(2).getReg() == 0 &&
109 MI->getOperand(3).getImmedValue() == 0) {
110 FrameIndex = MI->getOperand(0).getFrameIndex();
111 return MI->getOperand(4).getReg();
119 bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const {
120 switch (MI->getOpcode()) {
133 case X86::MMX_MOVD64rm:
134 case X86::MMX_MOVQ64rm:
135 // Loads from constant pools are trivially rematerializable.
136 return MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate() &&
137 MI->getOperand(3).isRegister() && MI->getOperand(4).isConstantPoolIndex() &&
138 MI->getOperand(1).getReg() == 0 &&
139 MI->getOperand(2).getImmedValue() == 1 &&
140 MI->getOperand(3).getReg() == 0;
142 // All other instructions marked M_REMATERIALIZABLE are always trivially
147 /// convertToThreeAddress - This method must be implemented by targets that
148 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
149 /// may be able to convert a two-address instruction into a true
150 /// three-address instruction on demand. This allows the X86 target (for
151 /// example) to convert ADD and SHL instructions into LEA instructions if they
152 /// would require register copies due to two-addressness.
154 /// This method returns a null pointer if the transformation cannot be
155 /// performed, otherwise it returns the new instruction.
158 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
159 MachineBasicBlock::iterator &MBBI,
160 LiveVariables &LV) const {
161 MachineInstr *MI = MBBI;
162 // All instructions input are two-addr instructions. Get the known operands.
163 unsigned Dest = MI->getOperand(0).getReg();
164 unsigned Src = MI->getOperand(1).getReg();
166 MachineInstr *NewMI = NULL;
167 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
168 // we have better subtarget support, enable the 16-bit LEA generation here.
169 bool DisableLEA16 = true;
171 switch (MI->getOpcode()) {
173 case X86::SHUFPSrri: {
174 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
175 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
177 unsigned A = MI->getOperand(0).getReg();
178 unsigned B = MI->getOperand(1).getReg();
179 unsigned C = MI->getOperand(2).getReg();
180 unsigned M = MI->getOperand(3).getImm();
181 if (B != C) return 0;
182 NewMI = BuildMI(get(X86::PSHUFDri), A).addReg(B).addImm(M);
186 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
187 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
188 // the flags produced by a shift yet, so this is safe.
189 unsigned Dest = MI->getOperand(0).getReg();
190 unsigned Src = MI->getOperand(1).getReg();
191 unsigned ShAmt = MI->getOperand(2).getImm();
192 if (ShAmt == 0 || ShAmt >= 4) return 0;
194 NewMI = BuildMI(get(X86::LEA64r), Dest)
195 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
199 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
200 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
201 // the flags produced by a shift yet, so this is safe.
202 unsigned Dest = MI->getOperand(0).getReg();
203 unsigned Src = MI->getOperand(1).getReg();
204 unsigned ShAmt = MI->getOperand(2).getImm();
205 if (ShAmt == 0 || ShAmt >= 4) return 0;
207 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
208 X86::LEA64_32r : X86::LEA32r;
209 NewMI = BuildMI(get(Opc), Dest)
210 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
214 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
215 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
216 // the flags produced by a shift yet, so this is safe.
217 unsigned Dest = MI->getOperand(0).getReg();
218 unsigned Src = MI->getOperand(1).getReg();
219 unsigned ShAmt = MI->getOperand(2).getImm();
220 if (ShAmt == 0 || ShAmt >= 4) return 0;
223 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
224 SSARegMap *RegMap = MFI->getParent()->getSSARegMap();
225 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
226 ? X86::LEA64_32r : X86::LEA32r;
227 unsigned leaInReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
228 unsigned leaOutReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
231 BuildMI(get(X86::INSERT_SUBREG), leaInReg).addReg(Src).addImm(2);
232 Ins->copyKillDeadInfo(MI);
234 NewMI = BuildMI(get(Opc), leaOutReg)
235 .addReg(0).addImm(1 << ShAmt).addReg(leaInReg).addImm(0);
238 BuildMI(get(X86::EXTRACT_SUBREG), Dest).addReg(leaOutReg).addImm(2);
239 Ext->copyKillDeadInfo(MI);
241 MFI->insert(MBBI, Ins); // Insert the insert_subreg
242 LV.instructionChanged(MI, NewMI); // Update live variables
243 LV.addVirtualRegisterKilled(leaInReg, NewMI);
244 MFI->insert(MBBI, NewMI); // Insert the new inst
245 LV.addVirtualRegisterKilled(leaOutReg, Ext);
246 MFI->insert(MBBI, Ext); // Insert the extract_subreg
249 NewMI = BuildMI(get(X86::LEA16r), Dest)
250 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
256 // FIXME: None of these instructions are promotable to LEAs without
257 // additional information. In particular, LEA doesn't set the flags that
258 // add and inc do. :(
260 switch (MI->getOpcode()) {
263 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
264 NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, 1);
268 if (DisableLEA16) return 0;
269 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
270 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 1);
274 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
275 NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, -1);
279 if (DisableLEA16) return 0;
280 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
281 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, -1);
284 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
285 NewMI = addRegReg(BuildMI(get(X86::LEA32r), Dest), Src,
286 MI->getOperand(2).getReg());
289 if (DisableLEA16) return 0;
290 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
291 NewMI = addRegReg(BuildMI(get(X86::LEA16r), Dest), Src,
292 MI->getOperand(2).getReg());
296 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
297 if (MI->getOperand(2).isImmediate())
298 NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src,
299 MI->getOperand(2).getImmedValue());
303 if (DisableLEA16) return 0;
304 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
305 if (MI->getOperand(2).isImmediate())
306 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src,
307 MI->getOperand(2).getImmedValue());
310 if (DisableLEA16) return 0;
312 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImmediate() &&
313 "Unknown shl instruction!");
314 unsigned ShAmt = MI->getOperand(2).getImmedValue();
315 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
317 AM.Scale = 1 << ShAmt;
319 unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r;
320 NewMI = addFullAddress(BuildMI(get(Opc), Dest), AM);
326 NewMI->copyKillDeadInfo(MI);
327 LV.instructionChanged(MI, NewMI); // Update live variables
328 MFI->insert(MBBI, NewMI); // Insert the new inst
333 /// commuteInstruction - We have a few instructions that must be hacked on to
336 MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
337 // FIXME: Can commute cmoves by changing the condition!
338 switch (MI->getOpcode()) {
339 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
340 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
341 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
342 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
343 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
344 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
347 switch (MI->getOpcode()) {
348 default: assert(0 && "Unreachable!");
349 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
350 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
351 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
352 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
353 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
354 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
356 unsigned Amt = MI->getOperand(3).getImmedValue();
357 unsigned A = MI->getOperand(0).getReg();
358 unsigned B = MI->getOperand(1).getReg();
359 unsigned C = MI->getOperand(2).getReg();
360 bool BisKill = MI->getOperand(1).isKill();
361 bool CisKill = MI->getOperand(2).isKill();
362 return BuildMI(get(Opc), A).addReg(C, false, false, CisKill)
363 .addReg(B, false, false, BisKill).addImm(Size-Amt);
366 return TargetInstrInfo::commuteInstruction(MI);
370 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
372 default: return X86::COND_INVALID;
373 case X86::JE: return X86::COND_E;
374 case X86::JNE: return X86::COND_NE;
375 case X86::JL: return X86::COND_L;
376 case X86::JLE: return X86::COND_LE;
377 case X86::JG: return X86::COND_G;
378 case X86::JGE: return X86::COND_GE;
379 case X86::JB: return X86::COND_B;
380 case X86::JBE: return X86::COND_BE;
381 case X86::JA: return X86::COND_A;
382 case X86::JAE: return X86::COND_AE;
383 case X86::JS: return X86::COND_S;
384 case X86::JNS: return X86::COND_NS;
385 case X86::JP: return X86::COND_P;
386 case X86::JNP: return X86::COND_NP;
387 case X86::JO: return X86::COND_O;
388 case X86::JNO: return X86::COND_NO;
390 case X86::NEW_JE: return X86::COND_E;
391 case X86::NEW_JNE: return X86::COND_NE;
392 case X86::NEW_JL: return X86::COND_L;
393 case X86::NEW_JLE: return X86::COND_LE;
394 case X86::NEW_JG: return X86::COND_G;
395 case X86::NEW_JGE: return X86::COND_GE;
396 case X86::NEW_JB: return X86::COND_B;
397 case X86::NEW_JBE: return X86::COND_BE;
398 case X86::NEW_JA: return X86::COND_A;
399 case X86::NEW_JAE: return X86::COND_AE;
400 case X86::NEW_JS: return X86::COND_S;
401 case X86::NEW_JNS: return X86::COND_NS;
402 case X86::NEW_JP: return X86::COND_P;
403 case X86::NEW_JNP: return X86::COND_NP;
404 case X86::NEW_JO: return X86::COND_O;
405 case X86::NEW_JNO: return X86::COND_NO;
410 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
411 if (!NewCCModeling) {
413 default: assert(0 && "Illegal condition code!");
414 case X86::COND_E: return X86::JE;
415 case X86::COND_NE: return X86::JNE;
416 case X86::COND_L: return X86::JL;
417 case X86::COND_LE: return X86::JLE;
418 case X86::COND_G: return X86::JG;
419 case X86::COND_GE: return X86::JGE;
420 case X86::COND_B: return X86::JB;
421 case X86::COND_BE: return X86::JBE;
422 case X86::COND_A: return X86::JA;
423 case X86::COND_AE: return X86::JAE;
424 case X86::COND_S: return X86::JS;
425 case X86::COND_NS: return X86::JNS;
426 case X86::COND_P: return X86::JP;
427 case X86::COND_NP: return X86::JNP;
428 case X86::COND_O: return X86::JO;
429 case X86::COND_NO: return X86::JNO;
434 default: assert(0 && "Illegal condition code!");
435 case X86::COND_E: return X86::NEW_JE;
436 case X86::COND_NE: return X86::NEW_JNE;
437 case X86::COND_L: return X86::NEW_JL;
438 case X86::COND_LE: return X86::NEW_JLE;
439 case X86::COND_G: return X86::NEW_JG;
440 case X86::COND_GE: return X86::NEW_JGE;
441 case X86::COND_B: return X86::NEW_JB;
442 case X86::COND_BE: return X86::NEW_JBE;
443 case X86::COND_A: return X86::NEW_JA;
444 case X86::COND_AE: return X86::NEW_JAE;
445 case X86::COND_S: return X86::NEW_JS;
446 case X86::COND_NS: return X86::NEW_JNS;
447 case X86::COND_P: return X86::NEW_JP;
448 case X86::COND_NP: return X86::NEW_JNP;
449 case X86::COND_O: return X86::NEW_JO;
450 case X86::COND_NO: return X86::NEW_JNO;
454 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
455 /// e.g. turning COND_E to COND_NE.
456 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
458 default: assert(0 && "Illegal condition code!");
459 case X86::COND_E: return X86::COND_NE;
460 case X86::COND_NE: return X86::COND_E;
461 case X86::COND_L: return X86::COND_GE;
462 case X86::COND_LE: return X86::COND_G;
463 case X86::COND_G: return X86::COND_LE;
464 case X86::COND_GE: return X86::COND_L;
465 case X86::COND_B: return X86::COND_AE;
466 case X86::COND_BE: return X86::COND_A;
467 case X86::COND_A: return X86::COND_BE;
468 case X86::COND_AE: return X86::COND_B;
469 case X86::COND_S: return X86::COND_NS;
470 case X86::COND_NS: return X86::COND_S;
471 case X86::COND_P: return X86::COND_NP;
472 case X86::COND_NP: return X86::COND_P;
473 case X86::COND_O: return X86::COND_NO;
474 case X86::COND_NO: return X86::COND_O;
478 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
479 const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
480 if (TID->Flags & M_TERMINATOR_FLAG) {
481 // Conditional branch is a special case.
482 if ((TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0)
484 if ((TID->Flags & M_PREDICABLE) == 0)
486 return !isPredicated(MI);
491 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
492 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
493 const X86InstrInfo &TII) {
494 if (MI->getOpcode() == X86::FP_REG_KILL)
496 return TII.isUnpredicatedTerminator(MI);
499 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
500 MachineBasicBlock *&TBB,
501 MachineBasicBlock *&FBB,
502 std::vector<MachineOperand> &Cond) const {
503 // If the block has no terminators, it just falls into the block after it.
504 MachineBasicBlock::iterator I = MBB.end();
505 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this))
508 // Get the last instruction in the block.
509 MachineInstr *LastInst = I;
511 // If there is only one terminator instruction, process it.
512 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) {
513 if (!isBranch(LastInst->getOpcode()))
516 // If the block ends with a branch there are 3 possibilities:
517 // it's an unconditional, conditional, or indirect branch.
519 if (LastInst->getOpcode() == X86::JMP) {
520 TBB = LastInst->getOperand(0).getMachineBasicBlock();
523 X86::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
524 if (BranchCode == X86::COND_INVALID)
525 return true; // Can't handle indirect branch.
527 // Otherwise, block ends with fall-through condbranch.
528 TBB = LastInst->getOperand(0).getMachineBasicBlock();
529 Cond.push_back(MachineOperand::CreateImm(BranchCode));
533 // Get the instruction before it if it's a terminator.
534 MachineInstr *SecondLastInst = I;
536 // If there are three terminators, we don't know what sort of block this is.
537 if (SecondLastInst && I != MBB.begin() &&
538 isBrAnalysisUnpredicatedTerminator(--I, *this))
541 // If the block ends with X86::JMP and a conditional branch, handle it.
542 X86::CondCode BranchCode = GetCondFromBranchOpc(SecondLastInst->getOpcode());
543 if (BranchCode != X86::COND_INVALID && LastInst->getOpcode() == X86::JMP) {
544 TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
545 Cond.push_back(MachineOperand::CreateImm(BranchCode));
546 FBB = LastInst->getOperand(0).getMachineBasicBlock();
550 // If the block ends with two X86::JMPs, handle it. The second one is not
551 // executed, so remove it.
552 if (SecondLastInst->getOpcode() == X86::JMP &&
553 LastInst->getOpcode() == X86::JMP) {
554 TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
556 I->eraseFromParent();
560 // Otherwise, can't handle this.
564 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
565 MachineBasicBlock::iterator I = MBB.end();
566 if (I == MBB.begin()) return 0;
568 if (I->getOpcode() != X86::JMP &&
569 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
572 // Remove the branch.
573 I->eraseFromParent();
577 if (I == MBB.begin()) return 1;
579 if (GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
582 // Remove the branch.
583 I->eraseFromParent();
588 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
589 MachineBasicBlock *FBB,
590 const std::vector<MachineOperand> &Cond) const {
591 // Shouldn't be a fall through.
592 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
593 assert((Cond.size() == 1 || Cond.size() == 0) &&
594 "X86 branch conditions have one component!");
596 if (FBB == 0) { // One way branch.
598 // Unconditional branch?
599 BuildMI(&MBB, get(X86::JMP)).addMBB(TBB);
601 // Conditional branch.
602 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
603 BuildMI(&MBB, get(Opc)).addMBB(TBB);
608 // Two-way Conditional branch.
609 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
610 BuildMI(&MBB, get(Opc)).addMBB(TBB);
611 BuildMI(&MBB, get(X86::JMP)).addMBB(FBB);
615 bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
616 if (MBB.empty()) return false;
618 switch (MBB.back().getOpcode()) {
619 case X86::RET: // Return.
624 case X86::JMP: // Uncond branch.
625 case X86::JMP32r: // Indirect branch.
626 case X86::JMP64r: // Indirect branch (64-bit).
627 case X86::JMP32m: // Indirect branch through mem.
628 case X86::JMP64m: // Indirect branch through mem (64-bit).
630 default: return false;
635 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
636 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
637 Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm()));
641 const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
642 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
643 if (Subtarget->is64Bit())
644 return &X86::GR64RegClass;
646 return &X86::GR32RegClass;