1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/LiveVariables.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Target/TargetAsmInfo.h"
36 NoFusing("disable-spill-fusing",
37 cl::desc("Disable fusing of spill code into instructions"));
39 PrintFailedFusing("print-failed-fuse-candidates",
40 cl::desc("Print instructions that the allocator wants to"
41 " fuse, but the X86 backend currently can't"),
44 ReMatPICStubLoad("remat-pic-stub-load",
45 cl::desc("Re-materialize load from stub in PIC mode"),
46 cl::init(false), cl::Hidden);
49 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
50 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
51 TM(tm), RI(tm, *this) {
52 SmallVector<unsigned,16> AmbEntries;
53 static const unsigned OpTbl2Addr[][2] = {
54 { X86::ADC32ri, X86::ADC32mi },
55 { X86::ADC32ri8, X86::ADC32mi8 },
56 { X86::ADC32rr, X86::ADC32mr },
57 { X86::ADC64ri32, X86::ADC64mi32 },
58 { X86::ADC64ri8, X86::ADC64mi8 },
59 { X86::ADC64rr, X86::ADC64mr },
60 { X86::ADD16ri, X86::ADD16mi },
61 { X86::ADD16ri8, X86::ADD16mi8 },
62 { X86::ADD16rr, X86::ADD16mr },
63 { X86::ADD32ri, X86::ADD32mi },
64 { X86::ADD32ri8, X86::ADD32mi8 },
65 { X86::ADD32rr, X86::ADD32mr },
66 { X86::ADD64ri32, X86::ADD64mi32 },
67 { X86::ADD64ri8, X86::ADD64mi8 },
68 { X86::ADD64rr, X86::ADD64mr },
69 { X86::ADD8ri, X86::ADD8mi },
70 { X86::ADD8rr, X86::ADD8mr },
71 { X86::AND16ri, X86::AND16mi },
72 { X86::AND16ri8, X86::AND16mi8 },
73 { X86::AND16rr, X86::AND16mr },
74 { X86::AND32ri, X86::AND32mi },
75 { X86::AND32ri8, X86::AND32mi8 },
76 { X86::AND32rr, X86::AND32mr },
77 { X86::AND64ri32, X86::AND64mi32 },
78 { X86::AND64ri8, X86::AND64mi8 },
79 { X86::AND64rr, X86::AND64mr },
80 { X86::AND8ri, X86::AND8mi },
81 { X86::AND8rr, X86::AND8mr },
82 { X86::DEC16r, X86::DEC16m },
83 { X86::DEC32r, X86::DEC32m },
84 { X86::DEC64_16r, X86::DEC64_16m },
85 { X86::DEC64_32r, X86::DEC64_32m },
86 { X86::DEC64r, X86::DEC64m },
87 { X86::DEC8r, X86::DEC8m },
88 { X86::INC16r, X86::INC16m },
89 { X86::INC32r, X86::INC32m },
90 { X86::INC64_16r, X86::INC64_16m },
91 { X86::INC64_32r, X86::INC64_32m },
92 { X86::INC64r, X86::INC64m },
93 { X86::INC8r, X86::INC8m },
94 { X86::NEG16r, X86::NEG16m },
95 { X86::NEG32r, X86::NEG32m },
96 { X86::NEG64r, X86::NEG64m },
97 { X86::NEG8r, X86::NEG8m },
98 { X86::NOT16r, X86::NOT16m },
99 { X86::NOT32r, X86::NOT32m },
100 { X86::NOT64r, X86::NOT64m },
101 { X86::NOT8r, X86::NOT8m },
102 { X86::OR16ri, X86::OR16mi },
103 { X86::OR16ri8, X86::OR16mi8 },
104 { X86::OR16rr, X86::OR16mr },
105 { X86::OR32ri, X86::OR32mi },
106 { X86::OR32ri8, X86::OR32mi8 },
107 { X86::OR32rr, X86::OR32mr },
108 { X86::OR64ri32, X86::OR64mi32 },
109 { X86::OR64ri8, X86::OR64mi8 },
110 { X86::OR64rr, X86::OR64mr },
111 { X86::OR8ri, X86::OR8mi },
112 { X86::OR8rr, X86::OR8mr },
113 { X86::ROL16r1, X86::ROL16m1 },
114 { X86::ROL16rCL, X86::ROL16mCL },
115 { X86::ROL16ri, X86::ROL16mi },
116 { X86::ROL32r1, X86::ROL32m1 },
117 { X86::ROL32rCL, X86::ROL32mCL },
118 { X86::ROL32ri, X86::ROL32mi },
119 { X86::ROL64r1, X86::ROL64m1 },
120 { X86::ROL64rCL, X86::ROL64mCL },
121 { X86::ROL64ri, X86::ROL64mi },
122 { X86::ROL8r1, X86::ROL8m1 },
123 { X86::ROL8rCL, X86::ROL8mCL },
124 { X86::ROL8ri, X86::ROL8mi },
125 { X86::ROR16r1, X86::ROR16m1 },
126 { X86::ROR16rCL, X86::ROR16mCL },
127 { X86::ROR16ri, X86::ROR16mi },
128 { X86::ROR32r1, X86::ROR32m1 },
129 { X86::ROR32rCL, X86::ROR32mCL },
130 { X86::ROR32ri, X86::ROR32mi },
131 { X86::ROR64r1, X86::ROR64m1 },
132 { X86::ROR64rCL, X86::ROR64mCL },
133 { X86::ROR64ri, X86::ROR64mi },
134 { X86::ROR8r1, X86::ROR8m1 },
135 { X86::ROR8rCL, X86::ROR8mCL },
136 { X86::ROR8ri, X86::ROR8mi },
137 { X86::SAR16r1, X86::SAR16m1 },
138 { X86::SAR16rCL, X86::SAR16mCL },
139 { X86::SAR16ri, X86::SAR16mi },
140 { X86::SAR32r1, X86::SAR32m1 },
141 { X86::SAR32rCL, X86::SAR32mCL },
142 { X86::SAR32ri, X86::SAR32mi },
143 { X86::SAR64r1, X86::SAR64m1 },
144 { X86::SAR64rCL, X86::SAR64mCL },
145 { X86::SAR64ri, X86::SAR64mi },
146 { X86::SAR8r1, X86::SAR8m1 },
147 { X86::SAR8rCL, X86::SAR8mCL },
148 { X86::SAR8ri, X86::SAR8mi },
149 { X86::SBB32ri, X86::SBB32mi },
150 { X86::SBB32ri8, X86::SBB32mi8 },
151 { X86::SBB32rr, X86::SBB32mr },
152 { X86::SBB64ri32, X86::SBB64mi32 },
153 { X86::SBB64ri8, X86::SBB64mi8 },
154 { X86::SBB64rr, X86::SBB64mr },
155 { X86::SHL16rCL, X86::SHL16mCL },
156 { X86::SHL16ri, X86::SHL16mi },
157 { X86::SHL32rCL, X86::SHL32mCL },
158 { X86::SHL32ri, X86::SHL32mi },
159 { X86::SHL64rCL, X86::SHL64mCL },
160 { X86::SHL64ri, X86::SHL64mi },
161 { X86::SHL8rCL, X86::SHL8mCL },
162 { X86::SHL8ri, X86::SHL8mi },
163 { X86::SHLD16rrCL, X86::SHLD16mrCL },
164 { X86::SHLD16rri8, X86::SHLD16mri8 },
165 { X86::SHLD32rrCL, X86::SHLD32mrCL },
166 { X86::SHLD32rri8, X86::SHLD32mri8 },
167 { X86::SHLD64rrCL, X86::SHLD64mrCL },
168 { X86::SHLD64rri8, X86::SHLD64mri8 },
169 { X86::SHR16r1, X86::SHR16m1 },
170 { X86::SHR16rCL, X86::SHR16mCL },
171 { X86::SHR16ri, X86::SHR16mi },
172 { X86::SHR32r1, X86::SHR32m1 },
173 { X86::SHR32rCL, X86::SHR32mCL },
174 { X86::SHR32ri, X86::SHR32mi },
175 { X86::SHR64r1, X86::SHR64m1 },
176 { X86::SHR64rCL, X86::SHR64mCL },
177 { X86::SHR64ri, X86::SHR64mi },
178 { X86::SHR8r1, X86::SHR8m1 },
179 { X86::SHR8rCL, X86::SHR8mCL },
180 { X86::SHR8ri, X86::SHR8mi },
181 { X86::SHRD16rrCL, X86::SHRD16mrCL },
182 { X86::SHRD16rri8, X86::SHRD16mri8 },
183 { X86::SHRD32rrCL, X86::SHRD32mrCL },
184 { X86::SHRD32rri8, X86::SHRD32mri8 },
185 { X86::SHRD64rrCL, X86::SHRD64mrCL },
186 { X86::SHRD64rri8, X86::SHRD64mri8 },
187 { X86::SUB16ri, X86::SUB16mi },
188 { X86::SUB16ri8, X86::SUB16mi8 },
189 { X86::SUB16rr, X86::SUB16mr },
190 { X86::SUB32ri, X86::SUB32mi },
191 { X86::SUB32ri8, X86::SUB32mi8 },
192 { X86::SUB32rr, X86::SUB32mr },
193 { X86::SUB64ri32, X86::SUB64mi32 },
194 { X86::SUB64ri8, X86::SUB64mi8 },
195 { X86::SUB64rr, X86::SUB64mr },
196 { X86::SUB8ri, X86::SUB8mi },
197 { X86::SUB8rr, X86::SUB8mr },
198 { X86::XOR16ri, X86::XOR16mi },
199 { X86::XOR16ri8, X86::XOR16mi8 },
200 { X86::XOR16rr, X86::XOR16mr },
201 { X86::XOR32ri, X86::XOR32mi },
202 { X86::XOR32ri8, X86::XOR32mi8 },
203 { X86::XOR32rr, X86::XOR32mr },
204 { X86::XOR64ri32, X86::XOR64mi32 },
205 { X86::XOR64ri8, X86::XOR64mi8 },
206 { X86::XOR64rr, X86::XOR64mr },
207 { X86::XOR8ri, X86::XOR8mi },
208 { X86::XOR8rr, X86::XOR8mr }
211 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
212 unsigned RegOp = OpTbl2Addr[i][0];
213 unsigned MemOp = OpTbl2Addr[i][1];
214 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
216 assert(false && "Duplicated entries?");
217 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); // Index 0,folded load and store
218 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
219 std::make_pair(RegOp,
221 AmbEntries.push_back(MemOp);
224 // If the third value is 1, then it's folding either a load or a store.
225 static const unsigned OpTbl0[][3] = {
226 { X86::CALL32r, X86::CALL32m, 1 },
227 { X86::CALL64r, X86::CALL64m, 1 },
228 { X86::CMP16ri, X86::CMP16mi, 1 },
229 { X86::CMP16ri8, X86::CMP16mi8, 1 },
230 { X86::CMP16rr, X86::CMP16mr, 1 },
231 { X86::CMP32ri, X86::CMP32mi, 1 },
232 { X86::CMP32ri8, X86::CMP32mi8, 1 },
233 { X86::CMP32rr, X86::CMP32mr, 1 },
234 { X86::CMP64ri32, X86::CMP64mi32, 1 },
235 { X86::CMP64ri8, X86::CMP64mi8, 1 },
236 { X86::CMP64rr, X86::CMP64mr, 1 },
237 { X86::CMP8ri, X86::CMP8mi, 1 },
238 { X86::CMP8rr, X86::CMP8mr, 1 },
239 { X86::DIV16r, X86::DIV16m, 1 },
240 { X86::DIV32r, X86::DIV32m, 1 },
241 { X86::DIV64r, X86::DIV64m, 1 },
242 { X86::DIV8r, X86::DIV8m, 1 },
243 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0 },
244 { X86::FsMOVAPDrr, X86::MOVSDmr, 0 },
245 { X86::FsMOVAPSrr, X86::MOVSSmr, 0 },
246 { X86::IDIV16r, X86::IDIV16m, 1 },
247 { X86::IDIV32r, X86::IDIV32m, 1 },
248 { X86::IDIV64r, X86::IDIV64m, 1 },
249 { X86::IDIV8r, X86::IDIV8m, 1 },
250 { X86::IMUL16r, X86::IMUL16m, 1 },
251 { X86::IMUL32r, X86::IMUL32m, 1 },
252 { X86::IMUL64r, X86::IMUL64m, 1 },
253 { X86::IMUL8r, X86::IMUL8m, 1 },
254 { X86::JMP32r, X86::JMP32m, 1 },
255 { X86::JMP64r, X86::JMP64m, 1 },
256 { X86::MOV16ri, X86::MOV16mi, 0 },
257 { X86::MOV16rr, X86::MOV16mr, 0 },
258 { X86::MOV16to16_, X86::MOV16_mr, 0 },
259 { X86::MOV32ri, X86::MOV32mi, 0 },
260 { X86::MOV32rr, X86::MOV32mr, 0 },
261 { X86::MOV32to32_, X86::MOV32_mr, 0 },
262 { X86::MOV64ri32, X86::MOV64mi32, 0 },
263 { X86::MOV64rr, X86::MOV64mr, 0 },
264 { X86::MOV8ri, X86::MOV8mi, 0 },
265 { X86::MOV8rr, X86::MOV8mr, 0 },
266 { X86::MOVAPDrr, X86::MOVAPDmr, 0 },
267 { X86::MOVAPSrr, X86::MOVAPSmr, 0 },
268 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0 },
269 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0 },
270 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0 },
271 { X86::MOVSDrr, X86::MOVSDmr, 0 },
272 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0 },
273 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0 },
274 { X86::MOVSSrr, X86::MOVSSmr, 0 },
275 { X86::MOVUPDrr, X86::MOVUPDmr, 0 },
276 { X86::MOVUPSrr, X86::MOVUPSmr, 0 },
277 { X86::MUL16r, X86::MUL16m, 1 },
278 { X86::MUL32r, X86::MUL32m, 1 },
279 { X86::MUL64r, X86::MUL64m, 1 },
280 { X86::MUL8r, X86::MUL8m, 1 },
281 { X86::SETAEr, X86::SETAEm, 0 },
282 { X86::SETAr, X86::SETAm, 0 },
283 { X86::SETBEr, X86::SETBEm, 0 },
284 { X86::SETBr, X86::SETBm, 0 },
285 { X86::SETCr, X86::SETCm, 0 },
286 { X86::SETEr, X86::SETEm, 0 },
287 { X86::SETGEr, X86::SETGEm, 0 },
288 { X86::SETGr, X86::SETGm, 0 },
289 { X86::SETLEr, X86::SETLEm, 0 },
290 { X86::SETLr, X86::SETLm, 0 },
291 { X86::SETNCr, X86::SETNCm, 0 },
292 { X86::SETNEr, X86::SETNEm, 0 },
293 { X86::SETNOr, X86::SETNOm, 0 },
294 { X86::SETNPr, X86::SETNPm, 0 },
295 { X86::SETNSr, X86::SETNSm, 0 },
296 { X86::SETOr, X86::SETOm, 0 },
297 { X86::SETPr, X86::SETPm, 0 },
298 { X86::SETSr, X86::SETSm, 0 },
299 { X86::TAILJMPr, X86::TAILJMPm, 1 },
300 { X86::TEST16ri, X86::TEST16mi, 1 },
301 { X86::TEST32ri, X86::TEST32mi, 1 },
302 { X86::TEST64ri32, X86::TEST64mi32, 1 },
303 { X86::TEST8ri, X86::TEST8mi, 1 }
306 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
307 unsigned RegOp = OpTbl0[i][0];
308 unsigned MemOp = OpTbl0[i][1];
309 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
311 assert(false && "Duplicated entries?");
312 unsigned FoldedLoad = OpTbl0[i][2];
313 // Index 0, folded load or store.
314 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
315 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
316 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
317 std::make_pair(RegOp, AuxInfo))).second)
318 AmbEntries.push_back(MemOp);
321 static const unsigned OpTbl1[][2] = {
322 { X86::CMP16rr, X86::CMP16rm },
323 { X86::CMP32rr, X86::CMP32rm },
324 { X86::CMP64rr, X86::CMP64rm },
325 { X86::CMP8rr, X86::CMP8rm },
326 { X86::CVTSD2SSrr, X86::CVTSD2SSrm },
327 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm },
328 { X86::CVTSI2SDrr, X86::CVTSI2SDrm },
329 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm },
330 { X86::CVTSI2SSrr, X86::CVTSI2SSrm },
331 { X86::CVTSS2SDrr, X86::CVTSS2SDrm },
332 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm },
333 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm },
334 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm },
335 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm },
336 { X86::FsMOVAPDrr, X86::MOVSDrm },
337 { X86::FsMOVAPSrr, X86::MOVSSrm },
338 { X86::IMUL16rri, X86::IMUL16rmi },
339 { X86::IMUL16rri8, X86::IMUL16rmi8 },
340 { X86::IMUL32rri, X86::IMUL32rmi },
341 { X86::IMUL32rri8, X86::IMUL32rmi8 },
342 { X86::IMUL64rri32, X86::IMUL64rmi32 },
343 { X86::IMUL64rri8, X86::IMUL64rmi8 },
344 { X86::Int_CMPSDrr, X86::Int_CMPSDrm },
345 { X86::Int_CMPSSrr, X86::Int_CMPSSrm },
346 { X86::Int_COMISDrr, X86::Int_COMISDrm },
347 { X86::Int_COMISSrr, X86::Int_COMISSrm },
348 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm },
349 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm },
350 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm },
351 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm },
352 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm },
353 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm },
354 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
355 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm },
356 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm },
357 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
358 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm },
359 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
360 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm },
361 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm },
362 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
363 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm },
364 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
365 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
366 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
367 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
368 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
369 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
370 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm },
371 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm },
372 { X86::MOV16rr, X86::MOV16rm },
373 { X86::MOV16to16_, X86::MOV16_rm },
374 { X86::MOV32rr, X86::MOV32rm },
375 { X86::MOV32to32_, X86::MOV32_rm },
376 { X86::MOV64rr, X86::MOV64rm },
377 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm },
378 { X86::MOV64toSDrr, X86::MOV64toSDrm },
379 { X86::MOV8rr, X86::MOV8rm },
380 { X86::MOVAPDrr, X86::MOVAPDrm },
381 { X86::MOVAPSrr, X86::MOVAPSrm },
382 { X86::MOVDDUPrr, X86::MOVDDUPrm },
383 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm },
384 { X86::MOVDI2SSrr, X86::MOVDI2SSrm },
385 { X86::MOVSD2PDrr, X86::MOVSD2PDrm },
386 { X86::MOVSDrr, X86::MOVSDrm },
387 { X86::MOVSHDUPrr, X86::MOVSHDUPrm },
388 { X86::MOVSLDUPrr, X86::MOVSLDUPrm },
389 { X86::MOVSS2PSrr, X86::MOVSS2PSrm },
390 { X86::MOVSSrr, X86::MOVSSrm },
391 { X86::MOVSX16rr8, X86::MOVSX16rm8 },
392 { X86::MOVSX32rr16, X86::MOVSX32rm16 },
393 { X86::MOVSX32rr8, X86::MOVSX32rm8 },
394 { X86::MOVSX64rr16, X86::MOVSX64rm16 },
395 { X86::MOVSX64rr32, X86::MOVSX64rm32 },
396 { X86::MOVSX64rr8, X86::MOVSX64rm8 },
397 { X86::MOVUPDrr, X86::MOVUPDrm },
398 { X86::MOVUPSrr, X86::MOVUPSrm },
399 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm },
400 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm },
401 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm },
402 { X86::MOVZX16rr8, X86::MOVZX16rm8 },
403 { X86::MOVZX32rr16, X86::MOVZX32rm16 },
404 { X86::MOVZX32rr8, X86::MOVZX32rm8 },
405 { X86::MOVZX64rr16, X86::MOVZX64rm16 },
406 { X86::MOVZX64rr32, X86::MOVZX64rm32 },
407 { X86::MOVZX64rr8, X86::MOVZX64rm8 },
408 { X86::PSHUFDri, X86::PSHUFDmi },
409 { X86::PSHUFHWri, X86::PSHUFHWmi },
410 { X86::PSHUFLWri, X86::PSHUFLWmi },
411 { X86::RCPPSr, X86::RCPPSm },
412 { X86::RCPPSr_Int, X86::RCPPSm_Int },
413 { X86::RSQRTPSr, X86::RSQRTPSm },
414 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int },
415 { X86::RSQRTSSr, X86::RSQRTSSm },
416 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int },
417 { X86::SQRTPDr, X86::SQRTPDm },
418 { X86::SQRTPDr_Int, X86::SQRTPDm_Int },
419 { X86::SQRTPSr, X86::SQRTPSm },
420 { X86::SQRTPSr_Int, X86::SQRTPSm_Int },
421 { X86::SQRTSDr, X86::SQRTSDm },
422 { X86::SQRTSDr_Int, X86::SQRTSDm_Int },
423 { X86::SQRTSSr, X86::SQRTSSm },
424 { X86::SQRTSSr_Int, X86::SQRTSSm_Int },
425 { X86::TEST16rr, X86::TEST16rm },
426 { X86::TEST32rr, X86::TEST32rm },
427 { X86::TEST64rr, X86::TEST64rm },
428 { X86::TEST8rr, X86::TEST8rm },
429 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
430 { X86::UCOMISDrr, X86::UCOMISDrm },
431 { X86::UCOMISSrr, X86::UCOMISSrm }
434 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
435 unsigned RegOp = OpTbl1[i][0];
436 unsigned MemOp = OpTbl1[i][1];
437 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
439 assert(false && "Duplicated entries?");
440 unsigned AuxInfo = 1 | (1 << 4); // Index 1, folded load
441 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
442 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
443 std::make_pair(RegOp, AuxInfo))).second)
444 AmbEntries.push_back(MemOp);
447 static const unsigned OpTbl2[][2] = {
448 { X86::ADC32rr, X86::ADC32rm },
449 { X86::ADC64rr, X86::ADC64rm },
450 { X86::ADD16rr, X86::ADD16rm },
451 { X86::ADD32rr, X86::ADD32rm },
452 { X86::ADD64rr, X86::ADD64rm },
453 { X86::ADD8rr, X86::ADD8rm },
454 { X86::ADDPDrr, X86::ADDPDrm },
455 { X86::ADDPSrr, X86::ADDPSrm },
456 { X86::ADDSDrr, X86::ADDSDrm },
457 { X86::ADDSSrr, X86::ADDSSrm },
458 { X86::ADDSUBPDrr, X86::ADDSUBPDrm },
459 { X86::ADDSUBPSrr, X86::ADDSUBPSrm },
460 { X86::AND16rr, X86::AND16rm },
461 { X86::AND32rr, X86::AND32rm },
462 { X86::AND64rr, X86::AND64rm },
463 { X86::AND8rr, X86::AND8rm },
464 { X86::ANDNPDrr, X86::ANDNPDrm },
465 { X86::ANDNPSrr, X86::ANDNPSrm },
466 { X86::ANDPDrr, X86::ANDPDrm },
467 { X86::ANDPSrr, X86::ANDPSrm },
468 { X86::CMOVA16rr, X86::CMOVA16rm },
469 { X86::CMOVA32rr, X86::CMOVA32rm },
470 { X86::CMOVA64rr, X86::CMOVA64rm },
471 { X86::CMOVAE16rr, X86::CMOVAE16rm },
472 { X86::CMOVAE32rr, X86::CMOVAE32rm },
473 { X86::CMOVAE64rr, X86::CMOVAE64rm },
474 { X86::CMOVB16rr, X86::CMOVB16rm },
475 { X86::CMOVB32rr, X86::CMOVB32rm },
476 { X86::CMOVB64rr, X86::CMOVB64rm },
477 { X86::CMOVBE16rr, X86::CMOVBE16rm },
478 { X86::CMOVBE32rr, X86::CMOVBE32rm },
479 { X86::CMOVBE64rr, X86::CMOVBE64rm },
480 { X86::CMOVE16rr, X86::CMOVE16rm },
481 { X86::CMOVE32rr, X86::CMOVE32rm },
482 { X86::CMOVE64rr, X86::CMOVE64rm },
483 { X86::CMOVG16rr, X86::CMOVG16rm },
484 { X86::CMOVG32rr, X86::CMOVG32rm },
485 { X86::CMOVG64rr, X86::CMOVG64rm },
486 { X86::CMOVGE16rr, X86::CMOVGE16rm },
487 { X86::CMOVGE32rr, X86::CMOVGE32rm },
488 { X86::CMOVGE64rr, X86::CMOVGE64rm },
489 { X86::CMOVL16rr, X86::CMOVL16rm },
490 { X86::CMOVL32rr, X86::CMOVL32rm },
491 { X86::CMOVL64rr, X86::CMOVL64rm },
492 { X86::CMOVLE16rr, X86::CMOVLE16rm },
493 { X86::CMOVLE32rr, X86::CMOVLE32rm },
494 { X86::CMOVLE64rr, X86::CMOVLE64rm },
495 { X86::CMOVNE16rr, X86::CMOVNE16rm },
496 { X86::CMOVNE32rr, X86::CMOVNE32rm },
497 { X86::CMOVNE64rr, X86::CMOVNE64rm },
498 { X86::CMOVNP16rr, X86::CMOVNP16rm },
499 { X86::CMOVNP32rr, X86::CMOVNP32rm },
500 { X86::CMOVNP64rr, X86::CMOVNP64rm },
501 { X86::CMOVNS16rr, X86::CMOVNS16rm },
502 { X86::CMOVNS32rr, X86::CMOVNS32rm },
503 { X86::CMOVNS64rr, X86::CMOVNS64rm },
504 { X86::CMOVP16rr, X86::CMOVP16rm },
505 { X86::CMOVP32rr, X86::CMOVP32rm },
506 { X86::CMOVP64rr, X86::CMOVP64rm },
507 { X86::CMOVS16rr, X86::CMOVS16rm },
508 { X86::CMOVS32rr, X86::CMOVS32rm },
509 { X86::CMOVS64rr, X86::CMOVS64rm },
510 { X86::CMPPDrri, X86::CMPPDrmi },
511 { X86::CMPPSrri, X86::CMPPSrmi },
512 { X86::CMPSDrr, X86::CMPSDrm },
513 { X86::CMPSSrr, X86::CMPSSrm },
514 { X86::DIVPDrr, X86::DIVPDrm },
515 { X86::DIVPSrr, X86::DIVPSrm },
516 { X86::DIVSDrr, X86::DIVSDrm },
517 { X86::DIVSSrr, X86::DIVSSrm },
518 { X86::FsANDNPDrr, X86::FsANDNPDrm },
519 { X86::FsANDNPSrr, X86::FsANDNPSrm },
520 { X86::FsANDPDrr, X86::FsANDPDrm },
521 { X86::FsANDPSrr, X86::FsANDPSrm },
522 { X86::FsORPDrr, X86::FsORPDrm },
523 { X86::FsORPSrr, X86::FsORPSrm },
524 { X86::FsXORPDrr, X86::FsXORPDrm },
525 { X86::FsXORPSrr, X86::FsXORPSrm },
526 { X86::HADDPDrr, X86::HADDPDrm },
527 { X86::HADDPSrr, X86::HADDPSrm },
528 { X86::HSUBPDrr, X86::HSUBPDrm },
529 { X86::HSUBPSrr, X86::HSUBPSrm },
530 { X86::IMUL16rr, X86::IMUL16rm },
531 { X86::IMUL32rr, X86::IMUL32rm },
532 { X86::IMUL64rr, X86::IMUL64rm },
533 { X86::MAXPDrr, X86::MAXPDrm },
534 { X86::MAXPDrr_Int, X86::MAXPDrm_Int },
535 { X86::MAXPSrr, X86::MAXPSrm },
536 { X86::MAXPSrr_Int, X86::MAXPSrm_Int },
537 { X86::MAXSDrr, X86::MAXSDrm },
538 { X86::MAXSDrr_Int, X86::MAXSDrm_Int },
539 { X86::MAXSSrr, X86::MAXSSrm },
540 { X86::MAXSSrr_Int, X86::MAXSSrm_Int },
541 { X86::MINPDrr, X86::MINPDrm },
542 { X86::MINPDrr_Int, X86::MINPDrm_Int },
543 { X86::MINPSrr, X86::MINPSrm },
544 { X86::MINPSrr_Int, X86::MINPSrm_Int },
545 { X86::MINSDrr, X86::MINSDrm },
546 { X86::MINSDrr_Int, X86::MINSDrm_Int },
547 { X86::MINSSrr, X86::MINSSrm },
548 { X86::MINSSrr_Int, X86::MINSSrm_Int },
549 { X86::MULPDrr, X86::MULPDrm },
550 { X86::MULPSrr, X86::MULPSrm },
551 { X86::MULSDrr, X86::MULSDrm },
552 { X86::MULSSrr, X86::MULSSrm },
553 { X86::OR16rr, X86::OR16rm },
554 { X86::OR32rr, X86::OR32rm },
555 { X86::OR64rr, X86::OR64rm },
556 { X86::OR8rr, X86::OR8rm },
557 { X86::ORPDrr, X86::ORPDrm },
558 { X86::ORPSrr, X86::ORPSrm },
559 { X86::PACKSSDWrr, X86::PACKSSDWrm },
560 { X86::PACKSSWBrr, X86::PACKSSWBrm },
561 { X86::PACKUSWBrr, X86::PACKUSWBrm },
562 { X86::PADDBrr, X86::PADDBrm },
563 { X86::PADDDrr, X86::PADDDrm },
564 { X86::PADDQrr, X86::PADDQrm },
565 { X86::PADDSBrr, X86::PADDSBrm },
566 { X86::PADDSWrr, X86::PADDSWrm },
567 { X86::PADDWrr, X86::PADDWrm },
568 { X86::PANDNrr, X86::PANDNrm },
569 { X86::PANDrr, X86::PANDrm },
570 { X86::PAVGBrr, X86::PAVGBrm },
571 { X86::PAVGWrr, X86::PAVGWrm },
572 { X86::PCMPEQBrr, X86::PCMPEQBrm },
573 { X86::PCMPEQDrr, X86::PCMPEQDrm },
574 { X86::PCMPEQWrr, X86::PCMPEQWrm },
575 { X86::PCMPGTBrr, X86::PCMPGTBrm },
576 { X86::PCMPGTDrr, X86::PCMPGTDrm },
577 { X86::PCMPGTWrr, X86::PCMPGTWrm },
578 { X86::PINSRWrri, X86::PINSRWrmi },
579 { X86::PMADDWDrr, X86::PMADDWDrm },
580 { X86::PMAXSWrr, X86::PMAXSWrm },
581 { X86::PMAXUBrr, X86::PMAXUBrm },
582 { X86::PMINSWrr, X86::PMINSWrm },
583 { X86::PMINUBrr, X86::PMINUBrm },
584 { X86::PMULDQrr, X86::PMULDQrm },
585 { X86::PMULHUWrr, X86::PMULHUWrm },
586 { X86::PMULHWrr, X86::PMULHWrm },
587 { X86::PMULLDrr, X86::PMULLDrm },
588 { X86::PMULLDrr_int, X86::PMULLDrm_int },
589 { X86::PMULLWrr, X86::PMULLWrm },
590 { X86::PMULUDQrr, X86::PMULUDQrm },
591 { X86::PORrr, X86::PORrm },
592 { X86::PSADBWrr, X86::PSADBWrm },
593 { X86::PSLLDrr, X86::PSLLDrm },
594 { X86::PSLLQrr, X86::PSLLQrm },
595 { X86::PSLLWrr, X86::PSLLWrm },
596 { X86::PSRADrr, X86::PSRADrm },
597 { X86::PSRAWrr, X86::PSRAWrm },
598 { X86::PSRLDrr, X86::PSRLDrm },
599 { X86::PSRLQrr, X86::PSRLQrm },
600 { X86::PSRLWrr, X86::PSRLWrm },
601 { X86::PSUBBrr, X86::PSUBBrm },
602 { X86::PSUBDrr, X86::PSUBDrm },
603 { X86::PSUBSBrr, X86::PSUBSBrm },
604 { X86::PSUBSWrr, X86::PSUBSWrm },
605 { X86::PSUBWrr, X86::PSUBWrm },
606 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm },
607 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm },
608 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm },
609 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm },
610 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm },
611 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm },
612 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm },
613 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm },
614 { X86::PXORrr, X86::PXORrm },
615 { X86::SBB32rr, X86::SBB32rm },
616 { X86::SBB64rr, X86::SBB64rm },
617 { X86::SHUFPDrri, X86::SHUFPDrmi },
618 { X86::SHUFPSrri, X86::SHUFPSrmi },
619 { X86::SUB16rr, X86::SUB16rm },
620 { X86::SUB32rr, X86::SUB32rm },
621 { X86::SUB64rr, X86::SUB64rm },
622 { X86::SUB8rr, X86::SUB8rm },
623 { X86::SUBPDrr, X86::SUBPDrm },
624 { X86::SUBPSrr, X86::SUBPSrm },
625 { X86::SUBSDrr, X86::SUBSDrm },
626 { X86::SUBSSrr, X86::SUBSSrm },
627 // FIXME: TEST*rr -> swapped operand of TEST*mr.
628 { X86::UNPCKHPDrr, X86::UNPCKHPDrm },
629 { X86::UNPCKHPSrr, X86::UNPCKHPSrm },
630 { X86::UNPCKLPDrr, X86::UNPCKLPDrm },
631 { X86::UNPCKLPSrr, X86::UNPCKLPSrm },
632 { X86::XOR16rr, X86::XOR16rm },
633 { X86::XOR32rr, X86::XOR32rm },
634 { X86::XOR64rr, X86::XOR64rm },
635 { X86::XOR8rr, X86::XOR8rm },
636 { X86::XORPDrr, X86::XORPDrm },
637 { X86::XORPSrr, X86::XORPSrm }
640 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
641 unsigned RegOp = OpTbl2[i][0];
642 unsigned MemOp = OpTbl2[i][1];
643 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
645 assert(false && "Duplicated entries?");
646 unsigned AuxInfo = 2 | (1 << 4); // Index 1, folded load
647 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
648 std::make_pair(RegOp, AuxInfo))).second)
649 AmbEntries.push_back(MemOp);
652 // Remove ambiguous entries.
653 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
656 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
658 unsigned& destReg) const {
659 switch (MI.getOpcode()) {
666 case X86::MOV16to16_:
667 case X86::MOV32to32_:
671 // FP Stack register class copies
672 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
673 case X86::MOV_Fp3264: case X86::MOV_Fp3280:
674 case X86::MOV_Fp6432: case X86::MOV_Fp8032:
676 case X86::FsMOVAPSrr:
677 case X86::FsMOVAPDrr:
680 case X86::MOVSS2PSrr:
681 case X86::MOVSD2PDrr:
682 case X86::MOVPS2SSrr:
683 case X86::MOVPD2SDrr:
684 case X86::MMX_MOVD64rr:
685 case X86::MMX_MOVQ64rr:
686 assert(MI.getNumOperands() >= 2 &&
687 MI.getOperand(0).isReg() &&
688 MI.getOperand(1).isReg() &&
689 "invalid register-register move instruction");
690 sourceReg = MI.getOperand(1).getReg();
691 destReg = MI.getOperand(0).getReg();
696 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
697 int &FrameIndex) const {
698 switch (MI->getOpcode()) {
711 case X86::MMX_MOVD64rm:
712 case X86::MMX_MOVQ64rm:
713 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
714 MI->getOperand(3).isReg() && MI->getOperand(4).isImm() &&
715 MI->getOperand(2).getImm() == 1 &&
716 MI->getOperand(3).getReg() == 0 &&
717 MI->getOperand(4).getImm() == 0) {
718 FrameIndex = MI->getOperand(1).getIndex();
719 return MI->getOperand(0).getReg();
726 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
727 int &FrameIndex) const {
728 switch (MI->getOpcode()) {
741 case X86::MMX_MOVD64mr:
742 case X86::MMX_MOVQ64mr:
743 case X86::MMX_MOVNTQmr:
744 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
745 MI->getOperand(2).isReg() && MI->getOperand(3).isImm() &&
746 MI->getOperand(1).getImm() == 1 &&
747 MI->getOperand(2).getReg() == 0 &&
748 MI->getOperand(3).getImm() == 0) {
749 FrameIndex = MI->getOperand(0).getIndex();
750 return MI->getOperand(4).getReg();
758 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
760 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
761 bool isPICBase = false;
762 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
763 E = MRI.def_end(); I != E; ++I) {
764 MachineInstr *DefMI = I.getOperand().getParent();
765 if (DefMI->getOpcode() != X86::MOVPC32r)
767 assert(!isPICBase && "More than one PIC base?");
773 /// isGVStub - Return true if the GV requires an extra load to get the
775 static inline bool isGVStub(GlobalValue *GV, X86TargetMachine &TM) {
776 return TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false);
780 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI) const {
781 switch (MI->getOpcode()) {
794 case X86::MMX_MOVD64rm:
795 case X86::MMX_MOVQ64rm: {
796 // Loads from constant pools are trivially rematerializable.
797 if (MI->getOperand(1).isReg() &&
798 MI->getOperand(2).isImm() &&
799 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
800 (MI->getOperand(4).isCPI() ||
801 (MI->getOperand(4).isGlobal() &&
802 isGVStub(MI->getOperand(4).getGlobal(), TM)))) {
803 unsigned BaseReg = MI->getOperand(1).getReg();
806 // Allow re-materialization of PIC load.
807 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
809 const MachineFunction &MF = *MI->getParent()->getParent();
810 const MachineRegisterInfo &MRI = MF.getRegInfo();
811 bool isPICBase = false;
812 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
813 E = MRI.def_end(); I != E; ++I) {
814 MachineInstr *DefMI = I.getOperand().getParent();
815 if (DefMI->getOpcode() != X86::MOVPC32r)
817 assert(!isPICBase && "More than one PIC base?");
827 if (MI->getOperand(2).isImm() &&
828 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
829 !MI->getOperand(4).isReg()) {
830 // lea fi#, lea GV, etc. are all rematerializable.
831 if (!MI->getOperand(1).isReg())
833 unsigned BaseReg = MI->getOperand(1).getReg();
836 // Allow re-materialization of lea PICBase + x.
837 const MachineFunction &MF = *MI->getParent()->getParent();
838 const MachineRegisterInfo &MRI = MF.getRegInfo();
839 return regIsPICBase(BaseReg, MRI);
845 // All other instructions marked M_REMATERIALIZABLE are always trivially
850 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
851 /// would clobber the EFLAGS condition register. Note the result may be
852 /// conservative. If it cannot definitely determine the safety after visiting
853 /// two instructions it assumes it's not safe.
854 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
855 MachineBasicBlock::iterator I) {
856 // It's always safe to clobber EFLAGS at the end of a block.
860 // For compile time consideration, if we are not able to determine the
861 // safety after visiting 2 instructions, we will assume it's not safe.
862 for (unsigned i = 0; i < 2; ++i) {
863 bool SeenDef = false;
864 for (unsigned j = 0, e = I->getNumOperands(); j != e; ++j) {
865 MachineOperand &MO = I->getOperand(j);
868 if (MO.getReg() == X86::EFLAGS) {
876 // This instruction defines EFLAGS, no need to look any further.
880 // If we make it to the end of the block, it's safe to clobber EFLAGS.
885 // Conservative answer.
889 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
890 MachineBasicBlock::iterator I,
892 const MachineInstr *Orig) const {
893 unsigned SubIdx = Orig->getOperand(0).isReg()
894 ? Orig->getOperand(0).getSubReg() : 0;
895 bool ChangeSubIdx = SubIdx != 0;
896 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
897 DestReg = RI.getSubReg(DestReg, SubIdx);
901 // MOV32r0 etc. are implemented with xor which clobbers condition code.
902 // Re-materialize them as movri instructions to avoid side effects.
903 bool Emitted = false;
904 switch (Orig->getOpcode()) {
910 if (!isSafeToClobberEFLAGS(MBB, I)) {
912 switch (Orig->getOpcode()) {
914 case X86::MOV8r0: Opc = X86::MOV8ri; break;
915 case X86::MOV16r0: Opc = X86::MOV16ri; break;
916 case X86::MOV32r0: Opc = X86::MOV32ri; break;
917 case X86::MOV64r0: Opc = X86::MOV64ri32; break;
919 BuildMI(MBB, I, get(Opc), DestReg).addImm(0);
927 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
928 MI->getOperand(0).setReg(DestReg);
933 MachineInstr *NewMI = prior(I);
934 NewMI->getOperand(0).setSubReg(SubIdx);
938 /// isInvariantLoad - Return true if the specified instruction (which is marked
939 /// mayLoad) is loading from a location whose value is invariant across the
940 /// function. For example, loading a value from the constant pool or from
941 /// from the argument area of a function if it does not change. This should
942 /// only return true of *all* loads the instruction does are invariant (if it
943 /// does multiple loads).
944 bool X86InstrInfo::isInvariantLoad(const MachineInstr *MI) const {
945 // This code cares about loads from three cases: constant pool entries,
946 // invariant argument slots, and global stubs. In order to handle these cases
947 // for all of the myriad of X86 instructions, we just scan for a CP/FI/GV
948 // operand and base our analysis on it. This is safe because the address of
949 // none of these three cases is ever used as anything other than a load base
950 // and X86 doesn't have any instructions that load from multiple places.
952 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
953 const MachineOperand &MO = MI->getOperand(i);
954 // Loads from constant pools are trivially invariant.
959 return isGVStub(MO.getGlobal(), TM);
961 // If this is a load from an invariant stack slot, the load is a constant.
963 const MachineFrameInfo &MFI =
964 *MI->getParent()->getParent()->getFrameInfo();
965 int Idx = MO.getIndex();
966 return MFI.isFixedObjectIndex(Idx) && MFI.isImmutableObjectIndex(Idx);
970 // All other instances of these instructions are presumed to have other
975 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
976 /// is not marked dead.
977 static bool hasLiveCondCodeDef(MachineInstr *MI) {
978 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
979 MachineOperand &MO = MI->getOperand(i);
980 if (MO.isReg() && MO.isDef() &&
981 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
988 /// convertToThreeAddress - This method must be implemented by targets that
989 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
990 /// may be able to convert a two-address instruction into a true
991 /// three-address instruction on demand. This allows the X86 target (for
992 /// example) to convert ADD and SHL instructions into LEA instructions if they
993 /// would require register copies due to two-addressness.
995 /// This method returns a null pointer if the transformation cannot be
996 /// performed, otherwise it returns the new instruction.
999 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1000 MachineBasicBlock::iterator &MBBI,
1001 LiveVariables *LV) const {
1002 MachineInstr *MI = MBBI;
1003 MachineFunction &MF = *MI->getParent()->getParent();
1004 // All instructions input are two-addr instructions. Get the known operands.
1005 unsigned Dest = MI->getOperand(0).getReg();
1006 unsigned Src = MI->getOperand(1).getReg();
1007 bool isDead = MI->getOperand(0).isDead();
1008 bool isKill = MI->getOperand(1).isKill();
1010 MachineInstr *NewMI = NULL;
1011 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1012 // we have better subtarget support, enable the 16-bit LEA generation here.
1013 bool DisableLEA16 = true;
1015 unsigned MIOpc = MI->getOpcode();
1017 case X86::SHUFPSrri: {
1018 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1019 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1021 unsigned B = MI->getOperand(1).getReg();
1022 unsigned C = MI->getOperand(2).getReg();
1023 if (B != C) return 0;
1024 unsigned A = MI->getOperand(0).getReg();
1025 unsigned M = MI->getOperand(3).getImm();
1026 NewMI = BuildMI(MF, get(X86::PSHUFDri)).addReg(A, true, false, false, isDead)
1027 .addReg(B, false, false, isKill).addImm(M);
1030 case X86::SHL64ri: {
1031 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1032 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1033 // the flags produced by a shift yet, so this is safe.
1034 unsigned ShAmt = MI->getOperand(2).getImm();
1035 if (ShAmt == 0 || ShAmt >= 4) return 0;
1037 NewMI = BuildMI(MF, get(X86::LEA64r)).addReg(Dest, true, false, false, isDead)
1038 .addReg(0).addImm(1 << ShAmt).addReg(Src, false, false, isKill).addImm(0);
1041 case X86::SHL32ri: {
1042 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1043 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1044 // the flags produced by a shift yet, so this is safe.
1045 unsigned ShAmt = MI->getOperand(2).getImm();
1046 if (ShAmt == 0 || ShAmt >= 4) return 0;
1048 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
1049 X86::LEA64_32r : X86::LEA32r;
1050 NewMI = BuildMI(MF, get(Opc)).addReg(Dest, true, false, false, isDead)
1051 .addReg(0).addImm(1 << ShAmt)
1052 .addReg(Src, false, false, isKill).addImm(0);
1055 case X86::SHL16ri: {
1056 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1057 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1058 // the flags produced by a shift yet, so this is safe.
1059 unsigned ShAmt = MI->getOperand(2).getImm();
1060 if (ShAmt == 0 || ShAmt >= 4) return 0;
1063 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
1064 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1065 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1066 ? X86::LEA64_32r : X86::LEA32r;
1067 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1068 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1070 // Build and insert into an implicit UNDEF value. This is OK because
1071 // well be shifting and then extracting the lower 16-bits.
1072 BuildMI(*MFI, MBBI, get(X86::IMPLICIT_DEF), leaInReg);
1073 MachineInstr *InsMI = BuildMI(*MFI, MBBI, get(X86::INSERT_SUBREG),leaInReg)
1074 .addReg(leaInReg).addReg(Src, false, false, isKill)
1075 .addImm(X86::SUBREG_16BIT);
1077 NewMI = BuildMI(*MFI, MBBI, get(Opc), leaOutReg).addReg(0).addImm(1 << ShAmt)
1078 .addReg(leaInReg, false, false, true).addImm(0);
1080 MachineInstr *ExtMI = BuildMI(*MFI, MBBI, get(X86::EXTRACT_SUBREG))
1081 .addReg(Dest, true, false, false, isDead)
1082 .addReg(leaOutReg, false, false, true).addImm(X86::SUBREG_16BIT);
1084 // Update live variables
1085 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1086 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1088 LV->replaceKillInstruction(Src, MI, InsMI);
1090 LV->replaceKillInstruction(Dest, MI, ExtMI);
1094 NewMI = BuildMI(MF, get(X86::LEA16r)).addReg(Dest, true, false, false, isDead)
1095 .addReg(0).addImm(1 << ShAmt)
1096 .addReg(Src, false, false, isKill).addImm(0);
1101 // The following opcodes also sets the condition code register(s). Only
1102 // convert them to equivalent lea if the condition code register def's
1104 if (hasLiveCondCodeDef(MI))
1107 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1112 case X86::INC64_32r: {
1113 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1114 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1115 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1116 NewMI = addRegOffset(BuildMI(MF, get(Opc))
1117 .addReg(Dest, true, false, false, isDead),
1122 case X86::INC64_16r:
1123 if (DisableLEA16) return 0;
1124 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1125 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r))
1126 .addReg(Dest, true, false, false, isDead),
1131 case X86::DEC64_32r: {
1132 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1133 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1134 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1135 NewMI = addRegOffset(BuildMI(MF, get(Opc))
1136 .addReg(Dest, true, false, false, isDead),
1141 case X86::DEC64_16r:
1142 if (DisableLEA16) return 0;
1143 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1144 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r))
1145 .addReg(Dest, true, false, false, isDead),
1149 case X86::ADD32rr: {
1150 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1151 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1152 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1153 unsigned Src2 = MI->getOperand(2).getReg();
1154 bool isKill2 = MI->getOperand(2).isKill();
1155 NewMI = addRegReg(BuildMI(MF, get(Opc))
1156 .addReg(Dest, true, false, false, isDead),
1157 Src, isKill, Src2, isKill2);
1159 LV->replaceKillInstruction(Src2, MI, NewMI);
1162 case X86::ADD16rr: {
1163 if (DisableLEA16) return 0;
1164 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1165 unsigned Src2 = MI->getOperand(2).getReg();
1166 bool isKill2 = MI->getOperand(2).isKill();
1167 NewMI = addRegReg(BuildMI(MF, get(X86::LEA16r))
1168 .addReg(Dest, true, false, false, isDead),
1169 Src, isKill, Src2, isKill2);
1171 LV->replaceKillInstruction(Src2, MI, NewMI);
1174 case X86::ADD64ri32:
1176 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1177 if (MI->getOperand(2).isImm())
1178 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA64r))
1179 .addReg(Dest, true, false, false, isDead),
1180 Src, isKill, MI->getOperand(2).getImm());
1184 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1185 if (MI->getOperand(2).isImm()) {
1186 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1187 NewMI = addRegOffset(BuildMI(MF, get(Opc))
1188 .addReg(Dest, true, false, false, isDead),
1189 Src, isKill, MI->getOperand(2).getImm());
1194 if (DisableLEA16) return 0;
1195 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1196 if (MI->getOperand(2).isImm())
1197 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r))
1198 .addReg(Dest, true, false, false, isDead),
1199 Src, isKill, MI->getOperand(2).getImm());
1202 if (DisableLEA16) return 0;
1204 case X86::SHL64ri: {
1205 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImm() &&
1206 "Unknown shl instruction!");
1207 unsigned ShAmt = MI->getOperand(2).getImm();
1208 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
1210 AM.Scale = 1 << ShAmt;
1212 unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
1213 : (MIOpc == X86::SHL32ri
1214 ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
1215 NewMI = addFullAddress(BuildMI(MF, get(Opc))
1216 .addReg(Dest, true, false, false, isDead), AM);
1218 NewMI->getOperand(3).setIsKill(true);
1226 if (!NewMI) return 0;
1228 if (LV) { // Update live variables
1230 LV->replaceKillInstruction(Src, MI, NewMI);
1232 LV->replaceKillInstruction(Dest, MI, NewMI);
1235 MFI->insert(MBBI, NewMI); // Insert the new inst
1239 /// commuteInstruction - We have a few instructions that must be hacked on to
1243 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1244 switch (MI->getOpcode()) {
1245 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1246 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1247 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1248 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1249 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1250 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1253 switch (MI->getOpcode()) {
1254 default: assert(0 && "Unreachable!");
1255 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1256 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1257 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1258 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1259 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1260 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1262 unsigned Amt = MI->getOperand(3).getImm();
1264 MachineFunction &MF = *MI->getParent()->getParent();
1265 MI = MF.CloneMachineInstr(MI);
1268 MI->setDesc(get(Opc));
1269 MI->getOperand(3).setImm(Size-Amt);
1270 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1272 case X86::CMOVB16rr:
1273 case X86::CMOVB32rr:
1274 case X86::CMOVB64rr:
1275 case X86::CMOVAE16rr:
1276 case X86::CMOVAE32rr:
1277 case X86::CMOVAE64rr:
1278 case X86::CMOVE16rr:
1279 case X86::CMOVE32rr:
1280 case X86::CMOVE64rr:
1281 case X86::CMOVNE16rr:
1282 case X86::CMOVNE32rr:
1283 case X86::CMOVNE64rr:
1284 case X86::CMOVBE16rr:
1285 case X86::CMOVBE32rr:
1286 case X86::CMOVBE64rr:
1287 case X86::CMOVA16rr:
1288 case X86::CMOVA32rr:
1289 case X86::CMOVA64rr:
1290 case X86::CMOVL16rr:
1291 case X86::CMOVL32rr:
1292 case X86::CMOVL64rr:
1293 case X86::CMOVGE16rr:
1294 case X86::CMOVGE32rr:
1295 case X86::CMOVGE64rr:
1296 case X86::CMOVLE16rr:
1297 case X86::CMOVLE32rr:
1298 case X86::CMOVLE64rr:
1299 case X86::CMOVG16rr:
1300 case X86::CMOVG32rr:
1301 case X86::CMOVG64rr:
1302 case X86::CMOVS16rr:
1303 case X86::CMOVS32rr:
1304 case X86::CMOVS64rr:
1305 case X86::CMOVNS16rr:
1306 case X86::CMOVNS32rr:
1307 case X86::CMOVNS64rr:
1308 case X86::CMOVP16rr:
1309 case X86::CMOVP32rr:
1310 case X86::CMOVP64rr:
1311 case X86::CMOVNP16rr:
1312 case X86::CMOVNP32rr:
1313 case X86::CMOVNP64rr: {
1315 switch (MI->getOpcode()) {
1317 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1318 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1319 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1320 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1321 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1322 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1323 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1324 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1325 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1326 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1327 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1328 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1329 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1330 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1331 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1332 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1333 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1334 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1335 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1336 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1337 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1338 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1339 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1340 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1341 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1342 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1343 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1344 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1345 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1346 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1347 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1348 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1349 case X86::CMOVS64rr: Opc = X86::CMOVNS32rr; break;
1350 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1351 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1352 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1353 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1354 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1355 case X86::CMOVP64rr: Opc = X86::CMOVNP32rr; break;
1356 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1357 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1358 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1361 MachineFunction &MF = *MI->getParent()->getParent();
1362 MI = MF.CloneMachineInstr(MI);
1365 MI->setDesc(get(Opc));
1366 // Fallthrough intended.
1369 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1373 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1375 default: return X86::COND_INVALID;
1376 case X86::JE: return X86::COND_E;
1377 case X86::JNE: return X86::COND_NE;
1378 case X86::JL: return X86::COND_L;
1379 case X86::JLE: return X86::COND_LE;
1380 case X86::JG: return X86::COND_G;
1381 case X86::JGE: return X86::COND_GE;
1382 case X86::JB: return X86::COND_B;
1383 case X86::JBE: return X86::COND_BE;
1384 case X86::JA: return X86::COND_A;
1385 case X86::JAE: return X86::COND_AE;
1386 case X86::JS: return X86::COND_S;
1387 case X86::JNS: return X86::COND_NS;
1388 case X86::JP: return X86::COND_P;
1389 case X86::JNP: return X86::COND_NP;
1390 case X86::JO: return X86::COND_O;
1391 case X86::JNO: return X86::COND_NO;
1392 case X86::JC: return X86::COND_C;
1393 case X86::JNC: return X86::COND_NC;
1397 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1399 default: assert(0 && "Illegal condition code!");
1400 case X86::COND_E: return X86::JE;
1401 case X86::COND_NE: return X86::JNE;
1402 case X86::COND_L: return X86::JL;
1403 case X86::COND_LE: return X86::JLE;
1404 case X86::COND_G: return X86::JG;
1405 case X86::COND_GE: return X86::JGE;
1406 case X86::COND_B: return X86::JB;
1407 case X86::COND_BE: return X86::JBE;
1408 case X86::COND_A: return X86::JA;
1409 case X86::COND_AE: return X86::JAE;
1410 case X86::COND_S: return X86::JS;
1411 case X86::COND_NS: return X86::JNS;
1412 case X86::COND_P: return X86::JP;
1413 case X86::COND_NP: return X86::JNP;
1414 case X86::COND_O: return X86::JO;
1415 case X86::COND_NO: return X86::JNO;
1416 case X86::COND_C: return X86::JC;
1417 case X86::COND_NC: return X86::JNC;
1421 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1422 /// e.g. turning COND_E to COND_NE.
1423 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1425 default: assert(0 && "Illegal condition code!");
1426 case X86::COND_E: return X86::COND_NE;
1427 case X86::COND_NE: return X86::COND_E;
1428 case X86::COND_L: return X86::COND_GE;
1429 case X86::COND_LE: return X86::COND_G;
1430 case X86::COND_G: return X86::COND_LE;
1431 case X86::COND_GE: return X86::COND_L;
1432 case X86::COND_B: return X86::COND_AE;
1433 case X86::COND_BE: return X86::COND_A;
1434 case X86::COND_A: return X86::COND_BE;
1435 case X86::COND_AE: return X86::COND_B;
1436 case X86::COND_S: return X86::COND_NS;
1437 case X86::COND_NS: return X86::COND_S;
1438 case X86::COND_P: return X86::COND_NP;
1439 case X86::COND_NP: return X86::COND_P;
1440 case X86::COND_O: return X86::COND_NO;
1441 case X86::COND_NO: return X86::COND_O;
1442 case X86::COND_C: return X86::COND_NC;
1443 case X86::COND_NC: return X86::COND_C;
1447 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1448 const TargetInstrDesc &TID = MI->getDesc();
1449 if (!TID.isTerminator()) return false;
1451 // Conditional branch is a special case.
1452 if (TID.isBranch() && !TID.isBarrier())
1454 if (!TID.isPredicable())
1456 return !isPredicated(MI);
1459 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1460 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1461 const X86InstrInfo &TII) {
1462 if (MI->getOpcode() == X86::FP_REG_KILL)
1464 return TII.isUnpredicatedTerminator(MI);
1467 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1468 MachineBasicBlock *&TBB,
1469 MachineBasicBlock *&FBB,
1470 SmallVectorImpl<MachineOperand> &Cond) const {
1471 // Start from the bottom of the block and work up, examining the
1472 // terminator instructions.
1473 MachineBasicBlock::iterator I = MBB.end();
1474 while (I != MBB.begin()) {
1476 // Working from the bottom, when we see a non-terminator
1477 // instruction, we're done.
1478 if (!isBrAnalysisUnpredicatedTerminator(I, *this))
1480 // A terminator that isn't a branch can't easily be handled
1481 // by this analysis.
1482 if (!I->getDesc().isBranch())
1484 // Handle unconditional branches.
1485 if (I->getOpcode() == X86::JMP) {
1486 // If the block has any instructions after a JMP, delete them.
1487 while (next(I) != MBB.end())
1488 next(I)->eraseFromParent();
1491 // Delete the JMP if it's equivalent to a fall-through.
1492 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1494 I->eraseFromParent();
1498 // TBB is used to indicate the unconditinal destination.
1499 TBB = I->getOperand(0).getMBB();
1502 // Handle conditional branches.
1503 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1504 if (BranchCode == X86::COND_INVALID)
1505 return true; // Can't handle indirect branch.
1506 // Working from the bottom, handle the first conditional branch.
1509 TBB = I->getOperand(0).getMBB();
1510 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1513 // Handle subsequent conditional branches. Only handle the case
1514 // where all conditional branches branch to the same destination
1515 // and their condition opcodes fit one of the special
1516 // multi-branch idioms.
1517 assert(Cond.size() == 1);
1519 // Only handle the case where all conditional branches branch to
1520 // the same destination.
1521 if (TBB != I->getOperand(0).getMBB())
1523 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1524 // If the conditions are the same, we can leave them alone.
1525 if (OldBranchCode == BranchCode)
1527 // If they differ, see if they fit one of the known patterns.
1528 // Theoretically we could handle more patterns here, but
1529 // we shouldn't expect to see them if instruction selection
1530 // has done a reasonable job.
1531 if ((OldBranchCode == X86::COND_NP &&
1532 BranchCode == X86::COND_E) ||
1533 (OldBranchCode == X86::COND_E &&
1534 BranchCode == X86::COND_NP))
1535 BranchCode = X86::COND_NP_OR_E;
1536 else if ((OldBranchCode == X86::COND_P &&
1537 BranchCode == X86::COND_NE) ||
1538 (OldBranchCode == X86::COND_NE &&
1539 BranchCode == X86::COND_P))
1540 BranchCode = X86::COND_NE_OR_P;
1543 // Update the MachineOperand.
1544 Cond[0].setImm(BranchCode);
1550 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1551 MachineBasicBlock::iterator I = MBB.end();
1554 while (I != MBB.begin()) {
1556 if (I->getOpcode() != X86::JMP &&
1557 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1559 // Remove the branch.
1560 I->eraseFromParent();
1568 static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB,
1569 const MachineOperand &MO) {
1571 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit(),
1572 MO.isKill(), MO.isDead(), MO.getSubReg());
1573 else if (MO.isImm())
1574 MIB = MIB.addImm(MO.getImm());
1576 MIB = MIB.addFrameIndex(MO.getIndex());
1577 else if (MO.isGlobal())
1578 MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
1579 else if (MO.isCPI())
1580 MIB = MIB.addConstantPoolIndex(MO.getIndex(), MO.getOffset());
1581 else if (MO.isJTI())
1582 MIB = MIB.addJumpTableIndex(MO.getIndex());
1583 else if (MO.isSymbol())
1584 MIB = MIB.addExternalSymbol(MO.getSymbolName());
1586 assert(0 && "Unknown operand for X86InstrAddOperand!");
1592 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1593 MachineBasicBlock *FBB,
1594 const SmallVectorImpl<MachineOperand> &Cond) const {
1595 // Shouldn't be a fall through.
1596 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1597 assert((Cond.size() == 1 || Cond.size() == 0) &&
1598 "X86 branch conditions have one component!");
1601 // Unconditional branch?
1602 assert(!FBB && "Unconditional branch with multiple successors!");
1603 BuildMI(&MBB, get(X86::JMP)).addMBB(TBB);
1607 // Conditional branch.
1609 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1611 case X86::COND_NP_OR_E:
1612 // Synthesize NP_OR_E with two branches.
1613 BuildMI(&MBB, get(X86::JNP)).addMBB(TBB);
1615 BuildMI(&MBB, get(X86::JE)).addMBB(TBB);
1618 case X86::COND_NE_OR_P:
1619 // Synthesize NE_OR_P with two branches.
1620 BuildMI(&MBB, get(X86::JNE)).addMBB(TBB);
1622 BuildMI(&MBB, get(X86::JP)).addMBB(TBB);
1626 unsigned Opc = GetCondBranchFromCond(CC);
1627 BuildMI(&MBB, get(Opc)).addMBB(TBB);
1632 // Two-way Conditional branch. Insert the second branch.
1633 BuildMI(&MBB, get(X86::JMP)).addMBB(FBB);
1639 bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1640 MachineBasicBlock::iterator MI,
1641 unsigned DestReg, unsigned SrcReg,
1642 const TargetRegisterClass *DestRC,
1643 const TargetRegisterClass *SrcRC) const {
1644 if (DestRC == SrcRC) {
1646 if (DestRC == &X86::GR64RegClass) {
1648 } else if (DestRC == &X86::GR32RegClass) {
1650 } else if (DestRC == &X86::GR16RegClass) {
1652 } else if (DestRC == &X86::GR8RegClass) {
1654 } else if (DestRC == &X86::GR32_RegClass) {
1655 Opc = X86::MOV32_rr;
1656 } else if (DestRC == &X86::GR16_RegClass) {
1657 Opc = X86::MOV16_rr;
1658 } else if (DestRC == &X86::RFP32RegClass) {
1659 Opc = X86::MOV_Fp3232;
1660 } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) {
1661 Opc = X86::MOV_Fp6464;
1662 } else if (DestRC == &X86::RFP80RegClass) {
1663 Opc = X86::MOV_Fp8080;
1664 } else if (DestRC == &X86::FR32RegClass) {
1665 Opc = X86::FsMOVAPSrr;
1666 } else if (DestRC == &X86::FR64RegClass) {
1667 Opc = X86::FsMOVAPDrr;
1668 } else if (DestRC == &X86::VR128RegClass) {
1669 Opc = X86::MOVAPSrr;
1670 } else if (DestRC == &X86::VR64RegClass) {
1671 Opc = X86::MMX_MOVQ64rr;
1675 BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
1679 // Moving EFLAGS to / from another register requires a push and a pop.
1680 if (SrcRC == &X86::CCRRegClass) {
1681 if (SrcReg != X86::EFLAGS)
1683 if (DestRC == &X86::GR64RegClass) {
1684 BuildMI(MBB, MI, get(X86::PUSHFQ));
1685 BuildMI(MBB, MI, get(X86::POP64r), DestReg);
1687 } else if (DestRC == &X86::GR32RegClass) {
1688 BuildMI(MBB, MI, get(X86::PUSHFD));
1689 BuildMI(MBB, MI, get(X86::POP32r), DestReg);
1692 } else if (DestRC == &X86::CCRRegClass) {
1693 if (DestReg != X86::EFLAGS)
1695 if (SrcRC == &X86::GR64RegClass) {
1696 BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg);
1697 BuildMI(MBB, MI, get(X86::POPFQ));
1699 } else if (SrcRC == &X86::GR32RegClass) {
1700 BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg);
1701 BuildMI(MBB, MI, get(X86::POPFD));
1706 // Moving from ST(0) turns into FpGET_ST0_32 etc.
1707 if (SrcRC == &X86::RSTRegClass) {
1708 // Copying from ST(0)/ST(1).
1709 if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
1710 // Can only copy from ST(0)/ST(1) right now
1712 bool isST0 = SrcReg == X86::ST0;
1714 if (DestRC == &X86::RFP32RegClass)
1715 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
1716 else if (DestRC == &X86::RFP64RegClass)
1717 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
1719 if (DestRC != &X86::RFP80RegClass)
1721 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
1723 BuildMI(MBB, MI, get(Opc), DestReg);
1727 // Moving to ST(0) turns into FpSET_ST0_32 etc.
1728 if (DestRC == &X86::RSTRegClass) {
1729 // Copying to ST(0). FIXME: handle ST(1) also
1730 if (DestReg != X86::ST0)
1731 // Can only copy to TOS right now
1734 if (SrcRC == &X86::RFP32RegClass)
1735 Opc = X86::FpSET_ST0_32;
1736 else if (SrcRC == &X86::RFP64RegClass)
1737 Opc = X86::FpSET_ST0_64;
1739 if (SrcRC != &X86::RFP80RegClass)
1741 Opc = X86::FpSET_ST0_80;
1743 BuildMI(MBB, MI, get(Opc)).addReg(SrcReg);
1747 // Not yet supported!
1751 static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
1752 bool isStackAligned) {
1754 if (RC == &X86::GR64RegClass) {
1756 } else if (RC == &X86::GR32RegClass) {
1758 } else if (RC == &X86::GR16RegClass) {
1760 } else if (RC == &X86::GR8RegClass) {
1762 } else if (RC == &X86::GR32_RegClass) {
1763 Opc = X86::MOV32_mr;
1764 } else if (RC == &X86::GR16_RegClass) {
1765 Opc = X86::MOV16_mr;
1766 } else if (RC == &X86::RFP80RegClass) {
1767 Opc = X86::ST_FpP80m; // pops
1768 } else if (RC == &X86::RFP64RegClass) {
1769 Opc = X86::ST_Fp64m;
1770 } else if (RC == &X86::RFP32RegClass) {
1771 Opc = X86::ST_Fp32m;
1772 } else if (RC == &X86::FR32RegClass) {
1774 } else if (RC == &X86::FR64RegClass) {
1776 } else if (RC == &X86::VR128RegClass) {
1777 // If stack is realigned we can use aligned stores.
1778 Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr;
1779 } else if (RC == &X86::VR64RegClass) {
1780 Opc = X86::MMX_MOVQ64mr;
1782 assert(0 && "Unknown regclass");
1789 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1790 MachineBasicBlock::iterator MI,
1791 unsigned SrcReg, bool isKill, int FrameIdx,
1792 const TargetRegisterClass *RC) const {
1793 const MachineFunction &MF = *MBB.getParent();
1794 bool isAligned = (RI.getStackAlignment() >= 16) ||
1795 RI.needsStackRealignment(MF);
1796 unsigned Opc = getStoreRegOpcode(RC, isAligned);
1797 addFrameReference(BuildMI(MBB, MI, get(Opc)), FrameIdx)
1798 .addReg(SrcReg, false, false, isKill);
1801 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
1803 SmallVectorImpl<MachineOperand> &Addr,
1804 const TargetRegisterClass *RC,
1805 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1806 bool isAligned = (RI.getStackAlignment() >= 16) ||
1807 RI.needsStackRealignment(MF);
1808 unsigned Opc = getStoreRegOpcode(RC, isAligned);
1809 MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
1810 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1811 MIB = X86InstrAddOperand(MIB, Addr[i]);
1812 MIB.addReg(SrcReg, false, false, isKill);
1813 NewMIs.push_back(MIB);
1816 static unsigned getLoadRegOpcode(const TargetRegisterClass *RC,
1817 bool isStackAligned) {
1819 if (RC == &X86::GR64RegClass) {
1821 } else if (RC == &X86::GR32RegClass) {
1823 } else if (RC == &X86::GR16RegClass) {
1825 } else if (RC == &X86::GR8RegClass) {
1827 } else if (RC == &X86::GR32_RegClass) {
1828 Opc = X86::MOV32_rm;
1829 } else if (RC == &X86::GR16_RegClass) {
1830 Opc = X86::MOV16_rm;
1831 } else if (RC == &X86::RFP80RegClass) {
1832 Opc = X86::LD_Fp80m;
1833 } else if (RC == &X86::RFP64RegClass) {
1834 Opc = X86::LD_Fp64m;
1835 } else if (RC == &X86::RFP32RegClass) {
1836 Opc = X86::LD_Fp32m;
1837 } else if (RC == &X86::FR32RegClass) {
1839 } else if (RC == &X86::FR64RegClass) {
1841 } else if (RC == &X86::VR128RegClass) {
1842 // If stack is realigned we can use aligned loads.
1843 Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm;
1844 } else if (RC == &X86::VR64RegClass) {
1845 Opc = X86::MMX_MOVQ64rm;
1847 assert(0 && "Unknown regclass");
1854 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1855 MachineBasicBlock::iterator MI,
1856 unsigned DestReg, int FrameIdx,
1857 const TargetRegisterClass *RC) const{
1858 const MachineFunction &MF = *MBB.getParent();
1859 bool isAligned = (RI.getStackAlignment() >= 16) ||
1860 RI.needsStackRealignment(MF);
1861 unsigned Opc = getLoadRegOpcode(RC, isAligned);
1862 addFrameReference(BuildMI(MBB, MI, get(Opc), DestReg), FrameIdx);
1865 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
1866 SmallVectorImpl<MachineOperand> &Addr,
1867 const TargetRegisterClass *RC,
1868 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1869 bool isAligned = (RI.getStackAlignment() >= 16) ||
1870 RI.needsStackRealignment(MF);
1871 unsigned Opc = getLoadRegOpcode(RC, isAligned);
1872 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
1873 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1874 MIB = X86InstrAddOperand(MIB, Addr[i]);
1875 NewMIs.push_back(MIB);
1878 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1879 MachineBasicBlock::iterator MI,
1880 const std::vector<CalleeSavedInfo> &CSI) const {
1884 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1885 unsigned SlotSize = is64Bit ? 8 : 4;
1887 MachineFunction &MF = *MBB.getParent();
1888 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1889 X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize);
1891 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
1892 for (unsigned i = CSI.size(); i != 0; --i) {
1893 unsigned Reg = CSI[i-1].getReg();
1894 // Add the callee-saved register as live-in. It's killed at the spill.
1896 BuildMI(MBB, MI, get(Opc))
1897 .addReg(Reg, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true);
1902 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1903 MachineBasicBlock::iterator MI,
1904 const std::vector<CalleeSavedInfo> &CSI) const {
1908 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1910 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
1911 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1912 unsigned Reg = CSI[i].getReg();
1913 BuildMI(MBB, MI, get(Opc), Reg);
1918 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
1919 const SmallVectorImpl<MachineOperand> &MOs,
1920 MachineInstr *MI, const TargetInstrInfo &TII) {
1921 // Create the base instruction with the memory operand as the first part.
1922 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true);
1923 MachineInstrBuilder MIB(NewMI);
1924 unsigned NumAddrOps = MOs.size();
1925 for (unsigned i = 0; i != NumAddrOps; ++i)
1926 MIB = X86InstrAddOperand(MIB, MOs[i]);
1927 if (NumAddrOps < 4) // FrameIndex only
1928 MIB.addImm(1).addReg(0).addImm(0);
1930 // Loop over the rest of the ri operands, converting them over.
1931 unsigned NumOps = MI->getDesc().getNumOperands()-2;
1932 for (unsigned i = 0; i != NumOps; ++i) {
1933 MachineOperand &MO = MI->getOperand(i+2);
1934 MIB = X86InstrAddOperand(MIB, MO);
1936 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
1937 MachineOperand &MO = MI->getOperand(i);
1938 MIB = X86InstrAddOperand(MIB, MO);
1943 static MachineInstr *FuseInst(MachineFunction &MF,
1944 unsigned Opcode, unsigned OpNo,
1945 const SmallVectorImpl<MachineOperand> &MOs,
1946 MachineInstr *MI, const TargetInstrInfo &TII) {
1947 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true);
1948 MachineInstrBuilder MIB(NewMI);
1950 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1951 MachineOperand &MO = MI->getOperand(i);
1953 assert(MO.isReg() && "Expected to fold into reg operand!");
1954 unsigned NumAddrOps = MOs.size();
1955 for (unsigned i = 0; i != NumAddrOps; ++i)
1956 MIB = X86InstrAddOperand(MIB, MOs[i]);
1957 if (NumAddrOps < 4) // FrameIndex only
1958 MIB.addImm(1).addReg(0).addImm(0);
1960 MIB = X86InstrAddOperand(MIB, MO);
1966 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
1967 const SmallVectorImpl<MachineOperand> &MOs,
1969 MachineFunction &MF = *MI->getParent()->getParent();
1970 MachineInstrBuilder MIB = BuildMI(MF, TII.get(Opcode));
1972 unsigned NumAddrOps = MOs.size();
1973 for (unsigned i = 0; i != NumAddrOps; ++i)
1974 MIB = X86InstrAddOperand(MIB, MOs[i]);
1975 if (NumAddrOps < 4) // FrameIndex only
1976 MIB.addImm(1).addReg(0).addImm(0);
1977 return MIB.addImm(0);
1981 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
1982 MachineInstr *MI, unsigned i,
1983 const SmallVectorImpl<MachineOperand> &MOs) const{
1984 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
1985 bool isTwoAddrFold = false;
1986 unsigned NumOps = MI->getDesc().getNumOperands();
1987 bool isTwoAddr = NumOps > 1 &&
1988 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
1990 MachineInstr *NewMI = NULL;
1991 // Folding a memory location into the two-address part of a two-address
1992 // instruction is different than folding it other places. It requires
1993 // replacing the *two* registers with the memory location.
1994 if (isTwoAddr && NumOps >= 2 && i < 2 &&
1995 MI->getOperand(0).isReg() &&
1996 MI->getOperand(1).isReg() &&
1997 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
1998 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
1999 isTwoAddrFold = true;
2000 } else if (i == 0) { // If operand 0
2001 if (MI->getOpcode() == X86::MOV16r0)
2002 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2003 else if (MI->getOpcode() == X86::MOV32r0)
2004 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2005 else if (MI->getOpcode() == X86::MOV64r0)
2006 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2007 else if (MI->getOpcode() == X86::MOV8r0)
2008 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2012 OpcodeTablePtr = &RegOp2MemOpTable0;
2013 } else if (i == 1) {
2014 OpcodeTablePtr = &RegOp2MemOpTable1;
2015 } else if (i == 2) {
2016 OpcodeTablePtr = &RegOp2MemOpTable2;
2019 // If table selected...
2020 if (OpcodeTablePtr) {
2021 // Find the Opcode to fuse
2022 DenseMap<unsigned*, unsigned>::iterator I =
2023 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
2024 if (I != OpcodeTablePtr->end()) {
2026 NewMI = FuseTwoAddrInst(MF, I->second, MOs, MI, *this);
2028 NewMI = FuseInst(MF, I->second, i, MOs, MI, *this);
2034 if (PrintFailedFusing)
2035 cerr << "We failed to fuse operand " << i << " in " << *MI;
2040 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2042 const SmallVectorImpl<unsigned> &Ops,
2043 int FrameIndex) const {
2044 // Check switch flag
2045 if (NoFusing) return NULL;
2047 const MachineFrameInfo *MFI = MF.getFrameInfo();
2048 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2049 // FIXME: Move alignment requirement into tables?
2050 if (Alignment < 16) {
2051 switch (MI->getOpcode()) {
2053 // Not always safe to fold movsd into these instructions since their load
2054 // folding variants expects the address to be 16 byte aligned.
2055 case X86::FsANDNPDrr:
2056 case X86::FsANDNPSrr:
2057 case X86::FsANDPDrr:
2058 case X86::FsANDPSrr:
2061 case X86::FsXORPDrr:
2062 case X86::FsXORPSrr:
2067 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2068 unsigned NewOpc = 0;
2069 switch (MI->getOpcode()) {
2070 default: return NULL;
2071 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2072 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2073 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2074 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2076 // Change to CMPXXri r, 0 first.
2077 MI->setDesc(get(NewOpc));
2078 MI->getOperand(1).ChangeToImmediate(0);
2079 } else if (Ops.size() != 1)
2082 SmallVector<MachineOperand,4> MOs;
2083 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2084 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs);
2087 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2089 const SmallVectorImpl<unsigned> &Ops,
2090 MachineInstr *LoadMI) const {
2091 // Check switch flag
2092 if (NoFusing) return NULL;
2094 // Determine the alignment of the load.
2095 unsigned Alignment = 0;
2096 if (LoadMI->hasOneMemOperand())
2097 Alignment = LoadMI->memoperands_begin()->getAlignment();
2099 // FIXME: Move alignment requirement into tables?
2100 if (Alignment < 16) {
2101 switch (MI->getOpcode()) {
2103 // Not always safe to fold movsd into these instructions since their load
2104 // folding variants expects the address to be 16 byte aligned.
2105 case X86::FsANDNPDrr:
2106 case X86::FsANDNPSrr:
2107 case X86::FsANDPDrr:
2108 case X86::FsANDPSrr:
2111 case X86::FsXORPDrr:
2112 case X86::FsXORPSrr:
2117 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2118 unsigned NewOpc = 0;
2119 switch (MI->getOpcode()) {
2120 default: return NULL;
2121 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2122 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2123 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2124 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2126 // Change to CMPXXri r, 0 first.
2127 MI->setDesc(get(NewOpc));
2128 MI->getOperand(1).ChangeToImmediate(0);
2129 } else if (Ops.size() != 1)
2132 SmallVector<MachineOperand,4> MOs;
2133 if (LoadMI->getOpcode() == X86::V_SET0 ||
2134 LoadMI->getOpcode() == X86::V_SETALLONES) {
2135 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
2136 // Create a constant-pool entry and operands to load from it.
2138 // x86-32 PIC requires a PIC base register for constant pools.
2139 unsigned PICBase = 0;
2140 if (TM.getRelocationModel() == Reloc::PIC_ &&
2141 !TM.getSubtarget<X86Subtarget>().is64Bit())
2142 // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
2143 // This doesn't work for several reasons.
2144 // 1. GlobalBaseReg may have been spilled.
2145 // 2. It may not be live at MI.
2148 // Create a v4i32 constant-pool entry.
2149 MachineConstantPool &MCP = *MF.getConstantPool();
2150 const VectorType *Ty = VectorType::get(Type::Int32Ty, 4);
2151 Constant *C = LoadMI->getOpcode() == X86::V_SET0 ?
2152 ConstantVector::getNullValue(Ty) :
2153 ConstantVector::getAllOnesValue(Ty);
2154 unsigned CPI = MCP.getConstantPoolIndex(C, /*AlignmentLog2=*/4);
2156 // Create operands to load from the constant pool entry.
2157 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2158 MOs.push_back(MachineOperand::CreateImm(1));
2159 MOs.push_back(MachineOperand::CreateReg(0, false));
2160 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2162 // Folding a normal load. Just copy the load's address operands.
2163 unsigned NumOps = LoadMI->getDesc().getNumOperands();
2164 for (unsigned i = NumOps - 4; i != NumOps; ++i)
2165 MOs.push_back(LoadMI->getOperand(i));
2167 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs);
2171 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2172 const SmallVectorImpl<unsigned> &Ops) const {
2173 // Check switch flag
2174 if (NoFusing) return 0;
2176 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2177 switch (MI->getOpcode()) {
2178 default: return false;
2187 if (Ops.size() != 1)
2190 unsigned OpNum = Ops[0];
2191 unsigned Opc = MI->getOpcode();
2192 unsigned NumOps = MI->getDesc().getNumOperands();
2193 bool isTwoAddr = NumOps > 1 &&
2194 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2196 // Folding a memory location into the two-address part of a two-address
2197 // instruction is different than folding it other places. It requires
2198 // replacing the *two* registers with the memory location.
2199 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
2200 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2201 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2202 } else if (OpNum == 0) { // If operand 0
2211 OpcodeTablePtr = &RegOp2MemOpTable0;
2212 } else if (OpNum == 1) {
2213 OpcodeTablePtr = &RegOp2MemOpTable1;
2214 } else if (OpNum == 2) {
2215 OpcodeTablePtr = &RegOp2MemOpTable2;
2218 if (OpcodeTablePtr) {
2219 // Find the Opcode to fuse
2220 DenseMap<unsigned*, unsigned>::iterator I =
2221 OpcodeTablePtr->find((unsigned*)Opc);
2222 if (I != OpcodeTablePtr->end())
2228 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2229 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2230 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2231 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2232 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2233 if (I == MemOp2RegOpTable.end())
2235 unsigned Opc = I->second.first;
2236 unsigned Index = I->second.second & 0xf;
2237 bool FoldedLoad = I->second.second & (1 << 4);
2238 bool FoldedStore = I->second.second & (1 << 5);
2239 if (UnfoldLoad && !FoldedLoad)
2241 UnfoldLoad &= FoldedLoad;
2242 if (UnfoldStore && !FoldedStore)
2244 UnfoldStore &= FoldedStore;
2246 const TargetInstrDesc &TID = get(Opc);
2247 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2248 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
2249 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
2250 SmallVector<MachineOperand,4> AddrOps;
2251 SmallVector<MachineOperand,2> BeforeOps;
2252 SmallVector<MachineOperand,2> AfterOps;
2253 SmallVector<MachineOperand,4> ImpOps;
2254 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2255 MachineOperand &Op = MI->getOperand(i);
2256 if (i >= Index && i < Index+4)
2257 AddrOps.push_back(Op);
2258 else if (Op.isReg() && Op.isImplicit())
2259 ImpOps.push_back(Op);
2261 BeforeOps.push_back(Op);
2263 AfterOps.push_back(Op);
2266 // Emit the load instruction.
2268 loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs);
2270 // Address operands cannot be marked isKill.
2271 for (unsigned i = 1; i != 5; ++i) {
2272 MachineOperand &MO = NewMIs[0]->getOperand(i);
2274 MO.setIsKill(false);
2279 // Emit the data processing instruction.
2280 MachineInstr *DataMI = MF.CreateMachineInstr(TID, true);
2281 MachineInstrBuilder MIB(DataMI);
2284 MIB.addReg(Reg, true);
2285 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2286 MIB = X86InstrAddOperand(MIB, BeforeOps[i]);
2289 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2290 MIB = X86InstrAddOperand(MIB, AfterOps[i]);
2291 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2292 MachineOperand &MO = ImpOps[i];
2293 MIB.addReg(MO.getReg(), MO.isDef(), true, MO.isKill(), MO.isDead());
2295 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2296 unsigned NewOpc = 0;
2297 switch (DataMI->getOpcode()) {
2299 case X86::CMP64ri32:
2303 MachineOperand &MO0 = DataMI->getOperand(0);
2304 MachineOperand &MO1 = DataMI->getOperand(1);
2305 if (MO1.getImm() == 0) {
2306 switch (DataMI->getOpcode()) {
2308 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2309 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2310 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2311 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2313 DataMI->setDesc(get(NewOpc));
2314 MO1.ChangeToRegister(MO0.getReg(), false);
2318 NewMIs.push_back(DataMI);
2320 // Emit the store instruction.
2322 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
2323 const TargetRegisterClass *DstRC = DstTOI.isLookupPtrRegClass()
2324 ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
2325 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
2332 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2333 SmallVectorImpl<SDNode*> &NewNodes) const {
2334 if (!N->isMachineOpcode())
2337 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2338 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode());
2339 if (I == MemOp2RegOpTable.end())
2341 unsigned Opc = I->second.first;
2342 unsigned Index = I->second.second & 0xf;
2343 bool FoldedLoad = I->second.second & (1 << 4);
2344 bool FoldedStore = I->second.second & (1 << 5);
2345 const TargetInstrDesc &TID = get(Opc);
2346 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2347 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
2348 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
2349 std::vector<SDValue> AddrOps;
2350 std::vector<SDValue> BeforeOps;
2351 std::vector<SDValue> AfterOps;
2352 unsigned NumOps = N->getNumOperands();
2353 for (unsigned i = 0; i != NumOps-1; ++i) {
2354 SDValue Op = N->getOperand(i);
2355 if (i >= Index && i < Index+4)
2356 AddrOps.push_back(Op);
2358 BeforeOps.push_back(Op);
2360 AfterOps.push_back(Op);
2362 SDValue Chain = N->getOperand(NumOps-1);
2363 AddrOps.push_back(Chain);
2365 // Emit the load instruction.
2367 const MachineFunction &MF = DAG.getMachineFunction();
2369 MVT VT = *RC->vt_begin();
2370 bool isAligned = (RI.getStackAlignment() >= 16) ||
2371 RI.needsStackRealignment(MF);
2372 Load = DAG.getTargetNode(getLoadRegOpcode(RC, isAligned),
2374 &AddrOps[0], AddrOps.size());
2375 NewNodes.push_back(Load);
2378 // Emit the data processing instruction.
2379 std::vector<MVT> VTs;
2380 const TargetRegisterClass *DstRC = 0;
2381 if (TID.getNumDefs() > 0) {
2382 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
2383 DstRC = DstTOI.isLookupPtrRegClass()
2384 ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
2385 VTs.push_back(*DstRC->vt_begin());
2387 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2388 MVT VT = N->getValueType(i);
2389 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2393 BeforeOps.push_back(SDValue(Load, 0));
2394 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2395 SDNode *NewNode= DAG.getTargetNode(Opc, VTs, &BeforeOps[0], BeforeOps.size());
2396 NewNodes.push_back(NewNode);
2398 // Emit the store instruction.
2401 AddrOps.push_back(SDValue(NewNode, 0));
2402 AddrOps.push_back(Chain);
2403 bool isAligned = (RI.getStackAlignment() >= 16) ||
2404 RI.needsStackRealignment(MF);
2405 SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC, isAligned),
2406 MVT::Other, &AddrOps[0], AddrOps.size());
2407 NewNodes.push_back(Store);
2413 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2414 bool UnfoldLoad, bool UnfoldStore) const {
2415 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2416 MemOp2RegOpTable.find((unsigned*)Opc);
2417 if (I == MemOp2RegOpTable.end())
2419 bool FoldedLoad = I->second.second & (1 << 4);
2420 bool FoldedStore = I->second.second & (1 << 5);
2421 if (UnfoldLoad && !FoldedLoad)
2423 if (UnfoldStore && !FoldedStore)
2425 return I->second.first;
2428 bool X86InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
2429 if (MBB.empty()) return false;
2431 switch (MBB.back().getOpcode()) {
2432 case X86::TCRETURNri:
2433 case X86::TCRETURNdi:
2434 case X86::RET: // Return.
2439 case X86::JMP: // Uncond branch.
2440 case X86::JMP32r: // Indirect branch.
2441 case X86::JMP64r: // Indirect branch (64-bit).
2442 case X86::JMP32m: // Indirect branch through mem.
2443 case X86::JMP64m: // Indirect branch through mem (64-bit).
2445 default: return false;
2450 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2451 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
2452 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
2453 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
2455 Cond[0].setImm(GetOppositeBranchCondition(CC));
2460 IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const {
2461 // FIXME: Ignore bariers of x87 stack registers for now. We can't
2462 // allow any loads of these registers before FpGet_ST0_80.
2463 return RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
2464 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass;
2467 const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
2468 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
2469 if (Subtarget->is64Bit())
2470 return &X86::GR64RegClass;
2472 return &X86::GR32RegClass;
2475 unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) {
2476 switch (Desc->TSFlags & X86II::ImmMask) {
2477 case X86II::Imm8: return 1;
2478 case X86II::Imm16: return 2;
2479 case X86II::Imm32: return 4;
2480 case X86II::Imm64: return 8;
2481 default: assert(0 && "Immediate size not set!");
2486 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
2487 /// e.g. r8, xmm8, etc.
2488 bool X86InstrInfo::isX86_64ExtendedReg(const MachineOperand &MO) {
2489 if (!MO.isReg()) return false;
2490 switch (MO.getReg()) {
2492 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
2493 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
2494 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
2495 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
2496 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
2497 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
2498 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
2499 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
2500 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
2501 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
2508 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
2509 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
2510 /// size, and 3) use of X86-64 extended registers.
2511 unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
2513 const TargetInstrDesc &Desc = MI.getDesc();
2515 // Pseudo instructions do not need REX prefix byte.
2516 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
2518 if (Desc.TSFlags & X86II::REX_W)
2521 unsigned NumOps = Desc.getNumOperands();
2523 bool isTwoAddr = NumOps > 1 &&
2524 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
2526 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
2527 unsigned i = isTwoAddr ? 1 : 0;
2528 for (unsigned e = NumOps; i != e; ++i) {
2529 const MachineOperand& MO = MI.getOperand(i);
2531 unsigned Reg = MO.getReg();
2532 if (isX86_64NonExtLowByteReg(Reg))
2537 switch (Desc.TSFlags & X86II::FormMask) {
2538 case X86II::MRMInitReg:
2539 if (isX86_64ExtendedReg(MI.getOperand(0)))
2540 REX |= (1 << 0) | (1 << 2);
2542 case X86II::MRMSrcReg: {
2543 if (isX86_64ExtendedReg(MI.getOperand(0)))
2545 i = isTwoAddr ? 2 : 1;
2546 for (unsigned e = NumOps; i != e; ++i) {
2547 const MachineOperand& MO = MI.getOperand(i);
2548 if (isX86_64ExtendedReg(MO))
2553 case X86II::MRMSrcMem: {
2554 if (isX86_64ExtendedReg(MI.getOperand(0)))
2557 i = isTwoAddr ? 2 : 1;
2558 for (; i != NumOps; ++i) {
2559 const MachineOperand& MO = MI.getOperand(i);
2561 if (isX86_64ExtendedReg(MO))
2568 case X86II::MRM0m: case X86II::MRM1m:
2569 case X86II::MRM2m: case X86II::MRM3m:
2570 case X86II::MRM4m: case X86II::MRM5m:
2571 case X86II::MRM6m: case X86II::MRM7m:
2572 case X86II::MRMDestMem: {
2573 unsigned e = isTwoAddr ? 5 : 4;
2574 i = isTwoAddr ? 1 : 0;
2575 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
2578 for (; i != e; ++i) {
2579 const MachineOperand& MO = MI.getOperand(i);
2581 if (isX86_64ExtendedReg(MO))
2589 if (isX86_64ExtendedReg(MI.getOperand(0)))
2591 i = isTwoAddr ? 2 : 1;
2592 for (unsigned e = NumOps; i != e; ++i) {
2593 const MachineOperand& MO = MI.getOperand(i);
2594 if (isX86_64ExtendedReg(MO))
2604 /// sizePCRelativeBlockAddress - This method returns the size of a PC
2605 /// relative block address instruction
2607 static unsigned sizePCRelativeBlockAddress() {
2611 /// sizeGlobalAddress - Give the size of the emission of this global address
2613 static unsigned sizeGlobalAddress(bool dword) {
2614 return dword ? 8 : 4;
2617 /// sizeConstPoolAddress - Give the size of the emission of this constant
2620 static unsigned sizeConstPoolAddress(bool dword) {
2621 return dword ? 8 : 4;
2624 /// sizeExternalSymbolAddress - Give the size of the emission of this external
2627 static unsigned sizeExternalSymbolAddress(bool dword) {
2628 return dword ? 8 : 4;
2631 /// sizeJumpTableAddress - Give the size of the emission of this jump
2634 static unsigned sizeJumpTableAddress(bool dword) {
2635 return dword ? 8 : 4;
2638 static unsigned sizeConstant(unsigned Size) {
2642 static unsigned sizeRegModRMByte(){
2646 static unsigned sizeSIBByte(){
2650 static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
2651 unsigned FinalSize = 0;
2652 // If this is a simple integer displacement that doesn't require a relocation.
2654 FinalSize += sizeConstant(4);
2658 // Otherwise, this is something that requires a relocation.
2659 if (RelocOp->isGlobal()) {
2660 FinalSize += sizeGlobalAddress(false);
2661 } else if (RelocOp->isCPI()) {
2662 FinalSize += sizeConstPoolAddress(false);
2663 } else if (RelocOp->isJTI()) {
2664 FinalSize += sizeJumpTableAddress(false);
2666 assert(0 && "Unknown value to relocate!");
2671 static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
2672 bool IsPIC, bool Is64BitMode) {
2673 const MachineOperand &Op3 = MI.getOperand(Op+3);
2675 const MachineOperand *DispForReloc = 0;
2676 unsigned FinalSize = 0;
2678 // Figure out what sort of displacement we have to handle here.
2679 if (Op3.isGlobal()) {
2680 DispForReloc = &Op3;
2681 } else if (Op3.isCPI()) {
2682 if (Is64BitMode || IsPIC) {
2683 DispForReloc = &Op3;
2687 } else if (Op3.isJTI()) {
2688 if (Is64BitMode || IsPIC) {
2689 DispForReloc = &Op3;
2697 const MachineOperand &Base = MI.getOperand(Op);
2698 const MachineOperand &IndexReg = MI.getOperand(Op+2);
2700 unsigned BaseReg = Base.getReg();
2702 // Is a SIB byte needed?
2703 if (IndexReg.getReg() == 0 &&
2704 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
2705 if (BaseReg == 0) { // Just a displacement?
2706 // Emit special case [disp32] encoding
2708 FinalSize += getDisplacementFieldSize(DispForReloc);
2710 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
2711 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
2712 // Emit simple indirect register encoding... [EAX] f.e.
2714 // Be pessimistic and assume it's a disp32, not a disp8
2716 // Emit the most general non-SIB encoding: [REG+disp32]
2718 FinalSize += getDisplacementFieldSize(DispForReloc);
2722 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
2723 assert(IndexReg.getReg() != X86::ESP &&
2724 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
2726 bool ForceDisp32 = false;
2727 if (BaseReg == 0 || DispForReloc) {
2728 // Emit the normal disp32 encoding.
2735 FinalSize += sizeSIBByte();
2737 // Do we need to output a displacement?
2738 if (DispVal != 0 || ForceDisp32) {
2739 FinalSize += getDisplacementFieldSize(DispForReloc);
2746 static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
2747 const TargetInstrDesc *Desc,
2748 bool IsPIC, bool Is64BitMode) {
2750 unsigned Opcode = Desc->Opcode;
2751 unsigned FinalSize = 0;
2753 // Emit the lock opcode prefix as needed.
2754 if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
2756 // Emit segment overrid opcode prefix as needed.
2757 switch (Desc->TSFlags & X86II::SegOvrMask) {
2762 default: assert(0 && "Invalid segment!");
2763 case 0: break; // No segment override!
2766 // Emit the repeat opcode prefix as needed.
2767 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
2769 // Emit the operand size opcode prefix as needed.
2770 if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
2772 // Emit the address size opcode prefix as needed.
2773 if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
2775 bool Need0FPrefix = false;
2776 switch (Desc->TSFlags & X86II::Op0Mask) {
2777 case X86II::TB: // Two-byte opcode prefix
2778 case X86II::T8: // 0F 38
2779 case X86II::TA: // 0F 3A
2780 Need0FPrefix = true;
2782 case X86II::REP: break; // already handled.
2783 case X86II::XS: // F3 0F
2785 Need0FPrefix = true;
2787 case X86II::XD: // F2 0F
2789 Need0FPrefix = true;
2791 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
2792 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
2794 break; // Two-byte opcode prefix
2795 default: assert(0 && "Invalid prefix!");
2796 case 0: break; // No prefix!
2801 unsigned REX = X86InstrInfo::determineREX(MI);
2806 // 0x0F escape code must be emitted just before the opcode.
2810 switch (Desc->TSFlags & X86II::Op0Mask) {
2811 case X86II::T8: // 0F 38
2814 case X86II::TA: // 0F 3A
2819 // If this is a two-address instruction, skip one of the register operands.
2820 unsigned NumOps = Desc->getNumOperands();
2822 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
2825 switch (Desc->TSFlags & X86II::FormMask) {
2826 default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
2828 // Remember the current PC offset, this is the PIC relocation
2833 case TargetInstrInfo::INLINEASM: {
2834 const MachineFunction *MF = MI.getParent()->getParent();
2835 const char *AsmStr = MI.getOperand(0).getSymbolName();
2836 const TargetAsmInfo* AI = MF->getTarget().getTargetAsmInfo();
2837 FinalSize += AI->getInlineAsmLength(AsmStr);
2840 case TargetInstrInfo::DBG_LABEL:
2841 case TargetInstrInfo::EH_LABEL:
2843 case TargetInstrInfo::IMPLICIT_DEF:
2844 case TargetInstrInfo::DECLARE:
2845 case X86::DWARF_LOC:
2846 case X86::FP_REG_KILL:
2848 case X86::MOVPC32r: {
2849 // This emits the "call" portion of this pseudo instruction.
2851 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2855 case X86::TLS_gs_ri:
2857 FinalSize += sizeGlobalAddress(false);
2865 if (CurOp != NumOps) {
2866 const MachineOperand &MO = MI.getOperand(CurOp++);
2868 FinalSize += sizePCRelativeBlockAddress();
2869 } else if (MO.isGlobal()) {
2870 FinalSize += sizeGlobalAddress(false);
2871 } else if (MO.isSymbol()) {
2872 FinalSize += sizeExternalSymbolAddress(false);
2873 } else if (MO.isImm()) {
2874 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2876 assert(0 && "Unknown RawFrm operand!");
2881 case X86II::AddRegFrm:
2885 if (CurOp != NumOps) {
2886 const MachineOperand &MO1 = MI.getOperand(CurOp++);
2887 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
2889 FinalSize += sizeConstant(Size);
2892 if (Opcode == X86::MOV64ri)
2894 if (MO1.isGlobal()) {
2895 FinalSize += sizeGlobalAddress(dword);
2896 } else if (MO1.isSymbol())
2897 FinalSize += sizeExternalSymbolAddress(dword);
2898 else if (MO1.isCPI())
2899 FinalSize += sizeConstPoolAddress(dword);
2900 else if (MO1.isJTI())
2901 FinalSize += sizeJumpTableAddress(dword);
2906 case X86II::MRMDestReg: {
2908 FinalSize += sizeRegModRMByte();
2910 if (CurOp != NumOps) {
2912 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2916 case X86II::MRMDestMem: {
2918 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
2920 if (CurOp != NumOps) {
2922 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2927 case X86II::MRMSrcReg:
2929 FinalSize += sizeRegModRMByte();
2931 if (CurOp != NumOps) {
2933 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2937 case X86II::MRMSrcMem: {
2940 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
2942 if (CurOp != NumOps) {
2944 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2949 case X86II::MRM0r: case X86II::MRM1r:
2950 case X86II::MRM2r: case X86II::MRM3r:
2951 case X86II::MRM4r: case X86II::MRM5r:
2952 case X86II::MRM6r: case X86II::MRM7r:
2955 FinalSize += sizeRegModRMByte();
2957 if (CurOp != NumOps) {
2958 const MachineOperand &MO1 = MI.getOperand(CurOp++);
2959 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
2961 FinalSize += sizeConstant(Size);
2964 if (Opcode == X86::MOV64ri32)
2966 if (MO1.isGlobal()) {
2967 FinalSize += sizeGlobalAddress(dword);
2968 } else if (MO1.isSymbol())
2969 FinalSize += sizeExternalSymbolAddress(dword);
2970 else if (MO1.isCPI())
2971 FinalSize += sizeConstPoolAddress(dword);
2972 else if (MO1.isJTI())
2973 FinalSize += sizeJumpTableAddress(dword);
2978 case X86II::MRM0m: case X86II::MRM1m:
2979 case X86II::MRM2m: case X86II::MRM3m:
2980 case X86II::MRM4m: case X86II::MRM5m:
2981 case X86II::MRM6m: case X86II::MRM7m: {
2984 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
2987 if (CurOp != NumOps) {
2988 const MachineOperand &MO = MI.getOperand(CurOp++);
2989 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
2991 FinalSize += sizeConstant(Size);
2994 if (Opcode == X86::MOV64mi32)
2996 if (MO.isGlobal()) {
2997 FinalSize += sizeGlobalAddress(dword);
2998 } else if (MO.isSymbol())
2999 FinalSize += sizeExternalSymbolAddress(dword);
3000 else if (MO.isCPI())
3001 FinalSize += sizeConstPoolAddress(dword);
3002 else if (MO.isJTI())
3003 FinalSize += sizeJumpTableAddress(dword);
3009 case X86II::MRMInitReg:
3011 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
3012 FinalSize += sizeRegModRMByte();
3017 if (!Desc->isVariadic() && CurOp != NumOps) {
3018 cerr << "Cannot determine size: ";
3029 unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
3030 const TargetInstrDesc &Desc = MI->getDesc();
3031 bool IsPIC = (TM.getRelocationModel() == Reloc::PIC_);
3032 bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
3033 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
3034 if (Desc.getOpcode() == X86::MOVPC32r) {
3035 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);
3040 /// getGlobalBaseReg - Return a virtual register initialized with the
3041 /// the global base register value. Output instructions required to
3042 /// initialize the register in the function entry block, if necessary.
3044 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3045 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3046 "X86-64 PIC uses RIP relative addressing");
3048 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3049 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3050 if (GlobalBaseReg != 0)
3051 return GlobalBaseReg;
3053 // Insert the set of GlobalBaseReg into the first MBB of the function
3054 MachineBasicBlock &FirstMBB = MF->front();
3055 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3056 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3057 unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3059 const TargetInstrInfo *TII = TM.getInstrInfo();
3060 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3061 // only used in JIT code emission as displacement to pc.
3062 BuildMI(FirstMBB, MBBI, TII->get(X86::MOVPC32r), PC).addImm(0);
3064 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3065 // not to pc, but to _GLOBAL_ADDRESS_TABLE_ external
3066 if (TM.getRelocationModel() == Reloc::PIC_ &&
3067 TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3069 RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3070 BuildMI(FirstMBB, MBBI, TII->get(X86::ADD32ri), GlobalBaseReg)
3071 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_");
3076 X86FI->setGlobalBaseReg(GlobalBaseReg);
3077 return GlobalBaseReg;