1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/LiveVariables.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/MC/MCAsmInfo.h"
42 NoFusing("disable-spill-fusing",
43 cl::desc("Disable fusing of spill code into instructions"));
45 PrintFailedFusing("print-failed-fuse-candidates",
46 cl::desc("Print instructions that the allocator wants to"
47 " fuse, but the X86 backend currently can't"),
50 ReMatPICStubLoad("remat-pic-stub-load",
51 cl::desc("Re-materialize load from stub in PIC mode"),
52 cl::init(false), cl::Hidden);
54 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
55 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
56 TM(tm), RI(tm, *this) {
57 SmallVector<unsigned,16> AmbEntries;
58 static const unsigned OpTbl2Addr[][2] = {
59 { X86::ADC32ri, X86::ADC32mi },
60 { X86::ADC32ri8, X86::ADC32mi8 },
61 { X86::ADC32rr, X86::ADC32mr },
62 { X86::ADC64ri32, X86::ADC64mi32 },
63 { X86::ADC64ri8, X86::ADC64mi8 },
64 { X86::ADC64rr, X86::ADC64mr },
65 { X86::ADD16ri, X86::ADD16mi },
66 { X86::ADD16ri8, X86::ADD16mi8 },
67 { X86::ADD16rr, X86::ADD16mr },
68 { X86::ADD32ri, X86::ADD32mi },
69 { X86::ADD32ri8, X86::ADD32mi8 },
70 { X86::ADD32rr, X86::ADD32mr },
71 { X86::ADD64ri32, X86::ADD64mi32 },
72 { X86::ADD64ri8, X86::ADD64mi8 },
73 { X86::ADD64rr, X86::ADD64mr },
74 { X86::ADD8ri, X86::ADD8mi },
75 { X86::ADD8rr, X86::ADD8mr },
76 { X86::AND16ri, X86::AND16mi },
77 { X86::AND16ri8, X86::AND16mi8 },
78 { X86::AND16rr, X86::AND16mr },
79 { X86::AND32ri, X86::AND32mi },
80 { X86::AND32ri8, X86::AND32mi8 },
81 { X86::AND32rr, X86::AND32mr },
82 { X86::AND64ri32, X86::AND64mi32 },
83 { X86::AND64ri8, X86::AND64mi8 },
84 { X86::AND64rr, X86::AND64mr },
85 { X86::AND8ri, X86::AND8mi },
86 { X86::AND8rr, X86::AND8mr },
87 { X86::DEC16r, X86::DEC16m },
88 { X86::DEC32r, X86::DEC32m },
89 { X86::DEC64_16r, X86::DEC64_16m },
90 { X86::DEC64_32r, X86::DEC64_32m },
91 { X86::DEC64r, X86::DEC64m },
92 { X86::DEC8r, X86::DEC8m },
93 { X86::INC16r, X86::INC16m },
94 { X86::INC32r, X86::INC32m },
95 { X86::INC64_16r, X86::INC64_16m },
96 { X86::INC64_32r, X86::INC64_32m },
97 { X86::INC64r, X86::INC64m },
98 { X86::INC8r, X86::INC8m },
99 { X86::NEG16r, X86::NEG16m },
100 { X86::NEG32r, X86::NEG32m },
101 { X86::NEG64r, X86::NEG64m },
102 { X86::NEG8r, X86::NEG8m },
103 { X86::NOT16r, X86::NOT16m },
104 { X86::NOT32r, X86::NOT32m },
105 { X86::NOT64r, X86::NOT64m },
106 { X86::NOT8r, X86::NOT8m },
107 { X86::OR16ri, X86::OR16mi },
108 { X86::OR16ri8, X86::OR16mi8 },
109 { X86::OR16rr, X86::OR16mr },
110 { X86::OR32ri, X86::OR32mi },
111 { X86::OR32ri8, X86::OR32mi8 },
112 { X86::OR32rr, X86::OR32mr },
113 { X86::OR64ri32, X86::OR64mi32 },
114 { X86::OR64ri8, X86::OR64mi8 },
115 { X86::OR64rr, X86::OR64mr },
116 { X86::OR8ri, X86::OR8mi },
117 { X86::OR8rr, X86::OR8mr },
118 { X86::ROL16r1, X86::ROL16m1 },
119 { X86::ROL16rCL, X86::ROL16mCL },
120 { X86::ROL16ri, X86::ROL16mi },
121 { X86::ROL32r1, X86::ROL32m1 },
122 { X86::ROL32rCL, X86::ROL32mCL },
123 { X86::ROL32ri, X86::ROL32mi },
124 { X86::ROL64r1, X86::ROL64m1 },
125 { X86::ROL64rCL, X86::ROL64mCL },
126 { X86::ROL64ri, X86::ROL64mi },
127 { X86::ROL8r1, X86::ROL8m1 },
128 { X86::ROL8rCL, X86::ROL8mCL },
129 { X86::ROL8ri, X86::ROL8mi },
130 { X86::ROR16r1, X86::ROR16m1 },
131 { X86::ROR16rCL, X86::ROR16mCL },
132 { X86::ROR16ri, X86::ROR16mi },
133 { X86::ROR32r1, X86::ROR32m1 },
134 { X86::ROR32rCL, X86::ROR32mCL },
135 { X86::ROR32ri, X86::ROR32mi },
136 { X86::ROR64r1, X86::ROR64m1 },
137 { X86::ROR64rCL, X86::ROR64mCL },
138 { X86::ROR64ri, X86::ROR64mi },
139 { X86::ROR8r1, X86::ROR8m1 },
140 { X86::ROR8rCL, X86::ROR8mCL },
141 { X86::ROR8ri, X86::ROR8mi },
142 { X86::SAR16r1, X86::SAR16m1 },
143 { X86::SAR16rCL, X86::SAR16mCL },
144 { X86::SAR16ri, X86::SAR16mi },
145 { X86::SAR32r1, X86::SAR32m1 },
146 { X86::SAR32rCL, X86::SAR32mCL },
147 { X86::SAR32ri, X86::SAR32mi },
148 { X86::SAR64r1, X86::SAR64m1 },
149 { X86::SAR64rCL, X86::SAR64mCL },
150 { X86::SAR64ri, X86::SAR64mi },
151 { X86::SAR8r1, X86::SAR8m1 },
152 { X86::SAR8rCL, X86::SAR8mCL },
153 { X86::SAR8ri, X86::SAR8mi },
154 { X86::SBB32ri, X86::SBB32mi },
155 { X86::SBB32ri8, X86::SBB32mi8 },
156 { X86::SBB32rr, X86::SBB32mr },
157 { X86::SBB64ri32, X86::SBB64mi32 },
158 { X86::SBB64ri8, X86::SBB64mi8 },
159 { X86::SBB64rr, X86::SBB64mr },
160 { X86::SHL16rCL, X86::SHL16mCL },
161 { X86::SHL16ri, X86::SHL16mi },
162 { X86::SHL32rCL, X86::SHL32mCL },
163 { X86::SHL32ri, X86::SHL32mi },
164 { X86::SHL64rCL, X86::SHL64mCL },
165 { X86::SHL64ri, X86::SHL64mi },
166 { X86::SHL8rCL, X86::SHL8mCL },
167 { X86::SHL8ri, X86::SHL8mi },
168 { X86::SHLD16rrCL, X86::SHLD16mrCL },
169 { X86::SHLD16rri8, X86::SHLD16mri8 },
170 { X86::SHLD32rrCL, X86::SHLD32mrCL },
171 { X86::SHLD32rri8, X86::SHLD32mri8 },
172 { X86::SHLD64rrCL, X86::SHLD64mrCL },
173 { X86::SHLD64rri8, X86::SHLD64mri8 },
174 { X86::SHR16r1, X86::SHR16m1 },
175 { X86::SHR16rCL, X86::SHR16mCL },
176 { X86::SHR16ri, X86::SHR16mi },
177 { X86::SHR32r1, X86::SHR32m1 },
178 { X86::SHR32rCL, X86::SHR32mCL },
179 { X86::SHR32ri, X86::SHR32mi },
180 { X86::SHR64r1, X86::SHR64m1 },
181 { X86::SHR64rCL, X86::SHR64mCL },
182 { X86::SHR64ri, X86::SHR64mi },
183 { X86::SHR8r1, X86::SHR8m1 },
184 { X86::SHR8rCL, X86::SHR8mCL },
185 { X86::SHR8ri, X86::SHR8mi },
186 { X86::SHRD16rrCL, X86::SHRD16mrCL },
187 { X86::SHRD16rri8, X86::SHRD16mri8 },
188 { X86::SHRD32rrCL, X86::SHRD32mrCL },
189 { X86::SHRD32rri8, X86::SHRD32mri8 },
190 { X86::SHRD64rrCL, X86::SHRD64mrCL },
191 { X86::SHRD64rri8, X86::SHRD64mri8 },
192 { X86::SUB16ri, X86::SUB16mi },
193 { X86::SUB16ri8, X86::SUB16mi8 },
194 { X86::SUB16rr, X86::SUB16mr },
195 { X86::SUB32ri, X86::SUB32mi },
196 { X86::SUB32ri8, X86::SUB32mi8 },
197 { X86::SUB32rr, X86::SUB32mr },
198 { X86::SUB64ri32, X86::SUB64mi32 },
199 { X86::SUB64ri8, X86::SUB64mi8 },
200 { X86::SUB64rr, X86::SUB64mr },
201 { X86::SUB8ri, X86::SUB8mi },
202 { X86::SUB8rr, X86::SUB8mr },
203 { X86::XOR16ri, X86::XOR16mi },
204 { X86::XOR16ri8, X86::XOR16mi8 },
205 { X86::XOR16rr, X86::XOR16mr },
206 { X86::XOR32ri, X86::XOR32mi },
207 { X86::XOR32ri8, X86::XOR32mi8 },
208 { X86::XOR32rr, X86::XOR32mr },
209 { X86::XOR64ri32, X86::XOR64mi32 },
210 { X86::XOR64ri8, X86::XOR64mi8 },
211 { X86::XOR64rr, X86::XOR64mr },
212 { X86::XOR8ri, X86::XOR8mi },
213 { X86::XOR8rr, X86::XOR8mr }
216 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
217 unsigned RegOp = OpTbl2Addr[i][0];
218 unsigned MemOp = OpTbl2Addr[i][1];
219 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
220 std::make_pair(MemOp,0))).second)
221 assert(false && "Duplicated entries?");
222 // Index 0, folded load and store, no alignment requirement.
223 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
224 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
225 std::make_pair(RegOp,
227 AmbEntries.push_back(MemOp);
230 // If the third value is 1, then it's folding either a load or a store.
231 static const unsigned OpTbl0[][4] = {
232 { X86::BT16ri8, X86::BT16mi8, 1, 0 },
233 { X86::BT32ri8, X86::BT32mi8, 1, 0 },
234 { X86::BT64ri8, X86::BT64mi8, 1, 0 },
235 { X86::CALL32r, X86::CALL32m, 1, 0 },
236 { X86::CALL64r, X86::CALL64m, 1, 0 },
237 { X86::CMP16ri, X86::CMP16mi, 1, 0 },
238 { X86::CMP16ri8, X86::CMP16mi8, 1, 0 },
239 { X86::CMP16rr, X86::CMP16mr, 1, 0 },
240 { X86::CMP32ri, X86::CMP32mi, 1, 0 },
241 { X86::CMP32ri8, X86::CMP32mi8, 1, 0 },
242 { X86::CMP32rr, X86::CMP32mr, 1, 0 },
243 { X86::CMP64ri32, X86::CMP64mi32, 1, 0 },
244 { X86::CMP64ri8, X86::CMP64mi8, 1, 0 },
245 { X86::CMP64rr, X86::CMP64mr, 1, 0 },
246 { X86::CMP8ri, X86::CMP8mi, 1, 0 },
247 { X86::CMP8rr, X86::CMP8mr, 1, 0 },
248 { X86::DIV16r, X86::DIV16m, 1, 0 },
249 { X86::DIV32r, X86::DIV32m, 1, 0 },
250 { X86::DIV64r, X86::DIV64m, 1, 0 },
251 { X86::DIV8r, X86::DIV8m, 1, 0 },
252 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 },
253 { X86::FsMOVAPDrr, X86::MOVSDmr, 0, 0 },
254 { X86::FsMOVAPSrr, X86::MOVSSmr, 0, 0 },
255 { X86::IDIV16r, X86::IDIV16m, 1, 0 },
256 { X86::IDIV32r, X86::IDIV32m, 1, 0 },
257 { X86::IDIV64r, X86::IDIV64m, 1, 0 },
258 { X86::IDIV8r, X86::IDIV8m, 1, 0 },
259 { X86::IMUL16r, X86::IMUL16m, 1, 0 },
260 { X86::IMUL32r, X86::IMUL32m, 1, 0 },
261 { X86::IMUL64r, X86::IMUL64m, 1, 0 },
262 { X86::IMUL8r, X86::IMUL8m, 1, 0 },
263 { X86::JMP32r, X86::JMP32m, 1, 0 },
264 { X86::JMP64r, X86::JMP64m, 1, 0 },
265 { X86::MOV16ri, X86::MOV16mi, 0, 0 },
266 { X86::MOV16rr, X86::MOV16mr, 0, 0 },
267 { X86::MOV32ri, X86::MOV32mi, 0, 0 },
268 { X86::MOV32rr, X86::MOV32mr, 0, 0 },
269 { X86::MOV32rr_TC, X86::MOV32mr_TC, 0, 0 },
270 { X86::MOV64ri32, X86::MOV64mi32, 0, 0 },
271 { X86::MOV64rr, X86::MOV64mr, 0, 0 },
272 { X86::MOV8ri, X86::MOV8mi, 0, 0 },
273 { X86::MOV8rr, X86::MOV8mr, 0, 0 },
274 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 },
275 { X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 },
276 { X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 },
277 { X86::MOVDQArr, X86::MOVDQAmr, 0, 16 },
278 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 },
279 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 },
280 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 },
281 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 },
282 { X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 },
283 { X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 },
284 { X86::MUL16r, X86::MUL16m, 1, 0 },
285 { X86::MUL32r, X86::MUL32m, 1, 0 },
286 { X86::MUL64r, X86::MUL64m, 1, 0 },
287 { X86::MUL8r, X86::MUL8m, 1, 0 },
288 { X86::SETAEr, X86::SETAEm, 0, 0 },
289 { X86::SETAr, X86::SETAm, 0, 0 },
290 { X86::SETBEr, X86::SETBEm, 0, 0 },
291 { X86::SETBr, X86::SETBm, 0, 0 },
292 { X86::SETEr, X86::SETEm, 0, 0 },
293 { X86::SETGEr, X86::SETGEm, 0, 0 },
294 { X86::SETGr, X86::SETGm, 0, 0 },
295 { X86::SETLEr, X86::SETLEm, 0, 0 },
296 { X86::SETLr, X86::SETLm, 0, 0 },
297 { X86::SETNEr, X86::SETNEm, 0, 0 },
298 { X86::SETNOr, X86::SETNOm, 0, 0 },
299 { X86::SETNPr, X86::SETNPm, 0, 0 },
300 { X86::SETNSr, X86::SETNSm, 0, 0 },
301 { X86::SETOr, X86::SETOm, 0, 0 },
302 { X86::SETPr, X86::SETPm, 0, 0 },
303 { X86::SETSr, X86::SETSm, 0, 0 },
304 { X86::TAILJMPr, X86::TAILJMPm, 1, 0 },
305 { X86::TAILJMPr64, X86::TAILJMPm64, 1, 0 },
306 { X86::TEST16ri, X86::TEST16mi, 1, 0 },
307 { X86::TEST32ri, X86::TEST32mi, 1, 0 },
308 { X86::TEST64ri32, X86::TEST64mi32, 1, 0 },
309 { X86::TEST8ri, X86::TEST8mi, 1, 0 }
312 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
313 unsigned RegOp = OpTbl0[i][0];
314 unsigned MemOp = OpTbl0[i][1];
315 unsigned Align = OpTbl0[i][3];
316 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
317 std::make_pair(MemOp,Align))).second)
318 assert(false && "Duplicated entries?");
319 unsigned FoldedLoad = OpTbl0[i][2];
320 // Index 0, folded load or store.
321 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
322 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
323 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
324 std::make_pair(RegOp, AuxInfo))).second)
325 AmbEntries.push_back(MemOp);
328 static const unsigned OpTbl1[][3] = {
329 { X86::CMP16rr, X86::CMP16rm, 0 },
330 { X86::CMP32rr, X86::CMP32rm, 0 },
331 { X86::CMP64rr, X86::CMP64rm, 0 },
332 { X86::CMP8rr, X86::CMP8rm, 0 },
333 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
334 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
335 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
336 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
337 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
338 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
339 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
340 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
341 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
342 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
343 { X86::FsMOVAPDrr, X86::MOVSDrm, 0 },
344 { X86::FsMOVAPSrr, X86::MOVSSrm, 0 },
345 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
346 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
347 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
348 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
349 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
350 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
351 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
352 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
353 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
354 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
355 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 },
356 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 },
357 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 },
358 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 },
359 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 },
360 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
361 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm, 0 },
362 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm, 0 },
363 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
364 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
365 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
366 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
367 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
368 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
369 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 },
370 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm, 0 },
371 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, 16 },
372 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, 16 },
373 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
374 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
375 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
376 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
377 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
378 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
379 { X86::MOV16rr, X86::MOV16rm, 0 },
380 { X86::MOV32rr, X86::MOV32rm, 0 },
381 { X86::MOV32rr_TC, X86::MOV32rm_TC, 0 },
382 { X86::MOV64rr, X86::MOV64rm, 0 },
383 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
384 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
385 { X86::MOV8rr, X86::MOV8rm, 0 },
386 { X86::MOVAPDrr, X86::MOVAPDrm, 16 },
387 { X86::MOVAPSrr, X86::MOVAPSrm, 16 },
388 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
389 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
390 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
391 { X86::MOVDQArr, X86::MOVDQArm, 16 },
392 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 },
393 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 },
394 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
395 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
396 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
397 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
398 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
399 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
400 { X86::MOVUPDrr, X86::MOVUPDrm, 16 },
401 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
402 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
403 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
404 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 },
405 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
406 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
407 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
408 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
409 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
410 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
411 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
412 { X86::PSHUFDri, X86::PSHUFDmi, 16 },
413 { X86::PSHUFHWri, X86::PSHUFHWmi, 16 },
414 { X86::PSHUFLWri, X86::PSHUFLWmi, 16 },
415 { X86::RCPPSr, X86::RCPPSm, 16 },
416 { X86::RCPPSr_Int, X86::RCPPSm_Int, 16 },
417 { X86::RSQRTPSr, X86::RSQRTPSm, 16 },
418 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 },
419 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
420 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
421 { X86::SQRTPDr, X86::SQRTPDm, 16 },
422 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 },
423 { X86::SQRTPSr, X86::SQRTPSm, 16 },
424 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 },
425 { X86::SQRTSDr, X86::SQRTSDm, 0 },
426 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
427 { X86::SQRTSSr, X86::SQRTSSm, 0 },
428 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
429 { X86::TEST16rr, X86::TEST16rm, 0 },
430 { X86::TEST32rr, X86::TEST32rm, 0 },
431 { X86::TEST64rr, X86::TEST64rm, 0 },
432 { X86::TEST8rr, X86::TEST8rm, 0 },
433 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
434 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
435 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }
438 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
439 unsigned RegOp = OpTbl1[i][0];
440 unsigned MemOp = OpTbl1[i][1];
441 unsigned Align = OpTbl1[i][2];
442 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
443 std::make_pair(MemOp,Align))).second)
444 assert(false && "Duplicated entries?");
445 // Index 1, folded load
446 unsigned AuxInfo = 1 | (1 << 4);
447 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
448 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
449 std::make_pair(RegOp, AuxInfo))).second)
450 AmbEntries.push_back(MemOp);
453 static const unsigned OpTbl2[][3] = {
454 { X86::ADC32rr, X86::ADC32rm, 0 },
455 { X86::ADC64rr, X86::ADC64rm, 0 },
456 { X86::ADD16rr, X86::ADD16rm, 0 },
457 { X86::ADD32rr, X86::ADD32rm, 0 },
458 { X86::ADD64rr, X86::ADD64rm, 0 },
459 { X86::ADD8rr, X86::ADD8rm, 0 },
460 { X86::ADDPDrr, X86::ADDPDrm, 16 },
461 { X86::ADDPSrr, X86::ADDPSrm, 16 },
462 { X86::ADDSDrr, X86::ADDSDrm, 0 },
463 { X86::ADDSSrr, X86::ADDSSrm, 0 },
464 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 },
465 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 },
466 { X86::AND16rr, X86::AND16rm, 0 },
467 { X86::AND32rr, X86::AND32rm, 0 },
468 { X86::AND64rr, X86::AND64rm, 0 },
469 { X86::AND8rr, X86::AND8rm, 0 },
470 { X86::ANDNPDrr, X86::ANDNPDrm, 16 },
471 { X86::ANDNPSrr, X86::ANDNPSrm, 16 },
472 { X86::ANDPDrr, X86::ANDPDrm, 16 },
473 { X86::ANDPSrr, X86::ANDPSrm, 16 },
474 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
475 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
476 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
477 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
478 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
479 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
480 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
481 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
482 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
483 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
484 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
485 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
486 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
487 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
488 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
489 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
490 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
491 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
492 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
493 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
494 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
495 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
496 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
497 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
498 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
499 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
500 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
501 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
502 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
503 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
504 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
505 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
506 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
507 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
508 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
509 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
510 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
511 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
512 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
513 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
514 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
515 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
516 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
517 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
518 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
519 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
520 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
521 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
522 { X86::CMPPDrri, X86::CMPPDrmi, 16 },
523 { X86::CMPPSrri, X86::CMPPSrmi, 16 },
524 { X86::CMPSDrr, X86::CMPSDrm, 0 },
525 { X86::CMPSSrr, X86::CMPSSrm, 0 },
526 { X86::DIVPDrr, X86::DIVPDrm, 16 },
527 { X86::DIVPSrr, X86::DIVPSrm, 16 },
528 { X86::DIVSDrr, X86::DIVSDrm, 0 },
529 { X86::DIVSSrr, X86::DIVSSrm, 0 },
530 { X86::FsANDNPDrr, X86::FsANDNPDrm, 16 },
531 { X86::FsANDNPSrr, X86::FsANDNPSrm, 16 },
532 { X86::FsANDPDrr, X86::FsANDPDrm, 16 },
533 { X86::FsANDPSrr, X86::FsANDPSrm, 16 },
534 { X86::FsORPDrr, X86::FsORPDrm, 16 },
535 { X86::FsORPSrr, X86::FsORPSrm, 16 },
536 { X86::FsXORPDrr, X86::FsXORPDrm, 16 },
537 { X86::FsXORPSrr, X86::FsXORPSrm, 16 },
538 { X86::HADDPDrr, X86::HADDPDrm, 16 },
539 { X86::HADDPSrr, X86::HADDPSrm, 16 },
540 { X86::HSUBPDrr, X86::HSUBPDrm, 16 },
541 { X86::HSUBPSrr, X86::HSUBPSrm, 16 },
542 { X86::IMUL16rr, X86::IMUL16rm, 0 },
543 { X86::IMUL32rr, X86::IMUL32rm, 0 },
544 { X86::IMUL64rr, X86::IMUL64rm, 0 },
545 { X86::MAXPDrr, X86::MAXPDrm, 16 },
546 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 },
547 { X86::MAXPSrr, X86::MAXPSrm, 16 },
548 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 },
549 { X86::MAXSDrr, X86::MAXSDrm, 0 },
550 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
551 { X86::MAXSSrr, X86::MAXSSrm, 0 },
552 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
553 { X86::MINPDrr, X86::MINPDrm, 16 },
554 { X86::MINPDrr_Int, X86::MINPDrm_Int, 16 },
555 { X86::MINPSrr, X86::MINPSrm, 16 },
556 { X86::MINPSrr_Int, X86::MINPSrm_Int, 16 },
557 { X86::MINSDrr, X86::MINSDrm, 0 },
558 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
559 { X86::MINSSrr, X86::MINSSrm, 0 },
560 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
561 { X86::MULPDrr, X86::MULPDrm, 16 },
562 { X86::MULPSrr, X86::MULPSrm, 16 },
563 { X86::MULSDrr, X86::MULSDrm, 0 },
564 { X86::MULSSrr, X86::MULSSrm, 0 },
565 { X86::OR16rr, X86::OR16rm, 0 },
566 { X86::OR32rr, X86::OR32rm, 0 },
567 { X86::OR64rr, X86::OR64rm, 0 },
568 { X86::OR8rr, X86::OR8rm, 0 },
569 { X86::ORPDrr, X86::ORPDrm, 16 },
570 { X86::ORPSrr, X86::ORPSrm, 16 },
571 { X86::PACKSSDWrr, X86::PACKSSDWrm, 16 },
572 { X86::PACKSSWBrr, X86::PACKSSWBrm, 16 },
573 { X86::PACKUSWBrr, X86::PACKUSWBrm, 16 },
574 { X86::PADDBrr, X86::PADDBrm, 16 },
575 { X86::PADDDrr, X86::PADDDrm, 16 },
576 { X86::PADDQrr, X86::PADDQrm, 16 },
577 { X86::PADDSBrr, X86::PADDSBrm, 16 },
578 { X86::PADDSWrr, X86::PADDSWrm, 16 },
579 { X86::PADDWrr, X86::PADDWrm, 16 },
580 { X86::PANDNrr, X86::PANDNrm, 16 },
581 { X86::PANDrr, X86::PANDrm, 16 },
582 { X86::PAVGBrr, X86::PAVGBrm, 16 },
583 { X86::PAVGWrr, X86::PAVGWrm, 16 },
584 { X86::PCMPEQBrr, X86::PCMPEQBrm, 16 },
585 { X86::PCMPEQDrr, X86::PCMPEQDrm, 16 },
586 { X86::PCMPEQWrr, X86::PCMPEQWrm, 16 },
587 { X86::PCMPGTBrr, X86::PCMPGTBrm, 16 },
588 { X86::PCMPGTDrr, X86::PCMPGTDrm, 16 },
589 { X86::PCMPGTWrr, X86::PCMPGTWrm, 16 },
590 { X86::PINSRWrri, X86::PINSRWrmi, 16 },
591 { X86::PMADDWDrr, X86::PMADDWDrm, 16 },
592 { X86::PMAXSWrr, X86::PMAXSWrm, 16 },
593 { X86::PMAXUBrr, X86::PMAXUBrm, 16 },
594 { X86::PMINSWrr, X86::PMINSWrm, 16 },
595 { X86::PMINUBrr, X86::PMINUBrm, 16 },
596 { X86::PMULDQrr, X86::PMULDQrm, 16 },
597 { X86::PMULHUWrr, X86::PMULHUWrm, 16 },
598 { X86::PMULHWrr, X86::PMULHWrm, 16 },
599 { X86::PMULLDrr, X86::PMULLDrm, 16 },
600 { X86::PMULLDrr_int, X86::PMULLDrm_int, 16 },
601 { X86::PMULLWrr, X86::PMULLWrm, 16 },
602 { X86::PMULUDQrr, X86::PMULUDQrm, 16 },
603 { X86::PORrr, X86::PORrm, 16 },
604 { X86::PSADBWrr, X86::PSADBWrm, 16 },
605 { X86::PSLLDrr, X86::PSLLDrm, 16 },
606 { X86::PSLLQrr, X86::PSLLQrm, 16 },
607 { X86::PSLLWrr, X86::PSLLWrm, 16 },
608 { X86::PSRADrr, X86::PSRADrm, 16 },
609 { X86::PSRAWrr, X86::PSRAWrm, 16 },
610 { X86::PSRLDrr, X86::PSRLDrm, 16 },
611 { X86::PSRLQrr, X86::PSRLQrm, 16 },
612 { X86::PSRLWrr, X86::PSRLWrm, 16 },
613 { X86::PSUBBrr, X86::PSUBBrm, 16 },
614 { X86::PSUBDrr, X86::PSUBDrm, 16 },
615 { X86::PSUBSBrr, X86::PSUBSBrm, 16 },
616 { X86::PSUBSWrr, X86::PSUBSWrm, 16 },
617 { X86::PSUBWrr, X86::PSUBWrm, 16 },
618 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 },
619 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 },
620 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 },
621 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 },
622 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 },
623 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 },
624 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 },
625 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 },
626 { X86::PXORrr, X86::PXORrm, 16 },
627 { X86::SBB32rr, X86::SBB32rm, 0 },
628 { X86::SBB64rr, X86::SBB64rm, 0 },
629 { X86::SHUFPDrri, X86::SHUFPDrmi, 16 },
630 { X86::SHUFPSrri, X86::SHUFPSrmi, 16 },
631 { X86::SUB16rr, X86::SUB16rm, 0 },
632 { X86::SUB32rr, X86::SUB32rm, 0 },
633 { X86::SUB64rr, X86::SUB64rm, 0 },
634 { X86::SUB8rr, X86::SUB8rm, 0 },
635 { X86::SUBPDrr, X86::SUBPDrm, 16 },
636 { X86::SUBPSrr, X86::SUBPSrm, 16 },
637 { X86::SUBSDrr, X86::SUBSDrm, 0 },
638 { X86::SUBSSrr, X86::SUBSSrm, 0 },
639 // FIXME: TEST*rr -> swapped operand of TEST*mr.
640 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 },
641 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 },
642 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 },
643 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 },
644 { X86::XOR16rr, X86::XOR16rm, 0 },
645 { X86::XOR32rr, X86::XOR32rm, 0 },
646 { X86::XOR64rr, X86::XOR64rm, 0 },
647 { X86::XOR8rr, X86::XOR8rm, 0 },
648 { X86::XORPDrr, X86::XORPDrm, 16 },
649 { X86::XORPSrr, X86::XORPSrm, 16 }
652 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
653 unsigned RegOp = OpTbl2[i][0];
654 unsigned MemOp = OpTbl2[i][1];
655 unsigned Align = OpTbl2[i][2];
656 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
657 std::make_pair(MemOp,Align))).second)
658 assert(false && "Duplicated entries?");
659 // Index 2, folded load
660 unsigned AuxInfo = 2 | (1 << 4);
661 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
662 std::make_pair(RegOp, AuxInfo))).second)
663 AmbEntries.push_back(MemOp);
666 // Remove ambiguous entries.
667 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
670 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
671 unsigned &SrcReg, unsigned &DstReg,
672 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
673 switch (MI.getOpcode()) {
677 case X86::MOV8rr_NOREX:
681 case X86::MOV32rr_TC:
682 case X86::MOV64rr_TC:
684 // FP Stack register class copies
685 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
686 case X86::MOV_Fp3264: case X86::MOV_Fp3280:
687 case X86::MOV_Fp6432: case X86::MOV_Fp8032:
689 // Note that MOVSSrr and MOVSDrr are not considered copies. FR32 and FR64
690 // copies are done with FsMOVAPSrr and FsMOVAPDrr.
692 case X86::FsMOVAPSrr:
693 case X86::FsMOVAPDrr:
697 case X86::MMX_MOVQ64rr:
698 assert(MI.getNumOperands() >= 2 &&
699 MI.getOperand(0).isReg() &&
700 MI.getOperand(1).isReg() &&
701 "invalid register-register move instruction");
702 SrcReg = MI.getOperand(1).getReg();
703 DstReg = MI.getOperand(0).getReg();
704 SrcSubIdx = MI.getOperand(1).getSubReg();
705 DstSubIdx = MI.getOperand(0).getSubReg();
711 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
712 unsigned &SrcReg, unsigned &DstReg,
713 unsigned &SubIdx) const {
714 switch (MI.getOpcode()) {
716 case X86::MOVSX16rr8:
717 case X86::MOVZX16rr8:
718 case X86::MOVSX32rr8:
719 case X86::MOVZX32rr8:
720 case X86::MOVSX64rr8:
721 case X86::MOVZX64rr8:
722 if (!TM.getSubtarget<X86Subtarget>().is64Bit())
723 // It's not always legal to reference the low 8-bit of the larger
724 // register in 32-bit mode.
726 case X86::MOVSX32rr16:
727 case X86::MOVZX32rr16:
728 case X86::MOVSX64rr16:
729 case X86::MOVZX64rr16:
730 case X86::MOVSX64rr32:
731 case X86::MOVZX64rr32: {
732 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
735 SrcReg = MI.getOperand(1).getReg();
736 DstReg = MI.getOperand(0).getReg();
737 switch (MI.getOpcode()) {
741 case X86::MOVSX16rr8:
742 case X86::MOVZX16rr8:
743 case X86::MOVSX32rr8:
744 case X86::MOVZX32rr8:
745 case X86::MOVSX64rr8:
746 case X86::MOVZX64rr8:
749 case X86::MOVSX32rr16:
750 case X86::MOVZX32rr16:
751 case X86::MOVSX64rr16:
752 case X86::MOVZX64rr16:
755 case X86::MOVSX64rr32:
756 case X86::MOVZX64rr32:
766 /// isFrameOperand - Return true and the FrameIndex if the specified
767 /// operand and follow operands form a reference to the stack frame.
768 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
769 int &FrameIndex) const {
770 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
771 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
772 MI->getOperand(Op+1).getImm() == 1 &&
773 MI->getOperand(Op+2).getReg() == 0 &&
774 MI->getOperand(Op+3).getImm() == 0) {
775 FrameIndex = MI->getOperand(Op).getIndex();
781 static bool isFrameLoadOpcode(int Opcode) {
794 case X86::MMX_MOVD64rm:
795 case X86::MMX_MOVQ64rm:
802 static bool isFrameStoreOpcode(int Opcode) {
815 case X86::MMX_MOVD64mr:
816 case X86::MMX_MOVQ64mr:
817 case X86::MMX_MOVNTQmr:
823 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
824 int &FrameIndex) const {
825 if (isFrameLoadOpcode(MI->getOpcode()))
826 if (isFrameOperand(MI, 1, FrameIndex))
827 return MI->getOperand(0).getReg();
831 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
832 int &FrameIndex) const {
833 if (isFrameLoadOpcode(MI->getOpcode())) {
835 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
837 // Check for post-frame index elimination operations
838 const MachineMemOperand *Dummy;
839 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
844 bool X86InstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
845 const MachineMemOperand *&MMO,
846 int &FrameIndex) const {
847 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
848 oe = MI->memoperands_end();
851 if ((*o)->isLoad() && (*o)->getValue())
852 if (const FixedStackPseudoSourceValue *Value =
853 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
854 FrameIndex = Value->getFrameIndex();
862 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
863 int &FrameIndex) const {
864 if (isFrameStoreOpcode(MI->getOpcode()))
865 if (isFrameOperand(MI, 0, FrameIndex))
866 return MI->getOperand(X86AddrNumOperands).getReg();
870 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
871 int &FrameIndex) const {
872 if (isFrameStoreOpcode(MI->getOpcode())) {
874 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
876 // Check for post-frame index elimination operations
877 const MachineMemOperand *Dummy;
878 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
883 bool X86InstrInfo::hasStoreToStackSlot(const MachineInstr *MI,
884 const MachineMemOperand *&MMO,
885 int &FrameIndex) const {
886 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
887 oe = MI->memoperands_end();
890 if ((*o)->isStore() && (*o)->getValue())
891 if (const FixedStackPseudoSourceValue *Value =
892 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
893 FrameIndex = Value->getFrameIndex();
901 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
903 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
904 bool isPICBase = false;
905 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
906 E = MRI.def_end(); I != E; ++I) {
907 MachineInstr *DefMI = I.getOperand().getParent();
908 if (DefMI->getOpcode() != X86::MOVPC32r)
910 assert(!isPICBase && "More than one PIC base?");
917 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
918 AliasAnalysis *AA) const {
919 switch (MI->getOpcode()) {
930 case X86::MOVUPSrm_Int:
933 case X86::MMX_MOVD64rm:
934 case X86::MMX_MOVQ64rm:
935 case X86::FsMOVAPSrm:
936 case X86::FsMOVAPDrm: {
937 // Loads from constant pools are trivially rematerializable.
938 if (MI->getOperand(1).isReg() &&
939 MI->getOperand(2).isImm() &&
940 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
941 MI->isInvariantLoad(AA)) {
942 unsigned BaseReg = MI->getOperand(1).getReg();
943 if (BaseReg == 0 || BaseReg == X86::RIP)
945 // Allow re-materialization of PIC load.
946 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
948 const MachineFunction &MF = *MI->getParent()->getParent();
949 const MachineRegisterInfo &MRI = MF.getRegInfo();
950 bool isPICBase = false;
951 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
952 E = MRI.def_end(); I != E; ++I) {
953 MachineInstr *DefMI = I.getOperand().getParent();
954 if (DefMI->getOpcode() != X86::MOVPC32r)
956 assert(!isPICBase && "More than one PIC base?");
966 if (MI->getOperand(2).isImm() &&
967 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
968 !MI->getOperand(4).isReg()) {
969 // lea fi#, lea GV, etc. are all rematerializable.
970 if (!MI->getOperand(1).isReg())
972 unsigned BaseReg = MI->getOperand(1).getReg();
975 // Allow re-materialization of lea PICBase + x.
976 const MachineFunction &MF = *MI->getParent()->getParent();
977 const MachineRegisterInfo &MRI = MF.getRegInfo();
978 return regIsPICBase(BaseReg, MRI);
984 // All other instructions marked M_REMATERIALIZABLE are always trivially
989 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
990 /// would clobber the EFLAGS condition register. Note the result may be
991 /// conservative. If it cannot definitely determine the safety after visiting
992 /// a few instructions in each direction it assumes it's not safe.
993 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
994 MachineBasicBlock::iterator I) {
995 MachineBasicBlock::iterator E = MBB.end();
997 // It's always safe to clobber EFLAGS at the end of a block.
1001 // For compile time consideration, if we are not able to determine the
1002 // safety after visiting 4 instructions in each direction, we will assume
1004 MachineBasicBlock::iterator Iter = I;
1005 for (unsigned i = 0; i < 4; ++i) {
1006 bool SeenDef = false;
1007 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1008 MachineOperand &MO = Iter->getOperand(j);
1011 if (MO.getReg() == X86::EFLAGS) {
1019 // This instruction defines EFLAGS, no need to look any further.
1022 // Skip over DBG_VALUE.
1023 while (Iter != E && Iter->isDebugValue())
1026 // If we make it to the end of the block, it's safe to clobber EFLAGS.
1031 MachineBasicBlock::iterator B = MBB.begin();
1033 for (unsigned i = 0; i < 4; ++i) {
1034 // If we make it to the beginning of the block, it's safe to clobber
1035 // EFLAGS iff EFLAGS is not live-in.
1037 return !MBB.isLiveIn(X86::EFLAGS);
1040 // Skip over DBG_VALUE.
1041 while (Iter != B && Iter->isDebugValue())
1044 bool SawKill = false;
1045 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1046 MachineOperand &MO = Iter->getOperand(j);
1047 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1048 if (MO.isDef()) return MO.isDead();
1049 if (MO.isKill()) SawKill = true;
1054 // This instruction kills EFLAGS and doesn't redefine it, so
1055 // there's no need to look further.
1059 // Conservative answer.
1063 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1064 MachineBasicBlock::iterator I,
1065 unsigned DestReg, unsigned SubIdx,
1066 const MachineInstr *Orig,
1067 const TargetRegisterInfo *TRI) const {
1068 DebugLoc DL = MBB.findDebugLoc(I);
1070 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
1071 DestReg = TRI->getSubReg(DestReg, SubIdx);
1075 // MOV32r0 etc. are implemented with xor which clobbers condition code.
1076 // Re-materialize them as movri instructions to avoid side effects.
1078 unsigned Opc = Orig->getOpcode();
1084 case X86::MOV64r0: {
1085 if (!isSafeToClobberEFLAGS(MBB, I)) {
1088 case X86::MOV8r0: Opc = X86::MOV8ri; break;
1089 case X86::MOV16r0: Opc = X86::MOV16ri; break;
1090 case X86::MOV32r0: Opc = X86::MOV32ri; break;
1091 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
1100 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1101 MI->getOperand(0).setReg(DestReg);
1104 BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0);
1107 MachineInstr *NewMI = prior(I);
1108 NewMI->getOperand(0).setSubReg(SubIdx);
1111 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1112 /// is not marked dead.
1113 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1114 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1115 MachineOperand &MO = MI->getOperand(i);
1116 if (MO.isReg() && MO.isDef() &&
1117 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1124 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1125 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1126 /// to a 32-bit superregister and then truncating back down to a 16-bit
1129 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1130 MachineFunction::iterator &MFI,
1131 MachineBasicBlock::iterator &MBBI,
1132 LiveVariables *LV) const {
1133 MachineInstr *MI = MBBI;
1134 unsigned Dest = MI->getOperand(0).getReg();
1135 unsigned Src = MI->getOperand(1).getReg();
1136 bool isDead = MI->getOperand(0).isDead();
1137 bool isKill = MI->getOperand(1).isKill();
1139 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1140 ? X86::LEA64_32r : X86::LEA32r;
1141 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1142 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1143 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1145 // Build and insert into an implicit UNDEF value. This is OK because
1146 // well be shifting and then extracting the lower 16-bits.
1147 // This has the potential to cause partial register stall. e.g.
1148 // movw (%rbp,%rcx,2), %dx
1149 // leal -65(%rdx), %esi
1150 // But testing has shown this *does* help performance in 64-bit mode (at
1151 // least on modern x86 machines).
1152 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1153 MachineInstr *InsMI =
1154 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
1156 .addReg(Src, getKillRegState(isKill))
1157 .addImm(X86::SUBREG_16BIT);
1159 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1160 get(Opc), leaOutReg);
1163 llvm_unreachable(0);
1165 case X86::SHL16ri: {
1166 unsigned ShAmt = MI->getOperand(2).getImm();
1167 MIB.addReg(0).addImm(1 << ShAmt)
1168 .addReg(leaInReg, RegState::Kill).addImm(0);
1172 case X86::INC64_16r:
1173 addLeaRegOffset(MIB, leaInReg, true, 1);
1176 case X86::DEC64_16r:
1177 addLeaRegOffset(MIB, leaInReg, true, -1);
1181 addLeaRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1183 case X86::ADD16rr: {
1184 unsigned Src2 = MI->getOperand(2).getReg();
1185 bool isKill2 = MI->getOperand(2).isKill();
1186 unsigned leaInReg2 = 0;
1187 MachineInstr *InsMI2 = 0;
1189 // ADD16rr %reg1028<kill>, %reg1028
1190 // just a single insert_subreg.
1191 addRegReg(MIB, leaInReg, true, leaInReg, false);
1193 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1194 // Build and insert into an implicit UNDEF value. This is OK because
1195 // well be shifting and then extracting the lower 16-bits.
1196 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
1198 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg2)
1200 .addReg(Src2, getKillRegState(isKill2))
1201 .addImm(X86::SUBREG_16BIT);
1202 addRegReg(MIB, leaInReg, true, leaInReg2, true);
1204 if (LV && isKill2 && InsMI2)
1205 LV->replaceKillInstruction(Src2, MI, InsMI2);
1210 MachineInstr *NewMI = MIB;
1211 MachineInstr *ExtMI =
1212 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
1213 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1214 .addReg(leaOutReg, RegState::Kill)
1215 .addImm(X86::SUBREG_16BIT);
1218 // Update live variables
1219 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1220 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1222 LV->replaceKillInstruction(Src, MI, InsMI);
1224 LV->replaceKillInstruction(Dest, MI, ExtMI);
1230 /// convertToThreeAddress - This method must be implemented by targets that
1231 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1232 /// may be able to convert a two-address instruction into a true
1233 /// three-address instruction on demand. This allows the X86 target (for
1234 /// example) to convert ADD and SHL instructions into LEA instructions if they
1235 /// would require register copies due to two-addressness.
1237 /// This method returns a null pointer if the transformation cannot be
1238 /// performed, otherwise it returns the new instruction.
1241 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1242 MachineBasicBlock::iterator &MBBI,
1243 LiveVariables *LV) const {
1244 MachineInstr *MI = MBBI;
1245 MachineFunction &MF = *MI->getParent()->getParent();
1246 // All instructions input are two-addr instructions. Get the known operands.
1247 unsigned Dest = MI->getOperand(0).getReg();
1248 unsigned Src = MI->getOperand(1).getReg();
1249 bool isDead = MI->getOperand(0).isDead();
1250 bool isKill = MI->getOperand(1).isKill();
1252 MachineInstr *NewMI = NULL;
1253 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1254 // we have better subtarget support, enable the 16-bit LEA generation here.
1255 // 16-bit LEA is also slow on Core2.
1256 bool DisableLEA16 = true;
1257 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1259 unsigned MIOpc = MI->getOpcode();
1261 case X86::SHUFPSrri: {
1262 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1263 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1265 unsigned B = MI->getOperand(1).getReg();
1266 unsigned C = MI->getOperand(2).getReg();
1267 if (B != C) return 0;
1268 unsigned A = MI->getOperand(0).getReg();
1269 unsigned M = MI->getOperand(3).getImm();
1270 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1271 .addReg(A, RegState::Define | getDeadRegState(isDead))
1272 .addReg(B, getKillRegState(isKill)).addImm(M);
1275 case X86::SHL64ri: {
1276 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1277 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1278 // the flags produced by a shift yet, so this is safe.
1279 unsigned ShAmt = MI->getOperand(2).getImm();
1280 if (ShAmt == 0 || ShAmt >= 4) return 0;
1282 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1283 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1284 .addReg(0).addImm(1 << ShAmt)
1285 .addReg(Src, getKillRegState(isKill))
1289 case X86::SHL32ri: {
1290 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1291 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1292 // the flags produced by a shift yet, so this is safe.
1293 unsigned ShAmt = MI->getOperand(2).getImm();
1294 if (ShAmt == 0 || ShAmt >= 4) return 0;
1296 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1297 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1298 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1299 .addReg(0).addImm(1 << ShAmt)
1300 .addReg(Src, getKillRegState(isKill)).addImm(0);
1303 case X86::SHL16ri: {
1304 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1305 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1306 // the flags produced by a shift yet, so this is safe.
1307 unsigned ShAmt = MI->getOperand(2).getImm();
1308 if (ShAmt == 0 || ShAmt >= 4) return 0;
1311 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1312 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1313 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1314 .addReg(0).addImm(1 << ShAmt)
1315 .addReg(Src, getKillRegState(isKill))
1320 // The following opcodes also sets the condition code register(s). Only
1321 // convert them to equivalent lea if the condition code register def's
1323 if (hasLiveCondCodeDef(MI))
1330 case X86::INC64_32r: {
1331 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1332 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1333 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1334 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1335 .addReg(Dest, RegState::Define |
1336 getDeadRegState(isDead)),
1341 case X86::INC64_16r:
1343 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1344 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1345 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1346 .addReg(Dest, RegState::Define |
1347 getDeadRegState(isDead)),
1352 case X86::DEC64_32r: {
1353 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1354 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1355 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1356 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1357 .addReg(Dest, RegState::Define |
1358 getDeadRegState(isDead)),
1363 case X86::DEC64_16r:
1365 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1366 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1367 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1368 .addReg(Dest, RegState::Define |
1369 getDeadRegState(isDead)),
1373 case X86::ADD32rr: {
1374 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1375 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1376 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1377 unsigned Src2 = MI->getOperand(2).getReg();
1378 bool isKill2 = MI->getOperand(2).isKill();
1379 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1380 .addReg(Dest, RegState::Define |
1381 getDeadRegState(isDead)),
1382 Src, isKill, Src2, isKill2);
1384 LV->replaceKillInstruction(Src2, MI, NewMI);
1387 case X86::ADD16rr: {
1389 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1390 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1391 unsigned Src2 = MI->getOperand(2).getReg();
1392 bool isKill2 = MI->getOperand(2).isKill();
1393 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1394 .addReg(Dest, RegState::Define |
1395 getDeadRegState(isDead)),
1396 Src, isKill, Src2, isKill2);
1398 LV->replaceKillInstruction(Src2, MI, NewMI);
1401 case X86::ADD64ri32:
1403 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1404 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1405 .addReg(Dest, RegState::Define |
1406 getDeadRegState(isDead)),
1407 Src, isKill, MI->getOperand(2).getImm());
1410 case X86::ADD32ri8: {
1411 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1412 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1413 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1414 .addReg(Dest, RegState::Define |
1415 getDeadRegState(isDead)),
1416 Src, isKill, MI->getOperand(2).getImm());
1422 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1423 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1424 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1425 .addReg(Dest, RegState::Define |
1426 getDeadRegState(isDead)),
1427 Src, isKill, MI->getOperand(2).getImm());
1433 if (!NewMI) return 0;
1435 if (LV) { // Update live variables
1437 LV->replaceKillInstruction(Src, MI, NewMI);
1439 LV->replaceKillInstruction(Dest, MI, NewMI);
1442 MFI->insert(MBBI, NewMI); // Insert the new inst
1446 /// commuteInstruction - We have a few instructions that must be hacked on to
1450 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1451 switch (MI->getOpcode()) {
1452 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1453 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1454 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1455 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1456 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1457 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1460 switch (MI->getOpcode()) {
1461 default: llvm_unreachable("Unreachable!");
1462 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1463 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1464 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1465 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1466 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1467 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1469 unsigned Amt = MI->getOperand(3).getImm();
1471 MachineFunction &MF = *MI->getParent()->getParent();
1472 MI = MF.CloneMachineInstr(MI);
1475 MI->setDesc(get(Opc));
1476 MI->getOperand(3).setImm(Size-Amt);
1477 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1479 case X86::CMOVB16rr:
1480 case X86::CMOVB32rr:
1481 case X86::CMOVB64rr:
1482 case X86::CMOVAE16rr:
1483 case X86::CMOVAE32rr:
1484 case X86::CMOVAE64rr:
1485 case X86::CMOVE16rr:
1486 case X86::CMOVE32rr:
1487 case X86::CMOVE64rr:
1488 case X86::CMOVNE16rr:
1489 case X86::CMOVNE32rr:
1490 case X86::CMOVNE64rr:
1491 case X86::CMOVBE16rr:
1492 case X86::CMOVBE32rr:
1493 case X86::CMOVBE64rr:
1494 case X86::CMOVA16rr:
1495 case X86::CMOVA32rr:
1496 case X86::CMOVA64rr:
1497 case X86::CMOVL16rr:
1498 case X86::CMOVL32rr:
1499 case X86::CMOVL64rr:
1500 case X86::CMOVGE16rr:
1501 case X86::CMOVGE32rr:
1502 case X86::CMOVGE64rr:
1503 case X86::CMOVLE16rr:
1504 case X86::CMOVLE32rr:
1505 case X86::CMOVLE64rr:
1506 case X86::CMOVG16rr:
1507 case X86::CMOVG32rr:
1508 case X86::CMOVG64rr:
1509 case X86::CMOVS16rr:
1510 case X86::CMOVS32rr:
1511 case X86::CMOVS64rr:
1512 case X86::CMOVNS16rr:
1513 case X86::CMOVNS32rr:
1514 case X86::CMOVNS64rr:
1515 case X86::CMOVP16rr:
1516 case X86::CMOVP32rr:
1517 case X86::CMOVP64rr:
1518 case X86::CMOVNP16rr:
1519 case X86::CMOVNP32rr:
1520 case X86::CMOVNP64rr:
1521 case X86::CMOVO16rr:
1522 case X86::CMOVO32rr:
1523 case X86::CMOVO64rr:
1524 case X86::CMOVNO16rr:
1525 case X86::CMOVNO32rr:
1526 case X86::CMOVNO64rr: {
1528 switch (MI->getOpcode()) {
1530 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1531 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1532 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1533 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1534 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1535 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1536 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1537 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1538 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1539 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1540 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1541 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1542 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1543 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1544 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1545 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1546 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1547 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1548 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1549 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1550 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1551 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1552 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1553 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1554 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1555 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1556 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1557 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1558 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1559 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1560 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1561 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1562 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1563 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1564 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1565 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1566 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1567 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1568 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1569 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1570 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1571 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1572 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1573 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1574 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1575 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1576 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1577 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1580 MachineFunction &MF = *MI->getParent()->getParent();
1581 MI = MF.CloneMachineInstr(MI);
1584 MI->setDesc(get(Opc));
1585 // Fallthrough intended.
1588 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1592 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1594 default: return X86::COND_INVALID;
1595 case X86::JE_4: return X86::COND_E;
1596 case X86::JNE_4: return X86::COND_NE;
1597 case X86::JL_4: return X86::COND_L;
1598 case X86::JLE_4: return X86::COND_LE;
1599 case X86::JG_4: return X86::COND_G;
1600 case X86::JGE_4: return X86::COND_GE;
1601 case X86::JB_4: return X86::COND_B;
1602 case X86::JBE_4: return X86::COND_BE;
1603 case X86::JA_4: return X86::COND_A;
1604 case X86::JAE_4: return X86::COND_AE;
1605 case X86::JS_4: return X86::COND_S;
1606 case X86::JNS_4: return X86::COND_NS;
1607 case X86::JP_4: return X86::COND_P;
1608 case X86::JNP_4: return X86::COND_NP;
1609 case X86::JO_4: return X86::COND_O;
1610 case X86::JNO_4: return X86::COND_NO;
1614 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1616 default: llvm_unreachable("Illegal condition code!");
1617 case X86::COND_E: return X86::JE_4;
1618 case X86::COND_NE: return X86::JNE_4;
1619 case X86::COND_L: return X86::JL_4;
1620 case X86::COND_LE: return X86::JLE_4;
1621 case X86::COND_G: return X86::JG_4;
1622 case X86::COND_GE: return X86::JGE_4;
1623 case X86::COND_B: return X86::JB_4;
1624 case X86::COND_BE: return X86::JBE_4;
1625 case X86::COND_A: return X86::JA_4;
1626 case X86::COND_AE: return X86::JAE_4;
1627 case X86::COND_S: return X86::JS_4;
1628 case X86::COND_NS: return X86::JNS_4;
1629 case X86::COND_P: return X86::JP_4;
1630 case X86::COND_NP: return X86::JNP_4;
1631 case X86::COND_O: return X86::JO_4;
1632 case X86::COND_NO: return X86::JNO_4;
1636 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1637 /// e.g. turning COND_E to COND_NE.
1638 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1640 default: llvm_unreachable("Illegal condition code!");
1641 case X86::COND_E: return X86::COND_NE;
1642 case X86::COND_NE: return X86::COND_E;
1643 case X86::COND_L: return X86::COND_GE;
1644 case X86::COND_LE: return X86::COND_G;
1645 case X86::COND_G: return X86::COND_LE;
1646 case X86::COND_GE: return X86::COND_L;
1647 case X86::COND_B: return X86::COND_AE;
1648 case X86::COND_BE: return X86::COND_A;
1649 case X86::COND_A: return X86::COND_BE;
1650 case X86::COND_AE: return X86::COND_B;
1651 case X86::COND_S: return X86::COND_NS;
1652 case X86::COND_NS: return X86::COND_S;
1653 case X86::COND_P: return X86::COND_NP;
1654 case X86::COND_NP: return X86::COND_P;
1655 case X86::COND_O: return X86::COND_NO;
1656 case X86::COND_NO: return X86::COND_O;
1660 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1661 const TargetInstrDesc &TID = MI->getDesc();
1662 if (!TID.isTerminator()) return false;
1664 // Conditional branch is a special case.
1665 if (TID.isBranch() && !TID.isBarrier())
1667 if (!TID.isPredicable())
1669 return !isPredicated(MI);
1672 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1673 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1674 const X86InstrInfo &TII) {
1675 if (MI->getOpcode() == X86::FP_REG_KILL)
1677 return TII.isUnpredicatedTerminator(MI);
1680 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1681 MachineBasicBlock *&TBB,
1682 MachineBasicBlock *&FBB,
1683 SmallVectorImpl<MachineOperand> &Cond,
1684 bool AllowModify) const {
1685 // Start from the bottom of the block and work up, examining the
1686 // terminator instructions.
1687 MachineBasicBlock::iterator I = MBB.end();
1688 while (I != MBB.begin()) {
1691 // Working from the bottom, when we see a non-terminator instruction, we're
1693 if (!isBrAnalysisUnpredicatedTerminator(I, *this))
1696 // A terminator that isn't a branch can't easily be handled by this
1698 if (!I->getDesc().isBranch())
1701 // Handle unconditional branches.
1702 if (I->getOpcode() == X86::JMP_4) {
1704 TBB = I->getOperand(0).getMBB();
1708 // If the block has any instructions after a JMP, delete them.
1709 while (llvm::next(I) != MBB.end())
1710 llvm::next(I)->eraseFromParent();
1715 // Delete the JMP if it's equivalent to a fall-through.
1716 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1718 I->eraseFromParent();
1723 // TBB is used to indicate the unconditinal destination.
1724 TBB = I->getOperand(0).getMBB();
1728 // Handle conditional branches.
1729 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1730 if (BranchCode == X86::COND_INVALID)
1731 return true; // Can't handle indirect branch.
1733 // Working from the bottom, handle the first conditional branch.
1736 TBB = I->getOperand(0).getMBB();
1737 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1741 // Handle subsequent conditional branches. Only handle the case where all
1742 // conditional branches branch to the same destination and their condition
1743 // opcodes fit one of the special multi-branch idioms.
1744 assert(Cond.size() == 1);
1747 // Only handle the case where all conditional branches branch to the same
1749 if (TBB != I->getOperand(0).getMBB())
1752 // If the conditions are the same, we can leave them alone.
1753 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1754 if (OldBranchCode == BranchCode)
1757 // If they differ, see if they fit one of the known patterns. Theoretically,
1758 // we could handle more patterns here, but we shouldn't expect to see them
1759 // if instruction selection has done a reasonable job.
1760 if ((OldBranchCode == X86::COND_NP &&
1761 BranchCode == X86::COND_E) ||
1762 (OldBranchCode == X86::COND_E &&
1763 BranchCode == X86::COND_NP))
1764 BranchCode = X86::COND_NP_OR_E;
1765 else if ((OldBranchCode == X86::COND_P &&
1766 BranchCode == X86::COND_NE) ||
1767 (OldBranchCode == X86::COND_NE &&
1768 BranchCode == X86::COND_P))
1769 BranchCode = X86::COND_NE_OR_P;
1773 // Update the MachineOperand.
1774 Cond[0].setImm(BranchCode);
1780 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1781 MachineBasicBlock::iterator I = MBB.end();
1784 while (I != MBB.begin()) {
1786 if (I->getOpcode() != X86::JMP_4 &&
1787 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1789 // Remove the branch.
1790 I->eraseFromParent();
1799 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1800 MachineBasicBlock *FBB,
1801 const SmallVectorImpl<MachineOperand> &Cond) const {
1802 // FIXME this should probably have a DebugLoc operand
1803 DebugLoc dl = DebugLoc::getUnknownLoc();
1804 // Shouldn't be a fall through.
1805 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1806 assert((Cond.size() == 1 || Cond.size() == 0) &&
1807 "X86 branch conditions have one component!");
1810 // Unconditional branch?
1811 assert(!FBB && "Unconditional branch with multiple successors!");
1812 BuildMI(&MBB, dl, get(X86::JMP_4)).addMBB(TBB);
1816 // Conditional branch.
1818 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1820 case X86::COND_NP_OR_E:
1821 // Synthesize NP_OR_E with two branches.
1822 BuildMI(&MBB, dl, get(X86::JNP_4)).addMBB(TBB);
1824 BuildMI(&MBB, dl, get(X86::JE_4)).addMBB(TBB);
1827 case X86::COND_NE_OR_P:
1828 // Synthesize NE_OR_P with two branches.
1829 BuildMI(&MBB, dl, get(X86::JNE_4)).addMBB(TBB);
1831 BuildMI(&MBB, dl, get(X86::JP_4)).addMBB(TBB);
1835 unsigned Opc = GetCondBranchFromCond(CC);
1836 BuildMI(&MBB, dl, get(Opc)).addMBB(TBB);
1841 // Two-way Conditional branch. Insert the second branch.
1842 BuildMI(&MBB, dl, get(X86::JMP_4)).addMBB(FBB);
1848 /// isHReg - Test if the given register is a physical h register.
1849 static bool isHReg(unsigned Reg) {
1850 return X86::GR8_ABCD_HRegClass.contains(Reg);
1853 bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1854 MachineBasicBlock::iterator MI,
1855 unsigned DestReg, unsigned SrcReg,
1856 const TargetRegisterClass *DestRC,
1857 const TargetRegisterClass *SrcRC) const {
1858 DebugLoc DL = MBB.findDebugLoc(MI);
1860 // Determine if DstRC and SrcRC have a common superclass in common.
1861 const TargetRegisterClass *CommonRC = DestRC;
1862 if (DestRC == SrcRC)
1863 /* Source and destination have the same register class. */;
1864 else if (CommonRC->hasSuperClass(SrcRC))
1866 else if (!DestRC->hasSubClass(SrcRC)) {
1867 // Neither of GR64_NOREX or GR64_NOSP is a superclass of the other,
1868 // but we want to copy them as GR64. Similarly, for GR32_NOREX and
1869 // GR32_NOSP, copy as GR32.
1870 if (SrcRC->hasSuperClass(&X86::GR64RegClass) &&
1871 DestRC->hasSuperClass(&X86::GR64RegClass))
1872 CommonRC = &X86::GR64RegClass;
1873 else if (SrcRC->hasSuperClass(&X86::GR32RegClass) &&
1874 DestRC->hasSuperClass(&X86::GR32RegClass))
1875 CommonRC = &X86::GR32RegClass;
1882 if (CommonRC == &X86::GR64RegClass || CommonRC == &X86::GR64_NOSPRegClass) {
1884 } else if (CommonRC == &X86::GR32RegClass ||
1885 CommonRC == &X86::GR32_NOSPRegClass) {
1887 } else if (CommonRC == &X86::GR16RegClass) {
1889 } else if (CommonRC == &X86::GR8RegClass) {
1890 // Copying to or from a physical H register on x86-64 requires a NOREX
1891 // move. Otherwise use a normal move.
1892 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
1893 TM.getSubtarget<X86Subtarget>().is64Bit())
1894 Opc = X86::MOV8rr_NOREX;
1897 } else if (CommonRC == &X86::GR64_ABCDRegClass) {
1899 } else if (CommonRC == &X86::GR32_ABCDRegClass) {
1901 } else if (CommonRC == &X86::GR16_ABCDRegClass) {
1903 } else if (CommonRC == &X86::GR8_ABCD_LRegClass) {
1905 } else if (CommonRC == &X86::GR8_ABCD_HRegClass) {
1906 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1907 Opc = X86::MOV8rr_NOREX;
1910 } else if (CommonRC == &X86::GR64_NOREXRegClass ||
1911 CommonRC == &X86::GR64_NOREX_NOSPRegClass) {
1913 } else if (CommonRC == &X86::GR32_NOREXRegClass) {
1915 } else if (CommonRC == &X86::GR16_NOREXRegClass) {
1917 } else if (CommonRC == &X86::GR8_NOREXRegClass) {
1919 } else if (CommonRC == &X86::GR64_TCRegClass) {
1920 Opc = X86::MOV64rr_TC;
1921 } else if (CommonRC == &X86::GR32_TCRegClass) {
1922 Opc = X86::MOV32rr_TC;
1923 } else if (CommonRC == &X86::RFP32RegClass) {
1924 Opc = X86::MOV_Fp3232;
1925 } else if (CommonRC == &X86::RFP64RegClass || CommonRC == &X86::RSTRegClass) {
1926 Opc = X86::MOV_Fp6464;
1927 } else if (CommonRC == &X86::RFP80RegClass) {
1928 Opc = X86::MOV_Fp8080;
1929 } else if (CommonRC == &X86::FR32RegClass) {
1930 Opc = X86::FsMOVAPSrr;
1931 } else if (CommonRC == &X86::FR64RegClass) {
1932 Opc = X86::FsMOVAPDrr;
1933 } else if (CommonRC == &X86::VR128RegClass) {
1934 Opc = X86::MOVAPSrr;
1935 } else if (CommonRC == &X86::VR64RegClass) {
1936 Opc = X86::MMX_MOVQ64rr;
1940 BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg);
1944 // Moving EFLAGS to / from another register requires a push and a pop.
1945 if (SrcRC == &X86::CCRRegClass) {
1946 if (SrcReg != X86::EFLAGS)
1948 if (DestRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1949 BuildMI(MBB, MI, DL, get(X86::PUSHFQ64));
1950 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1952 } else if (DestRC == &X86::GR32RegClass ||
1953 DestRC == &X86::GR32_NOSPRegClass) {
1954 BuildMI(MBB, MI, DL, get(X86::PUSHFD));
1955 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
1958 } else if (DestRC == &X86::CCRRegClass) {
1959 if (DestReg != X86::EFLAGS)
1961 if (SrcRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1962 BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg);
1963 BuildMI(MBB, MI, DL, get(X86::POPFQ));
1965 } else if (SrcRC == &X86::GR32RegClass ||
1966 DestRC == &X86::GR32_NOSPRegClass) {
1967 BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg);
1968 BuildMI(MBB, MI, DL, get(X86::POPFD));
1973 // Moving from ST(0) turns into FpGET_ST0_32 etc.
1974 if (SrcRC == &X86::RSTRegClass) {
1975 // Copying from ST(0)/ST(1).
1976 if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
1977 // Can only copy from ST(0)/ST(1) right now
1979 bool isST0 = SrcReg == X86::ST0;
1981 if (DestRC == &X86::RFP32RegClass)
1982 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
1983 else if (DestRC == &X86::RFP64RegClass)
1984 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
1986 if (DestRC != &X86::RFP80RegClass)
1988 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
1990 BuildMI(MBB, MI, DL, get(Opc), DestReg);
1994 // Moving to ST(0) turns into FpSET_ST0_32 etc.
1995 if (DestRC == &X86::RSTRegClass) {
1996 // Copying to ST(0) / ST(1).
1997 if (DestReg != X86::ST0 && DestReg != X86::ST1)
1998 // Can only copy to TOS right now
2000 bool isST0 = DestReg == X86::ST0;
2002 if (SrcRC == &X86::RFP32RegClass)
2003 Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32;
2004 else if (SrcRC == &X86::RFP64RegClass)
2005 Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64;
2007 if (SrcRC != &X86::RFP80RegClass)
2009 Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80;
2011 BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg);
2015 // Not yet supported!
2019 static unsigned getStoreRegOpcode(unsigned SrcReg,
2020 const TargetRegisterClass *RC,
2021 bool isStackAligned,
2022 TargetMachine &TM) {
2024 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
2026 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
2028 } else if (RC == &X86::GR16RegClass) {
2030 } else if (RC == &X86::GR8RegClass) {
2031 // Copying to or from a physical H register on x86-64 requires a NOREX
2032 // move. Otherwise use a normal move.
2033 if (isHReg(SrcReg) &&
2034 TM.getSubtarget<X86Subtarget>().is64Bit())
2035 Opc = X86::MOV8mr_NOREX;
2038 } else if (RC == &X86::GR64_ABCDRegClass) {
2040 } else if (RC == &X86::GR32_ABCDRegClass) {
2042 } else if (RC == &X86::GR16_ABCDRegClass) {
2044 } else if (RC == &X86::GR8_ABCD_LRegClass) {
2046 } else if (RC == &X86::GR8_ABCD_HRegClass) {
2047 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2048 Opc = X86::MOV8mr_NOREX;
2051 } else if (RC == &X86::GR64_NOREXRegClass ||
2052 RC == &X86::GR64_NOREX_NOSPRegClass) {
2054 } else if (RC == &X86::GR32_NOREXRegClass) {
2056 } else if (RC == &X86::GR16_NOREXRegClass) {
2058 } else if (RC == &X86::GR8_NOREXRegClass) {
2060 } else if (RC == &X86::GR64_TCRegClass) {
2061 Opc = X86::MOV64mr_TC;
2062 } else if (RC == &X86::GR32_TCRegClass) {
2063 Opc = X86::MOV32mr_TC;
2064 } else if (RC == &X86::RFP80RegClass) {
2065 Opc = X86::ST_FpP80m; // pops
2066 } else if (RC == &X86::RFP64RegClass) {
2067 Opc = X86::ST_Fp64m;
2068 } else if (RC == &X86::RFP32RegClass) {
2069 Opc = X86::ST_Fp32m;
2070 } else if (RC == &X86::FR32RegClass) {
2072 } else if (RC == &X86::FR64RegClass) {
2074 } else if (RC == &X86::VR128RegClass) {
2075 // If stack is realigned we can use aligned stores.
2076 Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr;
2077 } else if (RC == &X86::VR64RegClass) {
2078 Opc = X86::MMX_MOVQ64mr;
2080 llvm_unreachable("Unknown regclass");
2086 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
2087 MachineBasicBlock::iterator MI,
2088 unsigned SrcReg, bool isKill, int FrameIdx,
2089 const TargetRegisterClass *RC) const {
2090 const MachineFunction &MF = *MBB.getParent();
2091 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
2092 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2093 DebugLoc DL = MBB.findDebugLoc(MI);
2094 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
2095 .addReg(SrcReg, getKillRegState(isKill));
2098 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2100 SmallVectorImpl<MachineOperand> &Addr,
2101 const TargetRegisterClass *RC,
2102 MachineInstr::mmo_iterator MMOBegin,
2103 MachineInstr::mmo_iterator MMOEnd,
2104 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2105 bool isAligned = (*MMOBegin)->getAlignment() >= 16;
2106 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2107 DebugLoc DL = DebugLoc::getUnknownLoc();
2108 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2109 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2110 MIB.addOperand(Addr[i]);
2111 MIB.addReg(SrcReg, getKillRegState(isKill));
2112 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2113 NewMIs.push_back(MIB);
2116 static unsigned getLoadRegOpcode(unsigned DestReg,
2117 const TargetRegisterClass *RC,
2118 bool isStackAligned,
2119 const TargetMachine &TM) {
2121 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
2123 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
2125 } else if (RC == &X86::GR16RegClass) {
2127 } else if (RC == &X86::GR8RegClass) {
2128 // Copying to or from a physical H register on x86-64 requires a NOREX
2129 // move. Otherwise use a normal move.
2130 if (isHReg(DestReg) &&
2131 TM.getSubtarget<X86Subtarget>().is64Bit())
2132 Opc = X86::MOV8rm_NOREX;
2135 } else if (RC == &X86::GR64_ABCDRegClass) {
2137 } else if (RC == &X86::GR32_ABCDRegClass) {
2139 } else if (RC == &X86::GR16_ABCDRegClass) {
2141 } else if (RC == &X86::GR8_ABCD_LRegClass) {
2143 } else if (RC == &X86::GR8_ABCD_HRegClass) {
2144 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2145 Opc = X86::MOV8rm_NOREX;
2148 } else if (RC == &X86::GR64_NOREXRegClass ||
2149 RC == &X86::GR64_NOREX_NOSPRegClass) {
2151 } else if (RC == &X86::GR32_NOREXRegClass) {
2153 } else if (RC == &X86::GR16_NOREXRegClass) {
2155 } else if (RC == &X86::GR8_NOREXRegClass) {
2157 } else if (RC == &X86::GR64_TCRegClass) {
2158 Opc = X86::MOV64rm_TC;
2159 } else if (RC == &X86::GR32_TCRegClass) {
2160 Opc = X86::MOV32rm_TC;
2161 } else if (RC == &X86::RFP80RegClass) {
2162 Opc = X86::LD_Fp80m;
2163 } else if (RC == &X86::RFP64RegClass) {
2164 Opc = X86::LD_Fp64m;
2165 } else if (RC == &X86::RFP32RegClass) {
2166 Opc = X86::LD_Fp32m;
2167 } else if (RC == &X86::FR32RegClass) {
2169 } else if (RC == &X86::FR64RegClass) {
2171 } else if (RC == &X86::VR128RegClass) {
2172 // If stack is realigned we can use aligned loads.
2173 Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm;
2174 } else if (RC == &X86::VR64RegClass) {
2175 Opc = X86::MMX_MOVQ64rm;
2177 llvm_unreachable("Unknown regclass");
2183 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2184 MachineBasicBlock::iterator MI,
2185 unsigned DestReg, int FrameIdx,
2186 const TargetRegisterClass *RC) const{
2187 const MachineFunction &MF = *MBB.getParent();
2188 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
2189 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2190 DebugLoc DL = MBB.findDebugLoc(MI);
2191 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2194 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2195 SmallVectorImpl<MachineOperand> &Addr,
2196 const TargetRegisterClass *RC,
2197 MachineInstr::mmo_iterator MMOBegin,
2198 MachineInstr::mmo_iterator MMOEnd,
2199 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2200 bool isAligned = (*MMOBegin)->getAlignment() >= 16;
2201 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2202 DebugLoc DL = DebugLoc::getUnknownLoc();
2203 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2204 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2205 MIB.addOperand(Addr[i]);
2206 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2207 NewMIs.push_back(MIB);
2210 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
2211 MachineBasicBlock::iterator MI,
2212 const std::vector<CalleeSavedInfo> &CSI) const {
2216 DebugLoc DL = MBB.findDebugLoc(MI);
2218 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2219 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2220 unsigned SlotSize = is64Bit ? 8 : 4;
2222 MachineFunction &MF = *MBB.getParent();
2223 unsigned FPReg = RI.getFrameRegister(MF);
2224 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2225 unsigned CalleeFrameSize = 0;
2227 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
2228 for (unsigned i = CSI.size(); i != 0; --i) {
2229 unsigned Reg = CSI[i-1].getReg();
2230 const TargetRegisterClass *RegClass = CSI[i-1].getRegClass();
2231 // Add the callee-saved register as live-in. It's killed at the spill.
2234 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
2236 if (RegClass != &X86::VR128RegClass && !isWin64) {
2237 CalleeFrameSize += SlotSize;
2238 BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
2240 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass);
2244 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
2248 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
2249 MachineBasicBlock::iterator MI,
2250 const std::vector<CalleeSavedInfo> &CSI) const {
2254 DebugLoc DL = MBB.findDebugLoc(MI);
2256 MachineFunction &MF = *MBB.getParent();
2257 unsigned FPReg = RI.getFrameRegister(MF);
2258 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2259 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2260 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
2261 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2262 unsigned Reg = CSI[i].getReg();
2264 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
2266 const TargetRegisterClass *RegClass = CSI[i].getRegClass();
2267 if (RegClass != &X86::VR128RegClass && !isWin64) {
2268 BuildMI(MBB, MI, DL, get(Opc), Reg);
2270 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
2276 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2277 const SmallVectorImpl<MachineOperand> &MOs,
2279 const TargetInstrInfo &TII) {
2280 // Create the base instruction with the memory operand as the first part.
2281 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2282 MI->getDebugLoc(), true);
2283 MachineInstrBuilder MIB(NewMI);
2284 unsigned NumAddrOps = MOs.size();
2285 for (unsigned i = 0; i != NumAddrOps; ++i)
2286 MIB.addOperand(MOs[i]);
2287 if (NumAddrOps < 4) // FrameIndex only
2290 // Loop over the rest of the ri operands, converting them over.
2291 unsigned NumOps = MI->getDesc().getNumOperands()-2;
2292 for (unsigned i = 0; i != NumOps; ++i) {
2293 MachineOperand &MO = MI->getOperand(i+2);
2296 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2297 MachineOperand &MO = MI->getOperand(i);
2303 static MachineInstr *FuseInst(MachineFunction &MF,
2304 unsigned Opcode, unsigned OpNo,
2305 const SmallVectorImpl<MachineOperand> &MOs,
2306 MachineInstr *MI, const TargetInstrInfo &TII) {
2307 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2308 MI->getDebugLoc(), true);
2309 MachineInstrBuilder MIB(NewMI);
2311 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2312 MachineOperand &MO = MI->getOperand(i);
2314 assert(MO.isReg() && "Expected to fold into reg operand!");
2315 unsigned NumAddrOps = MOs.size();
2316 for (unsigned i = 0; i != NumAddrOps; ++i)
2317 MIB.addOperand(MOs[i]);
2318 if (NumAddrOps < 4) // FrameIndex only
2327 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2328 const SmallVectorImpl<MachineOperand> &MOs,
2330 MachineFunction &MF = *MI->getParent()->getParent();
2331 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2333 unsigned NumAddrOps = MOs.size();
2334 for (unsigned i = 0; i != NumAddrOps; ++i)
2335 MIB.addOperand(MOs[i]);
2336 if (NumAddrOps < 4) // FrameIndex only
2338 return MIB.addImm(0);
2342 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2343 MachineInstr *MI, unsigned i,
2344 const SmallVectorImpl<MachineOperand> &MOs,
2345 unsigned Size, unsigned Align) const {
2346 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2347 bool isTwoAddrFold = false;
2348 unsigned NumOps = MI->getDesc().getNumOperands();
2349 bool isTwoAddr = NumOps > 1 &&
2350 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2352 MachineInstr *NewMI = NULL;
2353 // Folding a memory location into the two-address part of a two-address
2354 // instruction is different than folding it other places. It requires
2355 // replacing the *two* registers with the memory location.
2356 if (isTwoAddr && NumOps >= 2 && i < 2 &&
2357 MI->getOperand(0).isReg() &&
2358 MI->getOperand(1).isReg() &&
2359 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2360 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2361 isTwoAddrFold = true;
2362 } else if (i == 0) { // If operand 0
2363 if (MI->getOpcode() == X86::MOV64r0)
2364 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2365 else if (MI->getOpcode() == X86::MOV32r0)
2366 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2367 else if (MI->getOpcode() == X86::MOV16r0)
2368 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2369 else if (MI->getOpcode() == X86::MOV8r0)
2370 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2374 OpcodeTablePtr = &RegOp2MemOpTable0;
2375 } else if (i == 1) {
2376 OpcodeTablePtr = &RegOp2MemOpTable1;
2377 } else if (i == 2) {
2378 OpcodeTablePtr = &RegOp2MemOpTable2;
2381 // If table selected...
2382 if (OpcodeTablePtr) {
2383 // Find the Opcode to fuse
2384 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2385 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
2386 if (I != OpcodeTablePtr->end()) {
2387 unsigned Opcode = I->second.first;
2388 unsigned MinAlign = I->second.second;
2389 if (Align < MinAlign)
2391 bool NarrowToMOV32rm = false;
2393 unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize();
2394 if (Size < RCSize) {
2395 // Check if it's safe to fold the load. If the size of the object is
2396 // narrower than the load width, then it's not.
2397 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2399 // If this is a 64-bit load, but the spill slot is 32, then we can do
2400 // a 32-bit load which is implicitly zero-extended. This likely is due
2401 // to liveintervalanalysis remat'ing a load from stack slot.
2402 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2404 Opcode = X86::MOV32rm;
2405 NarrowToMOV32rm = true;
2410 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2412 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2414 if (NarrowToMOV32rm) {
2415 // If this is the special case where we use a MOV32rm to load a 32-bit
2416 // value and zero-extend the top bits. Change the destination register
2418 unsigned DstReg = NewMI->getOperand(0).getReg();
2419 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2420 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2421 4/*x86_subreg_32bit*/));
2423 NewMI->getOperand(0).setSubReg(4/*x86_subreg_32bit*/);
2430 if (PrintFailedFusing)
2431 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
2436 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2438 const SmallVectorImpl<unsigned> &Ops,
2439 int FrameIndex) const {
2440 // Check switch flag
2441 if (NoFusing) return NULL;
2443 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2444 switch (MI->getOpcode()) {
2445 case X86::CVTSD2SSrr:
2446 case X86::Int_CVTSD2SSrr:
2447 case X86::CVTSS2SDrr:
2448 case X86::Int_CVTSS2SDrr:
2450 case X86::RCPSSr_Int:
2451 case X86::ROUNDSDr_Int:
2452 case X86::ROUNDSSr_Int:
2454 case X86::RSQRTSSr_Int:
2456 case X86::SQRTSSr_Int:
2460 const MachineFrameInfo *MFI = MF.getFrameInfo();
2461 unsigned Size = MFI->getObjectSize(FrameIndex);
2462 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2463 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2464 unsigned NewOpc = 0;
2465 unsigned RCSize = 0;
2466 switch (MI->getOpcode()) {
2467 default: return NULL;
2468 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
2469 case X86::TEST16rr: NewOpc = X86::CMP16ri; RCSize = 2; break;
2470 case X86::TEST32rr: NewOpc = X86::CMP32ri; RCSize = 4; break;
2471 case X86::TEST64rr: NewOpc = X86::CMP64ri32; RCSize = 8; break;
2473 // Check if it's safe to fold the load. If the size of the object is
2474 // narrower than the load width, then it's not.
2477 // Change to CMPXXri r, 0 first.
2478 MI->setDesc(get(NewOpc));
2479 MI->getOperand(1).ChangeToImmediate(0);
2480 } else if (Ops.size() != 1)
2483 SmallVector<MachineOperand,4> MOs;
2484 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2485 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2488 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2490 const SmallVectorImpl<unsigned> &Ops,
2491 MachineInstr *LoadMI) const {
2492 // Check switch flag
2493 if (NoFusing) return NULL;
2495 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2496 switch (MI->getOpcode()) {
2497 case X86::CVTSD2SSrr:
2498 case X86::Int_CVTSD2SSrr:
2499 case X86::CVTSS2SDrr:
2500 case X86::Int_CVTSS2SDrr:
2502 case X86::RCPSSr_Int:
2503 case X86::ROUNDSDr_Int:
2504 case X86::ROUNDSSr_Int:
2506 case X86::RSQRTSSr_Int:
2508 case X86::SQRTSSr_Int:
2512 // Determine the alignment of the load.
2513 unsigned Alignment = 0;
2514 if (LoadMI->hasOneMemOperand())
2515 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
2517 switch (LoadMI->getOpcode()) {
2519 case X86::V_SETALLONES:
2529 llvm_unreachable("Don't know how to fold this instruction!");
2531 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2532 unsigned NewOpc = 0;
2533 switch (MI->getOpcode()) {
2534 default: return NULL;
2535 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2536 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2537 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2538 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2540 // Change to CMPXXri r, 0 first.
2541 MI->setDesc(get(NewOpc));
2542 MI->getOperand(1).ChangeToImmediate(0);
2543 } else if (Ops.size() != 1)
2546 SmallVector<MachineOperand,X86AddrNumOperands> MOs;
2547 switch (LoadMI->getOpcode()) {
2549 case X86::V_SETALLONES:
2551 case X86::FsFLD0SS: {
2552 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
2553 // Create a constant-pool entry and operands to load from it.
2555 // Medium and large mode can't fold loads this way.
2556 if (TM.getCodeModel() != CodeModel::Small &&
2557 TM.getCodeModel() != CodeModel::Kernel)
2560 // x86-32 PIC requires a PIC base register for constant pools.
2561 unsigned PICBase = 0;
2562 if (TM.getRelocationModel() == Reloc::PIC_) {
2563 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2566 // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
2567 // This doesn't work for several reasons.
2568 // 1. GlobalBaseReg may have been spilled.
2569 // 2. It may not be live at MI.
2573 // Create a constant-pool entry.
2574 MachineConstantPool &MCP = *MF.getConstantPool();
2576 if (LoadMI->getOpcode() == X86::FsFLD0SS)
2577 Ty = Type::getFloatTy(MF.getFunction()->getContext());
2578 else if (LoadMI->getOpcode() == X86::FsFLD0SD)
2579 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
2581 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
2582 Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ?
2583 Constant::getAllOnesValue(Ty) :
2584 Constant::getNullValue(Ty);
2585 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
2587 // Create operands to load from the constant pool entry.
2588 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2589 MOs.push_back(MachineOperand::CreateImm(1));
2590 MOs.push_back(MachineOperand::CreateReg(0, false));
2591 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2592 MOs.push_back(MachineOperand::CreateReg(0, false));
2596 // Folding a normal load. Just copy the load's address operands.
2597 unsigned NumOps = LoadMI->getDesc().getNumOperands();
2598 for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i)
2599 MOs.push_back(LoadMI->getOperand(i));
2603 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
2607 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2608 const SmallVectorImpl<unsigned> &Ops) const {
2609 // Check switch flag
2610 if (NoFusing) return 0;
2612 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2613 switch (MI->getOpcode()) {
2614 default: return false;
2623 if (Ops.size() != 1)
2626 unsigned OpNum = Ops[0];
2627 unsigned Opc = MI->getOpcode();
2628 unsigned NumOps = MI->getDesc().getNumOperands();
2629 bool isTwoAddr = NumOps > 1 &&
2630 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2632 // Folding a memory location into the two-address part of a two-address
2633 // instruction is different than folding it other places. It requires
2634 // replacing the *two* registers with the memory location.
2635 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2636 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2637 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2638 } else if (OpNum == 0) { // If operand 0
2647 OpcodeTablePtr = &RegOp2MemOpTable0;
2648 } else if (OpNum == 1) {
2649 OpcodeTablePtr = &RegOp2MemOpTable1;
2650 } else if (OpNum == 2) {
2651 OpcodeTablePtr = &RegOp2MemOpTable2;
2654 if (OpcodeTablePtr) {
2655 // Find the Opcode to fuse
2656 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2657 OpcodeTablePtr->find((unsigned*)Opc);
2658 if (I != OpcodeTablePtr->end())
2664 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2665 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2666 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2667 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2668 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2669 if (I == MemOp2RegOpTable.end())
2671 unsigned Opc = I->second.first;
2672 unsigned Index = I->second.second & 0xf;
2673 bool FoldedLoad = I->second.second & (1 << 4);
2674 bool FoldedStore = I->second.second & (1 << 5);
2675 if (UnfoldLoad && !FoldedLoad)
2677 UnfoldLoad &= FoldedLoad;
2678 if (UnfoldStore && !FoldedStore)
2680 UnfoldStore &= FoldedStore;
2682 const TargetInstrDesc &TID = get(Opc);
2683 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2684 const TargetRegisterClass *RC = TOI.getRegClass(&RI);
2685 SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
2686 SmallVector<MachineOperand,2> BeforeOps;
2687 SmallVector<MachineOperand,2> AfterOps;
2688 SmallVector<MachineOperand,4> ImpOps;
2689 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2690 MachineOperand &Op = MI->getOperand(i);
2691 if (i >= Index && i < Index + X86AddrNumOperands)
2692 AddrOps.push_back(Op);
2693 else if (Op.isReg() && Op.isImplicit())
2694 ImpOps.push_back(Op);
2696 BeforeOps.push_back(Op);
2698 AfterOps.push_back(Op);
2701 // Emit the load instruction.
2703 std::pair<MachineInstr::mmo_iterator,
2704 MachineInstr::mmo_iterator> MMOs =
2705 MF.extractLoadMemRefs(MI->memoperands_begin(),
2706 MI->memoperands_end());
2707 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
2709 // Address operands cannot be marked isKill.
2710 for (unsigned i = 1; i != 1 + X86AddrNumOperands; ++i) {
2711 MachineOperand &MO = NewMIs[0]->getOperand(i);
2713 MO.setIsKill(false);
2718 // Emit the data processing instruction.
2719 MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true);
2720 MachineInstrBuilder MIB(DataMI);
2723 MIB.addReg(Reg, RegState::Define);
2724 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2725 MIB.addOperand(BeforeOps[i]);
2728 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2729 MIB.addOperand(AfterOps[i]);
2730 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2731 MachineOperand &MO = ImpOps[i];
2732 MIB.addReg(MO.getReg(),
2733 getDefRegState(MO.isDef()) |
2734 RegState::Implicit |
2735 getKillRegState(MO.isKill()) |
2736 getDeadRegState(MO.isDead()) |
2737 getUndefRegState(MO.isUndef()));
2739 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2740 unsigned NewOpc = 0;
2741 switch (DataMI->getOpcode()) {
2743 case X86::CMP64ri32:
2747 MachineOperand &MO0 = DataMI->getOperand(0);
2748 MachineOperand &MO1 = DataMI->getOperand(1);
2749 if (MO1.getImm() == 0) {
2750 switch (DataMI->getOpcode()) {
2752 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2753 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2754 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2755 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2757 DataMI->setDesc(get(NewOpc));
2758 MO1.ChangeToRegister(MO0.getReg(), false);
2762 NewMIs.push_back(DataMI);
2764 // Emit the store instruction.
2766 const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI);
2767 std::pair<MachineInstr::mmo_iterator,
2768 MachineInstr::mmo_iterator> MMOs =
2769 MF.extractStoreMemRefs(MI->memoperands_begin(),
2770 MI->memoperands_end());
2771 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
2778 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2779 SmallVectorImpl<SDNode*> &NewNodes) const {
2780 if (!N->isMachineOpcode())
2783 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2784 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode());
2785 if (I == MemOp2RegOpTable.end())
2787 unsigned Opc = I->second.first;
2788 unsigned Index = I->second.second & 0xf;
2789 bool FoldedLoad = I->second.second & (1 << 4);
2790 bool FoldedStore = I->second.second & (1 << 5);
2791 const TargetInstrDesc &TID = get(Opc);
2792 const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI);
2793 unsigned NumDefs = TID.NumDefs;
2794 std::vector<SDValue> AddrOps;
2795 std::vector<SDValue> BeforeOps;
2796 std::vector<SDValue> AfterOps;
2797 DebugLoc dl = N->getDebugLoc();
2798 unsigned NumOps = N->getNumOperands();
2799 for (unsigned i = 0; i != NumOps-1; ++i) {
2800 SDValue Op = N->getOperand(i);
2801 if (i >= Index-NumDefs && i < Index-NumDefs + X86AddrNumOperands)
2802 AddrOps.push_back(Op);
2803 else if (i < Index-NumDefs)
2804 BeforeOps.push_back(Op);
2805 else if (i > Index-NumDefs)
2806 AfterOps.push_back(Op);
2808 SDValue Chain = N->getOperand(NumOps-1);
2809 AddrOps.push_back(Chain);
2811 // Emit the load instruction.
2813 MachineFunction &MF = DAG.getMachineFunction();
2815 EVT VT = *RC->vt_begin();
2816 std::pair<MachineInstr::mmo_iterator,
2817 MachineInstr::mmo_iterator> MMOs =
2818 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2819 cast<MachineSDNode>(N)->memoperands_end());
2820 bool isAligned = (*MMOs.first)->getAlignment() >= 16;
2821 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
2822 VT, MVT::Other, &AddrOps[0], AddrOps.size());
2823 NewNodes.push_back(Load);
2825 // Preserve memory reference information.
2826 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2829 // Emit the data processing instruction.
2830 std::vector<EVT> VTs;
2831 const TargetRegisterClass *DstRC = 0;
2832 if (TID.getNumDefs() > 0) {
2833 DstRC = TID.OpInfo[0].getRegClass(&RI);
2834 VTs.push_back(*DstRC->vt_begin());
2836 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2837 EVT VT = N->getValueType(i);
2838 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2842 BeforeOps.push_back(SDValue(Load, 0));
2843 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2844 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
2846 NewNodes.push_back(NewNode);
2848 // Emit the store instruction.
2851 AddrOps.push_back(SDValue(NewNode, 0));
2852 AddrOps.push_back(Chain);
2853 std::pair<MachineInstr::mmo_iterator,
2854 MachineInstr::mmo_iterator> MMOs =
2855 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2856 cast<MachineSDNode>(N)->memoperands_end());
2857 bool isAligned = (*MMOs.first)->getAlignment() >= 16;
2858 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
2861 &AddrOps[0], AddrOps.size());
2862 NewNodes.push_back(Store);
2864 // Preserve memory reference information.
2865 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2871 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2872 bool UnfoldLoad, bool UnfoldStore,
2873 unsigned *LoadRegIndex) const {
2874 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2875 MemOp2RegOpTable.find((unsigned*)Opc);
2876 if (I == MemOp2RegOpTable.end())
2878 bool FoldedLoad = I->second.second & (1 << 4);
2879 bool FoldedStore = I->second.second & (1 << 5);
2880 if (UnfoldLoad && !FoldedLoad)
2882 if (UnfoldStore && !FoldedStore)
2885 *LoadRegIndex = I->second.second & 0xf;
2886 return I->second.first;
2890 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
2891 int64_t &Offset1, int64_t &Offset2) const {
2892 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
2894 unsigned Opc1 = Load1->getMachineOpcode();
2895 unsigned Opc2 = Load2->getMachineOpcode();
2897 default: return false;
2907 case X86::MMX_MOVD64rm:
2908 case X86::MMX_MOVQ64rm:
2909 case X86::FsMOVAPSrm:
2910 case X86::FsMOVAPDrm:
2913 case X86::MOVUPSrm_Int:
2917 case X86::MOVDQUrm_Int:
2921 default: return false;
2931 case X86::MMX_MOVD64rm:
2932 case X86::MMX_MOVQ64rm:
2933 case X86::FsMOVAPSrm:
2934 case X86::FsMOVAPDrm:
2937 case X86::MOVUPSrm_Int:
2941 case X86::MOVDQUrm_Int:
2945 // Check if chain operands and base addresses match.
2946 if (Load1->getOperand(0) != Load2->getOperand(0) ||
2947 Load1->getOperand(5) != Load2->getOperand(5))
2949 // Segment operands should match as well.
2950 if (Load1->getOperand(4) != Load2->getOperand(4))
2952 // Scale should be 1, Index should be Reg0.
2953 if (Load1->getOperand(1) == Load2->getOperand(1) &&
2954 Load1->getOperand(2) == Load2->getOperand(2)) {
2955 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
2957 SDValue Op2 = Load1->getOperand(2);
2958 if (!isa<RegisterSDNode>(Op2) ||
2959 cast<RegisterSDNode>(Op2)->getReg() != 0)
2962 // Now let's examine the displacements.
2963 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
2964 isa<ConstantSDNode>(Load2->getOperand(3))) {
2965 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
2966 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
2973 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
2974 int64_t Offset1, int64_t Offset2,
2975 unsigned NumLoads) const {
2976 assert(Offset2 > Offset1);
2977 if ((Offset2 - Offset1) / 8 > 64)
2980 unsigned Opc1 = Load1->getMachineOpcode();
2981 unsigned Opc2 = Load2->getMachineOpcode();
2983 return false; // FIXME: overly conservative?
2990 case X86::MMX_MOVD64rm:
2991 case X86::MMX_MOVQ64rm:
2995 EVT VT = Load1->getValueType(0);
2996 switch (VT.getSimpleVT().SimpleTy) {
2998 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
2999 // have 16 of them to play with.
3000 if (TM.getSubtargetImpl()->is64Bit()) {
3003 } else if (NumLoads)
3022 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
3023 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
3024 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
3025 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
3027 Cond[0].setImm(GetOppositeBranchCondition(CC));
3032 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
3033 // FIXME: Return false for x87 stack register classes for now. We can't
3034 // allow any loads of these registers before FpGet_ST0_80.
3035 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
3036 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
3040 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher)
3041 /// register? e.g. r8, xmm8, xmm13, etc.
3042 bool X86InstrInfo::isX86_64ExtendedReg(unsigned RegNo) {
3045 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
3046 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
3047 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
3048 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
3049 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
3050 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
3051 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
3052 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
3053 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
3054 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
3061 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
3062 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
3063 /// size, and 3) use of X86-64 extended registers.
3064 unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
3066 const TargetInstrDesc &Desc = MI.getDesc();
3068 // Pseudo instructions do not need REX prefix byte.
3069 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
3071 if (Desc.TSFlags & X86II::REX_W)
3074 unsigned NumOps = Desc.getNumOperands();
3076 bool isTwoAddr = NumOps > 1 &&
3077 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
3079 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
3080 unsigned i = isTwoAddr ? 1 : 0;
3081 for (unsigned e = NumOps; i != e; ++i) {
3082 const MachineOperand& MO = MI.getOperand(i);
3084 unsigned Reg = MO.getReg();
3085 if (isX86_64NonExtLowByteReg(Reg))
3090 switch (Desc.TSFlags & X86II::FormMask) {
3091 case X86II::MRMInitReg:
3092 if (isX86_64ExtendedReg(MI.getOperand(0)))
3093 REX |= (1 << 0) | (1 << 2);
3095 case X86II::MRMSrcReg: {
3096 if (isX86_64ExtendedReg(MI.getOperand(0)))
3098 i = isTwoAddr ? 2 : 1;
3099 for (unsigned e = NumOps; i != e; ++i) {
3100 const MachineOperand& MO = MI.getOperand(i);
3101 if (isX86_64ExtendedReg(MO))
3106 case X86II::MRMSrcMem: {
3107 if (isX86_64ExtendedReg(MI.getOperand(0)))
3110 i = isTwoAddr ? 2 : 1;
3111 for (; i != NumOps; ++i) {
3112 const MachineOperand& MO = MI.getOperand(i);
3114 if (isX86_64ExtendedReg(MO))
3121 case X86II::MRM0m: case X86II::MRM1m:
3122 case X86II::MRM2m: case X86II::MRM3m:
3123 case X86II::MRM4m: case X86II::MRM5m:
3124 case X86II::MRM6m: case X86II::MRM7m:
3125 case X86II::MRMDestMem: {
3126 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
3127 i = isTwoAddr ? 1 : 0;
3128 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
3131 for (; i != e; ++i) {
3132 const MachineOperand& MO = MI.getOperand(i);
3134 if (isX86_64ExtendedReg(MO))
3142 if (isX86_64ExtendedReg(MI.getOperand(0)))
3144 i = isTwoAddr ? 2 : 1;
3145 for (unsigned e = NumOps; i != e; ++i) {
3146 const MachineOperand& MO = MI.getOperand(i);
3147 if (isX86_64ExtendedReg(MO))
3157 /// sizePCRelativeBlockAddress - This method returns the size of a PC
3158 /// relative block address instruction
3160 static unsigned sizePCRelativeBlockAddress() {
3164 /// sizeGlobalAddress - Give the size of the emission of this global address
3166 static unsigned sizeGlobalAddress(bool dword) {
3167 return dword ? 8 : 4;
3170 /// sizeConstPoolAddress - Give the size of the emission of this constant
3173 static unsigned sizeConstPoolAddress(bool dword) {
3174 return dword ? 8 : 4;
3177 /// sizeExternalSymbolAddress - Give the size of the emission of this external
3180 static unsigned sizeExternalSymbolAddress(bool dword) {
3181 return dword ? 8 : 4;
3184 /// sizeJumpTableAddress - Give the size of the emission of this jump
3187 static unsigned sizeJumpTableAddress(bool dword) {
3188 return dword ? 8 : 4;
3191 static unsigned sizeConstant(unsigned Size) {
3195 static unsigned sizeRegModRMByte(){
3199 static unsigned sizeSIBByte(){
3203 static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
3204 unsigned FinalSize = 0;
3205 // If this is a simple integer displacement that doesn't require a relocation.
3207 FinalSize += sizeConstant(4);
3211 // Otherwise, this is something that requires a relocation.
3212 if (RelocOp->isGlobal()) {
3213 FinalSize += sizeGlobalAddress(false);
3214 } else if (RelocOp->isCPI()) {
3215 FinalSize += sizeConstPoolAddress(false);
3216 } else if (RelocOp->isJTI()) {
3217 FinalSize += sizeJumpTableAddress(false);
3219 llvm_unreachable("Unknown value to relocate!");
3224 static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
3225 bool IsPIC, bool Is64BitMode) {
3226 const MachineOperand &Op3 = MI.getOperand(Op+3);
3228 const MachineOperand *DispForReloc = 0;
3229 unsigned FinalSize = 0;
3231 // Figure out what sort of displacement we have to handle here.
3232 if (Op3.isGlobal()) {
3233 DispForReloc = &Op3;
3234 } else if (Op3.isCPI()) {
3235 if (Is64BitMode || IsPIC) {
3236 DispForReloc = &Op3;
3240 } else if (Op3.isJTI()) {
3241 if (Is64BitMode || IsPIC) {
3242 DispForReloc = &Op3;
3250 const MachineOperand &Base = MI.getOperand(Op);
3251 const MachineOperand &IndexReg = MI.getOperand(Op+2);
3253 unsigned BaseReg = Base.getReg();
3255 // Is a SIB byte needed?
3256 if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
3257 IndexReg.getReg() == 0 &&
3258 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
3259 if (BaseReg == 0) { // Just a displacement?
3260 // Emit special case [disp32] encoding
3262 FinalSize += getDisplacementFieldSize(DispForReloc);
3264 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
3265 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
3266 // Emit simple indirect register encoding... [EAX] f.e.
3268 // Be pessimistic and assume it's a disp32, not a disp8
3270 // Emit the most general non-SIB encoding: [REG+disp32]
3272 FinalSize += getDisplacementFieldSize(DispForReloc);
3276 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
3277 assert(IndexReg.getReg() != X86::ESP &&
3278 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
3280 bool ForceDisp32 = false;
3281 if (BaseReg == 0 || DispForReloc) {
3282 // Emit the normal disp32 encoding.
3289 FinalSize += sizeSIBByte();
3291 // Do we need to output a displacement?
3292 if (DispVal != 0 || ForceDisp32) {
3293 FinalSize += getDisplacementFieldSize(DispForReloc);
3300 static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
3301 const TargetInstrDesc *Desc,
3302 bool IsPIC, bool Is64BitMode) {
3304 unsigned Opcode = Desc->Opcode;
3305 unsigned FinalSize = 0;
3307 // Emit the lock opcode prefix as needed.
3308 if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
3310 // Emit segment override opcode prefix as needed.
3311 switch (Desc->TSFlags & X86II::SegOvrMask) {
3316 default: llvm_unreachable("Invalid segment!");
3317 case 0: break; // No segment override!
3320 // Emit the repeat opcode prefix as needed.
3321 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
3323 // Emit the operand size opcode prefix as needed.
3324 if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
3326 // Emit the address size opcode prefix as needed.
3327 if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
3329 bool Need0FPrefix = false;
3330 switch (Desc->TSFlags & X86II::Op0Mask) {
3331 case X86II::TB: // Two-byte opcode prefix
3332 case X86II::T8: // 0F 38
3333 case X86II::TA: // 0F 3A
3334 Need0FPrefix = true;
3336 case X86II::TF: // F2 0F 38
3338 Need0FPrefix = true;
3340 case X86II::REP: break; // already handled.
3341 case X86II::XS: // F3 0F
3343 Need0FPrefix = true;
3345 case X86II::XD: // F2 0F
3347 Need0FPrefix = true;
3349 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
3350 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
3352 break; // Two-byte opcode prefix
3353 default: llvm_unreachable("Invalid prefix!");
3354 case 0: break; // No prefix!
3359 unsigned REX = X86InstrInfo::determineREX(MI);
3364 // 0x0F escape code must be emitted just before the opcode.
3368 switch (Desc->TSFlags & X86II::Op0Mask) {
3369 case X86II::T8: // 0F 38
3372 case X86II::TA: // 0F 3A
3375 case X86II::TF: // F2 0F 38
3380 // If this is a two-address instruction, skip one of the register operands.
3381 unsigned NumOps = Desc->getNumOperands();
3383 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
3385 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
3386 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
3389 switch (Desc->TSFlags & X86II::FormMask) {
3390 default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
3392 // Remember the current PC offset, this is the PIC relocation
3397 case TargetOpcode::INLINEASM: {
3398 const MachineFunction *MF = MI.getParent()->getParent();
3399 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
3400 FinalSize += TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
3401 *MF->getTarget().getMCAsmInfo());
3404 case TargetOpcode::DBG_LABEL:
3405 case TargetOpcode::EH_LABEL:
3407 case TargetOpcode::IMPLICIT_DEF:
3408 case TargetOpcode::KILL:
3409 case X86::FP_REG_KILL:
3411 case X86::MOVPC32r: {
3412 // This emits the "call" portion of this pseudo instruction.
3414 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3423 if (CurOp != NumOps) {
3424 const MachineOperand &MO = MI.getOperand(CurOp++);
3426 FinalSize += sizePCRelativeBlockAddress();
3427 } else if (MO.isGlobal()) {
3428 FinalSize += sizeGlobalAddress(false);
3429 } else if (MO.isSymbol()) {
3430 FinalSize += sizeExternalSymbolAddress(false);
3431 } else if (MO.isImm()) {
3432 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3434 llvm_unreachable("Unknown RawFrm operand!");
3439 case X86II::AddRegFrm:
3443 if (CurOp != NumOps) {
3444 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3445 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
3447 FinalSize += sizeConstant(Size);
3450 if (Opcode == X86::MOV64ri)
3452 if (MO1.isGlobal()) {
3453 FinalSize += sizeGlobalAddress(dword);
3454 } else if (MO1.isSymbol())
3455 FinalSize += sizeExternalSymbolAddress(dword);
3456 else if (MO1.isCPI())
3457 FinalSize += sizeConstPoolAddress(dword);
3458 else if (MO1.isJTI())
3459 FinalSize += sizeJumpTableAddress(dword);
3464 case X86II::MRMDestReg: {
3466 FinalSize += sizeRegModRMByte();
3468 if (CurOp != NumOps) {
3470 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3474 case X86II::MRMDestMem: {
3476 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3477 CurOp += X86AddrNumOperands + 1;
3478 if (CurOp != NumOps) {
3480 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3485 case X86II::MRMSrcReg:
3487 FinalSize += sizeRegModRMByte();
3489 if (CurOp != NumOps) {
3491 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3495 case X86II::MRMSrcMem: {
3497 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
3498 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
3499 AddrOperands = X86AddrNumOperands - 1; // No segment register
3501 AddrOperands = X86AddrNumOperands;
3504 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
3505 CurOp += AddrOperands + 1;
3506 if (CurOp != NumOps) {
3508 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3513 case X86II::MRM0r: case X86II::MRM1r:
3514 case X86II::MRM2r: case X86II::MRM3r:
3515 case X86II::MRM4r: case X86II::MRM5r:
3516 case X86II::MRM6r: case X86II::MRM7r:
3518 if (Desc->getOpcode() == X86::LFENCE ||
3519 Desc->getOpcode() == X86::MFENCE) {
3520 // Special handling of lfence and mfence;
3521 FinalSize += sizeRegModRMByte();
3522 } else if (Desc->getOpcode() == X86::MONITOR ||
3523 Desc->getOpcode() == X86::MWAIT) {
3524 // Special handling of monitor and mwait.
3525 FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode.
3528 FinalSize += sizeRegModRMByte();
3531 if (CurOp != NumOps) {
3532 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3533 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
3535 FinalSize += sizeConstant(Size);
3538 if (Opcode == X86::MOV64ri32)
3540 if (MO1.isGlobal()) {
3541 FinalSize += sizeGlobalAddress(dword);
3542 } else if (MO1.isSymbol())
3543 FinalSize += sizeExternalSymbolAddress(dword);
3544 else if (MO1.isCPI())
3545 FinalSize += sizeConstPoolAddress(dword);
3546 else if (MO1.isJTI())
3547 FinalSize += sizeJumpTableAddress(dword);
3552 case X86II::MRM0m: case X86II::MRM1m:
3553 case X86II::MRM2m: case X86II::MRM3m:
3554 case X86II::MRM4m: case X86II::MRM5m:
3555 case X86II::MRM6m: case X86II::MRM7m: {
3558 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3559 CurOp += X86AddrNumOperands;
3561 if (CurOp != NumOps) {
3562 const MachineOperand &MO = MI.getOperand(CurOp++);
3563 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
3565 FinalSize += sizeConstant(Size);
3568 if (Opcode == X86::MOV64mi32)
3570 if (MO.isGlobal()) {
3571 FinalSize += sizeGlobalAddress(dword);
3572 } else if (MO.isSymbol())
3573 FinalSize += sizeExternalSymbolAddress(dword);
3574 else if (MO.isCPI())
3575 FinalSize += sizeConstPoolAddress(dword);
3576 else if (MO.isJTI())
3577 FinalSize += sizeJumpTableAddress(dword);
3591 case X86II::MRMInitReg:
3593 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
3594 FinalSize += sizeRegModRMByte();
3599 if (!Desc->isVariadic() && CurOp != NumOps) {
3601 raw_string_ostream Msg(msg);
3602 Msg << "Cannot determine size: " << MI;
3603 llvm_report_error(Msg.str());
3611 unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
3612 const TargetInstrDesc &Desc = MI->getDesc();
3613 bool IsPIC = TM.getRelocationModel() == Reloc::PIC_;
3614 bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
3615 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
3616 if (Desc.getOpcode() == X86::MOVPC32r)
3617 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);
3621 /// getGlobalBaseReg - Return a virtual register initialized with the
3622 /// the global base register value. Output instructions required to
3623 /// initialize the register in the function entry block, if necessary.
3625 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3626 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3627 "X86-64 PIC uses RIP relative addressing");
3629 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3630 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3631 if (GlobalBaseReg != 0)
3632 return GlobalBaseReg;
3634 // Insert the set of GlobalBaseReg into the first MBB of the function
3635 MachineBasicBlock &FirstMBB = MF->front();
3636 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3637 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
3638 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3639 unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3641 const TargetInstrInfo *TII = TM.getInstrInfo();
3642 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3643 // only used in JIT code emission as displacement to pc.
3644 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3646 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3647 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3648 if (TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3649 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3650 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3651 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3652 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3653 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3658 X86FI->setGlobalBaseReg(GlobalBaseReg);
3659 return GlobalBaseReg;