1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // Low word of MMX to GPR.
19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
20 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
21 // GPR to low word of MMX.
22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
23 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
25 //===----------------------------------------------------------------------===//
26 // MMX Pattern Fragments
27 //===----------------------------------------------------------------------===//
29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
30 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
32 //===----------------------------------------------------------------------===//
33 // SSE specific DAG Nodes.
34 //===----------------------------------------------------------------------===//
36 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
37 SDTCisFP<0>, SDTCisInt<2> ]>;
38 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
39 SDTCisFP<1>, SDTCisVT<3, i8>,
42 def X86umin : SDNode<"X86ISD::UMIN", SDTIntBinOp>;
43 def X86umax : SDNode<"X86ISD::UMAX", SDTIntBinOp>;
44 def X86smin : SDNode<"X86ISD::SMIN", SDTIntBinOp>;
45 def X86smax : SDNode<"X86ISD::SMAX", SDTIntBinOp>;
47 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
48 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
50 // Commutative and Associative FMIN and FMAX.
51 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
52 [SDNPCommutative, SDNPAssociative]>;
53 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
54 [SDNPCommutative, SDNPAssociative]>;
56 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
57 [SDNPCommutative, SDNPAssociative]>;
58 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
59 [SDNPCommutative, SDNPAssociative]>;
60 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
61 [SDNPCommutative, SDNPAssociative]>;
62 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
63 [SDNPCommutative, SDNPAssociative]>;
64 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
65 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
66 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
67 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
68 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
69 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
70 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
71 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
72 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
73 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
74 def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
75 //def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
76 def X86pshufb : SDNode<"X86ISD::PSHUFB",
77 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
79 def X86andnp : SDNode<"X86ISD::ANDNP",
80 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
82 def X86psign : SDNode<"X86ISD::PSIGN",
83 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
85 def X86pextrb : SDNode<"X86ISD::PEXTRB",
86 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
87 def X86pextrw : SDNode<"X86ISD::PEXTRW",
88 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
89 def X86pinsrb : SDNode<"X86ISD::PINSRB",
90 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
91 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
92 def X86pinsrw : SDNode<"X86ISD::PINSRW",
93 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
94 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
95 def X86insertps : SDNode<"X86ISD::INSERTPS",
96 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
97 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
98 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
99 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
101 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
102 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
104 def X86vzext : SDNode<"X86ISD::VZEXT",
105 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
106 SDTCisInt<0>, SDTCisInt<1>,
107 SDTCisOpSmallerThanOp<1, 0>]>>;
109 def X86vsext : SDNode<"X86ISD::VSEXT",
110 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
111 SDTCisInt<0>, SDTCisInt<1>,
112 SDTCisOpSmallerThanOp<1, 0>]>>;
114 def X86vtrunc : SDNode<"X86ISD::VTRUNC",
115 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
116 SDTCisInt<0>, SDTCisInt<1>,
117 SDTCisOpSmallerThanOp<0, 1>]>>;
118 def X86trunc : SDNode<"X86ISD::TRUNC",
119 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
120 SDTCisOpSmallerThanOp<0, 1>]>>;
122 def X86vtruncm : SDNode<"X86ISD::VTRUNCM",
123 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
124 SDTCisInt<0>, SDTCisInt<1>,
125 SDTCisVec<2>, SDTCisInt<2>,
126 SDTCisOpSmallerThanOp<0, 2>]>>;
127 def X86vfpext : SDNode<"X86ISD::VFPEXT",
128 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
129 SDTCisFP<0>, SDTCisFP<1>,
130 SDTCisOpSmallerThanOp<1, 0>]>>;
131 def X86vfpround: SDNode<"X86ISD::VFPROUND",
132 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
133 SDTCisFP<0>, SDTCisFP<1>,
134 SDTCisOpSmallerThanOp<0, 1>]>>;
136 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
137 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
138 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
139 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
140 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
142 def X86IntCmpMask : SDTypeProfile<1, 2,
143 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
144 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
145 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
148 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<0>, SDTCisVec<1>,
149 SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
150 def X86CmpMaskCCScalar :
151 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
153 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
154 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
155 def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
157 def X86vshl : SDNode<"X86ISD::VSHL",
158 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
160 def X86vsrl : SDNode<"X86ISD::VSRL",
161 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
163 def X86vsra : SDNode<"X86ISD::VSRA",
164 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
167 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
168 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
169 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
171 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
173 SDTCisSameAs<2, 1>]>;
174 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
175 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
176 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
177 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
178 def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
180 SDTCisSameAs<2, 1>]>>;
181 def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
183 SDTCisSameAs<2, 1>]>>;
184 def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
186 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
187 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
188 SDTCisSameAs<1,2>]>>;
189 def X86pmuldq : SDNode<"X86ISD::PMULDQ",
190 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
191 SDTCisSameAs<1,2>]>>;
193 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
194 // translated into one of the target nodes below during lowering.
195 // Note: this is a work in progress...
196 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
197 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
199 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
200 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
202 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
204 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
205 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
206 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
207 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
209 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
210 def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
212 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
213 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
215 def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
216 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
218 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
219 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
220 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
221 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
222 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
223 SDTCisVec<0>, SDTCisInt<2>]>;
224 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
225 SDTCisVec<0>, SDTCisInt<3>]>;
227 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
228 def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
230 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
231 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
232 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
234 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
236 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
237 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
238 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
240 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
241 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
243 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
244 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
245 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
247 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
248 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
250 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
251 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
252 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
254 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
255 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
257 def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
258 def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
259 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
260 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
261 def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
262 def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
264 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
266 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
267 def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;
268 def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
269 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
270 def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
271 [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
273 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
275 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
277 def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
278 def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
279 def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
280 def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
282 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
283 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
284 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
285 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
286 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
287 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
289 def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound>;
290 def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound>;
291 def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound>;
292 def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound>;
293 def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound>;
294 def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound>;
296 def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
297 def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
298 def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
300 def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
301 def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
303 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
304 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
306 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
307 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
308 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
311 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
312 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
314 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 3,
315 [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
316 SDTCisVec<3>, SDTCisVec<1>, SDTCisInt<1>]>, []>;
317 def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 3,
319 SDTCisVec<3>, SDTCisVec<1>, SDTCisInt<1>]>, []>;
321 //===----------------------------------------------------------------------===//
322 // SSE Complex Patterns
323 //===----------------------------------------------------------------------===//
325 // These are 'extloads' from a scalar to the low element of a vector, zeroing
326 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
328 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
329 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
331 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
332 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
335 def ssmem : Operand<v4f32> {
336 let PrintMethod = "printf32mem";
337 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
338 let ParserMatchClass = X86Mem32AsmOperand;
339 let OperandType = "OPERAND_MEMORY";
341 def sdmem : Operand<v2f64> {
342 let PrintMethod = "printf64mem";
343 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
344 let ParserMatchClass = X86Mem64AsmOperand;
345 let OperandType = "OPERAND_MEMORY";
348 //===----------------------------------------------------------------------===//
349 // SSE pattern fragments
350 //===----------------------------------------------------------------------===//
352 // 128-bit load pattern fragments
353 // NOTE: all 128-bit integer vector loads are promoted to v2i64
354 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
355 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
356 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
358 // 256-bit load pattern fragments
359 // NOTE: all 256-bit integer vector loads are promoted to v4i64
360 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
361 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
362 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
364 // 512-bit load pattern fragments
365 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
366 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
367 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
368 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
369 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
370 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
372 // 128-/256-/512-bit extload pattern fragments
373 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
374 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
375 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
377 // These are needed to match a scalar load that is used in a vector-only
378 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
379 // The memory operand is required to be a 128-bit load, so it must be converted
380 // from a vector to a scalar.
381 def loadf32_128 : PatFrag<(ops node:$ptr),
382 (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
383 def loadf64_128 : PatFrag<(ops node:$ptr),
384 (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
386 // Like 'store', but always requires 128-bit vector alignment.
387 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
388 (store node:$val, node:$ptr), [{
389 return cast<StoreSDNode>(N)->getAlignment() >= 16;
392 // Like 'store', but always requires 256-bit vector alignment.
393 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
394 (store node:$val, node:$ptr), [{
395 return cast<StoreSDNode>(N)->getAlignment() >= 32;
398 // Like 'store', but always requires 512-bit vector alignment.
399 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
400 (store node:$val, node:$ptr), [{
401 return cast<StoreSDNode>(N)->getAlignment() >= 64;
404 // Like 'load', but always requires 128-bit vector alignment.
405 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
406 return cast<LoadSDNode>(N)->getAlignment() >= 16;
409 // Like 'X86vzload', but always requires 128-bit vector alignment.
410 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
411 return cast<MemSDNode>(N)->getAlignment() >= 16;
414 // Like 'load', but always requires 256-bit vector alignment.
415 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
416 return cast<LoadSDNode>(N)->getAlignment() >= 32;
419 // Like 'load', but always requires 512-bit vector alignment.
420 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
421 return cast<LoadSDNode>(N)->getAlignment() >= 64;
424 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
425 (f32 (alignedload node:$ptr))>;
426 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
427 (f64 (alignedload node:$ptr))>;
429 // 128-bit aligned load pattern fragments
430 // NOTE: all 128-bit integer vector loads are promoted to v2i64
431 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
432 (v4f32 (alignedload node:$ptr))>;
433 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
434 (v2f64 (alignedload node:$ptr))>;
435 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
436 (v2i64 (alignedload node:$ptr))>;
438 // 256-bit aligned load pattern fragments
439 // NOTE: all 256-bit integer vector loads are promoted to v4i64
440 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
441 (v8f32 (alignedload256 node:$ptr))>;
442 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
443 (v4f64 (alignedload256 node:$ptr))>;
444 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
445 (v4i64 (alignedload256 node:$ptr))>;
447 // 512-bit aligned load pattern fragments
448 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
449 (v16f32 (alignedload512 node:$ptr))>;
450 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
451 (v16i32 (alignedload512 node:$ptr))>;
452 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
453 (v8f64 (alignedload512 node:$ptr))>;
454 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
455 (v8i64 (alignedload512 node:$ptr))>;
457 // Like 'load', but uses special alignment checks suitable for use in
458 // memory operands in most SSE instructions, which are required to
459 // be naturally aligned on some targets but not on others. If the subtarget
460 // allows unaligned accesses, match any load, though this may require
461 // setting a feature bit in the processor (on startup, for example).
462 // Opteron 10h and later implement such a feature.
463 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
464 return Subtarget->hasSSEUnalignedMem()
465 || cast<LoadSDNode>(N)->getAlignment() >= 16;
468 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
469 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
471 // 128-bit memop pattern fragments
472 // NOTE: all 128-bit integer vector loads are promoted to v2i64
473 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
474 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
475 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
477 // These are needed to match a scalar memop that is used in a vector-only
478 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
479 // The memory operand is required to be a 128-bit load, so it must be converted
480 // from a vector to a scalar.
481 def memopfsf32_128 : PatFrag<(ops node:$ptr),
482 (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
483 def memopfsf64_128 : PatFrag<(ops node:$ptr),
484 (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
487 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
489 // FIXME: 8 byte alignment for mmx reads is not required
490 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
491 return cast<LoadSDNode>(N)->getAlignment() >= 8;
494 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
497 // Like 'store', but requires the non-temporal bit to be set
498 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
499 (st node:$val, node:$ptr), [{
500 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
501 return ST->isNonTemporal();
505 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
506 (st node:$val, node:$ptr), [{
507 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
508 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
509 ST->getAddressingMode() == ISD::UNINDEXED &&
510 ST->getAlignment() >= 16;
514 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
515 (st node:$val, node:$ptr), [{
516 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
517 return ST->isNonTemporal() &&
518 ST->getAlignment() < 16;
522 // 128-bit bitconvert pattern fragments
523 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
524 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
525 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
526 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
527 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
528 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
530 // 256-bit bitconvert pattern fragments
531 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
532 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
533 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
534 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
535 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
537 // 512-bit bitconvert pattern fragments
538 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
539 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
540 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
541 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
543 def vzmovl_v2i64 : PatFrag<(ops node:$src),
544 (bitconvert (v2i64 (X86vzmovl
545 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
546 def vzmovl_v4i32 : PatFrag<(ops node:$src),
547 (bitconvert (v4i32 (X86vzmovl
548 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
550 def vzload_v2i64 : PatFrag<(ops node:$src),
551 (bitconvert (v2i64 (X86vzload node:$src)))>;
554 def fp32imm0 : PatLeaf<(f32 fpimm), [{
555 return N->isExactlyValue(+0.0);
558 def I8Imm : SDNodeXForm<imm, [{
559 // Transformation function: get the low 8 bits.
560 return getI8Imm((uint8_t)N->getZExtValue());
563 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
564 def FROUND_CURRENT : ImmLeaf<i32, [{
565 return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
568 // BYTE_imm - Transform bit immediates into byte immediates.
569 def BYTE_imm : SDNodeXForm<imm, [{
570 // Transformation function: imm >> 3
571 return getI32Imm(N->getZExtValue() >> 3);
574 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
575 // to VEXTRACTF128/VEXTRACTI128 imm.
576 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
577 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N));
580 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
581 // VINSERTF128/VINSERTI128 imm.
582 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
583 return getI8Imm(X86::getInsertVINSERT128Immediate(N));
586 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
587 // to VEXTRACTF64x4 imm.
588 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
589 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N));
592 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
594 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
595 return getI8Imm(X86::getInsertVINSERT256Immediate(N));
598 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
599 (extract_subvector node:$bigvec,
601 return X86::isVEXTRACT128Index(N);
602 }], EXTRACT_get_vextract128_imm>;
604 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
606 (insert_subvector node:$bigvec, node:$smallvec,
608 return X86::isVINSERT128Index(N);
609 }], INSERT_get_vinsert128_imm>;
612 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
613 (extract_subvector node:$bigvec,
615 return X86::isVEXTRACT256Index(N);
616 }], EXTRACT_get_vextract256_imm>;
618 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
620 (insert_subvector node:$bigvec, node:$smallvec,
622 return X86::isVINSERT256Index(N);
623 }], INSERT_get_vinsert256_imm>;