1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX Pattern Fragments
16 //===----------------------------------------------------------------------===//
18 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
19 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
21 //===----------------------------------------------------------------------===//
22 // SSE specific DAG Nodes.
23 //===----------------------------------------------------------------------===//
25 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
26 SDTCisFP<0>, SDTCisInt<2> ]>;
27 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
28 SDTCisFP<1>, SDTCisVT<3, i8>]>;
30 def X86umin : SDNode<"X86ISD::UMIN", SDTIntBinOp>;
31 def X86umax : SDNode<"X86ISD::UMAX", SDTIntBinOp>;
32 def X86smin : SDNode<"X86ISD::SMIN", SDTIntBinOp>;
33 def X86smax : SDNode<"X86ISD::SMAX", SDTIntBinOp>;
35 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
36 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
38 // Commutative and Associative FMIN and FMAX.
39 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
40 [SDNPCommutative, SDNPAssociative]>;
41 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
42 [SDNPCommutative, SDNPAssociative]>;
44 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
45 [SDNPCommutative, SDNPAssociative]>;
46 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
47 [SDNPCommutative, SDNPAssociative]>;
48 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
49 [SDNPCommutative, SDNPAssociative]>;
50 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
51 [SDNPCommutative, SDNPAssociative]>;
52 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
53 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
54 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
55 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
56 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
57 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
58 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
59 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
60 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
61 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
62 def X86cmpss : SDNode<"X86ISD::FSETCCss", SDTX86Cmpss>;
63 def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
64 def X86pshufb : SDNode<"X86ISD::PSHUFB",
65 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
67 def X86andnp : SDNode<"X86ISD::ANDNP",
68 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
70 def X86psign : SDNode<"X86ISD::PSIGN",
71 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
73 def X86pextrb : SDNode<"X86ISD::PEXTRB",
74 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
75 def X86pextrw : SDNode<"X86ISD::PEXTRW",
76 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
77 def X86pinsrb : SDNode<"X86ISD::PINSRB",
78 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
79 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
80 def X86pinsrw : SDNode<"X86ISD::PINSRW",
81 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
82 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
83 def X86insrtps : SDNode<"X86ISD::INSERTPS",
84 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
85 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
86 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
87 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
89 def X86vzmovly : SDNode<"X86ISD::VZEXT_MOVL",
90 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
91 SDTCisOpSmallerThanOp<1, 0> ]>>;
93 def X86vsmovl : SDNode<"X86ISD::VSEXT_MOVL",
95 [SDTCisVec<0>, SDTCisInt<1>, SDTCisInt<0>]>>;
97 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
98 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
100 def X86vzext : SDNode<"X86ISD::VZEXT",
101 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
102 SDTCisInt<0>, SDTCisInt<1>]>>;
104 def X86vsext : SDNode<"X86ISD::VSEXT",
105 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
106 SDTCisInt<0>, SDTCisInt<1>]>>;
108 def X86vfpext : SDNode<"X86ISD::VFPEXT",
109 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
110 SDTCisFP<0>, SDTCisFP<1>]>>;
111 def X86vfpround: SDNode<"X86ISD::VFPROUND",
112 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
113 SDTCisFP<0>, SDTCisFP<1>]>>;
115 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
116 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
117 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
118 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
119 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
121 def X86IntCmpMask : SDTypeProfile<1, 2,
122 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
123 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
124 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
126 def X86CmpMaskCC : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
127 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
128 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
130 def X86vshl : SDNode<"X86ISD::VSHL",
131 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
133 def X86vsrl : SDNode<"X86ISD::VSRL",
134 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
136 def X86vsra : SDNode<"X86ISD::VSRA",
137 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
140 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
141 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
142 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
144 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
146 SDTCisSameAs<2, 1>]>;
147 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
148 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
149 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
150 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
151 def X86ktest : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
152 def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
154 SDTCisSameAs<2, 1>]>>;
156 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
157 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
158 SDTCisSameAs<1,2>]>>;
160 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
161 // translated into one of the target nodes below during lowering.
162 // Note: this is a work in progress...
163 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
164 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
166 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
167 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
169 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
170 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
171 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
172 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
174 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
175 def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
177 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
178 SDTCisSameAs<1,2>, SDTCisVT<3, i32>]>;
180 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
181 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
183 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
185 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
186 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
187 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
189 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
191 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
192 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
193 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
195 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
196 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
198 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
199 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
200 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
202 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
203 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
205 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
206 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
208 def X86VPermilp : SDNode<"X86ISD::VPERMILP", SDTShuff2OpI>;
209 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
210 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
211 def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
213 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
215 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
216 def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;
218 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
219 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
220 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
221 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
222 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
223 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
224 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
226 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
227 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
229 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
230 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
231 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
234 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
235 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
237 //===----------------------------------------------------------------------===//
238 // SSE Complex Patterns
239 //===----------------------------------------------------------------------===//
241 // These are 'extloads' from a scalar to the low element of a vector, zeroing
242 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
244 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
245 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
247 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
248 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
251 def ssmem : Operand<v4f32> {
252 let PrintMethod = "printf32mem";
253 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
254 let ParserMatchClass = X86MemAsmOperand;
255 let OperandType = "OPERAND_MEMORY";
257 def sdmem : Operand<v2f64> {
258 let PrintMethod = "printf64mem";
259 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
260 let ParserMatchClass = X86MemAsmOperand;
261 let OperandType = "OPERAND_MEMORY";
264 //===----------------------------------------------------------------------===//
265 // SSE pattern fragments
266 //===----------------------------------------------------------------------===//
268 // 128-bit load pattern fragments
269 // NOTE: all 128-bit integer vector loads are promoted to v2i64
270 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
271 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
272 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
274 // 256-bit load pattern fragments
275 // NOTE: all 256-bit integer vector loads are promoted to v4i64
276 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
277 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
278 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
280 // 512-bit load pattern fragments
281 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
282 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
283 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
285 // 128-/256-/512-bit extload pattern fragments
286 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
287 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
288 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
290 // Like 'store', but always requires 128-bit vector alignment.
291 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
292 (store node:$val, node:$ptr), [{
293 return cast<StoreSDNode>(N)->getAlignment() >= 16;
296 // Like 'store', but always requires 256-bit vector alignment.
297 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
298 (store node:$val, node:$ptr), [{
299 return cast<StoreSDNode>(N)->getAlignment() >= 32;
302 // Like 'store', but always requires 512-bit vector alignment.
303 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
304 (store node:$val, node:$ptr), [{
305 return cast<StoreSDNode>(N)->getAlignment() >= 64;
308 // Like 'load', but always requires 128-bit vector alignment.
309 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
310 return cast<LoadSDNode>(N)->getAlignment() >= 16;
313 // Like 'X86vzload', but always requires 128-bit vector alignment.
314 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
315 return cast<MemSDNode>(N)->getAlignment() >= 16;
318 // Like 'load', but always requires 256-bit vector alignment.
319 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
320 return cast<LoadSDNode>(N)->getAlignment() >= 32;
323 // Like 'load', but always requires 512-bit vector alignment.
324 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
325 return cast<LoadSDNode>(N)->getAlignment() >= 64;
328 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
329 (f32 (alignedload node:$ptr))>;
330 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
331 (f64 (alignedload node:$ptr))>;
333 // 128-bit aligned load pattern fragments
334 // NOTE: all 128-bit integer vector loads are promoted to v2i64
335 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
336 (v4f32 (alignedload node:$ptr))>;
337 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
338 (v2f64 (alignedload node:$ptr))>;
339 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
340 (v2i64 (alignedload node:$ptr))>;
342 // 256-bit aligned load pattern fragments
343 // NOTE: all 256-bit integer vector loads are promoted to v4i64
344 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
345 (v8f32 (alignedload256 node:$ptr))>;
346 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
347 (v4f64 (alignedload256 node:$ptr))>;
348 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
349 (v4i64 (alignedload256 node:$ptr))>;
351 // 512-bit aligned load pattern fragments
352 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
353 (v16f32 (alignedload512 node:$ptr))>;
354 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
355 (v16i32 (alignedload512 node:$ptr))>;
356 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
357 (v8f64 (alignedload512 node:$ptr))>;
358 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
359 (v8i64 (alignedload512 node:$ptr))>;
361 // Like 'load', but uses special alignment checks suitable for use in
362 // memory operands in most SSE instructions, which are required to
363 // be naturally aligned on some targets but not on others. If the subtarget
364 // allows unaligned accesses, match any load, though this may require
365 // setting a feature bit in the processor (on startup, for example).
366 // Opteron 10h and later implement such a feature.
367 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
368 return Subtarget->hasVectorUAMem()
369 || cast<LoadSDNode>(N)->getAlignment() >= 16;
372 def memop4 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
373 return Subtarget->hasVectorUAMem()
374 || cast<LoadSDNode>(N)->getAlignment() >= 4;
377 def memop8 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
378 return Subtarget->hasVectorUAMem()
379 || cast<LoadSDNode>(N)->getAlignment() >= 8;
382 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
383 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
385 // 128-bit memop pattern fragments
386 // NOTE: all 128-bit integer vector loads are promoted to v2i64
387 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
388 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
389 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
391 // 256-bit memop pattern fragments
392 // NOTE: all 256-bit integer vector loads are promoted to v4i64
393 def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>;
394 def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>;
395 def memopv4i64 : PatFrag<(ops node:$ptr), (v4i64 (memop node:$ptr))>;
397 // 512-bit memop pattern fragments
398 def memopv16f32 : PatFrag<(ops node:$ptr), (v16f32 (memop4 node:$ptr))>;
399 def memopv8f64 : PatFrag<(ops node:$ptr), (v8f64 (memop8 node:$ptr))>;
400 def memopv16i32 : PatFrag<(ops node:$ptr), (v16i32 (memop4 node:$ptr))>;
401 def memopv8i64 : PatFrag<(ops node:$ptr), (v8i64 (memop8 node:$ptr))>;
403 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
405 // FIXME: 8 byte alignment for mmx reads is not required
406 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
407 return cast<LoadSDNode>(N)->getAlignment() >= 8;
410 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
413 // Like 'store', but requires the non-temporal bit to be set
414 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
415 (st node:$val, node:$ptr), [{
416 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
417 return ST->isNonTemporal();
421 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
422 (st node:$val, node:$ptr), [{
423 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
424 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
425 ST->getAddressingMode() == ISD::UNINDEXED &&
426 ST->getAlignment() >= 16;
430 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
431 (st node:$val, node:$ptr), [{
432 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
433 return ST->isNonTemporal() &&
434 ST->getAlignment() < 16;
438 // 128-bit bitconvert pattern fragments
439 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
440 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
441 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
442 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
443 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
444 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
446 // 256-bit bitconvert pattern fragments
447 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
448 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
449 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
450 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
452 // 512-bit bitconvert pattern fragments
453 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
454 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
456 def vzmovl_v2i64 : PatFrag<(ops node:$src),
457 (bitconvert (v2i64 (X86vzmovl
458 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
459 def vzmovl_v4i32 : PatFrag<(ops node:$src),
460 (bitconvert (v4i32 (X86vzmovl
461 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
463 def vzload_v2i64 : PatFrag<(ops node:$src),
464 (bitconvert (v2i64 (X86vzload node:$src)))>;
467 def fp32imm0 : PatLeaf<(f32 fpimm), [{
468 return N->isExactlyValue(+0.0);
471 // BYTE_imm - Transform bit immediates into byte immediates.
472 def BYTE_imm : SDNodeXForm<imm, [{
473 // Transformation function: imm >> 3
474 return getI32Imm(N->getZExtValue() >> 3);
477 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
478 // to VEXTRACTF128/VEXTRACTI128 imm.
479 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
480 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N));
483 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
484 // VINSERTF128/VINSERTI128 imm.
485 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
486 return getI8Imm(X86::getInsertVINSERT128Immediate(N));
489 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
490 // to VEXTRACTF64x4 imm.
491 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
492 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N));
495 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
497 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
498 return getI8Imm(X86::getInsertVINSERT256Immediate(N));
501 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
502 (extract_subvector node:$bigvec,
504 return X86::isVEXTRACT128Index(N);
505 }], EXTRACT_get_vextract128_imm>;
507 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
509 (insert_subvector node:$bigvec, node:$smallvec,
511 return X86::isVINSERT128Index(N);
512 }], INSERT_get_vinsert128_imm>;
515 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
516 (extract_subvector node:$bigvec,
518 return X86::isVEXTRACT256Index(N);
519 }], EXTRACT_get_vextract256_imm>;
521 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
523 (insert_subvector node:$bigvec, node:$smallvec,
525 return X86::isVINSERT256Index(N);
526 }], INSERT_get_vinsert256_imm>;