1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>; def RawFrmMemOffs : Format<7>;
25 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
26 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
27 def MRM6r : Format<22>; def MRM7r : Format<23>;
28 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
29 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
30 def MRM6m : Format<30>; def MRM7m : Format<31>;
31 def MRM_C1 : Format<33>;
32 def MRM_C2 : Format<34>;
33 def MRM_C3 : Format<35>;
34 def MRM_C4 : Format<36>;
35 def MRM_C8 : Format<37>;
36 def MRM_C9 : Format<38>;
37 def MRM_CA : Format<39>;
38 def MRM_CB : Format<40>;
39 def MRM_E8 : Format<41>;
40 def MRM_F0 : Format<42>;
41 def RawFrmImm8 : Format<43>;
42 def RawFrmImm16 : Format<44>;
43 def MRM_F8 : Format<45>;
44 def MRM_F9 : Format<46>;
45 def MRM_D0 : Format<47>;
46 def MRM_D1 : Format<48>;
47 def MRM_D4 : Format<49>;
48 def MRM_D5 : Format<50>;
49 def MRM_D6 : Format<51>;
50 def MRM_D8 : Format<52>;
51 def MRM_D9 : Format<53>;
52 def MRM_DA : Format<54>;
53 def MRM_DB : Format<55>;
54 def MRM_DC : Format<56>;
55 def MRM_DD : Format<57>;
56 def MRM_DE : Format<58>;
57 def MRM_DF : Format<59>;
59 // ImmType - This specifies the immediate type used by an instruction. This is
60 // part of the ad-hoc solution used to emit machine instruction encodings by our
61 // machine code emitter.
62 class ImmType<bits<3> val> {
65 def NoImm : ImmType<0>;
66 def Imm8 : ImmType<1>;
67 def Imm8PCRel : ImmType<2>;
68 def Imm16 : ImmType<3>;
69 def Imm16PCRel : ImmType<4>;
70 def Imm32 : ImmType<5>;
71 def Imm32PCRel : ImmType<6>;
72 def Imm64 : ImmType<7>;
74 // FPFormat - This specifies what form this FP instruction has. This is used by
75 // the Floating-Point stackifier pass.
76 class FPFormat<bits<3> val> {
79 def NotFP : FPFormat<0>;
80 def ZeroArgFP : FPFormat<1>;
81 def OneArgFP : FPFormat<2>;
82 def OneArgFPRW : FPFormat<3>;
83 def TwoArgFP : FPFormat<4>;
84 def CompareFP : FPFormat<5>;
85 def CondMovFP : FPFormat<6>;
86 def SpecialFP : FPFormat<7>;
88 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
89 // Keep in sync with tables in X86InstrInfo.cpp.
90 class Domain<bits<2> val> {
93 def GenericDomain : Domain<0>;
94 def SSEPackedSingle : Domain<1>;
95 def SSEPackedDouble : Domain<2>;
96 def SSEPackedInt : Domain<3>;
98 // Class specifying the vector form of the decompressed
99 // displacement of 8-bit.
100 class CD8VForm<bits<3> val> {
103 def CD8VF : CD8VForm<0>; // v := VL
104 def CD8VH : CD8VForm<1>; // v := VL/2
105 def CD8VQ : CD8VForm<2>; // v := VL/4
106 def CD8VO : CD8VForm<3>; // v := VL/8
107 def CD8VT1 : CD8VForm<4>; // v := 1
108 def CD8VT2 : CD8VForm<5>; // v := 2
109 def CD8VT4 : CD8VForm<6>; // v := 4
110 def CD8VT8 : CD8VForm<7>; // v := 8
112 // Prefix byte classes which are used to indicate to the ad-hoc machine code
113 // emitter that various prefix bytes are required.
114 class OpSize { bit hasOpSizePrefix = 1; }
115 class OpSize16 { bit hasOpSize16Prefix = 1; }
116 class AdSize { bit hasAdSizePrefix = 1; }
117 class REX_W { bit hasREX_WPrefix = 1; }
118 class LOCK { bit hasLockPrefix = 1; }
119 class TB { bits<5> Prefix = 1; }
120 class REP { bits<5> Prefix = 2; }
121 class D8 { bits<5> Prefix = 3; }
122 class D9 { bits<5> Prefix = 4; }
123 class DA { bits<5> Prefix = 5; }
124 class DB { bits<5> Prefix = 6; }
125 class DC { bits<5> Prefix = 7; }
126 class DD { bits<5> Prefix = 8; }
127 class DE { bits<5> Prefix = 9; }
128 class DF { bits<5> Prefix = 10; }
129 class XD { bits<5> Prefix = 11; }
130 class XS { bits<5> Prefix = 12; }
131 class T8 { bits<5> Prefix = 13; }
132 class TA { bits<5> Prefix = 14; }
133 class A6 { bits<5> Prefix = 15; }
134 class A7 { bits<5> Prefix = 16; }
135 class T8XD { bits<5> Prefix = 17; }
136 class T8XS { bits<5> Prefix = 18; }
137 class TAXD { bits<5> Prefix = 19; }
138 class XOP8 { bits<5> Prefix = 20; }
139 class XOP9 { bits<5> Prefix = 21; }
140 class XOPA { bits<5> Prefix = 22; }
141 class PD { bits<5> Prefix = 23; }
142 class T8PD { bits<5> Prefix = 24; }
143 class TAPD { bits<5> Prefix = 25; }
144 class VEX { bit hasVEXPrefix = 1; }
145 class VEX_W { bit hasVEX_WPrefix = 1; }
146 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
147 class VEX_4VOp3 : VEX { bit hasVEX_4VOp3Prefix = 1; }
148 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
149 class VEX_L { bit hasVEX_L = 1; }
150 class VEX_LIG { bit ignoresVEX_L = 1; }
151 class EVEX : VEX { bit hasEVEXPrefix = 1; }
152 class EVEX_4V : VEX_4V { bit hasEVEXPrefix = 1; }
153 class EVEX_K { bit hasEVEX_K = 1; }
154 class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; }
155 class EVEX_B { bit hasEVEX_B = 1; }
156 class EVEX_RC { bit hasEVEX_RC = 1; }
157 class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; }
158 class EVEX_CD8<int esize, CD8VForm form> {
159 bits<2> EVEX_CD8E = !if(!eq(esize, 8), 0b00,
160 !if(!eq(esize, 16), 0b01,
161 !if(!eq(esize, 32), 0b10,
162 !if(!eq(esize, 64), 0b11, ?))));
163 bits<3> EVEX_CD8V = form.Value;
165 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
166 class MemOp4 { bit hasMemOp4Prefix = 1; }
167 class XOP { bit hasXOP_Prefix = 1; }
168 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
171 Domain d = GenericDomain>
173 let Namespace = "X86";
175 bits<8> Opcode = opcod;
177 bits<6> FormBits = Form.Value;
180 dag OutOperandList = outs;
181 dag InOperandList = ins;
182 string AsmString = AsmStr;
184 // If this is a pseudo instruction, mark it isCodeGenOnly.
185 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
187 let Itinerary = itin;
190 // Attributes specific to X86 instructions...
192 bit ForceDisassemble = 0; // Force instruction to disassemble even though it's
193 // isCodeGenonly. Needed to hide an ambiguous
194 // AsmString from the parser, but still disassemble.
196 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
197 bit hasOpSize16Prefix = 0;// Does this inst have a 0x66 prefix in 16-bit mode?
198 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
200 bits<5> Prefix = 0; // Which prefix byte does this inst have?
201 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
202 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
203 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
204 Domain ExeDomain = d;
205 bit hasVEXPrefix = 0; // Does this inst require a VEX prefix?
206 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
207 bit hasVEX_4VPrefix = 0; // Does this inst require the VEX.VVVV field?
208 bit hasVEX_4VOp3Prefix = 0; // Does this inst require the VEX.VVVV field to
209 // encode the third operand?
210 bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register
211 // to be encoded in a immediate field?
212 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
213 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
214 bit hasEVEXPrefix = 0; // Does this inst require EVEX form?
215 bit hasEVEX_K = 0; // Does this inst require masking?
216 bit hasEVEX_Z = 0; // Does this inst set the EVEX_Z field?
217 bit hasEVEX_L2 = 0; // Does this inst set the EVEX_L2 field?
218 bit hasEVEX_B = 0; // Does this inst set the EVEX_B field?
219 bits<2> EVEX_CD8E = 0; // Compressed disp8 form - element-size.
220 bits<3> EVEX_CD8V = 0; // Compressed disp8 form - vector-width.
221 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
222 bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands
223 bit hasXOP_Prefix = 0; // Does this inst require an XOP prefix?
224 bit hasEVEX_RC = 0; // Explicitly specified rounding control in FP instruction.
226 // TSFlags layout should be kept in sync with X86InstrInfo.h.
227 let TSFlags{5-0} = FormBits;
228 let TSFlags{6} = hasOpSizePrefix;
229 let TSFlags{7} = hasOpSize16Prefix;
230 let TSFlags{8} = hasAdSizePrefix;
231 let TSFlags{13-9} = Prefix;
232 let TSFlags{14} = hasREX_WPrefix;
233 let TSFlags{17-15} = ImmT.Value;
234 let TSFlags{20-18} = FPForm.Value;
235 let TSFlags{21} = hasLockPrefix;
236 let TSFlags{23-22} = ExeDomain.Value;
237 let TSFlags{31-24} = Opcode;
238 let TSFlags{32} = hasVEXPrefix;
239 let TSFlags{33} = hasVEX_WPrefix;
240 let TSFlags{34} = hasVEX_4VPrefix;
241 let TSFlags{35} = hasVEX_4VOp3Prefix;
242 let TSFlags{36} = hasVEX_i8ImmReg;
243 let TSFlags{37} = hasVEX_L;
244 let TSFlags{38} = ignoresVEX_L;
245 let TSFlags{39} = hasEVEXPrefix;
246 let TSFlags{40} = hasEVEX_K;
247 let TSFlags{41} = hasEVEX_Z;
248 let TSFlags{42} = hasEVEX_L2;
249 let TSFlags{43} = hasEVEX_B;
250 let TSFlags{45-44} = EVEX_CD8E;
251 let TSFlags{48-46} = EVEX_CD8V;
252 let TSFlags{49} = has3DNow0F0FOpcode;
253 let TSFlags{50} = hasMemOp4Prefix;
254 let TSFlags{51} = hasXOP_Prefix;
255 let TSFlags{52} = hasEVEX_RC;
258 class PseudoI<dag oops, dag iops, list<dag> pattern>
259 : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> {
260 let Pattern = pattern;
263 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
264 list<dag> pattern, InstrItinClass itin = NoItinerary,
265 Domain d = GenericDomain>
266 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
267 let Pattern = pattern;
270 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
271 list<dag> pattern, InstrItinClass itin = NoItinerary,
272 Domain d = GenericDomain>
273 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
274 let Pattern = pattern;
277 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
278 list<dag> pattern, InstrItinClass itin = NoItinerary>
279 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
280 let Pattern = pattern;
283 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
284 list<dag> pattern, InstrItinClass itin = NoItinerary>
285 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
286 let Pattern = pattern;
289 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
290 list<dag> pattern, InstrItinClass itin = NoItinerary>
291 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
292 let Pattern = pattern;
296 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
297 list<dag> pattern, InstrItinClass itin = NoItinerary>
298 : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> {
299 let Pattern = pattern;
303 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
304 list<dag> pattern, InstrItinClass itin = NoItinerary>
305 : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> {
306 let Pattern = pattern;
310 // FPStack Instruction Templates:
311 // FPI - Floating Point Instruction template.
312 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm,
313 InstrItinClass itin = NoItinerary>
314 : I<o, F, outs, ins, asm, [], itin> {}
316 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
317 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
318 InstrItinClass itin = NoItinerary>
319 : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> {
321 let Pattern = pattern;
324 // Templates for instructions that use a 16- or 32-bit segmented address as
325 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
327 // Iseg16 - 16-bit segment selector, 16-bit offset
328 // Iseg32 - 16-bit segment selector, 32-bit offset
330 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
331 list<dag> pattern, InstrItinClass itin = NoItinerary>
332 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
333 let Pattern = pattern;
337 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
338 list<dag> pattern, InstrItinClass itin = NoItinerary>
339 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
340 let Pattern = pattern;
348 // SI - SSE 1 & 2 scalar instructions
349 class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
350 list<dag> pattern, InstrItinClass itin = NoItinerary>
351 : I<o, F, outs, ins, asm, pattern, itin> {
352 let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
353 !if(hasVEXPrefix /* VEX */, [UseAVX],
354 !if(!eq(Prefix, __xs.Prefix), [UseSSE1],
355 !if(!eq(Prefix, __xd.Prefix), [UseSSE2],
356 !if(!eq(Prefix, __pd.Prefix), [UseSSE2], [UseSSE1])))));
358 // AVX instructions have a 'v' prefix in the mnemonic
359 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
362 // SIi8 - SSE 1 & 2 scalar instructions
363 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
364 list<dag> pattern, InstrItinClass itin = NoItinerary>
365 : Ii8<o, F, outs, ins, asm, pattern, itin> {
366 let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
367 !if(hasVEXPrefix /* VEX */, [UseAVX],
368 !if(!eq(Prefix, __xs.Prefix), [UseSSE1], [UseSSE2])));
370 // AVX instructions have a 'v' prefix in the mnemonic
371 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
374 // PI - SSE 1 & 2 packed instructions
375 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
376 InstrItinClass itin, Domain d>
377 : I<o, F, outs, ins, asm, pattern, itin, d> {
378 let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
379 !if(hasVEXPrefix /* VEX */, [HasAVX],
380 !if(!eq(Prefix, __pd.Prefix), [UseSSE2], [UseSSE1])));
382 // AVX instructions have a 'v' prefix in the mnemonic
383 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
386 // MMXPI - SSE 1 & 2 packed instructions with MMX operands
387 class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
388 InstrItinClass itin, Domain d>
389 : I<o, F, outs, ins, asm, pattern, itin, d> {
390 let Predicates = !if(!eq(Prefix, __pd.Prefix), [HasSSE2], [HasSSE1]);
393 // PIi8 - SSE 1 & 2 packed instructions with immediate
394 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
395 list<dag> pattern, InstrItinClass itin, Domain d>
396 : Ii8<o, F, outs, ins, asm, pattern, itin, d> {
397 let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
398 !if(hasVEXPrefix /* VEX */, [HasAVX],
399 !if(!eq(Prefix, __pd.Prefix), [UseSSE2], [UseSSE1])));
401 // AVX instructions have a 'v' prefix in the mnemonic
402 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
405 // SSE1 Instruction Templates:
407 // SSI - SSE1 instructions with XS prefix.
408 // PSI - SSE1 instructions with TB prefix.
409 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
410 // VSSI - SSE1 instructions with XS prefix in AVX form.
411 // VPSI - SSE1 instructions with TB prefix in AVX form, packed single.
413 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm,
414 list<dag> pattern, InstrItinClass itin = NoItinerary>
415 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
416 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
417 list<dag> pattern, InstrItinClass itin = NoItinerary>
418 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
419 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
420 list<dag> pattern, InstrItinClass itin = NoItinerary>
421 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
423 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
424 list<dag> pattern, InstrItinClass itin = NoItinerary>
425 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
427 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
428 list<dag> pattern, InstrItinClass itin = NoItinerary>
429 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
431 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
432 list<dag> pattern, InstrItinClass itin = NoItinerary>
433 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, TB,
436 // SSE2 Instruction Templates:
438 // SDI - SSE2 instructions with XD prefix.
439 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
440 // S2SI - SSE2 instructions with XS prefix.
441 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
442 // PDI - SSE2 instructions with PD prefix, packed double domain.
443 // PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix.
444 // VSDI - SSE2 scalar instructions with XD prefix in AVX form.
445 // VPDI - SSE2 vector instructions with PD prefix in AVX form,
446 // packed double domain.
447 // VS2I - SSE2 scalar instructions with PD prefix in AVX form.
448 // S2I - SSE2 scalar instructions with PD prefix.
449 // MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as
451 // MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as
454 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
455 list<dag> pattern, InstrItinClass itin = NoItinerary>
456 : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
457 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
458 list<dag> pattern, InstrItinClass itin = NoItinerary>
459 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
460 class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
461 list<dag> pattern, InstrItinClass itin = NoItinerary>
462 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE2]>;
463 class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
464 list<dag> pattern, InstrItinClass itin = NoItinerary>
465 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>;
466 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
467 list<dag> pattern, InstrItinClass itin = NoItinerary>
468 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
470 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
471 list<dag> pattern, InstrItinClass itin = NoItinerary>
472 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
474 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
475 list<dag> pattern, InstrItinClass itin = NoItinerary>
476 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD,
478 class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
479 list<dag> pattern, InstrItinClass itin = NoItinerary>
480 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
482 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
483 list<dag> pattern, InstrItinClass itin = NoItinerary>
484 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>,
485 PD, Requires<[HasAVX]>;
486 class VS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
487 list<dag> pattern, InstrItinClass itin = NoItinerary>
488 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, PD,
490 class S2I<bits<8> o, Format F, dag outs, dag ins, string asm,
491 list<dag> pattern, InstrItinClass itin = NoItinerary>
492 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[UseSSE2]>;
493 class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
494 list<dag> pattern, InstrItinClass itin = NoItinerary>
495 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
496 class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
497 list<dag> pattern, InstrItinClass itin = NoItinerary>
498 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
500 // SSE3 Instruction Templates:
502 // S3I - SSE3 instructions with PD prefixes.
503 // S3SI - SSE3 instructions with XS prefix.
504 // S3DI - SSE3 instructions with XD prefix.
506 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
507 list<dag> pattern, InstrItinClass itin = NoItinerary>
508 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS,
510 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
511 list<dag> pattern, InstrItinClass itin = NoItinerary>
512 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD,
514 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
515 list<dag> pattern, InstrItinClass itin = NoItinerary>
516 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
520 // SSSE3 Instruction Templates:
522 // SS38I - SSSE3 instructions with T8 prefix.
523 // SS3AI - SSSE3 instructions with TA prefix.
524 // MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands.
525 // MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands.
527 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
528 // uses the MMX registers. The 64-bit versions are grouped with the MMX
529 // classes. They need to be enabled even if AVX is enabled.
531 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
532 list<dag> pattern, InstrItinClass itin = NoItinerary>
533 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
534 Requires<[UseSSSE3]>;
535 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
536 list<dag> pattern, InstrItinClass itin = NoItinerary>
537 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
538 Requires<[UseSSSE3]>;
539 class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
540 list<dag> pattern, InstrItinClass itin = NoItinerary>
541 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
542 Requires<[HasSSSE3]>;
543 class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
544 list<dag> pattern, InstrItinClass itin = NoItinerary>
545 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
546 Requires<[HasSSSE3]>;
548 // SSE4.1 Instruction Templates:
550 // SS48I - SSE 4.1 instructions with T8 prefix.
551 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
553 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
554 list<dag> pattern, InstrItinClass itin = NoItinerary>
555 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
556 Requires<[UseSSE41]>;
557 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
558 list<dag> pattern, InstrItinClass itin = NoItinerary>
559 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
560 Requires<[UseSSE41]>;
562 // SSE4.2 Instruction Templates:
564 // SS428I - SSE 4.2 instructions with T8 prefix.
565 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
566 list<dag> pattern, InstrItinClass itin = NoItinerary>
567 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
568 Requires<[UseSSE42]>;
570 // SS42FI - SSE 4.2 instructions with T8XD prefix.
571 // NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns.
572 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
573 list<dag> pattern, InstrItinClass itin = NoItinerary>
574 : I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>;
576 // SS42AI = SSE 4.2 instructions with TA prefix
577 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
578 list<dag> pattern, InstrItinClass itin = NoItinerary>
579 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
580 Requires<[UseSSE42]>;
582 // AVX Instruction Templates:
583 // Instructions introduced in AVX (no SSE equivalent forms)
585 // AVX8I - AVX instructions with T8PD prefix.
586 // AVXAIi8 - AVX instructions with TAPD prefix and ImmT = Imm8.
587 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
588 list<dag> pattern, InstrItinClass itin = NoItinerary>
589 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
591 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
592 list<dag> pattern, InstrItinClass itin = NoItinerary>
593 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
596 // AVX2 Instruction Templates:
597 // Instructions introduced in AVX2 (no SSE equivalent forms)
599 // AVX28I - AVX2 instructions with T8PD prefix.
600 // AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8.
601 class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
602 list<dag> pattern, InstrItinClass itin = NoItinerary>
603 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
605 class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
606 list<dag> pattern, InstrItinClass itin = NoItinerary>
607 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
611 // AVX-512 Instruction Templates:
612 // Instructions introduced in AVX-512 (no SSE equivalent forms)
614 // AVX5128I - AVX-512 instructions with T8PD prefix.
615 // AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8.
616 // AVX512PDI - AVX-512 instructions with PD, double packed.
617 // AVX512PSI - AVX-512 instructions with TB, single packed.
618 // AVX512XS8I - AVX-512 instructions with T8 and XS prefixes.
619 // AVX512XSI - AVX-512 instructions with XS prefix, generic domain.
620 // AVX512BI - AVX-512 instructions with PD, int packed domain.
621 // AVX512SI - AVX-512 scalar instructions with PD prefix.
623 class AVX5128I<bits<8> o, Format F, dag outs, dag ins, string asm,
624 list<dag> pattern, InstrItinClass itin = NoItinerary>
625 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
626 Requires<[HasAVX512]>;
627 class AVX512XS8I<bits<8> o, Format F, dag outs, dag ins, string asm,
628 list<dag> pattern, InstrItinClass itin = NoItinerary>
629 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8XS,
630 Requires<[HasAVX512]>;
631 class AVX512XSI<bits<8> o, Format F, dag outs, dag ins, string asm,
632 list<dag> pattern, InstrItinClass itin = NoItinerary>
633 : I<o, F, outs, ins, asm, pattern, itin>, XS,
634 Requires<[HasAVX512]>;
635 class AVX512XDI<bits<8> o, Format F, dag outs, dag ins, string asm,
636 list<dag> pattern, InstrItinClass itin = NoItinerary>
637 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, XD,
638 Requires<[HasAVX512]>;
639 class AVX512BI<bits<8> o, Format F, dag outs, dag ins, string asm,
640 list<dag> pattern, InstrItinClass itin = NoItinerary>
641 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
642 Requires<[HasAVX512]>;
643 class AVX512BIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
644 list<dag> pattern, InstrItinClass itin = NoItinerary>
645 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
646 Requires<[HasAVX512]>;
647 class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
648 list<dag> pattern, InstrItinClass itin = NoItinerary>
649 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
650 Requires<[HasAVX512]>;
651 class AVX512Ii8<bits<8> o, Format F, dag outs, dag ins, string asm,
652 list<dag> pattern, InstrItinClass itin = NoItinerary>
653 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB,
654 Requires<[HasAVX512]>;
655 class AVX512PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
656 list<dag> pattern, InstrItinClass itin = NoItinerary>
657 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
658 Requires<[HasAVX512]>;
659 class AVX512PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
660 list<dag> pattern, InstrItinClass itin = NoItinerary>
661 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
662 Requires<[HasAVX512]>;
663 class AVX512PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
664 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
665 : Ii8<o, F, outs, ins, asm, pattern, itin, d>, TB, Requires<[HasAVX512]>;
666 class AVX512PI<bits<8> o, Format F, dag outs, dag ins, string asm,
667 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
668 : I<o, F, outs, ins, asm, pattern, itin, d>, TB, Requires<[HasAVX512]>;
669 class AVX512FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
670 list<dag>pattern, InstrItinClass itin = NoItinerary>
671 : I<o, F, outs, ins, asm, pattern, itin>, T8PD,
672 EVEX_4V, Requires<[HasAVX512]>;
674 // AES Instruction Templates:
677 // These use the same encoding as the SSE4.2 T8 and TA encodings.
678 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
679 list<dag>pattern, InstrItinClass itin = IIC_AES>
680 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
683 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
684 list<dag> pattern, InstrItinClass itin = NoItinerary>
685 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
688 // PCLMUL Instruction Templates
689 class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
690 list<dag>pattern, InstrItinClass itin = NoItinerary>
691 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
692 Requires<[HasPCLMUL]>;
694 class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
695 list<dag>pattern, InstrItinClass itin = NoItinerary>
696 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
697 VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
699 // FMA3 Instruction Templates
700 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
701 list<dag>pattern, InstrItinClass itin = NoItinerary>
702 : I<o, F, outs, ins, asm, pattern, itin>, T8PD,
703 VEX_4V, FMASC, Requires<[HasFMA]>;
705 // FMA4 Instruction Templates
706 class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
707 list<dag>pattern, InstrItinClass itin = NoItinerary>
708 : Ii8<o, F, outs, ins, asm, pattern, itin>, TAPD,
709 VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>;
711 // XOP 2, 3 and 4 Operand Instruction Template
712 class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,
713 list<dag> pattern, InstrItinClass itin = NoItinerary>
714 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
715 XOP, XOP9, Requires<[HasXOP]>;
717 // XOP 2, 3 and 4 Operand Instruction Templates with imm byte
718 class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,
719 list<dag> pattern, InstrItinClass itin = NoItinerary>
720 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
721 XOP, XOP8, Requires<[HasXOP]>;
723 // XOP 5 operand instruction (VEX encoding!)
724 class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
725 list<dag>pattern, InstrItinClass itin = NoItinerary>
726 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
727 VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
729 // X86-64 Instruction templates...
732 class RI<bits<8> o, Format F, dag outs, dag ins, string asm,
733 list<dag> pattern, InstrItinClass itin = NoItinerary>
734 : I<o, F, outs, ins, asm, pattern, itin>, REX_W;
735 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
736 list<dag> pattern, InstrItinClass itin = NoItinerary>
737 : Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W;
738 class RIi16 <bits<8> o, Format F, dag outs, dag ins, string asm,
739 list<dag> pattern, InstrItinClass itin = NoItinerary>
740 : Ii16<o, F, outs, ins, asm, pattern, itin>, REX_W;
741 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
742 list<dag> pattern, InstrItinClass itin = NoItinerary>
743 : Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W;
745 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
746 list<dag> pattern, InstrItinClass itin = NoItinerary>
747 : X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W {
748 let Pattern = pattern;
752 class RIi64_NOREX<bits<8> o, Format f, dag outs, dag ins, string asm,
753 list<dag> pattern, InstrItinClass itin = NoItinerary>
754 : X86Inst<o, f, Imm64, outs, ins, asm, itin> {
755 let Pattern = pattern;
759 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
760 list<dag> pattern, InstrItinClass itin = NoItinerary>
761 : SSI<o, F, outs, ins, asm, pattern, itin>, REX_W;
762 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
763 list<dag> pattern, InstrItinClass itin = NoItinerary>
764 : SDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
765 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
766 list<dag> pattern, InstrItinClass itin = NoItinerary>
767 : PDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
768 class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
769 list<dag> pattern, InstrItinClass itin = NoItinerary>
770 : VPDI<o, F, outs, ins, asm, pattern, itin>, VEX_W;
771 class RS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
772 list<dag> pattern, InstrItinClass itin = NoItinerary>
773 : S2I<o, F, outs, ins, asm, pattern, itin>, REX_W;
774 class VRS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
775 list<dag> pattern, InstrItinClass itin = NoItinerary>
776 : VS2I<o, F, outs, ins, asm, pattern, itin>, VEX_W;
778 // MMX Instruction templates
781 // MMXI - MMX instructions with TB prefix.
782 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
783 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
784 // MMX2I - MMX / SSE2 instructions with PD prefix.
785 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
786 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
787 // MMXID - MMX instructions with XD prefix.
788 // MMXIS - MMX instructions with XS prefix.
789 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
790 list<dag> pattern, InstrItinClass itin = NoItinerary>
791 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
792 class MMXI32<bits<8> o, Format F, dag outs, dag ins, string asm,
793 list<dag> pattern, InstrItinClass itin = NoItinerary>
794 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX,Not64BitMode]>;
795 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
796 list<dag> pattern, InstrItinClass itin = NoItinerary>
797 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX,In64BitMode]>;
798 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
799 list<dag> pattern, InstrItinClass itin = NoItinerary>
800 : I<o, F, outs, ins, asm, pattern, itin>, TB, REX_W, Requires<[HasMMX]>;
801 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
802 list<dag> pattern, InstrItinClass itin = NoItinerary>
803 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[HasMMX]>;
804 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
805 list<dag> pattern, InstrItinClass itin = NoItinerary>
806 : Ii8<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
807 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
808 list<dag> pattern, InstrItinClass itin = NoItinerary>
809 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>;
810 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
811 list<dag> pattern, InstrItinClass itin = NoItinerary>
812 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>;