1 //===- X86InstrFormats.td - X86 Instruction Formats --------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>;
25 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
26 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
27 def MRM6r : Format<22>; def MRM7r : Format<23>;
28 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
29 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
30 def MRM6m : Format<30>; def MRM7m : Format<31>;
31 def MRMInitReg : Format<32>;
32 def MRM_C1 : Format<33>;
33 def MRM_C2 : Format<34>;
34 def MRM_C3 : Format<35>;
35 def MRM_C4 : Format<36>;
36 def MRM_C8 : Format<37>;
37 def MRM_C9 : Format<38>;
38 def MRM_E8 : Format<39>;
39 def MRM_F0 : Format<40>;
40 def MRM_F8 : Format<41>;
41 def MRM_F9 : Format<42>;
42 def RawFrmImm8 : Format<43>;
43 def RawFrmImm16 : Format<44>;
44 def MRM_D0 : Format<45>;
45 def MRM_D1 : Format<46>;
47 // ImmType - This specifies the immediate type used by an instruction. This is
48 // part of the ad-hoc solution used to emit machine instruction encodings by our
49 // machine code emitter.
50 class ImmType<bits<3> val> {
53 def NoImm : ImmType<0>;
54 def Imm8 : ImmType<1>;
55 def Imm8PCRel : ImmType<2>;
56 def Imm16 : ImmType<3>;
57 def Imm16PCRel : ImmType<4>;
58 def Imm32 : ImmType<5>;
59 def Imm32PCRel : ImmType<6>;
60 def Imm64 : ImmType<7>;
62 // FPFormat - This specifies what form this FP instruction has. This is used by
63 // the Floating-Point stackifier pass.
64 class FPFormat<bits<3> val> {
67 def NotFP : FPFormat<0>;
68 def ZeroArgFP : FPFormat<1>;
69 def OneArgFP : FPFormat<2>;
70 def OneArgFPRW : FPFormat<3>;
71 def TwoArgFP : FPFormat<4>;
72 def CompareFP : FPFormat<5>;
73 def CondMovFP : FPFormat<6>;
74 def SpecialFP : FPFormat<7>;
76 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
77 // Keep in sync with tables in X86InstrInfo.cpp.
78 class Domain<bits<2> val> {
81 def GenericDomain : Domain<0>;
82 def SSEPackedSingle : Domain<1>;
83 def SSEPackedDouble : Domain<2>;
84 def SSEPackedInt : Domain<3>;
86 // Prefix byte classes which are used to indicate to the ad-hoc machine code
87 // emitter that various prefix bytes are required.
88 class OpSize { bit hasOpSizePrefix = 1; }
89 class AdSize { bit hasAdSizePrefix = 1; }
90 class REX_W { bit hasREX_WPrefix = 1; }
91 class LOCK { bit hasLockPrefix = 1; }
92 class SegFS { bits<2> SegOvrBits = 1; }
93 class SegGS { bits<2> SegOvrBits = 2; }
94 class TB { bits<5> Prefix = 1; }
95 class REP { bits<5> Prefix = 2; }
96 class D8 { bits<5> Prefix = 3; }
97 class D9 { bits<5> Prefix = 4; }
98 class DA { bits<5> Prefix = 5; }
99 class DB { bits<5> Prefix = 6; }
100 class DC { bits<5> Prefix = 7; }
101 class DD { bits<5> Prefix = 8; }
102 class DE { bits<5> Prefix = 9; }
103 class DF { bits<5> Prefix = 10; }
104 class XD { bits<5> Prefix = 11; }
105 class XS { bits<5> Prefix = 12; }
106 class T8 { bits<5> Prefix = 13; }
107 class TA { bits<5> Prefix = 14; }
108 class A6 { bits<5> Prefix = 15; }
109 class A7 { bits<5> Prefix = 16; }
110 class T8XD { bits<5> Prefix = 17; }
111 class T8XS { bits<5> Prefix = 18; }
112 class TAXD { bits<5> Prefix = 19; }
113 class XOP8 { bits<5> Prefix = 20; }
114 class XOP9 { bits<5> Prefix = 21; }
115 class VEX { bit hasVEXPrefix = 1; }
116 class VEX_W { bit hasVEX_WPrefix = 1; }
117 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
118 class VEX_4VOp3 : VEX { bit hasVEX_4VOp3Prefix = 1; }
119 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
120 class VEX_L { bit hasVEX_L = 1; }
121 class VEX_LIG { bit ignoresVEX_L = 1; }
122 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
123 class MemOp4 { bit hasMemOp4Prefix = 1; }
124 class XOP { bit hasXOP_Prefix = 1; }
125 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
128 Domain d = GenericDomain>
130 let Namespace = "X86";
132 bits<8> Opcode = opcod;
134 bits<6> FormBits = Form.Value;
137 dag OutOperandList = outs;
138 dag InOperandList = ins;
139 string AsmString = AsmStr;
141 // If this is a pseudo instruction, mark it isCodeGenOnly.
142 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
144 let Itinerary = itin;
147 // Attributes specific to X86 instructions...
149 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
150 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
152 bits<5> Prefix = 0; // Which prefix byte does this inst have?
153 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
154 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
155 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
156 bits<2> SegOvrBits = 0; // Segment override prefix.
157 Domain ExeDomain = d;
158 bit hasVEXPrefix = 0; // Does this inst require a VEX prefix?
159 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
160 bit hasVEX_4VPrefix = 0; // Does this inst require the VEX.VVVV field?
161 bit hasVEX_4VOp3Prefix = 0; // Does this inst require the VEX.VVVV field to
162 // encode the third operand?
163 bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register
164 // to be encoded in a immediate field?
165 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
166 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
167 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
168 bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands
169 bit hasXOP_Prefix = 0; // Does this inst require an XOP prefix?
171 // TSFlags layout should be kept in sync with X86InstrInfo.h.
172 let TSFlags{5-0} = FormBits;
173 let TSFlags{6} = hasOpSizePrefix;
174 let TSFlags{7} = hasAdSizePrefix;
175 let TSFlags{12-8} = Prefix;
176 let TSFlags{13} = hasREX_WPrefix;
177 let TSFlags{16-14} = ImmT.Value;
178 let TSFlags{19-17} = FPForm.Value;
179 let TSFlags{20} = hasLockPrefix;
180 let TSFlags{22-21} = SegOvrBits;
181 let TSFlags{24-23} = ExeDomain.Value;
182 let TSFlags{32-25} = Opcode;
183 let TSFlags{33} = hasVEXPrefix;
184 let TSFlags{34} = hasVEX_WPrefix;
185 let TSFlags{35} = hasVEX_4VPrefix;
186 let TSFlags{36} = hasVEX_4VOp3Prefix;
187 let TSFlags{37} = hasVEX_i8ImmReg;
188 let TSFlags{38} = hasVEX_L;
189 let TSFlags{39} = ignoresVEX_L;
190 let TSFlags{40} = has3DNow0F0FOpcode;
191 let TSFlags{41} = hasMemOp4Prefix;
192 let TSFlags{42} = hasXOP_Prefix;
195 class PseudoI<dag oops, dag iops, list<dag> pattern>
196 : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> {
197 let Pattern = pattern;
200 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
201 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT,
202 Domain d = GenericDomain>
203 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
204 let Pattern = pattern;
207 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
208 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT,
209 Domain d = GenericDomain>
210 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
211 let Pattern = pattern;
214 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
215 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
216 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
217 let Pattern = pattern;
220 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
221 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
222 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
223 let Pattern = pattern;
226 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
227 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
228 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
229 let Pattern = pattern;
233 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
234 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
235 : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> {
236 let Pattern = pattern;
240 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
241 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
242 : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> {
243 let Pattern = pattern;
247 // FPStack Instruction Templates:
248 // FPI - Floating Point Instruction template.
249 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
250 : I<o, F, outs, ins, asm, []> {}
252 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
253 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
254 InstrItinClass itin = IIC_DEFAULT>
255 : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> {
257 let Pattern = pattern;
260 // Templates for instructions that use a 16- or 32-bit segmented address as
261 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
263 // Iseg16 - 16-bit segment selector, 16-bit offset
264 // Iseg32 - 16-bit segment selector, 32-bit offset
266 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
267 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
268 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
269 let Pattern = pattern;
273 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
274 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
275 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
276 let Pattern = pattern;
280 // SI - SSE 1 & 2 scalar instructions
281 class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
282 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
283 : I<o, F, outs, ins, asm, pattern, itin> {
284 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
285 !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
287 // AVX instructions have a 'v' prefix in the mnemonic
288 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
291 // SIi8 - SSE 1 & 2 scalar instructions
292 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
293 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
294 : Ii8<o, F, outs, ins, asm, pattern, itin> {
295 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
296 !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
298 // AVX instructions have a 'v' prefix in the mnemonic
299 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
302 // PI - SSE 1 & 2 packed instructions
303 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
304 InstrItinClass itin, Domain d>
305 : I<o, F, outs, ins, asm, pattern, itin, d> {
306 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
307 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
309 // AVX instructions have a 'v' prefix in the mnemonic
310 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
313 // PIi8 - SSE 1 & 2 packed instructions with immediate
314 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
315 list<dag> pattern, InstrItinClass itin, Domain d>
316 : Ii8<o, F, outs, ins, asm, pattern, itin, d> {
317 let Predicates = !if(hasVEX_4VPrefix /* VEX */, [HasAVX],
318 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
320 // AVX instructions have a 'v' prefix in the mnemonic
321 let AsmString = !if(hasVEX_4VPrefix, !strconcat("v", asm), asm);
324 // SSE1 Instruction Templates:
326 // SSI - SSE1 instructions with XS prefix.
327 // PSI - SSE1 instructions with TB prefix.
328 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
329 // VSSI - SSE1 instructions with XS prefix in AVX form.
330 // VPSI - SSE1 instructions with TB prefix in AVX form.
332 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm,
333 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
334 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasSSE1]>;
335 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
336 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
337 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasSSE1]>;
338 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
339 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
340 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
342 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
343 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
344 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
346 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
347 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
348 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
350 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
351 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
352 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, TB,
355 // SSE2 Instruction Templates:
357 // SDI - SSE2 instructions with XD prefix.
358 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
359 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
360 // PDI - SSE2 instructions with TB and OpSize prefixes.
361 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
362 // VSDI - SSE2 instructions with XD prefix in AVX form.
363 // VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form.
365 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
366 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
367 : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
368 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
369 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
370 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
371 class SSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
373 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
374 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
375 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
376 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
378 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
379 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
380 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
382 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
383 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
384 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD,
386 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
387 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
388 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>, TB,
389 OpSize, Requires<[HasAVX]>;
391 // SSE3 Instruction Templates:
393 // S3I - SSE3 instructions with TB and OpSize prefixes.
394 // S3SI - SSE3 instructions with XS prefix.
395 // S3DI - SSE3 instructions with XD prefix.
397 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
398 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
399 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS,
401 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
402 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
403 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD,
405 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
406 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
407 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
411 // SSSE3 Instruction Templates:
413 // SS38I - SSSE3 instructions with T8 prefix.
414 // SS3AI - SSSE3 instructions with TA prefix.
416 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
417 // uses the MMX registers. The 64-bit versions are grouped with the MMX
418 // classes. They need to be enabled even if AVX is enabled.
420 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
421 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
422 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
423 Requires<[HasSSSE3]>;
424 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
425 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
426 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
427 Requires<[HasSSSE3]>;
429 // SSE4.1 Instruction Templates:
431 // SS48I - SSE 4.1 instructions with T8 prefix.
432 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
434 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
435 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
436 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
437 Requires<[HasSSE41]>;
438 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
439 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
440 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
441 Requires<[HasSSE41]>;
443 // SSE4.2 Instruction Templates:
445 // SS428I - SSE 4.2 instructions with T8 prefix.
446 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
447 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
448 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
449 Requires<[HasSSE42]>;
451 // SS42FI - SSE 4.2 instructions with T8XD prefix.
452 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
453 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
454 : I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>;
456 // SS42AI = SSE 4.2 instructions with TA prefix
457 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
458 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
459 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
460 Requires<[HasSSE42]>;
462 // AVX Instruction Templates:
463 // Instructions introduced in AVX (no SSE equivalent forms)
465 // AVX8I - AVX instructions with T8 and OpSize prefix.
466 // AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8.
467 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
468 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
469 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
471 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
472 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
473 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
476 // AVX2 Instruction Templates:
477 // Instructions introduced in AVX2 (no SSE equivalent forms)
479 // AVX28I - AVX2 instructions with T8 and OpSize prefix.
480 // AVX2AIi8 - AVX2 instructions with TA, OpSize prefix and ImmT = Imm8.
481 class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
482 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
483 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
485 class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
486 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
487 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
490 // AES Instruction Templates:
493 // These use the same encoding as the SSE4.2 T8 and TA encodings.
494 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
495 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
496 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
497 Requires<[HasSSE2, HasAES]>;
499 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
500 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
501 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
502 Requires<[HasSSE2, HasAES]>;
504 // CLMUL Instruction Templates
505 class CLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
506 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
507 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
508 OpSize, Requires<[HasSSE2, HasCLMUL]>;
510 class AVXCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
511 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
512 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
513 OpSize, VEX_4V, Requires<[HasAVX, HasCLMUL]>;
515 // FMA3 Instruction Templates
516 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
517 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
518 : I<o, F, outs, ins, asm, pattern, itin>, T8,
519 OpSize, VEX_4V, Requires<[HasFMA3]>;
521 // FMA4 Instruction Templates
522 class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
523 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
524 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
525 OpSize, VEX_4V, VEX_I8IMM, Requires<[HasFMA4]>;
527 // XOP 2, 3 and 4 Operand Instruction Template
528 class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,
529 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
530 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
531 XOP, XOP9, Requires<[HasXOP]>;
533 // XOP 2, 3 and 4 Operand Instruction Templates with imm byte
534 class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,
535 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
536 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
537 XOP, XOP8, Requires<[HasXOP]>;
539 // XOP 5 operand instruction (VEX encoding!)
540 class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
541 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
542 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
543 OpSize, VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
545 // X86-64 Instruction templates...
548 class RI<bits<8> o, Format F, dag outs, dag ins, string asm,
549 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
550 : I<o, F, outs, ins, asm, pattern, itin>, REX_W;
551 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
552 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
553 : Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W;
554 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
555 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
556 : Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W;
558 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
559 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
560 : X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W {
561 let Pattern = pattern;
565 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
566 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
567 : SSI<o, F, outs, ins, asm, pattern, itin>, REX_W;
568 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
569 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
570 : SDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
571 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
572 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
573 : PDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
574 class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
575 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
576 : VPDI<o, F, outs, ins, asm, pattern, itin>, VEX_W;
578 // MMX Instruction templates
581 // MMXI - MMX instructions with TB prefix.
582 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
583 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
584 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
585 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
586 // MMXID - MMX instructions with XD prefix.
587 // MMXIS - MMX instructions with XS prefix.
588 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
589 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
590 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
591 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
592 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
593 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX,In64BitMode]>;
594 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
595 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
596 : I<o, F, outs, ins, asm, pattern, itin>, TB, REX_W, Requires<[HasMMX]>;
597 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
598 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
599 : I<o, F, outs, ins, asm, pattern, itin>, TB, OpSize, Requires<[HasMMX]>;
600 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
601 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
602 : Ii8<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
603 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
604 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
605 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>;
606 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
607 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
608 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>;