1 //===- X86InstrFormats.td - X86 Instruction Formats --------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>;
25 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
26 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
27 def MRM6r : Format<22>; def MRM7r : Format<23>;
28 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
29 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
30 def MRM6m : Format<30>; def MRM7m : Format<31>;
31 def MRMInitReg : Format<32>;
32 def MRM_C1 : Format<33>;
33 def MRM_C2 : Format<34>;
34 def MRM_C3 : Format<35>;
35 def MRM_C4 : Format<36>;
36 def MRM_C8 : Format<37>;
37 def MRM_C9 : Format<38>;
38 def MRM_E8 : Format<39>;
39 def MRM_F0 : Format<40>;
40 def MRM_F8 : Format<41>;
41 def MRM_F9 : Format<42>;
43 // ImmType - This specifies the immediate type used by an instruction. This is
44 // part of the ad-hoc solution used to emit machine instruction encodings by our
45 // machine code emitter.
46 class ImmType<bits<3> val> {
49 def NoImm : ImmType<0>;
50 def Imm8 : ImmType<1>;
51 def Imm8PCRel : ImmType<2>;
52 def Imm16 : ImmType<3>;
53 def Imm32 : ImmType<4>;
54 def Imm32PCRel : ImmType<5>;
55 def Imm64 : ImmType<6>;
57 // FPFormat - This specifies what form this FP instruction has. This is used by
58 // the Floating-Point stackifier pass.
59 class FPFormat<bits<3> val> {
62 def NotFP : FPFormat<0>;
63 def ZeroArgFP : FPFormat<1>;
64 def OneArgFP : FPFormat<2>;
65 def OneArgFPRW : FPFormat<3>;
66 def TwoArgFP : FPFormat<4>;
67 def CompareFP : FPFormat<5>;
68 def CondMovFP : FPFormat<6>;
69 def SpecialFP : FPFormat<7>;
71 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
72 // Keep in sync with tables in X86InstrInfo.cpp.
73 class Domain<bits<2> val> {
76 def GenericDomain : Domain<0>;
77 def SSEPackedSingle : Domain<1>;
78 def SSEPackedDouble : Domain<2>;
79 def SSEPackedInt : Domain<3>;
81 // Prefix byte classes which are used to indicate to the ad-hoc machine code
82 // emitter that various prefix bytes are required.
83 class OpSize { bit hasOpSizePrefix = 1; }
84 class AdSize { bit hasAdSizePrefix = 1; }
85 class REX_W { bit hasREX_WPrefix = 1; }
86 class LOCK { bit hasLockPrefix = 1; }
87 class SegFS { bits<2> SegOvrBits = 1; }
88 class SegGS { bits<2> SegOvrBits = 2; }
89 class TB { bits<4> Prefix = 1; }
90 class REP { bits<4> Prefix = 2; }
91 class D8 { bits<4> Prefix = 3; }
92 class D9 { bits<4> Prefix = 4; }
93 class DA { bits<4> Prefix = 5; }
94 class DB { bits<4> Prefix = 6; }
95 class DC { bits<4> Prefix = 7; }
96 class DD { bits<4> Prefix = 8; }
97 class DE { bits<4> Prefix = 9; }
98 class DF { bits<4> Prefix = 10; }
99 class XD { bits<4> Prefix = 11; }
100 class XS { bits<4> Prefix = 12; }
101 class T8 { bits<4> Prefix = 13; }
102 class TA { bits<4> Prefix = 14; }
103 class TF { bits<4> Prefix = 15; }
104 class VEX { bit hasVEXPrefix = 1; }
105 class VEX_W { bit hasVEX_WPrefix = 1; }
106 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
107 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
109 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
110 string AsmStr, Domain d = GenericDomain>
112 let Namespace = "X86";
114 bits<8> Opcode = opcod;
116 bits<6> FormBits = Form.Value;
119 dag OutOperandList = outs;
120 dag InOperandList = ins;
121 string AsmString = AsmStr;
124 // Attributes specific to X86 instructions...
126 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
127 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
129 bits<4> Prefix = 0; // Which prefix byte does this inst have?
130 bit hasREX_WPrefix = 0; // Does this inst requires the REX.W prefix?
131 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
132 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
133 bits<2> SegOvrBits = 0; // Segment override prefix.
134 Domain ExeDomain = d;
135 bit hasVEXPrefix = 0; // Does this inst requires a VEX prefix?
136 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
137 bit hasVEX_4VPrefix = 0; // Does this inst requires the VEX.VVVV field?
138 bit hasVEX_i8ImmReg = 0; // Does this inst requires the last source register
139 // to be encoded in a immediate field?
141 // TSFlags layout should be kept in sync with X86InstrInfo.h.
142 let TSFlags{5-0} = FormBits;
143 let TSFlags{6} = hasOpSizePrefix;
144 let TSFlags{7} = hasAdSizePrefix;
145 let TSFlags{11-8} = Prefix;
146 let TSFlags{12} = hasREX_WPrefix;
147 let TSFlags{15-13} = ImmT.Value;
148 let TSFlags{18-16} = FPForm.Value;
149 let TSFlags{19} = hasLockPrefix;
150 let TSFlags{21-20} = SegOvrBits;
151 let TSFlags{23-22} = ExeDomain.Value;
152 let TSFlags{31-24} = Opcode;
153 let TSFlags{32} = hasVEXPrefix;
154 let TSFlags{33} = hasVEX_WPrefix;
155 let TSFlags{34} = hasVEX_4VPrefix;
156 let TSFlags{35} = hasVEX_i8ImmReg;
159 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
160 list<dag> pattern, Domain d = GenericDomain>
161 : X86Inst<o, f, NoImm, outs, ins, asm, d> {
162 let Pattern = pattern;
165 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
166 list<dag> pattern, Domain d = GenericDomain>
167 : X86Inst<o, f, Imm8, outs, ins, asm, d> {
168 let Pattern = pattern;
171 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
173 : X86Inst<o, f, Imm8PCRel, outs, ins, asm> {
174 let Pattern = pattern;
177 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
179 : X86Inst<o, f, Imm16, outs, ins, asm> {
180 let Pattern = pattern;
183 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
185 : X86Inst<o, f, Imm32, outs, ins, asm> {
186 let Pattern = pattern;
190 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
192 : X86Inst<o, f, Imm32PCRel, outs, ins, asm> {
193 let Pattern = pattern;
197 // FPStack Instruction Templates:
198 // FPI - Floating Point Instruction template.
199 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
200 : I<o, F, outs, ins, asm, []> {}
202 // FpI_ - Floating Point Psuedo Instruction template. Not Predicated.
203 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>
204 : X86Inst<0, Pseudo, NoImm, outs, ins, ""> {
206 let Pattern = pattern;
209 // Templates for instructions that use a 16- or 32-bit segmented address as
210 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
212 // Iseg16 - 16-bit segment selector, 16-bit offset
213 // Iseg32 - 16-bit segment selector, 32-bit offset
215 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
216 list<dag> pattern> : X86Inst<o, f, NoImm, outs, ins, asm> {
217 let Pattern = pattern;
221 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
222 list<dag> pattern> : X86Inst<o, f, NoImm, outs, ins, asm> {
223 let Pattern = pattern;
227 // SI - SSE 1 & 2 scalar instructions
228 class SI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
229 : I<o, F, outs, ins, asm, pattern> {
230 let Predicates = !if(hasVEXPrefix /* VEX_4V */,
231 !if(!eq(Prefix, 11 /* XD */), [HasAVX, HasSSE2], [HasAVX, HasSSE1]),
232 !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
234 // AVX instructions have a 'v' prefix in the mnemonic
235 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
238 // SIi8 - SSE 1 & 2 scalar instructions
239 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
241 : Ii8<o, F, outs, ins, asm, pattern> {
242 let Predicates = !if(hasVEXPrefix /* VEX_4V */,
243 !if(!eq(Prefix, 11 /* XD */), [HasAVX, HasSSE2], [HasAVX, HasSSE1]),
244 !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
246 // AVX instructions have a 'v' prefix in the mnemonic
247 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
250 // PI - SSE 1 & 2 packed instructions
251 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
253 : I<o, F, outs, ins, asm, pattern, d> {
254 let Predicates = !if(hasVEXPrefix /* VEX_4V */,
255 !if(hasOpSizePrefix /* OpSize */, [HasAVX, HasSSE2], [HasAVX, HasSSE1]),
256 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
258 // AVX instructions have a 'v' prefix in the mnemonic
259 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
262 // PIi8 - SSE 1 & 2 packed instructions with immediate
263 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
264 list<dag> pattern, Domain d>
265 : Ii8<o, F, outs, ins, asm, pattern, d> {
266 let Predicates = !if(hasVEX_4VPrefix /* VEX_4V */,
267 !if(hasOpSizePrefix /* OpSize */, [HasAVX, HasSSE2], [HasAVX, HasSSE1]),
268 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
270 // AVX instructions have a 'v' prefix in the mnemonic
271 let AsmString = !if(hasVEX_4VPrefix, !strconcat("v", asm), asm);
274 // SSE1 Instruction Templates:
276 // SSI - SSE1 instructions with XS prefix.
277 // PSI - SSE1 instructions with TB prefix.
278 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
279 // VSSI - SSE1 instructions with XS prefix in AVX form.
280 // VPSI - SSE1 instructions with TB prefix in AVX form.
282 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
283 : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
284 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
286 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
287 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
288 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
290 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
292 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
294 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
296 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, XS,
297 Requires<[HasAVX, HasSSE1]>;
298 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
300 : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedSingle>,
301 Requires<[HasAVX, HasSSE1]>;
303 // SSE2 Instruction Templates:
305 // SDI - SSE2 instructions with XD prefix.
306 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
307 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
308 // PDI - SSE2 instructions with TB and OpSize prefixes.
309 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
310 // VSDI - SSE2 instructions with XD prefix in AVX form.
311 // VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form.
313 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
314 : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
315 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
317 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
318 class SSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
320 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
321 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
322 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
324 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
326 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
328 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
330 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, XD,
331 Requires<[HasAVX, HasSSE2]>;
332 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
334 : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedDouble>,
335 OpSize, Requires<[HasAVX, HasSSE2]>;
337 // SSE3 Instruction Templates:
339 // S3I - SSE3 instructions with TB and OpSize prefixes.
340 // S3SI - SSE3 instructions with XS prefix.
341 // S3DI - SSE3 instructions with XD prefix.
343 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
345 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, XS,
347 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
349 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, XD,
351 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
352 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
356 // SSSE3 Instruction Templates:
358 // SS38I - SSSE3 instructions with T8 prefix.
359 // SS3AI - SSSE3 instructions with TA prefix.
361 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
362 // uses the MMX registers. We put those instructions here because they better
363 // fit into the SSSE3 instruction category rather than the MMX category.
365 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
367 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
368 Requires<[HasSSSE3]>;
369 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
371 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
372 Requires<[HasSSSE3]>;
374 // SSE4.1 Instruction Templates:
376 // SS48I - SSE 4.1 instructions with T8 prefix.
377 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
379 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
381 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
382 Requires<[HasSSE41]>;
383 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
385 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
386 Requires<[HasSSE41]>;
388 // SSE4.2 Instruction Templates:
390 // SS428I - SSE 4.2 instructions with T8 prefix.
391 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
393 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
394 Requires<[HasSSE42]>;
396 // SS42FI - SSE 4.2 instructions with TF prefix.
397 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
399 : I<o, F, outs, ins, asm, pattern>, TF, Requires<[HasSSE42]>;
401 // SS42AI = SSE 4.2 instructions with TA prefix
402 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
404 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
405 Requires<[HasSSE42]>;
407 // AES Instruction Templates:
410 // These use the same encoding as the SSE4.2 T8 and TA encodings.
411 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
413 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
416 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
418 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
421 // X86-64 Instruction templates...
424 class RI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
425 : I<o, F, outs, ins, asm, pattern>, REX_W;
426 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
428 : Ii8<o, F, outs, ins, asm, pattern>, REX_W;
429 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
431 : Ii32<o, F, outs, ins, asm, pattern>, REX_W;
433 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
435 : X86Inst<o, f, Imm64, outs, ins, asm>, REX_W {
436 let Pattern = pattern;
440 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
442 : SSI<o, F, outs, ins, asm, pattern>, REX_W;
443 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
445 : SDI<o, F, outs, ins, asm, pattern>, REX_W;
446 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
448 : PDI<o, F, outs, ins, asm, pattern>, REX_W;
450 // MMX Instruction templates
453 // MMXI - MMX instructions with TB prefix.
454 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
455 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
456 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
457 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
458 // MMXID - MMX instructions with XD prefix.
459 // MMXIS - MMX instructions with XS prefix.
460 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
462 : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
463 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
465 : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX,In64BitMode]>;
466 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
468 : I<o, F, outs, ins, asm, pattern>, TB, REX_W, Requires<[HasMMX]>;
469 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
471 : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasMMX]>;
472 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
474 : Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
475 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
477 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX]>;
478 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
480 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX]>;