1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<7> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>; def RawFrmMemOffs : Format<7>;
25 def RawFrmSrc : Format<8>; def RawFrmDst : Format<9>;
26 def RawFrmDstSrc: Format<10>;
27 def RawFrmImm8 : Format<11>;
28 def RawFrmImm16 : Format<12>;
29 def MRMXr : Format<14>; def MRMXm : Format<15>;
30 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
31 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
32 def MRM6r : Format<22>; def MRM7r : Format<23>;
33 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
34 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
35 def MRM6m : Format<30>; def MRM7m : Format<31>;
36 def MRM_C0 : Format<32>; def MRM_C1 : Format<33>; def MRM_C2 : Format<34>;
37 def MRM_C3 : Format<35>; def MRM_C4 : Format<36>; def MRM_C8 : Format<37>;
38 def MRM_C9 : Format<38>; def MRM_CA : Format<39>; def MRM_CB : Format<40>;
39 def MRM_D0 : Format<41>; def MRM_D1 : Format<42>; def MRM_D4 : Format<43>;
40 def MRM_D5 : Format<44>; def MRM_D6 : Format<45>; def MRM_D8 : Format<46>;
41 def MRM_D9 : Format<47>; def MRM_DA : Format<48>; def MRM_DB : Format<49>;
42 def MRM_DC : Format<50>; def MRM_DD : Format<51>; def MRM_DE : Format<52>;
43 def MRM_DF : Format<53>; def MRM_E0 : Format<54>; def MRM_E1 : Format<55>;
44 def MRM_E2 : Format<56>; def MRM_E3 : Format<57>; def MRM_E4 : Format<58>;
45 def MRM_E5 : Format<59>; def MRM_E8 : Format<60>; def MRM_E9 : Format<61>;
46 def MRM_EA : Format<62>; def MRM_EB : Format<63>; def MRM_EC : Format<64>;
47 def MRM_ED : Format<65>; def MRM_EE : Format<66>; def MRM_F0 : Format<67>;
48 def MRM_F1 : Format<68>; def MRM_F2 : Format<69>; def MRM_F3 : Format<70>;
49 def MRM_F4 : Format<71>; def MRM_F5 : Format<72>; def MRM_F6 : Format<73>;
50 def MRM_F7 : Format<74>; def MRM_F8 : Format<75>; def MRM_F9 : Format<76>;
51 def MRM_FA : Format<77>; def MRM_FB : Format<78>; def MRM_FC : Format<79>;
52 def MRM_FD : Format<80>; def MRM_FE : Format<81>; def MRM_FF : Format<82>;
54 // ImmType - This specifies the immediate type used by an instruction. This is
55 // part of the ad-hoc solution used to emit machine instruction encodings by our
56 // machine code emitter.
57 class ImmType<bits<4> val> {
60 def NoImm : ImmType<0>;
61 def Imm8 : ImmType<1>;
62 def Imm8PCRel : ImmType<2>;
63 def Imm16 : ImmType<3>;
64 def Imm16PCRel : ImmType<4>;
65 def Imm32 : ImmType<5>;
66 def Imm32PCRel : ImmType<6>;
67 def Imm32S : ImmType<7>;
68 def Imm64 : ImmType<8>;
70 // FPFormat - This specifies what form this FP instruction has. This is used by
71 // the Floating-Point stackifier pass.
72 class FPFormat<bits<3> val> {
75 def NotFP : FPFormat<0>;
76 def ZeroArgFP : FPFormat<1>;
77 def OneArgFP : FPFormat<2>;
78 def OneArgFPRW : FPFormat<3>;
79 def TwoArgFP : FPFormat<4>;
80 def CompareFP : FPFormat<5>;
81 def CondMovFP : FPFormat<6>;
82 def SpecialFP : FPFormat<7>;
84 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
85 // Keep in sync with tables in X86InstrInfo.cpp.
86 class Domain<bits<2> val> {
89 def GenericDomain : Domain<0>;
90 def SSEPackedSingle : Domain<1>;
91 def SSEPackedDouble : Domain<2>;
92 def SSEPackedInt : Domain<3>;
94 // Class specifying the vector form of the decompressed
95 // displacement of 8-bit.
96 class CD8VForm<bits<3> val> {
99 def CD8VF : CD8VForm<0>; // v := VL
100 def CD8VH : CD8VForm<1>; // v := VL/2
101 def CD8VQ : CD8VForm<2>; // v := VL/4
102 def CD8VO : CD8VForm<3>; // v := VL/8
103 def CD8VT1 : CD8VForm<4>; // v := 1
104 def CD8VT2 : CD8VForm<5>; // v := 2
105 def CD8VT4 : CD8VForm<6>; // v := 4
106 def CD8VT8 : CD8VForm<7>; // v := 8
108 // Class specifying the prefix used an opcode extension.
109 class Prefix<bits<3> val> {
112 def NoPrfx : Prefix<0>;
118 // Class specifying the opcode map.
119 class Map<bits<3> val> {
130 // Class specifying the encoding
131 class Encoding<bits<2> val> {
134 def EncNormal : Encoding<0>;
135 def EncVEX : Encoding<1>;
136 def EncXOP : Encoding<2>;
137 def EncEVEX : Encoding<3>;
139 // Operand size for encodings that change based on mode.
140 class OperandSize<bits<2> val> {
143 def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix.
144 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
145 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
147 // Prefix byte classes which are used to indicate to the ad-hoc machine code
148 // emitter that various prefix bytes are required.
149 class OpSize16 { OperandSize OpSize = OpSize16; }
150 class OpSize32 { OperandSize OpSize = OpSize32; }
151 class AdSize { bit hasAdSizePrefix = 1; }
152 class REX_W { bit hasREX_WPrefix = 1; }
153 class LOCK { bit hasLockPrefix = 1; }
154 class REP { bit hasREPPrefix = 1; }
155 class TB { Map OpMap = TB; }
156 class T8 { Map OpMap = T8; }
157 class TA { Map OpMap = TA; }
158 class XOP8 { Map OpMap = XOP8; Prefix OpPrefix = PS; }
159 class XOP9 { Map OpMap = XOP9; Prefix OpPrefix = PS; }
160 class XOPA { Map OpMap = XOPA; Prefix OpPrefix = PS; }
161 class OBXS { Prefix OpPrefix = XS; }
162 class PS : TB { Prefix OpPrefix = PS; }
163 class PD : TB { Prefix OpPrefix = PD; }
164 class XD : TB { Prefix OpPrefix = XD; }
165 class XS : TB { Prefix OpPrefix = XS; }
166 class T8PS : T8 { Prefix OpPrefix = PS; }
167 class T8PD : T8 { Prefix OpPrefix = PD; }
168 class T8XD : T8 { Prefix OpPrefix = XD; }
169 class T8XS : T8 { Prefix OpPrefix = XS; }
170 class TAPS : TA { Prefix OpPrefix = PS; }
171 class TAPD : TA { Prefix OpPrefix = PD; }
172 class TAXD : TA { Prefix OpPrefix = XD; }
173 class VEX { Encoding OpEnc = EncVEX; }
174 class VEX_W { bit hasVEX_WPrefix = 1; }
175 class VEX_4V : VEX { bit hasVEX_4V = 1; }
176 class VEX_4VOp3 : VEX { bit hasVEX_4VOp3 = 1; }
177 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
178 class VEX_L { bit hasVEX_L = 1; }
179 class VEX_LIG { bit ignoresVEX_L = 1; }
180 class EVEX : VEX { Encoding OpEnc = EncEVEX; }
181 class EVEX_4V : VEX_4V { Encoding OpEnc = EncEVEX; }
182 class EVEX_K { bit hasEVEX_K = 1; }
183 class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; }
184 class EVEX_B { bit hasEVEX_B = 1; }
185 class EVEX_RC { bit hasEVEX_RC = 1; }
186 class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; }
187 class EVEX_CD8<int esize, CD8VForm form> {
188 bits<2> EVEX_CD8E = !if(!eq(esize, 8), 0b00,
189 !if(!eq(esize, 16), 0b01,
190 !if(!eq(esize, 32), 0b10,
191 !if(!eq(esize, 64), 0b11, ?))));
192 bits<3> EVEX_CD8V = form.Value;
194 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
195 class MemOp4 { bit hasMemOp4Prefix = 1; }
196 class XOP { Encoding OpEnc = EncXOP; }
197 class XOP_4V : XOP { bit hasVEX_4V = 1; }
198 class XOP_4VOp3 : XOP { bit hasVEX_4VOp3 = 1; }
200 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
203 Domain d = GenericDomain>
205 let Namespace = "X86";
207 bits<8> Opcode = opcod;
209 bits<7> FormBits = Form.Value;
212 dag OutOperandList = outs;
213 dag InOperandList = ins;
214 string AsmString = AsmStr;
216 // If this is a pseudo instruction, mark it isCodeGenOnly.
217 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
219 let Itinerary = itin;
222 // Attributes specific to X86 instructions...
224 bit ForceDisassemble = 0; // Force instruction to disassemble even though it's
225 // isCodeGenonly. Needed to hide an ambiguous
226 // AsmString from the parser, but still disassemble.
228 OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change
229 // based on operand size of the mode
230 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
232 Prefix OpPrefix = NoPrfx; // Which prefix byte does this inst have?
233 Map OpMap = OB; // Which opcode map does this inst have?
234 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
235 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
236 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
237 Domain ExeDomain = d;
238 bit hasREPPrefix = 0; // Does this inst have a REP prefix?
239 Encoding OpEnc = EncNormal; // Encoding used by this instruction
240 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
241 bit hasVEX_4V = 0; // Does this inst require the VEX.VVVV field?
242 bit hasVEX_4VOp3 = 0; // Does this inst require the VEX.VVVV field to
243 // encode the third operand?
244 bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register
245 // to be encoded in a immediate field?
246 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
247 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
248 bit hasEVEX_K = 0; // Does this inst require masking?
249 bit hasEVEX_Z = 0; // Does this inst set the EVEX_Z field?
250 bit hasEVEX_L2 = 0; // Does this inst set the EVEX_L2 field?
251 bit hasEVEX_B = 0; // Does this inst set the EVEX_B field?
252 bits<2> EVEX_CD8E = 0; // Compressed disp8 form - element-size.
253 bits<3> EVEX_CD8V = 0; // Compressed disp8 form - vector-width.
254 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
255 bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands
256 bit hasEVEX_RC = 0; // Explicitly specified rounding control in FP instruction.
258 // TSFlags layout should be kept in sync with X86InstrInfo.h.
259 let TSFlags{6-0} = FormBits;
260 let TSFlags{8-7} = OpSize.Value;
261 let TSFlags{9} = hasAdSizePrefix;
262 let TSFlags{12-10} = OpPrefix.Value;
263 let TSFlags{15-13} = OpMap.Value;
264 let TSFlags{16} = hasREX_WPrefix;
265 let TSFlags{20-17} = ImmT.Value;
266 let TSFlags{23-21} = FPForm.Value;
267 let TSFlags{24} = hasLockPrefix;
268 let TSFlags{25} = hasREPPrefix;
269 let TSFlags{27-26} = ExeDomain.Value;
270 let TSFlags{29-28} = OpEnc.Value;
271 let TSFlags{37-30} = Opcode;
272 let TSFlags{38} = hasVEX_WPrefix;
273 let TSFlags{39} = hasVEX_4V;
274 let TSFlags{40} = hasVEX_4VOp3;
275 let TSFlags{41} = hasVEX_i8ImmReg;
276 let TSFlags{42} = hasVEX_L;
277 let TSFlags{43} = ignoresVEX_L;
278 let TSFlags{44} = hasEVEX_K;
279 let TSFlags{45} = hasEVEX_Z;
280 let TSFlags{46} = hasEVEX_L2;
281 let TSFlags{47} = hasEVEX_B;
282 let TSFlags{49-48} = EVEX_CD8E;
283 let TSFlags{52-50} = EVEX_CD8V;
284 let TSFlags{53} = has3DNow0F0FOpcode;
285 let TSFlags{54} = hasMemOp4Prefix;
286 let TSFlags{55} = hasEVEX_RC;
289 class PseudoI<dag oops, dag iops, list<dag> pattern>
290 : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> {
291 let Pattern = pattern;
294 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
295 list<dag> pattern, InstrItinClass itin = NoItinerary,
296 Domain d = GenericDomain>
297 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
298 let Pattern = pattern;
301 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
302 list<dag> pattern, InstrItinClass itin = NoItinerary,
303 Domain d = GenericDomain>
304 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
305 let Pattern = pattern;
308 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
309 list<dag> pattern, InstrItinClass itin = NoItinerary>
310 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
311 let Pattern = pattern;
314 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
315 list<dag> pattern, InstrItinClass itin = NoItinerary>
316 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
317 let Pattern = pattern;
320 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
321 list<dag> pattern, InstrItinClass itin = NoItinerary>
322 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
323 let Pattern = pattern;
326 class Ii32S<bits<8> o, Format f, dag outs, dag ins, string asm,
327 list<dag> pattern, InstrItinClass itin = NoItinerary>
328 : X86Inst<o, f, Imm32S, outs, ins, asm, itin> {
329 let Pattern = pattern;
333 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
334 list<dag> pattern, InstrItinClass itin = NoItinerary>
335 : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> {
336 let Pattern = pattern;
340 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
341 list<dag> pattern, InstrItinClass itin = NoItinerary>
342 : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> {
343 let Pattern = pattern;
347 // FPStack Instruction Templates:
348 // FPI - Floating Point Instruction template.
349 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm,
350 InstrItinClass itin = NoItinerary>
351 : I<o, F, outs, ins, asm, [], itin> {}
353 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
354 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
355 InstrItinClass itin = NoItinerary>
356 : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> {
358 let Pattern = pattern;
361 // Templates for instructions that use a 16- or 32-bit segmented address as
362 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
364 // Iseg16 - 16-bit segment selector, 16-bit offset
365 // Iseg32 - 16-bit segment selector, 32-bit offset
367 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
368 list<dag> pattern, InstrItinClass itin = NoItinerary>
369 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
370 let Pattern = pattern;
374 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
375 list<dag> pattern, InstrItinClass itin = NoItinerary>
376 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
377 let Pattern = pattern;
381 // SI - SSE 1 & 2 scalar instructions
382 class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
383 list<dag> pattern, InstrItinClass itin = NoItinerary>
384 : I<o, F, outs, ins, asm, pattern, itin> {
385 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
386 !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX],
387 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1],
388 !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2],
389 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],
392 // AVX instructions have a 'v' prefix in the mnemonic
393 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
394 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
398 // SIi8 - SSE 1 & 2 scalar instructions
399 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
400 list<dag> pattern, InstrItinClass itin = NoItinerary>
401 : Ii8<o, F, outs, ins, asm, pattern, itin> {
402 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
403 !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX],
404 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1],
407 // AVX instructions have a 'v' prefix in the mnemonic
408 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
409 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
413 // PI - SSE 1 & 2 packed instructions
414 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
415 InstrItinClass itin, Domain d>
416 : I<o, F, outs, ins, asm, pattern, itin, d> {
417 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
418 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX],
419 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],
422 // AVX instructions have a 'v' prefix in the mnemonic
423 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
424 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
428 // MMXPI - SSE 1 & 2 packed instructions with MMX operands
429 class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
430 InstrItinClass itin, Domain d>
431 : I<o, F, outs, ins, asm, pattern, itin, d> {
432 let Predicates = !if(!eq(OpPrefix.Value, PD.Value), [HasSSE2],
436 // PIi8 - SSE 1 & 2 packed instructions with immediate
437 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
438 list<dag> pattern, InstrItinClass itin, Domain d>
439 : Ii8<o, F, outs, ins, asm, pattern, itin, d> {
440 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
441 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX],
442 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],
445 // AVX instructions have a 'v' prefix in the mnemonic
446 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm),
447 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm),
451 // SSE1 Instruction Templates:
453 // SSI - SSE1 instructions with XS prefix.
454 // PSI - SSE1 instructions with PS prefix.
455 // PSIi8 - SSE1 instructions with ImmT == Imm8 and PS prefix.
456 // VSSI - SSE1 instructions with XS prefix in AVX form.
457 // VPSI - SSE1 instructions with PS prefix in AVX form, packed single.
459 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm,
460 list<dag> pattern, InstrItinClass itin = NoItinerary>
461 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
462 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
463 list<dag> pattern, InstrItinClass itin = NoItinerary>
464 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
465 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
466 list<dag> pattern, InstrItinClass itin = NoItinerary>
467 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS,
469 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
470 list<dag> pattern, InstrItinClass itin = NoItinerary>
471 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS,
473 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
474 list<dag> pattern, InstrItinClass itin = NoItinerary>
475 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
477 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
478 list<dag> pattern, InstrItinClass itin = NoItinerary>
479 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, PS,
482 // SSE2 Instruction Templates:
484 // SDI - SSE2 instructions with XD prefix.
485 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
486 // S2SI - SSE2 instructions with XS prefix.
487 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
488 // PDI - SSE2 instructions with PD prefix, packed double domain.
489 // PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix.
490 // VSDI - SSE2 scalar instructions with XD prefix in AVX form.
491 // VPDI - SSE2 vector instructions with PD prefix in AVX form,
492 // packed double domain.
493 // VS2I - SSE2 scalar instructions with PD prefix in AVX form.
494 // S2I - SSE2 scalar instructions with PD prefix.
495 // MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as
497 // MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as
500 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
501 list<dag> pattern, InstrItinClass itin = NoItinerary>
502 : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
503 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
504 list<dag> pattern, InstrItinClass itin = NoItinerary>
505 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
506 class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
507 list<dag> pattern, InstrItinClass itin = NoItinerary>
508 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE2]>;
509 class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
510 list<dag> pattern, InstrItinClass itin = NoItinerary>
511 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>;
512 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
513 list<dag> pattern, InstrItinClass itin = NoItinerary>
514 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
516 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
517 list<dag> pattern, InstrItinClass itin = NoItinerary>
518 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
520 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
521 list<dag> pattern, InstrItinClass itin = NoItinerary>
522 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD,
524 class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
525 list<dag> pattern, InstrItinClass itin = NoItinerary>
526 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
528 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
529 list<dag> pattern, InstrItinClass itin = NoItinerary>
530 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>,
531 PD, Requires<[HasAVX]>;
532 class VS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
533 list<dag> pattern, InstrItinClass itin = NoItinerary>
534 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, PD,
536 class S2I<bits<8> o, Format F, dag outs, dag ins, string asm,
537 list<dag> pattern, InstrItinClass itin = NoItinerary>
538 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[UseSSE2]>;
539 class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
540 list<dag> pattern, InstrItinClass itin = NoItinerary>
541 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
542 class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
543 list<dag> pattern, InstrItinClass itin = NoItinerary>
544 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
546 // SSE3 Instruction Templates:
548 // S3I - SSE3 instructions with PD prefixes.
549 // S3SI - SSE3 instructions with XS prefix.
550 // S3DI - SSE3 instructions with XD prefix.
552 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
553 list<dag> pattern, InstrItinClass itin = NoItinerary>
554 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS,
556 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
557 list<dag> pattern, InstrItinClass itin = NoItinerary>
558 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD,
560 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
561 list<dag> pattern, InstrItinClass itin = NoItinerary>
562 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
566 // SSSE3 Instruction Templates:
568 // SS38I - SSSE3 instructions with T8 prefix.
569 // SS3AI - SSSE3 instructions with TA prefix.
570 // MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands.
571 // MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands.
573 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
574 // uses the MMX registers. The 64-bit versions are grouped with the MMX
575 // classes. They need to be enabled even if AVX is enabled.
577 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
578 list<dag> pattern, InstrItinClass itin = NoItinerary>
579 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
580 Requires<[UseSSSE3]>;
581 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
582 list<dag> pattern, InstrItinClass itin = NoItinerary>
583 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
584 Requires<[UseSSSE3]>;
585 class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
586 list<dag> pattern, InstrItinClass itin = NoItinerary>
587 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PS,
588 Requires<[HasSSSE3]>;
589 class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
590 list<dag> pattern, InstrItinClass itin = NoItinerary>
591 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPS,
592 Requires<[HasSSSE3]>;
594 // SSE4.1 Instruction Templates:
596 // SS48I - SSE 4.1 instructions with T8 prefix.
597 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
599 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
600 list<dag> pattern, InstrItinClass itin = NoItinerary>
601 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
602 Requires<[UseSSE41]>;
603 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
604 list<dag> pattern, InstrItinClass itin = NoItinerary>
605 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
606 Requires<[UseSSE41]>;
608 // SSE4.2 Instruction Templates:
610 // SS428I - SSE 4.2 instructions with T8 prefix.
611 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
612 list<dag> pattern, InstrItinClass itin = NoItinerary>
613 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
614 Requires<[UseSSE42]>;
616 // SS42FI - SSE 4.2 instructions with T8XD prefix.
617 // NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns.
618 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
619 list<dag> pattern, InstrItinClass itin = NoItinerary>
620 : I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>;
622 // SS42AI = SSE 4.2 instructions with TA prefix
623 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
624 list<dag> pattern, InstrItinClass itin = NoItinerary>
625 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
626 Requires<[UseSSE42]>;
628 // AVX Instruction Templates:
629 // Instructions introduced in AVX (no SSE equivalent forms)
631 // AVX8I - AVX instructions with T8PD prefix.
632 // AVXAIi8 - AVX instructions with TAPD prefix and ImmT = Imm8.
633 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
634 list<dag> pattern, InstrItinClass itin = NoItinerary>
635 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
637 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
638 list<dag> pattern, InstrItinClass itin = NoItinerary>
639 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
642 // AVX2 Instruction Templates:
643 // Instructions introduced in AVX2 (no SSE equivalent forms)
645 // AVX28I - AVX2 instructions with T8PD prefix.
646 // AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8.
647 class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
648 list<dag> pattern, InstrItinClass itin = NoItinerary>
649 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
651 class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
652 list<dag> pattern, InstrItinClass itin = NoItinerary>
653 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
657 // AVX-512 Instruction Templates:
658 // Instructions introduced in AVX-512 (no SSE equivalent forms)
660 // AVX5128I - AVX-512 instructions with T8PD prefix.
661 // AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8.
662 // AVX512PDI - AVX-512 instructions with PD, double packed.
663 // AVX512PSI - AVX-512 instructions with PS, single packed.
664 // AVX512XS8I - AVX-512 instructions with T8 and XS prefixes.
665 // AVX512XSI - AVX-512 instructions with XS prefix, generic domain.
666 // AVX512BI - AVX-512 instructions with PD, int packed domain.
667 // AVX512SI - AVX-512 scalar instructions with PD prefix.
669 class AVX5128I<bits<8> o, Format F, dag outs, dag ins, string asm,
670 list<dag> pattern, InstrItinClass itin = NoItinerary>
671 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
672 Requires<[HasAVX512]>;
673 class AVX512XS8I<bits<8> o, Format F, dag outs, dag ins, string asm,
674 list<dag> pattern, InstrItinClass itin = NoItinerary>
675 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8XS,
676 Requires<[HasAVX512]>;
677 class AVX512XSI<bits<8> o, Format F, dag outs, dag ins, string asm,
678 list<dag> pattern, InstrItinClass itin = NoItinerary>
679 : I<o, F, outs, ins, asm, pattern, itin>, XS,
680 Requires<[HasAVX512]>;
681 class AVX512XDI<bits<8> o, Format F, dag outs, dag ins, string asm,
682 list<dag> pattern, InstrItinClass itin = NoItinerary>
683 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, XD,
684 Requires<[HasAVX512]>;
685 class AVX512BI<bits<8> o, Format F, dag outs, dag ins, string asm,
686 list<dag> pattern, InstrItinClass itin = NoItinerary>
687 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
688 Requires<[HasAVX512]>;
689 class AVX512BIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
690 list<dag> pattern, InstrItinClass itin = NoItinerary>
691 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
692 Requires<[HasAVX512]>;
693 class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
694 list<dag> pattern, InstrItinClass itin = NoItinerary>
695 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
696 Requires<[HasAVX512]>;
697 class AVX512Ii8<bits<8> o, Format F, dag outs, dag ins, string asm,
698 list<dag> pattern, InstrItinClass itin = NoItinerary>
699 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>,
700 Requires<[HasAVX512]>;
701 class AVX512PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
702 list<dag> pattern, InstrItinClass itin = NoItinerary>
703 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
704 Requires<[HasAVX512]>;
705 class AVX512PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
706 list<dag> pattern, InstrItinClass itin = NoItinerary>
707 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, PS,
708 Requires<[HasAVX512]>;
709 class AVX512PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
710 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
711 : Ii8<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>;
712 class AVX512PI<bits<8> o, Format F, dag outs, dag ins, string asm,
713 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
714 : I<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>;
715 class AVX512FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
716 list<dag>pattern, InstrItinClass itin = NoItinerary>
717 : I<o, F, outs, ins, asm, pattern, itin>, T8PD,
718 EVEX_4V, Requires<[HasAVX512]>;
720 // AES Instruction Templates:
723 // These use the same encoding as the SSE4.2 T8 and TA encodings.
724 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
725 list<dag>pattern, InstrItinClass itin = IIC_AES>
726 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
729 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
730 list<dag> pattern, InstrItinClass itin = NoItinerary>
731 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
734 // PCLMUL Instruction Templates
735 class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
736 list<dag>pattern, InstrItinClass itin = NoItinerary>
737 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
738 Requires<[HasPCLMUL]>;
740 class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
741 list<dag>pattern, InstrItinClass itin = NoItinerary>
742 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
743 VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
745 // FMA3 Instruction Templates
746 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
747 list<dag>pattern, InstrItinClass itin = NoItinerary>
748 : I<o, F, outs, ins, asm, pattern, itin>, T8PD,
749 VEX_4V, FMASC, Requires<[HasFMA]>;
751 // FMA4 Instruction Templates
752 class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
753 list<dag>pattern, InstrItinClass itin = NoItinerary>
754 : Ii8<o, F, outs, ins, asm, pattern, itin>, TAPD,
755 VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>;
757 // XOP 2, 3 and 4 Operand Instruction Template
758 class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,
759 list<dag> pattern, InstrItinClass itin = NoItinerary>
760 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
761 XOP9, Requires<[HasXOP]>;
763 // XOP 2, 3 and 4 Operand Instruction Templates with imm byte
764 class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,
765 list<dag> pattern, InstrItinClass itin = NoItinerary>
766 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
767 XOP8, Requires<[HasXOP]>;
769 // XOP 5 operand instruction (VEX encoding!)
770 class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
771 list<dag>pattern, InstrItinClass itin = NoItinerary>
772 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
773 VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
775 // X86-64 Instruction templates...
778 class RI<bits<8> o, Format F, dag outs, dag ins, string asm,
779 list<dag> pattern, InstrItinClass itin = NoItinerary>
780 : I<o, F, outs, ins, asm, pattern, itin>, REX_W;
781 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
782 list<dag> pattern, InstrItinClass itin = NoItinerary>
783 : Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W;
784 class RIi16 <bits<8> o, Format F, dag outs, dag ins, string asm,
785 list<dag> pattern, InstrItinClass itin = NoItinerary>
786 : Ii16<o, F, outs, ins, asm, pattern, itin>, REX_W;
787 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
788 list<dag> pattern, InstrItinClass itin = NoItinerary>
789 : Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W;
790 class RIi32S <bits<8> o, Format F, dag outs, dag ins, string asm,
791 list<dag> pattern, InstrItinClass itin = NoItinerary>
792 : Ii32S<o, F, outs, ins, asm, pattern, itin>, REX_W;
794 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
795 list<dag> pattern, InstrItinClass itin = NoItinerary>
796 : X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W {
797 let Pattern = pattern;
801 class RIi64_NOREX<bits<8> o, Format f, dag outs, dag ins, string asm,
802 list<dag> pattern, InstrItinClass itin = NoItinerary>
803 : X86Inst<o, f, Imm64, outs, ins, asm, itin> {
804 let Pattern = pattern;
808 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
809 list<dag> pattern, InstrItinClass itin = NoItinerary>
810 : SSI<o, F, outs, ins, asm, pattern, itin>, REX_W;
811 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
812 list<dag> pattern, InstrItinClass itin = NoItinerary>
813 : SDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
814 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
815 list<dag> pattern, InstrItinClass itin = NoItinerary>
816 : PDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
817 class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
818 list<dag> pattern, InstrItinClass itin = NoItinerary>
819 : VPDI<o, F, outs, ins, asm, pattern, itin>, VEX_W;
820 class RS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
821 list<dag> pattern, InstrItinClass itin = NoItinerary>
822 : S2I<o, F, outs, ins, asm, pattern, itin>, REX_W;
823 class VRS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
824 list<dag> pattern, InstrItinClass itin = NoItinerary>
825 : VS2I<o, F, outs, ins, asm, pattern, itin>, VEX_W;
827 // MMX Instruction templates
830 // MMXI - MMX instructions with TB prefix.
831 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
832 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
833 // MMX2I - MMX / SSE2 instructions with PD prefix.
834 // MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix.
835 // MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix.
836 // MMXID - MMX instructions with XD prefix.
837 // MMXIS - MMX instructions with XS prefix.
838 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
839 list<dag> pattern, InstrItinClass itin = NoItinerary>
840 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX]>;
841 class MMXI32<bits<8> o, Format F, dag outs, dag ins, string asm,
842 list<dag> pattern, InstrItinClass itin = NoItinerary>
843 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX,Not64BitMode]>;
844 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
845 list<dag> pattern, InstrItinClass itin = NoItinerary>
846 : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX,In64BitMode]>;
847 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
848 list<dag> pattern, InstrItinClass itin = NoItinerary>
849 : I<o, F, outs, ins, asm, pattern, itin>, PS, REX_W, Requires<[HasMMX]>;
850 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
851 list<dag> pattern, InstrItinClass itin = NoItinerary>
852 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[HasMMX]>;
853 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
854 list<dag> pattern, InstrItinClass itin = NoItinerary>
855 : Ii8<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX]>;
856 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
857 list<dag> pattern, InstrItinClass itin = NoItinerary>
858 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>;
859 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
860 list<dag> pattern, InstrItinClass itin = NoItinerary>
861 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>;