1 //===- X86InstrFormats.td - X86 Instruction Formats --------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>;
25 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
26 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
27 def MRM6r : Format<22>; def MRM7r : Format<23>;
28 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
29 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
30 def MRM6m : Format<30>; def MRM7m : Format<31>;
31 def MRMInitReg : Format<32>;
32 def MRM_C1 : Format<33>;
33 def MRM_C2 : Format<34>;
34 def MRM_C3 : Format<35>;
35 def MRM_C4 : Format<36>;
36 def MRM_C8 : Format<37>;
37 def MRM_C9 : Format<38>;
38 def MRM_E8 : Format<39>;
39 def MRM_F0 : Format<40>;
40 def MRM_F8 : Format<41>;
41 def MRM_F9 : Format<42>;
43 // ImmType - This specifies the immediate type used by an instruction. This is
44 // part of the ad-hoc solution used to emit machine instruction encodings by our
45 // machine code emitter.
46 class ImmType<bits<3> val> {
49 def NoImm : ImmType<0>;
50 def Imm8 : ImmType<1>;
51 def Imm8PCRel : ImmType<2>;
52 def Imm16 : ImmType<3>;
53 def Imm32 : ImmType<4>;
54 def Imm32PCRel : ImmType<5>;
55 def Imm64 : ImmType<6>;
57 // FPFormat - This specifies what form this FP instruction has. This is used by
58 // the Floating-Point stackifier pass.
59 class FPFormat<bits<3> val> {
62 def NotFP : FPFormat<0>;
63 def ZeroArgFP : FPFormat<1>;
64 def OneArgFP : FPFormat<2>;
65 def OneArgFPRW : FPFormat<3>;
66 def TwoArgFP : FPFormat<4>;
67 def CompareFP : FPFormat<5>;
68 def CondMovFP : FPFormat<6>;
69 def SpecialFP : FPFormat<7>;
71 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
72 // Keep in sync with tables in X86InstrInfo.cpp.
73 class Domain<bits<2> val> {
76 def GenericDomain : Domain<0>;
77 def SSEPackedSingle : Domain<1>;
78 def SSEPackedDouble : Domain<2>;
79 def SSEPackedInt : Domain<3>;
81 // Prefix byte classes which are used to indicate to the ad-hoc machine code
82 // emitter that various prefix bytes are required.
83 class OpSize { bit hasOpSizePrefix = 1; }
84 class AdSize { bit hasAdSizePrefix = 1; }
85 class REX_W { bit hasREX_WPrefix = 1; }
86 class LOCK { bit hasLockPrefix = 1; }
87 class SegFS { bits<2> SegOvrBits = 1; }
88 class SegGS { bits<2> SegOvrBits = 2; }
89 class TB { bits<4> Prefix = 1; }
90 class REP { bits<4> Prefix = 2; }
91 class D8 { bits<4> Prefix = 3; }
92 class D9 { bits<4> Prefix = 4; }
93 class DA { bits<4> Prefix = 5; }
94 class DB { bits<4> Prefix = 6; }
95 class DC { bits<4> Prefix = 7; }
96 class DD { bits<4> Prefix = 8; }
97 class DE { bits<4> Prefix = 9; }
98 class DF { bits<4> Prefix = 10; }
99 class XD { bits<4> Prefix = 11; }
100 class XS { bits<4> Prefix = 12; }
101 class T8 { bits<4> Prefix = 13; }
102 class TA { bits<4> Prefix = 14; }
103 class TF { bits<4> Prefix = 15; }
104 class VEX { bit hasVEXPrefix = 1; }
105 class VEX_W { bit hasVEX_WPrefix = 1; }
106 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
108 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
109 string AsmStr, Domain d = GenericDomain>
111 let Namespace = "X86";
113 bits<8> Opcode = opcod;
115 bits<6> FormBits = Form.Value;
118 dag OutOperandList = outs;
119 dag InOperandList = ins;
120 string AsmString = AsmStr;
123 // Attributes specific to X86 instructions...
125 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
126 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
128 bits<4> Prefix = 0; // Which prefix byte does this inst have?
129 bit hasREX_WPrefix = 0; // Does this inst requires the REX.W prefix?
130 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
131 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
132 bits<2> SegOvrBits = 0; // Segment override prefix.
133 Domain ExeDomain = d;
134 bit hasVEXPrefix = 0; // Does this inst requires a VEX prefix?
135 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
136 bit hasVEX_4VPrefix = 0; // Does this inst requires the VEX.VVVV field?
138 // TSFlags layout should be kept in sync with X86InstrInfo.h.
139 let TSFlags{5-0} = FormBits;
140 let TSFlags{6} = hasOpSizePrefix;
141 let TSFlags{7} = hasAdSizePrefix;
142 let TSFlags{11-8} = Prefix;
143 let TSFlags{12} = hasREX_WPrefix;
144 let TSFlags{15-13} = ImmT.Value;
145 let TSFlags{18-16} = FPForm.Value;
146 let TSFlags{19} = hasLockPrefix;
147 let TSFlags{21-20} = SegOvrBits;
148 let TSFlags{23-22} = ExeDomain.Value;
149 let TSFlags{31-24} = Opcode;
150 let TSFlags{32} = hasVEXPrefix;
151 let TSFlags{33} = hasVEX_WPrefix;
152 let TSFlags{34} = hasVEX_4VPrefix;
155 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
156 list<dag> pattern, Domain d = GenericDomain>
157 : X86Inst<o, f, NoImm, outs, ins, asm, d> {
158 let Pattern = pattern;
161 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
162 list<dag> pattern, Domain d = GenericDomain>
163 : X86Inst<o, f, Imm8, outs, ins, asm, d> {
164 let Pattern = pattern;
167 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
169 : X86Inst<o, f, Imm8PCRel, outs, ins, asm> {
170 let Pattern = pattern;
173 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
175 : X86Inst<o, f, Imm16, outs, ins, asm> {
176 let Pattern = pattern;
179 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
181 : X86Inst<o, f, Imm32, outs, ins, asm> {
182 let Pattern = pattern;
186 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
188 : X86Inst<o, f, Imm32PCRel, outs, ins, asm> {
189 let Pattern = pattern;
193 // FPStack Instruction Templates:
194 // FPI - Floating Point Instruction template.
195 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
196 : I<o, F, outs, ins, asm, []> {}
198 // FpI_ - Floating Point Psuedo Instruction template. Not Predicated.
199 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>
200 : X86Inst<0, Pseudo, NoImm, outs, ins, ""> {
202 let Pattern = pattern;
205 // Templates for instructions that use a 16- or 32-bit segmented address as
206 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
208 // Iseg16 - 16-bit segment selector, 16-bit offset
209 // Iseg32 - 16-bit segment selector, 32-bit offset
211 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
212 list<dag> pattern> : X86Inst<o, f, NoImm, outs, ins, asm> {
213 let Pattern = pattern;
217 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
218 list<dag> pattern> : X86Inst<o, f, NoImm, outs, ins, asm> {
219 let Pattern = pattern;
223 // SI - SSE 1 & 2 scalar instructions
224 class SI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
225 : I<o, F, outs, ins, asm, pattern> {
226 let Predicates = !if(hasVEXPrefix /* VEX_4V */,
227 !if(!eq(Prefix, 11 /* XD */), [HasAVX, HasSSE2], [HasAVX, HasSSE1]),
228 !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
230 // AVX instructions have a 'v' prefix in the mnemonic
231 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
234 // SIi8 - SSE 1 & 2 scalar instructions
235 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
237 : Ii8<o, F, outs, ins, asm, pattern> {
238 let Predicates = !if(hasVEXPrefix /* VEX_4V */,
239 !if(!eq(Prefix, 11 /* XD */), [HasAVX, HasSSE2], [HasAVX, HasSSE1]),
240 !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
242 // AVX instructions have a 'v' prefix in the mnemonic
243 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
246 // PI - SSE 1 & 2 packed instructions
247 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
249 : I<o, F, outs, ins, asm, pattern, d> {
250 let Predicates = !if(hasVEXPrefix /* VEX_4V */,
251 !if(hasOpSizePrefix /* OpSize */, [HasAVX, HasSSE2], [HasAVX, HasSSE1]),
252 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
254 // AVX instructions have a 'v' prefix in the mnemonic
255 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
258 // PIi8 - SSE 1 & 2 packed instructions with immediate
259 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
260 list<dag> pattern, Domain d>
261 : Ii8<o, F, outs, ins, asm, pattern, d> {
262 let Predicates = !if(hasVEX_4VPrefix /* VEX_4V */,
263 !if(hasOpSizePrefix /* OpSize */, [HasAVX, HasSSE2], [HasAVX, HasSSE1]),
264 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
266 // AVX instructions have a 'v' prefix in the mnemonic
267 let AsmString = !if(hasVEX_4VPrefix, !strconcat("v", asm), asm);
270 // SSE1 Instruction Templates:
272 // SSI - SSE1 instructions with XS prefix.
273 // PSI - SSE1 instructions with TB prefix.
274 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
275 // VSSI - SSE1 instructions with XS prefix in AVX form.
276 // VPSI - SSE1 instructions with TB prefix in AVX form.
278 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
279 : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
280 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
282 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
283 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
284 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
286 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
288 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
290 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
292 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, XS,
293 Requires<[HasAVX, HasSSE1]>;
294 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
296 : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedSingle>,
297 Requires<[HasAVX, HasSSE1]>;
299 // SSE2 Instruction Templates:
301 // SDI - SSE2 instructions with XD prefix.
302 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
303 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
304 // PDI - SSE2 instructions with TB and OpSize prefixes.
305 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
306 // VSDI - SSE2 instructions with XD prefix in AVX form.
307 // VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form.
309 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
310 : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
311 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
313 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
314 class SSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
316 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
317 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
318 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
320 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
322 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
324 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
326 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, XD,
327 Requires<[HasAVX, HasSSE2]>;
328 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
330 : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedDouble>,
331 OpSize, Requires<[HasAVX, HasSSE2]>;
333 // SSE3 Instruction Templates:
335 // S3I - SSE3 instructions with TB and OpSize prefixes.
336 // S3SI - SSE3 instructions with XS prefix.
337 // S3DI - SSE3 instructions with XD prefix.
339 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
341 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, XS,
343 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
345 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, XD,
347 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
348 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
352 // SSSE3 Instruction Templates:
354 // SS38I - SSSE3 instructions with T8 prefix.
355 // SS3AI - SSSE3 instructions with TA prefix.
357 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
358 // uses the MMX registers. We put those instructions here because they better
359 // fit into the SSSE3 instruction category rather than the MMX category.
361 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
363 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
364 Requires<[HasSSSE3]>;
365 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
367 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
368 Requires<[HasSSSE3]>;
370 // SSE4.1 Instruction Templates:
372 // SS48I - SSE 4.1 instructions with T8 prefix.
373 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
375 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
377 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
378 Requires<[HasSSE41]>;
379 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
381 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
382 Requires<[HasSSE41]>;
384 // SSE4.2 Instruction Templates:
386 // SS428I - SSE 4.2 instructions with T8 prefix.
387 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
389 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
390 Requires<[HasSSE42]>;
392 // SS42FI - SSE 4.2 instructions with TF prefix.
393 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
395 : I<o, F, outs, ins, asm, pattern>, TF, Requires<[HasSSE42]>;
397 // SS42AI = SSE 4.2 instructions with TA prefix
398 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
400 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
401 Requires<[HasSSE42]>;
403 // AES Instruction Templates:
406 // These use the same encoding as the SSE4.2 T8 and TA encodings.
407 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
409 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
412 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
414 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
417 // X86-64 Instruction templates...
420 class RI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
421 : I<o, F, outs, ins, asm, pattern>, REX_W;
422 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
424 : Ii8<o, F, outs, ins, asm, pattern>, REX_W;
425 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
427 : Ii32<o, F, outs, ins, asm, pattern>, REX_W;
429 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
431 : X86Inst<o, f, Imm64, outs, ins, asm>, REX_W {
432 let Pattern = pattern;
436 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
438 : SSI<o, F, outs, ins, asm, pattern>, REX_W;
439 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
441 : SDI<o, F, outs, ins, asm, pattern>, REX_W;
442 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
444 : PDI<o, F, outs, ins, asm, pattern>, REX_W;
446 // MMX Instruction templates
449 // MMXI - MMX instructions with TB prefix.
450 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
451 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
452 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
453 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
454 // MMXID - MMX instructions with XD prefix.
455 // MMXIS - MMX instructions with XS prefix.
456 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
458 : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
459 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
461 : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX,In64BitMode]>;
462 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
464 : I<o, F, outs, ins, asm, pattern>, TB, REX_W, Requires<[HasMMX]>;
465 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
467 : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasMMX]>;
468 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
470 : Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
471 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
473 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX]>;
474 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
476 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX]>;