1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>;
25 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
26 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
27 def MRM6r : Format<22>; def MRM7r : Format<23>;
28 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
29 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
30 def MRM6m : Format<30>; def MRM7m : Format<31>;
31 def MRMInitReg : Format<32>;
32 def MRM_C1 : Format<33>;
33 def MRM_C2 : Format<34>;
34 def MRM_C3 : Format<35>;
35 def MRM_C4 : Format<36>;
36 def MRM_C8 : Format<37>;
37 def MRM_C9 : Format<38>;
38 def MRM_E8 : Format<39>;
39 def MRM_F0 : Format<40>;
40 def MRM_F8 : Format<41>;
41 def MRM_F9 : Format<42>;
42 def RawFrmImm8 : Format<43>;
43 def RawFrmImm16 : Format<44>;
44 def MRM_D0 : Format<45>;
45 def MRM_D1 : Format<46>;
46 def MRM_D4 : Format<47>;
47 def MRM_D5 : Format<48>;
48 def MRM_D6 : Format<49>;
49 def MRM_D8 : Format<50>;
50 def MRM_D9 : Format<51>;
51 def MRM_DA : Format<52>;
52 def MRM_DB : Format<53>;
53 def MRM_DC : Format<54>;
54 def MRM_DD : Format<55>;
55 def MRM_DE : Format<56>;
56 def MRM_DF : Format<57>;
58 // ImmType - This specifies the immediate type used by an instruction. This is
59 // part of the ad-hoc solution used to emit machine instruction encodings by our
60 // machine code emitter.
61 class ImmType<bits<3> val> {
64 def NoImm : ImmType<0>;
65 def Imm8 : ImmType<1>;
66 def Imm8PCRel : ImmType<2>;
67 def Imm16 : ImmType<3>;
68 def Imm16PCRel : ImmType<4>;
69 def Imm32 : ImmType<5>;
70 def Imm32PCRel : ImmType<6>;
71 def Imm64 : ImmType<7>;
73 // FPFormat - This specifies what form this FP instruction has. This is used by
74 // the Floating-Point stackifier pass.
75 class FPFormat<bits<3> val> {
78 def NotFP : FPFormat<0>;
79 def ZeroArgFP : FPFormat<1>;
80 def OneArgFP : FPFormat<2>;
81 def OneArgFPRW : FPFormat<3>;
82 def TwoArgFP : FPFormat<4>;
83 def CompareFP : FPFormat<5>;
84 def CondMovFP : FPFormat<6>;
85 def SpecialFP : FPFormat<7>;
87 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
88 // Keep in sync with tables in X86InstrInfo.cpp.
89 class Domain<bits<2> val> {
92 def GenericDomain : Domain<0>;
93 def SSEPackedSingle : Domain<1>;
94 def SSEPackedDouble : Domain<2>;
95 def SSEPackedInt : Domain<3>;
97 // Prefix byte classes which are used to indicate to the ad-hoc machine code
98 // emitter that various prefix bytes are required.
99 class OpSize { bit hasOpSizePrefix = 1; }
100 class AdSize { bit hasAdSizePrefix = 1; }
101 class REX_W { bit hasREX_WPrefix = 1; }
102 class LOCK { bit hasLockPrefix = 1; }
103 class SegFS { bits<2> SegOvrBits = 1; }
104 class SegGS { bits<2> SegOvrBits = 2; }
105 class TB { bits<5> Prefix = 1; }
106 class REP { bits<5> Prefix = 2; }
107 class D8 { bits<5> Prefix = 3; }
108 class D9 { bits<5> Prefix = 4; }
109 class DA { bits<5> Prefix = 5; }
110 class DB { bits<5> Prefix = 6; }
111 class DC { bits<5> Prefix = 7; }
112 class DD { bits<5> Prefix = 8; }
113 class DE { bits<5> Prefix = 9; }
114 class DF { bits<5> Prefix = 10; }
115 class XD { bits<5> Prefix = 11; }
116 class XS { bits<5> Prefix = 12; }
117 class T8 { bits<5> Prefix = 13; }
118 class TA { bits<5> Prefix = 14; }
119 class A6 { bits<5> Prefix = 15; }
120 class A7 { bits<5> Prefix = 16; }
121 class T8XD { bits<5> Prefix = 17; }
122 class T8XS { bits<5> Prefix = 18; }
123 class TAXD { bits<5> Prefix = 19; }
124 class XOP8 { bits<5> Prefix = 20; }
125 class XOP9 { bits<5> Prefix = 21; }
126 class VEX { bit hasVEXPrefix = 1; }
127 class VEX_W { bit hasVEX_WPrefix = 1; }
128 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
129 class VEX_4VOp3 : VEX { bit hasVEX_4VOp3Prefix = 1; }
130 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
131 class VEX_L { bit hasVEX_L = 1; }
132 class VEX_LIG { bit ignoresVEX_L = 1; }
133 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
134 class MemOp4 { bit hasMemOp4Prefix = 1; }
135 class XOP { bit hasXOP_Prefix = 1; }
136 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
139 Domain d = GenericDomain>
141 let Namespace = "X86";
143 bits<8> Opcode = opcod;
145 bits<6> FormBits = Form.Value;
148 dag OutOperandList = outs;
149 dag InOperandList = ins;
150 string AsmString = AsmStr;
152 // If this is a pseudo instruction, mark it isCodeGenOnly.
153 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
155 let Itinerary = itin;
158 // Attributes specific to X86 instructions...
160 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
161 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
163 bits<5> Prefix = 0; // Which prefix byte does this inst have?
164 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
165 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
166 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
167 bits<2> SegOvrBits = 0; // Segment override prefix.
168 Domain ExeDomain = d;
169 bit hasVEXPrefix = 0; // Does this inst require a VEX prefix?
170 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
171 bit hasVEX_4VPrefix = 0; // Does this inst require the VEX.VVVV field?
172 bit hasVEX_4VOp3Prefix = 0; // Does this inst require the VEX.VVVV field to
173 // encode the third operand?
174 bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register
175 // to be encoded in a immediate field?
176 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
177 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
178 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
179 bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands
180 bit hasXOP_Prefix = 0; // Does this inst require an XOP prefix?
182 // TSFlags layout should be kept in sync with X86InstrInfo.h.
183 let TSFlags{5-0} = FormBits;
184 let TSFlags{6} = hasOpSizePrefix;
185 let TSFlags{7} = hasAdSizePrefix;
186 let TSFlags{12-8} = Prefix;
187 let TSFlags{13} = hasREX_WPrefix;
188 let TSFlags{16-14} = ImmT.Value;
189 let TSFlags{19-17} = FPForm.Value;
190 let TSFlags{20} = hasLockPrefix;
191 let TSFlags{22-21} = SegOvrBits;
192 let TSFlags{24-23} = ExeDomain.Value;
193 let TSFlags{32-25} = Opcode;
194 let TSFlags{33} = hasVEXPrefix;
195 let TSFlags{34} = hasVEX_WPrefix;
196 let TSFlags{35} = hasVEX_4VPrefix;
197 let TSFlags{36} = hasVEX_4VOp3Prefix;
198 let TSFlags{37} = hasVEX_i8ImmReg;
199 let TSFlags{38} = hasVEX_L;
200 let TSFlags{39} = ignoresVEX_L;
201 let TSFlags{40} = has3DNow0F0FOpcode;
202 let TSFlags{41} = hasMemOp4Prefix;
203 let TSFlags{42} = hasXOP_Prefix;
206 class PseudoI<dag oops, dag iops, list<dag> pattern>
207 : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> {
208 let Pattern = pattern;
211 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
212 list<dag> pattern, InstrItinClass itin = NoItinerary,
213 Domain d = GenericDomain>
214 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
215 let Pattern = pattern;
218 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
219 list<dag> pattern, InstrItinClass itin = NoItinerary,
220 Domain d = GenericDomain>
221 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
222 let Pattern = pattern;
225 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
226 list<dag> pattern, InstrItinClass itin = NoItinerary>
227 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
228 let Pattern = pattern;
231 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
232 list<dag> pattern, InstrItinClass itin = NoItinerary>
233 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
234 let Pattern = pattern;
237 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
238 list<dag> pattern, InstrItinClass itin = NoItinerary>
239 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
240 let Pattern = pattern;
244 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
245 list<dag> pattern, InstrItinClass itin = NoItinerary>
246 : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> {
247 let Pattern = pattern;
251 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
252 list<dag> pattern, InstrItinClass itin = NoItinerary>
253 : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> {
254 let Pattern = pattern;
258 // FPStack Instruction Templates:
259 // FPI - Floating Point Instruction template.
260 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm,
261 InstrItinClass itin = NoItinerary>
262 : I<o, F, outs, ins, asm, [], itin> {}
264 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
265 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
266 InstrItinClass itin = NoItinerary>
267 : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> {
269 let Pattern = pattern;
272 // Templates for instructions that use a 16- or 32-bit segmented address as
273 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
275 // Iseg16 - 16-bit segment selector, 16-bit offset
276 // Iseg32 - 16-bit segment selector, 32-bit offset
278 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
279 list<dag> pattern, InstrItinClass itin = NoItinerary>
280 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
281 let Pattern = pattern;
285 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
286 list<dag> pattern, InstrItinClass itin = NoItinerary>
287 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
288 let Pattern = pattern;
294 // SI - SSE 1 & 2 scalar instructions
295 class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
296 list<dag> pattern, InstrItinClass itin = NoItinerary>
297 : I<o, F, outs, ins, asm, pattern, itin> {
298 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
299 !if(!eq(Prefix, __xs.Prefix), [UseSSE1], [UseSSE2]));
301 // AVX instructions have a 'v' prefix in the mnemonic
302 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
305 // SIi8 - SSE 1 & 2 scalar instructions
306 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
307 list<dag> pattern, InstrItinClass itin = NoItinerary>
308 : Ii8<o, F, outs, ins, asm, pattern, itin> {
309 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
310 !if(!eq(Prefix, __xs.Prefix), [UseSSE1], [UseSSE2]));
312 // AVX instructions have a 'v' prefix in the mnemonic
313 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
316 // PI - SSE 1 & 2 packed instructions
317 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
318 InstrItinClass itin, Domain d>
319 : I<o, F, outs, ins, asm, pattern, itin, d> {
320 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
321 !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1]));
323 // AVX instructions have a 'v' prefix in the mnemonic
324 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
327 // MMXPI - SSE 1 & 2 packed instructions with MMX operands
328 class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
329 InstrItinClass itin, Domain d>
330 : I<o, F, outs, ins, asm, pattern, itin, d> {
331 let Predicates = !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]);
334 // PIi8 - SSE 1 & 2 packed instructions with immediate
335 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
336 list<dag> pattern, InstrItinClass itin, Domain d>
337 : Ii8<o, F, outs, ins, asm, pattern, itin, d> {
338 let Predicates = !if(hasVEX_4VPrefix /* VEX */, [HasAVX],
339 !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1]));
341 // AVX instructions have a 'v' prefix in the mnemonic
342 let AsmString = !if(hasVEX_4VPrefix, !strconcat("v", asm), asm);
345 // SSE1 Instruction Templates:
347 // SSI - SSE1 instructions with XS prefix.
348 // PSI - SSE1 instructions with TB prefix.
349 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
350 // VSSI - SSE1 instructions with XS prefix in AVX form.
351 // VPSI - SSE1 instructions with TB prefix in AVX form.
353 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm,
354 list<dag> pattern, InstrItinClass itin = NoItinerary>
355 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
356 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
357 list<dag> pattern, InstrItinClass itin = NoItinerary>
358 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
359 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
360 list<dag> pattern, InstrItinClass itin = NoItinerary>
361 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
363 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
364 list<dag> pattern, InstrItinClass itin = NoItinerary>
365 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
367 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
368 list<dag> pattern, InstrItinClass itin = NoItinerary>
369 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
371 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
372 list<dag> pattern, InstrItinClass itin = NoItinerary>
373 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, TB,
376 // SSE2 Instruction Templates:
378 // SDI - SSE2 instructions with XD prefix.
379 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
380 // S2SI - SSE2 instructions with XS prefix.
381 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
382 // PDI - SSE2 instructions with TB and OpSize prefixes.
383 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
384 // VSDI - SSE2 instructions with XD prefix in AVX form.
385 // VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form.
386 // MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as
388 // MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as
391 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
392 list<dag> pattern, InstrItinClass itin = NoItinerary>
393 : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
394 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
395 list<dag> pattern, InstrItinClass itin = NoItinerary>
396 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
397 class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
398 list<dag> pattern, InstrItinClass itin = NoItinerary>
399 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE2]>;
400 class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
401 list<dag> pattern, InstrItinClass itin = NoItinerary>
402 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>;
403 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
404 list<dag> pattern, InstrItinClass itin = NoItinerary>
405 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
407 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
408 list<dag> pattern, InstrItinClass itin = NoItinerary>
409 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
411 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
412 list<dag> pattern, InstrItinClass itin = NoItinerary>
413 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD,
415 class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
416 list<dag> pattern, InstrItinClass itin = NoItinerary>
417 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
419 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
420 list<dag> pattern, InstrItinClass itin = NoItinerary>
421 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>, TB,
422 OpSize, Requires<[HasAVX]>;
423 class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
424 list<dag> pattern, InstrItinClass itin = NoItinerary>
425 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
426 class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
427 list<dag> pattern, InstrItinClass itin = NoItinerary>
428 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
430 // SSE3 Instruction Templates:
432 // S3I - SSE3 instructions with TB and OpSize prefixes.
433 // S3SI - SSE3 instructions with XS prefix.
434 // S3DI - SSE3 instructions with XD prefix.
436 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
437 list<dag> pattern, InstrItinClass itin = NoItinerary>
438 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS,
440 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
441 list<dag> pattern, InstrItinClass itin = NoItinerary>
442 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD,
444 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
445 list<dag> pattern, InstrItinClass itin = NoItinerary>
446 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
450 // SSSE3 Instruction Templates:
452 // SS38I - SSSE3 instructions with T8 prefix.
453 // SS3AI - SSSE3 instructions with TA prefix.
454 // MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands.
455 // MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands.
457 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
458 // uses the MMX registers. The 64-bit versions are grouped with the MMX
459 // classes. They need to be enabled even if AVX is enabled.
461 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
462 list<dag> pattern, InstrItinClass itin = NoItinerary>
463 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
464 Requires<[UseSSSE3]>;
465 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
466 list<dag> pattern, InstrItinClass itin = NoItinerary>
467 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
468 Requires<[UseSSSE3]>;
469 class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
470 list<dag> pattern, InstrItinClass itin = NoItinerary>
471 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
472 Requires<[HasSSSE3]>;
473 class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
474 list<dag> pattern, InstrItinClass itin = NoItinerary>
475 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
476 Requires<[HasSSSE3]>;
478 // SSE4.1 Instruction Templates:
480 // SS48I - SSE 4.1 instructions with T8 prefix.
481 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
483 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
484 list<dag> pattern, InstrItinClass itin = NoItinerary>
485 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
486 Requires<[UseSSE41]>;
487 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
488 list<dag> pattern, InstrItinClass itin = NoItinerary>
489 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
490 Requires<[UseSSE41]>;
492 // SSE4.2 Instruction Templates:
494 // SS428I - SSE 4.2 instructions with T8 prefix.
495 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
496 list<dag> pattern, InstrItinClass itin = NoItinerary>
497 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
498 Requires<[UseSSE42]>;
500 // SS42FI - SSE 4.2 instructions with T8XD prefix.
501 // NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns.
502 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
503 list<dag> pattern, InstrItinClass itin = NoItinerary>
504 : I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>;
506 // SS42AI = SSE 4.2 instructions with TA prefix
507 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
508 list<dag> pattern, InstrItinClass itin = NoItinerary>
509 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
510 Requires<[UseSSE42]>;
512 // AVX Instruction Templates:
513 // Instructions introduced in AVX (no SSE equivalent forms)
515 // AVX8I - AVX instructions with T8 and OpSize prefix.
516 // AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8.
517 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
518 list<dag> pattern, InstrItinClass itin = NoItinerary>
519 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
521 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
522 list<dag> pattern, InstrItinClass itin = NoItinerary>
523 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
526 // AVX2 Instruction Templates:
527 // Instructions introduced in AVX2 (no SSE equivalent forms)
529 // AVX28I - AVX2 instructions with T8 and OpSize prefix.
530 // AVX2AIi8 - AVX2 instructions with TA, OpSize prefix and ImmT = Imm8.
531 class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
532 list<dag> pattern, InstrItinClass itin = NoItinerary>
533 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
535 class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
536 list<dag> pattern, InstrItinClass itin = NoItinerary>
537 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
540 // AES Instruction Templates:
543 // These use the same encoding as the SSE4.2 T8 and TA encodings.
544 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
545 list<dag>pattern, InstrItinClass itin = NoItinerary>
546 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
549 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
550 list<dag> pattern, InstrItinClass itin = NoItinerary>
551 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
554 // PCLMUL Instruction Templates
555 class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
556 list<dag>pattern, InstrItinClass itin = NoItinerary>
557 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
558 OpSize, Requires<[HasPCLMUL]>;
560 class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
561 list<dag>pattern, InstrItinClass itin = NoItinerary>
562 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
563 OpSize, VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
565 // FMA3 Instruction Templates
566 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
567 list<dag>pattern, InstrItinClass itin = NoItinerary>
568 : I<o, F, outs, ins, asm, pattern, itin>, T8,
569 OpSize, VEX_4V, Requires<[HasFMA]>;
571 // FMA4 Instruction Templates
572 class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
573 list<dag>pattern, InstrItinClass itin = NoItinerary>
574 : Ii8<o, F, outs, ins, asm, pattern, itin>, TA,
575 OpSize, VEX_4V, VEX_I8IMM, Requires<[HasFMA4]>;
577 // XOP 2, 3 and 4 Operand Instruction Template
578 class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,
579 list<dag> pattern, InstrItinClass itin = NoItinerary>
580 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
581 XOP, XOP9, Requires<[HasXOP]>;
583 // XOP 2, 3 and 4 Operand Instruction Templates with imm byte
584 class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,
585 list<dag> pattern, InstrItinClass itin = NoItinerary>
586 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
587 XOP, XOP8, Requires<[HasXOP]>;
589 // XOP 5 operand instruction (VEX encoding!)
590 class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
591 list<dag>pattern, InstrItinClass itin = NoItinerary>
592 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
593 OpSize, VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
595 // X86-64 Instruction templates...
598 class RI<bits<8> o, Format F, dag outs, dag ins, string asm,
599 list<dag> pattern, InstrItinClass itin = NoItinerary>
600 : I<o, F, outs, ins, asm, pattern, itin>, REX_W;
601 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
602 list<dag> pattern, InstrItinClass itin = NoItinerary>
603 : Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W;
604 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
605 list<dag> pattern, InstrItinClass itin = NoItinerary>
606 : Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W;
608 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
609 list<dag> pattern, InstrItinClass itin = NoItinerary>
610 : X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W {
611 let Pattern = pattern;
615 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
616 list<dag> pattern, InstrItinClass itin = NoItinerary>
617 : SSI<o, F, outs, ins, asm, pattern, itin>, REX_W;
618 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
619 list<dag> pattern, InstrItinClass itin = NoItinerary>
620 : SDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
621 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
622 list<dag> pattern, InstrItinClass itin = NoItinerary>
623 : PDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
624 class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
625 list<dag> pattern, InstrItinClass itin = NoItinerary>
626 : VPDI<o, F, outs, ins, asm, pattern, itin>, VEX_W;
628 // MMX Instruction templates
631 // MMXI - MMX instructions with TB prefix.
632 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
633 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
634 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
635 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
636 // MMXID - MMX instructions with XD prefix.
637 // MMXIS - MMX instructions with XS prefix.
638 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
639 list<dag> pattern, InstrItinClass itin = NoItinerary>
640 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
641 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
642 list<dag> pattern, InstrItinClass itin = NoItinerary>
643 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX,In64BitMode]>;
644 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
645 list<dag> pattern, InstrItinClass itin = NoItinerary>
646 : I<o, F, outs, ins, asm, pattern, itin>, TB, REX_W, Requires<[HasMMX]>;
647 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
648 list<dag> pattern, InstrItinClass itin = NoItinerary>
649 : I<o, F, outs, ins, asm, pattern, itin>, TB, OpSize, Requires<[HasMMX]>;
650 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
651 list<dag> pattern, InstrItinClass itin = NoItinerary>
652 : Ii8<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
653 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
654 list<dag> pattern, InstrItinClass itin = NoItinerary>
655 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>;
656 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
657 list<dag> pattern, InstrItinClass itin = NoItinerary>
658 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>;