1 //==- X86InstrFPStack.td - Describe the X86 Instruction Set --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 x87 FPU instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // FPStack specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def SDTX86FpGet2 : SDTypeProfile<2, 0, [SDTCisVT<0, f80>,
22 def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>,
24 SDTCisVT<2, OtherVT>]>;
25 def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
27 SDTCisVT<2, OtherVT>]>;
28 def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>,
29 SDTCisVT<2, OtherVT>]>;
30 def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
32 def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
34 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
35 [SDNPHasChain, SDNPMayLoad]>;
36 def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
37 [SDNPHasChain, SDNPInFlag, SDNPMayStore]>;
38 def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
39 [SDNPHasChain, SDNPMayLoad]>;
40 def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild,
41 [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
42 def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
43 [SDNPHasChain, SDNPMayStore]>;
44 def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
45 [SDNPHasChain, SDNPMayStore]>;
46 def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem,
47 [SDNPHasChain, SDNPMayStore]>;
48 def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore,
49 [SDNPHasChain, SDNPMayStore, SDNPSideEffect]>;
51 //===----------------------------------------------------------------------===//
52 // FPStack pattern fragments
53 //===----------------------------------------------------------------------===//
55 def fpimm0 : PatLeaf<(fpimm), [{
56 return N->isExactlyValue(+0.0);
59 def fpimmneg0 : PatLeaf<(fpimm), [{
60 return N->isExactlyValue(-0.0);
63 def fpimm1 : PatLeaf<(fpimm), [{
64 return N->isExactlyValue(+1.0);
67 def fpimmneg1 : PatLeaf<(fpimm), [{
68 return N->isExactlyValue(-1.0);
71 // Some 'special' instructions
72 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
73 def FP32_TO_INT16_IN_MEM : I<0, Pseudo,
74 (outs), (ins i16mem:$dst, RFP32:$src),
75 "#FP32_TO_INT16_IN_MEM PSEUDO!",
76 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>;
77 def FP32_TO_INT32_IN_MEM : I<0, Pseudo,
78 (outs), (ins i32mem:$dst, RFP32:$src),
79 "#FP32_TO_INT32_IN_MEM PSEUDO!",
80 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>;
81 def FP32_TO_INT64_IN_MEM : I<0, Pseudo,
82 (outs), (ins i64mem:$dst, RFP32:$src),
83 "#FP32_TO_INT64_IN_MEM PSEUDO!",
84 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>;
85 def FP64_TO_INT16_IN_MEM : I<0, Pseudo,
86 (outs), (ins i16mem:$dst, RFP64:$src),
87 "#FP64_TO_INT16_IN_MEM PSEUDO!",
88 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>;
89 def FP64_TO_INT32_IN_MEM : I<0, Pseudo,
90 (outs), (ins i32mem:$dst, RFP64:$src),
91 "#FP64_TO_INT32_IN_MEM PSEUDO!",
92 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>;
93 def FP64_TO_INT64_IN_MEM : I<0, Pseudo,
94 (outs), (ins i64mem:$dst, RFP64:$src),
95 "#FP64_TO_INT64_IN_MEM PSEUDO!",
96 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>;
97 def FP80_TO_INT16_IN_MEM : I<0, Pseudo,
98 (outs), (ins i16mem:$dst, RFP80:$src),
99 "#FP80_TO_INT16_IN_MEM PSEUDO!",
100 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>;
101 def FP80_TO_INT32_IN_MEM : I<0, Pseudo,
102 (outs), (ins i32mem:$dst, RFP80:$src),
103 "#FP80_TO_INT32_IN_MEM PSEUDO!",
104 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>;
105 def FP80_TO_INT64_IN_MEM : I<0, Pseudo,
106 (outs), (ins i64mem:$dst, RFP80:$src),
107 "#FP80_TO_INT64_IN_MEM PSEUDO!",
108 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>;
111 let isTerminator = 1 in
112 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
113 def FP_REG_KILL : I<0, Pseudo, (outs), (ins), "#FP_REG_KILL", []>;
115 // All FP Stack operations are represented with four instructions here. The
116 // first three instructions, generated by the instruction selector, use "RFP32"
117 // "RFP64" or "RFP80" registers: traditional register files to reference 32-bit,
118 // 64-bit or 80-bit floating point values. These sizes apply to the values,
119 // not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be
120 // copied to each other without losing information. These instructions are all
121 // pseudo instructions and use the "_Fp" suffix.
122 // In some cases there are additional variants with a mixture of different
124 // The second instruction is defined with FPI, which is the actual instruction
125 // emitted by the assembler. These use "RST" registers, although frequently
126 // the actual register(s) used are implicit. These are always 80 bits.
127 // The FP stackifier pass converts one to the other after register allocation
130 // Note that the FpI instruction should have instruction selection info (e.g.
131 // a pattern) and the FPI instruction should have emission info (e.g. opcode
132 // encoding and asm printing info).
134 // Pseudo Instructions for FP stack return values.
135 def FpGET_ST0_32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP, []>; // FPR = ST(0)
136 def FpGET_ST0_64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP, []>; // FPR = ST(0)
137 def FpGET_ST0_80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>; // FPR = ST(0)
139 def FpGET_ST0_ST1 : FpI_<(outs RFP80:$dst1, RFP80:$dst2), (ins), SpecialFP,
140 []>; // FPR = ST(0), FPR = ST(1)
143 let Defs = [ST0] in {
144 def FpSET_ST0_32 : FpI_<(outs), (ins RFP32:$src), SpecialFP, []>; // ST(0) = FPR
145 def FpSET_ST0_64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, []>; // ST(0) = FPR
146 def FpSET_ST0_80 : FpI_<(outs), (ins RFP80:$src), SpecialFP, []>; // ST(0) = FPR
149 // FpIf32, FpIf64 - Floating Point Psuedo Instruction template.
150 // f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1.
151 // f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2.
152 // f80 instructions cannot use SSE and use neither of these.
153 class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
154 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>;
155 class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
156 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>;
158 // Register copies. Just copies, the shortening ones do not truncate.
159 let neverHasSideEffects = 1 in {
160 def MOV_Fp3232 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), SpecialFP, []>;
161 def MOV_Fp3264 : FpIf32<(outs RFP64:$dst), (ins RFP32:$src), SpecialFP, []>;
162 def MOV_Fp6432 : FpIf32<(outs RFP32:$dst), (ins RFP64:$src), SpecialFP, []>;
163 def MOV_Fp6464 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), SpecialFP, []>;
164 def MOV_Fp8032 : FpIf32<(outs RFP32:$dst), (ins RFP80:$src), SpecialFP, []>;
165 def MOV_Fp3280 : FpIf32<(outs RFP80:$dst), (ins RFP32:$src), SpecialFP, []>;
166 def MOV_Fp8064 : FpIf64<(outs RFP64:$dst), (ins RFP80:$src), SpecialFP, []>;
167 def MOV_Fp6480 : FpIf64<(outs RFP80:$dst), (ins RFP64:$src), SpecialFP, []>;
168 def MOV_Fp8080 : FpI_ <(outs RFP80:$dst), (ins RFP80:$src), SpecialFP, []>;
171 // Factoring for arithmetic.
172 multiclass FPBinary_rr<SDNode OpNode> {
173 // Register op register -> register
174 // These are separated out because they have no reversed form.
175 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP,
176 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
177 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP,
178 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
179 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP,
180 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
182 // The FopST0 series are not included here because of the irregularities
183 // in where the 'r' goes in assembly output.
184 // These instructions cannot address 80-bit memory.
185 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> {
186 // ST(0) = ST(0) + [mem]
187 def _Fp32m : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, f32mem:$src2), OneArgFPRW,
189 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>;
190 def _Fp64m : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, f64mem:$src2), OneArgFPRW,
192 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>;
193 def _Fp64m32: FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, f32mem:$src2), OneArgFPRW,
195 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2))))]>;
196 def _Fp80m32: FpI_<(outs RFP80:$dst), (ins RFP80:$src1, f32mem:$src2), OneArgFPRW,
198 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2))))]>;
199 def _Fp80m64: FpI_<(outs RFP80:$dst), (ins RFP80:$src1, f64mem:$src2), OneArgFPRW,
201 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2))))]>;
202 def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src),
203 !strconcat("f", !strconcat(asmstring, "{s}\t$src"))> { let mayLoad = 1; }
204 def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src),
205 !strconcat("f", !strconcat(asmstring, "{l}\t$src"))> { let mayLoad = 1; }
206 // ST(0) = ST(0) + [memint]
207 def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), OneArgFPRW,
208 [(set RFP32:$dst, (OpNode RFP32:$src1,
209 (X86fild addr:$src2, i16)))]>;
210 def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), OneArgFPRW,
211 [(set RFP32:$dst, (OpNode RFP32:$src1,
212 (X86fild addr:$src2, i32)))]>;
213 def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), OneArgFPRW,
214 [(set RFP64:$dst, (OpNode RFP64:$src1,
215 (X86fild addr:$src2, i16)))]>;
216 def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), OneArgFPRW,
217 [(set RFP64:$dst, (OpNode RFP64:$src1,
218 (X86fild addr:$src2, i32)))]>;
219 def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), OneArgFPRW,
220 [(set RFP80:$dst, (OpNode RFP80:$src1,
221 (X86fild addr:$src2, i16)))]>;
222 def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), OneArgFPRW,
223 [(set RFP80:$dst, (OpNode RFP80:$src1,
224 (X86fild addr:$src2, i32)))]>;
225 def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src),
226 !strconcat("fi", !strconcat(asmstring, "{s}\t$src"))> { let mayLoad = 1; }
227 def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src),
228 !strconcat("fi", !strconcat(asmstring, "{l}\t$src"))> { let mayLoad = 1; }
231 defm ADD : FPBinary_rr<fadd>;
232 defm SUB : FPBinary_rr<fsub>;
233 defm MUL : FPBinary_rr<fmul>;
234 defm DIV : FPBinary_rr<fdiv>;
235 defm ADD : FPBinary<fadd, MRM0m, "add">;
236 defm SUB : FPBinary<fsub, MRM4m, "sub">;
237 defm SUBR: FPBinary<fsub ,MRM5m, "subr">;
238 defm MUL : FPBinary<fmul, MRM1m, "mul">;
239 defm DIV : FPBinary<fdiv, MRM6m, "div">;
240 defm DIVR: FPBinary<fdiv, MRM7m, "divr">;
242 class FPST0rInst<bits<8> o, string asm>
243 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, D8;
244 class FPrST0Inst<bits<8> o, string asm>
245 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DC;
246 class FPrST0PInst<bits<8> o, string asm>
247 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DE;
249 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
250 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
251 // we have to put some 'r's in and take them out of weird places.
252 def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">;
253 def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, %ST(0)}">;
254 def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp\t$op">;
255 def SUBR_FST0r : FPST0rInst <0xE8, "fsubr\t$op">;
256 def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, %ST(0)}">;
257 def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p\t$op">;
258 def SUB_FST0r : FPST0rInst <0xE0, "fsub\t$op">;
259 def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, %ST(0)}">;
260 def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">;
261 def MUL_FST0r : FPST0rInst <0xC8, "fmul\t$op">;
262 def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, %ST(0)}">;
263 def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp\t$op">;
264 def DIVR_FST0r : FPST0rInst <0xF8, "fdivr\t$op">;
265 def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, %ST(0)}">;
266 def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p\t$op">;
267 def DIV_FST0r : FPST0rInst <0xF0, "fdiv\t$op">;
268 def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, %ST(0)}">;
269 def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">;
272 multiclass FPUnary<SDNode OpNode, bits<8> opcode, string asmstring> {
273 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW,
274 [(set RFP32:$dst, (OpNode RFP32:$src))]>;
275 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW,
276 [(set RFP64:$dst, (OpNode RFP64:$src))]>;
277 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW,
278 [(set RFP80:$dst, (OpNode RFP80:$src))]>;
279 def _F : FPI<opcode, RawFrm, (outs), (ins), asmstring>, D9;
282 defm CHS : FPUnary<fneg, 0xE0, "fchs">;
283 defm ABS : FPUnary<fabs, 0xE1, "fabs">;
284 defm SQRT: FPUnary<fsqrt,0xFA, "fsqrt">;
285 defm SIN : FPUnary<fsin, 0xFE, "fsin">;
286 defm COS : FPUnary<fcos, 0xFF, "fcos">;
288 let neverHasSideEffects = 1 in {
289 def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>;
290 def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>;
291 def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>;
293 def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9;
295 // Floating point cmovs.
296 multiclass FPCMov<PatLeaf cc> {
297 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2),
299 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2,
301 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2),
303 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2,
305 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2),
307 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,
310 let Uses = [EFLAGS], isTwoAddress = 1 in {
311 defm CMOVB : FPCMov<X86_COND_B>;
312 defm CMOVBE : FPCMov<X86_COND_BE>;
313 defm CMOVE : FPCMov<X86_COND_E>;
314 defm CMOVP : FPCMov<X86_COND_P>;
315 defm CMOVNB : FPCMov<X86_COND_AE>;
316 defm CMOVNBE: FPCMov<X86_COND_A>;
317 defm CMOVNE : FPCMov<X86_COND_NE>;
318 defm CMOVNP : FPCMov<X86_COND_NP>;
321 // These are not factored because there's no clean way to pass DA/DB.
322 def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
323 "fcmovb\t{$op, %st(0)|%ST(0), $op}">, DA;
324 def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
325 "fcmovbe\t{$op, %st(0)|%ST(0), $op}">, DA;
326 def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
327 "fcmove\t{$op, %st(0)|%ST(0), $op}">, DA;
328 def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
329 "fcmovu\t {$op, %st(0)|%ST(0), $op}">, DA;
330 def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
331 "fcmovnb\t{$op, %st(0)|%ST(0), $op}">, DB;
332 def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
333 "fcmovnbe\t{$op, %st(0)|%ST(0), $op}">, DB;
334 def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
335 "fcmovne\t{$op, %st(0)|%ST(0), $op}">, DB;
336 def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
337 "fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB;
339 // Floating point loads & stores.
340 let isSimpleLoad = 1 in {
341 def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
342 [(set RFP32:$dst, (loadf32 addr:$src))]>;
343 let isReMaterializable = 1, mayHaveSideEffects = 1 in
344 def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP,
345 [(set RFP64:$dst, (loadf64 addr:$src))]>;
346 def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP,
347 [(set RFP80:$dst, (loadf80 addr:$src))]>;
349 def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP,
350 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>;
351 def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP,
352 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>;
353 def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP,
354 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>;
355 def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP,
356 [(set RFP32:$dst, (X86fild addr:$src, i16))]>;
357 def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP,
358 [(set RFP32:$dst, (X86fild addr:$src, i32))]>;
359 def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP,
360 [(set RFP32:$dst, (X86fild addr:$src, i64))]>;
361 def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP,
362 [(set RFP64:$dst, (X86fild addr:$src, i16))]>;
363 def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP,
364 [(set RFP64:$dst, (X86fild addr:$src, i32))]>;
365 def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP,
366 [(set RFP64:$dst, (X86fild addr:$src, i64))]>;
367 def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP,
368 [(set RFP80:$dst, (X86fild addr:$src, i16))]>;
369 def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP,
370 [(set RFP80:$dst, (X86fild addr:$src, i32))]>;
371 def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP,
372 [(set RFP80:$dst, (X86fild addr:$src, i64))]>;
374 def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP,
375 [(store RFP32:$src, addr:$op)]>;
376 def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP,
377 [(truncstoref32 RFP64:$src, addr:$op)]>;
378 def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP,
379 [(store RFP64:$src, addr:$op)]>;
380 def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP,
381 [(truncstoref32 RFP80:$src, addr:$op)]>;
382 def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP,
383 [(truncstoref64 RFP80:$src, addr:$op)]>;
384 // FST does not support 80-bit memory target; FSTP must be used.
386 let mayStore = 1, neverHasSideEffects = 1 in {
387 def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>;
388 def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>;
389 def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>;
390 def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>;
391 def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>;
393 def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP,
394 [(store RFP80:$src, addr:$op)]>;
395 let mayStore = 1, neverHasSideEffects = 1 in {
396 def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>;
397 def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>;
398 def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>;
399 def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>;
400 def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>;
401 def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>;
402 def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>;
403 def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>;
404 def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>;
408 def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
409 def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
410 def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">;
411 def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;
412 def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;
413 def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
415 let mayStore = 1 in {
416 def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;
417 def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
418 def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">;
419 def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">;
420 def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">;
421 def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">;
422 def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">;
423 def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">;
424 def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">;
425 def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">;
428 // FISTTP requires SSE3 even though it's a FPStack op.
429 def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP,
430 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>,
432 def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP,
433 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>,
435 def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP,
436 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>,
438 def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP,
439 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>,
441 def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP,
442 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>,
444 def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP,
445 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>,
447 def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP,
448 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>,
450 def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP,
451 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>,
453 def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP,
454 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>,
457 let mayStore = 1 in {
458 def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">;
459 def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">;
460 def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">;
463 // FP Stack manipulation instructions.
464 def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld\t$op">, D9;
465 def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst\t$op">, DD;
466 def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp\t$op">, DD;
467 def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch\t$op">, D9;
469 // Floating point constant loads.
470 let isReMaterializable = 1 in {
471 def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
472 [(set RFP32:$dst, fpimm0)]>;
473 def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
474 [(set RFP32:$dst, fpimm1)]>;
475 def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
476 [(set RFP64:$dst, fpimm0)]>;
477 def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
478 [(set RFP64:$dst, fpimm1)]>;
479 def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
480 [(set RFP80:$dst, fpimm0)]>;
481 def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
482 [(set RFP80:$dst, fpimm1)]>;
485 def LD_F0 : FPI<0xEE, RawFrm, (outs), (ins), "fldz">, D9;
486 def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1">, D9;
489 // Floating point compares.
490 let Defs = [EFLAGS] in {
491 def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
492 []>; // FPSW = cmp ST(0) with ST(i)
493 def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
494 []>; // FPSW = cmp ST(0) with ST(i)
495 def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
496 []>; // FPSW = cmp ST(0) with ST(i)
498 def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
499 [(X86cmp RFP32:$lhs, RFP32:$rhs),
500 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
501 def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
502 [(X86cmp RFP64:$lhs, RFP64:$rhs),
503 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
504 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
505 [(X86cmp RFP80:$lhs, RFP80:$rhs),
506 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
509 let Defs = [EFLAGS], Uses = [ST0] in {
510 def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
511 (outs), (ins RST:$reg),
513 def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
514 (outs), (ins RST:$reg),
516 def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
520 def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
521 (outs), (ins RST:$reg),
522 "fucomi\t{$reg, %st(0)|%ST(0), $reg}">, DB;
523 def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
524 (outs), (ins RST:$reg),
525 "fucomip\t{$reg, %st(0)|%ST(0), $reg}">, DF;
528 // Floating point flag ops.
530 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
531 (outs), (ins), "fnstsw", []>, DF;
533 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
534 (outs), (ins i16mem:$dst), "fnstcw\t$dst",
535 [(X86fp_cwd_get16 addr:$dst)]>;
538 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
539 (outs), (ins i16mem:$dst), "fldcw\t$dst", []>;
541 //===----------------------------------------------------------------------===//
542 // Non-Instruction Patterns
543 //===----------------------------------------------------------------------===//
545 // Required for RET of f32 / f64 / f80 values.
546 def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>;
547 def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>;
548 def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>;
550 // Required for CALL which return f32 / f64 / f80 values.
551 def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>;
552 def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, RFP64:$src)>;
553 def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>;
554 def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op, RFP80:$src)>;
555 def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op, RFP80:$src)>;
556 def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op, RFP80:$src)>;
558 // Floating point constant -0.0 and -1.0
559 def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>;
560 def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>;
561 def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>;
562 def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>;
563 def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>;
564 def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>;
566 // Used to conv. i64 to f64 since there isn't a SSE version.
567 def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>;
569 // FP extensions map onto simple pseudo-value conversions if they are to/from
571 def : Pat<(f64 (fextend RFP32:$src)), (MOV_Fp3264 RFP32:$src)>,
572 Requires<[FPStackf32]>;
573 def : Pat<(f80 (fextend RFP32:$src)), (MOV_Fp3280 RFP32:$src)>,
574 Requires<[FPStackf32]>;
575 def : Pat<(f80 (fextend RFP64:$src)), (MOV_Fp6480 RFP64:$src)>,
576 Requires<[FPStackf64]>;
578 // FP truncations map onto simple pseudo-value conversions if they are to/from
579 // the FP stack. We have validated that only value-preserving truncations make
581 def : Pat<(f32 (fround RFP64:$src)), (MOV_Fp6432 RFP64:$src)>,
582 Requires<[FPStackf32]>;
583 def : Pat<(f32 (fround RFP80:$src)), (MOV_Fp8032 RFP80:$src)>,
584 Requires<[FPStackf32]>;
585 def : Pat<(f64 (fround RFP80:$src)), (MOV_Fp8064 RFP80:$src)>,
586 Requires<[FPStackf64]>;