1 //==- X86InstrFPStack.td - Describe the X86 Instruction Set -------*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 x87 FPU instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // FPStack specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def SDTX86FpGet : SDTypeProfile<1, 0, [SDTCisFP<0>]>;
21 def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
22 def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>,
24 SDTCisVT<2, OtherVT>]>;
25 def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
27 SDTCisVT<2, OtherVT>]>;
28 def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>,
29 SDTCisVT<2, OtherVT>]>;
30 def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
32 def X86fpget : SDNode<"X86ISD::FP_GET_RESULT", SDTX86FpGet,
33 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
34 def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet,
35 [SDNPHasChain, SDNPOutFlag]>;
36 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
38 def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
39 [SDNPHasChain, SDNPInFlag]>;
40 def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
42 def X86fildflag : SDNode<"X86ISD::FILD_FLAG",SDTX86Fild,
43 [SDNPHasChain, SDNPOutFlag]>;
44 def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
46 def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
48 def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem,
51 //===----------------------------------------------------------------------===//
52 // FPStack pattern fragments
53 //===----------------------------------------------------------------------===//
55 def fpimm0 : PatLeaf<(fpimm), [{
56 return N->isExactlyValue(+0.0);
59 def fpimmneg0 : PatLeaf<(fpimm), [{
60 return N->isExactlyValue(-0.0);
63 def fpimm1 : PatLeaf<(fpimm), [{
64 return N->isExactlyValue(+1.0);
67 def fpimmneg1 : PatLeaf<(fpimm), [{
68 return N->isExactlyValue(-1.0);
71 // Some 'special' instructions
72 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
73 def FP32_TO_INT16_IN_MEM : I<0, Pseudo,
74 (ops i16mem:$dst, RFP32:$src),
75 "#FP32_TO_INT16_IN_MEM PSEUDO!",
76 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>;
77 def FP32_TO_INT32_IN_MEM : I<0, Pseudo,
78 (ops i32mem:$dst, RFP32:$src),
79 "#FP32_TO_INT32_IN_MEM PSEUDO!",
80 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>;
81 def FP32_TO_INT64_IN_MEM : I<0, Pseudo,
82 (ops i64mem:$dst, RFP32:$src),
83 "#FP32_TO_INT64_IN_MEM PSEUDO!",
84 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>;
85 def FP64_TO_INT16_IN_MEM : I<0, Pseudo,
86 (ops i16mem:$dst, RFP64:$src),
87 "#FP64_TO_INT16_IN_MEM PSEUDO!",
88 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>;
89 def FP64_TO_INT32_IN_MEM : I<0, Pseudo,
90 (ops i32mem:$dst, RFP64:$src),
91 "#FP64_TO_INT32_IN_MEM PSEUDO!",
92 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>;
93 def FP64_TO_INT64_IN_MEM : I<0, Pseudo,
94 (ops i64mem:$dst, RFP64:$src),
95 "#FP64_TO_INT64_IN_MEM PSEUDO!",
96 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>;
99 let isTerminator = 1 in
100 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
101 def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL", []>;
103 // All FP Stack operations are represented with three instructions here. The
104 // first two instructions, generated by the instruction selector, uses "RFP32"
105 // or "RFP64" registers: traditional register files to reference 32-bit or
106 // 64-bit floating point values. These sizes apply to the values, not the
107 // registers, which are always 64 bits; RFP32 and RFP64 can be copied to
108 // each other without losing information. These instructions are all psuedo
109 // instructions and use the "_Fp" suffix.
110 // In some cases there are additional variants with a mixture of 32-bit and
112 // The second instruction is defined with FPI, which is the actual instruction
113 // emitted by the assembler. These use "RST" registers, although frequently
114 // the actual register(s) used are implicit. These are always 64-bits.
115 // The FP stackifier pass converts one to the other after register allocation
118 // Note that the FpI instruction should have instruction selection info (e.g.
119 // a pattern) and the FPI instruction should have emission info (e.g. opcode
120 // encoding and asm printing info).
122 // FPI - Floating Point Instruction template.
123 class FPI<bits<8> o, Format F, dag ops, string asm> : I<o, F, ops, asm, []> {}
125 // FpI_ - Floating Point Psuedo Instruction template. Not Predicated.
126 class FpI_<dag ops, FPFormat fp, list<dag> pattern>
127 : X86Inst<0, Pseudo, NoImm, ops, ""> {
128 let FPForm = fp; let FPFormBits = FPForm.Value;
129 let Pattern = pattern;
132 // Random Pseudo Instructions.
133 def FpGETRESULT32 : FpI_<(ops RFP32:$dst), SpecialFP,
134 [(set RFP32:$dst, X86fpget)]>; // FPR = ST(0)
136 def FpGETRESULT64 : FpI_<(ops RFP64:$dst), SpecialFP,
137 [(set RFP64:$dst, X86fpget)]>; // FPR = ST(0)
139 let noResults = 1 in {
140 def FpSETRESULT32 : FpI_<(ops RFP32:$src), SpecialFP,
141 [(X86fpset RFP32:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
143 def FpSETRESULT64 : FpI_<(ops RFP64:$src), SpecialFP,
144 [(X86fpset RFP64:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
146 // FpI - Floating Point Psuedo Instruction template. Predicated on FPStack.
147 class FpI<dag ops, FPFormat fp, list<dag> pattern> :
148 FpI_<ops, fp, pattern>, Requires<[FPStack]>;
150 // Register copies. Just copies, the 64->32 version does not truncate.
151 def MOV_Fp3232 : FpI<(ops RFP32:$dst, RFP32:$src), SpecialFP, []>;
152 def MOV_Fp3264 : FpI<(ops RFP64:$dst, RFP32:$src), SpecialFP, []>;
153 def MOV_Fp6432 : FpI<(ops RFP32:$dst, RFP64:$src), SpecialFP, []>;
154 def MOV_Fp6464 : FpI<(ops RFP64:$dst, RFP64:$src), SpecialFP, []>;
156 // Factoring for arithmetic.
157 multiclass FPBinary_rr<SDNode OpNode> {
158 // Register op register -> register
159 // These are separated out because they have no reversed form.
160 def _Fp32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), TwoArgFP,
161 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
162 def _Fp64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), TwoArgFP,
163 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
165 // The FopST0 series are not included here because of the irregularities
166 // in where the 'r' goes in assembly output.
167 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> {
168 // ST(0) = ST(0) + [mem]
169 def _Fp32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW,
171 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>;
172 def _Fp64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW,
174 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>;
175 def _Fp64m32: FpI<(ops RFP64:$dst, RFP64:$src1, f32mem:$src2), OneArgFPRW,
177 (OpNode RFP64:$src1, (extloadf32 addr:$src2)))]>;
178 def _F32m : FPI<0xD8, fp, (ops f32mem:$src),
179 !strconcat("f", !strconcat(asmstring, "{s} $src"))>;
180 def _F64m : FPI<0xDC, fp, (ops f64mem:$src),
181 !strconcat("f", !strconcat(asmstring, "{l} $src"))>;
182 // ST(0) = ST(0) + [memint]
183 def _FpI16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW,
184 [(set RFP32:$dst, (OpNode RFP32:$src1,
185 (X86fild addr:$src2, i16)))]>;
186 def _FpI32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW,
187 [(set RFP32:$dst, (OpNode RFP32:$src1,
188 (X86fild addr:$src2, i32)))]>;
189 def _FpI16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW,
190 [(set RFP64:$dst, (OpNode RFP64:$src1,
191 (X86fild addr:$src2, i16)))]>;
192 def _FpI32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW,
193 [(set RFP64:$dst, (OpNode RFP64:$src1,
194 (X86fild addr:$src2, i32)))]>;
195 def _FI16m : FPI<0xDE, fp, (ops i16mem:$src),
196 !strconcat("fi", !strconcat(asmstring, "{s} $src"))>;
197 def _FI32m : FPI<0xDA, fp, (ops i32mem:$src),
198 !strconcat("fi", !strconcat(asmstring, "{l} $src"))>;
201 defm ADD : FPBinary_rr<fadd>;
202 defm SUB : FPBinary_rr<fsub>;
203 defm MUL : FPBinary_rr<fmul>;
204 defm DIV : FPBinary_rr<fdiv>;
205 defm ADD : FPBinary<fadd, MRM0m, "add">;
206 defm SUB : FPBinary<fsub, MRM4m, "sub">;
207 defm SUBR: FPBinary<fsub ,MRM5m, "subr">;
208 defm MUL : FPBinary<fmul, MRM1m, "mul">;
209 defm DIV : FPBinary<fdiv, MRM6m, "div">;
210 defm DIVR: FPBinary<fdiv, MRM7m, "divr">;
212 class FPST0rInst<bits<8> o, string asm>
213 : FPI<o, AddRegFrm, (ops RST:$op), asm>, D8;
214 class FPrST0Inst<bits<8> o, string asm>
215 : FPI<o, AddRegFrm, (ops RST:$op), asm>, DC;
216 class FPrST0PInst<bits<8> o, string asm>
217 : FPI<o, AddRegFrm, (ops RST:$op), asm>, DE;
219 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
220 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
221 // we have to put some 'r's in and take them out of weird places.
222 def ADD_FST0r : FPST0rInst <0xC0, "fadd $op">;
223 def ADD_FrST0 : FPrST0Inst <0xC0, "fadd {%st(0), $op|$op, %ST(0)}">;
224 def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp $op">;
225 def SUBR_FST0r : FPST0rInst <0xE8, "fsubr $op">;
226 def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r} {%st(0), $op|$op, %ST(0)}">;
227 def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p $op">;
228 def SUB_FST0r : FPST0rInst <0xE0, "fsub $op">;
229 def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r} {%st(0), $op|$op, %ST(0)}">;
230 def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p $op">;
231 def MUL_FST0r : FPST0rInst <0xC8, "fmul $op">;
232 def MUL_FrST0 : FPrST0Inst <0xC8, "fmul {%st(0), $op|$op, %ST(0)}">;
233 def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp $op">;
234 def DIVR_FST0r : FPST0rInst <0xF8, "fdivr $op">;
235 def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r} {%st(0), $op|$op, %ST(0)}">;
236 def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p $op">;
237 def DIV_FST0r : FPST0rInst <0xF0, "fdiv $op">;
238 def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r} {%st(0), $op|$op, %ST(0)}">;
239 def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p $op">;
242 multiclass FPUnary<SDNode OpNode, bits<8> opcode, string asmstring> {
243 def _Fp32 : FpI<(ops RFP32:$dst, RFP32:$src), OneArgFPRW,
244 [(set RFP32:$dst, (OpNode RFP32:$src))]>;
245 def _Fp64 : FpI<(ops RFP64:$dst, RFP64:$src), OneArgFPRW,
246 [(set RFP64:$dst, (OpNode RFP64:$src))]>;
247 def _F : FPI<opcode, RawFrm, (ops), asmstring>, D9;
250 defm CHS : FPUnary<fneg, 0xE0, "fchs">;
251 defm ABS : FPUnary<fabs, 0xE1, "fabs">;
252 defm SQRT: FPUnary<fsqrt,0xFA, "fsqrt">;
253 defm SIN : FPUnary<fsin, 0xFE, "fsin">;
254 defm COS : FPUnary<fcos, 0xFF, "fcos">;
256 def TST_Fp32 : FpI<(ops RFP32:$src), OneArgFP,
258 def TST_Fp64 : FpI<(ops RFP64:$src), OneArgFP,
260 def TST_F : FPI<0xE4, RawFrm, (ops), "ftst">, D9;
262 // Floating point cmovs.
263 multiclass FPCMov<PatLeaf cc> {
264 def _Fp32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP,
265 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2,
267 def _Fp64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP,
268 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2,
271 let isTwoAddress = 1 in {
272 defm CMOVB : FPCMov<X86_COND_B>;
273 defm CMOVBE : FPCMov<X86_COND_BE>;
274 defm CMOVE : FPCMov<X86_COND_E>;
275 defm CMOVP : FPCMov<X86_COND_P>;
276 defm CMOVNB : FPCMov<X86_COND_AE>;
277 defm CMOVNBE: FPCMov<X86_COND_A>;
278 defm CMOVNE : FPCMov<X86_COND_NE>;
279 defm CMOVNP : FPCMov<X86_COND_NP>;
282 // These are not factored because there's no clean way to pass DA/DB.
283 def CMOVB_F : FPI<0xC0, AddRegFrm, (ops RST:$op),
284 "fcmovb {$op, %st(0)|%ST(0), $op}">, DA;
285 def CMOVBE_F : FPI<0xD0, AddRegFrm, (ops RST:$op),
286 "fcmovbe {$op, %st(0)|%ST(0), $op}">, DA;
287 def CMOVE_F : FPI<0xC8, AddRegFrm, (ops RST:$op),
288 "fcmove {$op, %st(0)|%ST(0), $op}">, DA;
289 def CMOVP_F : FPI<0xD8, AddRegFrm, (ops RST:$op),
290 "fcmovu {$op, %st(0)|%ST(0), $op}">, DA;
291 def CMOVNB_F : FPI<0xC0, AddRegFrm, (ops RST:$op),
292 "fcmovnb {$op, %st(0)|%ST(0), $op}">, DB;
293 def CMOVNBE_F: FPI<0xD0, AddRegFrm, (ops RST:$op),
294 "fcmovnbe {$op, %st(0)|%ST(0), $op}">, DB;
295 def CMOVNE_F : FPI<0xC8, AddRegFrm, (ops RST:$op),
296 "fcmovne {$op, %st(0)|%ST(0), $op}">, DB;
297 def CMOVNP_F : FPI<0xD8, AddRegFrm, (ops RST:$op),
298 "fcmovnu {$op, %st(0)|%ST(0), $op}">, DB;
300 // Floating point loads & stores.
301 def LD_Fp32m : FpI<(ops RFP32:$dst, f32mem:$src), ZeroArgFP,
302 [(set RFP32:$dst, (loadf32 addr:$src))]>;
303 def LD_Fp64m : FpI<(ops RFP64:$dst, f64mem:$src), ZeroArgFP,
304 [(set RFP64:$dst, (loadf64 addr:$src))]>;
305 def ILD_Fp16m32: FpI<(ops RFP32:$dst, i16mem:$src), ZeroArgFP,
306 [(set RFP32:$dst, (X86fild addr:$src, i16))]>;
307 def ILD_Fp32m32: FpI<(ops RFP32:$dst, i32mem:$src), ZeroArgFP,
308 [(set RFP32:$dst, (X86fild addr:$src, i32))]>;
309 def ILD_Fp64m32: FpI<(ops RFP32:$dst, i64mem:$src), ZeroArgFP,
310 [(set RFP32:$dst, (X86fild addr:$src, i64))]>;
311 def ILD_Fp16m64: FpI<(ops RFP64:$dst, i16mem:$src), ZeroArgFP,
312 [(set RFP64:$dst, (X86fild addr:$src, i16))]>;
313 def ILD_Fp32m64: FpI<(ops RFP64:$dst, i32mem:$src), ZeroArgFP,
314 [(set RFP64:$dst, (X86fild addr:$src, i32))]>;
315 def ILD_Fp64m64: FpI<(ops RFP64:$dst, i64mem:$src), ZeroArgFP,
316 [(set RFP64:$dst, (X86fild addr:$src, i64))]>;
318 def ST_Fp32m : FpI<(ops f32mem:$op, RFP32:$src), OneArgFP,
319 [(store RFP32:$src, addr:$op)]>;
320 def ST_Fp64m32 : FpI<(ops f32mem:$op, RFP64:$src), OneArgFP,
321 [(truncstoref32 RFP64:$src, addr:$op)]>;
322 def ST_Fp64m : FpI<(ops f64mem:$op, RFP64:$src), OneArgFP,
323 [(store RFP64:$src, addr:$op)]>;
325 def ST_FpP32m : FpI<(ops f32mem:$op, RFP32:$src), OneArgFP, []>;
326 def ST_FpP64m32 : FpI<(ops f32mem:$op, RFP64:$src), OneArgFP, []>;
327 def ST_FpP64m : FpI<(ops f64mem:$op, RFP64:$src), OneArgFP, []>;
328 def IST_Fp16m32 : FpI<(ops i16mem:$op, RFP32:$src), OneArgFP, []>;
329 def IST_Fp32m32 : FpI<(ops i32mem:$op, RFP32:$src), OneArgFP, []>;
330 def IST_Fp64m32 : FpI<(ops i64mem:$op, RFP32:$src), OneArgFP, []>;
331 def IST_Fp16m64 : FpI<(ops i16mem:$op, RFP64:$src), OneArgFP, []>;
332 def IST_Fp32m64 : FpI<(ops i32mem:$op, RFP64:$src), OneArgFP, []>;
333 def IST_Fp64m64 : FpI<(ops i64mem:$op, RFP64:$src), OneArgFP, []>;
335 def LD_F32m : FPI<0xD9, MRM0m, (ops f32mem:$src), "fld{s} $src">;
336 def LD_F64m : FPI<0xDD, MRM0m, (ops f64mem:$src), "fld{l} $src">;
337 def ILD_F16m : FPI<0xDF, MRM0m, (ops i16mem:$src), "fild{s} $src">;
338 def ILD_F32m : FPI<0xDB, MRM0m, (ops i32mem:$src), "fild{l} $src">;
339 def ILD_F64m : FPI<0xDF, MRM5m, (ops i64mem:$src), "fild{ll} $src">;
340 def ST_F32m : FPI<0xD9, MRM2m, (ops f32mem:$dst), "fst{s} $dst">;
341 def ST_F64m : FPI<0xDD, MRM2m, (ops f64mem:$dst), "fst{l} $dst">;
342 def ST_FP32m : FPI<0xD9, MRM3m, (ops f32mem:$dst), "fstp{s} $dst">;
343 def ST_FP64m : FPI<0xDD, MRM3m, (ops f64mem:$dst), "fstp{l} $dst">;
344 def IST_F16m : FPI<0xDF, MRM2m, (ops i16mem:$dst), "fist{s} $dst">;
345 def IST_F32m : FPI<0xDB, MRM2m, (ops i32mem:$dst), "fist{l} $dst">;
346 def IST_FP16m : FPI<0xDF, MRM3m, (ops i16mem:$dst), "fistp{s} $dst">;
347 def IST_FP32m : FPI<0xDB, MRM3m, (ops i32mem:$dst), "fistp{l} $dst">;
348 def IST_FP64m : FPI<0xDF, MRM7m, (ops i64mem:$dst), "fistp{ll} $dst">;
350 // FISTTP requires SSE3 even though it's a FPStack op.
351 def ISTT_Fp16m32 : FpI_<(ops i16mem:$op, RFP32:$src), OneArgFP,
352 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>,
354 def ISTT_Fp32m32 : FpI_<(ops i32mem:$op, RFP32:$src), OneArgFP,
355 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>,
357 def ISTT_Fp64m32 : FpI_<(ops i64mem:$op, RFP32:$src), OneArgFP,
358 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>,
360 def ISTT_Fp16m64 : FpI_<(ops i16mem:$op, RFP64:$src), OneArgFP,
361 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>,
363 def ISTT_Fp32m64 : FpI_<(ops i32mem:$op, RFP64:$src), OneArgFP,
364 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>,
366 def ISTT_Fp64m64 : FpI_<(ops i64mem:$op, RFP64:$src), OneArgFP,
367 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>,
370 def ISTT_FP16m : FPI<0xDF, MRM1m, (ops i16mem:$dst), "fisttp{s} $dst">;
371 def ISTT_FP32m : FPI<0xDB, MRM1m, (ops i32mem:$dst), "fisttp{l} $dst">;
372 def ISTT_FP64m : FPI<0xDD, MRM1m, (ops i64mem:$dst), "fisttp{ll} $dst">;
374 // FP Stack manipulation instructions.
375 def LD_Frr : FPI<0xC0, AddRegFrm, (ops RST:$op), "fld $op">, D9;
376 def ST_Frr : FPI<0xD0, AddRegFrm, (ops RST:$op), "fst $op">, DD;
377 def ST_FPrr : FPI<0xD8, AddRegFrm, (ops RST:$op), "fstp $op">, DD;
378 def XCH_F : FPI<0xC8, AddRegFrm, (ops RST:$op), "fxch $op">, D9;
380 // Floating point constant loads.
381 let isReMaterializable = 1 in {
382 def LD_Fp032 : FpI<(ops RFP32:$dst), ZeroArgFP,
383 [(set RFP32:$dst, fpimm0)]>;
384 def LD_Fp132 : FpI<(ops RFP32:$dst), ZeroArgFP,
385 [(set RFP32:$dst, fpimm1)]>;
386 def LD_Fp064 : FpI<(ops RFP64:$dst), ZeroArgFP,
387 [(set RFP64:$dst, fpimm0)]>;
388 def LD_Fp164 : FpI<(ops RFP64:$dst), ZeroArgFP,
389 [(set RFP64:$dst, fpimm1)]>;
392 def LD_F0 : FPI<0xEE, RawFrm, (ops), "fldz">, D9;
393 def LD_F1 : FPI<0xE8, RawFrm, (ops), "fld1">, D9;
396 // Floating point compares.
397 def UCOM_Fpr32 : FpI<(ops RFP32:$lhs, RFP32:$rhs), CompareFP,
398 []>; // FPSW = cmp ST(0) with ST(i)
399 def UCOM_FpIr32: FpI<(ops RFP32:$lhs, RFP32:$rhs), CompareFP,
400 [(X86cmp RFP32:$lhs, RFP32:$rhs)]>; // CC = ST(0) cmp ST(i)
401 def UCOM_Fpr64 : FpI<(ops RFP64:$lhs, RFP64:$rhs), CompareFP,
402 []>; // FPSW = cmp ST(0) with ST(i)
403 def UCOM_FpIr64: FpI<(ops RFP64:$lhs, RFP64:$rhs), CompareFP,
404 [(X86cmp RFP64:$lhs, RFP64:$rhs)]>; // CC = ST(0) cmp ST(i)
406 def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
408 "fucom $reg">, DD, Imp<[ST0],[]>;
409 def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
411 "fucomp $reg">, DD, Imp<[ST0],[]>;
412 def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
414 "fucompp">, DA, Imp<[ST0],[]>;
416 def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
418 "fucomi {$reg, %st(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
419 def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
421 "fucomip {$reg, %st(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>;
423 // Floating point flag ops.
424 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
425 (ops), "fnstsw", []>, DF, Imp<[],[AX]>;
427 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
428 (ops i16mem:$dst), "fnstcw $dst", []>;
429 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
430 (ops i16mem:$dst), "fldcw $dst", []>;
432 //===----------------------------------------------------------------------===//
433 // Non-Instruction Patterns
434 //===----------------------------------------------------------------------===//
436 // Required for RET of f32 / f64 values.
437 def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>;
438 def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>;
440 // Required for CALL which return f32 / f64 values.
441 def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>;
442 def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, RFP64:$src)>;
443 def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>;
445 // Floating point constant -0.0 and -1.0
446 def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStack]>;
447 def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStack]>;
448 def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStack]>;
449 def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStack]>;
451 // Used to conv. i64 to f64 since there isn't a SSE version.
452 def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>;
454 def : Pat<(extloadf32 addr:$src),
455 (MOV_Fp3264 (LD_Fp32m addr:$src))>, Requires<[FPStack]>;
456 def : Pat<(fextend RFP32:$src), (MOV_Fp3264 RFP32:$src)>, Requires<[FPStack]>;