1 //===-- X86InstrControl.td - Control Flow Instructions -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 jump, return, call, and related instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Control Flow Instructions.
18 // Return instructions.
20 // The X86retflag return instructions are variadic because we may add ST0 and
21 // ST1 arguments when returning values on the x87 stack.
22 let isTerminator = 1, isReturn = 1, isBarrier = 1,
23 hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
24 def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops),
25 "ret{l}", [(X86retflag 0)], IIC_RET>, OpSize32,
26 Requires<[Not64BitMode]>;
27 def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops),
28 "ret{q}", [(X86retflag 0)], IIC_RET>, OpSize32,
29 Requires<[In64BitMode]>;
30 def RETW : I <0xC3, RawFrm, (outs), (ins),
32 [], IIC_RET>, OpSize16;
33 def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
35 [(X86retflag timm:$amt)], IIC_RET_IMM>, OpSize32,
36 Requires<[Not64BitMode]>;
37 def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
39 [(X86retflag timm:$amt)], IIC_RET_IMM>, OpSize32,
40 Requires<[In64BitMode]>;
41 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
43 [], IIC_RET_IMM>, OpSize16;
44 def LRETL : I <0xCB, RawFrm, (outs), (ins),
45 "{l}ret{l|f}", [], IIC_RET>, OpSize32;
46 def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
47 "{l}ret{|f}q", [], IIC_RET>, Requires<[In64BitMode]>;
48 def LRETW : I <0xCB, RawFrm, (outs), (ins),
49 "{l}ret{w|f}", [], IIC_RET>, OpSize16;
50 def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
51 "{l}ret{l|f}\t$amt", [], IIC_RET>, OpSize32;
52 def LRETIQ : RIi16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
53 "{l}ret{|f}q\t$amt", [], IIC_RET>, Requires<[In64BitMode]>;
54 def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
55 "{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize16;
58 // Unconditional branches.
59 let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
60 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
61 "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>, OpSize32;
62 def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
63 "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>, OpSize16,
64 Requires<[In16BitMode]>;
65 let hasSideEffects = 0 in
66 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
67 "jmp\t$dst", [], IIC_JMP_REL>;
70 // Conditional Branches.
71 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in {
72 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
73 let hasSideEffects = 0 in
74 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, [],
76 def _2 : Ii16PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
77 [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>, OpSize16,
78 TB, Requires<[In16BitMode]>;
79 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
80 [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>, TB,
85 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
86 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
87 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
88 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
89 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
90 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
91 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
92 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
93 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
94 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
95 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
96 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
97 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
98 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
99 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
100 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
102 // jcx/jecx/jrcx instructions.
103 let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in {
104 // These are the 32-bit versions of this instruction for the asmparser. In
105 // 32-bit mode, the address size prefix is jcxz and the unprefixed version is
108 def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
109 "jcxz\t$dst", [], IIC_JCXZ>, AdSize16;
111 def JECXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
112 "jecxz\t$dst", [], IIC_JCXZ>, AdSize32;
115 def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
116 "jrcxz\t$dst", [], IIC_JCXZ>, AdSize64;
120 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
121 def JMP16r : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst",
122 [(brind GR16:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>,
123 OpSize16, Sched<[WriteJump]>;
124 def JMP16m : I<0xFF, MRM4m, (outs), (ins i16mem:$dst), "jmp{w}\t{*}$dst",
125 [(brind (loadi16 addr:$dst))], IIC_JMP_MEM>,
126 Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>;
128 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
129 [(brind GR32:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>,
130 OpSize32, Sched<[WriteJump]>;
131 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
132 [(brind (loadi32 addr:$dst))], IIC_JMP_MEM>,
133 Requires<[Not64BitMode]>, OpSize32, Sched<[WriteJumpLd]>;
135 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
136 [(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>,
138 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
139 [(brind (loadi64 addr:$dst))], IIC_JMP_MEM>,
140 Requires<[In64BitMode]>, Sched<[WriteJumpLd]>;
142 let Predicates = [Not64BitMode] in {
143 def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
144 (ins i16imm:$off, i16imm:$seg),
145 "ljmp{w}\t$seg, $off", [],
146 IIC_JMP_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
147 def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
148 (ins i32imm:$off, i16imm:$seg),
149 "ljmp{l}\t$seg, $off", [],
150 IIC_JMP_FAR_PTR>, OpSize32, Sched<[WriteJump]>;
152 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
153 "ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>,
156 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
157 "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize16,
158 Sched<[WriteJumpLd]>;
159 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
160 "ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize32,
161 Sched<[WriteJumpLd]>;
166 let SchedRW = [WriteJump] in {
167 def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", [], IIC_LOOP>;
168 def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", [], IIC_LOOPE>;
169 def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", [], IIC_LOOPNE>;
172 //===----------------------------------------------------------------------===//
173 // Call Instructions...
176 // All calls clobber the non-callee saved registers. ESP is marked as
177 // a use to prevent stack-pointer assignments that appear immediately
178 // before calls from potentially appearing dead. Uses for argument
179 // registers are added manually.
180 let Uses = [ESP] in {
181 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
182 (outs), (ins i32imm_pcrel:$dst),
183 "call{l}\t$dst", [], IIC_CALL_RI>, OpSize32,
184 Requires<[Not64BitMode]>, Sched<[WriteJump]>;
185 let hasSideEffects = 0 in
186 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
187 (outs), (ins i16imm_pcrel:$dst),
188 "call{w}\t$dst", [], IIC_CALL_RI>, OpSize16,
190 def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst),
191 "call{w}\t{*}$dst", [(X86call GR16:$dst)], IIC_CALL_RI>,
192 OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
193 def CALL16m : I<0xFF, MRM2m, (outs), (ins i16mem:$dst),
194 "call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))],
195 IIC_CALL_MEM>, OpSize16,
196 Requires<[Not64BitMode,FavorMemIndirectCall]>,
197 Sched<[WriteJumpLd]>;
198 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
199 "call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>,
200 OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
201 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),
202 "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))],
203 IIC_CALL_MEM>, OpSize32,
204 Requires<[Not64BitMode,FavorMemIndirectCall]>,
205 Sched<[WriteJumpLd]>;
207 let Predicates = [Not64BitMode] in {
208 def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
209 (ins i16imm:$off, i16imm:$seg),
210 "lcall{w}\t$seg, $off", [],
211 IIC_CALL_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
212 def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
213 (ins i32imm:$off, i16imm:$seg),
214 "lcall{l}\t$seg, $off", [],
215 IIC_CALL_FAR_PTR>, OpSize32, Sched<[WriteJump]>;
218 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
219 "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize16,
220 Sched<[WriteJumpLd]>;
221 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
222 "lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize32,
223 Sched<[WriteJumpLd]>;
229 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
230 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in
231 let Uses = [ESP] in {
232 def TCRETURNdi : PseudoI<(outs),
233 (ins i32imm_pcrel:$dst, i32imm:$offset), []>;
234 def TCRETURNri : PseudoI<(outs),
235 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>;
237 def TCRETURNmi : PseudoI<(outs),
238 (ins i32mem_TC:$dst, i32imm:$offset), []>;
240 // FIXME: The should be pseudo instructions that are lowered when going to
242 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
243 (ins i32imm_pcrel:$dst),
244 "jmp\t$dst # TAILCALL",
246 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
247 "", [], IIC_JMP_REG>; // FIXME: Remove encoding when JIT is dead.
249 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst),
250 "jmp{l}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;
254 //===----------------------------------------------------------------------===//
255 // Call Instructions...
258 // RSP is marked as a use to prevent stack-pointer assignments that appear
259 // immediately before calls from potentially appearing dead. Uses for argument
260 // registers are added manually.
261 let isCall = 1, Uses = [RSP], SchedRW = [WriteJump] in {
262 // NOTE: this pattern doesn't match "X86call imm", because we do not know
263 // that the offset between an arbitrary immediate and the call will fit in
264 // the 32-bit pcrel field that we have.
265 def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
266 (outs), (ins i64i32imm_pcrel:$dst),
267 "call{q}\t$dst", [], IIC_CALL_RI>, OpSize32,
268 Requires<[In64BitMode]>;
269 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst),
270 "call{q}\t{*}$dst", [(X86call GR64:$dst)],
272 Requires<[In64BitMode]>;
273 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst),
274 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))],
276 Requires<[In64BitMode,FavorMemIndirectCall]>;
278 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
279 "lcall{q}\t{*}$dst", [], IIC_CALL_FAR_MEM>;
282 let isCall = 1, isCodeGenOnly = 1 in
283 // __chkstk(MSVC): clobber R10, R11 and EFLAGS.
284 // ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP.
285 let Defs = [RAX, R10, R11, RSP, EFLAGS],
287 def W64ALLOCA : Ii32PCRel<0xE8, RawFrm,
288 (outs), (ins i64i32imm_pcrel:$dst),
289 "call{q}\t$dst", [], IIC_CALL_RI>,
290 Requires<[IsWin64]>, Sched<[WriteJump]>;
293 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
294 isCodeGenOnly = 1, Uses = [RSP], usesCustomInserter = 1,
295 SchedRW = [WriteJump] in {
296 def TCRETURNdi64 : PseudoI<(outs),
297 (ins i64i32imm_pcrel:$dst, i32imm:$offset),
299 def TCRETURNri64 : PseudoI<(outs),
300 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>;
302 def TCRETURNmi64 : PseudoI<(outs),
303 (ins i64mem_TC:$dst, i32imm:$offset), []>;
305 def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs),
306 (ins i64i32imm_pcrel:$dst),
307 "jmp\t$dst # TAILCALL", [], IIC_JMP_REL>;
308 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
309 "jmp{q}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;
312 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst),
313 "jmp{q}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;