1 //===- X86InstrArithmetic.td - Integer Arithmetic Instrs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the integer arithmetic instructions in the X86
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // LEA - Load Effective Address
18 let neverHasSideEffects = 1 in
19 def LEA16r : I<0x8D, MRMSrcMem,
20 (outs GR16:$dst), (ins i32mem:$src),
21 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
22 let isReMaterializable = 1 in
23 def LEA32r : I<0x8D, MRMSrcMem,
24 (outs GR32:$dst), (ins i32mem:$src),
25 "lea{l}\t{$src|$dst}, {$dst|$src}",
26 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
28 def LEA64_32r : I<0x8D, MRMSrcMem,
29 (outs GR32:$dst), (ins lea64_32mem:$src),
30 "lea{l}\t{$src|$dst}, {$dst|$src}",
31 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
33 let isReMaterializable = 1 in
34 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
35 "lea{q}\t{$src|$dst}, {$dst|$src}",
36 [(set GR64:$dst, lea64addr:$src)]>;
40 //===----------------------------------------------------------------------===//
41 // Fixed-Register Multiplication and Division Instructions.
44 // Extra precision multiplication
46 // AL is really implied by AX, but the registers in Defs must match the
47 // SDNode results (i8, i32).
48 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
49 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
50 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
51 // This probably ought to be moved to a def : Pat<> if the
52 // syntax can be accepted.
53 [(set AL, (mul AL, GR8:$src)),
54 (implicit EFLAGS)]>; // AL,AH = AL*GR8
56 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
57 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
59 []>, OpSize; // AX,DX = AX*GR16
61 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
62 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
64 []>; // EAX,EDX = EAX*GR32
65 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
66 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
67 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
69 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
70 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
72 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
73 // This probably ought to be moved to a def : Pat<> if the
74 // syntax can be accepted.
75 [(set AL, (mul AL, (loadi8 addr:$src))),
76 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
78 let mayLoad = 1, neverHasSideEffects = 1 in {
79 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
80 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
82 []>, OpSize; // AX,DX = AX*[mem16]
84 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
85 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
87 []>; // EAX,EDX = EAX*[mem32]
88 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
89 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
90 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
93 let neverHasSideEffects = 1 in {
94 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
95 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
97 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
98 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
99 OpSize; // AX,DX = AX*GR16
100 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
101 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
102 // EAX,EDX = EAX*GR32
103 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
104 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", []>;
105 // RAX,RDX = RAX*GR64
108 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
109 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
110 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
111 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
112 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
113 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
114 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
115 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
116 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
117 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
118 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
119 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
121 } // neverHasSideEffects
124 let Defs = [EFLAGS] in {
125 let Constraints = "$src1 = $dst" in {
127 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
128 // Register-Register Signed Integer Multiply
129 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
130 "imul{w}\t{$src2, $dst|$dst, $src2}",
131 [(set GR16:$dst, EFLAGS,
132 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
133 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
134 "imul{l}\t{$src2, $dst|$dst, $src2}",
135 [(set GR32:$dst, EFLAGS,
136 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
137 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
138 (ins GR64:$src1, GR64:$src2),
139 "imul{q}\t{$src2, $dst|$dst, $src2}",
140 [(set GR64:$dst, EFLAGS,
141 (X86smul_flag GR64:$src1, GR64:$src2))]>, TB;
144 // Register-Memory Signed Integer Multiply
145 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
146 (ins GR16:$src1, i16mem:$src2),
147 "imul{w}\t{$src2, $dst|$dst, $src2}",
148 [(set GR16:$dst, EFLAGS,
149 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
151 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
152 (ins GR32:$src1, i32mem:$src2),
153 "imul{l}\t{$src2, $dst|$dst, $src2}",
154 [(set GR32:$dst, EFLAGS,
155 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
156 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
157 (ins GR64:$src1, i64mem:$src2),
158 "imul{q}\t{$src2, $dst|$dst, $src2}",
159 [(set GR64:$dst, EFLAGS,
160 (X86smul_flag GR64:$src1, (load addr:$src2)))]>, TB;
161 } // Constraints = "$src1 = $dst"
165 // Suprisingly enough, these are not two address instructions!
166 let Defs = [EFLAGS] in {
167 // Register-Integer Signed Integer Multiply
168 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
169 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
170 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
171 [(set GR16:$dst, EFLAGS,
172 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
173 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
174 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
175 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
176 [(set GR16:$dst, EFLAGS,
177 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
179 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
180 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
181 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
182 [(set GR32:$dst, EFLAGS,
183 (X86smul_flag GR32:$src1, imm:$src2))]>;
184 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
185 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
186 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
187 [(set GR32:$dst, EFLAGS,
188 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
189 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
190 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
191 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
192 [(set GR64:$dst, EFLAGS,
193 (X86smul_flag GR64:$src1, i64immSExt32:$src2))]>;
194 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
195 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
196 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
197 [(set GR64:$dst, EFLAGS,
198 (X86smul_flag GR64:$src1, i64immSExt8:$src2))]>;
201 // Memory-Integer Signed Integer Multiply
202 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
203 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
204 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
205 [(set GR16:$dst, EFLAGS,
206 (X86smul_flag (load addr:$src1), imm:$src2))]>,
208 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
209 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
210 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
211 [(set GR16:$dst, EFLAGS,
212 (X86smul_flag (load addr:$src1),
213 i16immSExt8:$src2))]>, OpSize;
214 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
215 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
216 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
217 [(set GR32:$dst, EFLAGS,
218 (X86smul_flag (load addr:$src1), imm:$src2))]>;
219 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
220 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
221 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
222 [(set GR32:$dst, EFLAGS,
223 (X86smul_flag (load addr:$src1),
224 i32immSExt8:$src2))]>;
225 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
226 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
227 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 [(set GR64:$dst, EFLAGS,
229 (X86smul_flag (load addr:$src1),
230 i64immSExt32:$src2))]>;
231 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
232 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
233 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
234 [(set GR64:$dst, EFLAGS,
235 (X86smul_flag (load addr:$src1),
236 i64immSExt8:$src2))]>;
242 // unsigned division/remainder
243 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
244 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
246 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
247 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
248 "div{w}\t$src", []>, OpSize;
249 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
250 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
252 // RDX:RAX/r64 = RAX,RDX
253 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
254 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
258 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
259 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
261 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
262 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
263 "div{w}\t$src", []>, OpSize;
264 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
265 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
267 // RDX:RAX/[mem64] = RAX,RDX
268 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
269 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
273 // Signed division/remainder.
274 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
275 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
276 "idiv{b}\t$src", []>;
277 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
278 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
279 "idiv{w}\t$src", []>, OpSize;
280 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
281 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
282 "idiv{l}\t$src", []>;
283 // RDX:RAX/r64 = RAX,RDX
284 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
285 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
286 "idiv{q}\t$src", []>;
288 let mayLoad = 1, mayLoad = 1 in {
289 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
290 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
291 "idiv{b}\t$src", []>;
292 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
293 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
294 "idiv{w}\t$src", []>, OpSize;
295 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
296 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
297 "idiv{l}\t$src", []>;
298 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] = RAX,RDX
299 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
300 "idiv{q}\t$src", []>;
303 //===----------------------------------------------------------------------===//
304 // Two address Instructions.
307 // unary instructions
308 let CodeSize = 2 in {
309 let Defs = [EFLAGS] in {
310 let Constraints = "$src1 = $dst" in {
311 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
313 [(set GR8:$dst, (ineg GR8:$src1)),
315 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
317 [(set GR16:$dst, (ineg GR16:$src1)),
318 (implicit EFLAGS)]>, OpSize;
319 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
321 [(set GR32:$dst, (ineg GR32:$src1)),
323 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
324 [(set GR64:$dst, (ineg GR64:$src1)),
326 } // Constraints = "$src1 = $dst"
328 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
330 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
332 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
334 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
335 (implicit EFLAGS)]>, OpSize;
336 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
338 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
340 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
341 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
346 // Note: NOT does not set EFLAGS!
348 let Constraints = "$src1 = $dst" in {
349 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
350 let AddedComplexity = 15 in {
351 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
353 [(set GR8:$dst, (not GR8:$src1))]>;
354 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
356 [(set GR16:$dst, (not GR16:$src1))]>, OpSize;
357 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
359 [(set GR32:$dst, (not GR32:$src1))]>;
360 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",
361 [(set GR64:$dst, (not GR64:$src1))]>;
363 } // Constraints = "$src1 = $dst"
365 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
367 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
368 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
370 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
371 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
373 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
374 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
375 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
378 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
379 let Defs = [EFLAGS] in {
380 let Constraints = "$src1 = $dst" in {
382 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
384 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>;
386 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
387 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
389 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
390 OpSize, Requires<[In32BitMode]>;
391 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
393 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
394 Requires<[In32BitMode]>;
395 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
396 [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))]>;
397 } // isConvertibleToThreeAddress = 1, CodeSize = 1
400 // In 64-bit mode, single byte INC and DEC cannot be encoded.
401 let isConvertibleToThreeAddress = 1, CodeSize = 2 in {
402 // Can transform into LEA.
403 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
405 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
406 OpSize, Requires<[In64BitMode]>;
407 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
409 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
410 Requires<[In64BitMode]>;
411 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
413 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
414 OpSize, Requires<[In64BitMode]>;
415 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
417 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
418 Requires<[In64BitMode]>;
419 } // isConvertibleToThreeAddress = 1, CodeSize = 2
421 } // Constraints = "$src1 = $dst"
423 let CodeSize = 2 in {
424 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
425 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
427 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
428 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
430 OpSize, Requires<[In32BitMode]>;
431 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
432 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
434 Requires<[In32BitMode]>;
435 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
436 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
439 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
440 // how to unfold them.
441 // FIXME: What is this for??
442 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
443 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
445 OpSize, Requires<[In64BitMode]>;
446 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
447 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
449 Requires<[In64BitMode]>;
450 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
451 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
453 OpSize, Requires<[In64BitMode]>;
454 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
455 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
457 Requires<[In64BitMode]>;
460 let Constraints = "$src1 = $dst" in {
462 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
464 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>;
465 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
466 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
468 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
469 OpSize, Requires<[In32BitMode]>;
470 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
472 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
473 Requires<[In32BitMode]>;
474 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst",
475 [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))]>;
477 } // Constraints = "$src1 = $dst"
480 let CodeSize = 2 in {
481 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
482 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
484 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
485 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
487 OpSize, Requires<[In32BitMode]>;
488 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
489 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
491 Requires<[In32BitMode]>;
492 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
493 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
499 /// X86TypeInfo - This is a bunch of information that describes relevant X86
500 /// information about value types. For example, it can tell you what the
501 /// register class and preferred load to use.
502 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
503 PatFrag loadnode, X86MemOperand memoperand,
504 ImmType immkind, Operand immoperand,
505 SDPatternOperator immoperator,
506 bit hasOddOpcode, bit hasOpSizePrefix, bit hasREX_WPrefix> {
507 /// VT - This is the value type itself.
510 /// InstrSuffix - This is the suffix used on instructions with this type. For
511 /// example, i8 -> "b", i16 -> "w", i32 -> "l", i64 -> "q".
512 string InstrSuffix = instrsuffix;
514 /// RegClass - This is the register class associated with this type. For
515 /// example, i8 -> GR8, i16 -> GR16, i32 -> GR32, i64 -> GR64.
516 RegisterClass RegClass = regclass;
518 /// LoadNode - This is the load node associated with this type. For
519 /// example, i8 -> loadi8, i16 -> loadi16, i32 -> loadi32, i64 -> loadi64.
520 PatFrag LoadNode = loadnode;
522 /// MemOperand - This is the memory operand associated with this type. For
523 /// example, i8 -> i8mem, i16 -> i16mem, i32 -> i32mem, i64 -> i64mem.
524 X86MemOperand MemOperand = memoperand;
526 /// ImmEncoding - This is the encoding of an immediate of this type. For
527 /// example, i8 -> Imm8, i16 -> Imm16, i32 -> Imm32. Note that i64 -> Imm32
528 /// since the immediate fields of i64 instructions is a 32-bit sign extended
530 ImmType ImmEncoding = immkind;
532 /// ImmOperand - This is the operand kind of an immediate of this type. For
533 /// example, i8 -> i8imm, i16 -> i16imm, i32 -> i32imm. Note that i64 ->
534 /// i64i32imm since the immediate fields of i64 instructions is a 32-bit sign
536 Operand ImmOperand = immoperand;
538 /// ImmOperator - This is the operator that should be used to match an
539 /// immediate of this kind in a pattern (e.g. imm, or i64immSExt32).
540 SDPatternOperator ImmOperator = immoperator;
542 /// HasOddOpcode - This bit is true if the instruction should have an odd (as
543 /// opposed to even) opcode. Operations on i8 are usually even, operations on
544 /// other datatypes are odd.
545 bit HasOddOpcode = hasOddOpcode;
547 /// HasOpSizePrefix - This bit is set to true if the instruction should have
548 /// the 0x66 operand size prefix. This is set for i16 types.
549 bit HasOpSizePrefix = hasOpSizePrefix;
551 /// HasREX_WPrefix - This bit is set to true if the instruction should have
552 /// the 0x40 REX prefix. This is set for i64 types.
553 bit HasREX_WPrefix = hasREX_WPrefix;
556 def Xi8 : X86TypeInfo<i8 , "b", GR8 , loadi8 , i8mem , Imm8 , i8imm ,
558 def Xi16 : X86TypeInfo<i16, "w", GR16, loadi16, i16mem, Imm16, i16imm,
560 def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem, Imm32, i32imm,
562 def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem, Imm32, i64i32imm,
563 i64immSExt32, 1, 0, 1>;
565 /// ITy - This instruction base class takes the type info for the instruction.
567 /// 1. Concatenates together the instruction mnemonic with the appropriate
568 /// suffix letter, a tab, and the arguments.
569 /// 2. Infers whether the instruction should have a 0x66 prefix byte.
570 /// 3. Infers whether the instruction should have a 0x40 REX_W prefix.
571 /// 4. Infers whether the low bit of the opcode should be 0 (for i8 operations)
572 /// or 1 (for i16,i32,i64 operations).
573 class ITy<bits<8> opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins,
574 string mnemonic, string args, list<dag> pattern>
575 : I<{opcode{7}, opcode{6}, opcode{5}, opcode{4},
576 opcode{3}, opcode{2}, opcode{1}, typeinfo.HasOddOpcode },
578 !strconcat(mnemonic, "{", typeinfo.InstrSuffix, "}\t", args), pattern> {
580 // Infer instruction prefixes from type info.
581 let hasOpSizePrefix = typeinfo.HasOpSizePrefix;
582 let hasREX_WPrefix = typeinfo.HasREX_WPrefix;
586 class BinOpRR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
588 : ITy<opcode, MRMDestReg, typeinfo,
589 (outs typeinfo.RegClass:$dst),
590 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
591 mnemonic, "{$src2, $dst|$dst, $src2}",
592 [(set typeinfo.RegClass:$dst, EFLAGS,
593 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
595 class BinOpRR_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo>
596 : ITy<opcode, MRMSrcReg, typeinfo,
597 (outs typeinfo.RegClass:$dst),
598 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
599 mnemonic, "{$src2, $dst|$dst, $src2}", []> {
600 // The disassembler should know about this, but not the asmparser.
601 let isCodeGenOnly = 1;
604 class BinOpRM<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
606 : ITy<opcode, MRMSrcMem, typeinfo,
607 (outs typeinfo.RegClass:$dst),
608 (ins typeinfo.RegClass:$src1, typeinfo.MemOperand:$src2),
609 mnemonic, "{$src2, $dst|$dst, $src2}",
610 [(set typeinfo.RegClass:$dst, EFLAGS,
611 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
613 class BinOpRI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
614 SDNode opnode, Format f>
615 : ITy<opcode, f, typeinfo,
616 (outs typeinfo.RegClass:$dst),
617 (ins typeinfo.RegClass:$src1, typeinfo.ImmOperand:$src2),
618 mnemonic, "{$src2, $dst|$dst, $src2}",
619 [(set typeinfo.RegClass:$dst, EFLAGS,
620 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]> {
621 let ImmT = typeinfo.ImmEncoding;
626 // Logical operators.
627 let Defs = [EFLAGS] in {
628 let Constraints = "$src1 = $dst" in {
630 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
631 def AND8rr : BinOpRR<0x20, "and", Xi8 , X86and_flag>;
632 def AND16rr : BinOpRR<0x20, "and", Xi16, X86and_flag>;
633 def AND32rr : BinOpRR<0x20, "and", Xi32, X86and_flag>;
634 def AND64rr : BinOpRR<0x20, "and", Xi64, X86and_flag>;
638 // AND instructions with the destination register in REG and the source register
639 // in R/M. Included for the disassembler.
641 def AND8rr_REV : BinOpRR_Rev<0x22, "and", Xi8>;
642 def AND16rr_REV : BinOpRR_Rev<0x22, "and", Xi16>;
643 def AND32rr_REV : BinOpRR_Rev<0x22, "and", Xi32>;
644 def AND64rr_REV : BinOpRR_Rev<0x22, "and", Xi64>;
646 def AND8rm : BinOpRM<0x22, "and", Xi8 , X86and_flag>;
647 def AND16rm : BinOpRM<0x22, "and", Xi16, X86and_flag>;
648 def AND32rm : BinOpRM<0x22, "and", Xi32, X86and_flag>;
649 def AND64rm : BinOpRM<0x22, "and", Xi64, X86and_flag>;
651 def AND8ri : BinOpRI<0x80, "and", Xi8 , X86and_flag, MRM4r>;
652 def AND16ri : BinOpRI<0x80, "and", Xi16, X86and_flag, MRM4r>;
653 def AND32ri : BinOpRI<0x80, "and", Xi32, X86and_flag, MRM4r>;
654 def AND64ri32: BinOpRI<0x80, "and", Xi64, X86and_flag, MRM4r>;
656 def AND16ri8 : Ii8<0x83, MRM4r,
657 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
658 "and{w}\t{$src2, $dst|$dst, $src2}",
659 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
660 i16immSExt8:$src2))]>,
662 def AND32ri8 : Ii8<0x83, MRM4r,
663 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
664 "and{l}\t{$src2, $dst|$dst, $src2}",
665 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
666 i32immSExt8:$src2))]>;
667 def AND64ri8 : RIi8<0x83, MRM4r,
668 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
669 "and{q}\t{$src2, $dst|$dst, $src2}",
670 [(set GR64:$dst, EFLAGS,
671 (X86and_flag GR64:$src1, i64immSExt8:$src2))]>;
672 } // Constraints = "$src1 = $dst"
674 def AND8mr : I<0x20, MRMDestMem,
675 (outs), (ins i8mem :$dst, GR8 :$src),
676 "and{b}\t{$src, $dst|$dst, $src}",
677 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
679 def AND16mr : I<0x21, MRMDestMem,
680 (outs), (ins i16mem:$dst, GR16:$src),
681 "and{w}\t{$src, $dst|$dst, $src}",
682 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
685 def AND32mr : I<0x21, MRMDestMem,
686 (outs), (ins i32mem:$dst, GR32:$src),
687 "and{l}\t{$src, $dst|$dst, $src}",
688 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
690 def AND64mr : RI<0x21, MRMDestMem,
691 (outs), (ins i64mem:$dst, GR64:$src),
692 "and{q}\t{$src, $dst|$dst, $src}",
693 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
696 def AND8mi : Ii8<0x80, MRM4m,
697 (outs), (ins i8mem :$dst, i8imm :$src),
698 "and{b}\t{$src, $dst|$dst, $src}",
699 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
701 def AND16mi : Ii16<0x81, MRM4m,
702 (outs), (ins i16mem:$dst, i16imm:$src),
703 "and{w}\t{$src, $dst|$dst, $src}",
704 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
707 def AND32mi : Ii32<0x81, MRM4m,
708 (outs), (ins i32mem:$dst, i32imm:$src),
709 "and{l}\t{$src, $dst|$dst, $src}",
710 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
712 def AND64mi32 : RIi32<0x81, MRM4m,
713 (outs), (ins i64mem:$dst, i64i32imm:$src),
714 "and{q}\t{$src, $dst|$dst, $src}",
715 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
718 def AND16mi8 : Ii8<0x83, MRM4m,
719 (outs), (ins i16mem:$dst, i16i8imm :$src),
720 "and{w}\t{$src, $dst|$dst, $src}",
721 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
724 def AND32mi8 : Ii8<0x83, MRM4m,
725 (outs), (ins i32mem:$dst, i32i8imm :$src),
726 "and{l}\t{$src, $dst|$dst, $src}",
727 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
729 def AND64mi8 : RIi8<0x83, MRM4m,
730 (outs), (ins i64mem:$dst, i64i8imm :$src),
731 "and{q}\t{$src, $dst|$dst, $src}",
732 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
735 // FIXME: Implicitly modifiers AL.
736 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
737 "and{b}\t{$src, %al|%al, $src}", []>;
738 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
739 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
740 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
741 "and{l}\t{$src, %eax|%eax, $src}", []>;
742 def AND64i32 : RIi32<0x25, RawFrm, (outs), (ins i64i32imm:$src),
743 "and{q}\t{$src, %rax|%rax, $src}", []>;
745 let Constraints = "$src1 = $dst" in {
747 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
748 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
749 (ins GR8 :$src1, GR8 :$src2),
750 "or{b}\t{$src2, $dst|$dst, $src2}",
751 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
752 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
753 (ins GR16:$src1, GR16:$src2),
754 "or{w}\t{$src2, $dst|$dst, $src2}",
755 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
757 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
758 (ins GR32:$src1, GR32:$src2),
759 "or{l}\t{$src2, $dst|$dst, $src2}",
760 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
761 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst),
762 (ins GR64:$src1, GR64:$src2),
763 "or{q}\t{$src2, $dst|$dst, $src2}",
764 [(set GR64:$dst, EFLAGS,
765 (X86or_flag GR64:$src1, GR64:$src2))]>;
768 // OR instructions with the destination register in REG and the source register
769 // in R/M. Included for the disassembler.
770 let isCodeGenOnly = 1 in {
771 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
772 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
773 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
774 (ins GR16:$src1, GR16:$src2),
775 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
776 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
777 (ins GR32:$src1, GR32:$src2),
778 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
779 def OR64rr_REV : RI<0x0B, MRMSrcReg, (outs GR64:$dst),
780 (ins GR64:$src1, GR64:$src2),
781 "or{q}\t{$src2, $dst|$dst, $src2}", []>;
784 def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
785 (ins GR8 :$src1, i8mem :$src2),
786 "or{b}\t{$src2, $dst|$dst, $src2}",
787 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
788 (load addr:$src2)))]>;
789 def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
790 (ins GR16:$src1, i16mem:$src2),
791 "or{w}\t{$src2, $dst|$dst, $src2}",
792 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
793 (load addr:$src2)))]>,
795 def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
796 (ins GR32:$src1, i32mem:$src2),
797 "or{l}\t{$src2, $dst|$dst, $src2}",
798 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
799 (load addr:$src2)))]>;
800 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst),
801 (ins GR64:$src1, i64mem:$src2),
802 "or{q}\t{$src2, $dst|$dst, $src2}",
803 [(set GR64:$dst, EFLAGS,
804 (X86or_flag GR64:$src1, (load addr:$src2)))]>;
806 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
807 (ins GR8 :$src1, i8imm:$src2),
808 "or{b}\t{$src2, $dst|$dst, $src2}",
809 [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
810 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
811 (ins GR16:$src1, i16imm:$src2),
812 "or{w}\t{$src2, $dst|$dst, $src2}",
813 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
814 imm:$src2))]>, OpSize;
815 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
816 (ins GR32:$src1, i32imm:$src2),
817 "or{l}\t{$src2, $dst|$dst, $src2}",
818 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
820 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst),
821 (ins GR64:$src1, i64i32imm:$src2),
822 "or{q}\t{$src2, $dst|$dst, $src2}",
823 [(set GR64:$dst, EFLAGS,
824 (X86or_flag GR64:$src1, i64immSExt32:$src2))]>;
826 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
827 (ins GR16:$src1, i16i8imm:$src2),
828 "or{w}\t{$src2, $dst|$dst, $src2}",
829 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
830 i16immSExt8:$src2))]>, OpSize;
831 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
832 (ins GR32:$src1, i32i8imm:$src2),
833 "or{l}\t{$src2, $dst|$dst, $src2}",
834 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
835 i32immSExt8:$src2))]>;
836 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst),
837 (ins GR64:$src1, i64i8imm:$src2),
838 "or{q}\t{$src2, $dst|$dst, $src2}",
839 [(set GR64:$dst, EFLAGS,
840 (X86or_flag GR64:$src1, i64immSExt8:$src2))]>;
841 } // Constraints = "$src1 = $dst"
843 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
844 "or{b}\t{$src, $dst|$dst, $src}",
845 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
847 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
848 "or{w}\t{$src, $dst|$dst, $src}",
849 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
850 (implicit EFLAGS)]>, OpSize;
851 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
852 "or{l}\t{$src, $dst|$dst, $src}",
853 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
855 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
856 "or{q}\t{$src, $dst|$dst, $src}",
857 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
860 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
861 "or{b}\t{$src, $dst|$dst, $src}",
862 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
864 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
865 "or{w}\t{$src, $dst|$dst, $src}",
866 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
869 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
870 "or{l}\t{$src, $dst|$dst, $src}",
871 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
873 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
874 "or{q}\t{$src, $dst|$dst, $src}",
875 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
878 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
879 "or{w}\t{$src, $dst|$dst, $src}",
880 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
883 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
884 "or{l}\t{$src, $dst|$dst, $src}",
885 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
887 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
888 "or{q}\t{$src, $dst|$dst, $src}",
889 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
892 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
893 "or{b}\t{$src, %al|%al, $src}", []>;
894 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
895 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
896 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
897 "or{l}\t{$src, %eax|%eax, $src}", []>;
898 def OR64i32 : RIi32<0x0D, RawFrm, (outs), (ins i64i32imm:$src),
899 "or{q}\t{$src, %rax|%rax, $src}", []>;
902 let Constraints = "$src1 = $dst" in {
904 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
905 def XOR8rr : I<0x30, MRMDestReg,
906 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
907 "xor{b}\t{$src2, $dst|$dst, $src2}",
908 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
910 def XOR16rr : I<0x31, MRMDestReg,
911 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
912 "xor{w}\t{$src2, $dst|$dst, $src2}",
913 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
914 GR16:$src2))]>, OpSize;
915 def XOR32rr : I<0x31, MRMDestReg,
916 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
917 "xor{l}\t{$src2, $dst|$dst, $src2}",
918 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
920 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst),
921 (ins GR64:$src1, GR64:$src2),
922 "xor{q}\t{$src2, $dst|$dst, $src2}",
923 [(set GR64:$dst, EFLAGS,
924 (X86xor_flag GR64:$src1, GR64:$src2))]>;
925 } // isCommutable = 1
927 // XOR instructions with the destination register in REG and the source register
928 // in R/M. Included for the disassembler.
929 let isCodeGenOnly = 1 in {
930 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
931 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
932 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
933 (ins GR16:$src1, GR16:$src2),
934 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
935 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
936 (ins GR32:$src1, GR32:$src2),
937 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
938 def XOR64rr_REV : RI<0x33, MRMSrcReg, (outs GR64:$dst),
939 (ins GR64:$src1, GR64:$src2),
940 "xor{q}\t{$src2, $dst|$dst, $src2}", []>;
943 def XOR8rm : I<0x32, MRMSrcMem,
944 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
945 "xor{b}\t{$src2, $dst|$dst, $src2}",
946 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
947 (load addr:$src2)))]>;
948 def XOR16rm : I<0x33, MRMSrcMem,
949 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
950 "xor{w}\t{$src2, $dst|$dst, $src2}",
951 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
952 (load addr:$src2)))]>,
954 def XOR32rm : I<0x33, MRMSrcMem,
955 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
956 "xor{l}\t{$src2, $dst|$dst, $src2}",
957 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
958 (load addr:$src2)))]>;
959 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst),
960 (ins GR64:$src1, i64mem:$src2),
961 "xor{q}\t{$src2, $dst|$dst, $src2}",
962 [(set GR64:$dst, EFLAGS,
963 (X86xor_flag GR64:$src1, (load addr:$src2)))]>;
965 def XOR8ri : Ii8<0x80, MRM6r,
966 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
967 "xor{b}\t{$src2, $dst|$dst, $src2}",
968 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
969 def XOR16ri : Ii16<0x81, MRM6r,
970 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
971 "xor{w}\t{$src2, $dst|$dst, $src2}",
972 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
973 imm:$src2))]>, OpSize;
974 def XOR32ri : Ii32<0x81, MRM6r,
975 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
976 "xor{l}\t{$src2, $dst|$dst, $src2}",
977 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
979 def XOR64ri32 : RIi32<0x81, MRM6r,
980 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
981 "xor{q}\t{$src2, $dst|$dst, $src2}",
982 [(set GR64:$dst, EFLAGS,
983 (X86xor_flag GR64:$src1, i64immSExt32:$src2))]>;
985 def XOR16ri8 : Ii8<0x83, MRM6r,
986 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
987 "xor{w}\t{$src2, $dst|$dst, $src2}",
988 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
989 i16immSExt8:$src2))]>,
991 def XOR32ri8 : Ii8<0x83, MRM6r,
992 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
993 "xor{l}\t{$src2, $dst|$dst, $src2}",
994 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
995 i32immSExt8:$src2))]>;
996 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst),
997 (ins GR64:$src1, i64i8imm:$src2),
998 "xor{q}\t{$src2, $dst|$dst, $src2}",
999 [(set GR64:$dst, EFLAGS,
1000 (X86xor_flag GR64:$src1, i64immSExt8:$src2))]>;
1001 } // Constraints = "$src1 = $dst"
1004 def XOR8mr : I<0x30, MRMDestMem,
1005 (outs), (ins i8mem :$dst, GR8 :$src),
1006 "xor{b}\t{$src, $dst|$dst, $src}",
1007 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
1008 (implicit EFLAGS)]>;
1009 def XOR16mr : I<0x31, MRMDestMem,
1010 (outs), (ins i16mem:$dst, GR16:$src),
1011 "xor{w}\t{$src, $dst|$dst, $src}",
1012 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
1013 (implicit EFLAGS)]>,
1015 def XOR32mr : I<0x31, MRMDestMem,
1016 (outs), (ins i32mem:$dst, GR32:$src),
1017 "xor{l}\t{$src, $dst|$dst, $src}",
1018 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
1019 (implicit EFLAGS)]>;
1020 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1021 "xor{q}\t{$src, $dst|$dst, $src}",
1022 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
1023 (implicit EFLAGS)]>;
1025 def XOR8mi : Ii8<0x80, MRM6m,
1026 (outs), (ins i8mem :$dst, i8imm :$src),
1027 "xor{b}\t{$src, $dst|$dst, $src}",
1028 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
1029 (implicit EFLAGS)]>;
1030 def XOR16mi : Ii16<0x81, MRM6m,
1031 (outs), (ins i16mem:$dst, i16imm:$src),
1032 "xor{w}\t{$src, $dst|$dst, $src}",
1033 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
1034 (implicit EFLAGS)]>,
1036 def XOR32mi : Ii32<0x81, MRM6m,
1037 (outs), (ins i32mem:$dst, i32imm:$src),
1038 "xor{l}\t{$src, $dst|$dst, $src}",
1039 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
1040 (implicit EFLAGS)]>;
1041 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1042 "xor{q}\t{$src, $dst|$dst, $src}",
1043 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1044 (implicit EFLAGS)]>;
1046 def XOR16mi8 : Ii8<0x83, MRM6m,
1047 (outs), (ins i16mem:$dst, i16i8imm :$src),
1048 "xor{w}\t{$src, $dst|$dst, $src}",
1049 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
1050 (implicit EFLAGS)]>,
1052 def XOR32mi8 : Ii8<0x83, MRM6m,
1053 (outs), (ins i32mem:$dst, i32i8imm :$src),
1054 "xor{l}\t{$src, $dst|$dst, $src}",
1055 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
1056 (implicit EFLAGS)]>;
1057 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
1058 "xor{q}\t{$src, $dst|$dst, $src}",
1059 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
1060 (implicit EFLAGS)]>;
1062 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
1063 "xor{b}\t{$src, %al|%al, $src}", []>;
1064 def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
1065 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1066 def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
1067 "xor{l}\t{$src, %eax|%eax, $src}", []>;
1068 def XOR64i32 : RIi32<0x35, RawFrm, (outs), (ins i64i32imm:$src),
1069 "xor{q}\t{$src, %rax|%rax, $src}", []>;
1070 } // Defs = [EFLAGS]
1074 let Defs = [EFLAGS] in {
1075 let Constraints = "$src1 = $dst" in {
1076 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1077 // Register-Register Addition
1078 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
1079 (ins GR8 :$src1, GR8 :$src2),
1080 "add{b}\t{$src2, $dst|$dst, $src2}",
1081 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
1083 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1084 // Register-Register Addition
1085 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
1086 (ins GR16:$src1, GR16:$src2),
1087 "add{w}\t{$src2, $dst|$dst, $src2}",
1088 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
1089 GR16:$src2))]>, OpSize;
1090 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
1091 (ins GR32:$src1, GR32:$src2),
1092 "add{l}\t{$src2, $dst|$dst, $src2}",
1093 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
1095 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst),
1096 (ins GR64:$src1, GR64:$src2),
1097 "add{q}\t{$src2, $dst|$dst, $src2}",
1098 [(set GR64:$dst, EFLAGS,
1099 (X86add_flag GR64:$src1, GR64:$src2))]>;
1100 } // end isConvertibleToThreeAddress
1101 } // end isCommutable
1103 // These are alternate spellings for use by the disassembler, we mark them as
1104 // code gen only to ensure they aren't matched by the assembler.
1105 let isCodeGenOnly = 1 in {
1106 def ADD8rr_alt: I<0x02, MRMSrcReg,
1107 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1108 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
1109 def ADD16rr_alt: I<0x03, MRMSrcReg,
1110 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1111 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1112 def ADD32rr_alt: I<0x03, MRMSrcReg,
1113 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1114 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
1115 def ADD64rr_alt : RI<0x03, MRMSrcReg,
1116 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1117 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
1120 // Register-Memory Addition
1121 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
1122 (ins GR8 :$src1, i8mem :$src2),
1123 "add{b}\t{$src2, $dst|$dst, $src2}",
1124 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
1125 (load addr:$src2)))]>;
1126 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
1127 (ins GR16:$src1, i16mem:$src2),
1128 "add{w}\t{$src2, $dst|$dst, $src2}",
1129 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
1130 (load addr:$src2)))]>, OpSize;
1131 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
1132 (ins GR32:$src1, i32mem:$src2),
1133 "add{l}\t{$src2, $dst|$dst, $src2}",
1134 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
1135 (load addr:$src2)))]>;
1136 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst),
1137 (ins GR64:$src1, i64mem:$src2),
1138 "add{q}\t{$src2, $dst|$dst, $src2}",
1139 [(set GR64:$dst, EFLAGS,
1140 (X86add_flag GR64:$src1, (load addr:$src2)))]>;
1142 // Register-Integer Addition
1143 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1144 "add{b}\t{$src2, $dst|$dst, $src2}",
1145 [(set GR8:$dst, EFLAGS,
1146 (X86add_flag GR8:$src1, imm:$src2))]>;
1148 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1149 // Register-Integer Addition
1150 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
1151 (ins GR16:$src1, i16imm:$src2),
1152 "add{w}\t{$src2, $dst|$dst, $src2}",
1153 [(set GR16:$dst, EFLAGS,
1154 (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
1155 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
1156 (ins GR32:$src1, i32imm:$src2),
1157 "add{l}\t{$src2, $dst|$dst, $src2}",
1158 [(set GR32:$dst, EFLAGS,
1159 (X86add_flag GR32:$src1, imm:$src2))]>;
1160 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
1161 (ins GR16:$src1, i16i8imm:$src2),
1162 "add{w}\t{$src2, $dst|$dst, $src2}",
1163 [(set GR16:$dst, EFLAGS,
1164 (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1165 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
1166 (ins GR32:$src1, i32i8imm:$src2),
1167 "add{l}\t{$src2, $dst|$dst, $src2}",
1168 [(set GR32:$dst, EFLAGS,
1169 (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
1170 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst),
1171 (ins GR64:$src1, i64i8imm:$src2),
1172 "add{q}\t{$src2, $dst|$dst, $src2}",
1173 [(set GR64:$dst, EFLAGS,
1174 (X86add_flag GR64:$src1, i64immSExt8:$src2))]>;
1175 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst),
1176 (ins GR64:$src1, i64i32imm:$src2),
1177 "add{q}\t{$src2, $dst|$dst, $src2}",
1178 [(set GR64:$dst, EFLAGS,
1179 (X86add_flag GR64:$src1, i64immSExt32:$src2))]>;
1181 } // Constraints = "$src1 = $dst"
1183 // Memory-Register Addition
1184 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
1185 "add{b}\t{$src2, $dst|$dst, $src2}",
1186 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
1187 (implicit EFLAGS)]>;
1188 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1189 "add{w}\t{$src2, $dst|$dst, $src2}",
1190 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
1191 (implicit EFLAGS)]>, OpSize;
1192 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1193 "add{l}\t{$src2, $dst|$dst, $src2}",
1194 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
1195 (implicit EFLAGS)]>;
1196 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1197 "add{q}\t{$src2, $dst|$dst, $src2}",
1198 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
1199 (implicit EFLAGS)]>;
1200 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
1201 "add{b}\t{$src2, $dst|$dst, $src2}",
1202 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
1203 (implicit EFLAGS)]>;
1204 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
1205 "add{w}\t{$src2, $dst|$dst, $src2}",
1206 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
1207 (implicit EFLAGS)]>, OpSize;
1208 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
1209 "add{l}\t{$src2, $dst|$dst, $src2}",
1210 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
1211 (implicit EFLAGS)]>;
1212 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
1213 "add{q}\t{$src2, $dst|$dst, $src2}",
1214 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
1215 (implicit EFLAGS)]>;
1216 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1217 "add{w}\t{$src2, $dst|$dst, $src2}",
1218 [(store (add (load addr:$dst), i16immSExt8:$src2),
1220 (implicit EFLAGS)]>, OpSize;
1221 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1222 "add{l}\t{$src2, $dst|$dst, $src2}",
1223 [(store (add (load addr:$dst), i32immSExt8:$src2),
1225 (implicit EFLAGS)]>;
1226 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1227 "add{q}\t{$src2, $dst|$dst, $src2}",
1228 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
1229 (implicit EFLAGS)]>;
1232 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
1233 "add{b}\t{$src, %al|%al, $src}", []>;
1234 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
1235 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1236 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
1237 "add{l}\t{$src, %eax|%eax, $src}", []>;
1238 def ADD64i32 : RIi32<0x05, RawFrm, (outs), (ins i64i32imm:$src),
1239 "add{q}\t{$src, %rax|%rax, $src}", []>;
1241 let Uses = [EFLAGS] in {
1242 let Constraints = "$src1 = $dst" in {
1243 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1244 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1245 "adc{b}\t{$src2, $dst|$dst, $src2}",
1246 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
1247 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
1248 (ins GR16:$src1, GR16:$src2),
1249 "adc{w}\t{$src2, $dst|$dst, $src2}",
1250 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
1251 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
1252 (ins GR32:$src1, GR32:$src2),
1253 "adc{l}\t{$src2, $dst|$dst, $src2}",
1254 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
1255 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst),
1256 (ins GR64:$src1, GR64:$src2),
1257 "adc{q}\t{$src2, $dst|$dst, $src2}",
1258 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
1261 let isCodeGenOnly = 1 in {
1262 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1263 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
1264 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
1265 (ins GR16:$src1, GR16:$src2),
1266 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1267 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
1268 (ins GR32:$src1, GR32:$src2),
1269 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
1270 def ADC64rr_REV : RI<0x13, MRMSrcReg , (outs GR32:$dst),
1271 (ins GR64:$src1, GR64:$src2),
1272 "adc{q}\t{$src2, $dst|$dst, $src2}", []>;
1275 def ADC8rm : I<0x12, MRMSrcMem ,
1276 (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
1277 "adc{b}\t{$src2, $dst|$dst, $src2}",
1278 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
1279 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
1280 (ins GR16:$src1, i16mem:$src2),
1281 "adc{w}\t{$src2, $dst|$dst, $src2}",
1282 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
1284 def ADC32rm : I<0x13, MRMSrcMem ,
1285 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1286 "adc{l}\t{$src2, $dst|$dst, $src2}",
1287 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
1288 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst),
1289 (ins GR64:$src1, i64mem:$src2),
1290 "adc{q}\t{$src2, $dst|$dst, $src2}",
1291 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
1292 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1293 "adc{b}\t{$src2, $dst|$dst, $src2}",
1294 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
1295 def ADC16ri : Ii16<0x81, MRM2r,
1296 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1297 "adc{w}\t{$src2, $dst|$dst, $src2}",
1298 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
1299 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
1300 (ins GR16:$src1, i16i8imm:$src2),
1301 "adc{w}\t{$src2, $dst|$dst, $src2}",
1302 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
1304 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
1305 (ins GR32:$src1, i32imm:$src2),
1306 "adc{l}\t{$src2, $dst|$dst, $src2}",
1307 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
1308 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
1309 (ins GR32:$src1, i32i8imm:$src2),
1310 "adc{l}\t{$src2, $dst|$dst, $src2}",
1311 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
1312 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst),
1313 (ins GR64:$src1, i64i32imm:$src2),
1314 "adc{q}\t{$src2, $dst|$dst, $src2}",
1315 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
1316 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst),
1317 (ins GR64:$src1, i64i8imm:$src2),
1318 "adc{q}\t{$src2, $dst|$dst, $src2}",
1319 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
1320 } // Constraints = "$src1 = $dst"
1322 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
1323 "adc{b}\t{$src2, $dst|$dst, $src2}",
1324 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
1325 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1326 "adc{w}\t{$src2, $dst|$dst, $src2}",
1327 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
1329 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1330 "adc{l}\t{$src2, $dst|$dst, $src2}",
1331 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
1332 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1333 "adc{q}\t{$src2, $dst|$dst, $src2}",
1334 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
1335 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
1336 "adc{b}\t{$src2, $dst|$dst, $src2}",
1337 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1338 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
1339 "adc{w}\t{$src2, $dst|$dst, $src2}",
1340 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1342 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1343 "adc{w}\t{$src2, $dst|$dst, $src2}",
1344 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1346 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
1347 "adc{l}\t{$src2, $dst|$dst, $src2}",
1348 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1349 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1350 "adc{l}\t{$src2, $dst|$dst, $src2}",
1351 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1353 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
1354 "adc{q}\t{$src2, $dst|$dst, $src2}",
1355 [(store (adde (load addr:$dst), i64immSExt32:$src2),
1357 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1358 "adc{q}\t{$src2, $dst|$dst, $src2}",
1359 [(store (adde (load addr:$dst), i64immSExt8:$src2),
1362 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
1363 "adc{b}\t{$src, %al|%al, $src}", []>;
1364 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
1365 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1366 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
1367 "adc{l}\t{$src, %eax|%eax, $src}", []>;
1368 def ADC64i32 : RIi32<0x15, RawFrm, (outs), (ins i64i32imm:$src),
1369 "adc{q}\t{$src, %rax|%rax, $src}", []>;
1370 } // Uses = [EFLAGS]
1372 let Constraints = "$src1 = $dst" in {
1374 // Register-Register Subtraction
1375 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1376 "sub{b}\t{$src2, $dst|$dst, $src2}",
1377 [(set GR8:$dst, EFLAGS,
1378 (X86sub_flag GR8:$src1, GR8:$src2))]>;
1379 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
1380 "sub{w}\t{$src2, $dst|$dst, $src2}",
1381 [(set GR16:$dst, EFLAGS,
1382 (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
1383 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
1384 "sub{l}\t{$src2, $dst|$dst, $src2}",
1385 [(set GR32:$dst, EFLAGS,
1386 (X86sub_flag GR32:$src1, GR32:$src2))]>;
1387 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst),
1388 (ins GR64:$src1, GR64:$src2),
1389 "sub{q}\t{$src2, $dst|$dst, $src2}",
1390 [(set GR64:$dst, EFLAGS,
1391 (X86sub_flag GR64:$src1, GR64:$src2))]>;
1393 let isCodeGenOnly = 1 in {
1394 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1395 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
1396 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
1397 (ins GR16:$src1, GR16:$src2),
1398 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1399 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
1400 (ins GR32:$src1, GR32:$src2),
1401 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
1402 def SUB64rr_REV : RI<0x2B, MRMSrcReg, (outs GR64:$dst),
1403 (ins GR64:$src1, GR64:$src2),
1404 "sub{q}\t{$src2, $dst|$dst, $src2}", []>;
1407 // Register-Memory Subtraction
1408 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
1409 (ins GR8 :$src1, i8mem :$src2),
1410 "sub{b}\t{$src2, $dst|$dst, $src2}",
1411 [(set GR8:$dst, EFLAGS,
1412 (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
1413 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
1414 (ins GR16:$src1, i16mem:$src2),
1415 "sub{w}\t{$src2, $dst|$dst, $src2}",
1416 [(set GR16:$dst, EFLAGS,
1417 (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
1418 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
1419 (ins GR32:$src1, i32mem:$src2),
1420 "sub{l}\t{$src2, $dst|$dst, $src2}",
1421 [(set GR32:$dst, EFLAGS,
1422 (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
1423 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst),
1424 (ins GR64:$src1, i64mem:$src2),
1425 "sub{q}\t{$src2, $dst|$dst, $src2}",
1426 [(set GR64:$dst, EFLAGS,
1427 (X86sub_flag GR64:$src1, (load addr:$src2)))]>;
1429 // Register-Integer Subtraction
1430 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
1431 (ins GR8:$src1, i8imm:$src2),
1432 "sub{b}\t{$src2, $dst|$dst, $src2}",
1433 [(set GR8:$dst, EFLAGS,
1434 (X86sub_flag GR8:$src1, imm:$src2))]>;
1435 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
1436 (ins GR16:$src1, i16imm:$src2),
1437 "sub{w}\t{$src2, $dst|$dst, $src2}",
1438 [(set GR16:$dst, EFLAGS,
1439 (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
1440 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
1441 (ins GR32:$src1, i32imm:$src2),
1442 "sub{l}\t{$src2, $dst|$dst, $src2}",
1443 [(set GR32:$dst, EFLAGS,
1444 (X86sub_flag GR32:$src1, imm:$src2))]>;
1445 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
1446 (ins GR64:$src1, i64i32imm:$src2),
1447 "sub{q}\t{$src2, $dst|$dst, $src2}",
1448 [(set GR64:$dst, EFLAGS,
1449 (X86sub_flag GR64:$src1, i64immSExt32:$src2))]>;
1450 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
1451 (ins GR16:$src1, i16i8imm:$src2),
1452 "sub{w}\t{$src2, $dst|$dst, $src2}",
1453 [(set GR16:$dst, EFLAGS,
1454 (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1455 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
1456 (ins GR32:$src1, i32i8imm:$src2),
1457 "sub{l}\t{$src2, $dst|$dst, $src2}",
1458 [(set GR32:$dst, EFLAGS,
1459 (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
1460 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
1461 (ins GR64:$src1, i64i8imm:$src2),
1462 "sub{q}\t{$src2, $dst|$dst, $src2}",
1463 [(set GR64:$dst, EFLAGS,
1464 (X86sub_flag GR64:$src1, i64immSExt8:$src2))]>;
1465 } // Constraints = "$src1 = $dst"
1467 // Memory-Register Subtraction
1468 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1469 "sub{b}\t{$src2, $dst|$dst, $src2}",
1470 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
1471 (implicit EFLAGS)]>;
1472 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1473 "sub{w}\t{$src2, $dst|$dst, $src2}",
1474 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
1475 (implicit EFLAGS)]>, OpSize;
1476 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1477 "sub{l}\t{$src2, $dst|$dst, $src2}",
1478 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
1479 (implicit EFLAGS)]>;
1480 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1481 "sub{q}\t{$src2, $dst|$dst, $src2}",
1482 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
1483 (implicit EFLAGS)]>;
1485 // Memory-Integer Subtraction
1486 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
1487 "sub{b}\t{$src2, $dst|$dst, $src2}",
1488 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
1489 (implicit EFLAGS)]>;
1490 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
1491 "sub{w}\t{$src2, $dst|$dst, $src2}",
1492 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
1493 (implicit EFLAGS)]>, OpSize;
1494 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
1495 "sub{l}\t{$src2, $dst|$dst, $src2}",
1496 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
1497 (implicit EFLAGS)]>;
1498 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
1499 "sub{q}\t{$src2, $dst|$dst, $src2}",
1500 [(store (sub (load addr:$dst), i64immSExt32:$src2),
1502 (implicit EFLAGS)]>;
1503 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1504 "sub{w}\t{$src2, $dst|$dst, $src2}",
1505 [(store (sub (load addr:$dst), i16immSExt8:$src2),
1507 (implicit EFLAGS)]>, OpSize;
1508 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1509 "sub{l}\t{$src2, $dst|$dst, $src2}",
1510 [(store (sub (load addr:$dst), i32immSExt8:$src2),
1512 (implicit EFLAGS)]>;
1513 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1514 "sub{q}\t{$src2, $dst|$dst, $src2}",
1515 [(store (sub (load addr:$dst), i64immSExt8:$src2),
1517 (implicit EFLAGS)]>;
1519 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
1520 "sub{b}\t{$src, %al|%al, $src}", []>;
1521 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
1522 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1523 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
1524 "sub{l}\t{$src, %eax|%eax, $src}", []>;
1525 def SUB64i32 : RIi32<0x2D, RawFrm, (outs), (ins i64i32imm:$src),
1526 "sub{q}\t{$src, %rax|%rax, $src}", []>;
1528 let Uses = [EFLAGS] in {
1529 let Constraints = "$src1 = $dst" in {
1530 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
1531 (ins GR8:$src1, GR8:$src2),
1532 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1533 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
1534 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
1535 (ins GR16:$src1, GR16:$src2),
1536 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1537 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
1538 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
1539 (ins GR32:$src1, GR32:$src2),
1540 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1541 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
1542 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst),
1543 (ins GR64:$src1, GR64:$src2),
1544 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1545 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
1546 } // Constraints = "$src1 = $dst"
1549 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
1550 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1551 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
1552 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1553 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1554 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
1556 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1557 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1558 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
1559 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1560 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1561 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
1563 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
1564 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1565 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1566 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
1567 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1568 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1570 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1571 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1572 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1574 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
1575 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1576 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1577 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1578 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1579 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1580 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
1581 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1582 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
1583 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1584 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1585 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
1587 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
1588 "sbb{b}\t{$src, %al|%al, $src}", []>;
1589 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
1590 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1591 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
1592 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
1593 def SBB64i32 : RIi32<0x1D, RawFrm, (outs), (ins i64i32imm:$src),
1594 "sbb{q}\t{$src, %rax|%rax, $src}", []>;
1596 let Constraints = "$src1 = $dst" in {
1598 let isCodeGenOnly = 1 in {
1599 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1600 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
1601 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
1602 (ins GR16:$src1, GR16:$src2),
1603 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1604 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
1605 (ins GR32:$src1, GR32:$src2),
1606 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
1607 def SBB64rr_REV : RI<0x1B, MRMSrcReg, (outs GR64:$dst),
1608 (ins GR64:$src1, GR64:$src2),
1609 "sbb{q}\t{$src2, $dst|$dst, $src2}", []>;
1612 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
1613 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1614 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
1615 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
1616 (ins GR16:$src1, i16mem:$src2),
1617 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1618 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
1620 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
1621 (ins GR32:$src1, i32mem:$src2),
1622 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1623 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
1624 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst),
1625 (ins GR64:$src1, i64mem:$src2),
1626 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1627 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
1628 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1629 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1630 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
1631 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
1632 (ins GR16:$src1, i16imm:$src2),
1633 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1634 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
1635 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
1636 (ins GR16:$src1, i16i8imm:$src2),
1637 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1638 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
1640 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
1641 (ins GR32:$src1, i32imm:$src2),
1642 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1643 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
1644 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
1645 (ins GR32:$src1, i32i8imm:$src2),
1646 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1647 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
1648 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst),
1649 (ins GR64:$src1, i64i32imm:$src2),
1650 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1651 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
1652 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst),
1653 (ins GR64:$src1, i64i8imm:$src2),
1654 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1655 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
1657 } // Constraints = "$src1 = $dst"
1658 } // Uses = [EFLAGS]
1659 } // Defs = [EFLAGS]
1661 //===----------------------------------------------------------------------===//
1662 // Test instructions are just like AND, except they don't generate a result.
1664 let Defs = [EFLAGS] in {
1665 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
1666 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
1667 "test{b}\t{$src2, $src1|$src1, $src2}",
1668 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
1669 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
1670 "test{w}\t{$src2, $src1|$src1, $src2}",
1671 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
1674 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
1675 "test{l}\t{$src2, $src1|$src1, $src2}",
1676 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
1678 def TEST64rr : RI<0x85, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1679 "test{q}\t{$src2, $src1|$src1, $src2}",
1680 [(set EFLAGS, (X86cmp (and GR64:$src1, GR64:$src2), 0))]>;
1683 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
1684 "test{b}\t{$src2, $src1|$src1, $src2}",
1685 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
1687 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
1688 "test{w}\t{$src2, $src1|$src1, $src2}",
1689 [(set EFLAGS, (X86cmp (and GR16:$src1,
1690 (loadi16 addr:$src2)), 0))]>, OpSize;
1691 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
1692 "test{l}\t{$src2, $src1|$src1, $src2}",
1693 [(set EFLAGS, (X86cmp (and GR32:$src1,
1694 (loadi32 addr:$src2)), 0))]>;
1695 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1696 "test{q}\t{$src2, $src1|$src1, $src2}",
1697 [(set EFLAGS, (X86cmp (and GR64:$src1, (loadi64 addr:$src2)),
1700 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
1701 (outs), (ins GR8:$src1, i8imm:$src2),
1702 "test{b}\t{$src2, $src1|$src1, $src2}",
1703 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
1704 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
1705 (outs), (ins GR16:$src1, i16imm:$src2),
1706 "test{w}\t{$src2, $src1|$src1, $src2}",
1707 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
1709 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
1710 (outs), (ins GR32:$src1, i32imm:$src2),
1711 "test{l}\t{$src2, $src1|$src1, $src2}",
1712 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
1713 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1714 (ins GR64:$src1, i64i32imm:$src2),
1715 "test{q}\t{$src2, $src1|$src1, $src2}",
1716 [(set EFLAGS, (X86cmp (and GR64:$src1, i64immSExt32:$src2),
1719 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
1720 (outs), (ins i8mem:$src1, i8imm:$src2),
1721 "test{b}\t{$src2, $src1|$src1, $src2}",
1722 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
1724 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
1725 (outs), (ins i16mem:$src1, i16imm:$src2),
1726 "test{w}\t{$src2, $src1|$src1, $src2}",
1727 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
1729 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
1730 (outs), (ins i32mem:$src1, i32imm:$src2),
1731 "test{l}\t{$src2, $src1|$src1, $src2}",
1732 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
1734 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1735 (ins i64mem:$src1, i64i32imm:$src2),
1736 "test{q}\t{$src2, $src1|$src1, $src2}",
1737 [(set EFLAGS, (X86cmp (and (loadi64 addr:$src1),
1738 i64immSExt32:$src2), 0))]>;
1740 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
1741 "test{b}\t{$src, %al|%al, $src}", []>;
1742 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
1743 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1744 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
1745 "test{l}\t{$src, %eax|%eax, $src}", []>;
1746 def TEST64i32 : RIi32<0xa9, RawFrm, (outs), (ins i64i32imm:$src),
1747 "test{q}\t{$src, %rax|%rax, $src}", []>;
1749 } // Defs = [EFLAGS]
1752 //===----------------------------------------------------------------------===//
1753 // Integer comparisons
1755 let Defs = [EFLAGS] in {
1757 def CMP8rr : I<0x38, MRMDestReg,
1758 (outs), (ins GR8 :$src1, GR8 :$src2),
1759 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1760 [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
1761 def CMP16rr : I<0x39, MRMDestReg,
1762 (outs), (ins GR16:$src1, GR16:$src2),
1763 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1764 [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
1765 def CMP32rr : I<0x39, MRMDestReg,
1766 (outs), (ins GR32:$src1, GR32:$src2),
1767 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1768 [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
1769 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1770 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1771 [(set EFLAGS, (X86cmp GR64:$src1, GR64:$src2))]>;
1773 def CMP8mr : I<0x38, MRMDestMem,
1774 (outs), (ins i8mem :$src1, GR8 :$src2),
1775 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1776 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
1777 def CMP16mr : I<0x39, MRMDestMem,
1778 (outs), (ins i16mem:$src1, GR16:$src2),
1779 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1780 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
1782 def CMP32mr : I<0x39, MRMDestMem,
1783 (outs), (ins i32mem:$src1, GR32:$src2),
1784 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1785 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
1786 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1787 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1788 [(set EFLAGS, (X86cmp (loadi64 addr:$src1), GR64:$src2))]>;
1790 def CMP8rm : I<0x3A, MRMSrcMem,
1791 (outs), (ins GR8 :$src1, i8mem :$src2),
1792 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1793 [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
1794 def CMP16rm : I<0x3B, MRMSrcMem,
1795 (outs), (ins GR16:$src1, i16mem:$src2),
1796 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1797 [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
1799 def CMP32rm : I<0x3B, MRMSrcMem,
1800 (outs), (ins GR32:$src1, i32mem:$src2),
1801 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1802 [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
1803 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1804 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1805 [(set EFLAGS, (X86cmp GR64:$src1, (loadi64 addr:$src2)))]>;
1807 // These are alternate spellings for use by the disassembler, we mark them as
1808 // code gen only to ensure they aren't matched by the assembler.
1809 let isCodeGenOnly = 1 in {
1810 def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
1811 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
1812 def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
1813 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
1814 def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
1815 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
1816 def CMP64rr_alt : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1817 "cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
1820 def CMP8ri : Ii8<0x80, MRM7r,
1821 (outs), (ins GR8:$src1, i8imm:$src2),
1822 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1823 [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
1824 def CMP16ri : Ii16<0x81, MRM7r,
1825 (outs), (ins GR16:$src1, i16imm:$src2),
1826 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1827 [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
1828 def CMP32ri : Ii32<0x81, MRM7r,
1829 (outs), (ins GR32:$src1, i32imm:$src2),
1830 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1831 [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
1832 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1833 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1834 [(set EFLAGS, (X86cmp GR64:$src1, i64immSExt32:$src2))]>;
1836 def CMP8mi : Ii8 <0x80, MRM7m,
1837 (outs), (ins i8mem :$src1, i8imm :$src2),
1838 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1839 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
1840 def CMP16mi : Ii16<0x81, MRM7m,
1841 (outs), (ins i16mem:$src1, i16imm:$src2),
1842 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1843 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
1845 def CMP32mi : Ii32<0x81, MRM7m,
1846 (outs), (ins i32mem:$src1, i32imm:$src2),
1847 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1848 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
1849 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1850 (ins i64mem:$src1, i64i32imm:$src2),
1851 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1852 [(set EFLAGS, (X86cmp (loadi64 addr:$src1),
1853 i64immSExt32:$src2))]>;
1855 def CMP16ri8 : Ii8<0x83, MRM7r,
1856 (outs), (ins GR16:$src1, i16i8imm:$src2),
1857 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1858 [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
1860 def CMP32ri8 : Ii8<0x83, MRM7r,
1861 (outs), (ins GR32:$src1, i32i8imm:$src2),
1862 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1863 [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
1864 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1865 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1866 [(set EFLAGS, (X86cmp GR64:$src1, i64immSExt8:$src2))]>;
1868 def CMP16mi8 : Ii8<0x83, MRM7m,
1869 (outs), (ins i16mem:$src1, i16i8imm:$src2),
1870 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1871 [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
1872 i16immSExt8:$src2))]>, OpSize;
1873 def CMP32mi8 : Ii8<0x83, MRM7m,
1874 (outs), (ins i32mem:$src1, i32i8imm:$src2),
1875 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1876 [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
1877 i32immSExt8:$src2))]>;
1878 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1879 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1880 [(set EFLAGS, (X86cmp (loadi64 addr:$src1),
1881 i64immSExt8:$src2))]>;
1883 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
1884 "cmp{b}\t{$src, %al|%al, $src}", []>;
1885 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
1886 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1887 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
1888 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
1889 def CMP64i32 : RIi32<0x3D, RawFrm, (outs), (ins i64i32imm:$src),
1890 "cmp{q}\t{$src, %rax|%rax, $src}", []>;
1892 } // Defs = [EFLAGS]