1 //===- X86InstrArithmetic.td - Integer Arithmetic Instrs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the integer arithmetic instructions in the X86
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // LEA - Load Effective Address
18 let neverHasSideEffects = 1 in
19 def LEA16r : I<0x8D, MRMSrcMem,
20 (outs GR16:$dst), (ins i32mem:$src),
21 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
22 let isReMaterializable = 1 in
23 def LEA32r : I<0x8D, MRMSrcMem,
24 (outs GR32:$dst), (ins i32mem:$src),
25 "lea{l}\t{$src|$dst}, {$dst|$src}",
26 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
28 def LEA64_32r : I<0x8D, MRMSrcMem,
29 (outs GR32:$dst), (ins lea64_32mem:$src),
30 "lea{l}\t{$src|$dst}, {$dst|$src}",
31 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
33 let isReMaterializable = 1 in
34 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
35 "lea{q}\t{$src|$dst}, {$dst|$src}",
36 [(set GR64:$dst, lea64addr:$src)]>;
40 //===----------------------------------------------------------------------===//
41 // Fixed-Register Multiplication and Division Instructions.
44 // Extra precision multiplication
46 // AL is really implied by AX, but the registers in Defs must match the
47 // SDNode results (i8, i32).
48 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
49 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
50 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
51 // This probably ought to be moved to a def : Pat<> if the
52 // syntax can be accepted.
53 [(set AL, (mul AL, GR8:$src)),
54 (implicit EFLAGS)]>; // AL,AH = AL*GR8
56 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
57 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
59 []>, OpSize; // AX,DX = AX*GR16
61 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
62 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
64 []>; // EAX,EDX = EAX*GR32
65 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
66 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
67 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
69 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
70 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
72 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
73 // This probably ought to be moved to a def : Pat<> if the
74 // syntax can be accepted.
75 [(set AL, (mul AL, (loadi8 addr:$src))),
76 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
78 let mayLoad = 1, neverHasSideEffects = 1 in {
79 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
80 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
82 []>, OpSize; // AX,DX = AX*[mem16]
84 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
85 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
87 []>; // EAX,EDX = EAX*[mem32]
88 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
89 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
90 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
93 let neverHasSideEffects = 1 in {
94 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
95 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
97 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
98 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
99 OpSize; // AX,DX = AX*GR16
100 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
101 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
102 // EAX,EDX = EAX*GR32
103 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
104 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", []>;
105 // RAX,RDX = RAX*GR64
108 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
109 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
110 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
111 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
112 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
113 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
114 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
115 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
116 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
117 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
118 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
119 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
121 } // neverHasSideEffects
124 let Defs = [EFLAGS] in {
125 let Constraints = "$src1 = $dst" in {
127 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
128 // Register-Register Signed Integer Multiply
129 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
130 "imul{w}\t{$src2, $dst|$dst, $src2}",
131 [(set GR16:$dst, EFLAGS,
132 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
133 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
134 "imul{l}\t{$src2, $dst|$dst, $src2}",
135 [(set GR32:$dst, EFLAGS,
136 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
137 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
138 (ins GR64:$src1, GR64:$src2),
139 "imul{q}\t{$src2, $dst|$dst, $src2}",
140 [(set GR64:$dst, EFLAGS,
141 (X86smul_flag GR64:$src1, GR64:$src2))]>, TB;
144 // Register-Memory Signed Integer Multiply
145 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
146 (ins GR16:$src1, i16mem:$src2),
147 "imul{w}\t{$src2, $dst|$dst, $src2}",
148 [(set GR16:$dst, EFLAGS,
149 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
151 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
152 (ins GR32:$src1, i32mem:$src2),
153 "imul{l}\t{$src2, $dst|$dst, $src2}",
154 [(set GR32:$dst, EFLAGS,
155 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
156 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
157 (ins GR64:$src1, i64mem:$src2),
158 "imul{q}\t{$src2, $dst|$dst, $src2}",
159 [(set GR64:$dst, EFLAGS,
160 (X86smul_flag GR64:$src1, (load addr:$src2)))]>, TB;
161 } // Constraints = "$src1 = $dst"
165 // Suprisingly enough, these are not two address instructions!
166 let Defs = [EFLAGS] in {
167 // Register-Integer Signed Integer Multiply
168 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
169 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
170 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
171 [(set GR16:$dst, EFLAGS,
172 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
173 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
174 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
175 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
176 [(set GR16:$dst, EFLAGS,
177 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
179 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
180 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
181 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
182 [(set GR32:$dst, EFLAGS,
183 (X86smul_flag GR32:$src1, imm:$src2))]>;
184 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
185 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
186 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
187 [(set GR32:$dst, EFLAGS,
188 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
189 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
190 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
191 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
192 [(set GR64:$dst, EFLAGS,
193 (X86smul_flag GR64:$src1, i64immSExt32:$src2))]>;
194 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
195 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
196 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
197 [(set GR64:$dst, EFLAGS,
198 (X86smul_flag GR64:$src1, i64immSExt8:$src2))]>;
201 // Memory-Integer Signed Integer Multiply
202 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
203 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
204 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
205 [(set GR16:$dst, EFLAGS,
206 (X86smul_flag (load addr:$src1), imm:$src2))]>,
208 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
209 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
210 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
211 [(set GR16:$dst, EFLAGS,
212 (X86smul_flag (load addr:$src1),
213 i16immSExt8:$src2))]>, OpSize;
214 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
215 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
216 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
217 [(set GR32:$dst, EFLAGS,
218 (X86smul_flag (load addr:$src1), imm:$src2))]>;
219 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
220 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
221 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
222 [(set GR32:$dst, EFLAGS,
223 (X86smul_flag (load addr:$src1),
224 i32immSExt8:$src2))]>;
225 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
226 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
227 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 [(set GR64:$dst, EFLAGS,
229 (X86smul_flag (load addr:$src1),
230 i64immSExt32:$src2))]>;
231 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
232 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
233 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
234 [(set GR64:$dst, EFLAGS,
235 (X86smul_flag (load addr:$src1),
236 i64immSExt8:$src2))]>;
242 // unsigned division/remainder
243 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
244 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
246 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
247 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
248 "div{w}\t$src", []>, OpSize;
249 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
250 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
252 // RDX:RAX/r64 = RAX,RDX
253 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
254 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
258 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
259 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
261 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
262 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
263 "div{w}\t$src", []>, OpSize;
264 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
265 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
267 // RDX:RAX/[mem64] = RAX,RDX
268 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
269 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
273 // Signed division/remainder.
274 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
275 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
276 "idiv{b}\t$src", []>;
277 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
278 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
279 "idiv{w}\t$src", []>, OpSize;
280 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
281 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
282 "idiv{l}\t$src", []>;
283 // RDX:RAX/r64 = RAX,RDX
284 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
285 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
286 "idiv{q}\t$src", []>;
288 let mayLoad = 1, mayLoad = 1 in {
289 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
290 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
291 "idiv{b}\t$src", []>;
292 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
293 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
294 "idiv{w}\t$src", []>, OpSize;
295 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
296 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
297 "idiv{l}\t$src", []>;
298 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] = RAX,RDX
299 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
300 "idiv{q}\t$src", []>;
303 //===----------------------------------------------------------------------===//
304 // Two address Instructions.
307 // unary instructions
308 let CodeSize = 2 in {
309 let Defs = [EFLAGS] in {
310 let Constraints = "$src1 = $dst" in {
311 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
313 [(set GR8:$dst, (ineg GR8:$src1)),
315 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
317 [(set GR16:$dst, (ineg GR16:$src1)),
318 (implicit EFLAGS)]>, OpSize;
319 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
321 [(set GR32:$dst, (ineg GR32:$src1)),
323 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
324 [(set GR64:$dst, (ineg GR64:$src1)),
326 } // Constraints = "$src1 = $dst"
328 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
330 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
332 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
334 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
335 (implicit EFLAGS)]>, OpSize;
336 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
338 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
340 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
341 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
346 // Note: NOT does not set EFLAGS!
348 let Constraints = "$src1 = $dst" in {
349 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
350 let AddedComplexity = 15 in {
351 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
353 [(set GR8:$dst, (not GR8:$src1))]>;
354 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
356 [(set GR16:$dst, (not GR16:$src1))]>, OpSize;
357 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
359 [(set GR32:$dst, (not GR32:$src1))]>;
360 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",
361 [(set GR64:$dst, (not GR64:$src1))]>;
363 } // Constraints = "$src1 = $dst"
365 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
367 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
368 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
370 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
371 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
373 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
374 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
375 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
378 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
379 let Defs = [EFLAGS] in {
380 let Constraints = "$src1 = $dst" in {
382 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
384 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>;
386 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
387 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
389 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
390 OpSize, Requires<[In32BitMode]>;
391 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
393 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
394 Requires<[In32BitMode]>;
395 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
396 [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))]>;
397 } // isConvertibleToThreeAddress = 1, CodeSize = 1
400 // In 64-bit mode, single byte INC and DEC cannot be encoded.
401 let isConvertibleToThreeAddress = 1, CodeSize = 2 in {
402 // Can transform into LEA.
403 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
405 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
406 OpSize, Requires<[In64BitMode]>;
407 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
409 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
410 Requires<[In64BitMode]>;
411 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
413 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
414 OpSize, Requires<[In64BitMode]>;
415 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
417 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
418 Requires<[In64BitMode]>;
419 } // isConvertibleToThreeAddress = 1, CodeSize = 2
421 } // Constraints = "$src1 = $dst"
423 let CodeSize = 2 in {
424 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
425 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
427 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
428 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
430 OpSize, Requires<[In32BitMode]>;
431 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
432 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
434 Requires<[In32BitMode]>;
435 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
436 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
439 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
440 // how to unfold them.
441 // FIXME: What is this for??
442 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
443 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
445 OpSize, Requires<[In64BitMode]>;
446 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
447 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
449 Requires<[In64BitMode]>;
450 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
451 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
453 OpSize, Requires<[In64BitMode]>;
454 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
455 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
457 Requires<[In64BitMode]>;
460 let Constraints = "$src1 = $dst" in {
462 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
464 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>;
465 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
466 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
468 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
469 OpSize, Requires<[In32BitMode]>;
470 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
472 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
473 Requires<[In32BitMode]>;
474 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst",
475 [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))]>;
477 } // Constraints = "$src1 = $dst"
480 let CodeSize = 2 in {
481 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
482 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
484 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
485 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
487 OpSize, Requires<[In32BitMode]>;
488 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
489 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
491 Requires<[In32BitMode]>;
492 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
493 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
499 /// X86TypeInfo - This is a bunch of information that describes relevant X86
500 /// information about value types. For example, it can tell you what the
501 /// register class and preferred load to use.
502 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
503 PatFrag loadnode, X86MemOperand memoperand, ImmType immkind,
504 Operand immoperand, SDPatternOperator immoperator,
505 Operand imm8operand, SDPatternOperator imm8operator,
506 bit hasOddOpcode, bit hasOpSizePrefix, bit hasREX_WPrefix> {
507 /// VT - This is the value type itself.
510 /// InstrSuffix - This is the suffix used on instructions with this type. For
511 /// example, i8 -> "b", i16 -> "w", i32 -> "l", i64 -> "q".
512 string InstrSuffix = instrsuffix;
514 /// RegClass - This is the register class associated with this type. For
515 /// example, i8 -> GR8, i16 -> GR16, i32 -> GR32, i64 -> GR64.
516 RegisterClass RegClass = regclass;
518 /// LoadNode - This is the load node associated with this type. For
519 /// example, i8 -> loadi8, i16 -> loadi16, i32 -> loadi32, i64 -> loadi64.
520 PatFrag LoadNode = loadnode;
522 /// MemOperand - This is the memory operand associated with this type. For
523 /// example, i8 -> i8mem, i16 -> i16mem, i32 -> i32mem, i64 -> i64mem.
524 X86MemOperand MemOperand = memoperand;
526 /// ImmEncoding - This is the encoding of an immediate of this type. For
527 /// example, i8 -> Imm8, i16 -> Imm16, i32 -> Imm32. Note that i64 -> Imm32
528 /// since the immediate fields of i64 instructions is a 32-bit sign extended
530 ImmType ImmEncoding = immkind;
532 /// ImmOperand - This is the operand kind of an immediate of this type. For
533 /// example, i8 -> i8imm, i16 -> i16imm, i32 -> i32imm. Note that i64 ->
534 /// i64i32imm since the immediate fields of i64 instructions is a 32-bit sign
536 Operand ImmOperand = immoperand;
538 /// ImmOperator - This is the operator that should be used to match an
539 /// immediate of this kind in a pattern (e.g. imm, or i64immSExt32).
540 SDPatternOperator ImmOperator = immoperator;
542 /// Imm8Operand - This is the operand kind to use for an imm8 of this type.
543 /// For example, i8 -> <invalid>, i16 -> i16i8imm, i32 -> i32i8imm. This is
544 /// only used for instructions that have a sign-extended imm8 field form.
545 Operand Imm8Operand = imm8operand;
547 /// Imm8Operator - This is the operator that should be used to match an 8-bit
548 /// sign extended immediate of this kind in a pattern (e.g. imm16immSExt8).
549 SDPatternOperator Imm8Operator = imm8operator;
551 /// HasOddOpcode - This bit is true if the instruction should have an odd (as
552 /// opposed to even) opcode. Operations on i8 are usually even, operations on
553 /// other datatypes are odd.
554 bit HasOddOpcode = hasOddOpcode;
556 /// HasOpSizePrefix - This bit is set to true if the instruction should have
557 /// the 0x66 operand size prefix. This is set for i16 types.
558 bit HasOpSizePrefix = hasOpSizePrefix;
560 /// HasREX_WPrefix - This bit is set to true if the instruction should have
561 /// the 0x40 REX prefix. This is set for i64 types.
562 bit HasREX_WPrefix = hasREX_WPrefix;
565 def invalid_node : SDNode<"<<invalid_node>>", SDTIntLeaf,[],"<<invalid_node>>">;
568 def Xi8 : X86TypeInfo<i8 , "b", GR8 , loadi8 , i8mem ,
569 Imm8 , i8imm , imm, i8imm , invalid_node,
571 def Xi16 : X86TypeInfo<i16, "w", GR16, loadi16, i16mem,
572 Imm16, i16imm, imm, i16i8imm, i16immSExt8,
574 def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem,
575 Imm32, i32imm, imm, i32i8imm, i32immSExt8,
577 def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem,
578 Imm32, i64i32imm, i64immSExt32, i64i8imm, i64immSExt8,
581 /// ITy - This instruction base class takes the type info for the instruction.
583 /// 1. Concatenates together the instruction mnemonic with the appropriate
584 /// suffix letter, a tab, and the arguments.
585 /// 2. Infers whether the instruction should have a 0x66 prefix byte.
586 /// 3. Infers whether the instruction should have a 0x40 REX_W prefix.
587 /// 4. Infers whether the low bit of the opcode should be 0 (for i8 operations)
588 /// or 1 (for i16,i32,i64 operations).
589 class ITy<bits<8> opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins,
590 string mnemonic, string args, list<dag> pattern>
591 : I<{opcode{7}, opcode{6}, opcode{5}, opcode{4},
592 opcode{3}, opcode{2}, opcode{1}, typeinfo.HasOddOpcode },
594 !strconcat(mnemonic, "{", typeinfo.InstrSuffix, "}\t", args), pattern> {
596 // Infer instruction prefixes from type info.
597 let hasOpSizePrefix = typeinfo.HasOpSizePrefix;
598 let hasREX_WPrefix = typeinfo.HasREX_WPrefix;
602 class BinOpRR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
604 : ITy<opcode, MRMDestReg, typeinfo,
605 (outs typeinfo.RegClass:$dst),
606 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
607 mnemonic, "{$src2, $dst|$dst, $src2}",
608 [(set typeinfo.RegClass:$dst, EFLAGS,
609 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
611 class BinOpRR_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo>
612 : ITy<opcode, MRMSrcReg, typeinfo,
613 (outs typeinfo.RegClass:$dst),
614 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
615 mnemonic, "{$src2, $dst|$dst, $src2}", []> {
616 // The disassembler should know about this, but not the asmparser.
617 let isCodeGenOnly = 1;
620 class BinOpRM<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
622 : ITy<opcode, MRMSrcMem, typeinfo,
623 (outs typeinfo.RegClass:$dst),
624 (ins typeinfo.RegClass:$src1, typeinfo.MemOperand:$src2),
625 mnemonic, "{$src2, $dst|$dst, $src2}",
626 [(set typeinfo.RegClass:$dst, EFLAGS,
627 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
629 // BinOpRI - Instructions like "add reg, reg, imm".
630 class BinOpRI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
631 SDNode opnode, Format f>
632 : ITy<opcode, f, typeinfo,
633 (outs typeinfo.RegClass:$dst),
634 (ins typeinfo.RegClass:$src1, typeinfo.ImmOperand:$src2),
635 mnemonic, "{$src2, $dst|$dst, $src2}",
636 [(set typeinfo.RegClass:$dst, EFLAGS,
637 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]> {
638 let ImmT = typeinfo.ImmEncoding;
642 // BinOpRI8 - Instructions like "add reg, reg, imm8".
643 class BinOpRI8<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
644 SDNode opnode, Format f>
645 : ITy<opcode, f, typeinfo,
646 (outs typeinfo.RegClass:$dst),
647 (ins typeinfo.RegClass:$src1, typeinfo.Imm8Operand:$src2),
648 mnemonic, "{$src2, $dst|$dst, $src2}",
649 [(set typeinfo.RegClass:$dst, EFLAGS,
650 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]> {
651 let ImmT = Imm8; // Always 8-bit immediate.
655 // Logical operators.
656 let Defs = [EFLAGS] in {
657 let Constraints = "$src1 = $dst" in {
659 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
660 def AND8rr : BinOpRR<0x20, "and", Xi8 , X86and_flag>;
661 def AND16rr : BinOpRR<0x20, "and", Xi16, X86and_flag>;
662 def AND32rr : BinOpRR<0x20, "and", Xi32, X86and_flag>;
663 def AND64rr : BinOpRR<0x20, "and", Xi64, X86and_flag>;
667 // AND instructions with the destination register in REG and the source register
668 // in R/M. Included for the disassembler.
670 def AND8rr_REV : BinOpRR_Rev<0x22, "and", Xi8>;
671 def AND16rr_REV : BinOpRR_Rev<0x22, "and", Xi16>;
672 def AND32rr_REV : BinOpRR_Rev<0x22, "and", Xi32>;
673 def AND64rr_REV : BinOpRR_Rev<0x22, "and", Xi64>;
675 def AND8rm : BinOpRM<0x22, "and", Xi8 , X86and_flag>;
676 def AND16rm : BinOpRM<0x22, "and", Xi16, X86and_flag>;
677 def AND32rm : BinOpRM<0x22, "and", Xi32, X86and_flag>;
678 def AND64rm : BinOpRM<0x22, "and", Xi64, X86and_flag>;
680 def AND8ri : BinOpRI<0x80, "and", Xi8 , X86and_flag, MRM4r>;
681 def AND16ri : BinOpRI<0x80, "and", Xi16, X86and_flag, MRM4r>;
682 def AND32ri : BinOpRI<0x80, "and", Xi32, X86and_flag, MRM4r>;
683 def AND64ri32: BinOpRI<0x80, "and", Xi64, X86and_flag, MRM4r>;
685 def AND16ri8 : BinOpRI8<0x82, "and", Xi16, X86and_flag, MRM4r>;
686 def AND32ri8 : BinOpRI8<0x82, "and", Xi32, X86and_flag, MRM4r>;
687 def AND64ri8 : BinOpRI8<0x82, "and", Xi64, X86and_flag, MRM4r>;
688 } // Constraints = "$src1 = $dst"
690 def AND8mr : I<0x20, MRMDestMem,
691 (outs), (ins i8mem :$dst, GR8 :$src),
692 "and{b}\t{$src, $dst|$dst, $src}",
693 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
695 def AND16mr : I<0x21, MRMDestMem,
696 (outs), (ins i16mem:$dst, GR16:$src),
697 "and{w}\t{$src, $dst|$dst, $src}",
698 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
701 def AND32mr : I<0x21, MRMDestMem,
702 (outs), (ins i32mem:$dst, GR32:$src),
703 "and{l}\t{$src, $dst|$dst, $src}",
704 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
706 def AND64mr : RI<0x21, MRMDestMem,
707 (outs), (ins i64mem:$dst, GR64:$src),
708 "and{q}\t{$src, $dst|$dst, $src}",
709 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
712 def AND8mi : Ii8<0x80, MRM4m,
713 (outs), (ins i8mem :$dst, i8imm :$src),
714 "and{b}\t{$src, $dst|$dst, $src}",
715 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
717 def AND16mi : Ii16<0x81, MRM4m,
718 (outs), (ins i16mem:$dst, i16imm:$src),
719 "and{w}\t{$src, $dst|$dst, $src}",
720 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
723 def AND32mi : Ii32<0x81, MRM4m,
724 (outs), (ins i32mem:$dst, i32imm:$src),
725 "and{l}\t{$src, $dst|$dst, $src}",
726 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
728 def AND64mi32 : RIi32<0x81, MRM4m,
729 (outs), (ins i64mem:$dst, i64i32imm:$src),
730 "and{q}\t{$src, $dst|$dst, $src}",
731 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
734 def AND16mi8 : Ii8<0x83, MRM4m,
735 (outs), (ins i16mem:$dst, i16i8imm :$src),
736 "and{w}\t{$src, $dst|$dst, $src}",
737 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
740 def AND32mi8 : Ii8<0x83, MRM4m,
741 (outs), (ins i32mem:$dst, i32i8imm :$src),
742 "and{l}\t{$src, $dst|$dst, $src}",
743 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
745 def AND64mi8 : RIi8<0x83, MRM4m,
746 (outs), (ins i64mem:$dst, i64i8imm :$src),
747 "and{q}\t{$src, $dst|$dst, $src}",
748 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
751 // FIXME: Implicitly modifiers AL.
752 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
753 "and{b}\t{$src, %al|%al, $src}", []>;
754 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
755 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
756 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
757 "and{l}\t{$src, %eax|%eax, $src}", []>;
758 def AND64i32 : RIi32<0x25, RawFrm, (outs), (ins i64i32imm:$src),
759 "and{q}\t{$src, %rax|%rax, $src}", []>;
761 let Constraints = "$src1 = $dst" in {
763 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
764 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
765 (ins GR8 :$src1, GR8 :$src2),
766 "or{b}\t{$src2, $dst|$dst, $src2}",
767 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
768 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
769 (ins GR16:$src1, GR16:$src2),
770 "or{w}\t{$src2, $dst|$dst, $src2}",
771 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
773 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
774 (ins GR32:$src1, GR32:$src2),
775 "or{l}\t{$src2, $dst|$dst, $src2}",
776 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
777 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst),
778 (ins GR64:$src1, GR64:$src2),
779 "or{q}\t{$src2, $dst|$dst, $src2}",
780 [(set GR64:$dst, EFLAGS,
781 (X86or_flag GR64:$src1, GR64:$src2))]>;
784 // OR instructions with the destination register in REG and the source register
785 // in R/M. Included for the disassembler.
786 let isCodeGenOnly = 1 in {
787 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
788 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
789 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
790 (ins GR16:$src1, GR16:$src2),
791 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
792 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
793 (ins GR32:$src1, GR32:$src2),
794 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
795 def OR64rr_REV : RI<0x0B, MRMSrcReg, (outs GR64:$dst),
796 (ins GR64:$src1, GR64:$src2),
797 "or{q}\t{$src2, $dst|$dst, $src2}", []>;
800 def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
801 (ins GR8 :$src1, i8mem :$src2),
802 "or{b}\t{$src2, $dst|$dst, $src2}",
803 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
804 (load addr:$src2)))]>;
805 def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
806 (ins GR16:$src1, i16mem:$src2),
807 "or{w}\t{$src2, $dst|$dst, $src2}",
808 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
809 (load addr:$src2)))]>,
811 def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
812 (ins GR32:$src1, i32mem:$src2),
813 "or{l}\t{$src2, $dst|$dst, $src2}",
814 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
815 (load addr:$src2)))]>;
816 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst),
817 (ins GR64:$src1, i64mem:$src2),
818 "or{q}\t{$src2, $dst|$dst, $src2}",
819 [(set GR64:$dst, EFLAGS,
820 (X86or_flag GR64:$src1, (load addr:$src2)))]>;
822 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
823 (ins GR8 :$src1, i8imm:$src2),
824 "or{b}\t{$src2, $dst|$dst, $src2}",
825 [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
826 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
827 (ins GR16:$src1, i16imm:$src2),
828 "or{w}\t{$src2, $dst|$dst, $src2}",
829 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
830 imm:$src2))]>, OpSize;
831 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
832 (ins GR32:$src1, i32imm:$src2),
833 "or{l}\t{$src2, $dst|$dst, $src2}",
834 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
836 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst),
837 (ins GR64:$src1, i64i32imm:$src2),
838 "or{q}\t{$src2, $dst|$dst, $src2}",
839 [(set GR64:$dst, EFLAGS,
840 (X86or_flag GR64:$src1, i64immSExt32:$src2))]>;
842 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
843 (ins GR16:$src1, i16i8imm:$src2),
844 "or{w}\t{$src2, $dst|$dst, $src2}",
845 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
846 i16immSExt8:$src2))]>, OpSize;
847 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
848 (ins GR32:$src1, i32i8imm:$src2),
849 "or{l}\t{$src2, $dst|$dst, $src2}",
850 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
851 i32immSExt8:$src2))]>;
852 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst),
853 (ins GR64:$src1, i64i8imm:$src2),
854 "or{q}\t{$src2, $dst|$dst, $src2}",
855 [(set GR64:$dst, EFLAGS,
856 (X86or_flag GR64:$src1, i64immSExt8:$src2))]>;
857 } // Constraints = "$src1 = $dst"
859 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
860 "or{b}\t{$src, $dst|$dst, $src}",
861 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
863 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
864 "or{w}\t{$src, $dst|$dst, $src}",
865 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
866 (implicit EFLAGS)]>, OpSize;
867 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
868 "or{l}\t{$src, $dst|$dst, $src}",
869 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
871 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
872 "or{q}\t{$src, $dst|$dst, $src}",
873 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
876 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
877 "or{b}\t{$src, $dst|$dst, $src}",
878 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
880 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
881 "or{w}\t{$src, $dst|$dst, $src}",
882 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
885 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
886 "or{l}\t{$src, $dst|$dst, $src}",
887 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
889 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
890 "or{q}\t{$src, $dst|$dst, $src}",
891 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
894 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
895 "or{w}\t{$src, $dst|$dst, $src}",
896 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
899 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
900 "or{l}\t{$src, $dst|$dst, $src}",
901 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
903 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
904 "or{q}\t{$src, $dst|$dst, $src}",
905 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
908 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
909 "or{b}\t{$src, %al|%al, $src}", []>;
910 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
911 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
912 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
913 "or{l}\t{$src, %eax|%eax, $src}", []>;
914 def OR64i32 : RIi32<0x0D, RawFrm, (outs), (ins i64i32imm:$src),
915 "or{q}\t{$src, %rax|%rax, $src}", []>;
918 let Constraints = "$src1 = $dst" in {
920 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
921 def XOR8rr : I<0x30, MRMDestReg,
922 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
923 "xor{b}\t{$src2, $dst|$dst, $src2}",
924 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
926 def XOR16rr : I<0x31, MRMDestReg,
927 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
928 "xor{w}\t{$src2, $dst|$dst, $src2}",
929 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
930 GR16:$src2))]>, OpSize;
931 def XOR32rr : I<0x31, MRMDestReg,
932 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
933 "xor{l}\t{$src2, $dst|$dst, $src2}",
934 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
936 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst),
937 (ins GR64:$src1, GR64:$src2),
938 "xor{q}\t{$src2, $dst|$dst, $src2}",
939 [(set GR64:$dst, EFLAGS,
940 (X86xor_flag GR64:$src1, GR64:$src2))]>;
941 } // isCommutable = 1
943 // XOR instructions with the destination register in REG and the source register
944 // in R/M. Included for the disassembler.
945 let isCodeGenOnly = 1 in {
946 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
947 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
948 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
949 (ins GR16:$src1, GR16:$src2),
950 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
951 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
952 (ins GR32:$src1, GR32:$src2),
953 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
954 def XOR64rr_REV : RI<0x33, MRMSrcReg, (outs GR64:$dst),
955 (ins GR64:$src1, GR64:$src2),
956 "xor{q}\t{$src2, $dst|$dst, $src2}", []>;
959 def XOR8rm : I<0x32, MRMSrcMem,
960 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
961 "xor{b}\t{$src2, $dst|$dst, $src2}",
962 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
963 (load addr:$src2)))]>;
964 def XOR16rm : I<0x33, MRMSrcMem,
965 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
966 "xor{w}\t{$src2, $dst|$dst, $src2}",
967 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
968 (load addr:$src2)))]>,
970 def XOR32rm : I<0x33, MRMSrcMem,
971 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
972 "xor{l}\t{$src2, $dst|$dst, $src2}",
973 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
974 (load addr:$src2)))]>;
975 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst),
976 (ins GR64:$src1, i64mem:$src2),
977 "xor{q}\t{$src2, $dst|$dst, $src2}",
978 [(set GR64:$dst, EFLAGS,
979 (X86xor_flag GR64:$src1, (load addr:$src2)))]>;
981 def XOR8ri : Ii8<0x80, MRM6r,
982 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
983 "xor{b}\t{$src2, $dst|$dst, $src2}",
984 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
985 def XOR16ri : Ii16<0x81, MRM6r,
986 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
987 "xor{w}\t{$src2, $dst|$dst, $src2}",
988 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
989 imm:$src2))]>, OpSize;
990 def XOR32ri : Ii32<0x81, MRM6r,
991 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
992 "xor{l}\t{$src2, $dst|$dst, $src2}",
993 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
995 def XOR64ri32 : RIi32<0x81, MRM6r,
996 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
997 "xor{q}\t{$src2, $dst|$dst, $src2}",
998 [(set GR64:$dst, EFLAGS,
999 (X86xor_flag GR64:$src1, i64immSExt32:$src2))]>;
1001 def XOR16ri8 : Ii8<0x83, MRM6r,
1002 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1003 "xor{w}\t{$src2, $dst|$dst, $src2}",
1004 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
1005 i16immSExt8:$src2))]>,
1007 def XOR32ri8 : Ii8<0x83, MRM6r,
1008 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1009 "xor{l}\t{$src2, $dst|$dst, $src2}",
1010 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
1011 i32immSExt8:$src2))]>;
1012 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst),
1013 (ins GR64:$src1, i64i8imm:$src2),
1014 "xor{q}\t{$src2, $dst|$dst, $src2}",
1015 [(set GR64:$dst, EFLAGS,
1016 (X86xor_flag GR64:$src1, i64immSExt8:$src2))]>;
1017 } // Constraints = "$src1 = $dst"
1020 def XOR8mr : I<0x30, MRMDestMem,
1021 (outs), (ins i8mem :$dst, GR8 :$src),
1022 "xor{b}\t{$src, $dst|$dst, $src}",
1023 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
1024 (implicit EFLAGS)]>;
1025 def XOR16mr : I<0x31, MRMDestMem,
1026 (outs), (ins i16mem:$dst, GR16:$src),
1027 "xor{w}\t{$src, $dst|$dst, $src}",
1028 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
1029 (implicit EFLAGS)]>,
1031 def XOR32mr : I<0x31, MRMDestMem,
1032 (outs), (ins i32mem:$dst, GR32:$src),
1033 "xor{l}\t{$src, $dst|$dst, $src}",
1034 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
1035 (implicit EFLAGS)]>;
1036 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1037 "xor{q}\t{$src, $dst|$dst, $src}",
1038 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
1039 (implicit EFLAGS)]>;
1041 def XOR8mi : Ii8<0x80, MRM6m,
1042 (outs), (ins i8mem :$dst, i8imm :$src),
1043 "xor{b}\t{$src, $dst|$dst, $src}",
1044 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
1045 (implicit EFLAGS)]>;
1046 def XOR16mi : Ii16<0x81, MRM6m,
1047 (outs), (ins i16mem:$dst, i16imm:$src),
1048 "xor{w}\t{$src, $dst|$dst, $src}",
1049 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
1050 (implicit EFLAGS)]>,
1052 def XOR32mi : Ii32<0x81, MRM6m,
1053 (outs), (ins i32mem:$dst, i32imm:$src),
1054 "xor{l}\t{$src, $dst|$dst, $src}",
1055 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
1056 (implicit EFLAGS)]>;
1057 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1058 "xor{q}\t{$src, $dst|$dst, $src}",
1059 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1060 (implicit EFLAGS)]>;
1062 def XOR16mi8 : Ii8<0x83, MRM6m,
1063 (outs), (ins i16mem:$dst, i16i8imm :$src),
1064 "xor{w}\t{$src, $dst|$dst, $src}",
1065 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
1066 (implicit EFLAGS)]>,
1068 def XOR32mi8 : Ii8<0x83, MRM6m,
1069 (outs), (ins i32mem:$dst, i32i8imm :$src),
1070 "xor{l}\t{$src, $dst|$dst, $src}",
1071 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
1072 (implicit EFLAGS)]>;
1073 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
1074 "xor{q}\t{$src, $dst|$dst, $src}",
1075 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
1076 (implicit EFLAGS)]>;
1078 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
1079 "xor{b}\t{$src, %al|%al, $src}", []>;
1080 def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
1081 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1082 def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
1083 "xor{l}\t{$src, %eax|%eax, $src}", []>;
1084 def XOR64i32 : RIi32<0x35, RawFrm, (outs), (ins i64i32imm:$src),
1085 "xor{q}\t{$src, %rax|%rax, $src}", []>;
1086 } // Defs = [EFLAGS]
1090 let Defs = [EFLAGS] in {
1091 let Constraints = "$src1 = $dst" in {
1092 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1093 // Register-Register Addition
1094 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
1095 (ins GR8 :$src1, GR8 :$src2),
1096 "add{b}\t{$src2, $dst|$dst, $src2}",
1097 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
1099 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1100 // Register-Register Addition
1101 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
1102 (ins GR16:$src1, GR16:$src2),
1103 "add{w}\t{$src2, $dst|$dst, $src2}",
1104 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
1105 GR16:$src2))]>, OpSize;
1106 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
1107 (ins GR32:$src1, GR32:$src2),
1108 "add{l}\t{$src2, $dst|$dst, $src2}",
1109 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
1111 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst),
1112 (ins GR64:$src1, GR64:$src2),
1113 "add{q}\t{$src2, $dst|$dst, $src2}",
1114 [(set GR64:$dst, EFLAGS,
1115 (X86add_flag GR64:$src1, GR64:$src2))]>;
1116 } // end isConvertibleToThreeAddress
1117 } // end isCommutable
1119 // These are alternate spellings for use by the disassembler, we mark them as
1120 // code gen only to ensure they aren't matched by the assembler.
1121 let isCodeGenOnly = 1 in {
1122 def ADD8rr_alt: I<0x02, MRMSrcReg,
1123 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1124 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
1125 def ADD16rr_alt: I<0x03, MRMSrcReg,
1126 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1127 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1128 def ADD32rr_alt: I<0x03, MRMSrcReg,
1129 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1130 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
1131 def ADD64rr_alt : RI<0x03, MRMSrcReg,
1132 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1133 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
1136 // Register-Memory Addition
1137 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
1138 (ins GR8 :$src1, i8mem :$src2),
1139 "add{b}\t{$src2, $dst|$dst, $src2}",
1140 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
1141 (load addr:$src2)))]>;
1142 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
1143 (ins GR16:$src1, i16mem:$src2),
1144 "add{w}\t{$src2, $dst|$dst, $src2}",
1145 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
1146 (load addr:$src2)))]>, OpSize;
1147 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
1148 (ins GR32:$src1, i32mem:$src2),
1149 "add{l}\t{$src2, $dst|$dst, $src2}",
1150 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
1151 (load addr:$src2)))]>;
1152 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst),
1153 (ins GR64:$src1, i64mem:$src2),
1154 "add{q}\t{$src2, $dst|$dst, $src2}",
1155 [(set GR64:$dst, EFLAGS,
1156 (X86add_flag GR64:$src1, (load addr:$src2)))]>;
1158 // Register-Integer Addition
1159 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1160 "add{b}\t{$src2, $dst|$dst, $src2}",
1161 [(set GR8:$dst, EFLAGS,
1162 (X86add_flag GR8:$src1, imm:$src2))]>;
1164 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1165 // Register-Integer Addition
1166 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
1167 (ins GR16:$src1, i16imm:$src2),
1168 "add{w}\t{$src2, $dst|$dst, $src2}",
1169 [(set GR16:$dst, EFLAGS,
1170 (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
1171 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
1172 (ins GR32:$src1, i32imm:$src2),
1173 "add{l}\t{$src2, $dst|$dst, $src2}",
1174 [(set GR32:$dst, EFLAGS,
1175 (X86add_flag GR32:$src1, imm:$src2))]>;
1176 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
1177 (ins GR16:$src1, i16i8imm:$src2),
1178 "add{w}\t{$src2, $dst|$dst, $src2}",
1179 [(set GR16:$dst, EFLAGS,
1180 (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1181 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
1182 (ins GR32:$src1, i32i8imm:$src2),
1183 "add{l}\t{$src2, $dst|$dst, $src2}",
1184 [(set GR32:$dst, EFLAGS,
1185 (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
1186 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst),
1187 (ins GR64:$src1, i64i8imm:$src2),
1188 "add{q}\t{$src2, $dst|$dst, $src2}",
1189 [(set GR64:$dst, EFLAGS,
1190 (X86add_flag GR64:$src1, i64immSExt8:$src2))]>;
1191 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst),
1192 (ins GR64:$src1, i64i32imm:$src2),
1193 "add{q}\t{$src2, $dst|$dst, $src2}",
1194 [(set GR64:$dst, EFLAGS,
1195 (X86add_flag GR64:$src1, i64immSExt32:$src2))]>;
1197 } // Constraints = "$src1 = $dst"
1199 // Memory-Register Addition
1200 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
1201 "add{b}\t{$src2, $dst|$dst, $src2}",
1202 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
1203 (implicit EFLAGS)]>;
1204 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1205 "add{w}\t{$src2, $dst|$dst, $src2}",
1206 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
1207 (implicit EFLAGS)]>, OpSize;
1208 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1209 "add{l}\t{$src2, $dst|$dst, $src2}",
1210 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
1211 (implicit EFLAGS)]>;
1212 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1213 "add{q}\t{$src2, $dst|$dst, $src2}",
1214 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
1215 (implicit EFLAGS)]>;
1216 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
1217 "add{b}\t{$src2, $dst|$dst, $src2}",
1218 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
1219 (implicit EFLAGS)]>;
1220 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
1221 "add{w}\t{$src2, $dst|$dst, $src2}",
1222 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
1223 (implicit EFLAGS)]>, OpSize;
1224 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
1225 "add{l}\t{$src2, $dst|$dst, $src2}",
1226 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
1227 (implicit EFLAGS)]>;
1228 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
1229 "add{q}\t{$src2, $dst|$dst, $src2}",
1230 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
1231 (implicit EFLAGS)]>;
1232 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1233 "add{w}\t{$src2, $dst|$dst, $src2}",
1234 [(store (add (load addr:$dst), i16immSExt8:$src2),
1236 (implicit EFLAGS)]>, OpSize;
1237 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1238 "add{l}\t{$src2, $dst|$dst, $src2}",
1239 [(store (add (load addr:$dst), i32immSExt8:$src2),
1241 (implicit EFLAGS)]>;
1242 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1243 "add{q}\t{$src2, $dst|$dst, $src2}",
1244 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
1245 (implicit EFLAGS)]>;
1248 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
1249 "add{b}\t{$src, %al|%al, $src}", []>;
1250 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
1251 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1252 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
1253 "add{l}\t{$src, %eax|%eax, $src}", []>;
1254 def ADD64i32 : RIi32<0x05, RawFrm, (outs), (ins i64i32imm:$src),
1255 "add{q}\t{$src, %rax|%rax, $src}", []>;
1257 let Uses = [EFLAGS] in {
1258 let Constraints = "$src1 = $dst" in {
1259 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1260 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1261 "adc{b}\t{$src2, $dst|$dst, $src2}",
1262 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
1263 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
1264 (ins GR16:$src1, GR16:$src2),
1265 "adc{w}\t{$src2, $dst|$dst, $src2}",
1266 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
1267 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
1268 (ins GR32:$src1, GR32:$src2),
1269 "adc{l}\t{$src2, $dst|$dst, $src2}",
1270 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
1271 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst),
1272 (ins GR64:$src1, GR64:$src2),
1273 "adc{q}\t{$src2, $dst|$dst, $src2}",
1274 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
1277 let isCodeGenOnly = 1 in {
1278 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1279 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
1280 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
1281 (ins GR16:$src1, GR16:$src2),
1282 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1283 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
1284 (ins GR32:$src1, GR32:$src2),
1285 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
1286 def ADC64rr_REV : RI<0x13, MRMSrcReg , (outs GR32:$dst),
1287 (ins GR64:$src1, GR64:$src2),
1288 "adc{q}\t{$src2, $dst|$dst, $src2}", []>;
1291 def ADC8rm : I<0x12, MRMSrcMem ,
1292 (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
1293 "adc{b}\t{$src2, $dst|$dst, $src2}",
1294 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
1295 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
1296 (ins GR16:$src1, i16mem:$src2),
1297 "adc{w}\t{$src2, $dst|$dst, $src2}",
1298 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
1300 def ADC32rm : I<0x13, MRMSrcMem ,
1301 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1302 "adc{l}\t{$src2, $dst|$dst, $src2}",
1303 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
1304 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst),
1305 (ins GR64:$src1, i64mem:$src2),
1306 "adc{q}\t{$src2, $dst|$dst, $src2}",
1307 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
1308 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1309 "adc{b}\t{$src2, $dst|$dst, $src2}",
1310 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
1311 def ADC16ri : Ii16<0x81, MRM2r,
1312 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1313 "adc{w}\t{$src2, $dst|$dst, $src2}",
1314 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
1315 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
1316 (ins GR16:$src1, i16i8imm:$src2),
1317 "adc{w}\t{$src2, $dst|$dst, $src2}",
1318 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
1320 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
1321 (ins GR32:$src1, i32imm:$src2),
1322 "adc{l}\t{$src2, $dst|$dst, $src2}",
1323 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
1324 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
1325 (ins GR32:$src1, i32i8imm:$src2),
1326 "adc{l}\t{$src2, $dst|$dst, $src2}",
1327 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
1328 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst),
1329 (ins GR64:$src1, i64i32imm:$src2),
1330 "adc{q}\t{$src2, $dst|$dst, $src2}",
1331 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
1332 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst),
1333 (ins GR64:$src1, i64i8imm:$src2),
1334 "adc{q}\t{$src2, $dst|$dst, $src2}",
1335 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
1336 } // Constraints = "$src1 = $dst"
1338 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
1339 "adc{b}\t{$src2, $dst|$dst, $src2}",
1340 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
1341 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1342 "adc{w}\t{$src2, $dst|$dst, $src2}",
1343 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
1345 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1346 "adc{l}\t{$src2, $dst|$dst, $src2}",
1347 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
1348 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1349 "adc{q}\t{$src2, $dst|$dst, $src2}",
1350 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
1351 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
1352 "adc{b}\t{$src2, $dst|$dst, $src2}",
1353 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1354 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
1355 "adc{w}\t{$src2, $dst|$dst, $src2}",
1356 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1358 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1359 "adc{w}\t{$src2, $dst|$dst, $src2}",
1360 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1362 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
1363 "adc{l}\t{$src2, $dst|$dst, $src2}",
1364 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1365 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1366 "adc{l}\t{$src2, $dst|$dst, $src2}",
1367 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1369 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
1370 "adc{q}\t{$src2, $dst|$dst, $src2}",
1371 [(store (adde (load addr:$dst), i64immSExt32:$src2),
1373 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1374 "adc{q}\t{$src2, $dst|$dst, $src2}",
1375 [(store (adde (load addr:$dst), i64immSExt8:$src2),
1378 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
1379 "adc{b}\t{$src, %al|%al, $src}", []>;
1380 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
1381 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1382 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
1383 "adc{l}\t{$src, %eax|%eax, $src}", []>;
1384 def ADC64i32 : RIi32<0x15, RawFrm, (outs), (ins i64i32imm:$src),
1385 "adc{q}\t{$src, %rax|%rax, $src}", []>;
1386 } // Uses = [EFLAGS]
1388 let Constraints = "$src1 = $dst" in {
1390 // Register-Register Subtraction
1391 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1392 "sub{b}\t{$src2, $dst|$dst, $src2}",
1393 [(set GR8:$dst, EFLAGS,
1394 (X86sub_flag GR8:$src1, GR8:$src2))]>;
1395 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
1396 "sub{w}\t{$src2, $dst|$dst, $src2}",
1397 [(set GR16:$dst, EFLAGS,
1398 (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
1399 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
1400 "sub{l}\t{$src2, $dst|$dst, $src2}",
1401 [(set GR32:$dst, EFLAGS,
1402 (X86sub_flag GR32:$src1, GR32:$src2))]>;
1403 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst),
1404 (ins GR64:$src1, GR64:$src2),
1405 "sub{q}\t{$src2, $dst|$dst, $src2}",
1406 [(set GR64:$dst, EFLAGS,
1407 (X86sub_flag GR64:$src1, GR64:$src2))]>;
1409 let isCodeGenOnly = 1 in {
1410 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1411 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
1412 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
1413 (ins GR16:$src1, GR16:$src2),
1414 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1415 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
1416 (ins GR32:$src1, GR32:$src2),
1417 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
1418 def SUB64rr_REV : RI<0x2B, MRMSrcReg, (outs GR64:$dst),
1419 (ins GR64:$src1, GR64:$src2),
1420 "sub{q}\t{$src2, $dst|$dst, $src2}", []>;
1423 // Register-Memory Subtraction
1424 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
1425 (ins GR8 :$src1, i8mem :$src2),
1426 "sub{b}\t{$src2, $dst|$dst, $src2}",
1427 [(set GR8:$dst, EFLAGS,
1428 (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
1429 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
1430 (ins GR16:$src1, i16mem:$src2),
1431 "sub{w}\t{$src2, $dst|$dst, $src2}",
1432 [(set GR16:$dst, EFLAGS,
1433 (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
1434 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
1435 (ins GR32:$src1, i32mem:$src2),
1436 "sub{l}\t{$src2, $dst|$dst, $src2}",
1437 [(set GR32:$dst, EFLAGS,
1438 (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
1439 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst),
1440 (ins GR64:$src1, i64mem:$src2),
1441 "sub{q}\t{$src2, $dst|$dst, $src2}",
1442 [(set GR64:$dst, EFLAGS,
1443 (X86sub_flag GR64:$src1, (load addr:$src2)))]>;
1445 // Register-Integer Subtraction
1446 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
1447 (ins GR8:$src1, i8imm:$src2),
1448 "sub{b}\t{$src2, $dst|$dst, $src2}",
1449 [(set GR8:$dst, EFLAGS,
1450 (X86sub_flag GR8:$src1, imm:$src2))]>;
1451 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
1452 (ins GR16:$src1, i16imm:$src2),
1453 "sub{w}\t{$src2, $dst|$dst, $src2}",
1454 [(set GR16:$dst, EFLAGS,
1455 (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
1456 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
1457 (ins GR32:$src1, i32imm:$src2),
1458 "sub{l}\t{$src2, $dst|$dst, $src2}",
1459 [(set GR32:$dst, EFLAGS,
1460 (X86sub_flag GR32:$src1, imm:$src2))]>;
1461 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
1462 (ins GR64:$src1, i64i32imm:$src2),
1463 "sub{q}\t{$src2, $dst|$dst, $src2}",
1464 [(set GR64:$dst, EFLAGS,
1465 (X86sub_flag GR64:$src1, i64immSExt32:$src2))]>;
1466 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
1467 (ins GR16:$src1, i16i8imm:$src2),
1468 "sub{w}\t{$src2, $dst|$dst, $src2}",
1469 [(set GR16:$dst, EFLAGS,
1470 (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1471 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
1472 (ins GR32:$src1, i32i8imm:$src2),
1473 "sub{l}\t{$src2, $dst|$dst, $src2}",
1474 [(set GR32:$dst, EFLAGS,
1475 (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
1476 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
1477 (ins GR64:$src1, i64i8imm:$src2),
1478 "sub{q}\t{$src2, $dst|$dst, $src2}",
1479 [(set GR64:$dst, EFLAGS,
1480 (X86sub_flag GR64:$src1, i64immSExt8:$src2))]>;
1481 } // Constraints = "$src1 = $dst"
1483 // Memory-Register Subtraction
1484 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1485 "sub{b}\t{$src2, $dst|$dst, $src2}",
1486 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
1487 (implicit EFLAGS)]>;
1488 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1489 "sub{w}\t{$src2, $dst|$dst, $src2}",
1490 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
1491 (implicit EFLAGS)]>, OpSize;
1492 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1493 "sub{l}\t{$src2, $dst|$dst, $src2}",
1494 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
1495 (implicit EFLAGS)]>;
1496 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1497 "sub{q}\t{$src2, $dst|$dst, $src2}",
1498 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
1499 (implicit EFLAGS)]>;
1501 // Memory-Integer Subtraction
1502 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
1503 "sub{b}\t{$src2, $dst|$dst, $src2}",
1504 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
1505 (implicit EFLAGS)]>;
1506 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
1507 "sub{w}\t{$src2, $dst|$dst, $src2}",
1508 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
1509 (implicit EFLAGS)]>, OpSize;
1510 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
1511 "sub{l}\t{$src2, $dst|$dst, $src2}",
1512 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
1513 (implicit EFLAGS)]>;
1514 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
1515 "sub{q}\t{$src2, $dst|$dst, $src2}",
1516 [(store (sub (load addr:$dst), i64immSExt32:$src2),
1518 (implicit EFLAGS)]>;
1519 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1520 "sub{w}\t{$src2, $dst|$dst, $src2}",
1521 [(store (sub (load addr:$dst), i16immSExt8:$src2),
1523 (implicit EFLAGS)]>, OpSize;
1524 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1525 "sub{l}\t{$src2, $dst|$dst, $src2}",
1526 [(store (sub (load addr:$dst), i32immSExt8:$src2),
1528 (implicit EFLAGS)]>;
1529 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1530 "sub{q}\t{$src2, $dst|$dst, $src2}",
1531 [(store (sub (load addr:$dst), i64immSExt8:$src2),
1533 (implicit EFLAGS)]>;
1535 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
1536 "sub{b}\t{$src, %al|%al, $src}", []>;
1537 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
1538 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1539 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
1540 "sub{l}\t{$src, %eax|%eax, $src}", []>;
1541 def SUB64i32 : RIi32<0x2D, RawFrm, (outs), (ins i64i32imm:$src),
1542 "sub{q}\t{$src, %rax|%rax, $src}", []>;
1544 let Uses = [EFLAGS] in {
1545 let Constraints = "$src1 = $dst" in {
1546 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
1547 (ins GR8:$src1, GR8:$src2),
1548 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1549 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
1550 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
1551 (ins GR16:$src1, GR16:$src2),
1552 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1553 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
1554 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
1555 (ins GR32:$src1, GR32:$src2),
1556 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1557 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
1558 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst),
1559 (ins GR64:$src1, GR64:$src2),
1560 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1561 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
1562 } // Constraints = "$src1 = $dst"
1565 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
1566 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1567 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
1568 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1569 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1570 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
1572 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1573 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1574 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
1575 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1576 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1577 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
1579 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
1580 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1581 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1582 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
1583 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1584 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1586 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1587 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1588 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1590 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
1591 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1592 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1593 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1594 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1595 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1596 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
1597 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1598 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
1599 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1600 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1601 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
1603 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
1604 "sbb{b}\t{$src, %al|%al, $src}", []>;
1605 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
1606 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1607 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
1608 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
1609 def SBB64i32 : RIi32<0x1D, RawFrm, (outs), (ins i64i32imm:$src),
1610 "sbb{q}\t{$src, %rax|%rax, $src}", []>;
1612 let Constraints = "$src1 = $dst" in {
1614 let isCodeGenOnly = 1 in {
1615 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1616 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
1617 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
1618 (ins GR16:$src1, GR16:$src2),
1619 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1620 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
1621 (ins GR32:$src1, GR32:$src2),
1622 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
1623 def SBB64rr_REV : RI<0x1B, MRMSrcReg, (outs GR64:$dst),
1624 (ins GR64:$src1, GR64:$src2),
1625 "sbb{q}\t{$src2, $dst|$dst, $src2}", []>;
1628 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
1629 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1630 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
1631 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
1632 (ins GR16:$src1, i16mem:$src2),
1633 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1634 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
1636 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
1637 (ins GR32:$src1, i32mem:$src2),
1638 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1639 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
1640 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst),
1641 (ins GR64:$src1, i64mem:$src2),
1642 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1643 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
1644 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1645 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1646 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
1647 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
1648 (ins GR16:$src1, i16imm:$src2),
1649 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1650 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
1651 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
1652 (ins GR16:$src1, i16i8imm:$src2),
1653 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1654 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
1656 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
1657 (ins GR32:$src1, i32imm:$src2),
1658 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1659 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
1660 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
1661 (ins GR32:$src1, i32i8imm:$src2),
1662 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1663 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
1664 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst),
1665 (ins GR64:$src1, i64i32imm:$src2),
1666 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1667 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
1668 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst),
1669 (ins GR64:$src1, i64i8imm:$src2),
1670 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1671 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
1673 } // Constraints = "$src1 = $dst"
1674 } // Uses = [EFLAGS]
1675 } // Defs = [EFLAGS]
1677 //===----------------------------------------------------------------------===//
1678 // Test instructions are just like AND, except they don't generate a result.
1680 let Defs = [EFLAGS] in {
1681 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
1682 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
1683 "test{b}\t{$src2, $src1|$src1, $src2}",
1684 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
1685 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
1686 "test{w}\t{$src2, $src1|$src1, $src2}",
1687 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
1690 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
1691 "test{l}\t{$src2, $src1|$src1, $src2}",
1692 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
1694 def TEST64rr : RI<0x85, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1695 "test{q}\t{$src2, $src1|$src1, $src2}",
1696 [(set EFLAGS, (X86cmp (and GR64:$src1, GR64:$src2), 0))]>;
1699 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
1700 "test{b}\t{$src2, $src1|$src1, $src2}",
1701 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
1703 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
1704 "test{w}\t{$src2, $src1|$src1, $src2}",
1705 [(set EFLAGS, (X86cmp (and GR16:$src1,
1706 (loadi16 addr:$src2)), 0))]>, OpSize;
1707 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
1708 "test{l}\t{$src2, $src1|$src1, $src2}",
1709 [(set EFLAGS, (X86cmp (and GR32:$src1,
1710 (loadi32 addr:$src2)), 0))]>;
1711 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1712 "test{q}\t{$src2, $src1|$src1, $src2}",
1713 [(set EFLAGS, (X86cmp (and GR64:$src1, (loadi64 addr:$src2)),
1716 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
1717 (outs), (ins GR8:$src1, i8imm:$src2),
1718 "test{b}\t{$src2, $src1|$src1, $src2}",
1719 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
1720 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
1721 (outs), (ins GR16:$src1, i16imm:$src2),
1722 "test{w}\t{$src2, $src1|$src1, $src2}",
1723 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
1725 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
1726 (outs), (ins GR32:$src1, i32imm:$src2),
1727 "test{l}\t{$src2, $src1|$src1, $src2}",
1728 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
1729 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1730 (ins GR64:$src1, i64i32imm:$src2),
1731 "test{q}\t{$src2, $src1|$src1, $src2}",
1732 [(set EFLAGS, (X86cmp (and GR64:$src1, i64immSExt32:$src2),
1735 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
1736 (outs), (ins i8mem:$src1, i8imm:$src2),
1737 "test{b}\t{$src2, $src1|$src1, $src2}",
1738 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
1740 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
1741 (outs), (ins i16mem:$src1, i16imm:$src2),
1742 "test{w}\t{$src2, $src1|$src1, $src2}",
1743 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
1745 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
1746 (outs), (ins i32mem:$src1, i32imm:$src2),
1747 "test{l}\t{$src2, $src1|$src1, $src2}",
1748 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
1750 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1751 (ins i64mem:$src1, i64i32imm:$src2),
1752 "test{q}\t{$src2, $src1|$src1, $src2}",
1753 [(set EFLAGS, (X86cmp (and (loadi64 addr:$src1),
1754 i64immSExt32:$src2), 0))]>;
1756 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
1757 "test{b}\t{$src, %al|%al, $src}", []>;
1758 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
1759 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1760 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
1761 "test{l}\t{$src, %eax|%eax, $src}", []>;
1762 def TEST64i32 : RIi32<0xa9, RawFrm, (outs), (ins i64i32imm:$src),
1763 "test{q}\t{$src, %rax|%rax, $src}", []>;
1765 } // Defs = [EFLAGS]
1768 //===----------------------------------------------------------------------===//
1769 // Integer comparisons
1771 let Defs = [EFLAGS] in {
1773 def CMP8rr : I<0x38, MRMDestReg,
1774 (outs), (ins GR8 :$src1, GR8 :$src2),
1775 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1776 [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
1777 def CMP16rr : I<0x39, MRMDestReg,
1778 (outs), (ins GR16:$src1, GR16:$src2),
1779 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1780 [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
1781 def CMP32rr : I<0x39, MRMDestReg,
1782 (outs), (ins GR32:$src1, GR32:$src2),
1783 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1784 [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
1785 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1786 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1787 [(set EFLAGS, (X86cmp GR64:$src1, GR64:$src2))]>;
1789 def CMP8mr : I<0x38, MRMDestMem,
1790 (outs), (ins i8mem :$src1, GR8 :$src2),
1791 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1792 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
1793 def CMP16mr : I<0x39, MRMDestMem,
1794 (outs), (ins i16mem:$src1, GR16:$src2),
1795 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1796 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
1798 def CMP32mr : I<0x39, MRMDestMem,
1799 (outs), (ins i32mem:$src1, GR32:$src2),
1800 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1801 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
1802 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1803 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1804 [(set EFLAGS, (X86cmp (loadi64 addr:$src1), GR64:$src2))]>;
1806 def CMP8rm : I<0x3A, MRMSrcMem,
1807 (outs), (ins GR8 :$src1, i8mem :$src2),
1808 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1809 [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
1810 def CMP16rm : I<0x3B, MRMSrcMem,
1811 (outs), (ins GR16:$src1, i16mem:$src2),
1812 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1813 [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
1815 def CMP32rm : I<0x3B, MRMSrcMem,
1816 (outs), (ins GR32:$src1, i32mem:$src2),
1817 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1818 [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
1819 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1820 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1821 [(set EFLAGS, (X86cmp GR64:$src1, (loadi64 addr:$src2)))]>;
1823 // These are alternate spellings for use by the disassembler, we mark them as
1824 // code gen only to ensure they aren't matched by the assembler.
1825 let isCodeGenOnly = 1 in {
1826 def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
1827 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
1828 def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
1829 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
1830 def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
1831 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
1832 def CMP64rr_alt : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1833 "cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
1836 def CMP8ri : Ii8<0x80, MRM7r,
1837 (outs), (ins GR8:$src1, i8imm:$src2),
1838 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1839 [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
1840 def CMP16ri : Ii16<0x81, MRM7r,
1841 (outs), (ins GR16:$src1, i16imm:$src2),
1842 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1843 [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
1844 def CMP32ri : Ii32<0x81, MRM7r,
1845 (outs), (ins GR32:$src1, i32imm:$src2),
1846 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1847 [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
1848 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1849 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1850 [(set EFLAGS, (X86cmp GR64:$src1, i64immSExt32:$src2))]>;
1852 def CMP8mi : Ii8 <0x80, MRM7m,
1853 (outs), (ins i8mem :$src1, i8imm :$src2),
1854 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1855 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
1856 def CMP16mi : Ii16<0x81, MRM7m,
1857 (outs), (ins i16mem:$src1, i16imm:$src2),
1858 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1859 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
1861 def CMP32mi : Ii32<0x81, MRM7m,
1862 (outs), (ins i32mem:$src1, i32imm:$src2),
1863 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1864 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
1865 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1866 (ins i64mem:$src1, i64i32imm:$src2),
1867 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1868 [(set EFLAGS, (X86cmp (loadi64 addr:$src1),
1869 i64immSExt32:$src2))]>;
1871 def CMP16ri8 : Ii8<0x83, MRM7r,
1872 (outs), (ins GR16:$src1, i16i8imm:$src2),
1873 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1874 [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
1876 def CMP32ri8 : Ii8<0x83, MRM7r,
1877 (outs), (ins GR32:$src1, i32i8imm:$src2),
1878 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1879 [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
1880 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1881 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1882 [(set EFLAGS, (X86cmp GR64:$src1, i64immSExt8:$src2))]>;
1884 def CMP16mi8 : Ii8<0x83, MRM7m,
1885 (outs), (ins i16mem:$src1, i16i8imm:$src2),
1886 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1887 [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
1888 i16immSExt8:$src2))]>, OpSize;
1889 def CMP32mi8 : Ii8<0x83, MRM7m,
1890 (outs), (ins i32mem:$src1, i32i8imm:$src2),
1891 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1892 [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
1893 i32immSExt8:$src2))]>;
1894 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1895 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1896 [(set EFLAGS, (X86cmp (loadi64 addr:$src1),
1897 i64immSExt8:$src2))]>;
1899 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
1900 "cmp{b}\t{$src, %al|%al, $src}", []>;
1901 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
1902 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1903 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
1904 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
1905 def CMP64i32 : RIi32<0x3D, RawFrm, (outs), (ins i64i32imm:$src),
1906 "cmp{q}\t{$src, %rax|%rax, $src}", []>;
1908 } // Defs = [EFLAGS]