1 //===- X86InstrArithmetic.td - Integer Arithmetic Instrs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the integer arithmetic instructions in the X86
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // LEA - Load Effective Address
18 let neverHasSideEffects = 1 in
19 def LEA16r : I<0x8D, MRMSrcMem,
20 (outs GR16:$dst), (ins i32mem:$src),
21 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
22 let isReMaterializable = 1 in
23 def LEA32r : I<0x8D, MRMSrcMem,
24 (outs GR32:$dst), (ins i32mem:$src),
25 "lea{l}\t{$src|$dst}, {$dst|$src}",
26 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
28 def LEA64_32r : I<0x8D, MRMSrcMem,
29 (outs GR32:$dst), (ins lea64_32mem:$src),
30 "lea{l}\t{$src|$dst}, {$dst|$src}",
31 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
33 let isReMaterializable = 1 in
34 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
35 "lea{q}\t{$src|$dst}, {$dst|$src}",
36 [(set GR64:$dst, lea64addr:$src)]>;
40 //===----------------------------------------------------------------------===//
41 // Fixed-Register Multiplication and Division Instructions.
44 // Extra precision multiplication
46 // AL is really implied by AX, but the registers in Defs must match the
47 // SDNode results (i8, i32).
48 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
49 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
50 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
51 // This probably ought to be moved to a def : Pat<> if the
52 // syntax can be accepted.
53 [(set AL, (mul AL, GR8:$src)),
54 (implicit EFLAGS)]>; // AL,AH = AL*GR8
56 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
57 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
59 []>, OpSize; // AX,DX = AX*GR16
61 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
62 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
64 []>; // EAX,EDX = EAX*GR32
65 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
66 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
67 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
69 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
70 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
72 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
73 // This probably ought to be moved to a def : Pat<> if the
74 // syntax can be accepted.
75 [(set AL, (mul AL, (loadi8 addr:$src))),
76 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
78 let mayLoad = 1, neverHasSideEffects = 1 in {
79 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
80 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
82 []>, OpSize; // AX,DX = AX*[mem16]
84 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
85 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
87 []>; // EAX,EDX = EAX*[mem32]
88 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
89 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
90 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
93 let neverHasSideEffects = 1 in {
94 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
95 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
97 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
98 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
99 OpSize; // AX,DX = AX*GR16
100 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
101 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
102 // EAX,EDX = EAX*GR32
103 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
104 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", []>;
105 // RAX,RDX = RAX*GR64
108 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
109 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
110 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
111 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
112 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
113 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
114 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
115 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
116 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
117 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
118 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
119 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
121 } // neverHasSideEffects
124 let Defs = [EFLAGS] in {
125 let Constraints = "$src1 = $dst" in {
127 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
128 // Register-Register Signed Integer Multiply
129 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
130 "imul{w}\t{$src2, $dst|$dst, $src2}",
131 [(set GR16:$dst, EFLAGS,
132 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
133 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
134 "imul{l}\t{$src2, $dst|$dst, $src2}",
135 [(set GR32:$dst, EFLAGS,
136 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
137 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
138 (ins GR64:$src1, GR64:$src2),
139 "imul{q}\t{$src2, $dst|$dst, $src2}",
140 [(set GR64:$dst, EFLAGS,
141 (X86smul_flag GR64:$src1, GR64:$src2))]>, TB;
144 // Register-Memory Signed Integer Multiply
145 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
146 (ins GR16:$src1, i16mem:$src2),
147 "imul{w}\t{$src2, $dst|$dst, $src2}",
148 [(set GR16:$dst, EFLAGS,
149 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
151 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
152 (ins GR32:$src1, i32mem:$src2),
153 "imul{l}\t{$src2, $dst|$dst, $src2}",
154 [(set GR32:$dst, EFLAGS,
155 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
156 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
157 (ins GR64:$src1, i64mem:$src2),
158 "imul{q}\t{$src2, $dst|$dst, $src2}",
159 [(set GR64:$dst, EFLAGS,
160 (X86smul_flag GR64:$src1, (load addr:$src2)))]>, TB;
161 } // Constraints = "$src1 = $dst"
165 // Suprisingly enough, these are not two address instructions!
166 let Defs = [EFLAGS] in {
167 // Register-Integer Signed Integer Multiply
168 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
169 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
170 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
171 [(set GR16:$dst, EFLAGS,
172 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
173 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
174 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
175 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
176 [(set GR16:$dst, EFLAGS,
177 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
179 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
180 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
181 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
182 [(set GR32:$dst, EFLAGS,
183 (X86smul_flag GR32:$src1, imm:$src2))]>;
184 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
185 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
186 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
187 [(set GR32:$dst, EFLAGS,
188 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
189 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
190 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
191 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
192 [(set GR64:$dst, EFLAGS,
193 (X86smul_flag GR64:$src1, i64immSExt32:$src2))]>;
194 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
195 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
196 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
197 [(set GR64:$dst, EFLAGS,
198 (X86smul_flag GR64:$src1, i64immSExt8:$src2))]>;
201 // Memory-Integer Signed Integer Multiply
202 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
203 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
204 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
205 [(set GR16:$dst, EFLAGS,
206 (X86smul_flag (load addr:$src1), imm:$src2))]>,
208 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
209 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
210 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
211 [(set GR16:$dst, EFLAGS,
212 (X86smul_flag (load addr:$src1),
213 i16immSExt8:$src2))]>, OpSize;
214 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
215 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
216 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
217 [(set GR32:$dst, EFLAGS,
218 (X86smul_flag (load addr:$src1), imm:$src2))]>;
219 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
220 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
221 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
222 [(set GR32:$dst, EFLAGS,
223 (X86smul_flag (load addr:$src1),
224 i32immSExt8:$src2))]>;
225 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
226 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
227 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 [(set GR64:$dst, EFLAGS,
229 (X86smul_flag (load addr:$src1),
230 i64immSExt32:$src2))]>;
231 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
232 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
233 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
234 [(set GR64:$dst, EFLAGS,
235 (X86smul_flag (load addr:$src1),
236 i64immSExt8:$src2))]>;
242 // unsigned division/remainder
243 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
244 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
246 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
247 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
248 "div{w}\t$src", []>, OpSize;
249 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
250 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
252 // RDX:RAX/r64 = RAX,RDX
253 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
254 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
258 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
259 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
261 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
262 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
263 "div{w}\t$src", []>, OpSize;
264 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
265 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
267 // RDX:RAX/[mem64] = RAX,RDX
268 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
269 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
273 // Signed division/remainder.
274 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
275 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
276 "idiv{b}\t$src", []>;
277 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
278 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
279 "idiv{w}\t$src", []>, OpSize;
280 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
281 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
282 "idiv{l}\t$src", []>;
283 // RDX:RAX/r64 = RAX,RDX
284 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
285 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
286 "idiv{q}\t$src", []>;
288 let mayLoad = 1, mayLoad = 1 in {
289 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
290 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
291 "idiv{b}\t$src", []>;
292 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
293 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
294 "idiv{w}\t$src", []>, OpSize;
295 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
296 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
297 "idiv{l}\t$src", []>;
298 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] = RAX,RDX
299 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
300 "idiv{q}\t$src", []>;
303 //===----------------------------------------------------------------------===//
304 // Two address Instructions.
307 // unary instructions
308 let CodeSize = 2 in {
309 let Defs = [EFLAGS] in {
310 let Constraints = "$src1 = $dst" in {
311 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
313 [(set GR8:$dst, (ineg GR8:$src1)),
315 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
317 [(set GR16:$dst, (ineg GR16:$src1)),
318 (implicit EFLAGS)]>, OpSize;
319 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
321 [(set GR32:$dst, (ineg GR32:$src1)),
323 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
324 [(set GR64:$dst, (ineg GR64:$src1)),
326 } // Constraints = "$src1 = $dst"
328 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
330 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
332 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
334 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
335 (implicit EFLAGS)]>, OpSize;
336 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
338 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
340 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
341 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
346 // Note: NOT does not set EFLAGS!
348 let Constraints = "$src1 = $dst" in {
349 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
350 let AddedComplexity = 15 in {
351 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
353 [(set GR8:$dst, (not GR8:$src1))]>;
354 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
356 [(set GR16:$dst, (not GR16:$src1))]>, OpSize;
357 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
359 [(set GR32:$dst, (not GR32:$src1))]>;
360 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",
361 [(set GR64:$dst, (not GR64:$src1))]>;
363 } // Constraints = "$src1 = $dst"
365 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
367 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
368 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
370 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
371 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
373 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
374 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
375 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
378 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
379 let Defs = [EFLAGS] in {
380 let Constraints = "$src1 = $dst" in {
382 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
384 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>;
386 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
387 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
389 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
390 OpSize, Requires<[In32BitMode]>;
391 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
393 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
394 Requires<[In32BitMode]>;
395 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
396 [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))]>;
397 } // isConvertibleToThreeAddress = 1, CodeSize = 1
400 // In 64-bit mode, single byte INC and DEC cannot be encoded.
401 let isConvertibleToThreeAddress = 1, CodeSize = 2 in {
402 // Can transform into LEA.
403 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
405 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
406 OpSize, Requires<[In64BitMode]>;
407 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
409 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
410 Requires<[In64BitMode]>;
411 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
413 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
414 OpSize, Requires<[In64BitMode]>;
415 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
417 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
418 Requires<[In64BitMode]>;
419 } // isConvertibleToThreeAddress = 1, CodeSize = 2
421 } // Constraints = "$src1 = $dst"
423 let CodeSize = 2 in {
424 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
425 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
427 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
428 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
430 OpSize, Requires<[In32BitMode]>;
431 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
432 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
434 Requires<[In32BitMode]>;
435 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
436 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
439 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
440 // how to unfold them.
441 // FIXME: What is this for??
442 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
443 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
445 OpSize, Requires<[In64BitMode]>;
446 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
447 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
449 Requires<[In64BitMode]>;
450 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
451 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
453 OpSize, Requires<[In64BitMode]>;
454 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
455 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
457 Requires<[In64BitMode]>;
460 let Constraints = "$src1 = $dst" in {
462 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
464 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>;
465 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
466 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
468 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
469 OpSize, Requires<[In32BitMode]>;
470 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
472 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
473 Requires<[In32BitMode]>;
474 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst",
475 [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))]>;
477 } // Constraints = "$src1 = $dst"
480 let CodeSize = 2 in {
481 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
482 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
484 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
485 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
487 OpSize, Requires<[In32BitMode]>;
488 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
489 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
491 Requires<[In32BitMode]>;
492 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
493 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
499 class BinOpRR<bits<8> opcode, Format format, string mnemonic,
500 X86RegisterClass regclass, SDNode opnode>
501 : I<opcode, format, (outs regclass:$dst), (ins regclass:$src1,regclass:$src2),
502 !strconcat(mnemonic, "{", regclass.InstrSuffix,
503 "}\t{$src2, $dst|$dst, $src2}"),
504 [(set regclass:$dst, EFLAGS, (opnode regclass:$src1, regclass:$src2))]>;
506 // Logical operators.
507 let Defs = [EFLAGS] in {
508 let Constraints = "$src1 = $dst" in {
510 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
511 def AND8rr : BinOpRR<0x20, MRMDestReg, "and", GR8 , X86and_flag>;
512 def AND16rr : BinOpRR<0x21, MRMDestReg, "and", GR16, X86and_flag>, OpSize;
513 def AND32rr : BinOpRR<0x21, MRMDestReg, "and", GR32, X86and_flag>;
514 def AND64rr : BinOpRR<0x21, MRMDestReg, "and", GR64, X86and_flag>, REX_W;
518 // AND instructions with the destination register in REG and the source register
519 // in R/M. Included for the disassembler.
520 let isCodeGenOnly = 1 in {
521 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
522 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
523 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
524 (ins GR16:$src1, GR16:$src2),
525 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
526 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
527 (ins GR32:$src1, GR32:$src2),
528 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
529 def AND64rr_REV : RI<0x23, MRMSrcReg, (outs GR64:$dst),
530 (ins GR64:$src1, GR64:$src2),
531 "and{q}\t{$src2, $dst|$dst, $src2}", []>;
534 def AND8rm : I<0x22, MRMSrcMem,
535 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
536 "and{b}\t{$src2, $dst|$dst, $src2}",
537 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
538 (loadi8 addr:$src2)))]>;
539 def AND16rm : I<0x23, MRMSrcMem,
540 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
541 "and{w}\t{$src2, $dst|$dst, $src2}",
542 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
543 (loadi16 addr:$src2)))]>,
545 def AND32rm : I<0x23, MRMSrcMem,
546 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
547 "and{l}\t{$src2, $dst|$dst, $src2}",
548 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
549 (loadi32 addr:$src2)))]>;
550 def AND64rm : RI<0x23, MRMSrcMem,
551 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
552 "and{q}\t{$src2, $dst|$dst, $src2}",
553 [(set GR64:$dst, EFLAGS,
554 (X86and_flag GR64:$src1, (load addr:$src2)))]>;
556 def AND8ri : Ii8<0x80, MRM4r,
557 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
558 "and{b}\t{$src2, $dst|$dst, $src2}",
559 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
561 def AND16ri : Ii16<0x81, MRM4r,
562 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
563 "and{w}\t{$src2, $dst|$dst, $src2}",
564 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
565 imm:$src2))]>, OpSize;
566 def AND32ri : Ii32<0x81, MRM4r,
567 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
568 "and{l}\t{$src2, $dst|$dst, $src2}",
569 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
571 def AND64ri32 : RIi32<0x81, MRM4r,
572 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
573 "and{q}\t{$src2, $dst|$dst, $src2}",
574 [(set GR64:$dst, EFLAGS,
575 (X86and_flag GR64:$src1, i64immSExt32:$src2))]>;
577 def AND16ri8 : Ii8<0x83, MRM4r,
578 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
579 "and{w}\t{$src2, $dst|$dst, $src2}",
580 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
581 i16immSExt8:$src2))]>,
583 def AND32ri8 : Ii8<0x83, MRM4r,
584 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
585 "and{l}\t{$src2, $dst|$dst, $src2}",
586 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
587 i32immSExt8:$src2))]>;
588 def AND64ri8 : RIi8<0x83, MRM4r,
589 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
590 "and{q}\t{$src2, $dst|$dst, $src2}",
591 [(set GR64:$dst, EFLAGS,
592 (X86and_flag GR64:$src1, i64immSExt8:$src2))]>;
593 } // Constraints = "$src1 = $dst"
595 def AND8mr : I<0x20, MRMDestMem,
596 (outs), (ins i8mem :$dst, GR8 :$src),
597 "and{b}\t{$src, $dst|$dst, $src}",
598 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
600 def AND16mr : I<0x21, MRMDestMem,
601 (outs), (ins i16mem:$dst, GR16:$src),
602 "and{w}\t{$src, $dst|$dst, $src}",
603 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
606 def AND32mr : I<0x21, MRMDestMem,
607 (outs), (ins i32mem:$dst, GR32:$src),
608 "and{l}\t{$src, $dst|$dst, $src}",
609 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
611 def AND64mr : RI<0x21, MRMDestMem,
612 (outs), (ins i64mem:$dst, GR64:$src),
613 "and{q}\t{$src, $dst|$dst, $src}",
614 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
617 def AND8mi : Ii8<0x80, MRM4m,
618 (outs), (ins i8mem :$dst, i8imm :$src),
619 "and{b}\t{$src, $dst|$dst, $src}",
620 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
622 def AND16mi : Ii16<0x81, MRM4m,
623 (outs), (ins i16mem:$dst, i16imm:$src),
624 "and{w}\t{$src, $dst|$dst, $src}",
625 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
628 def AND32mi : Ii32<0x81, MRM4m,
629 (outs), (ins i32mem:$dst, i32imm:$src),
630 "and{l}\t{$src, $dst|$dst, $src}",
631 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
633 def AND64mi32 : RIi32<0x81, MRM4m,
634 (outs), (ins i64mem:$dst, i64i32imm:$src),
635 "and{q}\t{$src, $dst|$dst, $src}",
636 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
639 def AND16mi8 : Ii8<0x83, MRM4m,
640 (outs), (ins i16mem:$dst, i16i8imm :$src),
641 "and{w}\t{$src, $dst|$dst, $src}",
642 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
645 def AND32mi8 : Ii8<0x83, MRM4m,
646 (outs), (ins i32mem:$dst, i32i8imm :$src),
647 "and{l}\t{$src, $dst|$dst, $src}",
648 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
650 def AND64mi8 : RIi8<0x83, MRM4m,
651 (outs), (ins i64mem:$dst, i64i8imm :$src),
652 "and{q}\t{$src, $dst|$dst, $src}",
653 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
656 // FIXME: Implicitly modifiers AL.
657 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
658 "and{b}\t{$src, %al|%al, $src}", []>;
659 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
660 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
661 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
662 "and{l}\t{$src, %eax|%eax, $src}", []>;
663 def AND64i32 : RIi32<0x25, RawFrm, (outs), (ins i64i32imm:$src),
664 "and{q}\t{$src, %rax|%rax, $src}", []>;
666 let Constraints = "$src1 = $dst" in {
668 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
669 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
670 (ins GR8 :$src1, GR8 :$src2),
671 "or{b}\t{$src2, $dst|$dst, $src2}",
672 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
673 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
674 (ins GR16:$src1, GR16:$src2),
675 "or{w}\t{$src2, $dst|$dst, $src2}",
676 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
678 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
679 (ins GR32:$src1, GR32:$src2),
680 "or{l}\t{$src2, $dst|$dst, $src2}",
681 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
682 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst),
683 (ins GR64:$src1, GR64:$src2),
684 "or{q}\t{$src2, $dst|$dst, $src2}",
685 [(set GR64:$dst, EFLAGS,
686 (X86or_flag GR64:$src1, GR64:$src2))]>;
689 // OR instructions with the destination register in REG and the source register
690 // in R/M. Included for the disassembler.
691 let isCodeGenOnly = 1 in {
692 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
693 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
694 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
695 (ins GR16:$src1, GR16:$src2),
696 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
697 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
698 (ins GR32:$src1, GR32:$src2),
699 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
700 def OR64rr_REV : RI<0x0B, MRMSrcReg, (outs GR64:$dst),
701 (ins GR64:$src1, GR64:$src2),
702 "or{q}\t{$src2, $dst|$dst, $src2}", []>;
705 def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
706 (ins GR8 :$src1, i8mem :$src2),
707 "or{b}\t{$src2, $dst|$dst, $src2}",
708 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
709 (load addr:$src2)))]>;
710 def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
711 (ins GR16:$src1, i16mem:$src2),
712 "or{w}\t{$src2, $dst|$dst, $src2}",
713 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
714 (load addr:$src2)))]>,
716 def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
717 (ins GR32:$src1, i32mem:$src2),
718 "or{l}\t{$src2, $dst|$dst, $src2}",
719 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
720 (load addr:$src2)))]>;
721 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst),
722 (ins GR64:$src1, i64mem:$src2),
723 "or{q}\t{$src2, $dst|$dst, $src2}",
724 [(set GR64:$dst, EFLAGS,
725 (X86or_flag GR64:$src1, (load addr:$src2)))]>;
727 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
728 (ins GR8 :$src1, i8imm:$src2),
729 "or{b}\t{$src2, $dst|$dst, $src2}",
730 [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
731 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
732 (ins GR16:$src1, i16imm:$src2),
733 "or{w}\t{$src2, $dst|$dst, $src2}",
734 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
735 imm:$src2))]>, OpSize;
736 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
737 (ins GR32:$src1, i32imm:$src2),
738 "or{l}\t{$src2, $dst|$dst, $src2}",
739 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
741 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst),
742 (ins GR64:$src1, i64i32imm:$src2),
743 "or{q}\t{$src2, $dst|$dst, $src2}",
744 [(set GR64:$dst, EFLAGS,
745 (X86or_flag GR64:$src1, i64immSExt32:$src2))]>;
747 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
748 (ins GR16:$src1, i16i8imm:$src2),
749 "or{w}\t{$src2, $dst|$dst, $src2}",
750 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
751 i16immSExt8:$src2))]>, OpSize;
752 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
753 (ins GR32:$src1, i32i8imm:$src2),
754 "or{l}\t{$src2, $dst|$dst, $src2}",
755 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
756 i32immSExt8:$src2))]>;
757 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst),
758 (ins GR64:$src1, i64i8imm:$src2),
759 "or{q}\t{$src2, $dst|$dst, $src2}",
760 [(set GR64:$dst, EFLAGS,
761 (X86or_flag GR64:$src1, i64immSExt8:$src2))]>;
762 } // Constraints = "$src1 = $dst"
764 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
765 "or{b}\t{$src, $dst|$dst, $src}",
766 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
768 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
769 "or{w}\t{$src, $dst|$dst, $src}",
770 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
771 (implicit EFLAGS)]>, OpSize;
772 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
773 "or{l}\t{$src, $dst|$dst, $src}",
774 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
776 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
777 "or{q}\t{$src, $dst|$dst, $src}",
778 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
781 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
782 "or{b}\t{$src, $dst|$dst, $src}",
783 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
785 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
786 "or{w}\t{$src, $dst|$dst, $src}",
787 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
790 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
791 "or{l}\t{$src, $dst|$dst, $src}",
792 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
794 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
795 "or{q}\t{$src, $dst|$dst, $src}",
796 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
799 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
800 "or{w}\t{$src, $dst|$dst, $src}",
801 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
804 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
805 "or{l}\t{$src, $dst|$dst, $src}",
806 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
808 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
809 "or{q}\t{$src, $dst|$dst, $src}",
810 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
813 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
814 "or{b}\t{$src, %al|%al, $src}", []>;
815 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
816 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
817 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
818 "or{l}\t{$src, %eax|%eax, $src}", []>;
819 def OR64i32 : RIi32<0x0D, RawFrm, (outs), (ins i64i32imm:$src),
820 "or{q}\t{$src, %rax|%rax, $src}", []>;
823 let Constraints = "$src1 = $dst" in {
825 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
826 def XOR8rr : I<0x30, MRMDestReg,
827 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
828 "xor{b}\t{$src2, $dst|$dst, $src2}",
829 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
831 def XOR16rr : I<0x31, MRMDestReg,
832 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
833 "xor{w}\t{$src2, $dst|$dst, $src2}",
834 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
835 GR16:$src2))]>, OpSize;
836 def XOR32rr : I<0x31, MRMDestReg,
837 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
838 "xor{l}\t{$src2, $dst|$dst, $src2}",
839 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
841 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst),
842 (ins GR64:$src1, GR64:$src2),
843 "xor{q}\t{$src2, $dst|$dst, $src2}",
844 [(set GR64:$dst, EFLAGS,
845 (X86xor_flag GR64:$src1, GR64:$src2))]>;
846 } // isCommutable = 1
848 // XOR instructions with the destination register in REG and the source register
849 // in R/M. Included for the disassembler.
850 let isCodeGenOnly = 1 in {
851 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
852 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
853 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
854 (ins GR16:$src1, GR16:$src2),
855 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
856 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
857 (ins GR32:$src1, GR32:$src2),
858 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
859 def XOR64rr_REV : RI<0x33, MRMSrcReg, (outs GR64:$dst),
860 (ins GR64:$src1, GR64:$src2),
861 "xor{q}\t{$src2, $dst|$dst, $src2}", []>;
864 def XOR8rm : I<0x32, MRMSrcMem,
865 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
866 "xor{b}\t{$src2, $dst|$dst, $src2}",
867 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
868 (load addr:$src2)))]>;
869 def XOR16rm : I<0x33, MRMSrcMem,
870 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
871 "xor{w}\t{$src2, $dst|$dst, $src2}",
872 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
873 (load addr:$src2)))]>,
875 def XOR32rm : I<0x33, MRMSrcMem,
876 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
877 "xor{l}\t{$src2, $dst|$dst, $src2}",
878 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
879 (load addr:$src2)))]>;
880 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst),
881 (ins GR64:$src1, i64mem:$src2),
882 "xor{q}\t{$src2, $dst|$dst, $src2}",
883 [(set GR64:$dst, EFLAGS,
884 (X86xor_flag GR64:$src1, (load addr:$src2)))]>;
886 def XOR8ri : Ii8<0x80, MRM6r,
887 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
888 "xor{b}\t{$src2, $dst|$dst, $src2}",
889 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
890 def XOR16ri : Ii16<0x81, MRM6r,
891 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
892 "xor{w}\t{$src2, $dst|$dst, $src2}",
893 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
894 imm:$src2))]>, OpSize;
895 def XOR32ri : Ii32<0x81, MRM6r,
896 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
897 "xor{l}\t{$src2, $dst|$dst, $src2}",
898 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
900 def XOR64ri32 : RIi32<0x81, MRM6r,
901 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
902 "xor{q}\t{$src2, $dst|$dst, $src2}",
903 [(set GR64:$dst, EFLAGS,
904 (X86xor_flag GR64:$src1, i64immSExt32:$src2))]>;
906 def XOR16ri8 : Ii8<0x83, MRM6r,
907 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
908 "xor{w}\t{$src2, $dst|$dst, $src2}",
909 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
910 i16immSExt8:$src2))]>,
912 def XOR32ri8 : Ii8<0x83, MRM6r,
913 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
914 "xor{l}\t{$src2, $dst|$dst, $src2}",
915 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
916 i32immSExt8:$src2))]>;
917 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst),
918 (ins GR64:$src1, i64i8imm:$src2),
919 "xor{q}\t{$src2, $dst|$dst, $src2}",
920 [(set GR64:$dst, EFLAGS,
921 (X86xor_flag GR64:$src1, i64immSExt8:$src2))]>;
922 } // Constraints = "$src1 = $dst"
925 def XOR8mr : I<0x30, MRMDestMem,
926 (outs), (ins i8mem :$dst, GR8 :$src),
927 "xor{b}\t{$src, $dst|$dst, $src}",
928 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
930 def XOR16mr : I<0x31, MRMDestMem,
931 (outs), (ins i16mem:$dst, GR16:$src),
932 "xor{w}\t{$src, $dst|$dst, $src}",
933 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
936 def XOR32mr : I<0x31, MRMDestMem,
937 (outs), (ins i32mem:$dst, GR32:$src),
938 "xor{l}\t{$src, $dst|$dst, $src}",
939 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
941 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
942 "xor{q}\t{$src, $dst|$dst, $src}",
943 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
946 def XOR8mi : Ii8<0x80, MRM6m,
947 (outs), (ins i8mem :$dst, i8imm :$src),
948 "xor{b}\t{$src, $dst|$dst, $src}",
949 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
951 def XOR16mi : Ii16<0x81, MRM6m,
952 (outs), (ins i16mem:$dst, i16imm:$src),
953 "xor{w}\t{$src, $dst|$dst, $src}",
954 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
957 def XOR32mi : Ii32<0x81, MRM6m,
958 (outs), (ins i32mem:$dst, i32imm:$src),
959 "xor{l}\t{$src, $dst|$dst, $src}",
960 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
962 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
963 "xor{q}\t{$src, $dst|$dst, $src}",
964 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
967 def XOR16mi8 : Ii8<0x83, MRM6m,
968 (outs), (ins i16mem:$dst, i16i8imm :$src),
969 "xor{w}\t{$src, $dst|$dst, $src}",
970 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
973 def XOR32mi8 : Ii8<0x83, MRM6m,
974 (outs), (ins i32mem:$dst, i32i8imm :$src),
975 "xor{l}\t{$src, $dst|$dst, $src}",
976 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
978 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
979 "xor{q}\t{$src, $dst|$dst, $src}",
980 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
983 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
984 "xor{b}\t{$src, %al|%al, $src}", []>;
985 def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
986 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
987 def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
988 "xor{l}\t{$src, %eax|%eax, $src}", []>;
989 def XOR64i32 : RIi32<0x35, RawFrm, (outs), (ins i64i32imm:$src),
990 "xor{q}\t{$src, %rax|%rax, $src}", []>;
995 let Defs = [EFLAGS] in {
996 let Constraints = "$src1 = $dst" in {
997 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
998 // Register-Register Addition
999 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
1000 (ins GR8 :$src1, GR8 :$src2),
1001 "add{b}\t{$src2, $dst|$dst, $src2}",
1002 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
1004 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1005 // Register-Register Addition
1006 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
1007 (ins GR16:$src1, GR16:$src2),
1008 "add{w}\t{$src2, $dst|$dst, $src2}",
1009 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
1010 GR16:$src2))]>, OpSize;
1011 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
1012 (ins GR32:$src1, GR32:$src2),
1013 "add{l}\t{$src2, $dst|$dst, $src2}",
1014 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
1016 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst),
1017 (ins GR64:$src1, GR64:$src2),
1018 "add{q}\t{$src2, $dst|$dst, $src2}",
1019 [(set GR64:$dst, EFLAGS,
1020 (X86add_flag GR64:$src1, GR64:$src2))]>;
1021 } // end isConvertibleToThreeAddress
1022 } // end isCommutable
1024 // These are alternate spellings for use by the disassembler, we mark them as
1025 // code gen only to ensure they aren't matched by the assembler.
1026 let isCodeGenOnly = 1 in {
1027 def ADD8rr_alt: I<0x02, MRMSrcReg,
1028 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1029 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
1030 def ADD16rr_alt: I<0x03, MRMSrcReg,
1031 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1032 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1033 def ADD32rr_alt: I<0x03, MRMSrcReg,
1034 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1035 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
1036 def ADD64rr_alt : RI<0x03, MRMSrcReg,
1037 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1038 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
1041 // Register-Memory Addition
1042 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
1043 (ins GR8 :$src1, i8mem :$src2),
1044 "add{b}\t{$src2, $dst|$dst, $src2}",
1045 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
1046 (load addr:$src2)))]>;
1047 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
1048 (ins GR16:$src1, i16mem:$src2),
1049 "add{w}\t{$src2, $dst|$dst, $src2}",
1050 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
1051 (load addr:$src2)))]>, OpSize;
1052 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
1053 (ins GR32:$src1, i32mem:$src2),
1054 "add{l}\t{$src2, $dst|$dst, $src2}",
1055 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
1056 (load addr:$src2)))]>;
1057 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst),
1058 (ins GR64:$src1, i64mem:$src2),
1059 "add{q}\t{$src2, $dst|$dst, $src2}",
1060 [(set GR64:$dst, EFLAGS,
1061 (X86add_flag GR64:$src1, (load addr:$src2)))]>;
1063 // Register-Integer Addition
1064 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1065 "add{b}\t{$src2, $dst|$dst, $src2}",
1066 [(set GR8:$dst, EFLAGS,
1067 (X86add_flag GR8:$src1, imm:$src2))]>;
1069 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1070 // Register-Integer Addition
1071 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
1072 (ins GR16:$src1, i16imm:$src2),
1073 "add{w}\t{$src2, $dst|$dst, $src2}",
1074 [(set GR16:$dst, EFLAGS,
1075 (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
1076 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
1077 (ins GR32:$src1, i32imm:$src2),
1078 "add{l}\t{$src2, $dst|$dst, $src2}",
1079 [(set GR32:$dst, EFLAGS,
1080 (X86add_flag GR32:$src1, imm:$src2))]>;
1081 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
1082 (ins GR16:$src1, i16i8imm:$src2),
1083 "add{w}\t{$src2, $dst|$dst, $src2}",
1084 [(set GR16:$dst, EFLAGS,
1085 (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1086 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
1087 (ins GR32:$src1, i32i8imm:$src2),
1088 "add{l}\t{$src2, $dst|$dst, $src2}",
1089 [(set GR32:$dst, EFLAGS,
1090 (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
1091 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst),
1092 (ins GR64:$src1, i64i8imm:$src2),
1093 "add{q}\t{$src2, $dst|$dst, $src2}",
1094 [(set GR64:$dst, EFLAGS,
1095 (X86add_flag GR64:$src1, i64immSExt8:$src2))]>;
1096 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst),
1097 (ins GR64:$src1, i64i32imm:$src2),
1098 "add{q}\t{$src2, $dst|$dst, $src2}",
1099 [(set GR64:$dst, EFLAGS,
1100 (X86add_flag GR64:$src1, i64immSExt32:$src2))]>;
1102 } // Constraints = "$src1 = $dst"
1104 // Memory-Register Addition
1105 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
1106 "add{b}\t{$src2, $dst|$dst, $src2}",
1107 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
1108 (implicit EFLAGS)]>;
1109 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1110 "add{w}\t{$src2, $dst|$dst, $src2}",
1111 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
1112 (implicit EFLAGS)]>, OpSize;
1113 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1114 "add{l}\t{$src2, $dst|$dst, $src2}",
1115 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
1116 (implicit EFLAGS)]>;
1117 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1118 "add{q}\t{$src2, $dst|$dst, $src2}",
1119 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
1120 (implicit EFLAGS)]>;
1121 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
1122 "add{b}\t{$src2, $dst|$dst, $src2}",
1123 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
1124 (implicit EFLAGS)]>;
1125 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
1126 "add{w}\t{$src2, $dst|$dst, $src2}",
1127 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
1128 (implicit EFLAGS)]>, OpSize;
1129 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
1130 "add{l}\t{$src2, $dst|$dst, $src2}",
1131 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
1132 (implicit EFLAGS)]>;
1133 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
1134 "add{q}\t{$src2, $dst|$dst, $src2}",
1135 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
1136 (implicit EFLAGS)]>;
1137 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1138 "add{w}\t{$src2, $dst|$dst, $src2}",
1139 [(store (add (load addr:$dst), i16immSExt8:$src2),
1141 (implicit EFLAGS)]>, OpSize;
1142 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1143 "add{l}\t{$src2, $dst|$dst, $src2}",
1144 [(store (add (load addr:$dst), i32immSExt8:$src2),
1146 (implicit EFLAGS)]>;
1147 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1148 "add{q}\t{$src2, $dst|$dst, $src2}",
1149 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
1150 (implicit EFLAGS)]>;
1153 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
1154 "add{b}\t{$src, %al|%al, $src}", []>;
1155 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
1156 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1157 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
1158 "add{l}\t{$src, %eax|%eax, $src}", []>;
1159 def ADD64i32 : RIi32<0x05, RawFrm, (outs), (ins i64i32imm:$src),
1160 "add{q}\t{$src, %rax|%rax, $src}", []>;
1162 let Uses = [EFLAGS] in {
1163 let Constraints = "$src1 = $dst" in {
1164 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1165 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1166 "adc{b}\t{$src2, $dst|$dst, $src2}",
1167 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
1168 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
1169 (ins GR16:$src1, GR16:$src2),
1170 "adc{w}\t{$src2, $dst|$dst, $src2}",
1171 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
1172 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
1173 (ins GR32:$src1, GR32:$src2),
1174 "adc{l}\t{$src2, $dst|$dst, $src2}",
1175 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
1176 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst),
1177 (ins GR64:$src1, GR64:$src2),
1178 "adc{q}\t{$src2, $dst|$dst, $src2}",
1179 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
1182 let isCodeGenOnly = 1 in {
1183 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1184 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
1185 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
1186 (ins GR16:$src1, GR16:$src2),
1187 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1188 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
1189 (ins GR32:$src1, GR32:$src2),
1190 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
1191 def ADC64rr_REV : RI<0x13, MRMSrcReg , (outs GR32:$dst),
1192 (ins GR64:$src1, GR64:$src2),
1193 "adc{q}\t{$src2, $dst|$dst, $src2}", []>;
1196 def ADC8rm : I<0x12, MRMSrcMem ,
1197 (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
1198 "adc{b}\t{$src2, $dst|$dst, $src2}",
1199 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
1200 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
1201 (ins GR16:$src1, i16mem:$src2),
1202 "adc{w}\t{$src2, $dst|$dst, $src2}",
1203 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
1205 def ADC32rm : I<0x13, MRMSrcMem ,
1206 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1207 "adc{l}\t{$src2, $dst|$dst, $src2}",
1208 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
1209 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst),
1210 (ins GR64:$src1, i64mem:$src2),
1211 "adc{q}\t{$src2, $dst|$dst, $src2}",
1212 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
1213 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1214 "adc{b}\t{$src2, $dst|$dst, $src2}",
1215 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
1216 def ADC16ri : Ii16<0x81, MRM2r,
1217 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1218 "adc{w}\t{$src2, $dst|$dst, $src2}",
1219 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
1220 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
1221 (ins GR16:$src1, i16i8imm:$src2),
1222 "adc{w}\t{$src2, $dst|$dst, $src2}",
1223 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
1225 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
1226 (ins GR32:$src1, i32imm:$src2),
1227 "adc{l}\t{$src2, $dst|$dst, $src2}",
1228 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
1229 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
1230 (ins GR32:$src1, i32i8imm:$src2),
1231 "adc{l}\t{$src2, $dst|$dst, $src2}",
1232 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
1233 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst),
1234 (ins GR64:$src1, i64i32imm:$src2),
1235 "adc{q}\t{$src2, $dst|$dst, $src2}",
1236 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
1237 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst),
1238 (ins GR64:$src1, i64i8imm:$src2),
1239 "adc{q}\t{$src2, $dst|$dst, $src2}",
1240 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
1241 } // Constraints = "$src1 = $dst"
1243 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
1244 "adc{b}\t{$src2, $dst|$dst, $src2}",
1245 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
1246 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1247 "adc{w}\t{$src2, $dst|$dst, $src2}",
1248 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
1250 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1251 "adc{l}\t{$src2, $dst|$dst, $src2}",
1252 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
1253 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1254 "adc{q}\t{$src2, $dst|$dst, $src2}",
1255 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
1256 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
1257 "adc{b}\t{$src2, $dst|$dst, $src2}",
1258 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1259 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
1260 "adc{w}\t{$src2, $dst|$dst, $src2}",
1261 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1263 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1264 "adc{w}\t{$src2, $dst|$dst, $src2}",
1265 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1267 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
1268 "adc{l}\t{$src2, $dst|$dst, $src2}",
1269 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1270 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1271 "adc{l}\t{$src2, $dst|$dst, $src2}",
1272 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1274 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
1275 "adc{q}\t{$src2, $dst|$dst, $src2}",
1276 [(store (adde (load addr:$dst), i64immSExt32:$src2),
1278 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1279 "adc{q}\t{$src2, $dst|$dst, $src2}",
1280 [(store (adde (load addr:$dst), i64immSExt8:$src2),
1283 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
1284 "adc{b}\t{$src, %al|%al, $src}", []>;
1285 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
1286 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1287 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
1288 "adc{l}\t{$src, %eax|%eax, $src}", []>;
1289 def ADC64i32 : RIi32<0x15, RawFrm, (outs), (ins i64i32imm:$src),
1290 "adc{q}\t{$src, %rax|%rax, $src}", []>;
1291 } // Uses = [EFLAGS]
1293 let Constraints = "$src1 = $dst" in {
1295 // Register-Register Subtraction
1296 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1297 "sub{b}\t{$src2, $dst|$dst, $src2}",
1298 [(set GR8:$dst, EFLAGS,
1299 (X86sub_flag GR8:$src1, GR8:$src2))]>;
1300 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
1301 "sub{w}\t{$src2, $dst|$dst, $src2}",
1302 [(set GR16:$dst, EFLAGS,
1303 (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
1304 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
1305 "sub{l}\t{$src2, $dst|$dst, $src2}",
1306 [(set GR32:$dst, EFLAGS,
1307 (X86sub_flag GR32:$src1, GR32:$src2))]>;
1308 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst),
1309 (ins GR64:$src1, GR64:$src2),
1310 "sub{q}\t{$src2, $dst|$dst, $src2}",
1311 [(set GR64:$dst, EFLAGS,
1312 (X86sub_flag GR64:$src1, GR64:$src2))]>;
1314 let isCodeGenOnly = 1 in {
1315 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1316 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
1317 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
1318 (ins GR16:$src1, GR16:$src2),
1319 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1320 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
1321 (ins GR32:$src1, GR32:$src2),
1322 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
1323 def SUB64rr_REV : RI<0x2B, MRMSrcReg, (outs GR64:$dst),
1324 (ins GR64:$src1, GR64:$src2),
1325 "sub{q}\t{$src2, $dst|$dst, $src2}", []>;
1328 // Register-Memory Subtraction
1329 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
1330 (ins GR8 :$src1, i8mem :$src2),
1331 "sub{b}\t{$src2, $dst|$dst, $src2}",
1332 [(set GR8:$dst, EFLAGS,
1333 (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
1334 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
1335 (ins GR16:$src1, i16mem:$src2),
1336 "sub{w}\t{$src2, $dst|$dst, $src2}",
1337 [(set GR16:$dst, EFLAGS,
1338 (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
1339 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
1340 (ins GR32:$src1, i32mem:$src2),
1341 "sub{l}\t{$src2, $dst|$dst, $src2}",
1342 [(set GR32:$dst, EFLAGS,
1343 (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
1344 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst),
1345 (ins GR64:$src1, i64mem:$src2),
1346 "sub{q}\t{$src2, $dst|$dst, $src2}",
1347 [(set GR64:$dst, EFLAGS,
1348 (X86sub_flag GR64:$src1, (load addr:$src2)))]>;
1350 // Register-Integer Subtraction
1351 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
1352 (ins GR8:$src1, i8imm:$src2),
1353 "sub{b}\t{$src2, $dst|$dst, $src2}",
1354 [(set GR8:$dst, EFLAGS,
1355 (X86sub_flag GR8:$src1, imm:$src2))]>;
1356 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
1357 (ins GR16:$src1, i16imm:$src2),
1358 "sub{w}\t{$src2, $dst|$dst, $src2}",
1359 [(set GR16:$dst, EFLAGS,
1360 (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
1361 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
1362 (ins GR32:$src1, i32imm:$src2),
1363 "sub{l}\t{$src2, $dst|$dst, $src2}",
1364 [(set GR32:$dst, EFLAGS,
1365 (X86sub_flag GR32:$src1, imm:$src2))]>;
1366 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
1367 (ins GR64:$src1, i64i32imm:$src2),
1368 "sub{q}\t{$src2, $dst|$dst, $src2}",
1369 [(set GR64:$dst, EFLAGS,
1370 (X86sub_flag GR64:$src1, i64immSExt32:$src2))]>;
1371 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
1372 (ins GR16:$src1, i16i8imm:$src2),
1373 "sub{w}\t{$src2, $dst|$dst, $src2}",
1374 [(set GR16:$dst, EFLAGS,
1375 (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1376 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
1377 (ins GR32:$src1, i32i8imm:$src2),
1378 "sub{l}\t{$src2, $dst|$dst, $src2}",
1379 [(set GR32:$dst, EFLAGS,
1380 (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
1381 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
1382 (ins GR64:$src1, i64i8imm:$src2),
1383 "sub{q}\t{$src2, $dst|$dst, $src2}",
1384 [(set GR64:$dst, EFLAGS,
1385 (X86sub_flag GR64:$src1, i64immSExt8:$src2))]>;
1386 } // Constraints = "$src1 = $dst"
1388 // Memory-Register Subtraction
1389 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1390 "sub{b}\t{$src2, $dst|$dst, $src2}",
1391 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
1392 (implicit EFLAGS)]>;
1393 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1394 "sub{w}\t{$src2, $dst|$dst, $src2}",
1395 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
1396 (implicit EFLAGS)]>, OpSize;
1397 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1398 "sub{l}\t{$src2, $dst|$dst, $src2}",
1399 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
1400 (implicit EFLAGS)]>;
1401 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1402 "sub{q}\t{$src2, $dst|$dst, $src2}",
1403 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
1404 (implicit EFLAGS)]>;
1406 // Memory-Integer Subtraction
1407 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
1408 "sub{b}\t{$src2, $dst|$dst, $src2}",
1409 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
1410 (implicit EFLAGS)]>;
1411 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
1412 "sub{w}\t{$src2, $dst|$dst, $src2}",
1413 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
1414 (implicit EFLAGS)]>, OpSize;
1415 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
1416 "sub{l}\t{$src2, $dst|$dst, $src2}",
1417 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
1418 (implicit EFLAGS)]>;
1419 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
1420 "sub{q}\t{$src2, $dst|$dst, $src2}",
1421 [(store (sub (load addr:$dst), i64immSExt32:$src2),
1423 (implicit EFLAGS)]>;
1424 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1425 "sub{w}\t{$src2, $dst|$dst, $src2}",
1426 [(store (sub (load addr:$dst), i16immSExt8:$src2),
1428 (implicit EFLAGS)]>, OpSize;
1429 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1430 "sub{l}\t{$src2, $dst|$dst, $src2}",
1431 [(store (sub (load addr:$dst), i32immSExt8:$src2),
1433 (implicit EFLAGS)]>;
1434 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1435 "sub{q}\t{$src2, $dst|$dst, $src2}",
1436 [(store (sub (load addr:$dst), i64immSExt8:$src2),
1438 (implicit EFLAGS)]>;
1440 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
1441 "sub{b}\t{$src, %al|%al, $src}", []>;
1442 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
1443 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1444 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
1445 "sub{l}\t{$src, %eax|%eax, $src}", []>;
1446 def SUB64i32 : RIi32<0x2D, RawFrm, (outs), (ins i64i32imm:$src),
1447 "sub{q}\t{$src, %rax|%rax, $src}", []>;
1449 let Uses = [EFLAGS] in {
1450 let Constraints = "$src1 = $dst" in {
1451 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
1452 (ins GR8:$src1, GR8:$src2),
1453 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1454 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
1455 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
1456 (ins GR16:$src1, GR16:$src2),
1457 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1458 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
1459 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
1460 (ins GR32:$src1, GR32:$src2),
1461 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1462 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
1463 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst),
1464 (ins GR64:$src1, GR64:$src2),
1465 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1466 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
1467 } // Constraints = "$src1 = $dst"
1470 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
1471 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1472 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
1473 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1474 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1475 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
1477 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1478 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1479 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
1480 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1481 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1482 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
1484 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
1485 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1486 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1487 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
1488 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1489 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1491 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1492 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1493 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1495 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
1496 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1497 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1498 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1499 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1500 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1501 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
1502 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1503 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
1504 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1505 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1506 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
1508 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
1509 "sbb{b}\t{$src, %al|%al, $src}", []>;
1510 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
1511 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1512 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
1513 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
1514 def SBB64i32 : RIi32<0x1D, RawFrm, (outs), (ins i64i32imm:$src),
1515 "sbb{q}\t{$src, %rax|%rax, $src}", []>;
1517 let Constraints = "$src1 = $dst" in {
1519 let isCodeGenOnly = 1 in {
1520 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1521 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
1522 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
1523 (ins GR16:$src1, GR16:$src2),
1524 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1525 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
1526 (ins GR32:$src1, GR32:$src2),
1527 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
1528 def SBB64rr_REV : RI<0x1B, MRMSrcReg, (outs GR64:$dst),
1529 (ins GR64:$src1, GR64:$src2),
1530 "sbb{q}\t{$src2, $dst|$dst, $src2}", []>;
1533 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
1534 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1535 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
1536 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
1537 (ins GR16:$src1, i16mem:$src2),
1538 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1539 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
1541 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
1542 (ins GR32:$src1, i32mem:$src2),
1543 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1544 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
1545 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst),
1546 (ins GR64:$src1, i64mem:$src2),
1547 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1548 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
1549 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1550 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1551 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
1552 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
1553 (ins GR16:$src1, i16imm:$src2),
1554 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1555 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
1556 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
1557 (ins GR16:$src1, i16i8imm:$src2),
1558 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1559 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
1561 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
1562 (ins GR32:$src1, i32imm:$src2),
1563 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1564 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
1565 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
1566 (ins GR32:$src1, i32i8imm:$src2),
1567 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1568 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
1569 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst),
1570 (ins GR64:$src1, i64i32imm:$src2),
1571 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1572 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
1573 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst),
1574 (ins GR64:$src1, i64i8imm:$src2),
1575 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1576 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
1578 } // Constraints = "$src1 = $dst"
1579 } // Uses = [EFLAGS]
1580 } // Defs = [EFLAGS]
1582 //===----------------------------------------------------------------------===//
1583 // Test instructions are just like AND, except they don't generate a result.
1585 let Defs = [EFLAGS] in {
1586 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
1587 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
1588 "test{b}\t{$src2, $src1|$src1, $src2}",
1589 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
1590 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
1591 "test{w}\t{$src2, $src1|$src1, $src2}",
1592 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
1595 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
1596 "test{l}\t{$src2, $src1|$src1, $src2}",
1597 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
1599 def TEST64rr : RI<0x85, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1600 "test{q}\t{$src2, $src1|$src1, $src2}",
1601 [(set EFLAGS, (X86cmp (and GR64:$src1, GR64:$src2), 0))]>;
1604 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
1605 "test{b}\t{$src2, $src1|$src1, $src2}",
1606 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
1608 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
1609 "test{w}\t{$src2, $src1|$src1, $src2}",
1610 [(set EFLAGS, (X86cmp (and GR16:$src1,
1611 (loadi16 addr:$src2)), 0))]>, OpSize;
1612 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
1613 "test{l}\t{$src2, $src1|$src1, $src2}",
1614 [(set EFLAGS, (X86cmp (and GR32:$src1,
1615 (loadi32 addr:$src2)), 0))]>;
1616 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1617 "test{q}\t{$src2, $src1|$src1, $src2}",
1618 [(set EFLAGS, (X86cmp (and GR64:$src1, (loadi64 addr:$src2)),
1621 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
1622 (outs), (ins GR8:$src1, i8imm:$src2),
1623 "test{b}\t{$src2, $src1|$src1, $src2}",
1624 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
1625 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
1626 (outs), (ins GR16:$src1, i16imm:$src2),
1627 "test{w}\t{$src2, $src1|$src1, $src2}",
1628 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
1630 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
1631 (outs), (ins GR32:$src1, i32imm:$src2),
1632 "test{l}\t{$src2, $src1|$src1, $src2}",
1633 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
1634 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1635 (ins GR64:$src1, i64i32imm:$src2),
1636 "test{q}\t{$src2, $src1|$src1, $src2}",
1637 [(set EFLAGS, (X86cmp (and GR64:$src1, i64immSExt32:$src2),
1640 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
1641 (outs), (ins i8mem:$src1, i8imm:$src2),
1642 "test{b}\t{$src2, $src1|$src1, $src2}",
1643 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
1645 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
1646 (outs), (ins i16mem:$src1, i16imm:$src2),
1647 "test{w}\t{$src2, $src1|$src1, $src2}",
1648 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
1650 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
1651 (outs), (ins i32mem:$src1, i32imm:$src2),
1652 "test{l}\t{$src2, $src1|$src1, $src2}",
1653 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
1655 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1656 (ins i64mem:$src1, i64i32imm:$src2),
1657 "test{q}\t{$src2, $src1|$src1, $src2}",
1658 [(set EFLAGS, (X86cmp (and (loadi64 addr:$src1),
1659 i64immSExt32:$src2), 0))]>;
1661 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
1662 "test{b}\t{$src, %al|%al, $src}", []>;
1663 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
1664 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1665 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
1666 "test{l}\t{$src, %eax|%eax, $src}", []>;
1667 def TEST64i32 : RIi32<0xa9, RawFrm, (outs), (ins i64i32imm:$src),
1668 "test{q}\t{$src, %rax|%rax, $src}", []>;
1670 } // Defs = [EFLAGS]
1673 //===----------------------------------------------------------------------===//
1674 // Integer comparisons
1676 let Defs = [EFLAGS] in {
1678 def CMP8rr : I<0x38, MRMDestReg,
1679 (outs), (ins GR8 :$src1, GR8 :$src2),
1680 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1681 [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
1682 def CMP16rr : I<0x39, MRMDestReg,
1683 (outs), (ins GR16:$src1, GR16:$src2),
1684 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1685 [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
1686 def CMP32rr : I<0x39, MRMDestReg,
1687 (outs), (ins GR32:$src1, GR32:$src2),
1688 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1689 [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
1690 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1691 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1692 [(set EFLAGS, (X86cmp GR64:$src1, GR64:$src2))]>;
1694 def CMP8mr : I<0x38, MRMDestMem,
1695 (outs), (ins i8mem :$src1, GR8 :$src2),
1696 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1697 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
1698 def CMP16mr : I<0x39, MRMDestMem,
1699 (outs), (ins i16mem:$src1, GR16:$src2),
1700 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1701 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
1703 def CMP32mr : I<0x39, MRMDestMem,
1704 (outs), (ins i32mem:$src1, GR32:$src2),
1705 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1706 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
1707 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1708 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1709 [(set EFLAGS, (X86cmp (loadi64 addr:$src1), GR64:$src2))]>;
1711 def CMP8rm : I<0x3A, MRMSrcMem,
1712 (outs), (ins GR8 :$src1, i8mem :$src2),
1713 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1714 [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
1715 def CMP16rm : I<0x3B, MRMSrcMem,
1716 (outs), (ins GR16:$src1, i16mem:$src2),
1717 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1718 [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
1720 def CMP32rm : I<0x3B, MRMSrcMem,
1721 (outs), (ins GR32:$src1, i32mem:$src2),
1722 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1723 [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
1724 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1725 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1726 [(set EFLAGS, (X86cmp GR64:$src1, (loadi64 addr:$src2)))]>;
1728 // These are alternate spellings for use by the disassembler, we mark them as
1729 // code gen only to ensure they aren't matched by the assembler.
1730 let isCodeGenOnly = 1 in {
1731 def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
1732 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
1733 def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
1734 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
1735 def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
1736 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
1737 def CMP64rr_alt : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1738 "cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
1741 def CMP8ri : Ii8<0x80, MRM7r,
1742 (outs), (ins GR8:$src1, i8imm:$src2),
1743 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1744 [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
1745 def CMP16ri : Ii16<0x81, MRM7r,
1746 (outs), (ins GR16:$src1, i16imm:$src2),
1747 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1748 [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
1749 def CMP32ri : Ii32<0x81, MRM7r,
1750 (outs), (ins GR32:$src1, i32imm:$src2),
1751 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1752 [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
1753 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1754 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1755 [(set EFLAGS, (X86cmp GR64:$src1, i64immSExt32:$src2))]>;
1757 def CMP8mi : Ii8 <0x80, MRM7m,
1758 (outs), (ins i8mem :$src1, i8imm :$src2),
1759 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1760 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
1761 def CMP16mi : Ii16<0x81, MRM7m,
1762 (outs), (ins i16mem:$src1, i16imm:$src2),
1763 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1764 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
1766 def CMP32mi : Ii32<0x81, MRM7m,
1767 (outs), (ins i32mem:$src1, i32imm:$src2),
1768 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1769 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
1770 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1771 (ins i64mem:$src1, i64i32imm:$src2),
1772 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1773 [(set EFLAGS, (X86cmp (loadi64 addr:$src1),
1774 i64immSExt32:$src2))]>;
1776 def CMP16ri8 : Ii8<0x83, MRM7r,
1777 (outs), (ins GR16:$src1, i16i8imm:$src2),
1778 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1779 [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
1781 def CMP32ri8 : Ii8<0x83, MRM7r,
1782 (outs), (ins GR32:$src1, i32i8imm:$src2),
1783 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1784 [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
1785 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1786 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1787 [(set EFLAGS, (X86cmp GR64:$src1, i64immSExt8:$src2))]>;
1789 def CMP16mi8 : Ii8<0x83, MRM7m,
1790 (outs), (ins i16mem:$src1, i16i8imm:$src2),
1791 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1792 [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
1793 i16immSExt8:$src2))]>, OpSize;
1794 def CMP32mi8 : Ii8<0x83, MRM7m,
1795 (outs), (ins i32mem:$src1, i32i8imm:$src2),
1796 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1797 [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
1798 i32immSExt8:$src2))]>;
1799 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1800 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1801 [(set EFLAGS, (X86cmp (loadi64 addr:$src1),
1802 i64immSExt8:$src2))]>;
1804 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
1805 "cmp{b}\t{$src, %al|%al, $src}", []>;
1806 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
1807 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1808 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
1809 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
1810 def CMP64i32 : RIi32<0x3D, RawFrm, (outs), (ins i64i32imm:$src),
1811 "cmp{q}\t{$src, %rax|%rax, $src}", []>;
1813 } // Defs = [EFLAGS]